From c1e60f95bc9b5cbba0b93deef65d616e43ed5698 Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Thu, 24 Aug 2023 15:31:46 +0200
Subject: [PATCH] RTSD-161: indent on all files
---
.../lofar1/RSP/pfb2/src/vhdl/pfb2.vhd | 92 +-
.../lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd | 104 +-
.../lofar1/RSP/pfs/src/vhdl/pfs(str).vhd | 178 +-
applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd | 182 +-
.../RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd | 39 +-
.../pfs/src/vhdl/pfs_coefsbuf(stratix).vhd | 46 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd | 37 +-
.../RSP/pfs/src/vhdl/pfs_combine(rtl).vhd | 6 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd | 2 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd | 6 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd | 6 +-
.../RSP/pfs/src/vhdl/pfs_filter(rtl).vhd | 38 +-
.../RSP/pfs/src/vhdl/pfs_filter(stratix).vhd | 148 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd | 38 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd | 232 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd | 10 +-
.../src/vhdl/pfs_fir_coefsbuf(stratix).vhd | 38 +-
.../RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd | 4 +-
.../RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd | 14 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd | 2 +-
.../RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd | 80 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd | 4 +-
.../pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd | 62 +-
.../RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd | 4 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd | 4 +-
.../RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd | 6 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd | 4 +-
.../RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd | 38 +-
.../RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd | 60 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd | 6 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd | 42 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_top.vhd | 2 +-
.../lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd | 48 +-
.../lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd | 4 +-
.../lofar1/RSP/pft2/src/vhdl/pft(str).vhd | 170 +-
applications/lofar1/RSP/pft2/src/vhdl/pft.vhd | 170 +-
.../lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd | 218 +-
.../lofar1/RSP/pft2/src/vhdl/pft_bf.vhd | 216 +-
.../RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd | 148 +-
.../lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd | 146 +-
.../RSP/pft2/src/vhdl/pft_buffer(rtl).vhd | 81 +-
.../lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd | 79 +-
.../RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd | 2 +-
.../lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd | 2 +-
.../lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd | 4 +-
.../RSP/pft2/src/vhdl/pft_reverse(rtl).vhd | 4 +-
.../lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd | 4 +-
.../RSP/pft2/src/vhdl/pft_separate(rtl).vhd | 132 +-
.../lofar1/RSP/pft2/src/vhdl/pft_separate.vhd | 126 +-
.../RSP/pft2/src/vhdl/pft_stage(str).vhd | 214 +-
.../lofar1/RSP/pft2/src/vhdl/pft_stage.vhd | 216 +-
.../RSP/pft2/src/vhdl/pft_switch(rtl).vhd | 38 +-
.../lofar1/RSP/pft2/src/vhdl/pft_switch.vhd | 36 +-
.../RSP/pft2/src/vhdl/pft_tmult(rtl).vhd | 217 +-
.../lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd | 219 +-
.../lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd | 42 +-
.../lofar1/RSP/pft2/src/vhdl/pft_top.vhd | 6 +-
.../RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd | 44 +-
.../lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd | 42 +-
.../lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd | 164 +-
.../lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd | 414 +-
.../lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd | 160 +-
.../lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd | 2 +-
.../lofar2_unb2b_adc_6ch_200MHz.vhd | 112 +-
.../tb_lofar2_unb2b_adc_6ch_200MHz.vhd | 94 +-
.../lofar2_unb2b_adc_full.vhd | 110 +-
.../tb_lofar2_unb2b_adc_full.vhd | 94 +-
.../lofar2_unb2b_adc_one_node.vhd | 108 +-
.../tb_lofar2_unb2b_adc_one_node.vhd | 94 +-
.../src/vhdl/lofar2_unb2b_adc.vhd | 556 +-
.../src/vhdl/lofar2_unb2b_adc_pkg.vhd | 8 +-
.../src/vhdl/mmm_lofar2_unb2b_adc.vhd | 142 +-
.../src/vhdl/node_adc_input_and_timing.vhd | 437 +-
.../src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd | 418 +-
.../tb/vhdl/tb_lofar2_unb2b_adc.vhd | 98 +-
.../vhdl/tb_lofar2_unb2b_adc_multichannel.vhd | 350 +-
.../lofar2_unb2b_beamformer_one_node.vhd | 124 +-
...ofar2_unb2b_beamformer_one_node_256MHz.vhd | 124 +-
.../src/vhdl/lofar2_unb2b_beamformer.vhd | 948 +--
.../src/vhdl/lofar2_unb2b_beamformer_pkg.vhd | 10 +-
.../src/vhdl/mmm_lofar2_unb2b_beamformer.vhd | 327 +-
.../vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd | 642 +-
.../lofar2_unb2b_filterbank_full.vhd | 110 +-
.../lofar2_unb2b_filterbank_full_256MHz.vhd | 110 +-
.../src/vhdl/lofar2_unb2b_filterbank.vhd | 710 +-
.../src/vhdl/lofar2_unb2b_filterbank_pkg.vhd | 10 +-
.../src/vhdl/mmm_lofar2_unb2b_filterbank.vhd | 215 +-
.../vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd | 572 +-
.../lofar2_unb2b_ring_full.vhd | 118 +-
.../tb_lofar2_unb2b_ring_full.vhd | 106 +-
.../lofar2_unb2b_ring_one.vhd | 118 +-
.../tb_lofar2_unb2b_ring_one.vhd | 106 +-
.../src/vhdl/lofar2_unb2b_ring.vhd | 1023 +--
.../src/vhdl/lofar2_unb2b_ring_pkg.vhd | 10 +-
.../src/vhdl/mmc_lofar2_unb2b_ring.vhd | 154 +-
.../src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd | 432 +-
.../tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd | 20 +-
.../disturb2_unb2b_sdp_station_full.vhd | 142 +-
.../disturb2_unb2b_sdp_station_full_wg.vhd | 132 +-
.../lofar2_unb2b_sdp_station_adc.vhd | 110 +-
.../lofar2_unb2b_sdp_station_bf.vhd | 124 +-
.../lofar2_unb2b_sdp_station_fsub.vhd | 110 +-
.../lofar2_unb2b_sdp_station_full.vhd | 142 +-
.../lofar2_unb2b_sdp_station_full_wg.vhd | 124 +-
.../lofar2_unb2b_sdp_station_xsub_one.vhd | 110 +-
.../lofar2_unb2b_sdp_station_xsub_ring.vhd | 142 +-
.../src/vhdl/lofar2_unb2b_sdp_station.vhd | 1084 +--
.../src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd | 10 +-
.../src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd | 796 +-
.../qsys_lofar2_unb2b_sdp_station_pkg.vhd | 1104 +--
.../src/vhdl/lofar2_unb2c_ddrctrl.vhd | 900 +--
.../src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd | 127 +-
.../vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd | 368 +-
.../lofar2_unb2c_filterbank_full.vhd | 110 +-
.../lofar2_unb2c_filterbank_full_256MHz.vhd | 110 +-
.../src/vhdl/lofar2_unb2c_filterbank.vhd | 598 +-
.../src/vhdl/lofar2_unb2c_filterbank_pkg.vhd | 10 +-
.../src/vhdl/mmm_lofar2_unb2c_filterbank.vhd | 210 +-
.../vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd | 516 +-
.../lofar2_unb2c_ring_full.vhd | 102 +-
.../tb_lofar2_unb2c_ring_full.vhd | 90 +-
.../lofar2_unb2c_ring_one.vhd | 102 +-
.../tb_lofar2_unb2c_ring_one.vhd | 90 +-
.../src/vhdl/lofar2_unb2c_ring.vhd | 987 +--
.../src/vhdl/lofar2_unb2c_ring_pkg.vhd | 10 +-
.../src/vhdl/mmc_lofar2_unb2c_ring.vhd | 144 +-
.../src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd | 404 +-
.../tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd | 20 +-
.../disturb2_unb2c_sdp_station_full.vhd | 126 +-
.../disturb2_unb2c_sdp_station_full_wg.vhd | 108 +-
.../lofar2_unb2c_sdp_station_adc.vhd | 84 +-
.../lofar2_unb2c_sdp_station_bf.vhd | 108 +-
.../tb_tb_lofar2_unb2c_sdp_station_bf.vhd | 44 +-
.../lofar2_unb2c_sdp_station_bf_ring.vhd | 126 +-
.../lofar2_unb2c_sdp_station_fsub.vhd | 84 +-
.../tb_tb_lofar2_unb2c_sdp_station_fsub.vhd | 60 +-
.../lofar2_unb2c_sdp_station_full.vhd | 126 +-
.../lofar2_unb2c_sdp_station_full_wg.vhd | 108 +-
.../lofar2_unb2c_sdp_station_xsub_one.vhd | 84 +-
.../lofar2_unb2c_sdp_station_xsub_ring.vhd | 126 +-
.../src/vhdl/lofar2_unb2c_sdp_station.vhd | 1046 +--
.../src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd | 10 +-
.../src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd | 786 +-
.../qsys_lofar2_unb2c_sdp_station_pkg.vhd | 1076 +--
.../src/vhdl/Prototype_ddrctrl_controller.vhd | 492 +-
.../libraries/ddrctrl/src/vhdl/ddrctrl.vhd | 310 +-
.../ddrctrl/src/vhdl/ddrctrl_controller.vhd | 574 +-
.../ddrctrl/src/vhdl/ddrctrl_input.vhd | 88 +-
.../vhdl/ddrctrl_input_address_counter.vhd | 72 +-
.../ddrctrl/src/vhdl/ddrctrl_input_pack.vhd | 4 +-
.../ddrctrl/src/vhdl/ddrctrl_input_repack.vhd | 148 +-
.../ddrctrl/src/vhdl/ddrctrl_output.vhd | 130 +-
.../src/vhdl/ddrctrl_output_repack.vhd | 6 +-
.../src/vhdl/ddrctrl_output_unpack.vhd | 186 +-
.../libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd | 74 +-
.../vhdl/node_sdp_adc_input_and_timing.vhd | 472 +-
.../sdp/src/vhdl/node_sdp_beamformer.vhd | 350 +-
.../sdp/src/vhdl/node_sdp_correlator.vhd | 542 +-
.../sdp/src/vhdl/node_sdp_filterbank.vhd | 288 +-
.../vhdl/node_sdp_oversampled_filterbank.vhd | 688 +-
.../sdp/src/vhdl/sdp_beamformer_local.vhd | 156 +-
.../sdp/src/vhdl/sdp_beamformer_output.vhd | 299 +-
.../sdp/src/vhdl/sdp_beamformer_remote.vhd | 182 +-
.../libraries/sdp/src/vhdl/sdp_bf_weights.vhd | 58 +-
.../src/vhdl/sdp_crosslets_subband_select.vhd | 254 +-
.../libraries/sdp/src/vhdl/sdp_info.vhd | 32 +-
.../libraries/sdp/src/vhdl/sdp_info_reg.vhd | 61 +-
.../lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd | 317 +-
.../libraries/sdp/src/vhdl/sdp_scope.vhd | 54 +-
.../libraries/sdp/src/vhdl/sdp_station.vhd | 1294 +--
.../sdp/src/vhdl/sdp_statistics_offload.vhd | 220 +-
.../sdp/src/vhdl/sdp_subband_equalizer.vhd | 208 +-
.../sdp/src/vhdl/sdp_subband_weights.vhd | 118 +-
.../vhdl/tb_sdp_crosslets_subband_select.vhd | 66 +-
.../libraries/sdp/tb/vhdl/tb_sdp_info.vhd | 12 +-
.../libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd | 180 +-
.../sdp/tb/vhdl/tb_sdp_statistics_offload.vhd | 266 +-
.../tb/vhdl/tb_tb_sdp_statistics_offload.vhd | 34 +-
.../src/vhdl/rdma_demo_eth_tester_wrapper.vhd | 182 +-
.../rdma_demo/src/vhdl/rdma_demo_pkg.vhd | 94 +-
.../vhdl/rdma_demo_roce_tester_wrapper.vhd | 188 +-
.../lofar2_unb2b_ring_bsp/ring_pkg.vhd | 6 +-
.../hardware/lofar2_unb2b_ring_bsp/top.vhd | 1484 ++--
.../top_components_pkg.vhd | 410 +-
.../ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd | 908 +--
.../ta2_unb2b_bsp/top_components_pkg.vhd | 384 +-
.../ta2_channel_cross/ta2_channel_cross.vhd | 162 +-
.../ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd | 294 +-
.../ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd | 94 +-
.../ta2_unb2b_1GbE_ip_wrapper.vhd | 124 +-
.../ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd | 620 +-
.../ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd | 446 +-
.../ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd | 132 +-
.../ta2_unb2b_jesd204b_ip_wrapper.vhd | 40 +-
.../ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd | 120 +-
.../ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd | 62 +-
.../src/vhdl/node_unb1_bn_capture.vhd | 376 +-
.../src/vhdl/unb1_bn_capture.vhd | 1080 +--
.../src/vhdl/unb1_bn_capture_input.vhd | 356 +-
.../src/vhdl/unb1_bn_capture_mux.vhd | 104 +-
.../src/vhdl/unb1_bn_capture_pkg.vhd | 15 +-
.../src/vhdl/unb1_bn_capture_storage.vhd | 194 +-
.../src/vhdl/unb1_bn_capture_storage_reg.vhd | 115 +-
.../tb/vhdl/tb_unb1_bn_capture.vhd | 233 +-
.../tb/vhdl/tb_unb1_bn_capture_input.vhd | 187 +-
.../src/vhdl/node_unb1_bn_terminal_bg.vhd | 270 +-
.../src/vhdl/unb1_bn_terminal_bg.vhd | 680 +-
.../tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd | 220 +-
.../vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd | 66 +-
.../unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd | 380 +-
.../unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd | 164 +-
.../designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd | 512 +-
.../unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd | 116 +-
.../tb_unb1_ddr3_reorder_dual_rank.vhd | 26 +-
.../unb1_ddr3_reorder_dual_rank.vhd | 72 +-
.../tb_unb1_ddr3_reorder_single_rank.vhd | 26 +-
.../unb1_ddr3_reorder_single_rank.vhd | 72 +-
.../src/vhdl/mmm_unb1_ddr3_reorder.vhd | 444 +-
.../src/vhdl/node_unb1_ddr3_reorder.vhd | 386 +-
.../src/vhdl/unb1_ddr3_reorder.vhd | 543 +-
.../tb/vhdl/tb_unb1_ddr3_reorder.vhd | 114 +-
.../src/vhdl/mmm_unb1_ddr3_transpose.vhd | 423 +-
.../src/vhdl/unb1_ddr3_transpose.vhd | 633 +-
.../tb/vhdl/tb_unb1_ddr3_transpose.vhd | 86 +-
.../src/vhdl/mmm_unb1_fn_terminal_db.vhd | 363 +-
.../src/vhdl/node_unb1_fn_terminal_db.vhd | 266 +-
.../src/vhdl/unb1_fn_terminal_db.vhd | 436 +-
.../tb/vhdl/tb_unb1_fn_terminal_db.vhd | 284 +-
.../unb1_heater/src/vhdl/mmm_unb1_heater.vhd | 67 +-
.../src/vhdl/qsys_unb1_heater_pkg.vhd | 242 +-
.../unb1_heater/src/vhdl/unb1_heater.vhd | 394 +-
.../unb1_heater/tb/vhdl/tb_unb1_heater.vhd | 74 +-
.../tb_unb1_minimal_mm_arbiter.vhd | 10 +-
.../unb1_minimal_mm_arbiter.vhd | 62 +-
.../tb_unb1_minimal_qsys.vhd | 10 +-
.../unb1_minimal_qsys/unb1_minimal_qsys.vhd | 62 +-
.../mmm_unb1_minimal_qsys_wo_pll.vhd | 80 +-
.../qsys_wo_pll_unb1_minimal_pkg.vhd | 214 +-
.../tb_unb1_minimal_qsys_wo_pll.vhd | 74 +-
.../unb1_minimal_qsys_wo_pll.vhd | 360 +-
.../tb_unb1_minimal_sopc.vhd | 10 +-
.../unb1_minimal_sopc/unb1_minimal_sopc.vhd | 60 +-
.../src/vhdl/mmm_unb1_minimal.vhd | 364 +-
.../src/vhdl/qsys_unb1_minimal_pkg.vhd | 322 +-
.../unb1_minimal/src/vhdl/unb1_minimal.vhd | 360 +-
.../unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd | 74 +-
.../src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd | 116 +-
.../vhdl/node_unb1_terminal_bg_mesh_db.vhd | 344 +-
.../src/vhdl/unb1_terminal_bg_mesh_db.vhd | 506 +-
.../tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd | 272 +-
.../unb1_test_10GbE/tb_unb1_test_10GbE.vhd | 12 +-
.../unb1_test_10GbE/unb1_test_10GbE.vhd | 128 +-
.../tb_unb1_test_10GbE_tx_only.vhd | 12 +-
.../unb1_test_10GbE_tx_only.vhd | 110 +-
.../unb1_test_1GbE/tb_unb1_test_1GbE.vhd | 12 +-
.../unb1_test_1GbE/unb1_test_1GbE.vhd | 66 +-
.../unb1_test_all/tb_unb1_test_all.vhd | 12 +-
.../revisions/unb1_test_all/unb1_test_all.vhd | 146 +-
.../unb1_test_ddr/tb_unb1_test_ddr.vhd | 12 +-
.../revisions/unb1_test_ddr/unb1_test_ddr.vhd | 80 +-
.../tb_unb1_test_ddr_16g_MB_I.vhd | 12 +-
.../unb1_test_ddr_16g_MB_I.vhd | 76 +-
.../tb_unb1_test_ddr_16g_MB_II.vhd | 12 +-
.../unb1_test_ddr_16g_MB_II.vhd | 76 +-
.../tb_unb1_test_ddr_16g_MB_I_II.vhd | 12 +-
.../unb1_test_ddr_16g_MB_I_II.vhd | 84 +-
.../tb_unb1_test_ddr_MB_I.vhd | 12 +-
.../tb_unb1_test_ddr_MB_II.vhd | 12 +-
.../tb_unb1_test_ddr_MB_I_II.vhd | 12 +-
.../unb1_test_ddr_MB_I_II.vhd | 84 +-
.../unb1_test/src/vhdl/mmm_unb1_test.vhd | 282 +-
.../unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd | 666 +-
.../designs/unb1_test/src/vhdl/udp_stream.vhd | 325 +-
.../designs/unb1_test/src/vhdl/unb1_test.vhd | 1213 +--
.../unb1_test/src/vhdl/unb1_test_pkg.vhd | 69 +-
.../unb1_test/tb/vhdl/tb_unb1_test.vhd | 112 +-
.../src/vhdl/mmm_unb1_tr_10GbE.vhd | 36 +-
.../unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd | 619 +-
.../tb/vhdl/tb_unb1_tr_10GbE.vhd | 10 +-
.../unb1_board/src/vhdl/ctrl_unb1_board.vhd | 454 +-
.../src/vhdl/mms_unb1_board_sens.vhd | 78 +-
.../src/vhdl/mms_unb1_board_system_info.vhd | 115 +-
.../src/vhdl/node_unb1_fn_terminal_db.vhd | 266 +-
.../src/vhdl/unb1_board_back_io.vhd | 6 +-
.../src/vhdl/unb1_board_back_reorder.vhd | 130 +-
.../src/vhdl/unb1_board_back_select.vhd | 10 +-
.../unb1_board_back_uth_terminals_bidir.vhd | 94 +-
.../src/vhdl/unb1_board_clk200_pll.vhd | 290 +-
.../src/vhdl/unb1_board_clk25_pll.vhd | 46 +-
.../src/vhdl/unb1_board_clk_rst.vhd | 50 +-
.../src/vhdl/unb1_board_front_io.vhd | 54 +-
.../src/vhdl/unb1_board_mesh_io.vhd | 6 +-
.../vhdl/unb1_board_mesh_reorder_bidir.vhd | 58 +-
.../src/vhdl/unb1_board_mesh_reorder_rx.vhd | 14 +-
.../src/vhdl/unb1_board_mesh_reorder_tx.vhd | 40 +-
.../unb1_board_mesh_uth_terminals_bidir.vhd | 100 +-
.../src/vhdl/unb1_board_node_ctrl.vhd | 108 +-
.../src/vhdl/unb1_board_peripherals_pkg.vhd | 6 +-
.../unb1_board/src/vhdl/unb1_board_pkg.vhd | 32 +-
.../unb1_board/src/vhdl/unb1_board_sens.vhd | 84 +-
.../src/vhdl/unb1_board_sens_ctrl.vhd | 12 +-
.../src/vhdl/unb1_board_sens_reg.vhd | 33 +-
.../src/vhdl/unb1_board_system_info.vhd | 14 +-
.../src/vhdl/unb1_board_system_info_reg.vhd | 40 +-
.../src/vhdl/unb1_board_terminals_back.vhd | 228 +-
.../src/vhdl/unb1_board_terminals_mesh.vhd | 318 +-
.../src/vhdl/unb1_board_wdi_extend.vhd | 54 +-
.../src/vhdl/unb1_board_wdi_reg.vhd | 21 +-
.../tb/vhdl/tb_mms_unb1_board_sens.vhd | 102 +-
.../vhdl/tb_tb_tb_unb1_board_regression.vhd | 2 +-
.../tb/vhdl/tb_unb1_board_clk200_pll.vhd | 124 +-
.../vhdl/tb_unb1_board_mesh_reorder_bidir.vhd | 224 +-
.../tb/vhdl/tb_unb1_board_node_ctrl.vhd | 40 +-
.../unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd | 10 +-
.../tb/vhdl/unb1_board_back_model_sl.vhd | 10 +-
.../tb/vhdl/unb1_board_back_model_sosi.vhd | 10 +-
.../tb/vhdl/unb1_board_mesh_model_siso.vhd | 14 +-
.../tb/vhdl/unb1_board_mesh_model_sl.vhd | 16 +-
.../tb/vhdl/unb1_board_mesh_model_sosi.vhd | 14 +-
.../designs/unb2_led/src/vhdl/unb2_led.vhd | 116 +-
.../designs/unb2_led/tb/vhdl/tb_unb2_led.vhd | 20 +-
.../src/vhdl/mmm_unb2_minimal.vhd | 65 +-
.../src/vhdl/qsys_unb2_minimal_pkg.vhd | 256 +-
.../unb2_minimal/src/vhdl/unb2_minimal.vhd | 432 +-
.../unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd | 74 +-
.../unb2_pinning/src/vhdl/unb2_pinning.vhd | 1548 ++--
.../src/vhdl/unb2_singlemac.vhd | 422 +-
.../unb2_test_10GbE/tb_unb2_test_10GbE.vhd | 8 +-
.../unb2_test_10GbE/unb2_test_10GbE.vhd | 174 +-
.../unb2_test_1GbE/tb_unb2_test_1GbE.vhd | 8 +-
.../unb2_test_1GbE/unb2_test_1GbE.vhd | 76 +-
.../unb2_test_all/tb_unb2_test_all.vhd | 10 +-
.../revisions/unb2_test_all/unb2_test_all.vhd | 198 +-
.../tb_unb2_test_ddr_MB_I.vhd | 10 +-
.../unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd | 104 +-
.../tb_unb2_test_ddr_MB_II.vhd | 10 +-
.../unb2_test_ddr_MB_II.vhd | 104 +-
.../tb_unb2_test_ddr_MB_I_II.vhd | 10 +-
.../unb2_test_ddr_MB_I_II.vhd | 116 +-
.../unb2_test/src/vhdl/mmm_unb2_test.vhd | 391 +-
.../unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd | 700 +-
.../designs/unb2_test/src/vhdl/udp_stream.vhd | 335 +-
.../designs/unb2_test/src/vhdl/unb2_test.vhd | 1504 ++--
.../unb2_test/src/vhdl/unb2_test_pkg.vhd | 53 +-
.../unb2_test/tb/vhdl/tb_unb2_test.vhd | 254 +-
.../unb2_board/src/vhdl/ctrl_unb2_board.vhd | 604 +-
.../src/vhdl/mms_unb2_board_sens.vhd | 80 +-
.../src/vhdl/mms_unb2_board_system_info.vhd | 115 +-
.../src/vhdl/mms_unb2_fpga_sens.vhd | 92 +-
.../src/vhdl/unb2_board_back_io.vhd | 6 +-
.../src/vhdl/unb2_board_clk125_pll.vhd | 84 +-
.../src/vhdl/unb2_board_clk200_pll.vhd | 254 +-
.../src/vhdl/unb2_board_clk25_pll.vhd | 44 +-
.../src/vhdl/unb2_board_clk_rst.vhd | 50 +-
.../src/vhdl/unb2_board_front_io.vhd | 10 +-
.../src/vhdl/unb2_board_node_ctrl.vhd | 76 +-
.../src/vhdl/unb2_board_peripherals_pkg.vhd | 6 +-
.../unb2_board/src/vhdl/unb2_board_pkg.vhd | 24 +-
.../src/vhdl/unb2_board_pmbus_ctrl.vhd | 58 +-
.../src/vhdl/unb2_board_qsfp_leds.vhd | 168 +-
.../src/vhdl/unb2_board_ring_io.vhd | 6 +-
.../unb2_board/src/vhdl/unb2_board_sens.vhd | 118 +-
.../src/vhdl/unb2_board_sens_ctrl.vhd | 12 +-
.../src/vhdl/unb2_board_sens_reg.vhd | 33 +-
.../src/vhdl/unb2_board_system_info.vhd | 14 +-
.../src/vhdl/unb2_board_system_info_reg.vhd | 23 +-
.../src/vhdl/unb2_board_wdi_extend.vhd | 54 +-
.../src/vhdl/unb2_board_wdi_reg.vhd | 21 +-
.../src/vhdl/unb2_fpga_sens_reg.vhd | 36 +-
.../tb/vhdl/tb_mms_unb2_board_sens.vhd | 102 +-
.../tb/vhdl/tb_unb2_board_clk125_pll.vhd | 22 +-
.../tb/vhdl/tb_unb2_board_clk200_pll.vhd | 76 +-
.../tb/vhdl/tb_unb2_board_clk25_pll.vhd | 22 +-
.../tb/vhdl/tb_unb2_board_node_ctrl.vhd | 42 +-
.../tb/vhdl/tb_unb2_board_qsfp_leds.vhd | 92 +-
.../src/vhdl/unb2_board_10gbe.vhd | 36 +-
.../ddr4_micron46_mbIIskew_inst.vhd | 178 +-
.../ddr4_micron46_mbIskew_inst.vhd | 178 +-
.../src/vhdl/mmm_unb2a_heater.vhd | 70 +-
.../src/vhdl/qsys_unb2a_heater_pkg.vhd | 270 +-
.../unb2a_heater/src/vhdl/unb2a_heater.vhd | 464 +-
.../unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd | 74 +-
.../designs/unb2a_led/src/vhdl/unb2a_led.vhd | 152 +-
.../unb2a_led/tb/vhdl/tb_unb2a_led.vhd | 20 +-
.../src/vhdl/mmm_unb2a_minimal.vhd | 65 +-
.../src/vhdl/qsys_unb2a_minimal_pkg.vhd | 256 +-
.../unb2a_minimal/src/vhdl/unb2a_minimal.vhd | 420 +-
.../tb/vhdl/tb_unb2a_minimal.vhd | 104 +-
.../unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd | 8 +-
.../unb2a_test_10GbE/unb2a_test_10GbE.vhd | 174 +-
.../unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd | 8 +-
.../unb2a_test_1GbE/unb2a_test_1GbE.vhd | 76 +-
.../unb2a_test_all/tb_unb2a_test_all.vhd | 10 +-
.../unb2a_test_all/unb2a_test_all.vhd | 198 +-
.../tb_unb2a_test_ddr_MB_I.vhd | 10 +-
.../unb2a_test_ddr_MB_I.vhd | 104 +-
.../tb_unb2a_test_ddr_MB_II.vhd | 10 +-
.../unb2a_test_ddr_MB_II.vhd | 104 +-
.../tb_unb2a_test_ddr_MB_I_II.vhd | 10 +-
.../unb2a_test_ddr_MB_I_II.vhd | 116 +-
.../unb2a_test/src/vhdl/mmm_unb2a_test.vhd | 405 +-
.../src/vhdl/qsys_unb2a_test_pkg.vhd | 730 +-
.../unb2a_test/src/vhdl/udp_stream.vhd | 337 +-
.../unb2a_test/src/vhdl/unb2a_test.vhd | 1520 ++--
.../unb2a_test/src/vhdl/unb2a_test_pkg.vhd | 53 +-
.../unb2a_test/tb/vhdl/tb_unb2a_test.vhd | 254 +-
.../unb2a_board/src/vhdl/ctrl_unb2_board.vhd | 598 +-
.../src/vhdl/mms_unb2_board_sens.vhd | 82 +-
.../src/vhdl/mms_unb2_board_system_info.vhd | 115 +-
.../src/vhdl/mms_unb2_fpga_sens.vhd | 92 +-
.../src/vhdl/unb2_board_back_io.vhd | 6 +-
.../src/vhdl/unb2_board_clk125_pll.vhd | 84 +-
.../src/vhdl/unb2_board_clk200_pll.vhd | 254 +-
.../src/vhdl/unb2_board_clk25_pll.vhd | 44 +-
.../src/vhdl/unb2_board_clk_rst.vhd | 50 +-
.../src/vhdl/unb2_board_front_io.vhd | 10 +-
.../src/vhdl/unb2_board_hmc_ctrl.vhd | 10 +-
.../src/vhdl/unb2_board_node_ctrl.vhd | 76 +-
.../src/vhdl/unb2_board_peripherals_pkg.vhd | 6 +-
.../unb2a_board/src/vhdl/unb2_board_pkg.vhd | 24 +-
.../src/vhdl/unb2_board_pmbus_ctrl.vhd | 10 +-
.../src/vhdl/unb2_board_qsfp_leds.vhd | 168 +-
.../src/vhdl/unb2_board_ring_io.vhd | 6 +-
.../unb2a_board/src/vhdl/unb2_board_sens.vhd | 182 +-
.../src/vhdl/unb2_board_sens_ctrl.vhd | 14 +-
.../src/vhdl/unb2_board_sens_reg.vhd | 33 +-
.../src/vhdl/unb2_board_system_info.vhd | 14 +-
.../src/vhdl/unb2_board_system_info_reg.vhd | 23 +-
.../src/vhdl/unb2_board_wdi_extend.vhd | 54 +-
.../src/vhdl/unb2_board_wdi_reg.vhd | 21 +-
.../src/vhdl/unb2_fpga_sens_reg.vhd | 36 +-
.../tb/vhdl/tb_mms_unb2_board_sens.vhd | 110 +-
.../tb/vhdl/tb_unb2_board_clk125_pll.vhd | 22 +-
.../tb/vhdl/tb_unb2_board_clk200_pll.vhd | 76 +-
.../tb/vhdl/tb_unb2_board_clk25_pll.vhd | 22 +-
.../tb/vhdl/tb_unb2_board_node_ctrl.vhd | 42 +-
.../tb/vhdl/tb_unb2_board_qsfp_leds.vhd | 92 +-
.../src/vhdl/unb2_board_10gbe.vhd | 34 +-
.../src/vhdl/unb2b_arp_ping.vhd | 344 +-
.../unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd | 363 +-
.../unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd | 40 +-
.../tb/vhdl/tb_unb2b_arp_ping.vhd | 368 +-
.../src/vhdl/mmm_unb2b_heater.vhd | 74 +-
.../src/vhdl/qsys_unb2b_heater_pkg.vhd | 270 +-
.../unb2b_heater/src/vhdl/unb2b_heater.vhd | 484 +-
.../unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd | 74 +-
.../altjesd_ss_RX_corepll_inst.vhd | 34 +-
.../altjesd_ss_RX_frame_reset_inst.vhd | 26 +-
.../altjesd_ss_RX_link_reset_inst.vhd | 26 +-
.../altjesd_ss_RX_reset_seq_inst.vhd | 322 +-
.../altjesd_ss_RX_xcvr_reset_control_inst.vhd | 46 +-
.../device_clk/device_clk_inst.vhd | 30 +-
.../frame_clk/frame_clk_inst.vhd | 30 +-
.../ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd | 198 +-
.../link_clk/link_clk_inst.vhd | 30 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...sys_unb2b_minimal_avs_common_mm_0_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...sys_unb2b_minimal_avs_common_mm_1_inst.vhd | 86 +-
.../avs2_eth_coe_10/sim/avs2_eth_coe.vhd | 8 +-
.../sim/common_network_layers_pkg.vhd | 447 +-
.../avs2_eth_coe_10/sim/common_pkg.vhd | 134 +-
.../avs2_eth_coe_10/sim/dp_stream_pkg.vhd | 141 +-
.../avs2_eth_coe_10/sim/eth_pkg.vhd | 57 +-
.../avs2_eth_coe_10/sim/tech_tse_pkg.vhd | 4 +-
.../avs2_eth_coe_10/synth/avs2_eth_coe.vhd | 8 +-
.../synth/common_network_layers_pkg.vhd | 447 +-
.../avs2_eth_coe_10/synth/common_pkg.vhd | 134 +-
.../avs2_eth_coe_10/synth/dp_stream_pkg.vhd | 141 +-
.../avs2_eth_coe_10/synth/eth_pkg.vhd | 57 +-
.../avs2_eth_coe_10/synth/tech_tse_pkg.vhd | 4 +-
.../qsys_unb2b_minimal_avs_eth_0_inst.vhd | 166 +-
.../qsys_unb2b_minimal_clk_0_inst.vhd | 30 +-
.../qsys_unb2b_minimal_cpu_0_inst.vhd | 118 +-
.../qsys_unb2b_minimal_jesd204_inst.vhd | 198 +-
..._0_altera_avalon_jtag_uart_180_tj65noi.vhd | 1224 +--
.../qsys_unb2b_minimal_jtag_uart_0_inst.vhd | 54 +-
...tera_avalon_onchip_memory2_180_lo46q2y.vhd | 166 +-
...ys_unb2b_minimal_onchip_memory2_0_inst.vhd | 54 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_pio_pps_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...sys_unb2b_minimal_pio_system_info_inst.vhd | 86 +-
..._pio_wdi_altera_avalon_pio_180_2botkdq.vhd | 43 +-
.../qsys_unb2b_minimal_pio_wdi_inst.vhd | 46 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_dpmm_data_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_epcs_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
..._unb2b_minimal_reg_fpga_temp_sens_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...b2b_minimal_reg_fpga_voltage_sens_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_mmdp_data_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_remu_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_unb_sens_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_wdi_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...sys_unb2b_minimal_rom_system_info_inst.vhd | 86 +-
...imer_0_altera_avalon_timer_180_5qqtsby.vhd | 73 +-
.../qsys_unb2b_minimal_timer_0_inst.vhd | 46 +-
.../unb2b_jesd_node0/unb2b_jesd_node0.vhd | 96 +-
.../altjesd_ss_RX_corepll_inst.vhd | 34 +-
.../altjesd_ss_RX_frame_reset_inst.vhd | 26 +-
.../altjesd_ss_RX_link_reset_inst.vhd | 26 +-
.../altjesd_ss_RX_reset_seq_inst.vhd | 322 +-
.../altjesd_ss_RX_xcvr_reset_control_inst.vhd | 46 +-
.../device_clk/device_clk_inst.vhd | 30 +-
.../frame_clk/frame_clk_inst.vhd | 30 +-
.../ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd | 198 +-
.../link_clk/link_clk_inst.vhd | 30 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...sys_unb2b_minimal_avs_common_mm_0_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...sys_unb2b_minimal_avs_common_mm_1_inst.vhd | 86 +-
.../avs2_eth_coe_10/sim/avs2_eth_coe.vhd | 8 +-
.../sim/common_network_layers_pkg.vhd | 447 +-
.../avs2_eth_coe_10/sim/common_pkg.vhd | 134 +-
.../avs2_eth_coe_10/sim/dp_stream_pkg.vhd | 141 +-
.../avs2_eth_coe_10/sim/eth_pkg.vhd | 57 +-
.../avs2_eth_coe_10/sim/tech_tse_pkg.vhd | 4 +-
.../avs2_eth_coe_10/synth/avs2_eth_coe.vhd | 8 +-
.../synth/common_network_layers_pkg.vhd | 447 +-
.../avs2_eth_coe_10/synth/common_pkg.vhd | 134 +-
.../avs2_eth_coe_10/synth/dp_stream_pkg.vhd | 141 +-
.../avs2_eth_coe_10/synth/eth_pkg.vhd | 57 +-
.../avs2_eth_coe_10/synth/tech_tse_pkg.vhd | 4 +-
.../qsys_unb2b_minimal_avs_eth_0_inst.vhd | 166 +-
.../qsys_unb2b_minimal_clk_0_inst.vhd | 30 +-
.../qsys_unb2b_minimal_cpu_0_inst.vhd | 118 +-
.../qsys_unb2b_minimal_jesd204_inst.vhd | 198 +-
..._0_altera_avalon_jtag_uart_180_tj65noi.vhd | 1224 +--
.../qsys_unb2b_minimal_jtag_uart_0_inst.vhd | 54 +-
...tera_avalon_onchip_memory2_180_lo46q2y.vhd | 166 +-
...ys_unb2b_minimal_onchip_memory2_0_inst.vhd | 54 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_pio_pps_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...sys_unb2b_minimal_pio_system_info_inst.vhd | 86 +-
..._pio_wdi_altera_avalon_pio_180_2botkdq.vhd | 43 +-
.../qsys_unb2b_minimal_pio_wdi_inst.vhd | 46 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_dpmm_data_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_epcs_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
..._unb2b_minimal_reg_fpga_temp_sens_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...b2b_minimal_reg_fpga_voltage_sens_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_mmdp_data_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_remu_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_unb_sens_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_wdi_inst.vhd | 86 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...sys_unb2b_minimal_rom_system_info_inst.vhd | 86 +-
...imer_0_altera_avalon_timer_180_5qqtsby.vhd | 73 +-
.../qsys_unb2b_minimal_timer_0_inst.vhd | 46 +-
.../unb2b_jesd_node3/unb2b_jesd_node3.vhd | 96 +-
.../unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd | 165 +-
.../src/vhdl/qsys_unb2b_jesd_pkg.vhd | 380 +-
.../unb2b_jesd/src/vhdl/unb2b_jesd.vhd | 464 +-
.../unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd | 104 +-
.../unb2b_minimal_125m/unb2b_minimal_125m.vhd | 84 +-
.../src/vhdl/mmm_unb2b_minimal.vhd | 70 +-
.../src/vhdl/qsys_unb2b_minimal_pkg.vhd | 270 +-
.../unb2b_minimal/src/vhdl/unb2b_minimal.vhd | 438 +-
.../tb/vhdl/tb_unb2b_minimal.vhd | 104 +-
.../unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd | 8 +-
.../unb2b_test_10GbE/unb2b_test_10GbE.vhd | 174 +-
.../tb_unb2b_test_ddr_MB_I_II.vhd | 10 +-
.../unb2b_test_ddr_MB_I_II.vhd | 116 +-
.../unb2b_test/src/vhdl/mmm_unb2b_test.vhd | 398 +-
.../src/vhdl/qsys_unb2b_test_pkg.vhd | 714 +-
.../unb2b_test/src/vhdl/udp_stream.vhd | 337 +-
.../unb2b_test/src/vhdl/unb2b_test.vhd | 1510 ++--
.../unb2b_test/src/vhdl/unb2b_test_pkg.vhd | 53 +-
.../unb2b_test/tb/vhdl/tb_unb2b_test.vhd | 254 +-
.../unb2b_board/src/vhdl/ctrl_unb2b_board.vhd | 628 +-
.../src/vhdl/mms_unb2b_board_sens.vhd | 82 +-
.../src/vhdl/mms_unb2b_board_system_info.vhd | 115 +-
.../src/vhdl/mms_unb2b_fpga_sens.vhd | 40 +-
.../src/vhdl/unb2b_board_back_io.vhd | 6 +-
.../src/vhdl/unb2b_board_clk125_pll.vhd | 84 +-
.../src/vhdl/unb2b_board_clk200_pll.vhd | 254 +-
.../src/vhdl/unb2b_board_clk25_pll.vhd | 44 +-
.../src/vhdl/unb2b_board_clk_rst.vhd | 50 +-
.../src/vhdl/unb2b_board_front_io.vhd | 10 +-
.../src/vhdl/unb2b_board_hmc_ctrl.vhd | 10 +-
.../src/vhdl/unb2b_board_node_ctrl.vhd | 76 +-
.../src/vhdl/unb2b_board_peripherals_pkg.vhd | 6 +-
.../unb2b_board/src/vhdl/unb2b_board_pkg.vhd | 24 +-
.../src/vhdl/unb2b_board_pmbus_ctrl.vhd | 10 +-
.../src/vhdl/unb2b_board_qsfp_leds.vhd | 168 +-
.../src/vhdl/unb2b_board_ring_io.vhd | 6 +-
.../unb2b_board/src/vhdl/unb2b_board_sens.vhd | 182 +-
.../src/vhdl/unb2b_board_sens_ctrl.vhd | 14 +-
.../src/vhdl/unb2b_board_sens_reg.vhd | 33 +-
.../src/vhdl/unb2b_board_system_info.vhd | 14 +-
.../src/vhdl/unb2b_board_system_info_reg.vhd | 23 +-
.../src/vhdl/unb2b_board_wdi_extend.vhd | 54 +-
.../src/vhdl/unb2b_board_wdi_reg.vhd | 21 +-
.../tb/vhdl/tb_mms_unb2b_board_sens.vhd | 110 +-
.../tb/vhdl/tb_unb2b_board_clk125_pll.vhd | 22 +-
.../tb/vhdl/tb_unb2b_board_clk200_pll.vhd | 76 +-
.../tb/vhdl/tb_unb2b_board_clk25_pll.vhd | 22 +-
.../tb/vhdl/tb_unb2b_board_node_ctrl.vhd | 42 +-
.../tb/vhdl/tb_unb2b_board_qsfp_leds.vhd | 92 +-
.../src/vhdl/unb2b_board_10gbe.vhd | 34 +-
.../designs/unb2c_led/src/vhdl/unb2c_led.vhd | 168 +-
.../src/vhdl/mmm_unb2c_minimal.vhd | 60 +-
.../src/vhdl/qsys_unb2c_minimal_pkg.vhd | 242 +-
.../unb2c_minimal/src/vhdl/unb2c_minimal.vhd | 404 +-
.../tb/vhdl/tb_unb2c_minimal.vhd | 24 +-
.../unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd | 8 +-
.../unb2c_test_10GbE/unb2c_test_10GbE.vhd | 128 +-
.../tb_unb2c_test_1GbE_I.vhd | 42 +-
.../unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd | 64 +-
.../tb_unb2c_test_1GbE_II.vhd | 42 +-
.../unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd | 64 +-
.../unb2c_test_ddr/tb_unb2c_test_ddr.vhd | 8 +-
.../unb2c_test_ddr/unb2c_test_ddr.vhd | 88 +-
.../tb_unb2c_test_ddr_16G.vhd | 8 +-
.../unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd | 88 +-
.../tb_unb2c_test_heater.vhd | 8 +-
.../unb2c_test_heater/unb2c_test_heater.vhd | 64 +-
.../tb_unb2c_test_jesd204b.vhd | 8 +-
.../unb2c_test_jesd204b.vhd | 74 +-
.../unb2c_test_minimal/unb2c_test_minimal.vhd | 64 +-
.../unb2c_test/src/vhdl/mmm_unb2c_test.vhd | 301 +-
.../vhdl/node_adc_input_and_timing_nowg.vhd | 251 +-
.../src/vhdl/qsys_unb2c_test_pkg.vhd | 882 +-
.../unb2c_test/src/vhdl/udp_stream.vhd | 337 +-
.../unb2c_test/src/vhdl/unb2c_test.vhd | 1688 ++--
.../unb2c_test/src/vhdl/unb2c_test_pkg.vhd | 81 +-
.../unb2c_test/tb/vhdl/tb_unb2c_test.vhd | 186 +-
.../source/bscan2_8port_top.vhd | 152 +-
.../source/jtag_top(str).vhd | 222 +-
.../UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd | 34 +-
.../unb2c_board/src/vhdl/ctrl_unb2c_board.vhd | 542 +-
.../src/vhdl/mms_unb2c_board_system_info.vhd | 115 +-
.../src/vhdl/mms_unb2c_fpga_sens.vhd | 40 +-
.../src/vhdl/unb2c_board_back_io.vhd | 6 +-
.../src/vhdl/unb2c_board_clk125_pll.vhd | 84 +-
.../src/vhdl/unb2c_board_clk200_pll.vhd | 254 +-
.../src/vhdl/unb2c_board_clk25_pll.vhd | 44 +-
.../src/vhdl/unb2c_board_clk_rst.vhd | 50 +-
.../src/vhdl/unb2c_board_front_io.vhd | 10 +-
.../src/vhdl/unb2c_board_node_ctrl.vhd | 76 +-
.../src/vhdl/unb2c_board_peripherals_pkg.vhd | 6 +-
.../unb2c_board/src/vhdl/unb2c_board_pkg.vhd | 24 +-
.../src/vhdl/unb2c_board_qsfp_leds.vhd | 168 +-
.../src/vhdl/unb2c_board_ring_io.vhd | 6 +-
.../src/vhdl/unb2c_board_system_info.vhd | 14 +-
.../src/vhdl/unb2c_board_system_info_reg.vhd | 23 +-
.../src/vhdl/unb2c_board_wdi_extend.vhd | 54 +-
.../src/vhdl/unb2c_board_wdi_reg.vhd | 21 +-
.../tb/vhdl/tb_unb2c_board_clk125_pll.vhd | 22 +-
.../tb/vhdl/tb_unb2c_board_clk200_pll.vhd | 76 +-
.../tb/vhdl/tb_unb2c_board_clk25_pll.vhd | 22 +-
.../tb/vhdl/tb_unb2c_board_node_ctrl.vhd | 42 +-
.../tb/vhdl/tb_unb2c_board_qsfp_leds.vhd | 92 +-
.../src/vhdl/unb2c_board_10gbe.vhd | 34 +-
.../axi4/src/vhdl/axi4_lite_mm_bridge.vhd | 12 +-
.../base/axi4/src/vhdl/axi4_lite_pkg.vhd | 12 +-
.../axi4/src/vhdl/axi4_stream_dp_bridge.vhd | 64 +-
.../base/axi4/src/vhdl/axi4_stream_pkg.vhd | 90 +-
.../axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd | 52 +-
.../tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd | 2 +-
.../base/common/src/vhdl/avs_common_mm.vhd | 2 +-
.../common/src/vhdl/avs_common_mm_irq.vhd | 2 +-
.../src/vhdl/avs_common_mm_readlatency0.vhd | 2 +-
.../src/vhdl/avs_common_mm_readlatency2.vhd | 2 +-
.../src/vhdl/avs_common_mm_readlatency4.vhd | 2 +-
.../src/vhdl/avs_common_ram_crw_crw.vhd | 44 +-
.../common/src/vhdl/avs_common_reg_r_w.vhd | 6 +-
.../base/common/src/vhdl/common_acapture.vhd | 44 +-
.../common/src/vhdl/common_acapture_slv.vhd | 30 +-
.../common/src/vhdl/common_accumulate.vhd | 10 +-
.../base/common/src/vhdl/common_add_sub.vhd | 28 +-
.../common/src/vhdl/common_add_symbol.vhd | 100 +-
.../common/src/vhdl/common_adder_tree.vhd | 28 +-
.../vhdl/common_adder_tree_a_recursive.vhd | 106 +-
.../src/vhdl/common_adder_tree_a_str.vhd | 86 +-
.../base/common/src/vhdl/common_areset.vhd | 26 +-
.../base/common/src/vhdl/common_async.vhd | 4 +-
.../base/common/src/vhdl/common_async_slv.vhd | 24 +-
.../base/common/src/vhdl/common_bit_delay.vhd | 2 +-
.../base/common/src/vhdl/common_blockreg.vhd | 56 +-
.../base/common/src/vhdl/common_clip.vhd | 52 +-
.../src/vhdl/common_clock_active_detector.vhd | 102 +-
.../src/vhdl/common_clock_phase_detector.vhd | 26 +-
.../src/vhdl/common_complex_add_sub.vhd | 62 +-
.../common/src/vhdl/common_complex_round.vhd | 62 +-
.../common/src/vhdl/common_components_pkg.vhd | 44 +-
.../base/common/src/vhdl/common_counter.vhd | 6 +-
.../vhdl/common_create_strobes_from_valid.vhd | 4 +-
.../base/common/src/vhdl/common_ddio_in.vhd | 28 +-
.../base/common/src/vhdl/common_ddio_out.vhd | 28 +-
.../base/common/src/vhdl/common_ddreg.vhd | 150 +-
.../base/common/src/vhdl/common_ddreg_slv.vhd | 28 +-
.../base/common/src/vhdl/common_debounce.vhd | 40 +-
.../common/src/vhdl/common_deinterleave.vhd | 78 +-
.../base/common/src/vhdl/common_delay.vhd | 2 +-
.../common/src/vhdl/common_demultiplexer.vhd | 16 +-
.../common/src/vhdl/common_duty_cycle.vhd | 28 +-
libraries/base/common/src/vhdl/common_evt.vhd | 4 +-
.../base/common/src/vhdl/common_fanout.vhd | 68 +-
.../common/src/vhdl/common_fanout_tree.vhd | 170 +-
.../base/common/src/vhdl/common_field_pkg.vhd | 68 +-
.../base/common/src/vhdl/common_fifo_dc.vhd | 78 +-
.../src/vhdl/common_fifo_dc_lock_control.vhd | 148 +-
.../src/vhdl/common_fifo_dc_mixed_widths.vhd | 80 +-
.../base/common/src/vhdl/common_fifo_rd.vhd | 50 +-
.../base/common/src/vhdl/common_fifo_sc.vhd | 80 +-
.../common/src/vhdl/common_flank_to_pulse.vhd | 4 +-
.../common/src/vhdl/common_frame_busy.vhd | 14 +-
.../base/common/src/vhdl/common_init.vhd | 54 +-
.../base/common/src/vhdl/common_inout.vhd | 4 +-
.../src/vhdl/common_interface_layers_pkg.vhd | 8 +-
.../common/src/vhdl/common_interleave.vhd | 130 +-
.../src/vhdl/common_interval_monitor.vhd | 16 +-
.../base/common/src/vhdl/common_iobuf_in.vhd | 4 +-
.../common/src/vhdl/common_led_controller.vhd | 24 +-
.../src/vhdl/common_lfsr_sequences_pkg.vhd | 189 +-
.../base/common/src/vhdl/common_math_pkg.vhd | 8 +-
.../base/common/src/vhdl/common_mem_demux.vhd | 6 +-
.../base/common/src/vhdl/common_mem_mux.vhd | 6 +-
.../base/common/src/vhdl/common_mem_pkg.vhd | 44 +-
.../common/src/vhdl/common_multiplexer.vhd | 44 +-
.../src/vhdl/common_network_layers_pkg.vhd | 457 +-
.../vhdl/common_network_total_header_pkg.vhd | 155 +-
.../base/common/src/vhdl/common_operation.vhd | 30 +-
.../common/src/vhdl/common_operation_tree.vhd | 120 +-
.../src/vhdl/common_paged_ram_crw_crw.vhd | 201 +-
.../common/src/vhdl/common_paged_ram_r_w.vhd | 68 +-
.../src/vhdl/common_paged_ram_rw_rw.vhd | 74 +-
.../common/src/vhdl/common_paged_ram_w_rr.vhd | 64 +-
.../src/vhdl/common_paged_ram_ww_rr.vhd | 65 +-
.../base/common/src/vhdl/common_paged_reg.vhd | 26 +-
.../base/common/src/vhdl/common_peak.vhd | 8 +-
.../base/common/src/vhdl/common_pipeline.vhd | 4 +-
.../src/vhdl/common_pipeline_integer.vhd | 36 +-
.../src/vhdl/common_pipeline_natural.vhd | 36 +-
.../common/src/vhdl/common_pipeline_sl.vhd | 38 +-
.../src/vhdl/common_pipeline_symbol.vhd | 94 +-
libraries/base/common/src/vhdl/common_pkg.vhd | 140 +-
.../common/src/vhdl/common_pulse_delay.vhd | 52 +-
.../src/vhdl/common_pulse_delay_reg.vhd | 41 +-
.../common/src/vhdl/common_pulse_extend.vhd | 18 +-
.../base/common/src/vhdl/common_pulser.vhd | 50 +-
.../common/src/vhdl/common_pulser_us_ms_s.vhd | 78 +-
.../base/common/src/vhdl/common_ram_cr_cw.vhd | 56 +-
.../src/vhdl/common_ram_cr_cw_ratio.vhd | 58 +-
.../common/src/vhdl/common_ram_crw_cr.vhd | 56 +-
.../common/src/vhdl/common_ram_crw_cw.vhd | 56 +-
.../base/common/src/vhdl/common_ram_r_w.vhd | 52 +-
.../base/common/src/vhdl/common_ram_rw_rw.vhd | 58 +-
.../src/vhdl/common_reg_cross_domain.vhd | 48 +-
.../base/common/src/vhdl/common_reg_r_w.vhd | 88 +-
.../common/src/vhdl/common_reg_r_w_dc.vhd | 162 +-
.../common/src/vhdl/common_reinterleave.vhd | 106 +-
.../common/src/vhdl/common_reorder_symbol.vhd | 284 +-
.../common/src/vhdl/common_requantize.vhd | 128 +-
.../base/common/src/vhdl/common_request.vhd | 20 +-
.../base/common/src/vhdl/common_resize.vhd | 56 +-
.../common/src/vhdl/common_reverse_n_data.vhd | 206 +-
.../common/src/vhdl/common_rl_decrease.vhd | 12 +-
.../common/src/vhdl/common_rl_increase.vhd | 28 +-
.../common/src/vhdl/common_rl_register.vhd | 90 +-
libraries/base/common/src/vhdl/common_rom.vhd | 40 +-
.../base/common/src/vhdl/common_round.vhd | 54 +-
.../src/vhdl/common_select_m_symbols.vhd | 88 +-
.../common/src/vhdl/common_select_symbol.vhd | 22 +-
.../base/common/src/vhdl/common_shiftram.vhd | 80 +-
.../base/common/src/vhdl/common_shiftreg.vhd | 168 +-
.../src/vhdl/common_shiftreg_symbol.vhd | 58 +-
.../base/common/src/vhdl/common_spulse.vhd | 20 +-
.../common/src/vhdl/common_stable_delayed.vhd | 54 +-
.../common/src/vhdl/common_stable_monitor.vhd | 66 +-
.../base/common/src/vhdl/common_str_pkg.vhd | 90 +-
.../base/common/src/vhdl/common_switch.vhd | 2 +-
.../base/common/src/vhdl/common_toggle.vhd | 26 +-
.../common/src/vhdl/common_toggle_align.vhd | 22 +-
.../base/common/src/vhdl/common_transpose.vhd | 370 +-
.../src/vhdl/common_transpose_symbol.vhd | 122 +-
.../common/src/vhdl/common_variable_delay.vhd | 4 +-
.../src/vhdl/common_wideband_data_scope.vhd | 4 +-
libraries/base/common/src/vhdl/common_zip.vhd | 30 +-
.../src/vhdl/mms_common_pulse_delay.vhd | 60 +-
.../base/common/src/vhdl/mms_common_reg.vhd | 48 +-
.../src/vhdl/mms_common_stable_monitor.vhd | 77 +-
.../src/vhdl/mms_common_variable_delay.vhd | 52 +-
.../common/tb/vhdl/tb_common_acapture.vhd | 28 +-
.../base/common/tb/vhdl/tb_common_add_sub.vhd | 66 +-
.../common/tb/vhdl/tb_common_adder_tree.vhd | 88 +-
.../base/common/tb/vhdl/tb_common_async.vhd | 46 +-
.../vhdl/tb_common_clock_phase_detector.vhd | 56 +-
.../base/common/tb/vhdl/tb_common_counter.vhd | 36 +-
.../tb_common_create_strobes_from_valid.vhd | 34 +-
.../base/common/tb/vhdl/tb_common_ddreg.vhd | 32 +-
.../common/tb/vhdl/tb_common_debounce.vhd | 80 +-
.../common/tb/vhdl/tb_common_duty_cycle.vhd | 42 +-
.../common/tb/vhdl/tb_common_fanout_tree.vhd | 49 +-
.../vhdl/tb_common_fifo_dc_mixed_widths.vhd | 46 +-
.../base/common/tb/vhdl/tb_common_fifo_rd.vhd | 40 +-
.../tb/vhdl/tb_common_flank_to_pulse.vhd | 18 +-
.../base/common/tb/vhdl/tb_common_gcd.vhd | 6 +-
.../base/common/tb/vhdl/tb_common_init.vhd | 42 +-
.../common/tb/vhdl/tb_common_int2float.vhd | 22 +-
.../common/tb/vhdl/tb_common_iobuf_in.vhd | 26 +-
.../tb/vhdl/tb_common_led_controller.vhd | 64 +-
.../base/common/tb/vhdl/tb_common_log.vhd | 30 +-
.../base/common/tb/vhdl/tb_common_mem_mux.vhd | 77 +-
.../base/common/tb/vhdl/tb_common_mem_pkg.vhd | 228 +-
.../common/tb/vhdl/tb_common_multiplexer.vhd | 120 +-
.../tb/vhdl/tb_common_operation_tree.vhd | 110 +-
.../tb/vhdl/tb_common_paged_ram_crw_crw.vhd | 210 +-
.../tb/vhdl/tb_common_paged_ram_ww_rr.vhd | 146 +-
.../base/common/tb/vhdl/tb_common_pkg.vhd | 1245 +--
.../common/tb/vhdl/tb_common_pulse_delay.vhd | 30 +-
.../common/tb/vhdl/tb_common_pulse_extend.vhd | 32 +-
.../base/common/tb/vhdl/tb_common_pulser.vhd | 92 +-
.../tb/vhdl/tb_common_pulser_us_ms_s.vhd | 32 +-
.../tb/vhdl/tb_common_reg_cross_domain.vhd | 44 +-
.../common/tb/vhdl/tb_common_reinterleave.vhd | 88 +-
.../tb/vhdl/tb_common_reorder_symbol.vhd | 304 +-
.../base/common/tb/vhdl/tb_common_rl.vhd | 114 +-
.../common/tb/vhdl/tb_common_rl_register.vhd | 82 +-
.../tb/vhdl/tb_common_select_m_symbols.vhd | 226 +-
.../common/tb/vhdl/tb_common_shiftram.vhd | 40 +-
.../common/tb/vhdl/tb_common_shiftreg.vhd | 70 +-
.../base/common/tb/vhdl/tb_common_spulse.vhd | 38 +-
.../base/common/tb/vhdl/tb_common_switch.vhd | 53 +-
.../base/common/tb/vhdl/tb_common_toggle.vhd | 30 +-
.../common/tb/vhdl/tb_common_toggle_align.vhd | 28 +-
.../common/tb/vhdl/tb_common_transpose.vhd | 119 +-
.../tb/vhdl/tb_common_transpose_symbol.vhd | 168 +-
.../tb/vhdl/tb_common_variable_delay.vhd | 30 +-
.../base/common/tb/vhdl/tb_common_zip.vhd | 34 +-
.../common/tb/vhdl/tb_delta_cycle_demo.vhd | 4 +-
.../tb/vhdl/tb_mms_common_variable_delay.vhd | 40 +-
.../base/common/tb/vhdl/tb_requantize.vhd | 580 +-
libraries/base/common/tb/vhdl/tb_round.vhd | 294 +-
.../common/tb/vhdl/tb_tb_common_add_sub.vhd | 2 +-
.../tb/vhdl/tb_tb_common_adder_tree.vhd | 4 +-
...tb_tb_common_create_strobes_from_valid.vhd | 2 +-
.../tb/vhdl/tb_tb_common_fanout_tree.vhd | 4 +-
.../tb/vhdl/tb_tb_common_multiplexer.vhd | 4 +-
.../tb/vhdl/tb_tb_common_operation_tree.vhd | 2 +-
.../tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd | 4 +-
.../tb/vhdl/tb_tb_common_reinterleave.vhd | 6 +-
.../tb/vhdl/tb_tb_common_reorder_symbol.vhd | 2 +-
.../base/common/tb/vhdl/tb_tb_common_rl.vhd | 4 +-
.../tb/vhdl/tb_tb_common_rl_register.vhd | 4 +-
.../common/tb/vhdl/tb_tb_common_transpose.vhd | 24 +-
.../base/common/tb/vhdl/tb_tb_resize.vhd | 2 +-
libraries/base/common/tb/vhdl/tb_tb_round.vhd | 2 +-
.../src/vhdl/common_complex_mult_add.vhd | 158 +-
.../base/common_mult/src/vhdl/common_mult.vhd | 120 +-
.../common_mult/src/vhdl/common_mult_add.vhd | 12 +-
.../common_mult/src/vhdl/common_mult_add2.vhd | 102 +-
.../common_mult/src/vhdl/common_mult_add4.vhd | 112 +-
.../tb/vhdl/tb_common_complex_mult.vhd | 142 +-
.../common_mult/tb/vhdl/tb_common_mult.vhd | 282 +-
.../tb/vhdl/tb_common_mult_add2.vhd | 76 +-
.../tb/vhdl/tb_tb_common_complex_mult.vhd | 6 +-
.../common_mult/tb/vhdl/tb_tb_common_mult.vhd | 2 +-
.../base/diag/src/vhdl/diag_block_gen.vhd | 296 +-
.../base/diag/src/vhdl/diag_block_gen_reg.vhd | 132 +-
libraries/base/diag/src/vhdl/diag_bypass.vhd | 8 +-
.../base/diag/src/vhdl/diag_data_buffer.vhd | 193 +-
.../diag/src/vhdl/diag_data_buffer_dev.vhd | 207 +-
.../base/diag/src/vhdl/diag_frm_generator.vhd | 154 +-
.../base/diag/src/vhdl/diag_frm_monitor.vhd | 102 +-
libraries/base/diag/src/vhdl/diag_pkg.vhd | 95 +-
libraries/base/diag/src/vhdl/diag_rx_seq.vhd | 132 +-
libraries/base/diag/src/vhdl/diag_tx_frm.vhd | 94 +-
libraries/base/diag/src/vhdl/diag_tx_seq.vhd | 74 +-
libraries/base/diag/src/vhdl/diag_wg.vhd | 184 +-
.../base/diag/src/vhdl/diag_wg_wideband.vhd | 132 +-
.../diag/src/vhdl/diag_wg_wideband_reg.vhd | 123 +-
.../base/diag/src/vhdl/mms_diag_block_gen.vhd | 279 +-
.../diag/src/vhdl/mms_diag_data_buffer.vhd | 146 +-
.../src/vhdl/mms_diag_data_buffer_dev.vhd | 148 +-
.../base/diag/src/vhdl/mms_diag_rx_seq.vhd | 150 +-
.../base/diag/src/vhdl/mms_diag_tx_seq.vhd | 166 +-
.../diag/src/vhdl/mms_diag_wg_wideband.vhd | 128 +-
.../src/vhdl/mms_diag_wg_wideband_arr.vhd | 120 +-
.../base/diag/tb/vhdl/tb_diag_block_gen.vhd | 156 +-
.../diag/tb/vhdl/tb_diag_data_buffer_dev.vhd | 141 +-
.../diag/tb/vhdl/tb_diag_frm_generator.vhd | 66 +-
.../base/diag/tb/vhdl/tb_diag_frm_monitor.vhd | 98 +-
libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd | 786 +-
.../base/diag/tb/vhdl/tb_diag_regression.vhd | 2 +-
.../base/diag/tb/vhdl/tb_diag_rx_seq.vhd | 92 +-
.../base/diag/tb/vhdl/tb_diag_tx_frm.vhd | 56 +-
.../base/diag/tb/vhdl/tb_diag_tx_seq.vhd | 30 +-
libraries/base/diag/tb/vhdl/tb_diag_wg.vhd | 158 +-
.../base/diag/tb/vhdl/tb_diag_wg_wideband.vhd | 102 +-
.../diag/tb/vhdl/tb_mms_diag_block_gen.vhd | 196 +-
.../base/diag/tb/vhdl/tb_mms_diag_seq.vhd | 146 +-
.../diag/tb/vhdl/tb_tb_diag_block_gen.vhd | 6 +-
.../base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd | 4 +-
.../diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd | 22 +-
.../base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd | 4 +-
.../base/diagnostics/src/vhdl/diagnostics.vhd | 198 +-
.../diagnostics/src/vhdl/diagnostics_reg.vhd | 29 +-
.../diagnostics/src/vhdl/mm_rx_logger.vhd | 218 +-
.../diagnostics/src/vhdl/mm_rx_logger_reg.vhd | 113 +-
.../src/vhdl/mm_rx_logger_trig.vhd | 8 +-
.../diagnostics/src/vhdl/mm_tx_framer.vhd | 114 +-
.../diagnostics/src/vhdl/mm_tx_framer_reg.vhd | 43 +-
.../diagnostics/src/vhdl/mms_diagnostics.vhd | 144 +-
.../diagnostics/tb/vhdl/tb_diagnostics.vhd | 18 +-
.../tb/vhdl/tb_diagnostics_trnb_pkg.vhd | 170 +-
.../diagnostics/tb/vhdl/tb_mm_tx_framer.vhd | 78 +-
.../src/vhdl/mmm_unb1_dp_offload.vhd | 378 +-
.../src/vhdl/unb1_dp_offload.vhd | 646 +-
.../tb/vhdl/tb_unb1_dp_offload.vhd | 12 +-
.../base/dp/src/vhdl/dp_barrel_shift.vhd | 13 +-
.../base/dp/src/vhdl/dp_block_from_mm.vhd | 10 +-
.../base/dp/src/vhdl/dp_block_from_mm_dc.vhd | 180 +-
libraries/base/dp/src/vhdl/dp_block_gen.vhd | 8 +-
.../dp/src/vhdl/dp_block_gen_valid_arr.vhd | 54 +-
.../base/dp/src/vhdl/dp_block_reshape.vhd | 49 +-
.../base/dp/src/vhdl/dp_block_reshape_arr.vhd | 38 +-
.../dp/src/vhdl/dp_block_reshape_sync.vhd | 60 +-
.../base/dp/src/vhdl/dp_block_resize.vhd | 70 +-
.../base/dp/src/vhdl/dp_block_select.vhd | 86 +-
libraries/base/dp/src/vhdl/dp_block_to_mm.vhd | 10 +-
.../vhdl/dp_block_validate_bsn_at_sync.vhd | 127 +-
.../dp/src/vhdl/dp_block_validate_channel.vhd | 66 +-
.../dp/src/vhdl/dp_block_validate_err.vhd | 231 +-
.../dp/src/vhdl/dp_block_validate_length.vhd | 30 +-
libraries/base/dp/src/vhdl/dp_bsn_align.vhd | 380 +-
.../base/dp/src/vhdl/dp_bsn_align_reg.vhd | 65 +-
.../base/dp/src/vhdl/dp_bsn_align_v2.vhd | 207 +-
libraries/base/dp/src/vhdl/dp_bsn_delay.vhd | 108 +-
libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd | 162 +-
.../base/dp/src/vhdl/dp_bsn_monitor_reg.vhd | 61 +-
.../dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd | 61 +-
.../base/dp/src/vhdl/dp_bsn_monitor_v2.vhd | 166 +-
.../dp/src/vhdl/dp_bsn_restore_global.vhd | 86 +-
.../base/dp/src/vhdl/dp_bsn_scheduler.vhd | 30 +-
.../base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd | 63 +-
libraries/base/dp/src/vhdl/dp_bsn_source.vhd | 8 +-
.../base/dp/src/vhdl/dp_bsn_source_reg.vhd | 125 +-
.../base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd | 151 +-
.../base/dp/src/vhdl/dp_bsn_source_v2.vhd | 18 +-
.../dp/src/vhdl/dp_bsn_sync_scheduler.vhd | 30 +-
.../base/dp/src/vhdl/dp_calculate_crc.vhd | 16 +-
libraries/base/dp/src/vhdl/dp_complex_add.vhd | 94 +-
.../base/dp/src/vhdl/dp_complex_mult.vhd | 90 +-
.../base/dp/src/vhdl/dp_components_pkg.vhd | 6 +-
libraries/base/dp/src/vhdl/dp_concat.vhd | 114 +-
.../base/dp/src/vhdl/dp_concat_field_blk.vhd | 112 +-
libraries/base/dp/src/vhdl/dp_counter.vhd | 122 +-
.../base/dp/src/vhdl/dp_counter_func.vhd | 46 +-
.../dp/src/vhdl/dp_counter_func_single.vhd | 12 +-
.../base/dp/src/vhdl/dp_deinterleave.vhd | 122 +-
.../dp/src/vhdl/dp_deinterleave_one_to_n.vhd | 78 +-
libraries/base/dp/src/vhdl/dp_demux.vhd | 150 +-
libraries/base/dp/src/vhdl/dp_distribute.vhd | 188 +-
.../base/dp/src/vhdl/dp_dummy_source.vhd | 30 +-
libraries/base/dp/src/vhdl/dp_eop_extend.vhd | 30 +-
libraries/base/dp/src/vhdl/dp_example_dut.vhd | 6 +-
libraries/base/dp/src/vhdl/dp_field_blk.vhd | 244 +-
libraries/base/dp/src/vhdl/dp_fifo_core.vhd | 135 +-
.../base/dp/src/vhdl/dp_fifo_core_arr.vhd | 153 +-
libraries/base/dp/src/vhdl/dp_fifo_dc.vhd | 86 +-
libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd | 96 +-
.../dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd | 140 +-
libraries/base/dp/src/vhdl/dp_fifo_fill.vhd | 84 +-
.../base/dp/src/vhdl/dp_fifo_fill_core.vhd | 176 +-
.../base/dp/src/vhdl/dp_fifo_fill_dc.vhd | 92 +-
.../base/dp/src/vhdl/dp_fifo_fill_eop.vhd | 134 +-
.../base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd | 96 +-
.../base/dp/src/vhdl/dp_fifo_fill_reg.vhd | 89 +-
.../base/dp/src/vhdl/dp_fifo_fill_sc.vhd | 94 +-
.../base/dp/src/vhdl/dp_fifo_from_mm.vhd | 46 +-
.../base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd | 19 +-
libraries/base/dp/src/vhdl/dp_fifo_info.vhd | 122 +-
.../base/dp/src/vhdl/dp_fifo_monitor.vhd | 53 +-
.../base/dp/src/vhdl/dp_fifo_monitor_arr.vhd | 58 +-
libraries/base/dp/src/vhdl/dp_fifo_sc.vhd | 90 +-
libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd | 44 +-
.../base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd | 19 +-
libraries/base/dp/src/vhdl/dp_flush.vhd | 128 +-
libraries/base/dp/src/vhdl/dp_folder.vhd | 114 +-
.../dp/src/vhdl/dp_force_data_parallel.vhd | 38 +-
.../base/dp/src/vhdl/dp_force_data_serial.vhd | 58 +-
libraries/base/dp/src/vhdl/dp_frame.vhd | 74 +-
libraries/base/dp/src/vhdl/dp_frame_busy.vhd | 54 +-
.../base/dp/src/vhdl/dp_frame_busy_arr.vhd | 22 +-
libraries/base/dp/src/vhdl/dp_frame_fsn.vhd | 96 +-
libraries/base/dp/src/vhdl/dp_frame_rd.vhd | 72 +-
.../base/dp/src/vhdl/dp_frame_remove.vhd | 96 +-
.../base/dp/src/vhdl/dp_frame_repack.vhd | 116 +-
libraries/base/dp/src/vhdl/dp_frame_rx.vhd | 133 +-
.../base/dp/src/vhdl/dp_frame_scheduler.vhd | 78 +-
.../base/dp/src/vhdl/dp_frame_status.vhd | 50 +-
libraries/base/dp/src/vhdl/dp_frame_tx.vhd | 88 +-
libraries/base/dp/src/vhdl/dp_gap.vhd | 84 +-
libraries/base/dp/src/vhdl/dp_hdr_insert.vhd | 74 +-
libraries/base/dp/src/vhdl/dp_hdr_remove.vhd | 66 +-
libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd | 42 +-
libraries/base/dp/src/vhdl/dp_hold_data.vhd | 24 +-
libraries/base/dp/src/vhdl/dp_hold_input.vhd | 118 +-
.../dp/src/vhdl/dp_interleave_n_to_one.vhd | 116 +-
.../base/dp/src/vhdl/dp_latency_adapter.vhd | 104 +-
.../base/dp/src/vhdl/dp_latency_fifo.vhd | 66 +-
.../base/dp/src/vhdl/dp_latency_increase.vhd | 40 +-
libraries/base/dp/src/vhdl/dp_loopback.vhd | 192 +-
libraries/base/dp/src/vhdl/dp_mon.vhd | 32 +-
libraries/base/dp/src/vhdl/dp_mux.vhd | 110 +-
libraries/base/dp/src/vhdl/dp_offload_rx.vhd | 134 +-
.../base/dp/src/vhdl/dp_offload_rx_filter.vhd | 18 +-
.../dp/src/vhdl/dp_offload_rx_filter_mm.vhd | 144 +-
.../base/dp/src/vhdl/dp_offload_rx_legacy.vhd | 102 +-
libraries/base/dp/src/vhdl/dp_offload_tx.vhd | 244 +-
.../base/dp/src/vhdl/dp_offload_tx_legacy.vhd | 320 +-
.../dp/src/vhdl/dp_offload_tx_len_calc.vhd | 118 +-
.../base/dp/src/vhdl/dp_offload_tx_v3.vhd | 138 +-
libraries/base/dp/src/vhdl/dp_packet_dec.vhd | 168 +-
.../dp/src/vhdl/dp_packet_dec_channel_lo.vhd | 30 +-
.../base/dp/src/vhdl/dp_packet_detect.vhd | 32 +-
libraries/base/dp/src/vhdl/dp_packet_enc.vhd | 122 +-
.../dp/src/vhdl/dp_packet_enc_channel_lo.vhd | 52 +-
.../base/dp/src/vhdl/dp_packet_merge.vhd | 36 +-
libraries/base/dp/src/vhdl/dp_packet_pkg.vhd | 8 +-
.../base/dp/src/vhdl/dp_packet_unmerge.vhd | 8 +-
.../base/dp/src/vhdl/dp_packetizing_pkg.vhd | 64 +-
libraries/base/dp/src/vhdl/dp_pad_insert.vhd | 88 +-
libraries/base/dp/src/vhdl/dp_pad_remove.vhd | 52 +-
.../base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd | 118 +-
libraries/base/dp/src/vhdl/dp_pipeline.vhd | 98 +-
.../base/dp/src/vhdl/dp_pipeline_arr.vhd | 38 +-
.../base/dp/src/vhdl/dp_pipeline_ready.vhd | 170 +-
libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd | 76 +-
.../base/dp/src/vhdl/dp_ram_from_mm_reg.vhd | 37 +-
libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd | 76 +-
libraries/base/dp/src/vhdl/dp_ready.vhd | 18 +-
.../base/dp/src/vhdl/dp_reinterleave.vhd | 152 +-
libraries/base/dp/src/vhdl/dp_repack.vhd | 46 +-
libraries/base/dp/src/vhdl/dp_repack_data.vhd | 104 +-
.../base/dp/src/vhdl/dp_repack_legacy.vhd | 46 +-
libraries/base/dp/src/vhdl/dp_requantize.vhd | 160 +-
.../base/dp/src/vhdl/dp_reverse_n_data.vhd | 116 +-
.../base/dp/src/vhdl/dp_reverse_n_data_fc.vhd | 90 +-
libraries/base/dp/src/vhdl/dp_rsn_source.vhd | 18 +-
libraries/base/dp/src/vhdl/dp_selector.vhd | 42 +-
.../base/dp/src/vhdl/dp_selector_arr.vhd | 82 +-
libraries/base/dp/src/vhdl/dp_shiftram.vhd | 96 +-
libraries/base/dp/src/vhdl/dp_shiftreg.vhd | 72 +-
libraries/base/dp/src/vhdl/dp_split.vhd | 130 +-
libraries/base/dp/src/vhdl/dp_split_reg.vhd | 37 +-
.../base/dp/src/vhdl/dp_src_out_timer.vhd | 30 +-
libraries/base/dp/src/vhdl/dp_stream_pkg.vhd | 143 +-
.../dp/src/vhdl/dp_strobe_total_count.vhd | 115 +-
libraries/base/dp/src/vhdl/dp_switch.vhd | 116 +-
.../base/dp/src/vhdl/dp_sync_checker.vhd | 62 +-
libraries/base/dp/src/vhdl/dp_sync_insert.vhd | 8 +-
.../base/dp/src/vhdl/dp_sync_insert_v2.vhd | 56 +-
.../base/dp/src/vhdl/dp_sync_recover.vhd | 10 +-
libraries/base/dp/src/vhdl/dp_tail_remove.vhd | 50 +-
libraries/base/dp/src/vhdl/dp_throttle.vhd | 36 +-
.../base/dp/src/vhdl/dp_throttle_reg.vhd | 39 +-
.../base/dp/src/vhdl/dp_throttle_sop.vhd | 52 +-
.../base/dp/src/vhdl/dp_throttle_xon.vhd | 6 +-
libraries/base/dp/src/vhdl/dp_unfolder.vhd | 116 +-
libraries/base/dp/src/vhdl/dp_unframe.vhd | 68 +-
libraries/base/dp/src/vhdl/dp_validate.vhd | 26 +-
.../dp/src/vhdl/dp_wideband_sp_arr_scope.vhd | 8 +-
.../dp/src/vhdl/dp_wideband_wb_arr_scope.vhd | 6 +-
libraries/base/dp/src/vhdl/dp_xonoff.vhd | 6 +-
libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd | 37 +-
.../dp/src/vhdl/dp_xonoff_reg_timeout.vhd | 59 +-
.../base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd | 210 +-
.../dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd | 130 +-
.../vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd | 68 +-
.../base/dp/src/vhdl/mms_dp_block_select.vhd | 79 +-
.../base/dp/src/vhdl/mms_dp_bsn_align.vhd | 92 +-
.../base/dp/src/vhdl/mms_dp_bsn_monitor.vhd | 154 +-
.../dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd | 142 +-
.../base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd | 70 +-
.../base/dp/src/vhdl/mms_dp_bsn_source.vhd | 86 +-
.../base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd | 94 +-
.../base/dp/src/vhdl/mms_dp_fifo_fill.vhd | 118 +-
.../base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd | 50 +-
.../base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd | 50 +-
.../src/vhdl/mms_dp_force_data_parallel.vhd | 110 +-
.../vhdl/mms_dp_force_data_parallel_arr.vhd | 86 +-
.../dp/src/vhdl/mms_dp_force_data_serial.vhd | 104 +-
.../src/vhdl/mms_dp_force_data_serial_arr.vhd | 68 +-
libraries/base/dp/src/vhdl/mms_dp_gain.vhd | 88 +-
.../base/dp/src/vhdl/mms_dp_gain_arr.vhd | 220 +-
.../base/dp/src/vhdl/mms_dp_gain_serial.vhd | 82 +-
.../dp/src/vhdl/mms_dp_gain_serial_arr.vhd | 277 +-
.../base/dp/src/vhdl/mms_dp_packet_merge.vhd | 80 +-
.../base/dp/src/vhdl/mms_dp_ram_from_mm.vhd | 68 +-
libraries/base/dp/src/vhdl/mms_dp_scale.vhd | 98 +-
libraries/base/dp/src/vhdl/mms_dp_split.vhd | 94 +-
.../base/dp/src/vhdl/mms_dp_sync_checker.vhd | 97 +-
.../dp/src/vhdl/mms_dp_sync_checker_arr.vhd | 68 +-
.../base/dp/src/vhdl/mms_dp_throttle.vhd | 58 +-
libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd | 130 +-
libraries/base/dp/tb/vhdl/dp_phy_link.vhd | 24 +-
.../base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd | 18 +-
.../base/dp/tb/vhdl/dp_sosi_recorder.vhd | 52 +-
libraries/base/dp/tb/vhdl/dp_statistics.vhd | 16 +-
.../base/dp/tb/vhdl/dp_stream_player.vhd | 26 +-
.../base/dp/tb/vhdl/dp_stream_rec_play.vhd | 58 +-
.../base/dp/tb/vhdl/dp_stream_stimuli.vhd | 22 +-
.../base/dp/tb/vhdl/dp_stream_verify.vhd | 14 +-
libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd | 104 +-
libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd | 136 +-
libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd | 52 +-
libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd | 58 +-
.../base/dp/tb/vhdl/tb_dp_block_from_mm.vhd | 128 +-
libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd | 58 +-
.../dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd | 132 +-
.../base/dp/tb/vhdl/tb_dp_block_reshape.vhd | 144 +-
.../dp/tb/vhdl/tb_dp_block_reshape_sync.vhd | 170 +-
.../base/dp/tb/vhdl/tb_dp_block_select.vhd | 114 +-
.../vhdl/tb_dp_block_validate_bsn_at_sync.vhd | 160 +-
.../tb/vhdl/tb_dp_block_validate_channel.vhd | 110 +-
.../dp/tb/vhdl/tb_dp_block_validate_err.vhd | 154 +-
.../tb/vhdl/tb_dp_block_validate_length.vhd | 112 +-
libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd | 62 +-
.../base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd | 74 +-
.../base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd | 68 +-
.../base/dp/tb/vhdl/tb_dp_bsn_source.vhd | 44 +-
.../base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd | 80 +-
.../base/dp/tb/vhdl/tb_dp_calculate_crc.vhd | 80 +-
libraries/base/dp/tb/vhdl/tb_dp_concat.vhd | 36 +-
.../dp/tb/vhdl/tb_dp_concat_field_blk.vhd | 323 +-
libraries/base/dp/tb/vhdl/tb_dp_counter.vhd | 70 +-
.../base/dp/tb/vhdl/tb_dp_counter_offset.vhd | 72 +-
.../base/dp/tb/vhdl/tb_dp_deinterleave.vhd | 60 +-
.../tb_dp_deinterleave_interleave_to_one.vhd | 267 +-
.../tb_dp_deinterleave_one_to_n_to_one.vhd | 263 +-
libraries/base/dp/tb/vhdl/tb_dp_demux.vhd | 88 +-
.../base/dp/tb/vhdl/tb_dp_distribute.vhd | 142 +-
.../base/dp/tb/vhdl/tb_dp_example_dut.vhd | 158 +-
.../base/dp/tb/vhdl/tb_dp_example_no_dut.vhd | 14 +-
libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd | 64 +-
.../base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd | 74 +-
.../dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd | 136 +-
libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd | 58 +-
.../base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd | 72 +-
.../base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd | 64 +-
libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd | 94 +-
libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd | 62 +-
.../base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd | 166 +-
.../base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd | 210 +-
libraries/base/dp/tb/vhdl/tb_dp_flush.vhd | 48 +-
libraries/base/dp/tb/vhdl/tb_dp_folder.vhd | 62 +-
libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd | 185 +-
.../base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd | 167 +-
libraries/base/dp/tb/vhdl/tb_dp_gap.vhd | 44 +-
.../dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd | 116 +-
.../base/dp/tb/vhdl/tb_dp_latency_adapter.vhd | 38 +-
.../base/dp/tb/vhdl/tb_dp_latency_fifo.vhd | 68 +-
libraries/base/dp/tb/vhdl/tb_dp_mux.vhd | 66 +-
.../dp/tb/vhdl/tb_dp_offload_rx_filter.vhd | 147 +-
.../base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd | 562 +-
libraries/base/dp/tb/vhdl/tb_dp_packet.vhd | 70 +-
.../base/dp/tb/vhdl/tb_dp_packet_merge.vhd | 72 +-
.../base/dp/tb/vhdl/tb_dp_packetizing.vhd | 649 +-
.../dp/tb/vhdl/tb_dp_pad_insert_remove.vhd | 80 +-
libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd | 32 +-
.../base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd | 72 +-
.../base/dp/tb/vhdl/tb_dp_reinterleave.vhd | 64 +-
libraries/base/dp/tb/vhdl/tb_dp_repack.vhd | 102 +-
.../base/dp/tb/vhdl/tb_dp_repack_data.vhd | 230 +-
.../base/dp/tb/vhdl/tb_dp_repack_legacy.vhd | 244 +-
.../base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd | 244 +-
.../dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd | 215 +-
.../base/dp/tb/vhdl/tb_dp_rsn_source.vhd | 118 +-
.../base/dp/tb/vhdl/tb_dp_selector_arr.vhd | 116 +-
libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd | 68 +-
libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd | 48 +-
libraries/base/dp/tb/vhdl/tb_dp_split.vhd | 48 +-
.../dp/tb/vhdl/tb_dp_strobe_total_count.vhd | 88 +-
.../base/dp/tb/vhdl/tb_dp_sync_checker.vhd | 40 +-
.../base/dp/tb/vhdl/tb_dp_sync_insert.vhd | 42 +-
.../base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd | 54 +-
.../base/dp/tb/vhdl/tb_dp_sync_recover.vhd | 46 +-
.../base/dp/tb/vhdl/tb_dp_tail_remove.vhd | 86 +-
.../base/dp/tb/vhdl/tb_dp_throttle_sop.vhd | 64 +-
.../base/dp/tb/vhdl/tb_dp_throttle_xon.vhd | 50 +-
libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd | 34 +-
.../dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd | 36 +-
.../tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd | 102 +-
.../base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd | 86 +-
.../base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd | 196 +-
.../dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd | 234 +-
.../base/dp/tb/vhdl/tb_mms_dp_fields.vhd | 100 +-
.../base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd | 98 +-
.../tb_mms_dp_force_data_parallel_arr.vhd | 168 +-
.../vhdl/tb_mms_dp_force_data_serial_arr.vhd | 128 +-
.../base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd | 148 +-
.../dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd | 174 +-
libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd | 40 +-
.../dp/tb/vhdl/tb_mms_dp_sync_checker.vhd | 50 +-
.../base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd | 106 +-
libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd | 8 +-
libraries/base/dp/tb/vhdl/tb_tb2_dp_mux.vhd | 8 +-
libraries/base/dp/tb/vhdl/tb_tb3_dp_demux.vhd | 8 +-
libraries/base/dp/tb/vhdl/tb_tb3_dp_mux.vhd | 8 +-
.../dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd | 4 +-
.../base/dp/tb/vhdl/tb_tb_dp_block_gen.vhd | 4 +-
.../tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd | 4 +-
.../dp/tb/vhdl/tb_tb_dp_block_reshape.vhd | 6 +-
.../tb/vhdl/tb_tb_dp_block_reshape_sync.vhd | 4 +-
.../base/dp/tb/vhdl/tb_tb_dp_block_select.vhd | 22 +-
.../tb_tb_dp_block_validate_bsn_at_sync.vhd | 8 +-
.../vhdl/tb_tb_dp_block_validate_channel.vhd | 12 +-
.../tb/vhdl/tb_tb_dp_block_validate_err.vhd | 14 +-
.../vhdl/tb_tb_dp_block_validate_length.vhd | 10 +-
.../base/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd | 4 +-
.../base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd | 4 +-
.../dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd | 8 +-
.../tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd | 8 +-
.../dp/tb/vhdl/tb_tb_dp_calculate_crc.vhd | 16 +-
libraries/base/dp/tb/vhdl/tb_tb_dp_concat.vhd | 2 +-
.../dp/tb/vhdl/tb_tb_dp_concat_field_blk.vhd | 20 +-
.../base/dp/tb/vhdl/tb_tb_dp_counter.vhd | 16 +-
...b_tb_dp_deinterleave_interleave_to_one.vhd | 28 +-
.../tb_tb_dp_deinterleave_one_to_n_to_one.vhd | 36 +-
libraries/base/dp/tb/vhdl/tb_tb_dp_demux.vhd | 6 +-
.../base/dp/tb/vhdl/tb_tb_dp_distribute.vhd | 6 +-
.../base/dp/tb/vhdl/tb_tb_dp_example_dut.vhd | 16 +-
.../dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd | 14 +-
.../base/dp/tb/vhdl/tb_tb_dp_fifo_dc.vhd | 2 +-
.../base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd | 2 +-
.../tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd | 2 +-
.../base/dp/tb/vhdl/tb_tb_dp_fifo_fill.vhd | 2 +-
.../dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd | 4 +-
.../base/dp/tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd | 2 +-
.../base/dp/tb/vhdl/tb_tb_dp_fifo_info.vhd | 14 +-
.../base/dp/tb/vhdl/tb_tb_dp_fifo_sc.vhd | 2 +-
libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd | 14 +-
.../dp/tb/vhdl/tb_tb_dp_frame_scheduler.vhd | 2 +-
.../base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd | 6 +-
libraries/base/dp/tb/vhdl/tb_tb_dp_mux.vhd | 6 +-
.../dp/tb/vhdl/tb_tb_dp_offload_tx_v3.vhd | 4 +-
libraries/base/dp/tb/vhdl/tb_tb_dp_packet.vhd | 14 +-
.../base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd | 14 +-
.../base/dp/tb/vhdl/tb_tb_dp_packetizing.vhd | 2 +-
.../dp/tb/vhdl/tb_tb_dp_pad_insert_remove.vhd | 6 +-
.../base/dp/tb/vhdl/tb_tb_dp_pipeline.vhd | 6 +-
.../dp/tb/vhdl/tb_tb_dp_pipeline_ready.vhd | 8 +-
.../base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd | 18 +-
.../dp/tb/vhdl/tb_tb_dp_reverse_n_data.vhd | 20 +-
.../dp/tb/vhdl/tb_tb_dp_reverse_n_data_fc.vhd | 28 +-
.../base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd | 4 +-
libraries/base/dp/tb/vhdl/tb_tb_dp_split.vhd | 2 +-
.../tb/vhdl/tb_tb_dp_strobe_total_count.vhd | 2 +-
.../base/dp/tb/vhdl/tb_tb_dp_sync_checker.vhd | 38 +-
.../base/dp/tb/vhdl/tb_tb_dp_sync_insert.vhd | 26 +-
.../dp/tb/vhdl/tb_tb_dp_sync_insert_v2.vhd | 18 +-
.../base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd | 18 +-
.../base/dp/tb/vhdl/tb_tb_dp_throttle_xon.vhd | 22 +-
libraries/base/dp/tb/vhdl/tb_tb_dp_xonoff.vhd | 24 +-
.../dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd | 4 +-
.../tb_tb_mms_dp_force_data_parallel_arr.vhd | 32 +-
.../tb_tb_mms_dp_force_data_serial_arr.vhd | 28 +-
.../base/dp/tb/vhdl/tb_tb_mms_dp_gain_arr.vhd | 6 +-
.../tb/vhdl/tb_tb_mms_dp_gain_serial_arr.vhd | 6 +-
.../dp/tb/vhdl/tb_tb_tb_dp_backpressure.vhd | 6 +-
libraries/base/mm/src/vhdl/mm_arbiter.vhd | 158 +-
libraries/base/mm/src/vhdl/mm_bus.vhd | 72 +-
libraries/base/mm/src/vhdl/mm_bus_comb.vhd | 10 +-
libraries/base/mm/src/vhdl/mm_fields.vhd | 57 +-
.../base/mm/src/vhdl/mm_latency_adapter.vhd | 38 +-
libraries/base/mm/src/vhdl/mm_master_mux.vhd | 12 +-
libraries/base/mm/src/vhdl/mm_pipeline.vhd | 6 +-
.../base/mm/src/vhdl/mm_slave_enable.vhd | 24 +-
libraries/base/mm/src/vhdl/mm_slave_mux.vhd | 32 +-
libraries/base/mm/tb/vhdl/mm_file.vhd | 20 +-
libraries/base/mm/tb/vhdl/mm_file_pkg.vhd | 604 +-
libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd | 6 +-
.../base/mm/tb/vhdl/mm_waitrequest_model.vhd | 8 +-
libraries/base/mm/tb/vhdl/tb_mm_bus.vhd | 117 +-
libraries/base/mm/tb/vhdl/tb_mm_file.vhd | 92 +-
.../base/mm/tb/vhdl/tb_mm_master_mux.vhd | 133 +-
libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd | 4 +-
libraries/base/mm/tb/vhdl/tb_tb_mm_file.vhd | 2 +-
.../base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd | 4 +-
.../reorder/src/vhdl/mms_reorder_rewire.vhd | 78 +-
.../base/reorder/src/vhdl/reorder_col.vhd | 270 +-
.../reorder/src/vhdl/reorder_col_select.vhd | 155 +-
.../reorder/src/vhdl/reorder_col_wide.vhd | 72 +-
.../src/vhdl/reorder_col_wide_select.vhd | 48 +-
.../base/reorder/src/vhdl/reorder_matrix.vhd | 168 +-
.../base/reorder/src/vhdl/reorder_pkg.vhd | 34 +-
.../reorder/src/vhdl/reorder_retreive.vhd | 76 +-
.../base/reorder/src/vhdl/reorder_rewire.vhd | 12 +-
.../reorder/src/vhdl/reorder_rewire_reg.vhd | 65 +-
.../base/reorder/src/vhdl/reorder_row.vhd | 144 +-
.../reorder/src/vhdl/reorder_row_select.vhd | 46 +-
.../reorder/src/vhdl/reorder_sequencer.vhd | 96 +-
.../base/reorder/src/vhdl/reorder_store.vhd | 56 +-
.../reorder/src/vhdl/reorder_transpose.vhd | 318 +-
.../reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd | 253 +-
.../reorder/tb/vhdl/tb_mmf_reorder_row.vhd | 251 +-
.../reorder/tb/vhdl/tb_mms_reorder_rewire.vhd | 210 +-
.../base/reorder/tb/vhdl/tb_reorder_col.vhd | 120 +-
.../tb/vhdl/tb_reorder_col_select_all.vhd | 268 +-
.../reorder/tb/vhdl/tb_reorder_col_wide.vhd | 76 +-
.../vhdl/tb_reorder_col_wide_row_select.vhd | 124 +-
.../reorder/tb/vhdl/tb_reorder_transpose.vhd | 478 +-
.../reorder/tb/vhdl/tb_tb_reorder_col.vhd | 2 +-
.../tb/vhdl/tb_tb_reorder_col_select_all.vhd | 20 +-
.../tb_tb_reorder_col_wide_row_select.vhd | 2 +-
libraries/base/ring/src/vhdl/ring_info.vhd | 38 +-
libraries/base/ring/src/vhdl/ring_lane.vhd | 158 +-
.../base/ring/src/vhdl/ring_lane_info.vhd | 30 +-
.../base/ring/src/vhdl/ring_lane_info_reg.vhd | 40 +-
libraries/base/ring/src/vhdl/ring_mux.vhd | 60 +-
libraries/base/ring/src/vhdl/ring_pkg.vhd | 68 +-
libraries/base/ring/src/vhdl/ring_rx.vhd | 196 +-
libraries/base/ring/src/vhdl/ring_tx.vhd | 154 +-
.../base/ring/tb/vhdl/tb_ring_lane_info.vhd | 12 +-
libraries/base/sens/src/vhdl/sens.vhd | 78 +-
libraries/base/sens/src/vhdl/sens_ctrl.vhd | 22 +-
libraries/base/sens/tb/vhdl/tb_sens.vhd | 136 +-
libraries/base/ss/src/vhdl/ss.vhd | 276 +-
libraries/base/ss/src/vhdl/ss_parallel.vhd | 176 +-
libraries/base/ss/src/vhdl/ss_reorder.vhd | 142 +-
libraries/base/ss/src/vhdl/ss_retrieve.vhd | 70 +-
libraries/base/ss/src/vhdl/ss_store.vhd | 44 +-
libraries/base/ss/src/vhdl/ss_wide.vhd | 76 +-
.../base/ss/tb/vhdl/tb_mmf_ss_parallel.vhd | 253 +-
.../base/ss/tb/vhdl/tb_mmf_ss_reorder.vhd | 251 +-
libraries/base/ss/tb/vhdl/tb_ss.vhd | 120 +-
libraries/base/ss/tb/vhdl/tb_ss_wide.vhd | 76 +-
libraries/base/ss/tb/vhdl/tb_tb_ss.vhd | 2 +-
libraries/base/uth/src/vhdl/uth_pkg.vhd | 12 +-
libraries/base/uth/src/vhdl/uth_rx.vhd | 376 +-
libraries/base/uth/src/vhdl/uth_rx_tlen.vhd | 62 +-
.../base/uth/src/vhdl/uth_terminal_bidir.vhd | 28 +-
.../base/uth/src/vhdl/uth_terminal_rx.vhd | 210 +-
.../base/uth/src/vhdl/uth_terminal_tx.vhd | 200 +-
libraries/base/uth/src/vhdl/uth_tx.vhd | 280 +-
.../uth/tb/vhdl/tb_tb_tb_uth_regression.vhd | 2 +-
libraries/base/uth/tb/vhdl/tb_tb_uth.vhd | 8 +-
.../base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd | 8 +-
.../base/uth/tb/vhdl/tb_tb_uth_terminals.vhd | 8 +-
.../base/uth/tb/vhdl/tb_uth_terminals.vhd | 212 +-
libraries/base/util/src/vhdl/util_heater.vhd | 347 +-
.../base/util/src/vhdl/util_heater_pkg.vhd | 4 +-
libraries/base/util/src/vhdl/util_logic.vhd | 2 +-
.../base/util/tb/vhdl/tb_util_heater.vhd | 42 +-
.../dsp/beamformer/src/vhdl/beamformer.vhd | 203 +-
.../beamformer/tb/vhdl/tb_tb_beamformer.vhd | 46 +-
.../unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd | 440 +-
.../unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd | 223 +-
.../unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd | 438 +-
.../unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd | 50 +-
libraries/dsp/bf/src/vhdl/bf.vhd | 152 +-
libraries/dsp/bf/src/vhdl/bf_pkg.vhd | 6 +-
libraries/dsp/bf/src/vhdl/bf_unit.vhd | 431 +-
libraries/dsp/bf/tb/vhdl/tb_bf.vhd | 275 +-
libraries/dsp/bf/tb/vhdl/tb_bf_unit.vhd | 277 +-
.../src/vhdl/mmm_unb1_correlator.vhd | 224 +-
.../src/vhdl/unb1_correlator.vhd | 477 +-
.../tb/vhdl/tb_unb1_correlator.vhd | 10 +-
.../correlator/src/vhdl/corr_accumulator.vhd | 84 +-
.../dsp/correlator/src/vhdl/corr_adder.vhd | 90 +-
.../dsp/correlator/src/vhdl/corr_carousel.vhd | 40 +-
.../dsp/correlator/src/vhdl/corr_folder.vhd | 30 +-
.../src/vhdl/corr_folder_2arr_2.vhd | 86 +-
.../correlator/src/vhdl/corr_multiplier.vhd | 92 +-
.../src/vhdl/corr_output_framer.vhd | 76 +-
.../correlator/src/vhdl/corr_permutator.vhd | 40 +-
.../dsp/correlator/src/vhdl/corr_permutor.vhd | 106 +-
.../correlator/src/vhdl/corr_permutor_pkg.vhd | 6 +-
.../dsp/correlator/src/vhdl/corr_unfolder.vhd | 36 +-
.../src/vhdl/corr_visibility_buffer.vhd | 94 +-
.../correlator/src/vhdl/correlator_dev.vhd | 130 +-
.../correlator/tb/vhdl/tb_corr_carousel.vhd | 34 +-
.../dsp/correlator/tb/vhdl/tb_corr_folder.vhd | 10 +-
.../correlator/tb/vhdl/tb_corr_multiplier.vhd | 10 +-
.../correlator/tb/vhdl/tb_corr_permutator.vhd | 30 +-
.../correlator/tb/vhdl/tb_corr_permutor.vhd | 34 +-
.../dsp/correlator/tb/vhdl/tb_correlator.vhd | 311 +-
.../correlator/tb/vhdl/tb_correlator_dev.vhd | 112 +-
.../tb/vhdl/tb_tb_corr_accumulator.vhd | 22 +-
libraries/dsp/fft/src/vhdl/fft_lfsr.vhd | 4 +-
libraries/dsp/fft/src/vhdl/fft_pkg.vhd | 16 +-
libraries/dsp/fft/src/vhdl/fft_r2_bf_par.vhd | 362 +-
libraries/dsp/fft/src/vhdl/fft_r2_par.vhd | 512 +-
libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd | 396 +-
libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd | 256 +-
.../fft/src/vhdl/fft_reorder_sepa_pipe.vhd | 186 +-
libraries/dsp/fft/src/vhdl/fft_sepa.vhd | 62 +-
libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd | 182 +-
libraries/dsp/fft/src/vhdl/fft_switch.vhd | 56 +-
libraries/dsp/fft/src/vhdl/fft_unswitch.vhd | 56 +-
libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd | 158 +-
.../fft/src/vhdl/fft_wide_unit_control.vhd | 212 +-
.../dsp/fft/tb/vhdl/tb_fft_functions.vhd | 8 +-
libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd | 50 +-
libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd | 374 +-
.../dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd | 178 +-
libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd | 54 +-
libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd | 52 +-
libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd | 204 +-
.../fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd | 164 +-
libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd | 82 +-
libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd | 132 +-
.../dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd | 205 +-
libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2.vhd | 360 +-
.../dsp/fft/tb/vhdl/tb_mmf_fft_r2_par.vhd | 224 +-
.../dsp/fft/tb/vhdl/tb_mmf_fft_r2_pipe.vhd | 224 +-
.../dsp/fft/tb/vhdl/tb_mmf_fft_wide_unit.vhd | 263 +-
.../dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd | 72 +-
.../dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd | 72 +-
.../dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd | 134 +-
libraries/dsp/filter/src/vhdl/fil_pkg.vhd | 8 +-
.../dsp/filter/src/vhdl/fil_ppf_ctrl.vhd | 82 +-
.../dsp/filter/src/vhdl/fil_ppf_filter.vhd | 116 +-
.../dsp/filter/src/vhdl/fil_ppf_single.vhd | 188 +-
.../dsp/filter/src/vhdl/fil_ppf_wide.vhd | 70 +-
.../dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd | 179 +-
.../dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd | 181 +-
.../tb/vhdl/tb_fil_ppf_wide_file_data.vhd | 317 +-
.../filter/tb/vhdl/tb_tb_fil_ppf_single.vhd | 64 +-
.../dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide.vhd | 68 +-
.../tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd | 74 +-
.../fringe_stop/src/vhdl/fringe_stop_unit.vhd | 532 +-
.../tb/vhdl/tb_fringe_stop_unit.vhd | 147 +-
.../tb/vhdl/tb_tb_fringe_stop_unit.vhd | 28 +-
.../tb/vhdl/tb_tb_mmf_fringe_stop_unit.vhd | 10 +-
libraries/dsp/iquv/src/vhdl/iquv.vhd | 574 +-
libraries/dsp/iquv/src/vhdl/iquv_accum.vhd | 126 +-
libraries/dsp/iquv/src/vhdl/iquv_iab.vhd | 622 +-
libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd | 202 +-
libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd | 92 +-
.../dsp/iquv/tb/vhdl/tb_tb_iquv_file_data.vhd | 4 +-
.../iquv/tb/vhdl/tb_tb_iquv_iab_file_data.vhd | 4 +-
libraries/dsp/rTwoSDF/src/vhdl/rTwoBF.vhd | 44 +-
.../dsp/rTwoSDF/src/vhdl/rTwoBFStage.vhd | 172 +-
libraries/dsp/rTwoSDF/src/vhdl/rTwoOrder.vhd | 96 +-
libraries/dsp/rTwoSDF/src/vhdl/rTwoSDF.vhd | 212 +-
libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFPkg.vhd | 6 +-
.../dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd | 268 +-
.../dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd | 6 +-
.../dsp/rTwoSDF/tb/vhdl/tb_rTwoOrder.vhd | 38 +-
libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd | 98 +-
.../dsp/rTwoSDF/tb/vhdl/tb_tb_rTwoSDF.vhd | 32 +-
libraries/dsp/si/src/vhdl/si.vhd | 24 +-
libraries/dsp/si/src/vhdl/si_arr.vhd | 56 +-
libraries/dsp/si/tb/vhdl/tb_si.vhd | 34 +-
.../dsp/st/src/vhdl/mmp_st_histogram.vhd | 131 +-
libraries/dsp/st/src/vhdl/st_calc.vhd | 258 +-
libraries/dsp/st/src/vhdl/st_ctrl.vhd | 48 +-
libraries/dsp/st/src/vhdl/st_histogram.vhd | 77 +-
libraries/dsp/st/src/vhdl/st_sst.vhd | 320 +-
libraries/dsp/st/src/vhdl/st_xsq.vhd | 242 +-
libraries/dsp/st/src/vhdl/st_xsq_arr.vhd | 68 +-
libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd | 72 +-
libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd | 10 +-
libraries/dsp/st/src/vhdl/st_xst.vhd | 86 +-
libraries/dsp/st/tb/vhdl/tb_mmf_st_sst.vhd | 174 +-
.../dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd | 66 +-
libraries/dsp/st/tb/vhdl/tb_st_acc.vhd | 79 +-
libraries/dsp/st/tb/vhdl/tb_st_calc.vhd | 54 +-
libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd | 50 +-
libraries/dsp/st/tb/vhdl/tb_st_pkg.vhd | 6 +-
libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd | 72 +-
libraries/dsp/st/tb/vhdl/tb_st_xst.vhd | 117 +-
.../dsp/st/tb/vhdl/tb_tb_st_histogram.vhd | 76 +-
libraries/dsp/st/tb/vhdl/tb_tb_st_xsq.vhd | 20 +-
libraries/dsp/st/tb/vhdl/tb_tb_st_xst.vhd | 22 +-
.../dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd | 1526 ++--
.../dsp/verify_pfb/tb_verify_pfb_response.vhd | 143 +-
libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd | 146 +-
libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd | 244 +-
libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd | 248 +-
.../dsp/wpfb/tb/vhdl/tb_mmf_wpfb_unit.vhd | 409 +-
.../dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd | 427 +-
libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd | 269 +-
.../dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd | 403 +-
.../dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd | 711 +-
libraries/io/aduh/src/vhdl/aduh_dd_pkg.vhd | 10 +-
libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd | 70 +-
libraries/io/aduh/src/vhdl/aduh_monitor.vhd | 170 +-
.../io/aduh/src/vhdl/aduh_monitor_reg.vhd | 75 +-
libraries/io/aduh/src/vhdl/aduh_pll_pkg.vhd | 12 +-
libraries/io/aduh/src/vhdl/aduh_power_sum.vhd | 124 +-
libraries/io/aduh/src/vhdl/aduh_quad.vhd | 120 +-
libraries/io/aduh/src/vhdl/aduh_quad_reg.vhd | 425 +-
.../io/aduh/src/vhdl/aduh_quad_scope.vhd | 36 +-
libraries/io/aduh/src/vhdl/aduh_verify.vhd | 192 +-
.../io/aduh/src/vhdl/aduh_verify_bit.vhd | 12 +-
libraries/io/aduh/src/vhdl/lvdsh_dd.vhd | 330 +-
libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd | 554 +-
.../io/aduh/src/vhdl/lvdsh_dd_phs4_align.vhd | 208 +-
libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd | 406 +-
.../io/aduh/src/vhdl/mms_aduh_monitor.vhd | 98 +-
.../io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd | 100 +-
libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd | 192 +-
libraries/io/aduh/tb/vhdl/adc08d1020.vhd | 20 +-
libraries/io/aduh/tb/vhdl/adu_half.vhd | 98 +-
libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd | 157 +-
.../io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd | 74 +-
libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd | 182 +-
.../io/aduh/tb/vhdl/tb_aduh_power_sum.vhd | 74 +-
libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd | 142 +-
libraries/io/aduh/tb/vhdl/tb_lvdsh_dd.vhd | 94 +-
.../io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd | 110 +-
libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd | 104 +-
.../io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd | 146 +-
.../io/aduh/tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd | 2 +-
.../io/aduh/tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd | 2 +-
libraries/io/ddr/src/vhdl/io_ddr.vhd | 438 +-
.../io/ddr/src/vhdl/io_ddr_cross_domain.vhd | 78 +-
libraries/io/ddr/src/vhdl/io_ddr_driver.vhd | 38 +-
.../ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd | 12 +-
libraries/io/ddr/src/vhdl/io_ddr_reg.vhd | 21 +-
libraries/io/ddr/src/vhdl/mms_io_ddr.vhd | 196 +-
libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd | 256 +-
libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd | 224 +-
libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd | 10 +-
libraries/io/ddr3/src/vhdl/ddr3.vhd | 344 +-
libraries/io/ddr3/src/vhdl/ddr3_driver.vhd | 52 +-
.../io/ddr3/src/vhdl/ddr3_flush_ctrl.vhd | 26 +-
libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd | 286 +-
libraries/io/ddr3/src/vhdl/ddr3_reg.vhd | 117 +-
libraries/io/ddr3/src/vhdl/ddr3_seq.vhd | 162 +-
libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd | 378 +-
libraries/io/ddr3/src/vhdl/mms_ddr3.vhd | 172 +-
.../io/ddr3/src/vhdl/mms_ddr3_capture.vhd | 136 +-
libraries/io/ddr3/src/vhdl/seq_ddr3.vhd | 166 +-
libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd | 242 +-
.../io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd | 398 +-
libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd | 339 +-
libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd | 299 +-
libraries/io/epcs/src/vhdl/epcs_reg.vhd | 75 +-
libraries/io/epcs/src/vhdl/mms_epcs.vhd | 246 +-
libraries/io/epcs/tb/vhdl/tb_mms_epcs.vhd | 44 +-
.../src/vhdl/mmm_unb1_eth_10g.vhd | 166 +-
.../unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd | 808 +-
.../unb1_eth_10g/tb/vhdl/tb_unb1_eth_10g.vhd | 126 +-
libraries/io/eth/src/vhdl/avs2_eth.vhd | 74 +-
libraries/io/eth/src/vhdl/avs2_eth_coe.vhd | 8 +-
libraries/io/eth/src/vhdl/eth.vhd | 661 +-
libraries/io/eth/src/vhdl/eth_buffer.vhd | 116 +-
libraries/io/eth/src/vhdl/eth_checksum.vhd | 54 +-
libraries/io/eth/src/vhdl/eth_control.vhd | 42 +-
libraries/io/eth/src/vhdl/eth_crc_ctrl.vhd | 88 +-
libraries/io/eth/src/vhdl/eth_crc_word.vhd | 32 +-
libraries/io/eth/src/vhdl/eth_frm_discard.vhd | 6 +-
libraries/io/eth/src/vhdl/eth_hdr.vhd | 128 +-
libraries/io/eth/src/vhdl/eth_hdr_ctrl.vhd | 50 +-
libraries/io/eth/src/vhdl/eth_hdr_status.vhd | 52 +-
libraries/io/eth/src/vhdl/eth_hdr_store.vhd | 60 +-
libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd | 72 +-
.../eth/src/vhdl/eth_ip_header_checksum.vhd | 70 +-
.../io/eth/src/vhdl/eth_mm_reg_frame.vhd | 10 +-
.../io/eth/src/vhdl/eth_mm_registers.vhd | 195 +-
libraries/io/eth/src/vhdl/eth_pkg.vhd | 59 +-
libraries/io/eth/src/vhdl/eth_statistics.vhd | 68 +-
libraries/io/eth/src/vhdl/eth_stream.vhd | 146 +-
libraries/io/eth/src/vhdl/eth_stream_udp.vhd | 124 +-
libraries/io/eth/src/vhdl/eth_tester.vhd | 290 +-
libraries/io/eth/src/vhdl/eth_tester_pkg.vhd | 69 +-
libraries/io/eth/src/vhdl/eth_tester_rx.vhd | 194 +-
libraries/io/eth/src/vhdl/eth_tester_tx.vhd | 358 +-
libraries/io/eth/src/vhdl/eth_udp_channel.vhd | 8 +-
libraries/io/eth/tb/vhdl/tb_eth.vhd | 379 +-
libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd | 32 +-
libraries/io/eth/tb/vhdl/tb_eth_crc_ctrl.vhd | 40 +-
libraries/io/eth/tb/vhdl/tb_eth_hdr.vhd | 36 +-
.../eth/tb/vhdl/tb_eth_ip_header_checksum.vhd | 588 +-
.../io/eth/tb/vhdl/tb_eth_tester_pkg.vhd | 12 +-
.../io/eth/tb/vhdl/tb_eth_udp_offload.vhd | 495 +-
libraries/io/eth/tb/vhdl/tb_tb_eth.vhd | 34 +-
.../tb/vhdl/tb_tb_eth_ip_header_checksum.vhd | 4 +-
.../io/eth/tb/vhdl/tb_tb_eth_stream_udp.vhd | 34 +-
libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd | 129 +-
.../eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd | 67 +-
.../eth/tb/vhdl/tb_tb_tb_eth_regression.vhd | 2 +-
libraries/io/eth1g/src/vhdl/eth1g.vhd | 653 +-
libraries/io/eth1g/src/vhdl/eth1g_master.vhd | 399 +-
libraries/io/eth1g/src/vhdl/eth1g_mem_pkg.vhd | 302 +-
libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd | 377 +-
libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd | 30 +-
.../io/fpga_sense/src/vhdl/fpga_sense.vhd | 124 +-
libraries/io/i2c/src/vhdl/avs_i2c_master.vhd | 134 +-
libraries/io/i2c/src/vhdl/i2c_bit.vhd | 540 +-
.../io/i2c/src/vhdl/i2c_bit_scl_sense.vhd | 534 +-
libraries/io/i2c/src/vhdl/i2c_byte.vhd | 460 +-
libraries/io/i2c/src/vhdl/i2c_commander.vhd | 312 +-
.../i2c/src/vhdl/i2c_commander_aduh_pkg.vhd | 418 +-
.../io/i2c/src/vhdl/i2c_commander_ctrl.vhd | 14 +-
.../io/i2c/src/vhdl/i2c_commander_pkg.vhd | 51 +-
.../io/i2c/src/vhdl/i2c_commander_reg.vhd | 25 +-
.../src/vhdl/i2c_commander_unb2_pmbus_pkg.vhd | 245 +-
.../src/vhdl/i2c_commander_unb2_sens_pkg.vhd | 245 +-
.../i2c/src/vhdl/i2c_commander_unbh_pkg.vhd | 317 +-
libraries/io/i2c/src/vhdl/i2c_dev_adu_pkg.vhd | 30 +-
.../io/i2c/src/vhdl/i2c_dev_ltc4260_pkg.vhd | 14 +-
.../io/i2c/src/vhdl/i2c_dev_max1617_pkg.vhd | 2 +-
.../io/i2c/src/vhdl/i2c_dev_max6652_pkg.vhd | 2 +-
.../io/i2c/src/vhdl/i2c_dev_unb2_pkg.vhd | 30 +-
libraries/io/i2c/src/vhdl/i2c_dev_unb_pkg.vhd | 26 +-
libraries/io/i2c/src/vhdl/i2c_list_ctrl.vhd | 6 +-
libraries/io/i2c/src/vhdl/i2c_master.vhd | 184 +-
libraries/io/i2c/src/vhdl/i2c_mm.vhd | 204 +-
libraries/io/i2c/src/vhdl/i2c_pkg.vhd | 4 +-
libraries/io/i2c/src/vhdl/i2c_smbus.vhd | 140 +-
libraries/io/i2c/src/vhdl/i2c_smbus_pkg.vhd | 64 +-
libraries/io/i2c/src/vhdl/i2cslave.vhd | 28 +-
libraries/io/i2c/tb/vhdl/dev_ltc4260.vhd | 34 +-
libraries/io/i2c/tb/vhdl/dev_max1618.vhd | 32 +-
libraries/io/i2c/tb/vhdl/dev_max6652.vhd | 30 +-
libraries/io/i2c/tb/vhdl/dev_pca9555.vhd | 30 +-
libraries/io/i2c/tb/vhdl/dev_pmbus.vhd | 32 +-
libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd | 20 +-
.../io/i2c/tb/vhdl/tb_avs_i2c_master.vhd | 174 +-
libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd | 276 +-
libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd | 32 +-
.../io/i2c/tb/vhdl/tb_tb_i2c_commander.vhd | 2 +-
libraries/io/mac_10g/io_mac_10g.vhd | 68 +-
libraries/io/mdio/src/vhdl/avs_mdio.vhd | 110 +-
libraries/io/mdio/src/vhdl/mdio.vhd | 86 +-
libraries/io/mdio/src/vhdl/mdio_ctlr.vhd | 96 +-
libraries/io/mdio/src/vhdl/mdio_mm.vhd | 117 +-
libraries/io/mdio/src/vhdl/mdio_phy.vhd | 58 +-
libraries/io/mdio/src/vhdl/mdio_phy_reg.vhd | 81 +-
libraries/io/mdio/src/vhdl/mdio_pkg.vhd | 104 +-
.../src/vhdl/mdio_vitesse_vsc8486_pkg.vhd | 28 +-
libraries/io/mdio/tb/vhdl/mmd_slave.vhd | 16 +-
libraries/io/mdio/tb/vhdl/tb_mdio.vhd | 90 +-
libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd | 76 +-
.../io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd | 113 +-
libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd | 112 +-
libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd | 214 +-
.../io/nw_10GbE/src/vhdl/nw_arp_request.vhd | 87 +-
.../io/nw_10GbE/src/vhdl/nw_ping_response.vhd | 121 +-
libraries/io/nw_10GbE/tb/vhdl/tb_nw_10GbE.vhd | 381 +-
.../io/nw_10GbE/tb/vhdl/tb_nw_arp_request.vhd | 48 +-
.../nw_10GbE/tb/vhdl/tb_nw_ping_response.vhd | 104 +-
.../io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd | 34 +-
libraries/io/ppsh/src/vhdl/mm_ppsh.vhd | 58 +-
libraries/io/ppsh/src/vhdl/mms_ppsh.vhd | 112 +-
libraries/io/ppsh/src/vhdl/ppsh.vhd | 136 +-
libraries/io/ppsh/src/vhdl/ppsh_reg.vhd | 153 +-
libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd | 50 +-
libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd | 50 +-
libraries/io/remu/src/vhdl/mms_remu.vhd | 94 +-
libraries/io/remu/src/vhdl/remu_reg.vhd | 153 +-
libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd | 346 +-
.../src/vhdl/tr_10GbE_ip_checksum.vhd | 112 +-
.../tr_10GbE/src/vhdl/tr_10GbE_statistics.vhd | 154 +-
.../io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd | 34 +-
libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd | 340 +-
.../src/vhdl/mms_tr_nonbonded.vhd | 242 +-
.../io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd | 198 +-
.../src/vhdl/tr_nonbonded_reg.vhd | 63 +-
.../tb/vhdl/tb_tb_tr_nonbonded.vhd | 6 +-
.../tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd | 262 +-
libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd | 232 +-
libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd | 152 +-
.../io/tr_xaui/src/vhdl/tr_xaui_deframer.vhd | 102 +-
.../io/tr_xaui/src/vhdl/tr_xaui_framer.vhd | 96 +-
.../io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd | 152 +-
.../io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd | 10 +-
libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd | 132 +-
.../tr_xaui/tb/vhdl/tb_tr_xaui_deframer.vhd | 78 +-
.../io/tr_xaui/tb/vhdl/tb_tr_xaui_framer.vhd | 64 +-
.../technology/10gbase_r/sim_10gbase_r.vhd | 92 +-
.../10gbase_r/tb_tech_10gbase_r.vhd | 84 +-
.../technology/10gbase_r/tech_10gbase_r.vhd | 85 +-
.../10gbase_r/tech_10gbase_r_arria10.vhd | 10 +-
.../10gbase_r/tech_10gbase_r_arria10_e1sg.vhd | 12 +-
.../10gbase_r/tech_10gbase_r_arria10_e2sg.vhd | 12 +-
.../tech_10gbase_r_arria10_e3sge3.vhd | 12 +-
.../tech_10gbase_r_component_pkg.vhd | 2996 +++----
libraries/technology/clkbuf/tech_clkbuf.vhd | 12 +-
.../clkbuf/tech_clkbuf_component_pkg.vhd | 34 +-
libraries/technology/ddr/sim_ddr.vhd | 12 +-
libraries/technology/ddr/tech_ddr.vhd | 101 +-
libraries/technology/ddr/tech_ddr_arria10.vhd | 24 +-
.../technology/ddr/tech_ddr_arria10_e1sg.vhd | 36 +-
.../technology/ddr/tech_ddr_arria10_e2sg.vhd | 38 +-
.../ddr/tech_ddr_arria10_e3sge3.vhd | 30 +-
.../technology/ddr/tech_ddr_component_pkg.vhd | 1358 ++--
.../technology/ddr/tech_ddr_mem_model.vhd | 10 +-
.../ddr/tech_ddr_mem_model_component_pkg.vhd | 126 +-
libraries/technology/ddr/tech_ddr_pkg.vhd | 8 +-
.../technology/ddr/tech_ddr_stratixiv.vhd | 40 +-
.../technology/eth_10g/tb_tb_tech_eth_10g.vhd | 30 +-
.../technology/eth_10g/tb_tech_eth_10g.vhd | 382 +-
.../eth_10g/tb_tech_eth_10g_ppm.vhd | 70 +-
libraries/technology/eth_10g/tech_eth_10g.vhd | 420 +-
.../eth_10g/tech_eth_10g_arria10.vhd | 16 +-
.../eth_10g/tech_eth_10g_arria10_e1sg.vhd | 16 +-
.../eth_10g/tech_eth_10g_arria10_e2sg.vhd | 16 +-
.../eth_10g/tech_eth_10g_arria10_e3sge3.vhd | 16 +-
.../eth_10g/tech_eth_10g_clocks.vhd | 6 +-
.../eth_10g/tech_eth_10g_component_pkg.vhd | 416 +-
.../eth_10g/tech_eth_10g_stratixiv.vhd | 64 +-
.../fifo/tech_fifo_component_pkg.vhd | 622 +-
libraries/technology/fifo/tech_fifo_dc.vhd | 12 +-
.../fifo/tech_fifo_dc_mixed_widths.vhd | 12 +-
libraries/technology/fifo/tech_fifo_sc.vhd | 12 +-
.../flash/tech_flash_asmi_parallel.vhd | 16 +-
.../flash/tech_flash_component_pkg.vhd | 326 +-
.../flash/tech_flash_remote_update.vhd | 16 +-
.../fpga_temp_sens/tech_fpga_temp_sens.vhd | 82 +-
.../tech_fpga_temp_sens_component_pkg.vhd | 50 +-
.../tech_fpga_voltage_sens.vhd | 132 +-
.../tech_fpga_voltage_sens_component_pkg.vhd | 122 +-
.../tech_fractional_pll_clk125.vhd | 76 +-
.../tech_fractional_pll_clk200.vhd | 68 +-
.../tech_fractional_pll_component_pkg.vhd | 50 +-
.../iobuf/tech_iobuf_component_pkg.vhd | 226 +-
.../technology/iobuf/tech_iobuf_ddio_in.vhd | 12 +-
.../technology/iobuf/tech_iobuf_ddio_out.vhd | 12 +-
.../ip_arria10_complex_mult_rtl.vhd | 38 +-
.../ip_arria10_complex_mult_rtl_canonical.vhd | 8 +-
.../ip_arria10/ddio/ip_arria10_ddio_in.vhd | 16 +-
.../ip_arria10/ddio/ip_arria10_ddio_out.vhd | 16 +-
.../ddio/sim/ip_arria10_ddio_in_1.vhd | 16 +-
.../ddio/sim/ip_arria10_ddio_out_1.vhd | 16 +-
.../ddio/sim/tb_ip_arria10_ddio_1.vhd | 48 +-
.../ip_arria10/eth_10g/ip_arria10_eth_10g.vhd | 210 +-
.../ip_arria10/fifo/ip_arria10_fifo_dc.vhd | 58 +-
.../fifo/ip_arria10_fifo_dc_mixed_widths.vhd | 66 +-
.../ip_arria10/fifo/ip_arria10_fifo_sc.vhd | 14 +-
.../ip_arria10/mult/ip_arria10_mult.vhd | 36 +-
.../ip_arria10/mult/ip_arria10_mult_rtl.vhd | 16 +-
.../ip_arria10/ram/ip_arria10_ram_cr_cw.vhd | 146 +-
.../ip_arria10/ram/ip_arria10_ram_crw_crw.vhd | 188 +-
.../ram/ip_arria10_ram_crwk_crw.vhd | 158 +-
.../ip_arria10/ram/ip_arria10_ram_r_w.vhd | 128 +-
...rria10_simple_dual_port_ram_dual_clock.vhd | 30 +-
...ia10_simple_dual_port_ram_single_clock.vhd | 24 +-
..._arria10_true_dual_port_ram_dual_clock.vhd | 38 +-
.../tb_ip_arria10_tse_sgmii_gx.vhd | 575 +-
.../tb_ip_arria10_tse_sgmii_lvds.vhd | 549 +-
.../ddio/ip_arria10_e1sg_ddio_in.vhd | 16 +-
.../ddio/ip_arria10_e1sg_ddio_out.vhd | 16 +-
.../ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd | 16 +-
.../ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd | 16 +-
.../ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd | 48 +-
...tera_avalon_onchip_memory2_170_yroldmy.vhd | 168 +-
...tera_avalon_onchip_memory2_180_xymx6za.vhd | 168 +-
...g_2400_altera_emif_arch_nf_180_e37lt4i.vhd | 7184 ++++++++---------
.../ip_arria10_e1sg_ddr4_8g_2400_inst.vhd | 142 +-
.../eth_10g/ip_arria10_e1sg_eth_10g.vhd | 214 +-
.../fifo/ip_arria10_e1sg_fifo_dc.vhd | 58 +-
.../ip_arria10_e1sg_fifo_dc_mixed_widths.vhd | 66 +-
.../fifo/ip_arria10_e1sg_fifo_sc.vhd | 14 +-
.../jesd204b/ip_arria10_e1sg_jesd204b.vhd | 98 +-
...ip_arria10_e1sg_jesd204b_component_pkg.vhd | 14 +-
.../ip_arria10_e1sg_mult_add2_rtl.vhd | 18 +-
.../ip_arria10_e1sg_mult_add4_rtl.vhd | 10 +-
.../ram/ip_arria10_e1sg_ram_cr_cw.vhd | 146 +-
.../ram/ip_arria10_e1sg_ram_crw_crw.vhd | 188 +-
.../ram/ip_arria10_e1sg_ram_crwk_crw.vhd | 158 +-
.../ip_arria10_e1sg_ram_crwk_crw_inst.vhd | 62 +-
...1sg_ram_crwk_crw_ram_2port_170_qaianri.vhd | 132 +-
.../ram/ip_arria10_e1sg_ram_r_w.vhd | 128 +-
...0_e1sg_simple_dual_port_ram_dual_clock.vhd | 30 +-
...e1sg_simple_dual_port_ram_single_clock.vhd | 24 +-
...a10_e1sg_true_dual_port_ram_dual_clock.vhd | 38 +-
...sg_transceiver_reset_controller_3_inst.vhd | 70 +-
.../tb_ip_arria10_e1sg_tse_sgmii_gx.vhd | 575 +-
.../tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd | 549 +-
.../ddio/ip_arria10_e2sg_ddio_in.vhd | 16 +-
.../ddio/ip_arria10_e2sg_ddio_out.vhd | 16 +-
.../ddio/sim/ip_arria10_e2sg_ddio_in_1.vhd | 16 +-
.../ddio/sim/ip_arria10_e2sg_ddio_out_1.vhd | 16 +-
.../ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd | 48 +-
.../ip_arria10_e2sg_ddr4_8g_1600_inst.vhd | 178 +-
.../eth_10g/ip_arria10_e2sg_eth_10g.vhd | 214 +-
.../fifo/ip_arria10_e2sg_fifo_dc.vhd | 58 +-
.../ip_arria10_e2sg_fifo_dc_mixed_widths.vhd | 66 +-
.../fifo/ip_arria10_e2sg_fifo_sc.vhd | 14 +-
.../jesd204b/ip_arria10_e2sg_jesd204b.vhd | 98 +-
...ip_arria10_e2sg_jesd204b_component_pkg.vhd | 14 +-
.../ip_arria10_e2sg_mult_add2_rtl.vhd | 18 +-
.../ip_arria10_e2sg_mult_add4_rtl.vhd | 10 +-
.../ram/ip_arria10_e2sg_ram_cr_cw.vhd | 150 +-
.../ram/ip_arria10_e2sg_ram_crw_crw.vhd | 192 +-
.../ip_arria10_e2sg_ram_crw_crw_inst.vhd | 54 +-
...2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd | 122 +-
.../ram/ip_arria10_e2sg_ram_crwk_crw.vhd | 158 +-
.../ram/ip_arria10_e2sg_ram_r_w.vhd | 128 +-
...0_e2sg_simple_dual_port_ram_dual_clock.vhd | 30 +-
...e2sg_simple_dual_port_ram_single_clock.vhd | 24 +-
...a10_e2sg_true_dual_port_ram_dual_clock.vhd | 38 +-
.../tb_ip_arria10_e2sg_tse_sgmii_gx.vhd | 575 +-
.../tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd | 549 +-
.../ddio/ip_arria10_e3sge3_ddio_in.vhd | 16 +-
.../ddio/ip_arria10_e3sge3_ddio_out.vhd | 16 +-
.../ddio/sim/ip_arria10_e3sge3_ddio_in_1.vhd | 16 +-
.../ddio/sim/ip_arria10_e3sge3_ddio_out_1.vhd | 16 +-
.../ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd | 48 +-
.../eth_10g/ip_arria10_e3sge3_eth_10g.vhd | 214 +-
.../fifo/ip_arria10_e3sge3_fifo_dc.vhd | 58 +-
...ip_arria10_e3sge3_fifo_dc_mixed_widths.vhd | 66 +-
.../fifo/ip_arria10_e3sge3_fifo_sc.vhd | 14 +-
.../ip_arria10_e3sge3_mult_add4_rtl.vhd | 10 +-
.../ram/ip_arria10_e3sge3_ram_cr_cw.vhd | 146 +-
.../ram/ip_arria10_e3sge3_ram_crw_crw.vhd | 188 +-
.../ram/ip_arria10_e3sge3_ram_crwk_crw.vhd | 158 +-
.../ram/ip_arria10_e3sge3_ram_r_w.vhd | 128 +-
...e3sge3_simple_dual_port_ram_dual_clock.vhd | 30 +-
...sge3_simple_dual_port_ram_single_clock.vhd | 24 +-
...0_e3sge3_true_dual_port_ram_dual_clock.vhd | 38 +-
.../tb_ip_arria10_e3sge3_tse_sgmii_gx.vhd | 575 +-
.../tb_ip_arria10_e3sge3_tse_sgmii_lvds.vhd | 549 +-
.../ddio/ip_stratixiv_ddio_in.vhd | 4 +-
.../ddio/ip_stratixiv_ddio_out.vhd | 42 +-
.../eth_10g/ip_stratixiv_eth_10g.vhd | 150 +-
.../mult/ip_stratixiv_complex_mult_rtl.vhd | 48 +-
.../ip_stratixiv/mult/ip_stratixiv_mult.vhd | 24 +-
.../mult/ip_stratixiv_mult_add2_rtl.vhd | 18 +-
.../mult/ip_stratixiv_mult_add4_rtl.vhd | 10 +-
.../mult/ip_stratixiv_mult_rtl.vhd | 16 +-
.../phy_xaui/tb_ip_stratixiv_phy_xaui_ppm.vhd | 46 +-
.../ip_stratixiv_gxb_reconfig_v101.vhd | 40 +-
.../ip_stratixiv_gxb_reconfig_v111.vhd | 28 +-
.../ip_stratixiv_gxb_reconfig_v91.vhd | 50 +-
.../tb_ip_stratixiv_tse_sgmii_lvds.vhd | 541 +-
.../fifo/ip_ultrascale_fifo_dc.vhd | 244 +-
.../ip_ultrascale_fifo_dc_mixed_widths.vhd | 244 +-
.../fifo/ip_ultrascale_fifo_sc.vhd | 236 +-
.../ram/ip_ultrascale_ram_cr_cw.vhd | 192 +-
.../ram/ip_ultrascale_ram_crw_crw.vhd | 266 +-
.../technology/jesd204b/tech_jesd204b.vhd | 134 +-
.../jesd204b/tech_jesd204b_arria10_e1sg.vhd | 14 +-
.../jesd204b/tech_jesd204b_arria10_e2sg.vhd | 14 +-
.../jesd204b/tech_jesd204b_component_pkg.vhd | 334 +-
.../technology/jesd204b/tech_jesd204b_pkg.vhd | 2 +-
.../technology/jesd204b/tech_jesd204b_tx.vhd | 8 +-
.../technology/mac_10g/tb_tb_tech_mac_10g.vhd | 18 +-
.../technology/mac_10g/tb_tech_mac_10g.vhd | 234 +-
.../mac_10g/tb_tech_mac_10g_link_connect.vhd | 6 +-
.../mac_10g/tb_tech_mac_10g_pkg.vhd | 646 +-
.../mac_10g/tb_tech_mac_10g_receiver.vhd | 12 +-
.../mac_10g/tb_tech_mac_10g_setup.vhd | 24 +-
.../tb_tech_mac_10g_simulation_end.vhd | 6 +-
.../mac_10g/tb_tech_mac_10g_transmitter.vhd | 16 +-
.../tb_tech_mac_10g_verify_rx_at_eop.vhd | 12 +-
.../tb_tech_mac_10g_verify_rx_pkt_cnt.vhd | 4 +-
libraries/technology/mac_10g/tech_mac_10g.vhd | 189 +-
.../mac_10g/tech_mac_10g_arria10.vhd | 14 +-
.../mac_10g/tech_mac_10g_arria10_e1sg.vhd | 14 +-
.../mac_10g/tech_mac_10g_arria10_e2sg.vhd | 14 +-
.../mac_10g/tech_mac_10g_arria10_e3sge3.vhd | 14 +-
.../mac_10g/tech_mac_10g_component_pkg.vhd | 420 +-
.../mac_10g/tech_mac_10g_stratixiv.vhd | 14 +-
.../memory/tech_memory_component_pkg.vhd | 642 +-
.../memory/tech_memory_ram_cr_cw.vhd | 30 +-
.../memory/tech_memory_ram_crw_crw.vhd | 40 +-
.../memory/tech_memory_ram_crwk_crw.vhd | 40 +-
.../technology/memory/tech_memory_ram_r_w.vhd | 12 +-
.../technology/memory/tech_memory_rom_r.vhd | 12 +-
.../technology/mult/tech_complex_mult.vhd | 28 +-
libraries/technology/mult/tech_mult.vhd | 16 +-
libraries/technology/mult/tech_mult_add2.vhd | 12 +-
libraries/technology/mult/tech_mult_add4.vhd | 12 +-
.../mult/tech_mult_component_pkg.vhd | 680 +-
libraries/technology/mult/tech_mult_pkg.vhd | 4 +-
libraries/technology/pll/tech_pll_clk125.vhd | 12 +-
libraries/technology/pll/tech_pll_clk200.vhd | 12 +-
.../technology/pll/tech_pll_clk200_p6.vhd | 49 +-
libraries/technology/pll/tech_pll_clk25.vhd | 12 +-
.../technology/pll/tech_pll_component_pkg.vhd | 240 +-
.../pll/tech_pll_xgmii_mac_clocks.vhd | 50 +-
libraries/technology/technology_pkg.vhd | 56 +-
.../technology/technology_select_pkg.vhd | 4 +-
.../technology/technology_select_pkg_unb1.vhd | 4 +-
.../technology_select_pkg_unb2b.vhd | 4 +-
.../technology_select_pkg_unb2c.vhd | 4 +-
.../sim_transceiver_deserializer.vhd | 4 +-
.../transceiver/sim_transceiver_gx.vhd | 92 +-
.../sim_transceiver_serializer.vhd | 4 +-
.../transceiver/tb_sim_transceiver_serdes.vhd | 60 +-
.../tech_transceiver_arria10_1.vhd | 152 +-
.../tech_transceiver_arria10_48.vhd | 158 +-
.../tech_transceiver_component_pkg.vhd | 222 +-
.../transceiver/tech_transceiver_gx.vhd | 16 +-
.../tech_transceiver_gx_stratixiv.vhd | 180 +-
.../transceiver/tech_transceiver_rx_align.vhd | 30 +-
.../transceiver/tech_transceiver_rx_order.vhd | 4 +-
.../transceiver/tech_transceiver_rx_rst.vhd | 28 +-
.../transceiver/tech_transceiver_tx_align.vhd | 12 +-
.../transceiver/tech_transceiver_tx_rst.vhd | 28 +-
libraries/technology/tse/sim_tse.vhd | 164 +-
libraries/technology/tse/tb_tb_tech_tse.vhd | 22 +-
libraries/technology/tse/tb_tech_tse.vhd | 109 +-
libraries/technology/tse/tb_tech_tse_pkg.vhd | 700 +-
.../technology/tse/tb_tech_tse_with_setup.vhd | 104 +-
libraries/technology/tse/tech_tse.vhd | 206 +-
libraries/technology/tse/tech_tse_arria10.vhd | 64 +-
.../technology/tse/tech_tse_arria10_e1sg.vhd | 64 +-
.../technology/tse/tech_tse_arria10_e2sg.vhd | 64 +-
.../tse/tech_tse_arria10_e3sge3.vhd | 64 +-
.../technology/tse/tech_tse_component_pkg.vhd | 1044 +--
libraries/technology/tse/tech_tse_pkg.vhd | 12 +-
libraries/technology/tse/tech_tse_setup.vhd | 26 +-
.../technology/tse/tech_tse_stratixiv.vhd | 72 +-
.../technology/tse/tech_tse_with_setup.vhd | 146 +-
libraries/technology/xaui/sim_xaui.vhd | 110 +-
libraries/technology/xaui/tech_xaui.vhd | 34 +-
.../technology/xaui/tech_xaui_align_dly.vhd | 30 +-
.../xaui/tech_xaui_component_pkg.vhd | 376 +-
.../technology/xaui/tech_xaui_stratixiv.vhd | 236 +-
1969 files changed, 128072 insertions(+), 126207 deletions(-)
diff --git a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
index 7e61500080..e947115249 100644
--- a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
+++ b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
@@ -30,11 +30,11 @@
-- that occurs due to shared complex FFT and seperate in PFT_MODE_REAL2.
library IEEE, common_lib, dp_lib, pfs_lib, pft2_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use pfs_lib.pfs_pkg.all;
-use pft2_lib.pft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use pfs_lib.pfs_pkg.all;
+ use pft2_lib.pft_pkg.all;
entity pfb2 is
generic (
@@ -88,27 +88,27 @@ begin
gen_pfs : if g_pfs_bypass = false generate
u_pfs : entity pfs_lib.pfs
- generic map (
- g_nof_bands => g_nof_points,
- g_nof_taps => c_nof_coeffs,
- g_in_dat_w => g_pfs_in_dat_w,
- g_out_dat_w => g_pfs_out_dat_w,
- g_coef_dat_w => g_pfs_coef_dat_w,
- g_coefs_file => g_pfs_coefs_file
- )
- port map (
- in_dat_x => pfs_in_dat_x,
- in_dat_y => pfs_in_dat_y,
- in_val => pfs_in_val,
- in_sync => pfs_in_sync,
- out_dat_x => fil_out_dat_x,
- out_dat_y => fil_out_dat_y,
- out_val => fil_out_val,
- out_sync => fil_out_sync,
- clk => dp_clk,
- rst => dp_rst,
- restart => '0'
- );
+ generic map (
+ g_nof_bands => g_nof_points,
+ g_nof_taps => c_nof_coeffs,
+ g_in_dat_w => g_pfs_in_dat_w,
+ g_out_dat_w => g_pfs_out_dat_w,
+ g_coef_dat_w => g_pfs_coef_dat_w,
+ g_coefs_file => g_pfs_coefs_file
+ )
+ port map (
+ in_dat_x => pfs_in_dat_x,
+ in_dat_y => pfs_in_dat_y,
+ in_val => pfs_in_val,
+ in_sync => pfs_in_sync,
+ out_dat_x => fil_out_dat_x,
+ out_dat_y => fil_out_dat_y,
+ out_val => fil_out_val,
+ out_sync => fil_out_sync,
+ clk => dp_clk,
+ rst => dp_rst,
+ restart => '0'
+ );
end generate;
no_pfs : if g_pfs_bypass = true generate
@@ -124,26 +124,26 @@ begin
fil_sosi.sync <= fil_out_sync;
u_pft : entity pft2_lib.pft
- generic map (
- g_fft_size_w => ceil_log2(g_nof_points),
- g_in_dat_w => g_pfs_out_dat_w,
- g_out_dat_w => g_pft_out_dat_w,
- g_stage_dat_w => g_pft_stage_dat_w,
- g_mode => PFT_MODE_REAL2
- )
- port map (
- in_re => fil_out_dat_x,
- in_im => fil_out_dat_y,
- in_val => fil_out_val,
- in_sync => fil_out_sync,
- switch_en => g_pft_switch_en,
- out_re => pft_out_dat_re,
- out_im => pft_out_dat_im,
- out_val => pft_out_val,
- out_sync => pft_out_sync,
- clk => dp_clk,
- rst => dp_rst
- );
+ generic map (
+ g_fft_size_w => ceil_log2(g_nof_points),
+ g_in_dat_w => g_pfs_out_dat_w,
+ g_out_dat_w => g_pft_out_dat_w,
+ g_stage_dat_w => g_pft_stage_dat_w,
+ g_mode => PFT_MODE_REAL2
+ )
+ port map (
+ in_re => fil_out_dat_x,
+ in_im => fil_out_dat_y,
+ in_val => fil_out_val,
+ in_sync => fil_out_sync,
+ switch_en => g_pft_switch_en,
+ out_re => pft_out_dat_re,
+ out_im => pft_out_dat_im,
+ out_val => pft_out_val,
+ out_sync => pft_out_sync,
+ clk => dp_clk,
+ rst => dp_rst
+ );
-- Delay pft sync with respect pft data to fit DP sync timing
out_sosi.re <= RESIZE_DP_DSP_DATA(pft_out_dat_re);
diff --git a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
index 424b49e6e6..5181960682 100644
--- a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
+++ b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
@@ -29,12 +29,12 @@
-- Remark:
library IEEE, common_lib, dp_lib, pfs_lib, pft2_lib, st_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use pfs_lib.pfs_pkg.all;
-use pft2_lib.pft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use pfs_lib.pfs_pkg.all;
+ use pft2_lib.pft_pkg.all;
entity pfb2_unit is
generic (
@@ -85,30 +85,30 @@ begin
---------------------------------------------------------------
gen_pfb2: for I in 0 to g_nof_streams - 1 generate
u_pfb2 : entity work.pfb2
- generic map (
- g_nof_points => g_nof_points,
+ generic map (
+ g_nof_points => g_nof_points,
- -- pfs
- g_pfs_bypass => g_pfs_bypass,
- g_pfs_nof_taps => g_pfs_nof_taps,
- g_pfs_in_dat_w => g_pfs_in_dat_w,
- g_pfs_out_dat_w => g_pfs_out_dat_w,
- g_pfs_coef_dat_w => g_pfs_coef_dat_w,
- g_pfs_coefs_file => g_pfs_coefs_file,
+ -- pfs
+ g_pfs_bypass => g_pfs_bypass,
+ g_pfs_nof_taps => g_pfs_nof_taps,
+ g_pfs_in_dat_w => g_pfs_in_dat_w,
+ g_pfs_out_dat_w => g_pfs_out_dat_w,
+ g_pfs_coef_dat_w => g_pfs_coef_dat_w,
+ g_pfs_coefs_file => g_pfs_coefs_file,
- -- pft2
- g_pft_mode => g_pft_mode,
- g_pft_switch_en => g_pft_switch_en,
- g_pft_stage_dat_w => g_pft_stage_dat_w,
- g_pft_out_dat_w => g_pft_out_dat_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_sosi => in_sosi_arr(I),
- fil_sosi => fil_sosi_arr(I),
- out_sosi => pft_sosi_arr(I)
- );
+ -- pft2
+ g_pft_mode => g_pft_mode,
+ g_pft_switch_en => g_pft_switch_en,
+ g_pft_stage_dat_w => g_pft_stage_dat_w,
+ g_pft_out_dat_w => g_pft_out_dat_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_sosi => in_sosi_arr(I),
+ fil_sosi => fil_sosi_arr(I),
+ out_sosi => pft_sosi_arr(I)
+ );
end generate;
---------------------------------------------------------------
@@ -116,34 +116,34 @@ begin
---------------------------------------------------------------
-- MM mux for SST
u_mem_mux_sst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(g_sst_data_sz * c_nof_stats)
- )
- port map (
- mosi => ram_st_sst_mosi,
- miso => ram_st_sst_miso,
- mosi_arr => ram_st_sst_mosi_arr,
- miso_arr => ram_st_sst_miso_arr
- );
-
- gen_sst: for I in 0 to g_nof_streams - 1 generate
- u_sst : entity st_lib.st_sst
generic map (
- g_nof_stat => c_nof_stats,
- g_in_data_w => g_pft_out_dat_w,
- g_stat_data_w => g_sst_data_w,
- g_stat_data_sz => g_sst_data_sz
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(g_sst_data_sz * c_nof_stats)
)
port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_complex => pft_sosi_arr(I),
- ram_st_sst_mosi => ram_st_sst_mosi_arr(I),
- ram_st_sst_miso => ram_st_sst_miso_arr(I)
+ mosi => ram_st_sst_mosi,
+ miso => ram_st_sst_miso,
+ mosi_arr => ram_st_sst_mosi_arr,
+ miso_arr => ram_st_sst_miso_arr
);
+
+ gen_sst: for I in 0 to g_nof_streams - 1 generate
+ u_sst : entity st_lib.st_sst
+ generic map (
+ g_nof_stat => c_nof_stats,
+ g_in_data_w => g_pft_out_dat_w,
+ g_stat_data_w => g_sst_data_w,
+ g_stat_data_sz => g_sst_data_sz
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_complex => pft_sosi_arr(I),
+ ram_st_sst_mosi => ram_st_sst_mosi_arr(I),
+ ram_st_sst_miso => ram_st_sst_miso_arr(I)
+ );
end generate;
out_sosi_arr <= pft_sosi_arr;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd
index 09cb45d5da..10d6ce5be4 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd
@@ -1,7 +1,7 @@
library IEEE, pfs_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
library common_lib;
-use common_lib.common_pkg.all;
+ use common_lib.common_pkg.all;
architecture str of pfs is
constant c_nof_bands_w : natural := ceil_log2(g_nof_bands);
@@ -18,101 +18,101 @@ architecture str of pfs is
signal coefs : std_logic_vector(g_coef_dat_w * c_nof_fir_taps - 1 downto 0);
begin
ctrl : entity pfs_lib.pfs_ctrl
- generic map (
- g_nof_bands_w => c_nof_bands_w,
- g_nof_taps => c_nof_fir_taps,
- g_nof_taps_w => c_nof_fir_taps_w,
- g_taps_w => g_in_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- restart => restart,
- in_x => in_dat_x,
- in_y => in_dat_y,
- in_val => in_val,
- in_sync => in_sync,
- taps_rdaddr => taps_rdaddr,
- taps_wraddr => taps_wraddr,
- taps_wren => taps_wren,
- taps_in_x => taps_in_x,
- taps_in_y => taps_in_y,
- taps_out_x => taps_out_x,
- taps_out_y => taps_out_y,
- out_val => out_val,
- out_sync => out_sync
- );
+ generic map (
+ g_nof_bands_w => c_nof_bands_w,
+ g_nof_taps => c_nof_fir_taps,
+ g_nof_taps_w => c_nof_fir_taps_w,
+ g_taps_w => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ restart => restart,
+ in_x => in_dat_x,
+ in_y => in_dat_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ taps_rdaddr => taps_rdaddr,
+ taps_wraddr => taps_wraddr,
+ taps_wren => taps_wren,
+ taps_in_x => taps_in_x,
+ taps_in_y => taps_in_y,
+ taps_out_x => taps_out_x,
+ taps_out_y => taps_out_y,
+ out_val => out_val,
+ out_sync => out_sync
+ );
firx : entity pfs_lib.pfs_filter
- generic map (
- g_coef_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => g_in_dat_w,
- g_nof_taps => c_nof_fir_taps
- )
- port map(
- clk => clk,
- taps => taps_out_x,
- coefs => coefs,
- result => out_dat_x
- );
+ generic map (
+ g_coef_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => g_in_dat_w,
+ g_nof_taps => c_nof_fir_taps
+ )
+ port map(
+ clk => clk,
+ taps => taps_out_x,
+ coefs => coefs,
+ result => out_dat_x
+ );
firy : entity pfs_lib.pfs_filter
- generic map (
- g_coef_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => g_in_dat_w,
- g_nof_taps => c_nof_fir_taps
- )
- port map (
- clk => clk,
- taps => taps_out_y,
- coefs => coefs,
- result => out_dat_y
- );
+ generic map (
+ g_coef_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => g_in_dat_w,
+ g_nof_taps => c_nof_fir_taps
+ )
+ port map (
+ clk => clk,
+ taps => taps_out_y,
+ coefs => coefs,
+ result => out_dat_y
+ );
tapsbufx : entity pfs_lib.pfs_tapsbuf
- generic map (
- g_data_w => g_in_dat_w * c_nof_fir_taps,
- g_nof_words => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- wrdata => taps_out_x,
- wren => taps_wren,
- wraddr => taps_wraddr,
- rdaddr => taps_rdaddr,
- rddata => taps_in_x,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w * c_nof_fir_taps,
+ g_nof_words => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ wrdata => taps_out_x,
+ wren => taps_wren,
+ wraddr => taps_wraddr,
+ rdaddr => taps_rdaddr,
+ rddata => taps_in_x,
+ clk => clk,
+ rst => rst
+ );
tapsbufy : entity pfs_lib.pfs_tapsbuf
- generic map (
- g_data_w => g_in_dat_w * c_nof_fir_taps,
- g_nof_words => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- wrdata => taps_out_y,
- wren => taps_wren,
- wraddr => taps_wraddr,
- rdaddr => taps_rdaddr,
- rddata => taps_in_y,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w * c_nof_fir_taps,
+ g_nof_words => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ wrdata => taps_out_y,
+ wren => taps_wren,
+ wraddr => taps_wraddr,
+ rdaddr => taps_rdaddr,
+ rddata => taps_in_y,
+ clk => clk,
+ rst => rst
+ );
coefsbuf : entity pfs_lib.pfs_coefsbuf
- generic map (
- g_data_w => g_coef_dat_w * c_nof_fir_taps,
- g_nof_coefs => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- addr => taps_rdaddr,
- data => coefs,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_coef_dat_w * c_nof_fir_taps,
+ g_nof_coefs => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ addr => taps_rdaddr,
+ data => coefs,
+ clk => clk,
+ rst => rst
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
index ffdeb470a0..011f76277e 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.pfs_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.pfs_pkg.all;
entity pfs is
generic (
@@ -67,102 +67,102 @@ architecture str of pfs is
signal coefs : std_logic_vector(g_coef_dat_w * c_nof_fir_taps - 1 downto 0);
begin
ctrl : entity work.pfs_ctrl
- generic map (
- g_nof_bands_w => c_nof_bands_w,
- g_nof_taps => c_nof_fir_taps,
- g_nof_taps_w => c_nof_fir_taps_w,
- g_taps_w => g_in_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- restart => restart,
- in_x => in_dat_x,
- in_y => in_dat_y,
- in_val => in_val,
- in_sync => in_sync,
- taps_rdaddr => taps_rdaddr,
- taps_wraddr => taps_wraddr,
- taps_wren => taps_wren,
- taps_in_x => taps_in_x,
- taps_in_y => taps_in_y,
- taps_out_x => taps_out_x,
- taps_out_y => taps_out_y,
- out_val => out_val,
- out_sync => out_sync
- );
+ generic map (
+ g_nof_bands_w => c_nof_bands_w,
+ g_nof_taps => c_nof_fir_taps,
+ g_nof_taps_w => c_nof_fir_taps_w,
+ g_taps_w => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ restart => restart,
+ in_x => in_dat_x,
+ in_y => in_dat_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ taps_rdaddr => taps_rdaddr,
+ taps_wraddr => taps_wraddr,
+ taps_wren => taps_wren,
+ taps_in_x => taps_in_x,
+ taps_in_y => taps_in_y,
+ taps_out_x => taps_out_x,
+ taps_out_y => taps_out_y,
+ out_val => out_val,
+ out_sync => out_sync
+ );
firx : entity work.pfs_filter
- generic map (
- g_coef_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => g_in_dat_w,
- g_nof_taps => c_nof_fir_taps
- )
- port map(
- clk => clk,
- taps => taps_out_x,
- coefs => coefs,
- result => out_dat_x
- );
+ generic map (
+ g_coef_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => g_in_dat_w,
+ g_nof_taps => c_nof_fir_taps
+ )
+ port map(
+ clk => clk,
+ taps => taps_out_x,
+ coefs => coefs,
+ result => out_dat_x
+ );
firy : entity work.pfs_filter
- generic map (
- g_coef_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => g_in_dat_w,
- g_nof_taps => c_nof_fir_taps
- )
- port map (
- clk => clk,
- taps => taps_out_y,
- coefs => coefs,
- result => out_dat_y
- );
+ generic map (
+ g_coef_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => g_in_dat_w,
+ g_nof_taps => c_nof_fir_taps
+ )
+ port map (
+ clk => clk,
+ taps => taps_out_y,
+ coefs => coefs,
+ result => out_dat_y
+ );
tapsbufx : entity work.pfs_tapsbuf
- generic map (
- g_data_w => g_in_dat_w * c_nof_fir_taps,
- g_nof_words => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- wrdata => taps_out_x,
- wren => taps_wren,
- wraddr => taps_wraddr,
- rdaddr => taps_rdaddr,
- rddata => taps_in_x,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w * c_nof_fir_taps,
+ g_nof_words => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ wrdata => taps_out_x,
+ wren => taps_wren,
+ wraddr => taps_wraddr,
+ rdaddr => taps_rdaddr,
+ rddata => taps_in_x,
+ clk => clk,
+ rst => rst
+ );
tapsbufy : entity work.pfs_tapsbuf
- generic map (
- g_data_w => g_in_dat_w * c_nof_fir_taps,
- g_nof_words => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- wrdata => taps_out_y,
- wren => taps_wren,
- wraddr => taps_wraddr,
- rdaddr => taps_rdaddr,
- rddata => taps_in_y,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w * c_nof_fir_taps,
+ g_nof_words => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ wrdata => taps_out_y,
+ wren => taps_wren,
+ wraddr => taps_wraddr,
+ rdaddr => taps_rdaddr,
+ rddata => taps_in_y,
+ clk => clk,
+ rst => rst
+ );
coefsbuf : entity work.pfs_coefsbuf
- generic map (
- g_data_w => g_coef_dat_w * c_nof_fir_taps,
- g_coefs_file => g_coefs_file,
- g_nof_coefs => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- addr => taps_rdaddr,
- data => coefs,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_coef_dat_w * c_nof_fir_taps,
+ g_coefs_file => g_coefs_file,
+ g_nof_coefs => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ addr => taps_rdaddr,
+ data => coefs,
+ clk => clk,
+ rst => rst
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
index 257754314c..dc07813b06 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
@@ -1,25 +1,26 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_mem_pkg.all;
architecture str of pfs_coefsbuf is
- constant c_coefs_rom : t_c_mem := (latency => 2,
- adr_w => g_addr_w,
- dat_w => g_data_w,
- nof_dat => g_nof_coefs, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_coefs_rom : t_c_mem := (
+ latency => 2,
+ adr_w => g_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_nof_coefs, -- <= 2**g_addr_w
+ init_sl => '0');
begin
rom : entity common_lib.common_rom
- generic map (
- g_ram => c_coefs_rom,
- g_init_file => "data/pfs_coefsbuf_1024.hex" -- Quartus .hex extension, replaced by .bin in common_rom works for XST
- --g_init_file => "data/pfs_coefsbuf_1024.bin" -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
- )
- port map (
- rst => rst,
- clk => clk,
- rd_adr => addr,
- rd_dat => data
- );
+ generic map (
+ g_ram => c_coefs_rom,
+ g_init_file => "data/pfs_coefsbuf_1024.hex" -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ --g_init_file => "data/pfs_coefsbuf_1024.bin" -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ rd_adr => addr,
+ rd_dat => data
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
index 2983acb724..ee5dda5668 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
@@ -1,30 +1,30 @@
library IEEE, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_coefsbuf is
component altsyncram
- generic (
- operation_mode : string;
- width_a : natural;
- widthad_a : natural;
- numwords_a : natural;
- lpm_type : string;
- width_byteena_a : natural;
- outdata_reg_a : string;
- outdata_aclr_a : string;
- read_during_write_mode_mixed_ports : string;
- ram_block_type : string;
- init_file : string;
- intended_device_family : string
- );
- port (
- aclr0 : in std_logic;
- clock0 : in std_logic;
- address_a : in std_logic_vector(g_addr_w - 1 downto 0);
- q_a : out std_logic_vector(g_data_w - 1 downto 0)
- );
+ generic (
+ operation_mode : string;
+ width_a : natural;
+ widthad_a : natural;
+ numwords_a : natural;
+ lpm_type : string;
+ width_byteena_a : natural;
+ outdata_reg_a : string;
+ outdata_aclr_a : string;
+ read_during_write_mode_mixed_ports : string;
+ ram_block_type : string;
+ init_file : string;
+ intended_device_family : string
+ );
+ port (
+ aclr0 : in std_logic;
+ clock0 : in std_logic;
+ address_a : in std_logic_vector(g_addr_w - 1 downto 0);
+ q_a : out std_logic_vector(g_data_w - 1 downto 0)
+ );
end component;
begin
rom : altsyncram
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
index d28621875d..e868fcc36c 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_mem_pkg.all;
entity pfs_coefsbuf is
generic (
@@ -45,21 +45,22 @@ entity pfs_coefsbuf is
end pfs_coefsbuf;
architecture str of pfs_coefsbuf is
- constant c_coefs_rom : t_c_mem := (latency => 2,
- adr_w => g_addr_w,
- dat_w => g_data_w,
- nof_dat => g_nof_coefs, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_coefs_rom : t_c_mem := (
+ latency => 2,
+ adr_w => g_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_nof_coefs, -- <= 2**g_addr_w
+ init_sl => '0');
begin
rom : entity common_lib.common_rom
- generic map (
- g_ram => c_coefs_rom,
- g_init_file => g_coefs_file
- )
- port map (
- rst => rst,
- clk => clk,
- rd_adr => addr,
- rd_dat => data
- );
+ generic map (
+ g_ram => c_coefs_rom,
+ g_init_file => g_coefs_file
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ rd_adr => addr,
+ rd_dat => data
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
index 63fc7c7347..7c53ab6707 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
architecture rtl of pfs_combine is
signal i_out_dat_x : std_logic_vector(out_dat_x'range);
@@ -32,7 +32,7 @@ begin
end process;
select_value : process (i_out_dat_x, i_out_dat_y, in_val, in_dat_x, in_dat_y,
- in_sync)
+ in_sync)
begin
nxt_out_dat_x <= i_out_dat_x;
nxt_out_dat_y <= i_out_dat_y;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
index 6c921d33b6..8868aeaf9e 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
@@ -1,5 +1,5 @@
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity pfs_combine is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd
index 315298a5ae..bf832181f6 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
architecture rtl of pfs_ctrl is
-- The number of cycles that should be waited until the result that comes out
@@ -71,7 +71,7 @@ begin
end process;
write_control : process (restart, i_taps_wraddr, taps_in_x, taps_in_y, in_x_reg, rdval,
- in_y_reg)
+ in_y_reg)
begin
nxt_taps_wraddr <= std_logic_vector(unsigned(i_taps_wraddr) + 1);
if restart = '1' then
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd
index ab0bcedb05..294ed76510 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_ctrl is
generic (
@@ -123,7 +123,7 @@ begin
end process;
write_control : process (restart, i_taps_wraddr, taps_in_x, taps_in_y, in_x_reg, rdval,
- in_y_reg)
+ in_y_reg)
begin
nxt_taps_wraddr <= std_logic_vector(unsigned(i_taps_wraddr) + 1);
if restart = '1' then
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
index c17e494eb6..18c9d207f0 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
@@ -1,7 +1,7 @@
library IEEE, common_lib, common_mult_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture rtl of pfs_filter is
type type_res is array (0 to 7) of std_logic_vector(g_coef_w + g_taps_w + 1 - 1 downto 0);
@@ -25,27 +25,27 @@ begin
end process;
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
--- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
+ -- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
gen : for i in 0 to 7 generate
--MULT_ADD : ENTITY common_lib.common_mult_add(rtl)
--MULT_ADD : ENTITY common_lib.common_mult_add(virtex)
MULT_ADD : entity common_mult_lib.common_mult_add -- rtl
- generic map (
- g_in_a_w => g_taps_w,
- g_in_b_w => g_coef_w,
- g_out_dat_w => g_coef_w + g_taps_w + 1,
- g_add_sub => "ADD",
- g_pipeline => 3
- )
- port map (
- clk => clk,
- in_a0 => taps (g_taps_w * (2 * i + 1) - 1 downto g_taps_w * 2 * i),
- in_b0 => coefs(g_coef_w * (2 * i + 1) - 1 downto g_coef_w * 2 * i),
- in_a1 => taps (g_taps_w * (2 * i + 2) - 1 downto g_taps_w * (2 * i + 1)),
- in_b1 => coefs(g_coef_w * (2 * i + 2) - 1 downto g_coef_w * (2 * i + 1)),
- out_dat => res(i)
- );
+ generic map (
+ g_in_a_w => g_taps_w,
+ g_in_b_w => g_coef_w,
+ g_out_dat_w => g_coef_w + g_taps_w + 1,
+ g_add_sub => "ADD",
+ g_pipeline => 3
+ )
+ port map (
+ clk => clk,
+ in_a0 => taps (g_taps_w * (2 * i + 1) - 1 downto g_taps_w * 2 * i),
+ in_b0 => coefs(g_coef_w * (2 * i + 1) - 1 downto g_coef_w * 2 * i),
+ in_a1 => taps (g_taps_w * (2 * i + 2) - 1 downto g_taps_w * (2 * i + 1)),
+ in_b1 => coefs(g_coef_w * (2 * i + 2) - 1 downto g_coef_w * (2 * i + 1)),
+ out_dat => res(i)
+ );
end generate;
pipe : process (clk)
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
index d551fa6227..b2548ef147 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
@@ -1,80 +1,80 @@
library IEEE, lpm, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_filter is
component altmult_add
- generic (
- input_register_b2 : string := "CLOCK0";
- input_register_a1 : string := "CLOCK0";
- multiplier_register0 : string := "CLOCK0";
- signed_pipeline_aclr_b : string := "ACLR3";
- input_register_b3 : string := "CLOCK0";
- input_register_a2 : string := "CLOCK0";
- multiplier_register1 : string := "CLOCK0";
- addnsub_multiplier_pipeline_aclr1 : string := "ACLR3";
- input_register_a3 : string := "CLOCK0";
- multiplier_register2 : string := "CLOCK0";
- signed_aclr_a : string := "ACLR3";
- signed_register_a : string := "CLOCK0";
- number_of_multipliers : natural := 4;
- multiplier_register3 : string := "CLOCK0";
- multiplier_aclr0 : string := "ACLR3";
- addnsub_multiplier_pipeline_aclr3 : string := "ACLR3";
- signed_aclr_b : string := "ACLR3";
- signed_register_b : string := "CLOCK0";
- lpm_type : string := "altmult_add";
- multiplier_aclr1 : string := "ACLR3";
- input_aclr_b0 : string := "ACLR3";
- output_register : string := "CLOCK0";
- width_result : natural := g_taps_w + g_coef_w + 2;
- representation_a : string := "SIGNED";
- signed_pipeline_register_a : string := "CLOCK0";
- input_source_b0 : string := "DATAB";
- multiplier_aclr2 : string := "ACLR3";
- input_aclr_b1 : string := "ACLR3";
- input_aclr_a0 : string := "ACLR3";
- multiplier3_direction : string := "ADD";
- addnsub_multiplier_register1 : string := "CLOCK0";
- representation_b : string := "SIGNED";
- signed_pipeline_register_b : string := "CLOCK0";
- input_source_b1 : string := "DATAB";
- input_source_a0 : string := "DATAA";
- multiplier_aclr3 : string := "ACLR3";
- input_aclr_b2 : string := "ACLR3";
- input_aclr_a1 : string := "ACLR3";
- dedicated_multiplier_circuitry : string := "YES";
- input_source_b2 : string := "DATAB";
- input_source_a1 : string := "DATAA";
- input_aclr_b3 : string := "ACLR3";
- input_aclr_a2 : string := "ACLR3";
- addnsub_multiplier_register3 : string := "CLOCK0";
- addnsub_multiplier_aclr1 : string := "ACLR3";
- output_aclr : string := "ACLR3";
- input_source_b3 : string := "DATAB";
- input_source_a2 : string := "DATAA";
- input_aclr_a3 : string := "ACLR3";
- input_source_a3 : string := "DATAA";
- addnsub_multiplier_aclr3 : string := "ACLR3";
- intended_device_family : string := "Stratix II";
- addnsub_multiplier_pipeline_register1 : string := "CLOCK0";
- width_a : natural := g_taps_w;
- input_register_b0 : string := "CLOCK0";
- width_b : natural := g_coef_w;
- input_register_b1 : string := "CLOCK0";
- input_register_a0 : string := "CLOCK0";
- addnsub_multiplier_pipeline_register3 : string := "CLOCK0";
- multiplier1_direction : string := "ADD";
- signed_pipeline_aclr_a : string := "ACLR3"
- );
- port (
- dataa : in std_logic_vector(g_taps_w * 4 - 1 downto 0);
- datab : in std_logic_vector(g_coef_w * 4 - 1 downto 0);
- clock0 : in std_logic;
- aclr3 : in std_logic;
- result : out std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0)
- );
+ generic (
+ input_register_b2 : string := "CLOCK0";
+ input_register_a1 : string := "CLOCK0";
+ multiplier_register0 : string := "CLOCK0";
+ signed_pipeline_aclr_b : string := "ACLR3";
+ input_register_b3 : string := "CLOCK0";
+ input_register_a2 : string := "CLOCK0";
+ multiplier_register1 : string := "CLOCK0";
+ addnsub_multiplier_pipeline_aclr1 : string := "ACLR3";
+ input_register_a3 : string := "CLOCK0";
+ multiplier_register2 : string := "CLOCK0";
+ signed_aclr_a : string := "ACLR3";
+ signed_register_a : string := "CLOCK0";
+ number_of_multipliers : natural := 4;
+ multiplier_register3 : string := "CLOCK0";
+ multiplier_aclr0 : string := "ACLR3";
+ addnsub_multiplier_pipeline_aclr3 : string := "ACLR3";
+ signed_aclr_b : string := "ACLR3";
+ signed_register_b : string := "CLOCK0";
+ lpm_type : string := "altmult_add";
+ multiplier_aclr1 : string := "ACLR3";
+ input_aclr_b0 : string := "ACLR3";
+ output_register : string := "CLOCK0";
+ width_result : natural := g_taps_w + g_coef_w + 2;
+ representation_a : string := "SIGNED";
+ signed_pipeline_register_a : string := "CLOCK0";
+ input_source_b0 : string := "DATAB";
+ multiplier_aclr2 : string := "ACLR3";
+ input_aclr_b1 : string := "ACLR3";
+ input_aclr_a0 : string := "ACLR3";
+ multiplier3_direction : string := "ADD";
+ addnsub_multiplier_register1 : string := "CLOCK0";
+ representation_b : string := "SIGNED";
+ signed_pipeline_register_b : string := "CLOCK0";
+ input_source_b1 : string := "DATAB";
+ input_source_a0 : string := "DATAA";
+ multiplier_aclr3 : string := "ACLR3";
+ input_aclr_b2 : string := "ACLR3";
+ input_aclr_a1 : string := "ACLR3";
+ dedicated_multiplier_circuitry : string := "YES";
+ input_source_b2 : string := "DATAB";
+ input_source_a1 : string := "DATAA";
+ input_aclr_b3 : string := "ACLR3";
+ input_aclr_a2 : string := "ACLR3";
+ addnsub_multiplier_register3 : string := "CLOCK0";
+ addnsub_multiplier_aclr1 : string := "ACLR3";
+ output_aclr : string := "ACLR3";
+ input_source_b3 : string := "DATAB";
+ input_source_a2 : string := "DATAA";
+ input_aclr_a3 : string := "ACLR3";
+ input_source_a3 : string := "DATAA";
+ addnsub_multiplier_aclr3 : string := "ACLR3";
+ intended_device_family : string := "Stratix II";
+ addnsub_multiplier_pipeline_register1 : string := "CLOCK0";
+ width_a : natural := g_taps_w;
+ input_register_b0 : string := "CLOCK0";
+ width_b : natural := g_coef_w;
+ input_register_b1 : string := "CLOCK0";
+ input_register_a0 : string := "CLOCK0";
+ addnsub_multiplier_pipeline_register3 : string := "CLOCK0";
+ multiplier1_direction : string := "ADD";
+ signed_pipeline_aclr_a : string := "ACLR3"
+ );
+ port (
+ dataa : in std_logic_vector(g_taps_w * 4 - 1 downto 0);
+ datab : in std_logic_vector(g_coef_w * 4 - 1 downto 0);
+ clock0 : in std_logic;
+ aclr3 : in std_logic;
+ result : out std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0)
+ );
end component;
signal res_0 : std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0);
@@ -99,7 +99,7 @@ begin
end process;
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
--- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
+ -- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
ALTMULT_ADD_0 : altmult_add
port map (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
index ba25c7ab38..51a600298e 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib, common_mult_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity pfs_filter is
generic (
@@ -65,27 +65,27 @@ begin
end process;
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
--- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
+ -- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
gen : for i in 0 to 7 generate
--MULT_ADD : ENTITY common_lib.common_mult_add(rtl)
--MULT_ADD : ENTITY common_lib.common_mult_add(virtex)
MULT_ADD : entity common_mult_lib.common_mult_add -- rtl
- generic map (
- g_in_a_w => g_taps_w,
- g_in_b_w => g_coef_w,
- g_out_dat_w => g_coef_w + g_taps_w + 1,
- g_add_sub => "ADD",
- g_pipeline => 3
- )
- port map (
- clk => clk,
- in_a0 => taps (g_taps_w * (2 * i + 1) - 1 downto g_taps_w * 2 * i),
- in_b0 => coefs(g_coef_w * (2 * i + 1) - 1 downto g_coef_w * 2 * i),
- in_a1 => taps (g_taps_w * (2 * i + 2) - 1 downto g_taps_w * (2 * i + 1)),
- in_b1 => coefs(g_coef_w * (2 * i + 2) - 1 downto g_coef_w * (2 * i + 1)),
- out_dat => res(i)
- );
+ generic map (
+ g_in_a_w => g_taps_w,
+ g_in_b_w => g_coef_w,
+ g_out_dat_w => g_coef_w + g_taps_w + 1,
+ g_add_sub => "ADD",
+ g_pipeline => 3
+ )
+ port map (
+ clk => clk,
+ in_a0 => taps (g_taps_w * (2 * i + 1) - 1 downto g_taps_w * 2 * i),
+ in_b0 => coefs(g_coef_w * (2 * i + 1) - 1 downto g_coef_w * 2 * i),
+ in_a1 => taps (g_taps_w * (2 * i + 2) - 1 downto g_taps_w * (2 * i + 1)),
+ in_b1 => coefs(g_coef_w * (2 * i + 2) - 1 downto g_coef_w * (2 * i + 1)),
+ out_dat => res(i)
+ );
end generate;
pipe : process (clk)
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd
index abe1bfdfcd..81e7044b5a 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd
@@ -1,7 +1,7 @@
library IEEE, pfs_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
library common_lib;
-use common_lib.common_pkg.all;
+ use common_lib.common_pkg.all;
architecture str of pfs_fir is
constant c_nof_taps_w : natural := ceil_log2(g_nof_taps);
@@ -25,138 +25,138 @@ architecture str of pfs_fir is
signal i_res_val : std_logic;
begin
ctrl : entity pfs_lib.pfs_fir_ctrl
- generic map (
- g_nof_prefilter => g_nof_prefilter,
- g_nof_prefilter_w => c_nof_prefilter_w,
- g_nof_taps => g_nof_taps,
- g_nof_taps_w => c_nof_taps_w,
- g_sample_width => g_in_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- input_hor => in_hor,
- input_ver => in_ver,
- input_val => in_val,
- input_sync => in_sync,
- coefs_addr => coefs_addr,
- coefs_rden => coefs_rden,
- sample_addr => sample_addr,
- sample_data_hor => sample_data_hor,
- sample_data_ver => sample_data_ver,
- sample_wren => sample_wren,
- taps_addr => taps_addr,
- taps_rden => taps_rden,
- res_clr => res_clr,
- result_val => i_res_val,
- result_sync => res_sync
- );
+ generic map (
+ g_nof_prefilter => g_nof_prefilter,
+ g_nof_prefilter_w => c_nof_prefilter_w,
+ g_nof_taps => g_nof_taps,
+ g_nof_taps_w => c_nof_taps_w,
+ g_sample_width => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ input_hor => in_hor,
+ input_ver => in_ver,
+ input_val => in_val,
+ input_sync => in_sync,
+ coefs_addr => coefs_addr,
+ coefs_rden => coefs_rden,
+ sample_addr => sample_addr,
+ sample_data_hor => sample_data_hor,
+ sample_data_ver => sample_data_ver,
+ sample_wren => sample_wren,
+ taps_addr => taps_addr,
+ taps_rden => taps_rden,
+ res_clr => res_clr,
+ result_val => i_res_val,
+ result_sync => res_sync
+ );
mac_hor : entity pfs_lib.pfs_fir_mac
- generic map (
- g_a_in_w => g_in_dat_w,
- g_b_in_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => c_nof_taps_w,
- g_mult_pipeline => c_mult_latency
- )
- port map (
- data_a => taps_data_hor,
- data_b => coefs_data,
- res_clr => res_clr,
- res_val => i_res_val,
- clk => clk,
- rst => rst,
- result => res_hor
- );
+ generic map (
+ g_a_in_w => g_in_dat_w,
+ g_b_in_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => c_nof_taps_w,
+ g_mult_pipeline => c_mult_latency
+ )
+ port map (
+ data_a => taps_data_hor,
+ data_b => coefs_data,
+ res_clr => res_clr,
+ res_val => i_res_val,
+ clk => clk,
+ rst => rst,
+ result => res_hor
+ );
mac_ver : entity pfs_lib.pfs_fir_mac
- generic map (
- g_a_in_w => g_in_dat_w,
- g_b_in_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => c_nof_taps_w,
- g_mult_pipeline => c_mult_latency
- )
- port map (
- data_a => taps_data_ver,
- data_b => coefs_data,
- res_clr => res_clr,
- res_val => i_res_val,
- clk => clk,
- rst => rst,
- result => res_ver
- );
-
- coefsbuf_0 : if g_fir_nr = 0 generate
- coefsbuf : entity pfs_lib.pfs_fir_coefsbuf
generic map (
- g_data_w => g_coef_dat_w,
- g_coefs_w => c_addr_w,
- g_nof_coefs => c_nof_coefs,
- g_init_file => "../../../../../EPA/pfs/src/data/pfs_fir_coeff_0_"
- & natural'image(g_nof_prefilter * g_nof_taps) & "pts.hex"
+ g_a_in_w => g_in_dat_w,
+ g_b_in_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => c_nof_taps_w,
+ g_mult_pipeline => c_mult_latency
)
port map (
- addr => coefs_addr,
- rden => coefs_rden,
- data => coefs_data,
- clk => clk,
- rst => rst
+ data_a => taps_data_ver,
+ data_b => coefs_data,
+ res_clr => res_clr,
+ res_val => i_res_val,
+ clk => clk,
+ rst => rst,
+ result => res_ver
);
+
+ coefsbuf_0 : if g_fir_nr = 0 generate
+ coefsbuf : entity pfs_lib.pfs_fir_coefsbuf
+ generic map (
+ g_data_w => g_coef_dat_w,
+ g_coefs_w => c_addr_w,
+ g_nof_coefs => c_nof_coefs,
+ g_init_file => "../../../../../EPA/pfs/src/data/pfs_fir_coeff_0_"
+ & natural'image(g_nof_prefilter * g_nof_taps) & "pts.hex"
+ )
+ port map (
+ addr => coefs_addr,
+ rden => coefs_rden,
+ data => coefs_data,
+ clk => clk,
+ rst => rst
+ );
end generate;
coefsbuf_N : if g_fir_nr > 0 generate
coefsbuf : entity pfs_lib.pfs_fir_coefsbuf
- generic map (
- g_data_w => g_coef_dat_w,
- g_coefs_w => c_addr_w,
- g_nof_coefs => c_nof_coefs,
- g_init_file => "../../../../../EPA/pfs/src/data/pfs_fir_coeff_"
+ generic map (
+ g_data_w => g_coef_dat_w,
+ g_coefs_w => c_addr_w,
+ g_nof_coefs => c_nof_coefs,
+ g_init_file => "../../../../../EPA/pfs/src/data/pfs_fir_coeff_"
& natural'image(g_fir_nr) & "_" & natural'image(g_nof_prefilter * g_nof_taps) & "pts.hex"
- )
- port map (
- addr => coefs_addr,
- rden => coefs_rden,
- data => coefs_data,
- clk => clk,
- rst => rst
- );
+ )
+ port map (
+ addr => coefs_addr,
+ rden => coefs_rden,
+ data => coefs_data,
+ clk => clk,
+ rst => rst
+ );
end generate;
tapsbuf_hor : entity pfs_lib.pfs_fir_tapsbuf
- generic map (
- g_data_w => g_in_dat_w,
- g_nof_words => c_nof_coefs,
- g_addr_w => c_addr_w
- )
- port map (
- data_a => sample_data_hor,
- wren_a => sample_wren,
- addr_a => sample_addr,
- addr_b => taps_addr,
- rden_b => taps_rden,
- data_b => taps_data_hor,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w,
+ g_nof_words => c_nof_coefs,
+ g_addr_w => c_addr_w
+ )
+ port map (
+ data_a => sample_data_hor,
+ wren_a => sample_wren,
+ addr_a => sample_addr,
+ addr_b => taps_addr,
+ rden_b => taps_rden,
+ data_b => taps_data_hor,
+ clk => clk,
+ rst => rst
+ );
tapsbuf_ver : entity pfs_lib.pfs_fir_tapsbuf
- generic map (
- g_data_w => g_in_dat_w,
- g_nof_words => c_nof_coefs,
- g_addr_w => c_addr_w
- )
- port map (
- data_a => sample_data_ver,
- wren_a => sample_wren,
- addr_a => sample_addr,
- addr_b => taps_addr,
- rden_b => taps_rden,
- data_b => taps_data_ver,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w,
+ g_nof_words => c_nof_coefs,
+ g_addr_w => c_addr_w
+ )
+ port map (
+ data_a => sample_data_ver,
+ wren_a => sample_wren,
+ addr_a => sample_addr,
+ addr_b => taps_addr,
+ rden_b => taps_rden,
+ data_b => taps_data_ver,
+ clk => clk,
+ rst => rst
+ );
res_val <= i_res_val;
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
index b0c265b36f..55cf7fe981 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
@@ -1,16 +1,16 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_fir is
generic (
g_in_dat_w : natural;
g_out_dat_w : natural;
g_coef_dat_w : natural;
--- g_nof_fir : NATURAL;
--- g_nof_subbands : NATURAL;
+ -- g_nof_fir : NATURAL;
+ -- g_nof_subbands : NATURAL;
g_nof_prefilter : natural;
--- g_nof_polarizations : NATURAL;
+ -- g_nof_polarizations : NATURAL;
g_nof_taps : natural;
g_fir_nr : natural
);
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
index 75cc60eba8..0273a8f7f6 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
@@ -1,30 +1,30 @@
library IEEE, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_fir_coefsbuf is
component altsyncram
- generic (
- operation_mode : string;
- width_a : natural;
- widthad_a : natural;
- numwords_a : natural;
- lpm_type : string;
- width_byteena_a : natural;
- outdata_reg_a : string;
- outdata_aclr_a : string;
- read_during_write_mode_mixed_ports : string;
- ram_block_type : string;
- init_file : string;
- intended_device_family : string
- );
- port (
+ generic (
+ operation_mode : string;
+ width_a : natural;
+ widthad_a : natural;
+ numwords_a : natural;
+ lpm_type : string;
+ width_byteena_a : natural;
+ outdata_reg_a : string;
+ outdata_aclr_a : string;
+ read_during_write_mode_mixed_ports : string;
+ ram_block_type : string;
+ init_file : string;
+ intended_device_family : string
+ );
+ port (
aclr0 : in std_logic;
clock0 : in std_logic;
address_a : in std_logic_vector(g_coefs_w - 1 downto 0);
q_a : out std_logic_vector(g_data_w - 1 downto 0)
- );
+ );
end component;
begin
rom : altsyncram
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
index 5bd64c7a4a..a4e2717f21 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_fir_coefsbuf is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
index 1a2fc318a9..b6d8411beb 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
architecture rtl of pfs_fir_ctrl is
-- The number of cycles that should be waited until the result that comes out
@@ -46,7 +46,7 @@ begin
-- Output signals.
result_val <= mac_res_delay(mac_res_delay'high);
result_sync <= sync_delay(sync_delay'high);
--- res_clr <= mac_res_delay(c_mac_clr_delay - 1);
+ -- res_clr <= mac_res_delay(c_mac_clr_delay - 1);
taps_addr <= i_taps_addr;
sample_data_hor <= i_sample_data_hor;
sample_data_ver <= i_sample_data_ver;
@@ -175,9 +175,9 @@ begin
if input_val = '1' then
nxt_sample_data_hor <= std_logic_vector(to_signed(
- to_integer(signed(input_hor)), i_sample_data_hor'length));
+ to_integer(signed(input_hor)), i_sample_data_hor'length));
nxt_sample_data_ver <= std_logic_vector(to_signed(
- to_integer(signed(input_ver)), i_sample_data_ver'length));
+ to_integer(signed(input_ver)), i_sample_data_ver'length));
end if;
end process;
@@ -198,12 +198,12 @@ begin
if unsigned(prefilter_cnt) = (g_nof_prefilter - 1) and last_tap = '1' then
nxt_taps_addr_base <=
- std_logic_vector(unsigned(taps_addr_base) + 1);
+ std_logic_vector(unsigned(taps_addr_base) + 1);
end if;
end process;
taps_addr_offset <= std_logic_vector(unsigned(taps_addr_base)
- + unsigned(taps_cnt));
+ + unsigned(taps_cnt));
-- The MAC delay register is used to generate a valid pulse for the MAC output
-- when the FIR calculation is done, and to generate a reset pulse to set the
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
index d3c70a8bb1..1b28c5c2b5 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
@@ -1,5 +1,5 @@
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
entity pfs_fir_ctrl is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd
index e036325cd4..5bcada560a 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd
@@ -1,47 +1,47 @@
library IEEE, lpm, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_fir_mac is
component altmult_accum
- generic (
- intended_device_family : string;
- width_a : natural;
- width_b : natural;
- representation_a : string;
- representation_b : string;
- lpm_type : string;
- width_result : natural;
- input_source_a : string;
- input_source_b : string;
- multiplier_rounding : string;
- multiplier_saturation : string;
- port_mult_is_saturated : string;
- accumulator_rounding : string;
- accumulator_saturation : string;
- port_accum_is_saturated : string;
- accum_direction : string;
- input_reg_a : string;
- input_aclr_a : string;
- input_reg_b : string;
- input_aclr_b : string;
- multiplier_reg : string;
- multiplier_aclr : string;
- accum_sload_reg : string;
- accum_sload_pipeline_reg : string;
- output_reg : string;
- output_aclr : string;
- dedicated_multiplier_circuitry : string
- );
- port (
- dataa : in std_logic_vector(width_a - 1 downto 0);
- datab : in std_logic_vector(width_b - 1 downto 0);
- accum_sload : in std_logic;
- aclr0 : in std_logic;
- clock0 : in std_logic;
- result : out std_logic_vector(width_result - 1 downto 0)
- );
+ generic (
+ intended_device_family : string;
+ width_a : natural;
+ width_b : natural;
+ representation_a : string;
+ representation_b : string;
+ lpm_type : string;
+ width_result : natural;
+ input_source_a : string;
+ input_source_b : string;
+ multiplier_rounding : string;
+ multiplier_saturation : string;
+ port_mult_is_saturated : string;
+ accumulator_rounding : string;
+ accumulator_saturation : string;
+ port_accum_is_saturated : string;
+ accum_direction : string;
+ input_reg_a : string;
+ input_aclr_a : string;
+ input_reg_b : string;
+ input_aclr_b : string;
+ multiplier_reg : string;
+ multiplier_aclr : string;
+ accum_sload_reg : string;
+ accum_sload_pipeline_reg : string;
+ output_reg : string;
+ output_aclr : string;
+ dedicated_multiplier_circuitry : string
+ );
+ port (
+ dataa : in std_logic_vector(width_a - 1 downto 0);
+ datab : in std_logic_vector(width_b - 1 downto 0);
+ accum_sload : in std_logic;
+ aclr0 : in std_logic;
+ clock0 : in std_logic;
+ result : out std_logic_vector(width_result - 1 downto 0)
+ );
end component;
-- NOTE: although it appears otherwise, bit growth in the accumulation is accounted for!
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
index a9ff53a2cc..e62ca5df44 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_fir_mac is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd
index 000968fe0e..6e8f91e504 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd
@@ -1,37 +1,37 @@
library IEEE, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_fir_tapsbuf is
component altsyncram
- generic (
- intended_device_family : string;
- operation_mode : string;
- width_a : natural;
- widthad_a : natural;
- numwords_a : natural;
- width_b : natural;
- widthad_b : natural;
- numwords_b : natural;
- lpm_type : string;
- width_byteena_a : natural;
- outdata_reg_b : string;
- address_reg_b : string;
- outdata_aclr_b : string;
- read_during_write_mode_mixed_ports : string;
- init_file : string;
- ram_block_type : string
- );
- port (
- wren_a : in std_logic;
- aclr0 : in std_logic;
- clock0 : in std_logic;
- address_a : in std_logic_vector(g_addr_w - 1 downto 0);
- address_b : in std_logic_vector(g_addr_w - 1 downto 0);
- q_b : out std_logic_vector(g_data_w - 1 downto 0);
- data_a : in std_logic_vector(g_data_w - 1 downto 0)
- );
+ generic (
+ intended_device_family : string;
+ operation_mode : string;
+ width_a : natural;
+ widthad_a : natural;
+ numwords_a : natural;
+ width_b : natural;
+ widthad_b : natural;
+ numwords_b : natural;
+ lpm_type : string;
+ width_byteena_a : natural;
+ outdata_reg_b : string;
+ address_reg_b : string;
+ outdata_aclr_b : string;
+ read_during_write_mode_mixed_ports : string;
+ init_file : string;
+ ram_block_type : string
+ );
+ port (
+ wren_a : in std_logic;
+ aclr0 : in std_logic;
+ clock0 : in std_logic;
+ address_a : in std_logic_vector(g_addr_w - 1 downto 0);
+ address_b : in std_logic_vector(g_addr_w - 1 downto 0);
+ q_b : out std_logic_vector(g_data_w - 1 downto 0);
+ data_a : in std_logic_vector(g_data_w - 1 downto 0)
+ );
end component;
begin
altsyncram_component : altsyncram
@@ -51,7 +51,7 @@ begin
outdata_aclr_b => "CLEAR0",
read_during_write_mode_mixed_ports => "DONT_CARE",
init_file => "../../../../../EPA/pfs/src/data/pfs_fir_taps_"
- & natural'image(g_nof_words) & "pts.hex",
+ & natural'image(g_nof_words) & "pts.hex",
ram_block_type => "AUTO"
)
port map (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
index 05d2564512..3f3f594777 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_fir_tapsbuf is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
index 47dcc7272d..623dd3f8e5 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
@@ -24,8 +24,8 @@
-- Remark: Use package to keep default pfs constants
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
package pfs_pkg is
constant c_pfs_coef_w : natural := 16;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
index de1f3ccf28..80f0911b7f 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
architecture rtl of pfs_rotate is
signal i_out_dat_x : std_logic_vector(out_dat_x'range);
@@ -43,7 +43,7 @@ begin
end process;
interleaver_proc : process (in_val, cnt, in_dat_x, in_dat_y, in_sync,
- i_out_dat_x, i_out_dat_y)
+ i_out_dat_x, i_out_dat_y)
begin
nxt_out_dat_x <= i_out_dat_x;
nxt_out_dat_y <= i_out_dat_y;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
index 96b25a28cd..8b2a949fef 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_rotate is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
index 5f59cf66fd..f4b5970183 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
@@ -1,28 +1,28 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use ieee.std_logic_unsigned.all;
+ use common_lib.common_pkg.all;
architecture rtl of pfs_tapsbuf is
-type RamType is array(0 to 2**g_addr_w) of std_logic_vector(g_data_w - 1 downto 0);
+ type RamType is array(0 to 2**g_addr_w) of std_logic_vector(g_data_w - 1 downto 0);
--- pfs_tapsbuf_1024.hex is empty (all zeros)
-signal RAM : RamType := (others => (others => '0'));
+ -- pfs_tapsbuf_1024.hex is empty (all zeros)
+ signal RAM : RamType := (others => (others => '0'));
-signal read_addrb : std_logic_vector(g_addr_w - 1 downto 0);
+ signal read_addrb : std_logic_vector(g_addr_w - 1 downto 0);
begin
----------------------------------------------------------------
-process (clk)
-begin
- if (clk'event and clk = '1') then
- if (wren = '1') then
- RAM (conv_integer(wraddr)) <= wrdata;
- end if;
- read_addrb <= rdaddr;
+ ---------------------------------------------------------------
+ process (clk)
+ begin
+ if (clk'event and clk = '1') then
+ if (wren = '1') then
+ RAM (conv_integer(wraddr)) <= wrdata;
+ end if;
+ read_addrb <= rdaddr;
rddata <= RAM(conv_integer(read_addrb));
- end if;
-end process;
+ end if;
+ end process;
----------------------------------------------------------------
----------------------------------------------------------------
+ ---------------------------------------------------------------
+ ---------------------------------------------------------------
end rtl;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd
index c7dcd76860..0f7f20475d 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd
@@ -1,37 +1,37 @@
library IEEE, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_tapsbuf is
component altsyncram
- generic (
- intended_device_family : string;
- operation_mode : string;
- width_a : natural;
- widthad_a : natural;
- numwords_a : natural;
- width_b : natural;
- widthad_b : natural;
- numwords_b : natural;
- lpm_type : string;
- width_byteena_a : natural;
- outdata_reg_b : string;
- address_reg_b : string;
- outdata_aclr_b : string;
- read_during_write_mode_mixed_ports : string;
- init_file : string;
- ram_block_type : string
- );
- port (
- wren_a : in std_logic;
- aclr0 : in std_logic;
- clock0 : in std_logic;
- address_a : in std_logic_vector(g_addr_w - 1 downto 0);
- address_b : in std_logic_vector(g_addr_w - 1 downto 0);
- q_b : out std_logic_vector(g_data_w - 1 downto 0);
- data_a : in std_logic_vector(g_data_w - 1 downto 0)
- );
+ generic (
+ intended_device_family : string;
+ operation_mode : string;
+ width_a : natural;
+ widthad_a : natural;
+ numwords_a : natural;
+ width_b : natural;
+ widthad_b : natural;
+ numwords_b : natural;
+ lpm_type : string;
+ width_byteena_a : natural;
+ outdata_reg_b : string;
+ address_reg_b : string;
+ outdata_aclr_b : string;
+ read_during_write_mode_mixed_ports : string;
+ init_file : string;
+ ram_block_type : string
+ );
+ port (
+ wren_a : in std_logic;
+ aclr0 : in std_logic;
+ clock0 : in std_logic;
+ address_a : in std_logic_vector(g_addr_w - 1 downto 0);
+ address_b : in std_logic_vector(g_addr_w - 1 downto 0);
+ q_b : out std_logic_vector(g_data_w - 1 downto 0);
+ data_a : in std_logic_vector(g_data_w - 1 downto 0)
+ );
end component;
begin
altsyncram_component : altsyncram
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd
index fcbf46518a..a9a24ad36d 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_unsigned.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.std_logic_unsigned.all;
entity pfs_tapsbuf is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd
index 9651e9c167..f067d35ca5 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd
@@ -1,5 +1,5 @@
library IEEE, pfs_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
architecture str of pfs_top is
signal reg_in_dat_x : std_logic_vector(g_in_dat_w - 1 downto 0);
@@ -26,24 +26,24 @@ begin
end process;
pfs : entity pfs_lib.pfs
- generic map (
- g_nof_bands => g_nof_bands,
- g_nof_taps => g_nof_taps,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_coef_dat_w => g_coef_dat_w
- )
- port map (
- in_dat_x => reg_in_dat_x,
- in_dat_y => reg_in_dat_y,
- in_val => reg_in_val,
- in_sync => reg_in_sync,
- out_dat_x => d_out_dat_x,
- out_dat_y => d_out_dat_y,
- out_val => d_out_val,
- out_sync => d_out_sync,
- clk => clk,
- rst => rst,
- restart => '0'
- );
+ generic map (
+ g_nof_bands => g_nof_bands,
+ g_nof_taps => g_nof_taps,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_coef_dat_w => g_coef_dat_w
+ )
+ port map (
+ in_dat_x => reg_in_dat_x,
+ in_dat_y => reg_in_dat_y,
+ in_val => reg_in_val,
+ in_sync => reg_in_sync,
+ out_dat_x => d_out_dat_x,
+ out_dat_y => d_out_dat_y,
+ out_val => d_out_val,
+ out_sync => d_out_sync,
+ clk => clk,
+ rst => rst,
+ restart => '0'
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd
index a69a35d77d..aad940e765 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd
@@ -1,5 +1,5 @@
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity pfs_top is
generic (
diff --git a/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd b/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
index 17cc8b6885..15634f6f29 100644
--- a/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
+++ b/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
@@ -30,10 +30,10 @@
-- . View pfs_dat_x in decimal radix and analog format (right click)
library IEEE, pfs_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_pfs is
end tb_pfs;
@@ -57,26 +57,26 @@ begin
rst <= '0' after 3 * clk_period;
pfs : entity pfs_lib.pfs
- generic map (
- g_nof_bands => 1024,
- g_nof_taps => 16 * 1024,
- g_in_dat_w => 12,
- g_out_dat_w => 18,
- g_coef_dat_w => 16
- )
- port map (
- in_dat_x => in_dat_x,
- in_dat_y => in_dat_y,
- in_val => in_val,
- in_sync => in_sync,
- out_dat_x => pfs_dat_x,
- out_dat_y => pfs_dat_y,
- out_val => pfs_val,
- out_sync => pfs_sync,
- restart => '0',
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_nof_bands => 1024,
+ g_nof_taps => 16 * 1024,
+ g_in_dat_w => 12,
+ g_out_dat_w => 18,
+ g_coef_dat_w => 16
+ )
+ port map (
+ in_dat_x => in_dat_x,
+ in_dat_y => in_dat_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_dat_x => pfs_dat_x,
+ out_dat_y => pfs_dat_y,
+ out_val => pfs_val,
+ out_sync => pfs_sync,
+ restart => '0',
+ clk => clk,
+ rst => rst
+ );
-- Keep in_dat_x high for one slice to get the filter impules response. Using amplitude 1024
-- yields the FIR coefficients, this amplitude compensates the PFS scaling of 2^4/2^14. The
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd
index 20e0854462..75e102b69c 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
package pft_pkg is
constant c_pft_stage_dat_w : natural := 20;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd
index 47cd94497c..fb9204ec56 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd
@@ -1,9 +1,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib;
-use pft2_lib.pft_pkg.all;
+ use pft2_lib.pft_pkg.all;
architecture str of pft is
function pft_dat_w ( output_w : in natural; mode : in PFT_MODE_TYPE) return natural is
@@ -77,23 +77,23 @@ begin
-- NB. The first stage has index c_nof_stages-1, the last stage has index 0.
switch: entity pft2_lib.pft_switch
- generic map (
- g_dat_w => g_in_dat_w,
- g_fft_sz_w => g_fft_size_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- in_sync => in_sync,
- in_re => in_re,
- in_im => in_im,
- switch_en => switch_en,
- out_re => switch_re,
- out_im => switch_im,
- out_val => switch_val,
- out_sync => switch_sync
- );
+ generic map (
+ g_dat_w => g_in_dat_w,
+ g_fft_sz_w => g_fft_size_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ in_sync => in_sync,
+ in_re => in_re,
+ in_im => in_im,
+ switch_en => switch_en,
+ out_re => switch_re,
+ out_im => switch_im,
+ out_val => switch_val,
+ out_sync => switch_sync
+ );
first_gen : if (c_nof_stages > 1) generate
first_stage : entity pft2_lib.pft_stage
@@ -160,23 +160,23 @@ begin
only_gen : if c_nof_stages = 1 generate
only_stage : entity pft2_lib.pft_stage
- generic map (
- g_index => 0,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_pft_dat_w
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => pft_re,
- out_im => pft_im,
- out_val => pft_val,
- out_sync => pft_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 0,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_pft_dat_w
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => pft_re,
+ out_im => pft_im,
+ out_val => pft_val,
+ out_sync => pft_sync,
+ clk => clk,
+ rst => rst
+ );
end generate;
-- In "BITREV" mode, fft output is in bit reversed order.
@@ -210,7 +210,7 @@ begin
);
end generate;
- reverse_gen : if g_mode = PFT_MODE_COMPLEX generate
+ reverse_gen : if g_mode = PFT_MODE_COMPLEX generate
reverse : entity pft2_lib.pft_reverse
generic map (
g_fft_sz => 2**g_fft_size_w,
@@ -260,65 +260,65 @@ begin
end generate;
unswitch: entity pft2_lib.pft_unswitch
- generic map (
- g_dat_w => g_out_dat_w,
- g_fft_sz_w => g_fft_size_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => sep_val,
- in_sync => sep_sync,
- in_re => sep_re,
- in_im => sep_im,
- switch_en => switch_en,
- out_re => unswitch_re,
- out_im => unswitch_im,
- out_val => unswitch_val,
- out_sync => unswitch_sync
- );
+ generic map (
+ g_dat_w => g_out_dat_w,
+ g_fft_sz_w => g_fft_size_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => sep_val,
+ in_sync => sep_sync,
+ in_re => sep_re,
+ in_im => sep_im,
+ switch_en => switch_en,
+ out_re => unswitch_re,
+ out_im => unswitch_im,
+ out_val => unswitch_val,
+ out_sync => unswitch_sync
+ );
-- calculate the power. This is intended to be used in simulations only.
-- synthesis translate_off
- determine_bin : process (clk)
- begin
- if rising_edge(clk) then
- if unswitch_val = '1' then
- bin <= std_logic_vector(unsigned(bin) + 1);
- end if;
+ determine_bin : process (clk)
+ begin
+ if rising_edge(clk) then
+ if unswitch_val = '1' then
+ bin <= std_logic_vector(unsigned(bin) + 1);
end if;
- end process;
+ end if;
+ end process;
- band <= bin(bin'high downto 1);
+ band <= bin(bin'high downto 1);
- power <= std_logic_vector( signed(unswitch_re) * signed(unswitch_re)
- + signed(unswitch_im) * signed(unswitch_im)
- ) when unswitch_val = '1' else (others => '0');
+ power <= std_logic_vector( signed(unswitch_re) * signed(unswitch_re)
+ + signed(unswitch_im) * signed(unswitch_im)
+ ) when unswitch_val = '1' else (others => '0');
- -- Wave window: View fft_re, fft_im in analogue format
- -- Wave window: View power in binary format to get a spectrum diagram
+ -- Wave window: View fft_re, fft_im in analogue format
+ -- Wave window: View power in binary format to get a spectrum diagram
- -- power_x <= power WHEN bin(0) = '0' ELSE power_x;
- -- power_y <= power WHEN bin(0) = '1' ELSE power_y;
+ -- power_x <= power WHEN bin(0) = '0' ELSE power_x;
+ -- power_y <= power WHEN bin(0) = '1' ELSE power_y;
- -- Use clk to avoid limit cycle pulses in power_x and power_y
- demux_power : process(clk)
- begin
- if falling_edge(clk) then
- if unswitch_val = '1' then
- if bin(0) = '0' then
- fft_x_re <= unswitch_re;
- fft_x_im <= unswitch_im;
- power_x <= power;
- else
- fft_y_re <= unswitch_re;
- fft_y_im <= unswitch_im;
- power_y <= power;
- end if;
+ -- Use clk to avoid limit cycle pulses in power_x and power_y
+ demux_power : process(clk)
+ begin
+ if falling_edge(clk) then
+ if unswitch_val = '1' then
+ if bin(0) = '0' then
+ fft_x_re <= unswitch_re;
+ fft_x_im <= unswitch_im;
+ power_x <= power;
+ else
+ fft_y_re <= unswitch_re;
+ fft_y_im <= unswitch_im;
+ power_y <= power;
end if;
end if;
- end process;
+ end if;
+ end process;
-- synthesis translate_on
out_re <= unswitch_re;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
index 167561784c..669d260b45 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.pft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.pft_pkg.all;
entity pft is
generic (
@@ -122,23 +122,23 @@ begin
-- NB. The first stage has index c_nof_stages-1, the last stage has index 0.
switch: entity work.pft_switch
- generic map (
- g_dat_w => g_in_dat_w,
- g_fft_sz_w => g_fft_size_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- in_sync => in_sync,
- in_re => in_re,
- in_im => in_im,
- switch_en => switch_en,
- out_re => switch_re,
- out_im => switch_im,
- out_val => switch_val,
- out_sync => switch_sync
- );
+ generic map (
+ g_dat_w => g_in_dat_w,
+ g_fft_sz_w => g_fft_size_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ in_sync => in_sync,
+ in_re => in_re,
+ in_im => in_im,
+ switch_en => switch_en,
+ out_re => switch_re,
+ out_im => switch_im,
+ out_val => switch_val,
+ out_sync => switch_sync
+ );
first_gen : if (c_nof_stages > 1) generate
first_stage : entity work.pft_stage
@@ -205,23 +205,23 @@ begin
only_gen : if c_nof_stages = 1 generate
only_stage : entity work.pft_stage
- generic map (
- g_index => 0,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_pft_dat_w
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => pft_re,
- out_im => pft_im,
- out_val => pft_val,
- out_sync => pft_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 0,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_pft_dat_w
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => pft_re,
+ out_im => pft_im,
+ out_val => pft_val,
+ out_sync => pft_sync,
+ clk => clk,
+ rst => rst
+ );
end generate;
-- In "BITREV" mode, fft output is in bit reversed order.
@@ -255,7 +255,7 @@ begin
);
end generate;
- reverse_gen : if g_mode = PFT_MODE_COMPLEX generate
+ reverse_gen : if g_mode = PFT_MODE_COMPLEX generate
reverse : entity work.pft_reverse
generic map (
g_fft_sz => 2**g_fft_size_w,
@@ -305,65 +305,65 @@ begin
end generate;
unswitch: entity work.pft_unswitch
- generic map (
- g_dat_w => g_out_dat_w,
- g_fft_sz_w => g_fft_size_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => sep_val,
- in_sync => sep_sync,
- in_re => sep_re,
- in_im => sep_im,
- switch_en => switch_en,
- out_re => unswitch_re,
- out_im => unswitch_im,
- out_val => unswitch_val,
- out_sync => unswitch_sync
- );
+ generic map (
+ g_dat_w => g_out_dat_w,
+ g_fft_sz_w => g_fft_size_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => sep_val,
+ in_sync => sep_sync,
+ in_re => sep_re,
+ in_im => sep_im,
+ switch_en => switch_en,
+ out_re => unswitch_re,
+ out_im => unswitch_im,
+ out_val => unswitch_val,
+ out_sync => unswitch_sync
+ );
-- calculate the power. This is intended to be used in simulations only.
-- synthesis translate_off
- determine_bin : process (clk)
- begin
- if rising_edge(clk) then
- if unswitch_val = '1' then
- bin <= std_logic_vector(unsigned(bin) + 1);
- end if;
+ determine_bin : process (clk)
+ begin
+ if rising_edge(clk) then
+ if unswitch_val = '1' then
+ bin <= std_logic_vector(unsigned(bin) + 1);
end if;
- end process;
+ end if;
+ end process;
- band <= bin(bin'high downto 1);
+ band <= bin(bin'high downto 1);
- power <= std_logic_vector( signed(unswitch_re) * signed(unswitch_re)
- + signed(unswitch_im) * signed(unswitch_im)
- ) when unswitch_val = '1' else (others => '0');
+ power <= std_logic_vector( signed(unswitch_re) * signed(unswitch_re)
+ + signed(unswitch_im) * signed(unswitch_im)
+ ) when unswitch_val = '1' else (others => '0');
- -- Wave window: View fft_re, fft_im in analogue format
- -- Wave window: View power in binary format to get a spectrum diagram
+ -- Wave window: View fft_re, fft_im in analogue format
+ -- Wave window: View power in binary format to get a spectrum diagram
- -- power_x <= power WHEN bin(0) = '0' ELSE power_x;
- -- power_y <= power WHEN bin(0) = '1' ELSE power_y;
+ -- power_x <= power WHEN bin(0) = '0' ELSE power_x;
+ -- power_y <= power WHEN bin(0) = '1' ELSE power_y;
- -- Use clk to avoid limit cycle pulses in power_x and power_y
- demux_power : process(clk)
- begin
- if falling_edge(clk) then
- if unswitch_val = '1' then
- if bin(0) = '0' then
- fft_x_re <= unswitch_re;
- fft_x_im <= unswitch_im;
- power_x <= power;
- else
- fft_y_re <= unswitch_re;
- fft_y_im <= unswitch_im;
- power_y <= power;
- end if;
+ -- Use clk to avoid limit cycle pulses in power_x and power_y
+ demux_power : process(clk)
+ begin
+ if falling_edge(clk) then
+ if unswitch_val = '1' then
+ if bin(0) = '0' then
+ fft_x_re <= unswitch_re;
+ fft_x_im <= unswitch_im;
+ power_x <= power;
+ else
+ fft_y_re <= unswitch_re;
+ fft_y_im <= unswitch_im;
+ power_y <= power;
end if;
end if;
- end process;
+ end if;
+ end process;
-- synthesis translate_on
out_re <= unswitch_re;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
index 36e8e2a007..de7e5fe0dc 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
@@ -1,9 +1,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.all;
+ use common_lib.all;
architecture rtl of pft_bf is
constant c_read_pipeline : natural := 1;
@@ -209,11 +209,11 @@ begin
end if;
end process;
--- Adds/ Subs ------------------------------------------------------------------
+ -- Adds/ Subs ------------------------------------------------------------------
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
--cadd : ENTITY common_lib.common_caddsub
--GENERIC MAP (
@@ -237,119 +237,119 @@ begin
--);
cadd : entity common_complex_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_ar => add_ar,
- in_ai => add_ai,
- in_br => add_br,
- in_bi => add_bi,
- out_re => add_cr,
- out_im => add_ci
- );
-
--- csub : ENTITY common_lib.common_caddsub
--- GENERIC MAP (
--- g_in_a_w => c_dat_w,
--- g_in_b_w => c_dat_w,
--- g_out_c_w => c_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "SUB"
--- )
--- PORT MAP (
--- in_ar => sub_ar,
--- in_ai => sub_ai,
--- in_br => sub_br,
--- in_bi => sub_bi,
--- in_cr => '1',
--- in_ci => '1',
--- out_cr => sub_cr,
--- out_ci => sub_ci,
--- clk => clk,
--- rst => rst
--- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_ar => add_ar,
+ in_ai => add_ai,
+ in_br => add_br,
+ in_bi => add_bi,
+ out_re => add_cr,
+ out_im => add_ci
+ );
+
+ -- csub : ENTITY common_lib.common_caddsub
+ -- GENERIC MAP (
+ -- g_in_a_w => c_dat_w,
+ -- g_in_b_w => c_dat_w,
+ -- g_out_c_w => c_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "SUB"
+ -- )
+ -- PORT MAP (
+ -- in_ar => sub_ar,
+ -- in_ai => sub_ai,
+ -- in_br => sub_br,
+ -- in_bi => sub_bi,
+ -- in_cr => '1',
+ -- in_ci => '1',
+ -- out_cr => sub_cr,
+ -- out_ci => sub_ci,
+ -- clk => clk,
+ -- rst => rst
+ -- );
csub : entity common_complex_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_ar => sub_ar,
- in_ai => sub_ai,
- in_br => sub_br,
- in_bi => sub_bi,
- out_re => sub_cr,
- out_im => sub_ci
- );
-
--- regbank --------------------------------------------------------------------------
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_ar => sub_ar,
+ in_ai => sub_ai,
+ in_br => sub_br,
+ in_bi => sub_bi,
+ out_re => sub_cr,
+ out_im => sub_ci
+ );
+
+ -- regbank --------------------------------------------------------------------------
fifo_gen: if c_regbank_size > 8 generate
- fifo : entity common_lib.common_fifo_sc
- generic map (
- g_dat_w => wr_dat'LENGTH,
- g_nof_words => c_regbank_size
- )
- port map (
- wr_dat => wr_dat,
- wr_req => wr_req,
- rd_dat => rd_dat,
- rd_req => rd_req,
- clk => clk,
- rst => rst
- );
+ fifo : entity common_lib.common_fifo_sc
+ generic map (
+ g_dat_w => wr_dat'LENGTH,
+ g_nof_words => c_regbank_size
+ )
+ port map (
+ wr_dat => wr_dat,
+ wr_req => wr_req,
+ rd_dat => rd_dat,
+ rd_req => rd_req,
+ clk => clk,
+ rst => rst
+ );
end generate fifo_gen;
fifo2_gen : if c_regbank_size > c_pipeline and c_regbank_size <= 8 generate
- fifo2_reg : process (clk, rst)
- begin
- if rst = '1' then
- fifo_dat <= (others => (others => '0'));
- elsif rising_edge(clk) then
- fifo_dat <= nxt_fifo_dat;
- end if;
- end process;
+ fifo2_reg : process (clk, rst)
+ begin
+ if rst = '1' then
+ fifo_dat <= (others => (others => '0'));
+ elsif rising_edge(clk) then
+ fifo_dat <= nxt_fifo_dat;
+ end if;
+ end process;
- fifo2_proc : process(fifo_dat,wr_req,wr_dat)
- begin
- nxt_fifo_dat <= fifo_dat;
- if wr_req = '1' then
- nxt_fifo_dat <= wr_dat & fifo_dat(fifo_dat'high downto 1);
- end if;
- rd_dat <= fifo_dat(0);
- end process;
+ fifo2_proc : process(fifo_dat,wr_req,wr_dat)
+ begin
+ nxt_fifo_dat <= fifo_dat;
+ if wr_req = '1' then
+ nxt_fifo_dat <= wr_dat & fifo_dat(fifo_dat'high downto 1);
+ end if;
+ rd_dat <= fifo_dat(0);
+ end process;
end generate;
fifo3_gen : if c_regbank_size = c_pipeline generate
- fifo3_reg : process (clk, rst)
- begin
- if rst = '1' then
- fifo_dat <= (others => (others => '0'));
- elsif rising_edge(clk) then
- fifo_dat <= nxt_fifo_dat;
- end if;
- end process;
+ fifo3_reg : process (clk, rst)
+ begin
+ if rst = '1' then
+ fifo_dat <= (others => (others => '0'));
+ elsif rising_edge(clk) then
+ fifo_dat <= nxt_fifo_dat;
+ end if;
+ end process;
- fifo3_proc : process(fifo_dat, wr_req, wr_dat)
- begin
- nxt_fifo_dat <= fifo_dat;
- if wr_req = '1' then
- nxt_fifo_dat(0) <= wr_dat;
- end if;
- rd_dat <= fifo_dat(0);
- end process;
+ fifo3_proc : process(fifo_dat, wr_req, wr_dat)
+ begin
+ nxt_fifo_dat <= fifo_dat;
+ if wr_req = '1' then
+ nxt_fifo_dat(0) <= wr_dat;
+ end if;
+ rd_dat <= fifo_dat(0);
+ end process;
end generate;
assert c_regbank_size >= c_pipeline severity FAILURE;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
index 52eebaf095..4871950463 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
@@ -256,11 +256,11 @@ begin
end if;
end process;
--- Adds/ Subs ------------------------------------------------------------------
+ -- Adds/ Subs ------------------------------------------------------------------
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
--cadd : ENTITY common_lib.common_caddsub
--GENERIC MAP (
@@ -284,119 +284,119 @@ begin
--);
cadd : entity common_lib.common_complex_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_ar => add_ar,
- in_ai => add_ai,
- in_br => add_br,
- in_bi => add_bi,
- out_re => add_cr,
- out_im => add_ci
- );
-
--- csub : ENTITY common_lib.common_caddsub
--- GENERIC MAP (
--- g_in_a_w => c_dat_w,
--- g_in_b_w => c_dat_w,
--- g_out_c_w => c_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "SUB"
--- )
--- PORT MAP (
--- in_ar => sub_ar,
--- in_ai => sub_ai,
--- in_br => sub_br,
--- in_bi => sub_bi,
--- in_cr => '1',
--- in_ci => '1',
--- out_cr => sub_cr,
--- out_ci => sub_ci,
--- clk => clk,
--- rst => rst
--- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_ar => add_ar,
+ in_ai => add_ai,
+ in_br => add_br,
+ in_bi => add_bi,
+ out_re => add_cr,
+ out_im => add_ci
+ );
+
+ -- csub : ENTITY common_lib.common_caddsub
+ -- GENERIC MAP (
+ -- g_in_a_w => c_dat_w,
+ -- g_in_b_w => c_dat_w,
+ -- g_out_c_w => c_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "SUB"
+ -- )
+ -- PORT MAP (
+ -- in_ar => sub_ar,
+ -- in_ai => sub_ai,
+ -- in_br => sub_br,
+ -- in_bi => sub_bi,
+ -- in_cr => '1',
+ -- in_ci => '1',
+ -- out_cr => sub_cr,
+ -- out_ci => sub_ci,
+ -- clk => clk,
+ -- rst => rst
+ -- );
csub : entity common_lib.common_complex_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_ar => sub_ar,
- in_ai => sub_ai,
- in_br => sub_br,
- in_bi => sub_bi,
- out_re => sub_cr,
- out_im => sub_ci
- );
-
--- regbank --------------------------------------------------------------------------
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_ar => sub_ar,
+ in_ai => sub_ai,
+ in_br => sub_br,
+ in_bi => sub_bi,
+ out_re => sub_cr,
+ out_im => sub_ci
+ );
+
+ -- regbank --------------------------------------------------------------------------
fifo_gen: if c_regbank_size > 8 generate
- fifo : entity common_lib.common_fifo_sc
- generic map (
- g_dat_w => wr_dat'LENGTH,
- g_nof_words => c_regbank_size
- )
- port map (
- wr_dat => wr_dat,
- wr_req => wr_req,
- rd_dat => rd_dat,
- rd_req => rd_req,
- clk => clk,
- rst => rst
- );
+ fifo : entity common_lib.common_fifo_sc
+ generic map (
+ g_dat_w => wr_dat'LENGTH,
+ g_nof_words => c_regbank_size
+ )
+ port map (
+ wr_dat => wr_dat,
+ wr_req => wr_req,
+ rd_dat => rd_dat,
+ rd_req => rd_req,
+ clk => clk,
+ rst => rst
+ );
end generate fifo_gen;
fifo2_gen : if c_regbank_size > c_pipeline and c_regbank_size <= 8 generate
- fifo2_reg : process (clk, rst)
- begin
- if rst = '1' then
- fifo_dat <= (others => (others => '0'));
- elsif rising_edge(clk) then
- fifo_dat <= nxt_fifo_dat;
- end if;
- end process;
+ fifo2_reg : process (clk, rst)
+ begin
+ if rst = '1' then
+ fifo_dat <= (others => (others => '0'));
+ elsif rising_edge(clk) then
+ fifo_dat <= nxt_fifo_dat;
+ end if;
+ end process;
- fifo2_proc : process(fifo_dat,wr_req,wr_dat)
- begin
- nxt_fifo_dat <= fifo_dat;
- if wr_req = '1' then
- nxt_fifo_dat <= wr_dat & fifo_dat(fifo_dat'high downto 1);
- end if;
- rd_dat <= fifo_dat(0);
- end process;
+ fifo2_proc : process(fifo_dat,wr_req,wr_dat)
+ begin
+ nxt_fifo_dat <= fifo_dat;
+ if wr_req = '1' then
+ nxt_fifo_dat <= wr_dat & fifo_dat(fifo_dat'high downto 1);
+ end if;
+ rd_dat <= fifo_dat(0);
+ end process;
end generate;
fifo3_gen : if c_regbank_size = c_pipeline generate
- fifo3_reg : process (clk, rst)
- begin
- if rst = '1' then
- fifo_dat <= (others => (others => '0'));
- elsif rising_edge(clk) then
- fifo_dat <= nxt_fifo_dat;
- end if;
- end process;
+ fifo3_reg : process (clk, rst)
+ begin
+ if rst = '1' then
+ fifo_dat <= (others => (others => '0'));
+ elsif rising_edge(clk) then
+ fifo_dat <= nxt_fifo_dat;
+ end if;
+ end process;
- fifo3_proc : process(fifo_dat, wr_req, wr_dat)
- begin
- nxt_fifo_dat <= fifo_dat;
- if wr_req = '1' then
- nxt_fifo_dat(0) <= wr_dat;
- end if;
- rd_dat <= fifo_dat(0);
- end process;
+ fifo3_proc : process(fifo_dat, wr_req, wr_dat)
+ begin
+ nxt_fifo_dat <= fifo_dat;
+ if wr_req = '1' then
+ nxt_fifo_dat(0) <= wr_dat;
+ end if;
+ rd_dat <= fifo_dat(0);
+ end process;
end generate;
assert c_regbank_size >= c_pipeline severity FAILURE;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
index c8467e4475..ce76034bcb 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
@@ -1,9 +1,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.all;
+ use common_lib.all;
architecture rtl of pft_bf_fw is
constant c_add_pipeline : natural := 2;
@@ -154,79 +154,79 @@ begin
-- Adds/ Subs ----------------------------------------------------------------
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
-
--- yr_cry <= NOT yr_add;
-
--- yr : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => g_in_dat_w,
--- g_in_b_w => g_in_dat_w,
--- g_out_c_w => g_out_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "BOTH"
--- )
--- PORT MAP (
--- in_a => yr_a,
--- in_b => yr_b,
--- in_cry => yr_cry,
--- add_sub => yr_add,
--- clk => clk,
--- out_c => out_re
--- );
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+
+ -- yr_cry <= NOT yr_add;
+
+ -- yr : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => g_in_dat_w,
+ -- g_in_b_w => g_in_dat_w,
+ -- g_out_c_w => g_out_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "BOTH"
+ -- )
+ -- PORT MAP (
+ -- in_a => yr_a,
+ -- in_b => yr_b,
+ -- in_cry => yr_cry,
+ -- add_sub => yr_add,
+ -- clk => clk,
+ -- out_c => out_re
+ -- );
yr : entity common_add_sub
- generic map (
- g_direction => "BOTH",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- sel_add => yr_add,
- in_a => yr_a,
- in_b => yr_b,
- result => out_re
- );
-
--- yi_cry <= NOT yi_add;
---
--- yi : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => g_in_dat_w,
--- g_in_b_w => g_in_dat_w,
--- g_out_c_w => g_out_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "BOTH"
--- )
--- PORT MAP (
--- in_a => yi_a,
--- in_b => yi_b,
--- in_cry => yi_cry,
--- add_sub => yi_add,
--- clk => clk,
--- out_c => out_im
--- );
+ generic map (
+ g_direction => "BOTH",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ sel_add => yr_add,
+ in_a => yr_a,
+ in_b => yr_b,
+ result => out_re
+ );
+
+ -- yi_cry <= NOT yi_add;
+ --
+ -- yi : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => g_in_dat_w,
+ -- g_in_b_w => g_in_dat_w,
+ -- g_out_c_w => g_out_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "BOTH"
+ -- )
+ -- PORT MAP (
+ -- in_a => yi_a,
+ -- in_b => yi_b,
+ -- in_cry => yi_cry,
+ -- add_sub => yi_add,
+ -- clk => clk,
+ -- out_c => out_im
+ -- );
yi : entity common_add_sub
- generic map (
- g_direction => "BOTH",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- sel_add => yi_add,
- in_a => yi_a,
- in_b => yi_b,
- result => out_im
- );
+ generic map (
+ g_direction => "BOTH",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ sel_add => yi_add,
+ in_a => yi_a,
+ in_b => yi_b,
+ result => out_im
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
index f777f5e18d..066b9309b6 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
@@ -201,79 +201,79 @@ begin
-- Adds/ Subs ----------------------------------------------------------------
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
-
--- yr_cry <= NOT yr_add;
-
--- yr : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => g_in_dat_w,
--- g_in_b_w => g_in_dat_w,
--- g_out_c_w => g_out_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "BOTH"
--- )
--- PORT MAP (
--- in_a => yr_a,
--- in_b => yr_b,
--- in_cry => yr_cry,
--- add_sub => yr_add,
--- clk => clk,
--- out_c => out_re
--- );
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+
+ -- yr_cry <= NOT yr_add;
+
+ -- yr : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => g_in_dat_w,
+ -- g_in_b_w => g_in_dat_w,
+ -- g_out_c_w => g_out_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "BOTH"
+ -- )
+ -- PORT MAP (
+ -- in_a => yr_a,
+ -- in_b => yr_b,
+ -- in_cry => yr_cry,
+ -- add_sub => yr_add,
+ -- clk => clk,
+ -- out_c => out_re
+ -- );
yr : entity common_lib.common_add_sub
- generic map (
- g_direction => "BOTH",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- sel_add => yr_add,
- in_a => yr_a,
- in_b => yr_b,
- result => out_re
- );
-
--- yi_cry <= NOT yi_add;
---
--- yi : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => g_in_dat_w,
--- g_in_b_w => g_in_dat_w,
--- g_out_c_w => g_out_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "BOTH"
--- )
--- PORT MAP (
--- in_a => yi_a,
--- in_b => yi_b,
--- in_cry => yi_cry,
--- add_sub => yi_add,
--- clk => clk,
--- out_c => out_im
--- );
+ generic map (
+ g_direction => "BOTH",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ sel_add => yr_add,
+ in_a => yr_a,
+ in_b => yr_b,
+ result => out_re
+ );
+
+ -- yi_cry <= NOT yi_add;
+ --
+ -- yi : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => g_in_dat_w,
+ -- g_in_b_w => g_in_dat_w,
+ -- g_out_c_w => g_out_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "BOTH"
+ -- )
+ -- PORT MAP (
+ -- in_a => yi_a,
+ -- in_b => yi_b,
+ -- in_cry => yi_cry,
+ -- add_sub => yi_add,
+ -- clk => clk,
+ -- out_c => out_im
+ -- );
yi : entity common_lib.common_add_sub
- generic map (
- g_direction => "BOTH",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- sel_add => yi_add,
- in_a => yi_a,
- in_b => yi_b,
- result => out_im
- );
+ generic map (
+ g_direction => "BOTH",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ sel_add => yi_add,
+ in_a => yi_a,
+ in_b => yi_b,
+ result => out_im
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
index 85ff4fdba8..8a643c0f93 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
@@ -1,22 +1,23 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use common_lib.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
architecture rtl of pft_buffer is
constant c_latency : natural := 2;
constant c_adr_w : natural := g_fft_size_w + 1;
constant c_nof_words : natural := 2**c_adr_w;
- constant c_ram : t_c_mem := (latency => c_latency,
- adr_w => c_adr_w,
- dat_w => 2 * g_dat_w,
- nof_dat => c_nof_words, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_ram : t_c_mem := (
+ latency => c_latency,
+ adr_w => c_adr_w,
+ dat_w => 2 * g_dat_w,
+ nof_dat => c_nof_words, -- <= 2**g_addr_w
+ init_sl => '0');
signal rd_dat : std_logic_vector(2 * g_dat_w - 1 downto 0);
signal wr_dat : std_logic_vector(rd_dat'range);
@@ -101,36 +102,36 @@ begin
wr_dat <= wr_re & wr_im;
wr_en <= wr_val;
--- -- ram module
--- ram : ENTITY common_lib.common_dpram
--- GENERIC MAP (
--- g_dat_w => 2*g_dat_w,
--- g_adr_w => c_adr_w,
--- g_nof_words => c_nof_words
--- )
--- PORT MAP (
--- rd_dat => rd_dat,
--- rd_adr => rd_adr_paged,
--- rd_en => rd_en,
--- wr_dat => wr_dat,
--- wr_adr => wr_adr_paged,
--- wr_en => wr_en,
--- clk => clk,
--- rst => rst
--- );
+ -- -- ram module
+ -- ram : ENTITY common_lib.common_dpram
+ -- GENERIC MAP (
+ -- g_dat_w => 2*g_dat_w,
+ -- g_adr_w => c_adr_w,
+ -- g_nof_words => c_nof_words
+ -- )
+ -- PORT MAP (
+ -- rd_dat => rd_dat,
+ -- rd_adr => rd_adr_paged,
+ -- rd_en => rd_en,
+ -- wr_dat => wr_dat,
+ -- wr_adr => wr_adr_paged,
+ -- wr_en => wr_en,
+ -- clk => clk,
+ -- rst => rst
+ -- );
ram : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => wr_en,
- wr_adr => wr_adr_paged,
- wr_dat => wr_dat,
- rd_en => rd_en,
- rd_adr => rd_adr_paged,
- rd_dat => rd_dat
- );
+ generic map (
+ g_ram => c_ram
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => wr_en,
+ wr_adr => wr_adr_paged,
+ wr_dat => wr_dat,
+ rd_en => rd_en,
+ rd_adr => rd_adr_paged,
+ rd_dat => rd_dat
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
index 33f764deb9..1d8cebc038 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
@@ -24,12 +24,12 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity pft_buffer is
generic (
@@ -58,11 +58,12 @@ architecture rtl of pft_buffer is
constant c_adr_w : natural := g_fft_size_w + 1;
constant c_nof_words : natural := 2**c_adr_w;
- constant c_ram : t_c_mem := (latency => c_latency,
- adr_w => c_adr_w,
- dat_w => 2 * g_dat_w,
- nof_dat => c_nof_words, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_ram : t_c_mem := (
+ latency => c_latency,
+ adr_w => c_adr_w,
+ dat_w => 2 * g_dat_w,
+ nof_dat => c_nof_words, -- <= 2**g_addr_w
+ init_sl => '0');
signal rd_dat : std_logic_vector(2 * g_dat_w - 1 downto 0);
signal wr_dat : std_logic_vector(rd_dat'range);
@@ -147,36 +148,36 @@ begin
wr_dat <= wr_re & wr_im;
wr_en <= wr_val;
--- -- ram module
--- ram : ENTITY common_lib.common_dpram
--- GENERIC MAP (
--- g_dat_w => 2*g_dat_w,
--- g_adr_w => c_adr_w,
--- g_nof_words => c_nof_words
--- )
--- PORT MAP (
--- rd_dat => rd_dat,
--- rd_adr => rd_adr_paged,
--- rd_en => rd_en,
--- wr_dat => wr_dat,
--- wr_adr => wr_adr_paged,
--- wr_en => wr_en,
--- clk => clk,
--- rst => rst
--- );
+ -- -- ram module
+ -- ram : ENTITY common_lib.common_dpram
+ -- GENERIC MAP (
+ -- g_dat_w => 2*g_dat_w,
+ -- g_adr_w => c_adr_w,
+ -- g_nof_words => c_nof_words
+ -- )
+ -- PORT MAP (
+ -- rd_dat => rd_dat,
+ -- rd_adr => rd_adr_paged,
+ -- rd_en => rd_en,
+ -- wr_dat => wr_dat,
+ -- wr_adr => wr_adr_paged,
+ -- wr_en => wr_en,
+ -- clk => clk,
+ -- rst => rst
+ -- );
ram : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => wr_en,
- wr_adr => wr_adr_paged,
- wr_dat => wr_dat,
- rd_en => rd_en,
- rd_adr => rd_adr_paged,
- rd_dat => rd_dat
- );
+ generic map (
+ g_ram => c_ram
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => wr_en,
+ wr_adr => wr_adr_paged,
+ wr_dat => wr_dat,
+ rd_en => rd_en,
+ rd_adr => rd_adr_paged,
+ rd_dat => rd_dat
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
index 73c752e25b..dcc668e24d 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
@@ -1,5 +1,5 @@
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
architecture rtl of pft_lfsr is
-- uses preferred pair of pritive trinomials
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
index c6250be5bc..eeb6d51c73 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
@@ -24,7 +24,7 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity pft_lfsr is
port (
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
index 75fcb992ca..3da701efe2 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
@@ -24,8 +24,8 @@
-- Remark: Copy of pft(pkg).vhd to avoid () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
package pft_pkg is
constant c_pft_twiddle_w : natural := 16;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd
index 86d5cdd9f8..db768abce6 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
architecture rtl of pft_reverse is
signal i_rdaddr : std_logic_vector(rdaddr'range);
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd
index 80ebdc9969..488813a001 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pft_reverse is
generic (
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
index 885d8a147e..fdc7d0ee7d 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
@@ -1,9 +1,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.all;
+ use common_lib.all;
architecture rtl of pft_separate is
constant c_reg_delay : natural := 2;
@@ -164,71 +164,71 @@ begin
nxt_out_val <= rdval_dly(rdval_dly'high);
nxt_out_sync <= rdsync_dly(rdsync_dly'high);
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
-
--- add : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => add0'LENGTH,
--- g_in_b_w => add1'LENGTH,
--- g_out_c_w => add_out'LENGTH,
--- g_pipeline => c_add_delay-1,
--- g_add_sub => "ADD"
--- )
--- PORT MAP (
--- in_a => add0,
--- in_b => add1,
--- in_cry => '0',
--- out_c => add_out,
--- clk => clk
--- );
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+
+ -- add : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => add0'LENGTH,
+ -- g_in_b_w => add1'LENGTH,
+ -- g_out_c_w => add_out'LENGTH,
+ -- g_pipeline => c_add_delay-1,
+ -- g_add_sub => "ADD"
+ -- )
+ -- PORT MAP (
+ -- in_a => add0,
+ -- in_b => add1,
+ -- in_cry => '0',
+ -- out_c => add_out,
+ -- clk => clk
+ -- );
add : entity common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
- g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_a => add0,
- in_b => add1,
- result => add_out
- );
-
--- sub : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => sub0'LENGTH,
--- g_in_b_w => sub1'LENGTH,
--- g_out_c_w => sub_out'LENGTH,
--- g_pipeline => c_add_delay-1,
--- g_add_sub => "SUB"
--- )
--- PORT MAP (
--- in_a => sub0,
--- in_b => sub1,
--- in_cry => '1',
--- out_c => sub_out,
--- clk => clk
--- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_delay - 1, -- >= 0
+ g_in_dat_w => g_rd_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_a => add0,
+ in_b => add1,
+ result => add_out
+ );
+
+ -- sub : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => sub0'LENGTH,
+ -- g_in_b_w => sub1'LENGTH,
+ -- g_out_c_w => sub_out'LENGTH,
+ -- g_pipeline => c_add_delay-1,
+ -- g_add_sub => "SUB"
+ -- )
+ -- PORT MAP (
+ -- in_a => sub0,
+ -- in_b => sub1,
+ -- in_cry => '1',
+ -- out_c => sub_out,
+ -- clk => clk
+ -- );
sub : entity common_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
- g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_a => sub0,
- in_b => sub1,
- result => sub_out
- );
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_delay - 1, -- >= 0
+ g_in_dat_w => g_rd_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_a => sub0,
+ in_b => sub1,
+ result => sub_out
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
index 538b57aac8..5967f04f72 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pft_separate is
generic (
@@ -210,71 +210,71 @@ begin
nxt_out_val <= rdval_dly(rdval_dly'high);
nxt_out_sync <= rdsync_dly(rdsync_dly'high);
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
--- add : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => add0'LENGTH,
--- g_in_b_w => add1'LENGTH,
--- g_out_c_w => add_out'LENGTH,
--- g_pipeline => c_add_delay-1,
--- g_add_sub => "ADD"
--- )
--- PORT MAP (
--- in_a => add0,
--- in_b => add1,
--- in_cry => '0',
--- out_c => add_out,
--- clk => clk
--- );
+ -- add : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => add0'LENGTH,
+ -- g_in_b_w => add1'LENGTH,
+ -- g_out_c_w => add_out'LENGTH,
+ -- g_pipeline => c_add_delay-1,
+ -- g_add_sub => "ADD"
+ -- )
+ -- PORT MAP (
+ -- in_a => add0,
+ -- in_b => add1,
+ -- in_cry => '0',
+ -- out_c => add_out,
+ -- clk => clk
+ -- );
add : entity common_lib.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
- g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_a => add0,
- in_b => add1,
- result => add_out
- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_delay - 1, -- >= 0
+ g_in_dat_w => g_rd_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_a => add0,
+ in_b => add1,
+ result => add_out
+ );
--- sub : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => sub0'LENGTH,
--- g_in_b_w => sub1'LENGTH,
--- g_out_c_w => sub_out'LENGTH,
--- g_pipeline => c_add_delay-1,
--- g_add_sub => "SUB"
--- )
--- PORT MAP (
--- in_a => sub0,
--- in_b => sub1,
--- in_cry => '1',
--- out_c => sub_out,
--- clk => clk
--- );
+ -- sub : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => sub0'LENGTH,
+ -- g_in_b_w => sub1'LENGTH,
+ -- g_out_c_w => sub_out'LENGTH,
+ -- g_pipeline => c_add_delay-1,
+ -- g_add_sub => "SUB"
+ -- )
+ -- PORT MAP (
+ -- in_a => sub0,
+ -- in_b => sub1,
+ -- in_cry => '1',
+ -- out_c => sub_out,
+ -- clk => clk
+ -- );
sub : entity common_lib.common_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
- g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_a => sub0,
- in_b => sub1,
- result => sub_out
- );
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_delay - 1, -- >= 0
+ g_in_dat_w => g_rd_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_a => sub0,
+ in_b => sub1,
+ result => sub_out
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
index b4069cd55e..6c7d7b6dbe 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library common_lib, pft2_lib;
-use common_lib.all;
+ use common_lib.all;
architecture str of pft_stage is
constant c_round_pipeline_in : natural := 1;
@@ -42,128 +42,128 @@ architecture str of pft_stage is
begin
gen_middle: if g_index > 0 generate
bf1 : entity pft2_lib.pft_bf
- generic map (
- g_index => 2 * g_index + 1,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_bf1_out_w,
- g_bf_name => "bf1"
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => bf1_re,
- out_im => bf1_im,
- out_val => bf1_val,
- out_sync => bf1_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index + 1,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_bf1_out_w,
+ g_bf_name => "bf1"
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => bf1_re,
+ out_im => bf1_im,
+ out_val => bf1_val,
+ out_sync => bf1_sync,
+ clk => clk,
+ rst => rst
+ );
bf2 : entity pft2_lib.pft_bf
- generic map (
- g_index => 2 * g_index,
- g_in_dat_w => c_bf1_out_w,
- g_out_dat_w => c_bf2_out_w,
- g_bf_name => "bf2"
- )
- port map (
- in_re => bf1_re,
- in_im => bf1_im,
- in_val => bf1_val,
- in_sync => bf1_sync,
- out_re => bf2_re,
- out_im => bf2_im,
- out_val => bf2_val,
- out_sync => bf2_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index,
+ g_in_dat_w => c_bf1_out_w,
+ g_out_dat_w => c_bf2_out_w,
+ g_bf_name => "bf2"
+ )
+ port map (
+ in_re => bf1_re,
+ in_im => bf1_im,
+ in_val => bf1_val,
+ in_sync => bf1_sync,
+ out_re => bf2_re,
+ out_im => bf2_im,
+ out_val => bf2_val,
+ out_sync => bf2_sync,
+ clk => clk,
+ rst => rst
+ );
tmult : entity pft2_lib.pft_tmult
- generic map (
- g_in_dat_w => c_bf2_out_w,
- g_out_dat_w => g_out_dat_w,
- g_index => g_index
- )
- port map (
- in_re => bf2_re,
- in_im => bf2_im,
- in_val => bf2_val,
- in_sync => bf2_sync,
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_in_dat_w => c_bf2_out_w,
+ g_out_dat_w => g_out_dat_w,
+ g_index => g_index
+ )
+ port map (
+ in_re => bf2_re,
+ in_im => bf2_im,
+ in_val => bf2_val,
+ in_sync => bf2_sync,
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
end generate;
gen_last: if g_index = 0 generate
signal reg_val : std_logic;
signal reg_sync : std_logic;
- begin
+ begin
bf1_fw : entity pft2_lib.pft_bf_fw
- generic map (
- g_index => 2 * g_index + 1,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_bf1_out_w,
- g_bf_name => "bf1"
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => bf1_re,
- out_im => bf1_im,
- out_val => bf1_val,
- out_sync => bf1_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index + 1,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_bf1_out_w,
+ g_bf_name => "bf1"
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => bf1_re,
+ out_im => bf1_im,
+ out_val => bf1_val,
+ out_sync => bf1_sync,
+ clk => clk,
+ rst => rst
+ );
bf2_fw : entity pft2_lib.pft_bf_fw
- generic map (
- g_index => 2 * g_index,
- g_in_dat_w => c_bf1_out_w,
- g_out_dat_w => c_bf2_out_w,
- g_bf_name => "bf2"
- )
- port map (
- in_re => bf1_re,
- in_im => bf1_im,
- in_val => bf1_val,
- in_sync => bf1_sync,
- out_re => bf2_re,
- out_im => bf2_im,
- out_val => bf2_val,
- out_sync => bf2_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index,
+ g_in_dat_w => c_bf1_out_w,
+ g_out_dat_w => c_bf2_out_w,
+ g_bf_name => "bf2"
+ )
+ port map (
+ in_re => bf1_re,
+ in_im => bf1_im,
+ in_val => bf1_val,
+ in_sync => bf1_sync,
+ out_re => bf2_re,
+ out_im => bf2_im,
+ out_val => bf2_val,
+ out_sync => bf2_sync,
+ clk => clk,
+ rst => rst
+ );
u_rnd : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => c_bf2_out_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- in_re => bf2_re,
- in_im => bf2_im,
- out_re => out_re,
- out_im => out_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => c_bf2_out_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ in_re => bf2_re,
+ in_im => bf2_im,
+ out_re => out_re,
+ out_im => out_im,
+ clk => clk
+ );
p_regs: process(clk,rst)
begin
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
index 08b73281a2..4ce3cf4181 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
@@ -24,7 +24,7 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity pft_stage is
generic (
@@ -43,7 +43,7 @@ entity pft_stage is
out_sync : out std_logic;
clk : in std_logic;
rst : in std_logic
- );
+ );
end pft_stage;
architecture str of pft_stage is
@@ -66,128 +66,128 @@ architecture str of pft_stage is
begin
gen_middle: if g_index > 0 generate
bf1 : entity work.pft_bf
- generic map (
- g_index => 2 * g_index + 1,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_bf1_out_w,
- g_bf_name => "bf1"
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => bf1_re,
- out_im => bf1_im,
- out_val => bf1_val,
- out_sync => bf1_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index + 1,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_bf1_out_w,
+ g_bf_name => "bf1"
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => bf1_re,
+ out_im => bf1_im,
+ out_val => bf1_val,
+ out_sync => bf1_sync,
+ clk => clk,
+ rst => rst
+ );
bf2 : entity work.pft_bf
- generic map (
- g_index => 2 * g_index,
- g_in_dat_w => c_bf1_out_w,
- g_out_dat_w => c_bf2_out_w,
- g_bf_name => "bf2"
- )
- port map (
- in_re => bf1_re,
- in_im => bf1_im,
- in_val => bf1_val,
- in_sync => bf1_sync,
- out_re => bf2_re,
- out_im => bf2_im,
- out_val => bf2_val,
- out_sync => bf2_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index,
+ g_in_dat_w => c_bf1_out_w,
+ g_out_dat_w => c_bf2_out_w,
+ g_bf_name => "bf2"
+ )
+ port map (
+ in_re => bf1_re,
+ in_im => bf1_im,
+ in_val => bf1_val,
+ in_sync => bf1_sync,
+ out_re => bf2_re,
+ out_im => bf2_im,
+ out_val => bf2_val,
+ out_sync => bf2_sync,
+ clk => clk,
+ rst => rst
+ );
tmult : entity work.pft_tmult
- generic map (
- g_in_dat_w => c_bf2_out_w,
- g_out_dat_w => g_out_dat_w,
- g_index => g_index
- )
- port map (
- in_re => bf2_re,
- in_im => bf2_im,
- in_val => bf2_val,
- in_sync => bf2_sync,
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_in_dat_w => c_bf2_out_w,
+ g_out_dat_w => g_out_dat_w,
+ g_index => g_index
+ )
+ port map (
+ in_re => bf2_re,
+ in_im => bf2_im,
+ in_val => bf2_val,
+ in_sync => bf2_sync,
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
end generate;
gen_last: if g_index = 0 generate
signal reg_val : std_logic;
signal reg_sync : std_logic;
- begin
+ begin
bf1_fw : entity work.pft_bf_fw
- generic map (
- g_index => 2 * g_index + 1,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_bf1_out_w,
- g_bf_name => "bf1"
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => bf1_re,
- out_im => bf1_im,
- out_val => bf1_val,
- out_sync => bf1_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index + 1,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_bf1_out_w,
+ g_bf_name => "bf1"
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => bf1_re,
+ out_im => bf1_im,
+ out_val => bf1_val,
+ out_sync => bf1_sync,
+ clk => clk,
+ rst => rst
+ );
bf2_fw : entity work.pft_bf_fw
- generic map (
- g_index => 2 * g_index,
- g_in_dat_w => c_bf1_out_w,
- g_out_dat_w => c_bf2_out_w,
- g_bf_name => "bf2"
- )
- port map (
- in_re => bf1_re,
- in_im => bf1_im,
- in_val => bf1_val,
- in_sync => bf1_sync,
- out_re => bf2_re,
- out_im => bf2_im,
- out_val => bf2_val,
- out_sync => bf2_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index,
+ g_in_dat_w => c_bf1_out_w,
+ g_out_dat_w => c_bf2_out_w,
+ g_bf_name => "bf2"
+ )
+ port map (
+ in_re => bf1_re,
+ in_im => bf1_im,
+ in_val => bf1_val,
+ in_sync => bf1_sync,
+ out_re => bf2_re,
+ out_im => bf2_im,
+ out_val => bf2_val,
+ out_sync => bf2_sync,
+ clk => clk,
+ rst => rst
+ );
u_rnd : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => c_bf2_out_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- in_re => bf2_re,
- in_im => bf2_im,
- out_re => out_re,
- out_im => out_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => c_bf2_out_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ in_re => bf2_re,
+ in_im => bf2_im,
+ out_re => out_re,
+ out_im => out_im,
+ clk => clk
+ );
p_regs: process(clk,rst)
begin
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
index f721e58626..a5aed7fc37 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
@@ -1,22 +1,22 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib;
-use pft2_lib.all;
+ use pft2_lib.all;
architecture rtl of pft_switch is
-signal cnt : std_logic_vector(g_fft_sz_w downto 0);
-signal nxt_cnt : std_logic_vector(cnt'range);
+ signal cnt : std_logic_vector(g_fft_sz_w downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
-signal lfsr_bit1 : std_logic;
-signal lfsr_bit2 : std_logic;
-signal lfsr_en : std_logic;
+ signal lfsr_bit1 : std_logic;
+ signal lfsr_bit2 : std_logic;
+ signal lfsr_en : std_logic;
-signal nxt_out_val : std_logic;
-signal nxt_out_sync : std_logic;
-signal nxt_out_re : std_logic_vector(in_re'range);
-signal nxt_out_im : std_logic_vector(in_im'range);
+ signal nxt_out_val : std_logic;
+ signal nxt_out_sync : std_logic;
+ signal nxt_out_re : std_logic_vector(in_re'range);
+ signal nxt_out_im : std_logic_vector(in_im'range);
begin
registers : process (rst, clk)
begin
@@ -73,11 +73,11 @@ begin
end process;
lfsr: entity pft2_lib.pft_lfsr
- port map (
- clk => clk,
- rst => rst,
- in_en => lfsr_en,
- out_bit1 => lfsr_bit1,
- out_bit2 => lfsr_bit2
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_en => lfsr_en,
+ out_bit1 => lfsr_bit1,
+ out_bit2 => lfsr_bit2
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
index 0c6daed641..a8d8275f8c 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pft_switch is
generic (
@@ -48,17 +48,17 @@ entity pft_switch is
end pft_switch;
architecture rtl of pft_switch is
-signal cnt : std_logic_vector(g_fft_sz_w downto 0);
-signal nxt_cnt : std_logic_vector(cnt'range);
+ signal cnt : std_logic_vector(g_fft_sz_w downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
-signal lfsr_bit1 : std_logic;
-signal lfsr_bit2 : std_logic;
-signal lfsr_en : std_logic;
+ signal lfsr_bit1 : std_logic;
+ signal lfsr_bit2 : std_logic;
+ signal lfsr_en : std_logic;
-signal nxt_out_val : std_logic;
-signal nxt_out_sync : std_logic;
-signal nxt_out_re : std_logic_vector(in_re'range);
-signal nxt_out_im : std_logic_vector(in_im'range);
+ signal nxt_out_val : std_logic;
+ signal nxt_out_sync : std_logic;
+ signal nxt_out_re : std_logic_vector(in_re'range);
+ signal nxt_out_im : std_logic_vector(in_im'range);
begin
registers : process (rst, clk)
begin
@@ -115,11 +115,11 @@ begin
end process;
lfsr: entity work.pft_lfsr
- port map (
- clk => clk,
- rst => rst,
- in_en => lfsr_en,
- out_bit1 => lfsr_bit1,
- out_bit2 => lfsr_bit2
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_en => lfsr_en,
+ out_bit1 => lfsr_bit1,
+ out_bit2 => lfsr_bit2
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
index fc220fa98c..33b8e111ea 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_mult_lib;
library common_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
architecture rtl of pft_tmult is
constant c_nof_twids : natural := 16 * 2**(2 * (g_index - 1));
@@ -36,51 +36,52 @@ architecture rtl of pft_tmult is
constant c_coeff_w : natural := 16;
constant c_mult_out_w : natural := c_mult_in_w + c_coeff_w - 1;
- constant c_twid_rom : t_c_mem := (latency => 2,
- adr_w => c_adr_w,
- dat_w => 2 * c_coeff_w, -- complex
- nof_dat => 3 * c_nof_twids / 4, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_twid_rom : t_c_mem := (
+ latency => 2,
+ adr_w => c_adr_w,
+ dat_w => 2 * c_coeff_w, -- complex
+ nof_dat => 3 * c_nof_twids / 4, -- <= 2**g_addr_w
+ init_sl => '0');
- constant c_twid_file : string :=
+ constant c_twid_file : string :=
"data/twiddle_" & natural'image(c_coeff_w)
& "_" & natural'image(g_index) & ".hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
- --CONSTANT c_twid_file : STRING :=
- -- "../../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
- -- & "_" & NATURAL'IMAGE(g_index) & ".bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
-
- constant c_read_pipeline : natural := 1;
- constant c_mult_pipeline_input : natural := 1; -- 0 or 1
- constant c_mult_pipeline_product : natural := 0; -- 0 or 1
- constant c_mult_pipeline_adder : natural := 1; -- 0 or 1
- constant c_mult_pipeline_output : natural := 1; -- >= 0
- constant c_mult_pipeline : natural := c_mult_pipeline_input + c_mult_pipeline_product + c_mult_pipeline_adder + c_mult_pipeline_output; -- = 3
- constant c_round_pipeline_in : natural := 1;
- constant c_round_pipeline_out : natural := 1;
- constant c_round_pipeline : natural := c_round_pipeline_in + c_round_pipeline_out;
- constant c_pipeline : natural := c_round_pipeline + c_mult_pipeline + c_round_pipeline;
-
- signal reg_val : std_logic_vector(c_pipeline-1 downto 0);
- signal nxt_reg_val : std_logic_vector(reg_val'range);
- signal reg_sync : std_logic_vector(c_pipeline-1 downto 0);
-
- signal nxt_reg_sync : std_logic_vector(reg_sync'range);
-
- signal adr : std_logic_vector(c_adr_w - 1 downto 0);
- signal nxt_adr : std_logic_vector(c_adr_w - 1 downto 0);
-
- signal cnt : std_logic_vector(c_adr_w - 1 downto 0);
- signal nxt_cnt : std_logic_vector(cnt'range);
-
- signal mult_in_re : std_logic_vector(c_mult_in_w - 1 downto 0);
- signal mult_in_im : std_logic_vector(c_mult_in_w - 1 downto 0);
-
- signal mult_out_re : std_logic_vector(c_mult_out_w - 1 downto 0);
- signal mult_out_im : std_logic_vector(c_mult_out_w - 1 downto 0);
-
- signal coeff_dat : std_logic_vector(2 * c_coeff_w - 1 downto 0);
- signal coeff_re : std_logic_vector(c_coeff_w - 1 downto 0);
- signal coeff_im : std_logic_vector(c_coeff_w - 1 downto 0);
+ --CONSTANT c_twid_file : STRING :=
+ -- "../../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
+ -- & "_" & NATURAL'IMAGE(g_index) & ".bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
+
+ constant c_read_pipeline : natural := 1;
+ constant c_mult_pipeline_input : natural := 1; -- 0 or 1
+ constant c_mult_pipeline_product : natural := 0; -- 0 or 1
+ constant c_mult_pipeline_adder : natural := 1; -- 0 or 1
+ constant c_mult_pipeline_output : natural := 1; -- >= 0
+ constant c_mult_pipeline : natural := c_mult_pipeline_input + c_mult_pipeline_product + c_mult_pipeline_adder + c_mult_pipeline_output; -- = 3
+ constant c_round_pipeline_in : natural := 1;
+ constant c_round_pipeline_out : natural := 1;
+ constant c_round_pipeline : natural := c_round_pipeline_in + c_round_pipeline_out;
+ constant c_pipeline : natural := c_round_pipeline + c_mult_pipeline + c_round_pipeline;
+
+ signal reg_val : std_logic_vector(c_pipeline-1 downto 0);
+ signal nxt_reg_val : std_logic_vector(reg_val'range);
+ signal reg_sync : std_logic_vector(c_pipeline-1 downto 0);
+
+ signal nxt_reg_sync : std_logic_vector(reg_sync'range);
+
+ signal adr : std_logic_vector(c_adr_w - 1 downto 0);
+ signal nxt_adr : std_logic_vector(c_adr_w - 1 downto 0);
+
+ signal cnt : std_logic_vector(c_adr_w - 1 downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
+
+ signal mult_in_re : std_logic_vector(c_mult_in_w - 1 downto 0);
+ signal mult_in_im : std_logic_vector(c_mult_in_w - 1 downto 0);
+
+ signal mult_out_re : std_logic_vector(c_mult_out_w - 1 downto 0);
+ signal mult_out_im : std_logic_vector(c_mult_out_w - 1 downto 0);
+
+ signal coeff_dat : std_logic_vector(2 * c_coeff_w - 1 downto 0);
+ signal coeff_re : std_logic_vector(c_coeff_w - 1 downto 0);
+ signal coeff_im : std_logic_vector(c_coeff_w - 1 downto 0);
begin
p_regs : process (clk, rst)
begin
@@ -127,72 +128,72 @@ begin
out_sync <= reg_sync(0);
u_coeff : entity common_lib.common_rom
- generic map (
- g_ram => c_twid_rom,
- g_init_file => c_twid_file
- )
- port map (
- rst => rst,
- clk => clk,
- rd_adr => adr,
- rd_dat => coeff_dat
- );
+ generic map (
+ g_ram => c_twid_rom,
+ g_init_file => c_twid_file
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ rd_adr => adr,
+ rd_dat => coeff_dat
+ );
u_rnd1 : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_mult_in_w
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- out_re => mult_in_re,
- out_im => mult_in_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_mult_in_w
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ out_re => mult_in_re,
+ out_im => mult_in_im,
+ clk => clk
+ );
u_cmult : entity common_mult_lib.common_complex_mult
- generic map (
- g_variant => "IP",
- g_in_a_w => c_mult_in_w,
- g_in_b_w => c_coeff_w,
- g_out_p_w => c_mult_out_w,
- g_conjugate_b => false,
- g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
- g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
- g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
- g_pipeline_output => c_mult_pipeline_output -- >= 0
- )
- port map (
- in_ar => mult_in_re,
- in_ai => mult_in_im,
- in_br => coeff_re,
- in_bi => coeff_im,
- out_pr => mult_out_re,
- out_pi => mult_out_im,
- clk => clk
- );
+ generic map (
+ g_variant => "IP",
+ g_in_a_w => c_mult_in_w,
+ g_in_b_w => c_coeff_w,
+ g_out_p_w => c_mult_out_w,
+ g_conjugate_b => false,
+ g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
+ g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
+ g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
+ g_pipeline_output => c_mult_pipeline_output -- >= 0
+ )
+ port map (
+ in_ar => mult_in_re,
+ in_ai => mult_in_im,
+ in_br => coeff_re,
+ in_bi => coeff_im,
+ out_pr => mult_out_re,
+ out_pi => mult_out_im,
+ clk => clk
+ );
u_rnd2 : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => c_mult_out_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- in_re => mult_out_re,
- in_im => mult_out_im,
- out_re => out_re,
- out_im => out_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => c_mult_out_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ in_re => mult_out_re,
+ in_im => mult_out_im,
+ out_re => out_re,
+ out_im => out_im,
+ clk => clk
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
index e6ab7f98a9..ae154d9d49 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
@@ -24,14 +24,14 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_mult_lib;
library common_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.pft_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.pft_pkg.all;
entity pft_tmult is
generic (
@@ -61,51 +61,52 @@ architecture rtl of pft_tmult is
constant c_coeff_w : natural := c_pft_twiddle_w;
constant c_mult_out_w : natural := c_mult_in_w + c_coeff_w - 1;
- constant c_twid_rom : t_c_mem := (latency => 2,
- adr_w => c_adr_w,
- dat_w => 2 * c_coeff_w, -- complex
- nof_dat => 3 * c_nof_twids / 4, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_twid_rom : t_c_mem := (
+ latency => 2,
+ adr_w => c_adr_w,
+ dat_w => 2 * c_coeff_w, -- complex
+ nof_dat => 3 * c_nof_twids / 4, -- <= 2**g_addr_w
+ init_sl => '0');
- constant c_twid_file : string :=
+ constant c_twid_file : string :=
"data/twiddle_" & natural'image(c_coeff_w)
& "_" & natural'image(g_index) & ".hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
- --CONSTANT c_twid_file : STRING :=
- -- "../../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
- -- & "_" & NATURAL'IMAGE(g_index) & ".bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
-
- constant c_read_pipeline : natural := 1;
- constant c_mult_pipeline_input : natural := 1; -- 0 or 1
- constant c_mult_pipeline_product : natural := 0; -- 0 or 1
- constant c_mult_pipeline_adder : natural := 1; -- 0 or 1
- constant c_mult_pipeline_output : natural := 1; -- >= 0
- constant c_mult_pipeline : natural := c_mult_pipeline_input + c_mult_pipeline_product + c_mult_pipeline_adder + c_mult_pipeline_output; -- = 3
- constant c_round_pipeline_in : natural := 1;
- constant c_round_pipeline_out : natural := 1;
- constant c_round_pipeline : natural := c_round_pipeline_in + c_round_pipeline_out;
- constant c_pipeline : natural := c_round_pipeline + c_mult_pipeline + c_round_pipeline;
-
- signal reg_val : std_logic_vector(c_pipeline-1 downto 0);
- signal nxt_reg_val : std_logic_vector(reg_val'range);
- signal reg_sync : std_logic_vector(c_pipeline-1 downto 0);
-
- signal nxt_reg_sync : std_logic_vector(reg_sync'range);
-
- signal adr : std_logic_vector(c_adr_w - 1 downto 0);
- signal nxt_adr : std_logic_vector(c_adr_w - 1 downto 0);
-
- signal cnt : std_logic_vector(c_adr_w - 1 downto 0);
- signal nxt_cnt : std_logic_vector(cnt'range);
-
- signal mult_in_re : std_logic_vector(c_mult_in_w - 1 downto 0);
- signal mult_in_im : std_logic_vector(c_mult_in_w - 1 downto 0);
-
- signal mult_out_re : std_logic_vector(c_mult_out_w - 1 downto 0);
- signal mult_out_im : std_logic_vector(c_mult_out_w - 1 downto 0);
-
- signal coeff_dat : std_logic_vector(2 * c_coeff_w - 1 downto 0);
- signal coeff_re : std_logic_vector(c_coeff_w - 1 downto 0);
- signal coeff_im : std_logic_vector(c_coeff_w - 1 downto 0);
+ --CONSTANT c_twid_file : STRING :=
+ -- "../../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
+ -- & "_" & NATURAL'IMAGE(g_index) & ".bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
+
+ constant c_read_pipeline : natural := 1;
+ constant c_mult_pipeline_input : natural := 1; -- 0 or 1
+ constant c_mult_pipeline_product : natural := 0; -- 0 or 1
+ constant c_mult_pipeline_adder : natural := 1; -- 0 or 1
+ constant c_mult_pipeline_output : natural := 1; -- >= 0
+ constant c_mult_pipeline : natural := c_mult_pipeline_input + c_mult_pipeline_product + c_mult_pipeline_adder + c_mult_pipeline_output; -- = 3
+ constant c_round_pipeline_in : natural := 1;
+ constant c_round_pipeline_out : natural := 1;
+ constant c_round_pipeline : natural := c_round_pipeline_in + c_round_pipeline_out;
+ constant c_pipeline : natural := c_round_pipeline + c_mult_pipeline + c_round_pipeline;
+
+ signal reg_val : std_logic_vector(c_pipeline-1 downto 0);
+ signal nxt_reg_val : std_logic_vector(reg_val'range);
+ signal reg_sync : std_logic_vector(c_pipeline-1 downto 0);
+
+ signal nxt_reg_sync : std_logic_vector(reg_sync'range);
+
+ signal adr : std_logic_vector(c_adr_w - 1 downto 0);
+ signal nxt_adr : std_logic_vector(c_adr_w - 1 downto 0);
+
+ signal cnt : std_logic_vector(c_adr_w - 1 downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
+
+ signal mult_in_re : std_logic_vector(c_mult_in_w - 1 downto 0);
+ signal mult_in_im : std_logic_vector(c_mult_in_w - 1 downto 0);
+
+ signal mult_out_re : std_logic_vector(c_mult_out_w - 1 downto 0);
+ signal mult_out_im : std_logic_vector(c_mult_out_w - 1 downto 0);
+
+ signal coeff_dat : std_logic_vector(2 * c_coeff_w - 1 downto 0);
+ signal coeff_re : std_logic_vector(c_coeff_w - 1 downto 0);
+ signal coeff_im : std_logic_vector(c_coeff_w - 1 downto 0);
begin
p_regs : process (clk, rst)
begin
@@ -152,72 +153,72 @@ begin
out_sync <= reg_sync(0);
u_coeff : entity common_lib.common_rom
- generic map (
- g_ram => c_twid_rom,
- g_init_file => c_twid_file
- )
- port map (
- rst => rst,
- clk => clk,
- rd_adr => adr,
- rd_dat => coeff_dat
- );
+ generic map (
+ g_ram => c_twid_rom,
+ g_init_file => c_twid_file
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ rd_adr => adr,
+ rd_dat => coeff_dat
+ );
u_rnd1 : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_mult_in_w
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- out_re => mult_in_re,
- out_im => mult_in_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_mult_in_w
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ out_re => mult_in_re,
+ out_im => mult_in_im,
+ clk => clk
+ );
u_cmult : entity common_mult_lib.common_complex_mult
- generic map (
- g_variant => "IP",
- g_in_a_w => c_mult_in_w,
- g_in_b_w => c_coeff_w,
- g_out_p_w => c_mult_out_w,
- g_conjugate_b => false,
- g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
- g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
- g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
- g_pipeline_output => c_mult_pipeline_output -- >= 0
- )
- port map (
- in_ar => mult_in_re,
- in_ai => mult_in_im,
- in_br => coeff_re,
- in_bi => coeff_im,
- out_pr => mult_out_re,
- out_pi => mult_out_im,
- clk => clk
- );
+ generic map (
+ g_variant => "IP",
+ g_in_a_w => c_mult_in_w,
+ g_in_b_w => c_coeff_w,
+ g_out_p_w => c_mult_out_w,
+ g_conjugate_b => false,
+ g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
+ g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
+ g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
+ g_pipeline_output => c_mult_pipeline_output -- >= 0
+ )
+ port map (
+ in_ar => mult_in_re,
+ in_ai => mult_in_im,
+ in_br => coeff_re,
+ in_bi => coeff_im,
+ out_pr => mult_out_re,
+ out_pi => mult_out_im,
+ clk => clk
+ );
u_rnd2 : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => c_mult_out_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- in_re => mult_out_re,
- in_im => mult_out_im,
- out_re => out_re,
- out_im => out_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => c_mult_out_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ in_re => mult_out_re,
+ in_im => mult_out_im,
+ out_re => out_re,
+ out_im => out_im,
+ clk => clk
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd
index 6edd1a89f6..7836e4672b 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd
@@ -1,6 +1,6 @@
library IEEE, common_lib, pft2_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
architecture str of pft_top is
signal reg_in_re : std_logic_vector(g_in_dat_w - 1 downto 0);
@@ -33,23 +33,23 @@ begin
end process;
u_pft : entity pft2_lib.pft
- generic map (
- g_fft_size_w => g_fft_size_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_mode => g_mode
- )
- port map (
- in_re => reg_in_re,
- in_im => reg_in_im,
- in_val => reg_in_val,
- in_sync => reg_in_sync,
- switch_en => switch_en,
- out_re => d_out_re,
- out_im => d_out_im,
- out_val => d_out_val,
- out_sync => d_out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_fft_size_w => g_fft_size_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_mode => g_mode
+ )
+ port map (
+ in_re => reg_in_re,
+ in_im => reg_in_im,
+ in_val => reg_in_val,
+ in_sync => reg_in_sync,
+ switch_en => switch_en,
+ out_re => d_out_re,
+ out_im => d_out_im,
+ out_val => d_out_val,
+ out_sync => d_out_sync,
+ clk => clk,
+ rst => rst
+ );
end str;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
index f6d0eeb201..80f58fd09b 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
@@ -1,9 +1,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib;
-use pft2_lib.pft_pkg.all;
+ use pft2_lib.pft_pkg.all;
entity pft_top is
generic (
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
index e12c3622fe..6145d43245 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
@@ -1,23 +1,23 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib;
-use pft2_lib.all;
+ use pft2_lib.all;
architecture rtl of pft_unswitch is
-signal cnt : std_logic_vector(g_fft_sz_w downto 0);
-signal nxt_cnt : std_logic_vector(cnt'range);
+ signal cnt : std_logic_vector(g_fft_sz_w downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
-signal lfsr_bit1 : std_logic;
-signal lfsr_bit2 : std_logic;
+ signal lfsr_bit1 : std_logic;
+ signal lfsr_bit2 : std_logic;
-signal lfsr_en : std_logic;
+ signal lfsr_en : std_logic;
-signal nxt_out_val : std_logic;
-signal nxt_out_sync : std_logic;
-signal nxt_out_re : std_logic_vector(in_re'range);
-signal nxt_out_im : std_logic_vector(in_im'range);
+ signal nxt_out_val : std_logic;
+ signal nxt_out_sync : std_logic;
+ signal nxt_out_re : std_logic_vector(in_re'range);
+ signal nxt_out_im : std_logic_vector(in_im'range);
begin
registers : process (rst, clk)
begin
@@ -62,18 +62,18 @@ begin
nxt_out_re <= in_re;
nxt_out_im <= in_im;
if ((cnt(0) = '0' and cnt(cnt'high) = lfsr_bit1)
- or (cnt(0) = '1' and cnt(cnt'high) = lfsr_bit2)) and (switch_en = '1') then
- nxt_out_re <= std_logic_vector(-signed(in_re));
- nxt_out_im <= std_logic_vector(-signed(in_im));
+ or (cnt(0) = '1' and cnt(cnt'high) = lfsr_bit2)) and (switch_en = '1') then
+ nxt_out_re <= std_logic_vector(-signed(in_re));
+ nxt_out_im <= std_logic_vector(-signed(in_im));
end if;
end process;
lfsr: entity pft2_lib.pft_lfsr
- port map (
- clk => clk,
- rst => rst,
- in_en => lfsr_en,
- out_bit1 => lfsr_bit1,
- out_bit2 => lfsr_bit2
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_en => lfsr_en,
+ out_bit1 => lfsr_bit1,
+ out_bit2 => lfsr_bit2
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
index 726636e03b..a2b0c3a6b6 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pft_unswitch is
generic (
@@ -48,18 +48,18 @@ entity pft_unswitch is
end pft_unswitch;
architecture rtl of pft_unswitch is
-signal cnt : std_logic_vector(g_fft_sz_w downto 0);
-signal nxt_cnt : std_logic_vector(cnt'range);
+ signal cnt : std_logic_vector(g_fft_sz_w downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
-signal lfsr_bit1 : std_logic;
-signal lfsr_bit2 : std_logic;
+ signal lfsr_bit1 : std_logic;
+ signal lfsr_bit2 : std_logic;
-signal lfsr_en : std_logic;
+ signal lfsr_en : std_logic;
-signal nxt_out_val : std_logic;
-signal nxt_out_sync : std_logic;
-signal nxt_out_re : std_logic_vector(in_re'range);
-signal nxt_out_im : std_logic_vector(in_im'range);
+ signal nxt_out_val : std_logic;
+ signal nxt_out_sync : std_logic;
+ signal nxt_out_re : std_logic_vector(in_re'range);
+ signal nxt_out_im : std_logic_vector(in_im'range);
begin
registers : process (rst, clk)
begin
@@ -104,18 +104,18 @@ begin
nxt_out_re <= in_re;
nxt_out_im <= in_im;
if ((cnt(0) = '0' and cnt(cnt'high) = lfsr_bit1)
- or (cnt(0) = '1' and cnt(cnt'high) = lfsr_bit2)) and (switch_en = '1') then
- nxt_out_re <= std_logic_vector(-signed(in_re));
- nxt_out_im <= std_logic_vector(-signed(in_im));
+ or (cnt(0) = '1' and cnt(cnt'high) = lfsr_bit2)) and (switch_en = '1') then
+ nxt_out_re <= std_logic_vector(-signed(in_re));
+ nxt_out_im <= std_logic_vector(-signed(in_im));
end if;
end process;
lfsr: entity work.pft_lfsr
- port map (
- clk => clk,
- rst => rst,
- in_en => lfsr_en,
- out_bit1 => lfsr_bit1,
- out_bit2 => lfsr_bit2
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_en => lfsr_en,
+ out_bit1 => lfsr_bit1,
+ out_bit2 => lfsr_bit2
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
index 5294b0a66b..c1c5418bd7 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
@@ -1,7 +1,7 @@
library ieee, pfs_lib, pft2_lib, tst_lib;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use pft2_lib.pft_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use pft2_lib.pft_pkg.all;
entity tb_pft is
generic (
@@ -41,9 +41,9 @@ architecture tb of tb_pft is
signal out_val : std_logic;
signal out_sync : std_logic;
--- SIGNAL ref_re : STD_LOGIC_VECTOR(g_out_w-1 DOWNTO 0);
--- SIGNAL ref_im : STD_LOGIC_VECTOR(g_out_w-1 DOWNTO 0);
--- SIGNAL ref_val : STD_LOGIC;
+ -- SIGNAL ref_re : STD_LOGIC_VECTOR(g_out_w-1 DOWNTO 0);
+ -- SIGNAL ref_im : STD_LOGIC_VECTOR(g_out_w-1 DOWNTO 0);
+ -- SIGNAL ref_val : STD_LOGIC;
begin
rst <= '0' after g_rst_period;
val <= '1' after g_rst_period + g_clk_period / 2;
@@ -51,89 +51,89 @@ begin
clk <= not clk after g_clk_period / 2;
in_dat: entity tst_lib.tst_input
- generic map (
- g_file_name => c_pft_in_file,
- g_data_width => g_in_w
- )
- port map (
- clk => clk,
- rst => rst,
- en => '1',
- out_dat1 => in_x,
- out_dat2 => in_y,
- out_val => open -- in_val
- );
+ generic map (
+ g_file_name => c_pft_in_file,
+ g_data_width => g_in_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => '1',
+ out_dat1 => in_x,
+ out_dat2 => in_y,
+ out_val => open -- in_val
+ );
in_val <= val;
in_sync <= '0';
pfs : entity pfs_lib.pfs
- generic map (
- g_nof_bands => 2**g_fft_size_w, -- 2*g_nof_subbands,
- g_nof_taps => 2**g_fft_size_w * 16, -- 2*16*g_nof_subbands,
- g_in_dat_w => g_in_w,
- g_out_dat_w => g_pfs_w,
- g_coef_dat_w => g_pfs_coef_w
- )
- port map (
- in_dat_x => in_x,
- in_dat_y => in_y,
- in_val => in_val,
- in_sync => in_sync,
- out_dat_x => pfs_x,
- out_dat_y => pfs_y,
- out_val => pfs_val,
- out_sync => pfs_sync,
- clk => clk,
- rst => rst,
- restart => '0'
- );
+ generic map (
+ g_nof_bands => 2**g_fft_size_w, -- 2*g_nof_subbands,
+ g_nof_taps => 2**g_fft_size_w * 16, -- 2*16*g_nof_subbands,
+ g_in_dat_w => g_in_w,
+ g_out_dat_w => g_pfs_w,
+ g_coef_dat_w => g_pfs_coef_w
+ )
+ port map (
+ in_dat_x => in_x,
+ in_dat_y => in_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_dat_x => pfs_x,
+ out_dat_y => pfs_y,
+ out_val => pfs_val,
+ out_sync => pfs_sync,
+ clk => clk,
+ rst => rst,
+ restart => '0'
+ );
pft : entity pft2_lib.pft
- generic map (
- g_fft_size_w => g_fft_size_w,
- g_in_dat_w => g_pfs_w,
- g_out_dat_w => g_out_w,
- g_mode => PFT_MODE_REAL2
- )
- port map (
- in_re => pfs_x,
- in_im => pfs_y,
- in_val => pfs_val,
- in_sync => pfs_sync,
- switch_en => '1',
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_fft_size_w => g_fft_size_w,
+ g_in_dat_w => g_pfs_w,
+ g_out_dat_w => g_out_w,
+ g_mode => PFT_MODE_REAL2
+ )
+ port map (
+ in_re => pfs_x,
+ in_im => pfs_y,
+ in_val => pfs_val,
+ in_sync => pfs_sync,
+ switch_en => '1',
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
--- out_dat: ENTITY tst_lib.tst_output
--- GENERIC MAP (
--- g_file_name => c_pft_out_file,
--- g_data_width => out_re'LENGTH
--- )
--- PORT MAP (
--- clk => clk,
--- rst => rst,
--- in_dat1 => out_re,
--- in_dat2 => out_im,
--- in_val => out_val
--- );
+ -- out_dat: ENTITY tst_lib.tst_output
+ -- GENERIC MAP (
+ -- g_file_name => c_pft_out_file,
+ -- g_data_width => out_re'LENGTH
+ -- )
+ -- PORT MAP (
+ -- clk => clk,
+ -- rst => rst,
+ -- in_dat1 => out_re,
+ -- in_dat2 => out_im,
+ -- in_val => out_val
+ -- );
--- ref_dat: ENTITY tst_lib.tst_input
--- GENERIC MAP (
--- g_file_name => c_pft_ref_file,
--- g_data_width => ref_re'LENGTH
--- )
--- PORT MAP (
--- clk => clk,
--- rst => rst,
--- en => out_val,
--- out_dat1 => ref_re,
--- out_dat2 => ref_im,
--- out_val => ref_val
--- );
+ -- ref_dat: ENTITY tst_lib.tst_input
+ -- GENERIC MAP (
+ -- g_file_name => c_pft_ref_file,
+ -- g_data_width => ref_re'LENGTH
+ -- )
+ -- PORT MAP (
+ -- clk => clk,
+ -- rst => rst,
+ -- en => out_val,
+ -- out_dat1 => ref_re,
+ -- out_dat2 => ref_im,
+ -- out_val => ref_val
+ -- );
end tb;
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
index 7c4aa160e9..d713c22b7d 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
@@ -32,11 +32,11 @@
-- - The tb works OK for all three PFT modes.
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.pft_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.pft_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_pft2 is
generic (
@@ -235,9 +235,10 @@ architecture tb of tb_pft2 is
return to_integer(ur);
end func_bitrev;
- procedure proc_fft_bitrev(en : in std_logic;
- ref : in t_ref_dat;
- signal sr : out t_ref_fft_dat) is
+ procedure proc_fft_bitrev(
+ en : in std_logic;
+ ref : in t_ref_dat;
+ signal sr : out t_ref_fft_dat) is
constant N : natural := c_fft_size;
constant w : natural := c_fft_size_w;
variable r : natural;
@@ -251,9 +252,10 @@ architecture tb of tb_pft2 is
end proc_fft_bitrev;
-- PFT_MODE_COMPLEX
- procedure proc_fft_complex(en : in std_logic;
- ref : in t_ref_dat;
- signal sr : out t_ref_fft_dat) is
+ procedure proc_fft_complex(
+ en : in std_logic;
+ ref : in t_ref_dat;
+ signal sr : out t_ref_fft_dat) is
constant N : natural := c_fft_size;
begin
if en = '1' then
@@ -269,10 +271,11 @@ architecture tb of tb_pft2 is
-- . PFT seperate does not divide by 2 in Xa(m) = [X*(N-m) + X(m)]/2, Xb(m)=j[X*(N-m) - X(m)]/2
-- . PFT seperate result for m=N is same as for m=0
-- . PFT seperate puts real result for m=N/2 in imag of m=0
- procedure proc_fft_real2_im(en : in std_logic;
- re : in t_ref_dat;
- im : in t_ref_dat;
- signal sr : out t_ref_real2_dat) is
+ procedure proc_fft_real2_im(
+ en : in std_logic;
+ re : in t_ref_dat;
+ im : in t_ref_dat;
+ signal sr : out t_ref_real2_dat) is
constant N : natural := c_fft_size;
variable lo : integer;
variable hi : integer;
@@ -287,9 +290,10 @@ architecture tb of tb_pft2 is
end if;
end proc_fft_real2_im;
- procedure proc_fft_real2_re(en : in std_logic;
- re : in t_ref_dat;
- signal sr : out t_ref_real2_dat) is
+ procedure proc_fft_real2_re(
+ en : in std_logic;
+ re : in t_ref_dat;
+ signal sr : out t_ref_real2_dat) is
constant N : natural := c_fft_size;
variable lo : integer;
variable hi : integer;
@@ -327,104 +331,104 @@ begin
-----------------------------------------------------------------------------
u_in_x: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_in_x,
- g_file_repeat => g_repeat,
- g_nof_data => 1,
- g_data_width => c_in_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_en,
- out_dat => in_dat_x,
- out_val => in_val_x
- );
+ generic map (
+ g_file_name => c_file_pft_in_x,
+ g_file_repeat => g_repeat,
+ g_nof_data => 1,
+ g_data_width => c_in_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_en,
+ out_dat => in_dat_x,
+ out_val => in_val_x
+ );
u_in_y: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_in_y,
- g_file_repeat => g_repeat,
- g_nof_data => 1,
- g_data_width => c_in_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_en,
- out_dat => in_dat_y,
- out_val => in_val_y
- );
+ generic map (
+ g_file_name => c_file_pft_in_y,
+ g_file_repeat => g_repeat,
+ g_nof_data => 1,
+ g_data_width => c_in_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_en,
+ out_dat => in_dat_y,
+ out_val => in_val_y
+ );
-----------------------------------------------------------------------------
-- Read expected Xre, Xim, Yre, Yim data
-----------------------------------------------------------------------------
u_ref_x_re: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_ref_x_re,
- g_file_repeat => 1,
- g_nof_data => 1,
- g_data_width => c_file_pft_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => ref_en,
- out_dat => ref_dat_x_re,
- out_val => ref_val_x_re
- );
+ generic map (
+ g_file_name => c_file_pft_ref_x_re,
+ g_file_repeat => 1,
+ g_nof_data => 1,
+ g_data_width => c_file_pft_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => ref_en,
+ out_dat => ref_dat_x_re,
+ out_val => ref_val_x_re
+ );
u_ref_x_im: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_ref_x_im,
- g_file_repeat => 1,
- g_nof_data => 1,
- g_data_width => c_file_pft_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => ref_en,
- out_dat => ref_dat_x_im,
- out_val => ref_val_x_im
- );
+ generic map (
+ g_file_name => c_file_pft_ref_x_im,
+ g_file_repeat => 1,
+ g_nof_data => 1,
+ g_data_width => c_file_pft_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => ref_en,
+ out_dat => ref_dat_x_im,
+ out_val => ref_val_x_im
+ );
u_ref_y_re: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_ref_y_re,
- g_file_repeat => 1,
- g_nof_data => 1,
- g_data_width => c_file_pft_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => ref_en,
- out_dat => ref_dat_y_re,
- out_val => ref_val_y_re
- );
+ generic map (
+ g_file_name => c_file_pft_ref_y_re,
+ g_file_repeat => 1,
+ g_nof_data => 1,
+ g_data_width => c_file_pft_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => ref_en,
+ out_dat => ref_dat_y_re,
+ out_val => ref_val_y_re
+ );
u_ref_y_im: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_ref_y_im,
- g_file_repeat => 1,
- g_nof_data => 1,
- g_data_width => c_file_pft_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => ref_en,
- out_dat => ref_dat_y_im,
- out_val => ref_val_y_im
- );
+ generic map (
+ g_file_name => c_file_pft_ref_y_im,
+ g_file_repeat => 1,
+ g_nof_data => 1,
+ g_data_width => c_file_pft_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => ref_en,
+ out_dat => ref_dat_y_im,
+ out_val => ref_val_y_im
+ );
p_ref_reg : process(clk)
begin
@@ -498,106 +502,106 @@ begin
begin
if diff_rdy = '1' then
if diff_max_fft_re <= c_diff_max then report "FFT real output for re " & g_name_x & " and im " & g_name_y & " is OK" severity NOTE;
- else report "FFT real output for re " & g_name_x & " and im " & g_name_y & " is wrong" severity ERROR; end if;
- if diff_max_fft_im <= c_diff_max then report "FFT imag output for im " & g_name_x & " and im " & g_name_y & " is OK" severity NOTE;
- else report "FFT imag output for im " & g_name_x & " and im " & g_name_y & " is wrong" severity ERROR; end if;
- end if;
- end process;
- end generate;
-
- gen_diff_real2 : if g_pft_mode = PFT_MODE_REAL2 generate
- nxt_diff_cnt <= diff_cnt + 1 when out_val_dly = '1' and toggle_dly = '1' and diff_cnt < c_fft_size / 2 - 1 else
- 0 when out_val_dly = '1' and toggle_dly = '1' and diff_cnt = c_fft_size / 2 - 1 else
- diff_cnt;
- nxt_diff_rdy <= '1' when diff_cnt = c_fft_size / 2 - 1 else '0';
-
- diff_x_re <= 0 when out_val_dly = '0' else ref_real2_dat_x_re(diff_cnt) - out_x_re when toggle_dly = '0' else diff_x_re;
- diff_x_im <= 0 when out_val_dly = '0' else ref_real2_dat_x_im(diff_cnt) - out_x_im when toggle_dly = '0' else diff_x_im;
- diff_y_re <= 0 when out_val_dly = '0' else ref_real2_dat_y_re(diff_cnt) - out_y_re when toggle_dly = '1' else diff_y_re;
- diff_y_im <= 0 when out_val_dly = '0' else ref_real2_dat_y_im(diff_cnt) - out_y_im when toggle_dly = '1' else diff_y_im;
-
- diff_max_x_re <= largest(abs(diff_x_re), diff_max_x_re);
- diff_max_x_im <= largest(abs(diff_x_im), diff_max_x_im);
- diff_max_y_re <= largest(abs(diff_y_re), diff_max_y_re);
- diff_max_y_im <= largest(abs(diff_y_im), diff_max_y_im);
-
- assert diff_max_x_re <= c_diff_max report "FFT X re output differs too much from reference data" severity ERROR;
- assert diff_max_x_im <= c_diff_max report "FFT X im output differs too much from reference data" severity ERROR;
- assert diff_max_y_re <= c_diff_max report "FFT Y re output differs too much from reference data" severity ERROR;
- assert diff_max_y_im <= c_diff_max report "FFT Y im output differs too much from reference data" severity ERROR;
-
- p_report : process(diff_rdy)
- begin
- if diff_rdy = '1' then
- if diff_max_x_re <= c_diff_max then report "FFT X real output for " & g_name_x & " is OK" severity NOTE;
- else report "FFT X real output for " & g_name_x & " is wrong" severity ERROR; end if;
- if diff_max_x_im <= c_diff_max then report "FFT X imag output for " & g_name_x & " is OK" severity NOTE;
- else report "FFT X imag output for " & g_name_x & " is wrong" severity ERROR; end if;
- if diff_max_y_re <= c_diff_max then report "FFT Y real output for " & g_name_y & " is OK" severity NOTE;
- else report "FFT Y real output for " & g_name_y & " is wrong" severity ERROR; end if;
- if diff_max_y_im <= c_diff_max then report "FFT Y imag output for " & g_name_y & " is OK" severity NOTE;
- else report "FFT Y imag output for " & g_name_y & " is wrong" severity ERROR; end if;
- end if;
- end process;
- end generate;
-
- diff_val <= out_val_dly;
-
- -----------------------------------------------------------------------------
- -- PFT
- -----------------------------------------------------------------------------
-
- u_pft : entity work.pft
- generic map (
- g_fft_size_w => c_fft_size_w,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w,
- g_stage_dat_w => g_stage_dat_w,
- g_mode => g_pft_mode
- )
- port map (
- in_re => in_dat_x,
- in_im => in_dat_y,
- in_val => in_val,
- in_sync => in_sync,
- switch_en => g_switch_en,
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
-
- p_pft_reg : process(clk)
- begin
- if rising_edge(clk) then
- toggle <= nxt_toggle;
- toggle_dly <= toggle;
- out_re_dly <= out_re;
- out_im_dly <= out_im;
- out_val_dly <= out_val;
- out_fft_re <= nxt_out_fft_re;
- out_fft_im <= nxt_out_fft_im;
- out_x_re <= nxt_out_x_re;
- out_y_re <= nxt_out_y_re;
- out_x_im <= nxt_out_x_im;
- out_y_im <= nxt_out_y_im;
- end if;
- end process;
-
- nxt_toggle <= '0' when out_val = '0' else not toggle;
-
- gen_out_fft : if g_pft_mode = PFT_MODE_BITREV or g_pft_mode = PFT_MODE_COMPLEX generate
- nxt_out_fft_re <= 0 when out_val = '0' else to_integer(signed(out_re));
- nxt_out_fft_im <= 0 when out_val = '0' else to_integer(signed(out_im));
- end generate;
-
- gen_out_real2 : if g_pft_mode = PFT_MODE_REAL2 generate
- nxt_out_x_re <= 0 when out_val = '0' else to_integer(signed(out_re)) when toggle = '0' else out_x_re;
- nxt_out_y_re <= 0 when out_val = '0' else to_integer(signed(out_re)) when toggle = '1' else out_y_re;
- nxt_out_x_im <= 0 when out_val = '0' else to_integer(signed(out_im)) when toggle = '0' else out_x_im;
- nxt_out_y_im <= 0 when out_val = '0' else to_integer(signed(out_im)) when toggle = '1' else out_y_im;
- end generate;
-
-end tb;
+ else report "FFT real output for re " & g_name_x & " and im " & g_name_y & " is wrong" severity ERROR; end if;
+ if diff_max_fft_im <= c_diff_max then report "FFT imag output for im " & g_name_x & " and im " & g_name_y & " is OK" severity NOTE;
+ else report "FFT imag output for im " & g_name_x & " and im " & g_name_y & " is wrong" severity ERROR; end if;
+ end if;
+ end process;
+ end generate;
+
+ gen_diff_real2 : if g_pft_mode = PFT_MODE_REAL2 generate
+ nxt_diff_cnt <= diff_cnt + 1 when out_val_dly = '1' and toggle_dly = '1' and diff_cnt < c_fft_size / 2 - 1 else
+ 0 when out_val_dly = '1' and toggle_dly = '1' and diff_cnt = c_fft_size / 2 - 1 else
+ diff_cnt;
+ nxt_diff_rdy <= '1' when diff_cnt = c_fft_size / 2 - 1 else '0';
+
+ diff_x_re <= 0 when out_val_dly = '0' else ref_real2_dat_x_re(diff_cnt) - out_x_re when toggle_dly = '0' else diff_x_re;
+ diff_x_im <= 0 when out_val_dly = '0' else ref_real2_dat_x_im(diff_cnt) - out_x_im when toggle_dly = '0' else diff_x_im;
+ diff_y_re <= 0 when out_val_dly = '0' else ref_real2_dat_y_re(diff_cnt) - out_y_re when toggle_dly = '1' else diff_y_re;
+ diff_y_im <= 0 when out_val_dly = '0' else ref_real2_dat_y_im(diff_cnt) - out_y_im when toggle_dly = '1' else diff_y_im;
+
+ diff_max_x_re <= largest(abs(diff_x_re), diff_max_x_re);
+ diff_max_x_im <= largest(abs(diff_x_im), diff_max_x_im);
+ diff_max_y_re <= largest(abs(diff_y_re), diff_max_y_re);
+ diff_max_y_im <= largest(abs(diff_y_im), diff_max_y_im);
+
+ assert diff_max_x_re <= c_diff_max report "FFT X re output differs too much from reference data" severity ERROR;
+ assert diff_max_x_im <= c_diff_max report "FFT X im output differs too much from reference data" severity ERROR;
+ assert diff_max_y_re <= c_diff_max report "FFT Y re output differs too much from reference data" severity ERROR;
+ assert diff_max_y_im <= c_diff_max report "FFT Y im output differs too much from reference data" severity ERROR;
+
+ p_report : process(diff_rdy)
+ begin
+ if diff_rdy = '1' then
+ if diff_max_x_re <= c_diff_max then report "FFT X real output for " & g_name_x & " is OK" severity NOTE;
+ else report "FFT X real output for " & g_name_x & " is wrong" severity ERROR; end if;
+ if diff_max_x_im <= c_diff_max then report "FFT X imag output for " & g_name_x & " is OK" severity NOTE;
+ else report "FFT X imag output for " & g_name_x & " is wrong" severity ERROR; end if;
+ if diff_max_y_re <= c_diff_max then report "FFT Y real output for " & g_name_y & " is OK" severity NOTE;
+ else report "FFT Y real output for " & g_name_y & " is wrong" severity ERROR; end if;
+ if diff_max_y_im <= c_diff_max then report "FFT Y imag output for " & g_name_y & " is OK" severity NOTE;
+ else report "FFT Y imag output for " & g_name_y & " is wrong" severity ERROR; end if;
+ end if;
+ end process;
+ end generate;
+
+ diff_val <= out_val_dly;
+
+ -----------------------------------------------------------------------------
+ -- PFT
+ -----------------------------------------------------------------------------
+
+ u_pft : entity work.pft
+ generic map (
+ g_fft_size_w => c_fft_size_w,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w,
+ g_stage_dat_w => g_stage_dat_w,
+ g_mode => g_pft_mode
+ )
+ port map (
+ in_re => in_dat_x,
+ in_im => in_dat_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ switch_en => g_switch_en,
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
+
+ p_pft_reg : process(clk)
+ begin
+ if rising_edge(clk) then
+ toggle <= nxt_toggle;
+ toggle_dly <= toggle;
+ out_re_dly <= out_re;
+ out_im_dly <= out_im;
+ out_val_dly <= out_val;
+ out_fft_re <= nxt_out_fft_re;
+ out_fft_im <= nxt_out_fft_im;
+ out_x_re <= nxt_out_x_re;
+ out_y_re <= nxt_out_y_re;
+ out_x_im <= nxt_out_x_im;
+ out_y_im <= nxt_out_y_im;
+ end if;
+ end process;
+
+ nxt_toggle <= '0' when out_val = '0' else not toggle;
+
+ gen_out_fft : if g_pft_mode = PFT_MODE_BITREV or g_pft_mode = PFT_MODE_COMPLEX generate
+ nxt_out_fft_re <= 0 when out_val = '0' else to_integer(signed(out_re));
+ nxt_out_fft_im <= 0 when out_val = '0' else to_integer(signed(out_im));
+ end generate;
+
+ gen_out_real2 : if g_pft_mode = PFT_MODE_REAL2 generate
+ nxt_out_x_re <= 0 when out_val = '0' else to_integer(signed(out_re)) when toggle = '0' else out_x_re;
+ nxt_out_y_re <= 0 when out_val = '0' else to_integer(signed(out_re)) when toggle = '1' else out_y_re;
+ nxt_out_x_im <= 0 when out_val = '0' else to_integer(signed(out_im)) when toggle = '0' else out_x_im;
+ nxt_out_y_im <= 0 when out_val = '0' else to_integer(signed(out_im)) when toggle = '1' else out_y_im;
+ end generate;
+
+ end tb;
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
index cdc09c717a..2b5d68a7d4 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
@@ -1,10 +1,10 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib,common_lib;
-use pft2_lib.pft_pkg.all;
-use common_lib.common_pkg.all;
+ use pft2_lib.pft_pkg.all;
+ use common_lib.common_pkg.all;
entity tb_pft is
end tb_pft;
@@ -44,39 +44,39 @@ begin
cnt <= (others => '0');
elsif rising_edge(clk) then
cnt <= nxt_cnt;
- end if;
+ end if;
end process;
nxt_cnt <= std_logic_vector(unsigned(cnt) + 1) when in_sync = '0' else (others => '0');
pft : entity work.pft
- generic map (
- g_fft_size_w => g_fft_size_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_mode => PFT_MODE_REAL2
- )
- port map (
- in_re => in_x,
- in_im => in_y,
- in_val => in_val,
- in_sync => in_sync,
- switch_en => switch_en,
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_fft_size_w => g_fft_size_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_mode => PFT_MODE_REAL2
+ )
+ port map (
+ in_re => in_x,
+ in_im => in_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ switch_en => switch_en,
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
clk <= not(clk) after clk_period / 2;
rst <= '0' after rst_period;
switch_en <= '0';
--- in_sync <= '1' WHEN UNSIGNED(cnt)=g_pps_ps-1 ELSE '0';
--- in_val <= '1' WHEN UNSIGNED(cnt)=732;
+ -- in_sync <= '1' WHEN UNSIGNED(cnt)=g_pps_ps-1 ELSE '0';
+ -- in_val <= '1' WHEN UNSIGNED(cnt)=732;
input_ctrl : process
begin
@@ -91,7 +91,7 @@ begin
-- val
wait until unsigned(cnt) = 1024;
--- WAIT UNTIL UNSIGNED(cnt)=731;
+ -- WAIT UNTIL UNSIGNED(cnt)=731;
in_val <= '1';
for J in 1 to 10 loop
@@ -109,28 +109,28 @@ begin
wait;
end process;
--- -----------------------------------------------------------------------------
--- --
--- -- X = Y is sliding impulse
--- --
--- -----------------------------------------------------------------------------
--- in_gen: PROCESS
--- BEGIN
--- FOR I IN 0 TO g_fft_size-1 LOOP -- Slide impulse
--- FOR J IN 1 TO 1 LOOP -- Repeat impulse
--- IF in_val='1' THEN
--- WAIT UNTIL UNSIGNED(nxt_cnt(g_fft_size_w-1 DOWNTO 0))=I;
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w));
--- WAIT FOR clk_period;
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w));
--- WAIT FOR clk_period;
--- ELSE
--- WAIT UNTIL in_val='1';
--- END IF;
--- END LOOP;
--- END LOOP;
--- END PROCESS;
--- in_y <= in_x;
+ -- -----------------------------------------------------------------------------
+ -- --
+ -- -- X = Y is sliding impulse
+ -- --
+ -- -----------------------------------------------------------------------------
+ -- in_gen: PROCESS
+ -- BEGIN
+ -- FOR I IN 0 TO g_fft_size-1 LOOP -- Slide impulse
+ -- FOR J IN 1 TO 1 LOOP -- Repeat impulse
+ -- IF in_val='1' THEN
+ -- WAIT UNTIL UNSIGNED(nxt_cnt(g_fft_size_w-1 DOWNTO 0))=I;
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w));
+ -- WAIT FOR clk_period;
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w));
+ -- WAIT FOR clk_period;
+ -- ELSE
+ -- WAIT UNTIL in_val='1';
+ -- END IF;
+ -- END LOOP;
+ -- END LOOP;
+ -- END PROCESS;
+ -- in_y <= in_x;
-----------------------------------------------------------------------------
--
@@ -145,40 +145,40 @@ begin
elsif rising_edge(clk) then
if cnt(0) = '1' then
if in_val = '1' then
- in_x <= std_logic_vector(-signed(in_x));
- in_y <= std_logic_vector(signed(in_y));
+ in_x <= std_logic_vector(-signed(in_x));
+ in_y <= std_logic_vector(signed(in_y));
end if;
end if;
end if;
end process;
--- -----------------------------------------------------------------------------
--- --
--- -- X, Y is impulse 0, impulse 1 or DC
--- --
--- -----------------------------------------------------------------------------
--- --dc <= 0;
--- dc <= 300;
--- in_gen: PROCESS (clk,rst)
--- BEGIN
--- IF rst='1' THEN
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w));
--- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w));
--- ELSIF rising_edge(clk) THEN
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w));
--- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w));
--- IF UNSIGNED(nxt_cnt(g_fft_size_w-1 DOWNTO 0))=0 THEN
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w)); -- DC 0
--- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w)); -- DC
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 0
--- -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 0
--- END IF;
--- IF UNSIGNED(nxt_cnt(g_fft_size_w-1 DOWNTO 0))=1 THEN
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w)); -- DC 0
--- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w)); -- DC
--- -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 1
--- -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 1
--- END IF;
--- END IF;
--- END PROCESS;
+ -- -----------------------------------------------------------------------------
+ -- --
+ -- -- X, Y is impulse 0, impulse 1 or DC
+ -- --
+ -- -----------------------------------------------------------------------------
+ -- --dc <= 0;
+ -- dc <= 300;
+ -- in_gen: PROCESS (clk,rst)
+ -- BEGIN
+ -- IF rst='1' THEN
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w));
+ -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w));
+ -- ELSIF rising_edge(clk) THEN
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w));
+ -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w));
+ -- IF UNSIGNED(nxt_cnt(g_fft_size_w-1 DOWNTO 0))=0 THEN
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w)); -- DC 0
+ -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w)); -- DC
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 0
+ -- -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 0
+ -- END IF;
+ -- IF UNSIGNED(nxt_cnt(g_fft_size_w-1 DOWNTO 0))=1 THEN
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w)); -- DC 0
+ -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w)); -- DC
+ -- -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 1
+ -- -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 1
+ -- END IF;
+ -- END IF;
+ -- END PROCESS;
end tb;
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
index 48440aff87..793c2d2201 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
@@ -25,7 +25,7 @@
-- Description:
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_pft2 is
end tb_tb_pft2;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
index 36aaca529e..cf86f9d878 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_adc_6ch_200MHz is
generic (
@@ -75,7 +75,7 @@ entity lofar2_unb2b_adc_6ch_200MHz is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -107,52 +107,52 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_adc_lib.lofar2_unb2b_adc
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_jesd_freq => g_jesd_freq,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_jesd_freq => g_jesd_freq,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
index d1e33a7ff0..763ac32b9a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
@@ -28,11 +28,11 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_lofar2_unb2b_adc_6ch_200MHz is
end tb_lofar2_unb2b_adc_6ch_200MHz;
@@ -105,48 +105,48 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc_6ch_200MHz : entity work.lofar2_unb2b_adc_6ch_200MHz
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- BCK_RX => bck_rx,
- BCK_REF_CLK => bck_ref_clk,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ BCK_RX => bck_rx,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
index 7e46728d34..eb9d868354 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_adc_full is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2b_adc_full is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_adc_lib.lofar2_unb2b_adc
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
index 02076e8cc8..ece17b0efc 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
@@ -29,11 +29,11 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_lofar2_unb2b_adc_full is
end tb_lofar2_unb2b_adc_full;
@@ -106,48 +106,48 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc_full : entity work.lofar2_unb2b_adc_full
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- BCK_RX => bck_rx,
- BCK_REF_CLK => bck_ref_clk,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ BCK_RX => bck_rx,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
index 88acdb6b71..2b3bb307cd 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 1 ADC stream
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_adc_one_node is
generic (
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_adc_lib.lofar2_unb2b_adc
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
index 768efa68b7..9fec5faffc 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
@@ -29,11 +29,11 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_lofar2_unb2b_adc_one_node is
end tb_lofar2_unb2b_adc_one_node;
@@ -106,48 +106,48 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc_one_node : entity work.lofar2_unb2b_adc_one_node
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- BCK_RX => bck_rx,
- BCK_REF_CLK => bck_ref_clk,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ BCK_RX => bck_rx,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index f23f05116a..e2de8fc79a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -26,15 +26,15 @@
-- Use revisions to select one_node or full versions
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.lofar2_unb2b_adc_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.lofar2_unb2b_adc_pkg.all;
entity lofar2_unb2b_adc is
generic (
@@ -81,9 +81,9 @@ entity lofar2_unb2b_adc is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -228,209 +228,209 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- ram_scrap_mosi => c_mem_mosi_rst,
- ram_scrap_miso => open,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ ram_scrap_mosi => c_mem_mosi_rst,
+ ram_scrap_miso => open,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2b_adc
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Jesd reset control
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Jesd reset control
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- mm interfaces for control
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso
+ );
-----------------------------------------------------------------------------
-- node_adc_input_and_timing (AIT)
@@ -438,75 +438,75 @@ begin
-----------------------------------------------------------------------------
u_ait: entity work.node_adc_input_and_timing
- generic map(
- g_nof_streams => c_nof_streams,
- g_jesd_freq => g_jesd_freq,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => alt_sosi_arr
- );
-
- u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map(
+ g_nof_streams => c_nof_streams,
+ g_jesd_freq => g_jesd_freq,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => alt_sosi_arr
+ );
+
+ u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
index 27c3add615..f647fc38b4 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
@@ -20,12 +20,12 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package lofar2_unb2b_adc_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
index daffa485ac..d1c1211cef 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_adc_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_adc_pkg.all;
entity mmm_lofar2_unb2b_adc is
generic (
@@ -152,63 +152,83 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
-
- u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
-
- u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
-
- u_mm_file_reg_bsn_source : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
- port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
-
- u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
-
- u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
-
- u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
- u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
-
- u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
- u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
-
- u_mm_file_ram_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
- port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
- u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_jesd204b : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
+ port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+
+ u_mm_file_reg_dp_shiftram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
+ port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+
+ u_mm_file_reg_bsn_source : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
+ port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+
+ u_mm_file_reg_bsn_scheduler : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+
+ u_mm_file_reg_bsn_monitor_input : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+
+ u_mm_file_reg_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
+ port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
+ u_mm_file_ram_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
+ port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+
+ u_mm_file_ram_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
+ u_mm_file_reg_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+
+ u_mm_file_ram_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
+ u_mm_file_reg_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -285,9 +305,9 @@ begin
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
+ -- ToDo: This has changed in the peripherals package
rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ -- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -303,9 +323,9 @@ begin
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
+ -- ToDo: This has changed in the peripherals package
pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
--- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ -- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 869b3d932d..747413e29c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -27,16 +27,16 @@
-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
library IEEE, common_lib, unb2b_board_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.lofar2_unb2b_adc_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.lofar2_unb2b_adc_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity node_adc_input_and_timing is
generic (
@@ -119,11 +119,12 @@ end node_adc_input_and_timing;
architecture str of node_adc_input_and_timing is
constant c_nof_streams_jesd204b : natural := 12; -- IP is set up for 12 streams
- constant c_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_jesd_ctrl_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0');
-- Waveform Generator
constant c_wg_buf_directory : string := "data/";
@@ -186,35 +187,35 @@ begin
-----------------------------------------------------------------------------
u_jesd204b: entity tech_jesd204b_lib.tech_jesd204b
- generic map(
- g_sim => g_sim,
- g_nof_streams => c_nof_streams_jesd204b,
- g_nof_sync_n => g_nof_sync_n,
- g_jesd_freq => g_jesd_freq
- )
- port map(
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n_arr => jesd204b_sync_n,
-
- rx_sosi_arr => rx_sosi_arr,
- rx_clk => rx_clk,
- rx_rst => rx_rst,
- rx_sysref => rx_sysref,
-
- jesd204b_disable_arr => jesd204b_disable_arr,
-
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst_internal,
-
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
-
- -- Serial
- serial_tx_arr => open,
- serial_rx_arr => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b - 1 downto 0)
- );
+ generic map(
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams_jesd204b,
+ g_nof_sync_n => g_nof_sync_n,
+ g_jesd_freq => g_jesd_freq
+ )
+ port map(
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n_arr => jesd204b_sync_n,
+
+ rx_sosi_arr => rx_sosi_arr,
+ rx_clk => rx_clk,
+ rx_rst => rx_rst,
+ rx_sysref => rx_sysref,
+
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst_internal,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- Time delay: dp_shiftram
@@ -232,114 +233,114 @@ begin
end generate;
u_dp_shiftram : entity dp_lib.dp_shiftram
- generic map (
- g_nof_streams => c_nof_streams_jesd204b,
- g_nof_words => c_dp_shiftram_nof_samples,
- g_data_w => c_data_w,
- g_use_sync_in => true
- )
- port map (
- dp_rst => rx_rst,
- dp_clk => rx_clk,
+ generic map (
+ g_nof_streams => c_nof_streams_jesd204b,
+ g_nof_words => c_dp_shiftram_nof_samples,
+ g_data_w => c_data_w,
+ g_use_sync_in => true
+ )
+ port map (
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
- sync_in => bs_sosi.sync,
+ sync_in => bs_sosi.sync,
- reg_mosi => reg_dp_shiftram_mosi,
- reg_miso => reg_dp_shiftram_miso,
+ reg_mosi => reg_dp_shiftram_mosi,
+ reg_miso => reg_dp_shiftram_miso,
- snk_in_arr => dp_shiftram_snk_in_arr,
+ snk_in_arr => dp_shiftram_snk_in_arr,
- src_out_arr => ant_sosi_arr
- );
+ src_out_arr => ant_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Timestamp
-----------------------------------------------------------------------------
u_bsn_source : entity dp_lib.mms_dp_bsn_source
- generic map (
- g_cross_clock_domain => true,
- g_block_size => c_bs_block_size,
- g_nof_block_per_sync => c_bs_nof_block_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- dp_pps => rx_sysref,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_mosi,
- reg_miso => reg_bsn_source_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_block_size => c_bs_block_size,
+ g_nof_block_per_sync => c_bs_nof_block_per_sync,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ dp_pps => rx_sysref,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_bsn_source_mosi,
+ reg_miso => reg_bsn_source_miso,
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi
+ );
u_bsn_trigger_wg : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => true,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_miso => reg_bsn_scheduler_wg_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
- trigger_out => trigger_wg
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ trigger_out => trigger_wg
+ );
-----------------------------------------------------------------------------
-- WG (Test Signal Generator)
-----------------------------------------------------------------------------
u_wg_arr : entity diag_lib.mms_diag_wg_wideband_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_buf_dir => c_wg_buf_directory,
-
- -- Wideband parameters
- g_wideband_factor => 1,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => c_wg_buf_dat_w,
- g_buf_addr_w => c_wg_buf_addr_w,
- g_calc_support => true,
- g_calc_gain_w => 1,
- g_calc_dat_w => c_sdp_W_adc
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
-
- reg_mosi => reg_wg_mosi,
- reg_miso => reg_wg_miso,
-
- buf_mosi => ram_wg_mosi,
- buf_miso => ram_wg_miso,
-
- -- Streaming clock domain
- st_rst => rx_rst,
- st_clk => rx_clk,
- st_restart => trigger_wg,
-
- out_sosi_arr => wg_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_buf_dir => c_wg_buf_directory,
+
+ -- Wideband parameters
+ g_wideband_factor => 1,
+
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => c_wg_buf_dat_w,
+ g_buf_addr_w => c_wg_buf_addr_w,
+ g_calc_support => true,
+ g_calc_gain_w => 1,
+ g_calc_dat_w => c_sdp_W_adc
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_wg_mosi,
+ reg_miso => reg_wg_miso,
+
+ buf_mosi => ram_wg_mosi,
+ buf_miso => ram_wg_miso,
+
+ -- Streaming clock domain
+ st_rst => rx_rst,
+ st_clk => rx_clk,
+ st_restart => trigger_wg,
+
+ out_sosi_arr => wg_sosi_arr
+ );
-----------------------------------------------------------------------------
-- ADC/WG Mux (Input Select)
@@ -382,80 +383,80 @@ begin
-- BSN monitor (Block Checker)
---------------------------------------------------------------------------------------
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- They're all the same
- g_sync_timeout => g_bsn_sync_timeout,
- g_bsn_w => c_bs_bsn_w,
- g_log_first_bsn => false
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_input_mosi,
- reg_miso => reg_bsn_monitor_input_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- in_sosi_arr => st_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- They're all the same
+ g_sync_timeout => g_bsn_sync_timeout,
+ g_bsn_w => c_bs_bsn_w,
+ g_log_first_bsn => false
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_input_mosi,
+ reg_miso => reg_bsn_monitor_input_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ in_sosi_arr => st_sosi_arr(0 downto 0)
+ );
-----------------------------------------------------------------------------
-- Monitor ADU/WG output
-----------------------------------------------------------------------------
u_aduh_monitor : entity aduh_lib.mms_aduh_monitor_arr
- generic map (
- g_cross_clock_domain => true,
- g_nof_streams => g_nof_streams,
- g_symbol_w => c_data_w, -- TBD 16?
- g_nof_symbols_per_data => 1, -- Wideband factor is 1
- g_nof_accumulations => 200000512, -- = 195313 blocks * 1024 samples
- g_buffer_nof_symbols => g_aduh_buffer_nof_symbols, -- default 512, larger for full design
- g_buffer_use_sync => true -- True to capture all streams synchronously
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
-
- reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
- reg_miso => reg_aduh_monitor_miso,
- buf_mosi => ram_aduh_monitor_mosi, -- read and overwrite access to the signal path data buffers
- buf_miso => ram_aduh_monitor_miso,
-
- -- Streaming clock domain
- st_rst => rx_rst,
- st_clk => rx_clk,
-
- in_sosi_arr => st_sosi_arr
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_nof_streams => g_nof_streams,
+ g_symbol_w => c_data_w, -- TBD 16?
+ g_nof_symbols_per_data => 1, -- Wideband factor is 1
+ g_nof_accumulations => 200000512, -- = 195313 blocks * 1024 samples
+ g_buffer_nof_symbols => g_aduh_buffer_nof_symbols, -- default 512, larger for full design
+ g_buffer_use_sync => true -- True to capture all streams synchronously
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
+ reg_miso => reg_aduh_monitor_miso,
+ buf_mosi => ram_aduh_monitor_mosi, -- read and overwrite access to the signal path data buffers
+ buf_miso => ram_aduh_monitor_miso,
+
+ -- Streaming clock domain
+ st_rst => rx_rst,
+ st_clk => rx_clk,
+
+ in_sosi_arr => st_sosi_arr
+ );
- -----------------------------------------------------------------------------
--- Diagnostic Data Buffer
+ -----------------------------------------------------------------------------
+ -- Diagnostic Data Buffer
-----------------------------------------------------------------------------
u_diag_data_buffer_bsn : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => c_data_w,
- g_buf_nof_data => g_buf_nof_data,
- g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
- ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
- reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
- reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
-
- in_sosi_arr => st_sosi_arr,
- in_sync => st_sosi_arr(0).sync
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => c_data_w,
+ g_buf_nof_data => g_buf_nof_data,
+ g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
+
+ in_sosi_arr => st_sosi_arr,
+ in_sync => st_sosi_arr(0).sync
+ );
-----------------------------------------------------------------------------
-- Output Stage
@@ -486,23 +487,23 @@ begin
-- JESD Control register
-----------------------------------------------------------------------------
u_mm_jesd_ctrl_reg : entity common_lib.common_reg_r_w
- generic map (
- g_reg => c_mm_jesd_ctrl_reg,
- g_init_reg => (others => '0')
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- control side
- wr_en => jesd_ctrl_mosi.wr,
- wr_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- wr_dat => jesd_ctrl_mosi.wrdata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_en => jesd_ctrl_mosi.rd,
- rd_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- rd_dat => jesd_ctrl_miso.rddata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_val => OPEN,
- -- data side
- out_reg => mm_jesd_ctrl_reg,
- in_reg => mm_jesd_ctrl_reg
- );
+ generic map (
+ g_reg => c_mm_jesd_ctrl_reg,
+ g_init_reg => (others => '0')
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- control side
+ wr_en => jesd_ctrl_mosi.wr,
+ wr_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ wr_dat => jesd_ctrl_mosi.wrdata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_en => jesd_ctrl_mosi.rd,
+ rd_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ rd_dat => jesd_ctrl_miso.rddata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_val => OPEN,
+ -- data side
+ out_reg => mm_jesd_ctrl_reg,
+ in_reg => mm_jesd_ctrl_reg
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
index cd479c2bdb..baf31c7ce9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_adc_pkg is
-----------------------------------------------------------------------------
@@ -28,213 +28,213 @@ package qsys_lofar2_unb2b_adc_pkg is
-- $HDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_adc is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(11 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2b_adc;
+ component qsys_lofar2_unb2b_adc is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_aduh_monitor_clk_export : out std_logic; -- export
+ ram_aduh_monitor_read_export : out std_logic; -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_aduh_monitor_reset_export : out std_logic; -- export
+ ram_aduh_monitor_write_export : out std_logic; -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2b_adc;
end qsys_lofar2_unb2b_adc_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
index 627ac45ba4..bab5ccf9c2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
@@ -31,11 +31,11 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_lofar2_unb2b_adc is
end tb_lofar2_unb2b_adc;
@@ -108,50 +108,50 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc : entity work.lofar2_unb2b_adc
- generic map (
- g_design_name => "lofar2_unb2b_adc_one_node",
- g_design_note => "Lofar2 adc with one node",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_adc_one_node",
+ g_design_note => "Lofar2 adc with one node",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
index 16294442b7..5caff07771 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
@@ -31,12 +31,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib, ip_arria10_e1sg_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.all;
entity tb_lofar2_unb2b_adc_multichannel is
end tb_lofar2_unb2b_adc_multichannel;
@@ -59,30 +59,32 @@ architecture tb of tb_lofar2_unb2b_adc_multichannel is
-- Transport delays
type t_time_arr is array (0 to 11) of time;
constant c_nof_jesd204b_tx : natural := 3; -- number of jesd204b input sources to instantiate
- constant c_delay_data_arr : t_time_arr := (4000 ps,
- 5000 ps,
- 6000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps); -- transport delays tx to rx data
- constant c_delay_sysreftoadc_arr : t_time_arr := (4000 ps,
- 5000 ps,
- 6000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps); -- transport delays clock source to adc(tx)
+ constant c_delay_data_arr : t_time_arr := (
+ 4000 ps,
+ 5000 ps,
+ 6000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps); -- transport delays tx to rx data
+ constant c_delay_sysreftoadc_arr : t_time_arr := (
+ 4000 ps,
+ 5000 ps,
+ 6000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps); -- transport delays clock source to adc(tx)
constant c_delay_sysreftofpga : time := 10200 ps;
-- clocks and resets for the jesd204b tx
@@ -181,50 +183,50 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc : entity work.lofar2_unb2b_adc
- generic map (
- g_design_name => "lofar2_unb2b_adc_one_node",
- g_design_note => "Lofar2 adc with one node",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => bck_rx,
- JESD204B_REFCLK => jesd204b_sampclk_fpga,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref_fpga,
- JESD204B_SYNC_N => jesd204b_sync_n_fpga
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_adc_one_node",
+ g_design_note => "Lofar2 adc with one node",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => bck_rx,
+ JESD204B_REFCLK => jesd204b_sampclk_fpga,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref_fpga,
+ JESD204B_SYNC_N => jesd204b_sync_n_fpga
+ );
-----------------------------------------------------------------------------
-- Transport
@@ -233,7 +235,7 @@ begin
gen_transport : for i in 0 to c_nof_jesd204b_tx - 1 generate
jesd204b_sampclk_adc(i) <= transport jesd204b_sampclk after c_delay_sysreftoadc_arr(i);
jesd204b_sysref_adc(i) <= transport jesd204b_sysref after c_delay_sysreftoadc_arr(i);
--- txlink_clk(i) <= jesd204b_sampclk_div2 after c_delay_sysreftoadc_arr(i);
+ -- txlink_clk(i) <= jesd204b_sampclk_div2 after c_delay_sysreftoadc_arr(i);
bck_rx(i) <= transport serial_tx(i) after c_delay_data_arr(i);
jesd204b_sync_n_adc(i) <= transport jesd204b_sync_n_fpga(i) after c_delay_data_arr(i);
end generate;
@@ -247,56 +249,56 @@ begin
gen_jesd204b_tx : for i in 0 to c_nof_jesd204b_tx - 1 generate
u_ip_arria10_e1sg_jesd204b_tx : ip_arria10_e1sg_jesd204b_tx
- port map
- (
- csr_cf => OPEN,
- csr_cs => OPEN,
- csr_f => OPEN,
- csr_hd => OPEN,
- csr_k => OPEN,
- csr_l => OPEN,
- csr_lane_powerdown => open, -- out
- csr_m => OPEN,
- csr_n => OPEN,
- csr_np => OPEN,
- csr_tx_testmode => OPEN,
- csr_tx_testpattern_a => OPEN,
- csr_tx_testpattern_b => OPEN,
- csr_tx_testpattern_c => OPEN,
- csr_tx_testpattern_d => OPEN,
- csr_s => OPEN,
- dev_sync_n => dev_sync_n(i), -- out
- jesd204_tx_avs_chipselect => avs_chipselect(i), -- jesd204b_mosi_arr(i).chipselect,
- jesd204_tx_avs_address => avs_address(i),
- jesd204_tx_avs_read => avs_read(i),
- jesd204_tx_avs_readdata => avs_readdata(i),
- jesd204_tx_avs_waitrequest => open,
- jesd204_tx_avs_write => '0',
- jesd204_tx_avs_writedata => (others => '0'),
- jesd204_tx_avs_clk => mm_clk,
- jesd204_tx_avs_rst_n => avs_rst_n,
- jesd204_tx_dlb_data => open, -- debug/loopback testing
- jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
- jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
- jesd204_tx_frame_error => '0',
- jesd204_tx_int => OPEN, -- Connected to status IO in example design
- jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), -- in
- jesd204_tx_link_valid => jesd204b_tx_link_valid(i), -- in
- jesd204_tx_link_ready => jesd204b_tx_link_ready(i), -- out
- mdev_sync_n => dev_sync_n(i), -- in
- pll_locked => pll_locked, -- in
- sync_n => jesd204b_sync_n_adc(i), -- in
- tx_analogreset => tx_analogreset,
- tx_bonding_clocks => tx_bonding_clocks, -- : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
- tx_cal_busy => open,
- tx_digitalreset => tx_digitalreset,
- tx_serial_data => serial_tx(i downto i),
- txlink_clk => txlink_clk(i),
- txlink_rst_n_reset_n => txlink_rst_n,
- txphy_clk => txphy_clk(i downto i),
- somf => OPEN,
- sysref => jesd204b_sysref_adc(i)
- );
+ port map
+ (
+ csr_cf => OPEN,
+ csr_cs => OPEN,
+ csr_f => OPEN,
+ csr_hd => OPEN,
+ csr_k => OPEN,
+ csr_l => OPEN,
+ csr_lane_powerdown => open, -- out
+ csr_m => OPEN,
+ csr_n => OPEN,
+ csr_np => OPEN,
+ csr_tx_testmode => OPEN,
+ csr_tx_testpattern_a => OPEN,
+ csr_tx_testpattern_b => OPEN,
+ csr_tx_testpattern_c => OPEN,
+ csr_tx_testpattern_d => OPEN,
+ csr_s => OPEN,
+ dev_sync_n => dev_sync_n(i), -- out
+ jesd204_tx_avs_chipselect => avs_chipselect(i), -- jesd204b_mosi_arr(i).chipselect,
+ jesd204_tx_avs_address => avs_address(i),
+ jesd204_tx_avs_read => avs_read(i),
+ jesd204_tx_avs_readdata => avs_readdata(i),
+ jesd204_tx_avs_waitrequest => open,
+ jesd204_tx_avs_write => '0',
+ jesd204_tx_avs_writedata => (others => '0'),
+ jesd204_tx_avs_clk => mm_clk,
+ jesd204_tx_avs_rst_n => avs_rst_n,
+ jesd204_tx_dlb_data => open, -- debug/loopback testing
+ jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
+ jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
+ jesd204_tx_frame_error => '0',
+ jesd204_tx_int => OPEN, -- Connected to status IO in example design
+ jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), -- in
+ jesd204_tx_link_valid => jesd204b_tx_link_valid(i), -- in
+ jesd204_tx_link_ready => jesd204b_tx_link_ready(i), -- out
+ mdev_sync_n => dev_sync_n(i), -- in
+ pll_locked => pll_locked, -- in
+ sync_n => jesd204b_sync_n_adc(i), -- in
+ tx_analogreset => tx_analogreset,
+ tx_bonding_clocks => tx_bonding_clocks, -- : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy => open,
+ tx_digitalreset => tx_digitalreset,
+ tx_serial_data => serial_tx(i downto i),
+ txlink_clk => txlink_clk(i),
+ txlink_rst_n_reset_n => txlink_rst_n,
+ txphy_clk => txphy_clk(i downto i),
+ somf => OPEN,
+ sysref => jesd204b_sysref_adc(i)
+ );
-- Generate test pattern at each ADC
@@ -305,39 +307,39 @@ begin
variable even_sample : boolean := true;
begin
if mm_rst = '1' then
- jesd204b_tx_link_data_arr(i) <= (others => '0');
- jesd204b_tx_link_valid(i) <= '0';
- txlink_clk(i) <= '0';
- data := 0;
- even_sample := true;
- else
- if rising_edge(jesd204b_sampclk_adc(i)) then
- txlink_clk(i) <= not txlink_clk(i);
- jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
- jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
- if (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') then
- data := 1000;
- elsif (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') then
- data := -1000;
- else
- data := 0;
- end if;
-
- -- Frame the data to 32 bits at half the rate
- if(jesd204b_tx_link_ready(i) = '0') then
- even_sample := true;
- else
- even_sample := not even_sample;
- end if;
- if (even_sample = true) then
- jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(data, 16);
- jesd204b_tx_link_valid(i) <= '0';
- else
- jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16);
- jesd204b_tx_link_valid(i) <= '1';
- end if;
- end if;
- end if;
+ jesd204b_tx_link_data_arr(i) <= (others => '0');
+ jesd204b_tx_link_valid(i) <= '0';
+ txlink_clk(i) <= '0';
+ data := 0;
+ even_sample := true;
+ else
+ if rising_edge(jesd204b_sampclk_adc(i)) then
+ txlink_clk(i) <= not txlink_clk(i);
+ jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
+ jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
+ if (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') then
+ data := 1000;
+ elsif (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') then
+ data := -1000;
+ else
+ data := 0;
+ end if;
+
+ -- Frame the data to 32 bits at half the rate
+ if(jesd204b_tx_link_ready(i) = '0') then
+ even_sample := true;
+ else
+ even_sample := not even_sample;
+ end if;
+ if (even_sample = true) then
+ jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(data, 16);
+ jesd204b_tx_link_valid(i) <= '0';
+ else
+ jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16);
+ jesd204b_tx_link_valid(i) <= '1';
+ end if;
+ end if;
+ end if;
end process;
end generate;
@@ -385,23 +387,23 @@ begin
variable count : natural := 0;
begin
if mm_rst = '1' then
- jesd204b_sysref <= '0';
- count := 0;
- else
- if rising_edge(jesd204b_sampclk) then
+ jesd204b_sysref <= '0';
+ count := 0;
+ else
+ if rising_edge(jesd204b_sampclk) then
if (count = c_sysref_period - 1) then
- count := 0;
- else
- count := count + 1;
- end if;
-
- if count > c_sysref_period - 8 then
- jesd204b_sysref <= '1';
- else
- jesd204b_sysref <= '0';
- end if;
- end if;
- end if;
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+
+ if count > c_sysref_period - 8 then
+ jesd204b_sysref <= '1';
+ else
+ jesd204b_sysref <= '0';
+ end if;
+ end if;
+ end if;
end process;
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
index 90b3f26561..57bd95a2fb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_beamformer_one_node is
generic (
@@ -81,7 +81,7 @@ entity lofar2_unb2b_beamformer_one_node is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -113,58 +113,58 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_beamformer_lib.lofar2_unb2b_beamformer
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
index ebaa797084..91a2b0b758 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF with a DP_clk of 256MHz
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_beamformer_one_node_256MHz is
generic (
@@ -81,7 +81,7 @@ entity lofar2_unb2b_beamformer_one_node_256MHz is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -113,58 +113,58 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_beamformer_lib.lofar2_unb2b_beamformer
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
index 0d815568ee..84cbac1c01 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
@@ -27,19 +27,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2b_beamformer_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2b_beamformer_pkg.all;
entity lofar2_unb2b_beamformer is
generic (
@@ -91,9 +91,9 @@ entity lofar2_unb2b_beamformer is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -391,267 +391,267 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_dp_clk_freq,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_dp_clk_freq,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2b_beamformer
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
- reg_sdp_info_mosi => reg_sdp_info_mosi,
- reg_sdp_info_miso => reg_sdp_info_miso,
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- reg_bf_scale_mosi => reg_bf_scale_mosi,
- reg_bf_scale_miso => reg_bf_scale_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso,
- ram_st_bst_mosi => ram_st_bst_mosi,
- ram_st_bst_miso => ram_st_bst_miso,
- reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
- reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
+ ram_equalizer_gains_miso => ram_equalizer_gains_miso,
+ reg_dp_selector_mosi => reg_dp_selector_mosi,
+ reg_dp_selector_miso => reg_dp_selector_miso,
+ reg_sdp_info_mosi => reg_sdp_info_mosi,
+ reg_sdp_info_miso => reg_sdp_info_miso,
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+ reg_bf_scale_mosi => reg_bf_scale_mosi,
+ reg_bf_scale_miso => reg_bf_scale_miso,
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso,
+ ram_st_bst_mosi => ram_st_bst_mosi,
+ ram_st_bst_miso => ram_st_bst_miso,
+ reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
+ reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
+ reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
+ reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
-----------------------------------------------------------------------------
-- SDP Info register
-----------------------------------------------------------------------------
u_sdp_info : entity lofar2_sdp_lib.sdp_info
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
- -- inputs from other blocks
- gn_index => gn_index,
- f_adc => c_f_adc,
- fsub_type => c_fsub_type,
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
- -- sdp info
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info => sdp_info
+ );
-----------------------------------------------------------------------------
-- nof beamsets node_sdp_beamformers (BF)
@@ -672,211 +672,211 @@ begin
-- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
-----------------------------------------------------------------------------
u_ait: entity lofar2_unb2b_adc_lib.node_adc_input_and_timing
- generic map(
- g_nof_streams => c_sdp_S_pn,
- g_buf_nof_data => c_sdp_V_si_db,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd_ctrl_mosi => c_mem_mosi_rst,
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => ait_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_sdp_S_pn,
+ g_buf_nof_data => c_sdp_V_si_db,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd_ctrl_mosi => c_mem_mosi_rst,
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => ait_sosi_arr
+ );
-----------------------------------------------------------------------------
-- node_sdp_filterbank (FSUB)
-----------------------------------------------------------------------------
u_fsub : entity lofar2_sdp_lib.node_sdp_filterbank
- generic map(
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
- );
-
- -- Beamformers
- gen_bf : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
- u_bf : entity lofar2_sdp_lib.node_sdp_beamformer
generic map(
g_sim => g_sim,
- g_beamset_id => beamset_id,
- g_scope_selected_beamlet => g_scope_selected_subband
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
)
port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_sosi_arr,
- bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
- bf_udp_siso => bf_udp_siso_arr(beamset_id),
- bst_udp_sosi => OPEN,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
- ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
- ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
- reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
- reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
- reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
- reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
- reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
- ram_st_sst_mosi => ram_st_bst_mosi_arr(beamset_id),
- ram_st_sst_miso => ram_st_bst_miso_arr(beamset_id),
-
- sdp_info => sdp_info,
- gn_id => gn_id,
-
- eth_src_mac => cep_eth_src_mac,
- ip_src_addr => cep_ip_src_addr,
- udp_src_port => cep_udp_src_port,
-
- hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
);
+
+ -- Beamformers
+ gen_bf : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
+ u_bf : entity lofar2_sdp_lib.node_sdp_beamformer
+ generic map(
+ g_sim => g_sim,
+ g_beamset_id => beamset_id,
+ g_scope_selected_beamlet => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_sosi_arr,
+ bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
+ bf_udp_siso => bf_udp_siso_arr(beamset_id),
+ bst_udp_sosi => OPEN,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
+ ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
+ ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
+ reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
+ reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
+ reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
+ ram_st_sst_mosi => ram_st_bst_mosi_arr(beamset_id),
+ ram_st_sst_miso => ram_st_bst_miso_arr(beamset_id),
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+
+ eth_src_mac => cep_eth_src_mac,
+ ip_src_addr => cep_ip_src_addr,
+ udp_src_port => cep_udp_src_port,
+
+ hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
+ );
end generate;
-- MM multiplexing
u_mem_mux_ram_ss_ss_wide : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_ss_ss_wide
- )
- port map (
- mosi => ram_ss_ss_wide_mosi,
- miso => ram_ss_ss_wide_miso,
- mosi_arr => ram_ss_ss_wide_mosi_arr,
- miso_arr => ram_ss_ss_wide_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_ss_ss_wide
+ )
+ port map (
+ mosi => ram_ss_ss_wide_mosi,
+ miso => ram_ss_ss_wide_miso,
+ mosi_arr => ram_ss_ss_wide_mosi_arr,
+ miso_arr => ram_ss_ss_wide_miso_arr
+ );
u_mem_mux_ram_bf_weights : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_bf_weights
- )
- port map (
- mosi => ram_bf_weights_mosi,
- miso => ram_bf_weights_miso,
- mosi_arr => ram_bf_weights_mosi_arr,
- miso_arr => ram_bf_weights_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_bf_weights
+ )
+ port map (
+ mosi => ram_bf_weights_mosi,
+ miso => ram_bf_weights_miso,
+ mosi_arr => ram_bf_weights_mosi_arr,
+ miso_arr => ram_bf_weights_miso_arr
+ );
u_mem_mux_reg_bf_scale : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bf_scale
- )
- port map (
- mosi => reg_bf_scale_mosi,
- miso => reg_bf_scale_miso,
- mosi_arr => reg_bf_scale_mosi_arr,
- miso_arr => reg_bf_scale_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bf_scale
+ )
+ port map (
+ mosi => reg_bf_scale_mosi,
+ miso => reg_bf_scale_miso,
+ mosi_arr => reg_bf_scale_mosi_arr,
+ miso_arr => reg_bf_scale_miso_arr
+ );
u_mem_mux_reg_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_hdr_dat
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_hdr_dat
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
u_mem_mux_reg_dp_xonoff : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_dp_xonoff
- )
- port map (
- mosi => reg_dp_xonoff_mosi,
- miso => reg_dp_xonoff_miso,
- mosi_arr => reg_dp_xonoff_mosi_arr,
- miso_arr => reg_dp_xonoff_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_dp_xonoff
+ )
+ port map (
+ mosi => reg_dp_xonoff_mosi,
+ miso => reg_dp_xonoff_miso,
+ mosi_arr => reg_dp_xonoff_mosi_arr,
+ miso_arr => reg_dp_xonoff_miso_arr
+ );
u_mem_mux_ram_st_bst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_st_bst
- )
- port map (
- mosi => ram_st_bst_mosi,
- miso => ram_st_bst_miso,
- mosi_arr => ram_st_bst_mosi_arr,
- miso_arr => ram_st_bst_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_st_bst
+ )
+ port map (
+ mosi => ram_st_bst_mosi,
+ miso => ram_st_bst_miso,
+ mosi_arr => ram_st_bst_mosi_arr,
+ miso_arr => ram_st_bst_miso_arr
+ );
-----------------------------------------------------------------------------
-- DP MUX
@@ -887,34 +887,34 @@ begin
nw_10GbE_hdr_fields_in_arr(0) <= bf_10GbE_hdr_fields_out_arr(0);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_nof_input => c_sdp_N_beamsets,
- g_sel_ctrl_invert => true,
- g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
-
- snk_in_arr => bf_udp_sosi_arr,
- snk_out_arr => bf_udp_siso_arr,
-
- src_out => nw_10gbe_snk_in_arr(0),
- src_in => nw_10gbe_snk_out_arr(0)
- );
+ generic map (
+ g_nof_input => c_sdp_N_beamsets,
+ g_sel_ctrl_invert => true,
+ g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in_arr => bf_udp_sosi_arr,
+ snk_out_arr => bf_udp_siso_arr,
+
+ src_out => nw_10gbe_snk_in_arr(0),
+ src_in => nw_10gbe_snk_out_arr(0)
+ );
-----------------------------------------------------------------------------
-- Interface : 10GbE
-----------------------------------------------------------------------------
- -- put the QSFP_TX/RX ports into arrays
- i_QSFP_RX(0) <= QSFP_1_RX;
- QSFP_1_TX <= i_QSFP_TX(0);
- ------------
- -- Front IO
- ------------
- u_front_io : entity unb2b_board_lib.unb2b_board_front_io
+ -- put the QSFP_TX/RX ports into arrays
+ i_QSFP_RX(0) <= QSFP_1_RX;
+ QSFP_1_TX <= i_QSFP_TX(0);
+ ------------
+ -- Front IO
+ ------------
+ u_front_io : entity unb2b_board_lib.unb2b_board_front_io
generic map (
g_nof_qsfp_bus => c_nof_qsfp_bus
)
@@ -931,10 +931,10 @@ begin
QSFP_LED => QSFP_LED
);
- ---------
- -- PLL
- ---------
- u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
+ ---------
+ -- PLL
+ ---------
+ u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
generic map (
)
port map (
@@ -946,10 +946,10 @@ begin
rst_312 => open
);
- ---------------
- -- nw_10GbE
- ---------------
- u_nw_10GbE: entity nw_10GbE_lib.nw_10GbE
+ ---------------
+ -- nw_10GbE
+ ---------------
+ u_nw_10GbE: entity nw_10GbE_lib.nw_10GbE
generic map (
g_sim => g_sim,
g_sim_level => 1,
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
index 5fc60b88b1..a455ddb505 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
@@ -20,13 +20,13 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_beamformer_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
index 27f912bd20..b069d22c20 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_beamformer_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_beamformer_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2b_beamformer is
generic (
@@ -154,49 +154,49 @@ entity mmm_lofar2_unb2b_beamformer is
reg_si_mosi : out t_mem_mosi;
reg_si_miso : in t_mem_miso;
- -- Equalizer gains
- ram_equalizer_gains_mosi : out t_mem_mosi;
- ram_equalizer_gains_miso : in t_mem_miso;
+ -- Equalizer gains
+ ram_equalizer_gains_mosi : out t_mem_mosi;
+ ram_equalizer_gains_miso : in t_mem_miso;
- -- DP Selector
- reg_dp_selector_mosi : out t_mem_mosi;
- reg_dp_selector_miso : in t_mem_miso;
+ -- DP Selector
+ reg_dp_selector_mosi : out t_mem_mosi;
+ reg_dp_selector_miso : in t_mem_miso;
- -- SDP Info
- reg_sdp_info_mosi : out t_mem_mosi;
- reg_sdp_info_miso : in t_mem_miso;
+ -- SDP Info
+ reg_sdp_info_mosi : out t_mem_mosi;
+ reg_sdp_info_miso : in t_mem_miso;
- -- Beamlet Subband Select
- ram_ss_ss_wide_mosi : out t_mem_mosi;
- ram_ss_ss_wide_miso : in t_mem_miso;
+ -- Beamlet Subband Select
+ ram_ss_ss_wide_mosi : out t_mem_mosi;
+ ram_ss_ss_wide_miso : in t_mem_miso;
- -- Local BF bf weights
- ram_bf_weights_mosi : out t_mem_mosi;
- ram_bf_weights_miso : in t_mem_miso;
+ -- Local BF bf weights
+ ram_bf_weights_mosi : out t_mem_mosi;
+ ram_bf_weights_miso : in t_mem_miso;
- -- mms_dp_scale Scale Beamlets
- reg_bf_scale_mosi : out t_mem_mosi;
- reg_bf_scale_miso : in t_mem_miso;
+ -- mms_dp_scale Scale Beamlets
+ reg_bf_scale_mosi : out t_mem_mosi;
+ reg_bf_scale_miso : in t_mem_miso;
- -- Beamlet Data Output header fields
- reg_hdr_dat_mosi : out t_mem_mosi;
- reg_hdr_dat_miso : in t_mem_miso;
+ -- Beamlet Data Output header fields
+ reg_hdr_dat_mosi : out t_mem_mosi;
+ reg_hdr_dat_miso : in t_mem_miso;
- -- Beamlet Data Output xonoff
- reg_dp_xonoff_mosi : out t_mem_mosi;
- reg_dp_xonoff_miso : in t_mem_miso;
+ -- Beamlet Data Output xonoff
+ reg_dp_xonoff_mosi : out t_mem_mosi;
+ reg_dp_xonoff_miso : in t_mem_miso;
- -- Beamlet Statistics (BST)
- ram_st_bst_mosi : out t_mem_mosi;
- ram_st_bst_miso : in t_mem_miso;
+ -- Beamlet Statistics (BST)
+ ram_st_bst_mosi : out t_mem_mosi;
+ ram_st_bst_miso : in t_mem_miso;
- -- 10 GbE mac
- reg_nw_10GbE_mac_mosi : out t_mem_mosi;
- reg_nw_10GbE_mac_miso : in t_mem_miso;
+ -- 10 GbE mac
+ reg_nw_10GbE_mac_mosi : out t_mem_mosi;
+ reg_nw_10GbE_mac_miso : in t_mem_miso;
- -- 10 GbE eth
- reg_nw_10GbE_eth10g_mosi : out t_mem_mosi;
- reg_nw_10GbE_eth10g_miso : in t_mem_miso;
+ -- 10 GbE eth
+ reg_nw_10GbE_eth10g_mosi : out t_mem_mosi;
+ reg_nw_10GbE_eth10g_miso : in t_mem_miso;
-- Scrap ram
ram_scrap_mosi : out t_mem_mosi;
@@ -214,113 +214,150 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
-
- u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
-
- u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
-
- u_mm_file_reg_bsn_source : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
- port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
-
- u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
-
- u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
-
- u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
- u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
-
- u_mm_file_ram_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
- u_mm_file_reg_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
-
- u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
- u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
-
- u_mm_file_ram_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
- port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
- u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
-
- u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
-
- u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
-
- u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
-
- u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
-
- u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
-
- u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
-
- u_mm_file_ram_ss_ss_wide : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
-
- u_mm_file_ram_bf_weights : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- port map(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
-
- u_mm_file_reg_bf_scale : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
- port map(mm_rst, mm_clk, reg_bf_scale_mosi, reg_bf_scale_miso );
-
- u_mm_file_reg_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
- port map(mm_rst, mm_clk, reg_hdr_dat_mosi, reg_hdr_dat_miso );
-
- u_mm_file_reg_dp_xonoff : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
- port map(mm_rst, mm_clk, reg_dp_xonoff_mosi, reg_dp_xonoff_miso );
-
- u_mm_file_ram_st_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
- port map(mm_rst, mm_clk, ram_st_bst_mosi, ram_st_bst_miso );
-
- u_mm_file_reg_nw_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
-
- u_mm_file_reg_nw_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
-
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_jesd204b : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
+ port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+
+ u_mm_file_reg_dp_shiftram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
+ port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+
+ u_mm_file_reg_bsn_source : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
+ port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+
+ u_mm_file_reg_bsn_scheduler : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+
+ u_mm_file_reg_bsn_monitor_input : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+
+ u_mm_file_reg_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
+ port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
+ u_mm_file_ram_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
+ port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+
+ u_mm_file_ram_diag_data_buf_jesd : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
+ u_mm_file_reg_diag_data_buf_jesd : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
+
+ u_mm_file_ram_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
+ u_mm_file_reg_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+
+ u_mm_file_ram_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
+ u_mm_file_reg_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+
+ u_mm_file_ram_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
+ port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
+
+ u_mm_file_ram_fil_coefs : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
+ port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
+
+ u_mm_file_reg_si : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
+ port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
+
+ u_mm_file_ram_equalizer_gains : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
+ port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
+
+ u_mm_file_reg_dp_selector : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
+ port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
+
+ u_mm_file_reg_sdp_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+ port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+
+ u_mm_file_ram_ss_ss_wide : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ port map(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
+
+ u_mm_file_ram_bf_weights : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
+ port map(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
+
+ u_mm_file_reg_bf_scale : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
+ port map(mm_rst, mm_clk, reg_bf_scale_mosi, reg_bf_scale_miso );
+
+ u_mm_file_reg_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_hdr_dat_mosi, reg_hdr_dat_miso );
+
+ u_mm_file_reg_dp_xonoff : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_mosi, reg_dp_xonoff_miso );
+
+ u_mm_file_ram_st_bst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
+ port map(mm_rst, mm_clk, ram_st_bst_mosi, ram_st_bst_miso );
+
+ u_mm_file_reg_nw_10GbE_mac : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
+ port map(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
+
+ u_mm_file_reg_nw_10GbE_eth10g : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
+ port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
+
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -396,9 +433,9 @@ begin
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
+ -- ToDo: This has changed in the peripherals package
rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ -- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -414,9 +451,9 @@ begin
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
+ -- ToDo: This has changed in the peripherals package
pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
--- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ -- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
index 1df2a17b41..1fbcedf7e0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
@@ -19,331 +19,331 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_beamformer_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_beamformer is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buf_bsn_read_export : out std_logic; -- export
- ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buf_bsn_write_export : out std_logic; -- export
- ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buf_bsn_read_export : out std_logic; -- export
- reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buf_bsn_write_export : out std_logic; -- export
- reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2b_beamformer;
+ component qsys_lofar2_unb2b_beamformer is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_aduh_monitor_clk_export : out std_logic; -- export
+ ram_aduh_monitor_read_export : out std_logic; -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_aduh_monitor_reset_export : out std_logic; -- export
+ ram_aduh_monitor_write_export : out std_logic; -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bf_weights_clk_export : out std_logic; -- export
+ ram_bf_weights_read_export : out std_logic; -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_bf_weights_reset_export : out std_logic; -- export
+ ram_bf_weights_write_export : out std_logic; -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_st_bst_clk_export : out std_logic; -- export
+ ram_st_bst_read_export : out std_logic; -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_bst_reset_export : out std_logic; -- export
+ ram_st_bst_write_export : out std_logic; -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bf_scale_clk_export : out std_logic; -- export
+ reg_bf_scale_read_export : out std_logic; -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bf_scale_reset_export : out std_logic; -- export
+ reg_bf_scale_write_export : out std_logic; -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_xonoff_clk_export : out std_logic; -- export
+ reg_dp_xonoff_read_export : out std_logic; -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_reset_export : out std_logic; -- export
+ reg_dp_xonoff_write_export : out std_logic; -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_clk_export : out std_logic; -- export
+ reg_hdr_dat_read_export : out std_logic; -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_reset_export : out std_logic; -- export
+ reg_hdr_dat_write_export : out std_logic; -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic; -- export
+ reg_nw_10gbe_mac_read_export : out std_logic; -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic; -- export
+ reg_nw_10gbe_mac_write_export : out std_logic; -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2b_beamformer;
end qsys_lofar2_unb2b_beamformer_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
index bae7a2ad5a..d63e44233c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_filterbank_full is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2b_filterbank_full is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_filterbank_lib.lofar2_unb2b_filterbank
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
index e541eecf75..59a6c2de72 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_filterbank_full_256MHz is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2b_filterbank_full_256MHz is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_filterbank_lib.lofar2_unb2b_filterbank
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
index 9a0af000e4..5129984a1f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
@@ -27,19 +27,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2b_filterbank_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2b_filterbank_pkg.all;
+ use eth_lib.eth_pkg.all;
entity lofar2_unb2b_filterbank is
generic (
@@ -87,9 +87,9 @@ entity lofar2_unb2b_filterbank is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -299,243 +299,243 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_dp_clk_freq,
- g_dp_clk_use_pll => false,
- g_udp_offload => true,
- g_udp_offload_nof_streams => c_eth_nof_udp_ports
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_dp_clk_freq,
+ g_dp_clk_use_pll => false,
+ g_udp_offload => true,
+ g_udp_offload_nof_streams => c_eth_nof_udp_ports
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2b_filterbank
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- Jesd reset control
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Statistics offload
- reg_sdp_info_mosi => reg_sdp_info_mosi,
- reg_sdp_info_miso => reg_sdp_info_miso,
- reg_stat_enable_mosi => reg_stat_enable_mosi,
- reg_stat_enable_miso => reg_stat_enable_miso,
- reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
+ ram_equalizer_gains_miso => ram_equalizer_gains_miso,
+ reg_dp_selector_mosi => reg_dp_selector_mosi,
+ reg_dp_selector_miso => reg_dp_selector_miso,
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- Jesd reset control
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Statistics offload
+ reg_sdp_info_mosi => reg_sdp_info_mosi,
+ reg_sdp_info_miso => reg_sdp_info_miso,
+ reg_stat_enable_mosi => reg_stat_enable_mosi,
+ reg_stat_enable_miso => reg_stat_enable_miso,
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_miso
+ );
-----------------------------------------------------------------------------
-- SDP Info register
@@ -548,25 +548,25 @@ begin
sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
u_sdp_info : entity lofar2_sdp_lib.sdp_info
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
- -- inputs from other blocks
- gn_index => gn_index,
- f_adc => c_f_adc,
- fsub_type => c_fsub_type,
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
- -- sdp info
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info => sdp_info
+ );
-----------------------------------------------------------------------------
-- node_adc_input_and_timing (AIT)
@@ -574,102 +574,102 @@ begin
-----------------------------------------------------------------------------
u_ait: entity lofar2_unb2b_adc_lib.node_adc_input_and_timing
- generic map(
- g_nof_streams => c_sdp_S_pn,
- g_buf_nof_data => c_sdp_V_si_db,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => ait_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_sdp_S_pn,
+ g_buf_nof_data => c_sdp_V_si_db,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => ait_sosi_arr
+ );
-----------------------------------------------------------------------------
-- node_sdp_filterbank (FSUB)
-----------------------------------------------------------------------------
u_fsub : entity lofar2_sdp_lib.node_sdp_filterbank
- generic map(
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
-
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso,
-
- reg_enable_mosi => reg_stat_enable_mosi,
- reg_enable_miso => reg_stat_enable_miso,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
-
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso,
+
+ reg_enable_mosi => reg_stat_enable_mosi,
+ reg_enable_miso => reg_stat_enable_miso,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
index 7b73286048..ea0aaeb04b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
@@ -20,13 +20,13 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_filterbank_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
index 736f555d99..d27180e0dd 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_filterbank_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_filterbank_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2b_filterbank is
generic (
@@ -194,95 +194,126 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
-
- u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
-
- u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
-
- u_mm_file_reg_bsn_source : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
- port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
-
- u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
-
- u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
-
- u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
- u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
-
- u_mm_file_ram_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
- u_mm_file_reg_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
-
- u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
- u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
-
- u_mm_file_ram_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
- port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
- u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
-
- u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
-
- u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
-
- u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
-
- u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
-
- u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
-
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
-
- u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
-
- u_mm_file_reg_stat_enable : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE")
- port map(mm_rst, mm_clk, reg_stat_enable_mosi, reg_stat_enable_miso );
-
- u_mm_file_reg_stat_hdr_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_mosi, reg_stat_hdr_dat_miso);
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_jesd204b : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
+ port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+
+ u_mm_file_reg_dp_shiftram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
+ port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+
+ u_mm_file_reg_bsn_source : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
+ port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+
+ u_mm_file_reg_bsn_scheduler : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+
+ u_mm_file_reg_bsn_monitor_input : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+
+ u_mm_file_reg_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
+ port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
+ u_mm_file_ram_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
+ port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+
+ u_mm_file_ram_diag_data_buf_jesd : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
+ u_mm_file_reg_diag_data_buf_jesd : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
+
+ u_mm_file_ram_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
+ u_mm_file_reg_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+
+ u_mm_file_ram_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
+ u_mm_file_reg_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+
+ u_mm_file_ram_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
+ port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
+
+ u_mm_file_ram_fil_coefs : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
+ port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
+
+ u_mm_file_reg_si : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
+ port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
+
+ u_mm_file_ram_equalizer_gains : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
+ port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
+
+ u_mm_file_reg_dp_selector : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
+ port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
+
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+
+ u_mm_file_reg_sdp_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+ port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+
+ u_mm_file_reg_stat_enable : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE")
+ port map(mm_rst, mm_clk, reg_stat_enable_mosi, reg_stat_enable_miso );
+
+ u_mm_file_reg_stat_hdr_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_mosi, reg_stat_hdr_dat_miso);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -375,9 +406,9 @@ begin
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
+ -- ToDo: This has changed in the peripherals package
pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
--- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ -- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
index 21dc8f5640..d589f304f5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
@@ -19,299 +19,299 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_filterbank_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_filterbank is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buf_bsn_read_export : out std_logic; -- export
- ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buf_bsn_write_export : out std_logic; -- export
- ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ component qsys_lofar2_unb2b_filterbank is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_aduh_monitor_clk_export : out std_logic; -- export
+ ram_aduh_monitor_read_export : out std_logic; -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_aduh_monitor_reset_export : out std_logic; -- export
+ ram_aduh_monitor_write_export : out std_logic; -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_clk_export : out std_logic; -- export
- reg_stat_enable_read_export : out std_logic; -- export
- reg_stat_enable_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_reset_export : out std_logic; -- export
- reg_stat_enable_write_export : out std_logic; -- export
- reg_stat_enable_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_read_export : out std_logic; -- export
- reg_stat_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_write_export : out std_logic; -- export
- reg_stat_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_clk_export : out std_logic; -- export
+ reg_stat_enable_read_export : out std_logic; -- export
+ reg_stat_enable_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_reset_export : out std_logic; -- export
+ reg_stat_enable_write_export : out std_logic; -- export
+ reg_stat_enable_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buf_bsn_read_export : out std_logic; -- export
- reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buf_bsn_write_export : out std_logic; -- export
- reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_lofar2_unb2b_filterbank;
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_lofar2_unb2b_filterbank;
end qsys_lofar2_unb2b_filterbank_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
index afbced0491..16c31d39d2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete ring design with all 8 lanes.
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_ring_full is
generic (
@@ -93,56 +93,56 @@ end lofar2_unb2b_ring_full;
architecture str of lofar2_unb2b_ring_full is
begin
u_revision : entity lofar2_unb2b_ring_lib.lofar2_unb2b_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
index 18ccf3dd9e..b1a0fbc0ab 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
@@ -28,12 +28,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2b_ring_full is
end tb_lofar2_unb2b_ring_full;
@@ -100,53 +100,53 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_ring_full : entity work.lofar2_unb2b_ring_full
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX,
- QSFP_0_TX => i_QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX,
- RING_0_TX => i_RING_0_TX,
- RING_1_RX => i_RING_1_RX,
- RING_1_TX => i_RING_1_TX,
-
- -- LEDs
- QSFP_LED => open
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX,
+ QSFP_0_TX => i_QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX,
+ RING_0_TX => i_RING_0_TX,
+ RING_1_RX => i_RING_1_RX,
+ RING_1_TX => i_RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => open
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
index 86bb45908a..823c8e0b30 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
@@ -29,13 +29,13 @@
-- However only 1 ring_lane.vhd component is instantiated with lane index 0 (even).
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_ring_one is
generic (
@@ -96,56 +96,56 @@ end lofar2_unb2b_ring_one;
architecture str of lofar2_unb2b_ring_one is
begin
u_revision : entity lofar2_unb2b_ring_lib.lofar2_unb2b_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
index eccc9a2de9..37dbd95527 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
@@ -28,12 +28,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2b_ring_one is
end tb_lofar2_unb2b_ring_one;
@@ -100,53 +100,53 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_ring_one : entity work.lofar2_unb2b_ring_one
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX,
- QSFP_0_TX => i_QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX,
- RING_0_TX => i_RING_0_TX,
- RING_1_RX => i_RING_1_RX,
- RING_1_TX => i_RING_1_TX,
-
- -- LEDs
- QSFP_LED => open
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX,
+ QSFP_0_TX => i_QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX,
+ RING_0_TX => i_RING_0_TX,
+ RING_1_RX => i_RING_1_RX,
+ RING_1_TX => i_RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => open
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
index dbf744910f..59753bec5b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
@@ -27,21 +27,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, tr_10gbe_lib, eth_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2b_ring_pkg.all;
-use eth_lib.eth_pkg.all;
-use ring_lib.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2b_ring_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use ring_lib.ring_pkg.all;
entity lofar2_unb2b_ring is
generic (
@@ -110,7 +110,7 @@ architecture str of lofar2_unb2b_ring is
constant c_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_100M;
constant c_lofar2_sample_clk_freq : natural := c_sdp_N_clk_per_sync; -- fixed 200 MHz for LOFAR2.0 stage 1
- -- QSFP
+ -- QSFP
constant c_nof_qsfp_bus : natural := 1;
constant c_nof_streams_qsfp : natural := c_unb2b_board_tr_qsfp.bus_w * c_nof_qsfp_bus; -- 4
@@ -149,11 +149,12 @@ architecture str of lofar2_unb2b_ring is
constant c_addr_w_reg_dp_block_validate_err : natural := ceil_log2(c_nof_err_counts + 3);
constant c_addr_w_reg_dp_block_validate_bsn_at_sync : natural := ceil_log2(3);
- constant c_reg_ring_input_select : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_lanes),
- dat_w => 1,
- nof_dat => c_nof_lanes,
- init_sl => '0'); -- default use lane input = 0, 1 = local input.
+ constant c_reg_ring_input_select : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_lanes),
+ dat_w => 1,
+ nof_dat => c_nof_lanes,
+ init_sl => '0'); -- default use lane input = 0, 1 = local input.
signal gn_index : natural;
signal this_rn : std_logic_vector(c_byte_w - 1 downto 0);
@@ -343,318 +344,318 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_copi,
- reg_remu_miso => reg_remu_cipo,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_copi,
- reg_dpmm_data_miso => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_copi,
- reg_mmdp_data_miso => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_copi,
- reg_epcs_miso => reg_epcs_cipo,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_copi,
- reg_wdi_miso => reg_wdi_cipo,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_copi,
- reg_unb_system_info_miso => reg_unb_system_info_cipo,
- rom_unb_system_info_mosi => rom_unb_system_info_copi,
- rom_unb_system_info_miso => rom_unb_system_info_cipo,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_copi,
- reg_unb_sens_miso => reg_unb_sens_cipo,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_copi,
- reg_unb_pmbus_miso => reg_unb_pmbus_cipo,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_copi,
- reg_ppsh_miso => reg_ppsh_cipo,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_copi,
- eth1g_tse_miso => eth1g_tse_cipo,
- eth1g_reg_mosi => eth1g_reg_copi,
- eth1g_reg_miso => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_copi,
- eth1g_ram_miso => eth1g_ram_cipo,
-
- ram_scrap_mosi => ram_scrap_copi,
- ram_scrap_miso => ram_scrap_cipo,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_copi,
+ reg_unb_sens_miso => reg_unb_sens_cipo,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_cipo,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
+
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM controller
-----------------------------------------------------------------------------
u_mmc : entity work.mmc_lofar2_unb2b_ring
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_copi => reg_wdi_copi,
- reg_wdi_cipo => reg_wdi_cipo,
- reg_unb_system_info_copi => reg_unb_system_info_copi,
- reg_unb_system_info_cipo => reg_unb_system_info_cipo,
- rom_unb_system_info_copi => rom_unb_system_info_copi,
- rom_unb_system_info_cipo => rom_unb_system_info_cipo,
- reg_unb_sens_copi => reg_unb_sens_copi,
- reg_unb_sens_cipo => reg_unb_sens_cipo,
- reg_unb_pmbus_copi => reg_unb_pmbus_copi,
- reg_unb_pmbus_cipo => reg_unb_pmbus_cipo,
- reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
- reg_ppsh_copi => reg_ppsh_copi,
- reg_ppsh_cipo => reg_ppsh_cipo,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_copi => eth1g_tse_copi,
- eth1g_tse_cipo => eth1g_tse_cipo,
- eth1g_reg_copi => eth1g_reg_copi,
- eth1g_reg_cipo => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_copi => eth1g_ram_copi,
- eth1g_ram_cipo => eth1g_ram_cipo,
- reg_dpmm_data_copi => reg_dpmm_data_copi,
- reg_dpmm_data_cipo => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
- reg_mmdp_data_copi => reg_mmdp_data_copi,
- reg_mmdp_data_cipo => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
- reg_epcs_copi => reg_epcs_copi,
- reg_epcs_cipo => reg_epcs_cipo,
- reg_remu_copi => reg_remu_copi,
- reg_remu_cipo => reg_remu_cipo,
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi,
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo,
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi,
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo,
- reg_diag_bg_copi => reg_diag_bg_copi,
- reg_diag_bg_cipo => reg_diag_bg_cipo,
- ram_diag_bg_copi => ram_diag_bg_copi,
- ram_diag_bg_cipo => ram_diag_bg_cipo,
- reg_ring_lane_info_copi => reg_ring_lane_info_copi,
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo,
- reg_dp_xonoff_lane_copi => reg_dp_xonoff_lane_copi,
- reg_dp_xonoff_lane_cipo => reg_dp_xonoff_lane_cipo,
- reg_dp_xonoff_local_copi => reg_dp_xonoff_local_copi,
- reg_dp_xonoff_local_cipo => reg_dp_xonoff_local_cipo,
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo,
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_scrap_copi => ram_scrap_copi,
- ram_scrap_cipo => ram_scrap_cipo
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_unb_sens_copi => reg_unb_sens_copi,
+ reg_unb_sens_cipo => reg_unb_sens_cipo,
+ reg_unb_pmbus_copi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_cipo => reg_unb_pmbus_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi,
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo,
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi,
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo,
+ reg_diag_bg_copi => reg_diag_bg_copi,
+ reg_diag_bg_cipo => reg_diag_bg_cipo,
+ ram_diag_bg_copi => ram_diag_bg_copi,
+ ram_diag_bg_cipo => ram_diag_bg_cipo,
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi,
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo,
+ reg_dp_xonoff_lane_copi => reg_dp_xonoff_lane_copi,
+ reg_dp_xonoff_lane_cipo => reg_dp_xonoff_lane_cipo,
+ reg_dp_xonoff_local_copi => reg_dp_xonoff_local_copi,
+ reg_dp_xonoff_local_cipo => reg_dp_xonoff_local_cipo,
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo,
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo
+ );
-----------------------------------------------------------------------------
-- MM Mux
-----------------------------------------------------------------------------
u_mem_mux_ring_lane_info : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_ring_lane_info
- )
- port map (
- mosi => reg_ring_lane_info_copi,
- miso => reg_ring_lane_info_cipo,
- mosi_arr => reg_ring_lane_info_copi_arr,
- miso_arr => reg_ring_lane_info_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_ring_lane_info
+ )
+ port map (
+ mosi => reg_ring_lane_info_copi,
+ miso => reg_ring_lane_info_cipo,
+ mosi_arr => reg_ring_lane_info_copi_arr,
+ miso_arr => reg_ring_lane_info_cipo_arr
+ );
u_mem_mux_bsn_monitor_v2_ring_rx : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_rx_copi,
- miso => reg_bsn_monitor_v2_ring_rx_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_rx_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_rx_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_rx_copi,
+ miso => reg_bsn_monitor_v2_ring_rx_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_rx_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_rx_cipo_arr
+ );
u_mem_mux_bsn_monitor_v2_ring_tx : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_tx_copi,
- miso => reg_bsn_monitor_v2_ring_tx_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_tx_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_tx_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_tx_copi,
+ miso => reg_bsn_monitor_v2_ring_tx_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_tx_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_tx_cipo_arr
+ );
u_mem_mux_dp_block_validate_err : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_dp_block_validate_err
- )
- port map (
- mosi => reg_dp_block_validate_err_copi,
- miso => reg_dp_block_validate_err_cipo,
- mosi_arr => reg_dp_block_validate_err_copi_arr,
- miso_arr => reg_dp_block_validate_err_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_dp_block_validate_err
+ )
+ port map (
+ mosi => reg_dp_block_validate_err_copi,
+ miso => reg_dp_block_validate_err_cipo,
+ mosi_arr => reg_dp_block_validate_err_copi_arr,
+ miso_arr => reg_dp_block_validate_err_cipo_arr
+ );
u_mem_mux_dp_block_validate_bsn_at_sync : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_dp_block_validate_bsn_at_sync
- )
- port map (
- mosi => reg_dp_block_validate_bsn_at_sync_copi,
- miso => reg_dp_block_validate_bsn_at_sync_cipo,
- mosi_arr => reg_dp_block_validate_bsn_at_sync_copi_arr,
- miso_arr => reg_dp_block_validate_bsn_at_sync_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_dp_block_validate_bsn_at_sync
+ )
+ port map (
+ mosi => reg_dp_block_validate_bsn_at_sync_copi,
+ miso => reg_dp_block_validate_bsn_at_sync_cipo,
+ mosi_arr => reg_dp_block_validate_bsn_at_sync_copi_arr,
+ miso_arr => reg_dp_block_validate_bsn_at_sync_cipo_arr
+ );
-----------------------------------------------------------------------------
-- MMP diag_block_gen
-----------------------------------------------------------------------------
u_mmp_diag_block_gen : entity diag_lib.mms_diag_block_gen
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
-
- reg_bg_ctrl_mosi => reg_diag_bg_copi,
- reg_bg_ctrl_miso => reg_diag_bg_cipo,
- ram_bg_data_mosi => ram_diag_bg_copi,
- ram_bg_data_miso => ram_diag_bg_cipo,
-
- out_sosi_arr(0) => local_sosi
- );
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_copi,
+ reg_bg_ctrl_miso => reg_diag_bg_cipo,
+ ram_bg_data_mosi => ram_diag_bg_copi,
+ ram_bg_data_miso => ram_diag_bg_cipo,
+
+ out_sosi_arr(0) => local_sosi
+ );
bs_sosi <= local_sosi;
-----------------------------------------------------------------------------
-- MMP dp_xonoff from_lane_sosi
-----------------------------------------------------------------------------
u_mmp_dp_xonoff_lane : entity dp_lib.mms_dp_xonoff
- generic map (
- g_nof_streams => c_nof_lanes,
- g_default_value => '1' -- default enabled, because standard behaviour is to only pass on packets from lane.
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => c_nof_lanes,
+ g_default_value => '1' -- default enabled, because standard behaviour is to only pass on packets from lane.
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_dp_xonoff_lane_copi,
- reg_miso => reg_dp_xonoff_lane_cipo,
+ reg_mosi => reg_dp_xonoff_lane_copi,
+ reg_miso => reg_dp_xonoff_lane_cipo,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- snk_out_arr => OPEN,
- snk_in_arr => from_lane_sosi_arr,
+ snk_out_arr => OPEN,
+ snk_in_arr => from_lane_sosi_arr,
- src_in_arr => dp_xonoff_lane_src_in_arr,
- src_out_arr => dp_xonoff_lane_src_out_arr
- );
+ src_in_arr => dp_xonoff_lane_src_in_arr,
+ src_out_arr => dp_xonoff_lane_src_out_arr
+ );
-----------------------------------------------------------------------------
-- MMP dp_xonoff local_sosi
@@ -664,26 +665,26 @@ begin
end generate;
u_mmp_dp_xonoff_local : entity dp_lib.mms_dp_xonoff
- generic map (
- g_nof_streams => c_nof_lanes,
- g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => c_nof_lanes,
+ g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_dp_xonoff_local_copi,
- reg_miso => reg_dp_xonoff_local_cipo,
+ reg_mosi => reg_dp_xonoff_local_copi,
+ reg_miso => reg_dp_xonoff_local_cipo,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- snk_out_arr => OPEN,
- snk_in_arr => dp_xonoff_local_snk_in_arr,
+ snk_out_arr => OPEN,
+ snk_in_arr => dp_xonoff_local_snk_in_arr,
- src_in_arr => dp_xonoff_local_src_in_arr,
- src_out_arr => dp_xonoff_local_src_out_arr
- );
+ src_in_arr => dp_xonoff_local_src_in_arr,
+ src_out_arr => dp_xonoff_local_src_out_arr
+ );
-----------------------------------------------------------------------------
-- DP Mux
@@ -695,49 +696,49 @@ begin
dp_mux_snk_in_2arr(I)(1) <= dp_xonoff_local_src_out_arr(I);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_append_channel_lo => false,
- g_sel_ctrl_invert => true,
- g_use_fifo => true,
- g_bsn_w => c_longword_w,
- g_data_w => c_lane_data_w,
- g_in_channel_w => c_byte_w,
- g_error_w => c_nof_err_counts,
- g_use_bsn => true,
- g_use_in_channel => true,
- g_use_error => true,
- g_use_sync => true,
- -- Using fifo size of 2 * packet length for both inputs of the mux as a packet might arrive on both the local and remote input.
- g_fifo_size => array_init(2 * c_lane_packet_length, 2)
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_mux_snk_out_2arr(I),
- snk_in_arr => dp_mux_snk_in_2arr(I),
-
- src_in => c_dp_siso_rdy,
- src_out => to_lane_sosi_arr(I)
- );
+ generic map (
+ g_append_channel_lo => false,
+ g_sel_ctrl_invert => true,
+ g_use_fifo => true,
+ g_bsn_w => c_longword_w,
+ g_data_w => c_lane_data_w,
+ g_in_channel_w => c_byte_w,
+ g_error_w => c_nof_err_counts,
+ g_use_bsn => true,
+ g_use_in_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ -- Using fifo size of 2 * packet length for both inputs of the mux as a packet might arrive on both the local and remote input.
+ g_fifo_size => array_init(2 * c_lane_packet_length, 2)
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_mux_snk_out_2arr(I),
+ snk_in_arr => dp_mux_snk_in_2arr(I),
+
+ src_in => c_dp_siso_rdy,
+ src_out => to_lane_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
-- Ring info
-----------------------------------------------------------------------------
u_ring_info : entity ring_lib.ring_info
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_copi => reg_ring_info_copi,
- reg_cipo => reg_ring_info_cipo,
+ reg_copi => reg_ring_info_copi,
+ reg_cipo => reg_ring_info_cipo,
- ring_info => ring_info
- );
+ ring_info => ring_info
+ );
-- Use full c_byte_w range of ID for gn_index and ring_info.O_rn
gn_index <= TO_UINT(ID);
@@ -748,50 +749,50 @@ begin
-----------------------------------------------------------------------------
gen_even_lanes: for I in 0 to c_nof_even_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 1, -- transport in positive direction.
- g_lane_data_w => c_lane_data_w,
- g_lane_packet_length => c_lane_packet_length,
- g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_nof_rx_monitors,
- g_nof_tx_monitors => c_nof_tx_monitors,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => from_lane_sosi_arr(2 * I), -- even indices
- to_lane_sosi => to_lane_sosi_arr(2 * I),
- lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I),
- lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I),
- lane_tx_cable_sosi => lane_tx_cable_even_sosi_arr(I),
- lane_tx_board_sosi => lane_tx_board_even_sosi_arr(I),
- bs_sosi => bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I),
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I),
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_previous_rn,
- tx_select => ring_info.use_cable_to_next_rn
- );
+ generic map (
+ g_lane_direction => 1, -- transport in positive direction.
+ g_lane_data_w => c_lane_data_w,
+ g_lane_packet_length => c_lane_packet_length,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_nof_rx_monitors,
+ g_nof_tx_monitors => c_nof_tx_monitors,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => from_lane_sosi_arr(2 * I), -- even indices
+ to_lane_sosi => to_lane_sosi_arr(2 * I),
+ lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I),
+ lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I),
+ lane_tx_cable_sosi => lane_tx_cable_even_sosi_arr(I),
+ lane_tx_board_sosi => lane_tx_board_even_sosi_arr(I),
+ bs_sosi => bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_previous_rn,
+ tx_select => ring_info.use_cable_to_next_rn
+ );
end generate;
-----------------------------------------------------------------------------
@@ -799,50 +800,50 @@ begin
-----------------------------------------------------------------------------
gen_odd_lanes : for I in 0 to c_nof_odd_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 0, -- transport in negative direction.
- g_lane_data_w => c_lane_data_w,
- g_lane_packet_length => c_lane_packet_length,
- g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_nof_rx_monitors,
- g_nof_tx_monitors => c_nof_tx_monitors,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => from_lane_sosi_arr(2 * I + 1), -- odd indices
- to_lane_sosi => to_lane_sosi_arr(2 * I + 1),
- lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I),
- lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I),
- lane_tx_cable_sosi => lane_tx_cable_odd_sosi_arr(I),
- lane_tx_board_sosi => lane_tx_board_odd_sosi_arr(I),
- bs_sosi => bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I + 1),
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I + 1),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I + 1),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I + 1),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I + 1),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I + 1),
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
- tx_select => ring_info.use_cable_to_previous_rn
- );
+ generic map (
+ g_lane_direction => 0, -- transport in negative direction.
+ g_lane_data_w => c_lane_data_w,
+ g_lane_packet_length => c_lane_packet_length,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_nof_rx_monitors,
+ g_nof_tx_monitors => c_nof_tx_monitors,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => from_lane_sosi_arr(2 * I + 1), -- odd indices
+ to_lane_sosi => to_lane_sosi_arr(2 * I + 1),
+ lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I),
+ lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I),
+ lane_tx_cable_sosi => lane_tx_cable_odd_sosi_arr(I),
+ lane_tx_board_sosi => lane_tx_board_odd_sosi_arr(I),
+ bs_sosi => bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I + 1),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I + 1),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I + 1),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I + 1),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I + 1),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I + 1),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
+ tx_select => ring_info.use_cable_to_previous_rn
+ );
end generate;
-----------------------------------------------------------------------------
@@ -871,45 +872,45 @@ begin
-- tr_10GbE
-----------------------------------------------------------------------------
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_mac,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill,
- g_tx_fifo_size => c_fifo_tx_size
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mac_copi,
- reg_mac_miso => reg_tr_10GbE_mac_cipo,
-
- reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
- reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => tr_10gbe_src_out_arr,
- src_in_arr => tr_10gbe_src_in_arr,
-
- snk_out_arr => tr_10gbe_snk_out_arr,
- snk_in_arr => tr_10gbe_snk_in_arr,
-
- -- Serial IO
- serial_tx_arr => tr_10gbe_serial_tx_arr,
- serial_rx_arr => tr_10gbe_serial_rx_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_mac,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill,
+ g_tx_fifo_size => c_fifo_tx_size
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mac_copi,
+ reg_mac_miso => reg_tr_10GbE_mac_cipo,
+
+ reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => tr_10gbe_src_out_arr,
+ src_in_arr => tr_10gbe_src_in_arr,
+
+ snk_out_arr => tr_10gbe_snk_out_arr,
+ snk_in_arr => tr_10gbe_snk_in_arr,
+
+ -- Serial IO
+ serial_tx_arr => tr_10gbe_serial_tx_arr,
+ serial_rx_arr => tr_10gbe_serial_rx_arr
+ );
-----------------------------------------------------------------------------
-- Seperate serial tx/rx array
@@ -937,14 +938,14 @@ begin
-- PLL
---------
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
------------
-- Front IO
@@ -954,21 +955,21 @@ begin
QSFP_0_TX <= i_QSFP_TX(0);
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
------------
-- RING IO
@@ -983,18 +984,18 @@ begin
------------
unb2_board_qsfp_leds_tx_siso_arr(0) <= tr_10gbe_snk_out_arr(0);
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
-
- tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+
+ tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
index d922173d66..8a3700b4fb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
@@ -19,13 +19,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_ring_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
index 1ae1c752c2..88b9f3656a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_ring_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_ring_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmc_lofar2_unb2b_ring is
generic (
@@ -159,71 +159,93 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
-
- u_mm_file_reg_dp_block_validate_err : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_copi, reg_dp_block_validate_err_cipo );
-
- u_mm_file_reg_dp_block_validate_bsn_at_sync : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_copi, reg_dp_block_validate_bsn_at_sync_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_ring_rx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_copi, reg_bsn_monitor_v2_ring_rx_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_ring_tx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_copi, reg_bsn_monitor_v2_ring_tx_cipo );
-
- u_mm_file_reg_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_copi, reg_diag_bg_cipo );
- u_mm_file_ram_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_copi, ram_diag_bg_cipo );
-
- u_mm_file_reg_ring_lane_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO")
- port map(mm_rst, mm_clk, reg_ring_lane_info_copi, reg_ring_lane_info_cipo );
-
- u_mm_file_reg_dp_xonoff_lane : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LANE")
- port map(mm_rst, mm_clk, reg_dp_xonoff_lane_copi, reg_dp_xonoff_lane_cipo );
-
- u_mm_file_reg_dp_xonoff_local : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LOCAL")
- port map(mm_rst, mm_clk, reg_dp_xonoff_local_copi, reg_dp_xonoff_local_cipo );
-
- u_mm_file_reg_ring_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
- port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo);
-
- u_mm_file_reg_tr_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
-
- u_mm_file_reg_tr_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
-
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
+
+ u_mm_file_reg_dp_block_validate_err : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_copi, reg_dp_block_validate_err_cipo );
+
+ u_mm_file_reg_dp_block_validate_bsn_at_sync : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_copi, reg_dp_block_validate_bsn_at_sync_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_ring_rx : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_copi, reg_bsn_monitor_v2_ring_rx_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_ring_tx : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_copi, reg_bsn_monitor_v2_ring_tx_cipo );
+
+ u_mm_file_reg_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_copi, reg_diag_bg_cipo );
+ u_mm_file_ram_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_copi, ram_diag_bg_cipo );
+
+ u_mm_file_reg_ring_lane_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO")
+ port map(mm_rst, mm_clk, reg_ring_lane_info_copi, reg_ring_lane_info_cipo );
+
+ u_mm_file_reg_dp_xonoff_lane : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LANE")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_lane_copi, reg_dp_xonoff_lane_cipo );
+
+ u_mm_file_reg_dp_xonoff_local : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LOCAL")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_local_copi, reg_dp_xonoff_local_cipo );
+
+ u_mm_file_reg_ring_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
+ port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo);
+
+ u_mm_file_reg_tr_10GbE_mac : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
+
+ u_mm_file_reg_tr_10GbE_eth10g : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
+
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
index 44c943c0a7..f7f5197d72 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
@@ -19,227 +19,227 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_ring_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_ring is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export
- ram_diag_bg_clk_export : out std_logic; -- export
- ram_diag_bg_read_export : out std_logic; -- export
- ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_reset_export : out std_logic; -- export
- ram_diag_bg_write_export : out std_logic; -- export
- ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_clk_export : out std_logic; -- export
- reg_diag_bg_read_export : out std_logic; -- export
- reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_reset_export : out std_logic; -- export
- reg_diag_bg_write_export : out std_logic; -- export
- reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export
- reg_dp_block_validate_err_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_read_export : out std_logic; -- export
- reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_write_export : out std_logic; -- export
- reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_lane_clk_export : out std_logic; -- export
- reg_dp_xonoff_lane_read_export : out std_logic; -- export
- reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_lane_reset_export : out std_logic; -- export
- reg_dp_xonoff_lane_write_export : out std_logic; -- export
- reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_local_clk_export : out std_logic; -- export
- reg_dp_xonoff_local_read_export : out std_logic; -- export
- reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_local_reset_export : out std_logic; -- export
- reg_dp_xonoff_local_write_export : out std_logic; -- export
- reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_ring_lane_info_clk_export : out std_logic; -- export
- reg_ring_lane_info_read_export : out std_logic; -- export
- reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_reset_export : out std_logic; -- export
- reg_ring_lane_info_write_export : out std_logic; -- export
- reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2b_ring;
+ component qsys_lofar2_unb2b_ring is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export
+ ram_diag_bg_clk_export : out std_logic; -- export
+ ram_diag_bg_read_export : out std_logic; -- export
+ ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_reset_export : out std_logic; -- export
+ ram_diag_bg_write_export : out std_logic; -- export
+ ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_clk_export : out std_logic; -- export
+ reg_diag_bg_read_export : out std_logic; -- export
+ reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_reset_export : out std_logic; -- export
+ reg_diag_bg_write_export : out std_logic; -- export
+ reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_dp_block_validate_err_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_xonoff_lane_clk_export : out std_logic; -- export
+ reg_dp_xonoff_lane_read_export : out std_logic; -- export
+ reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_lane_reset_export : out std_logic; -- export
+ reg_dp_xonoff_lane_write_export : out std_logic; -- export
+ reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_xonoff_local_clk_export : out std_logic; -- export
+ reg_dp_xonoff_local_read_export : out std_logic; -- export
+ reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_local_reset_export : out std_logic; -- export
+ reg_dp_xonoff_local_write_export : out std_logic; -- export
+ reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_ring_lane_info_clk_export : out std_logic; -- export
+ reg_ring_lane_info_read_export : out std_logic; -- export
+ reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_reset_export : out std_logic; -- export
+ reg_ring_lane_info_write_export : out std_logic; -- export
+ reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2b_ring;
end qsys_lofar2_unb2b_ring_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
index d3b80ca5d9..a849e66204 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
@@ -29,9 +29,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_pkg.all;
entity tb_tb_lofar2_unb2b_ring is
end tb_tb_lofar2_unb2b_ring;
@@ -42,14 +42,14 @@ architecture tb of tb_tb_lofar2_unb2b_ring is
signal tb_end_vec : std_logic_vector(c_nof_tb - 1 downto 0) := (others => '0');
signal tb_end : std_logic; -- declare tb_end as STD_LOGIC to avoid 'No objects found' error on 'when -label tb_end' in *.do file
begin
--- g_multi_tb : BOOLEAN := FALSE;
--- g_unb_nr : NATURAL := 4;
--- g_design_name : STRING := "lofar2_unb2c_ring_one";
--- g_nof_rn : NATURAL := 16;
--- g_nof_block_per_sync : NATURAL := 32;
--- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
+ -- g_multi_tb : BOOLEAN := FALSE;
+ -- g_unb_nr : NATURAL := 4;
+ -- g_design_name : STRING := "lofar2_unb2c_ring_one";
+ -- g_nof_rn : NATURAL := 16;
+ -- g_nof_block_per_sync : NATURAL := 32;
+ -- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
--- using different g_unb_nr to avoid MM file clashing.
+ -- using different g_unb_nr to avoid MM file clashing.
u_one_1 : entity work.tb_lofar2_unb2b_ring generic map(true, 0, "lofar2_unb2b_ring_one", c_nof_rn, 3, 1) port map(tb_end_vec(0)); -- access scheme 1.
u_one_2_3 : entity work.tb_lofar2_unb2b_ring generic map(true, 1, "lofar2_unb2b_ring_one", c_nof_rn, 3, 2) port map(tb_end_vec(1)); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
u_full_1 : entity work.tb_lofar2_unb2b_ring generic map(true, 2, "lofar2_unb2b_ring_full", c_nof_rn, 3, 1) port map(tb_end_vec(2)); -- access scheme 1.
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
index bd619d7932..bcd3dba039 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete SDP station design with AIT input stage with 12 ADC streams, oversampeld FSUB, XSUB, BF and RING
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity disturb2_unb2b_sdp_station_full is
generic (
@@ -90,7 +90,7 @@ entity disturb2_unb2b_sdp_station_full is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -122,67 +122,67 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
index f8d6304056..d09f22cd75 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
@@ -26,15 +26,15 @@
-- Contains AIT input stage with WG, oversampled FSUB, XSUB, BF and RING, so without ADC JESD.
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity disturb2_unb2b_sdp_station_full_wg is
generic (
@@ -100,61 +100,61 @@ end disturb2_unb2b_sdp_station_full_wg;
architecture str of disturb2_unb2b_sdp_station_full_wg is
begin
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_wpfb => g_wpfb,
- g_wpfb_complex => g_wpfb_complex
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_wpfb => g_wpfb,
+ g_wpfb_complex => g_wpfb_complex
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
index 061841c5e4..85ef8c9df1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_adc is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2b_sdp_station_adc is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
index 852d977aee..8479da0e82 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_bf is
generic (
@@ -81,7 +81,7 @@ entity lofar2_unb2b_sdp_station_bf is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -113,58 +113,58 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
index 4869935901..877fe97c9a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_fsub is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2b_sdp_station_fsub is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
index fd878bb3cf..a26ca92a9b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete SDP station design with AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_full is
generic (
@@ -90,7 +90,7 @@ entity lofar2_unb2b_sdp_station_full is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -122,67 +122,67 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
index 5412994b0e..5321f5e2c1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
@@ -26,13 +26,13 @@
-- Contains AIT input stage with WG, FSUB, XSUB, BF and RING, so without ADC JESD.
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_full_wg is
generic (
@@ -96,59 +96,59 @@ end lofar2_unb2b_sdp_station_full_wg;
architecture str of lofar2_unb2b_sdp_station_full_wg is
begin
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
index 925e86ef84..c7d563a7d3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and XSUB for XST from one node.
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_xsub_one is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2b_sdp_station_xsub_one is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
index 1cd39a4cd9..693db344f0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -26,13 +26,13 @@
-- Contains complete SDP station design with AIT input stage with 12 ADC streams, FSUB, XSUB with ring
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_xsub_ring is
generic (
@@ -90,7 +90,7 @@ entity lofar2_unb2b_sdp_station_xsub_ring is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -122,67 +122,67 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index f4947909cf..52e900da8d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -27,20 +27,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2b_sdp_station_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2b_sdp_station_pkg.all;
+ use eth_lib.eth_pkg.all;
entity lofar2_unb2b_sdp_station is
generic (
@@ -104,9 +104,9 @@ entity lofar2_unb2b_sdp_station is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0) := (others => '0'); -- c_sdp_S_pn = 12, c_unb2b_board_nof_tr_jesd204b = 6
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic := '0'; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -486,315 +486,315 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
- g_dp_clk_use_pll => false,
- g_udp_offload => true,
- g_udp_offload_nof_streams => c_eth_nof_udp_ports
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_copi,
- reg_remu_miso => reg_remu_cipo,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_copi,
- reg_dpmm_data_miso => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_copi,
- reg_mmdp_data_miso => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_copi,
- reg_epcs_miso => reg_epcs_cipo,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_copi,
- reg_wdi_miso => reg_wdi_cipo,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_copi,
- reg_unb_system_info_miso => reg_unb_system_info_cipo,
- rom_unb_system_info_mosi => rom_unb_system_info_copi,
- rom_unb_system_info_miso => rom_unb_system_info_cipo,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_copi,
- reg_unb_sens_miso => reg_unb_sens_cipo,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_copi,
- reg_unb_pmbus_miso => reg_unb_pmbus_cipo,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_copi,
- reg_ppsh_miso => reg_ppsh_cipo,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_copi,
- eth1g_tse_miso => eth1g_tse_cipo,
- eth1g_reg_mosi => eth1g_reg_copi,
- eth1g_reg_miso => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_copi,
- eth1g_ram_miso => eth1g_ram_cipo,
-
- -- eth1g UDP streaming
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- ram_scrap_mosi => ram_scrap_copi,
- ram_scrap_miso => ram_scrap_cipo,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
+ g_dp_clk_use_pll => false,
+ g_udp_offload => true,
+ g_udp_offload_nof_streams => c_eth_nof_udp_ports
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_copi,
+ reg_unb_sens_miso => reg_unb_sens_cipo,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_cipo,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
+
+ -- eth1g UDP streaming
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2b_sdp_station
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_copi => reg_wdi_copi,
- reg_wdi_cipo => reg_wdi_cipo,
- reg_unb_system_info_copi => reg_unb_system_info_copi,
- reg_unb_system_info_cipo => reg_unb_system_info_cipo,
- rom_unb_system_info_copi => rom_unb_system_info_copi,
- rom_unb_system_info_cipo => rom_unb_system_info_cipo,
- reg_unb_sens_copi => reg_unb_sens_copi,
- reg_unb_sens_cipo => reg_unb_sens_cipo,
- reg_unb_pmbus_copi => reg_unb_pmbus_copi,
- reg_unb_pmbus_cipo => reg_unb_pmbus_cipo,
- reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
- reg_ppsh_copi => reg_ppsh_copi,
- reg_ppsh_cipo => reg_ppsh_cipo,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_copi => eth1g_tse_copi,
- eth1g_tse_cipo => eth1g_tse_cipo,
- eth1g_reg_copi => eth1g_reg_copi,
- eth1g_reg_cipo => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_copi => eth1g_ram_copi,
- eth1g_ram_cipo => eth1g_ram_cipo,
- reg_dpmm_data_copi => reg_dpmm_data_copi,
- reg_dpmm_data_cipo => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
- reg_mmdp_data_copi => reg_mmdp_data_copi,
- reg_mmdp_data_cipo => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
- reg_epcs_copi => reg_epcs_copi,
- reg_epcs_cipo => reg_epcs_cipo,
- reg_remu_copi => reg_remu_copi,
- reg_remu_cipo => reg_remu_cipo,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_copi => jesd204b_copi,
- jesd204b_cipo => jesd204b_cipo,
- jesd_ctrl_copi => jesd_ctrl_copi,
- jesd_ctrl_cipo => jesd_ctrl_cipo,
- reg_dp_shiftram_copi => reg_dp_shiftram_copi,
- reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
- reg_wg_copi => reg_wg_copi,
- reg_wg_cipo => reg_wg_cipo,
- ram_wg_copi => ram_wg_copi,
- ram_wg_cipo => ram_wg_cipo,
- reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_copi => ram_st_histogram_copi,
- ram_st_histogram_cipo => ram_st_histogram_cipo,
- reg_aduh_monitor_copi => reg_aduh_monitor_copi,
- reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
- ram_st_sst_copi => ram_st_sst_copi,
- ram_st_sst_cipo => ram_st_sst_cipo,
- ram_fil_coefs_copi => ram_fil_coefs_copi,
- ram_fil_coefs_cipo => ram_fil_coefs_cipo,
- reg_si_copi => reg_si_copi,
- reg_si_cipo => reg_si_cipo,
- ram_equalizer_gains_copi => ram_equalizer_gains_copi,
- ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
- ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
- ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
- reg_dp_selector_copi => reg_dp_selector_copi,
- reg_dp_selector_cipo => reg_dp_selector_cipo,
- reg_sdp_info_copi => reg_sdp_info_copi,
- reg_sdp_info_cipo => reg_sdp_info_cipo,
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
- ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
- ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
- ram_bf_weights_copi => ram_bf_weights_copi,
- ram_bf_weights_cipo => ram_bf_weights_cipo,
- reg_bf_scale_copi => reg_bf_scale_copi,
- reg_bf_scale_cipo => reg_bf_scale_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_dp_xonoff_copi => reg_dp_xonoff_copi,
- reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
- ram_st_bst_copi => ram_st_bst_copi,
- ram_st_bst_cipo => ram_st_bst_cipo,
- reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
- reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
- reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
- reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
- reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
- reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
- reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
- reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
- reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
- reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
- reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
- reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
- reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
- reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
- reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
- ram_scrap_copi => ram_scrap_copi,
- ram_scrap_cipo => ram_scrap_cipo,
- reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
- reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
- reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
- reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
- reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
- reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
- reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
- reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
- reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
- reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_unb_sens_copi => reg_unb_sens_copi,
+ reg_unb_sens_cipo => reg_unb_sens_cipo,
+ reg_unb_pmbus_copi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_cipo => reg_unb_pmbus_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo,
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+ reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo
+ );
-- Use full 8 bit gn_id = ID
gn_id <= ID;
@@ -803,200 +803,200 @@ begin
-- sdp nodes
-----------------------------------------------------------------------------
u_sdp_station : entity lofar2_sdp_lib.sdp_station
- generic map (
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_wpfb_complex => g_wpfb_complex,
- g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
- g_scope_selected_subband => g_scope_selected_subband,
- g_no_jesd => c_revision_select.no_jesd,
- g_use_fsub => c_revision_select.use_fsub,
- g_use_oversample => c_revision_select.use_oversample,
- g_use_xsub => c_revision_select.use_xsub,
- g_use_bf => c_revision_select.use_bf,
- g_use_ring => c_revision_select.use_ring,
- g_P_sq => c_revision_select.P_sq
- )
- port map (
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_pps => dp_pps,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- gn_id => gn_id,
- this_bck_id => this_bck_id,
- this_chip_id => this_chip_id,
-
- SA_CLK => SA_CLK,
-
- -- jesd204b
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => JESD204B_SYNC_N,
-
- -- UDP Offload
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- -- 10 GbE
- reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
- reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
- reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
- reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
-
- -- AIT
- jesd204b_copi => jesd204b_copi,
- jesd204b_cipo => jesd204b_cipo,
- jesd_ctrl_copi => jesd_ctrl_copi,
- jesd_ctrl_cipo => jesd_ctrl_cipo,
- reg_dp_shiftram_copi => reg_dp_shiftram_copi,
- reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
- reg_wg_copi => reg_wg_copi,
- reg_wg_cipo => reg_wg_cipo,
- ram_wg_copi => ram_wg_copi,
- ram_wg_cipo => ram_wg_cipo,
- reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_copi => ram_st_histogram_copi,
- ram_st_histogram_cipo => ram_st_histogram_cipo,
- reg_aduh_monitor_copi => reg_aduh_monitor_copi,
- reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
-
- -- FSUB
- ram_st_sst_copi => ram_st_sst_copi,
- ram_st_sst_cipo => ram_st_sst_cipo,
- reg_si_copi => reg_si_copi,
- reg_si_cipo => reg_si_cipo,
- ram_fil_coefs_copi => ram_fil_coefs_copi,
- ram_fil_coefs_cipo => ram_fil_coefs_cipo,
- ram_equalizer_gains_copi => ram_equalizer_gains_copi,
- ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
- ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
- ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
- reg_dp_selector_copi => reg_dp_selector_copi,
- reg_dp_selector_cipo => reg_dp_selector_cipo,
-
- -- SDP Info
- reg_sdp_info_copi => reg_sdp_info_copi,
- reg_sdp_info_cipo => reg_sdp_info_cipo,
-
- -- RING Info
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
-
- -- XSUB
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo,
-
- -- BF
- ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
- ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
- ram_bf_weights_copi => ram_bf_weights_copi,
- ram_bf_weights_cipo => ram_bf_weights_cipo,
- reg_bf_scale_copi => reg_bf_scale_copi,
- reg_bf_scale_cipo => reg_bf_scale_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_dp_xonoff_copi => reg_dp_xonoff_copi,
- reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
- ram_st_bst_copi => ram_st_bst_copi,
- ram_st_bst_cipo => ram_st_bst_cipo,
- reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
- reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
- reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
- reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
- reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
- reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
- reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
- reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
- reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
- reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
- reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
-
- -- SST
- reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
- reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
- reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
- reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-
- -- XST
- reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
-
- reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
- reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
-
- -- BST
- reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
- reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
- reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
- reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
-
- RING_0_TX => RING_0_TX,
- RING_0_RX => RING_0_RX,
- RING_1_TX => RING_1_TX,
- RING_1_RX => RING_1_RX,
-
- -- QSFP serial
- unb2_board_front_io_serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- unb2_board_front_io_serial_rx_arr => unb2_board_front_io_serial_rx_arr,
-
- -- QSFP LEDS
- unb2_board_qsfp_leds_tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
- unb2_board_qsfp_leds_tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
- unb2_board_qsfp_leds_rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_wpfb_complex => g_wpfb_complex,
+ g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
+ g_scope_selected_subband => g_scope_selected_subband,
+ g_no_jesd => c_revision_select.no_jesd,
+ g_use_fsub => c_revision_select.use_fsub,
+ g_use_oversample => c_revision_select.use_oversample,
+ g_use_xsub => c_revision_select.use_xsub,
+ g_use_bf => c_revision_select.use_bf,
+ g_use_ring => c_revision_select.use_ring,
+ g_P_sq => c_revision_select.P_sq
+ )
+ port map (
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_pps => dp_pps,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ gn_id => gn_id,
+ this_bck_id => this_bck_id,
+ this_chip_id => this_chip_id,
+
+ SA_CLK => SA_CLK,
+
+ -- jesd204b
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => JESD204B_SYNC_N,
+
+ -- UDP Offload
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ -- 10 GbE
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+
+ -- AIT
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+
+ -- FSUB
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+
+ -- SDP Info
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
+
+ -- RING Info
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+
+ -- XSUB
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
+
+ -- BF
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+
+ -- SST
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
+ -- XST
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+
+ -- BST
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
+
+ RING_0_TX => RING_0_TX,
+ RING_0_RX => RING_0_RX,
+ RING_1_TX => RING_1_TX,
+ RING_1_RX => RING_1_RX,
+
+ -- QSFP serial
+ unb2_board_front_io_serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ unb2_board_front_io_serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+
+ -- QSFP LEDS
+ unb2_board_qsfp_leds_tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ unb2_board_qsfp_leds_tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ unb2_board_qsfp_leds_rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Interface : 10GbE
@@ -1010,40 +1010,40 @@ begin
-- Front IO
------------
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
------------
-- LEDs
------------
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
-
- tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
- tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
- rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+
+ tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
index dd06a93a7f..2ff2fadd78 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
@@ -20,13 +20,13 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_sdp_station_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index 194e3ee418..06f03789ca 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_sdp_station_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_sdp_station_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2b_sdp_station is
generic (
@@ -150,187 +150,187 @@ entity mmm_lofar2_unb2b_sdp_station is
reg_si_copi : out t_mem_copi;
reg_si_cipo : in t_mem_cipo;
- -- Equalizer gains
- ram_equalizer_gains_copi : out t_mem_copi;
- ram_equalizer_gains_cipo : in t_mem_cipo;
- ram_equalizer_gains_cross_copi : out t_mem_copi;
- ram_equalizer_gains_cross_cipo : in t_mem_cipo;
+ -- Equalizer gains
+ ram_equalizer_gains_copi : out t_mem_copi;
+ ram_equalizer_gains_cipo : in t_mem_cipo;
+ ram_equalizer_gains_cross_copi : out t_mem_copi;
+ ram_equalizer_gains_cross_cipo : in t_mem_cipo;
- -- DP Selector
- reg_dp_selector_copi : out t_mem_copi;
- reg_dp_selector_cipo : in t_mem_cipo;
+ -- DP Selector
+ reg_dp_selector_copi : out t_mem_copi;
+ reg_dp_selector_cipo : in t_mem_cipo;
- -- SDP Info
- reg_sdp_info_copi : out t_mem_copi;
- reg_sdp_info_cipo : in t_mem_cipo;
+ -- SDP Info
+ reg_sdp_info_copi : out t_mem_copi;
+ reg_sdp_info_cipo : in t_mem_cipo;
- -- RING Info
- reg_ring_info_copi : out t_mem_copi;
- reg_ring_info_cipo : in t_mem_cipo;
+ -- RING Info
+ reg_ring_info_copi : out t_mem_copi;
+ reg_ring_info_cipo : in t_mem_cipo;
- -- Beamlet Subband Select
- ram_ss_ss_wide_copi : out t_mem_copi;
- ram_ss_ss_wide_cipo : in t_mem_cipo;
+ -- Beamlet Subband Select
+ ram_ss_ss_wide_copi : out t_mem_copi;
+ ram_ss_ss_wide_cipo : in t_mem_cipo;
- -- Local BF bf weights
- ram_bf_weights_copi : out t_mem_copi;
- ram_bf_weights_cipo : in t_mem_cipo;
+ -- Local BF bf weights
+ ram_bf_weights_copi : out t_mem_copi;
+ ram_bf_weights_cipo : in t_mem_cipo;
- -- BF bsn aligner_v2
- reg_bsn_align_v2_bf_copi : out t_mem_copi;
- reg_bsn_align_v2_bf_cipo : in t_mem_cipo;
+ -- BF bsn aligner_v2
+ reg_bsn_align_v2_bf_copi : out t_mem_copi;
+ reg_bsn_align_v2_bf_cipo : in t_mem_cipo;
- -- BF bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_rx_align_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_rx_align_bf_cipo : in t_mem_cipo;
- reg_bsn_monitor_v2_aligned_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_aligned_bf_cipo : in t_mem_cipo;
-
- -- mms_dp_scale Scale Beamlets
- reg_bf_scale_copi : out t_mem_copi;
- reg_bf_scale_cipo : in t_mem_cipo;
-
- -- Beamlet Data Output header fields
- reg_hdr_dat_copi : out t_mem_copi;
- reg_hdr_dat_cipo : in t_mem_cipo;
-
- -- Beamlet Data Output xonoff
- reg_dp_xonoff_copi : out t_mem_copi;
- reg_dp_xonoff_cipo : in t_mem_cipo;
-
- -- BF ring lane info
- reg_ring_lane_info_bf_copi : out t_mem_copi;
- reg_ring_lane_info_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_rx_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_tx_bf_cipo : in t_mem_cipo;
-
- -- BF ring validate err
- reg_dp_block_validate_err_bf_copi : out t_mem_copi;
- reg_dp_block_validate_err_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_bf_copi : out t_mem_copi;
- reg_dp_block_validate_bsn_at_sync_bf_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics (BST)
- ram_st_bst_copi : out t_mem_copi;
- ram_st_bst_cipo : in t_mem_cipo;
-
- -- Subband Statistics offload
- reg_stat_enable_sst_copi : out t_mem_copi;
- reg_stat_enable_sst_cipo : in t_mem_cipo;
-
- -- Statistics header info
- reg_stat_hdr_dat_sst_copi : out t_mem_copi;
- reg_stat_hdr_dat_sst_cipo : in t_mem_cipo;
-
- -- Crosslet Statistics offload
- reg_stat_enable_xst_copi : out t_mem_copi;
- reg_stat_enable_xst_cipo : in t_mem_cipo;
-
- -- Crosslet Statistics header info
- reg_stat_hdr_dat_xst_copi : out t_mem_copi;
- reg_stat_hdr_dat_xst_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics offload
- reg_stat_enable_bst_copi : out t_mem_copi;
- reg_stat_enable_bst_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics header info
- reg_stat_hdr_dat_bst_copi : out t_mem_copi;
- reg_stat_hdr_dat_bst_cipo : in t_mem_cipo;
-
- -- crosslets_info
- reg_crosslets_info_copi : out t_mem_copi;
- reg_crosslets_info_cipo : in t_mem_cipo;
-
- -- crosslets_info
- reg_nof_crosslets_copi : out t_mem_copi;
- reg_nof_crosslets_cipo : in t_mem_cipo;
-
- -- bsn_sync_scheduler_xsub
- reg_bsn_sync_scheduler_xsub_copi : out t_mem_copi;
- reg_bsn_sync_scheduler_xsub_cipo : in t_mem_cipo;
-
- -- st_xsq (XST)
- ram_st_xsq_copi : out t_mem_copi;
- ram_st_xsq_cipo : in t_mem_cipo;
-
- -- 10 GbE mac
- reg_nw_10GbE_mac_copi : out t_mem_copi;
- reg_nw_10GbE_mac_cipo : in t_mem_cipo;
-
- -- 10 GbE eth
- reg_nw_10GbE_eth10g_copi : out t_mem_copi;
- reg_nw_10GbE_eth10g_cipo : in t_mem_cipo;
-
- -- XST bsn aligner_v2
- reg_bsn_align_v2_xsub_copi : out t_mem_copi;
- reg_bsn_align_v2_xsub_cipo : in t_mem_cipo;
-
- -- XST bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_rx_align_xsub_copi : out t_mem_copi;
- reg_bsn_monitor_v2_rx_align_xsub_cipo : in t_mem_cipo;
- reg_bsn_monitor_v2_aligned_xsub_copi : out t_mem_copi;
- reg_bsn_monitor_v2_aligned_xsub_cipo : in t_mem_cipo;
-
- -- XST UDP offload bsn monitor
- reg_bsn_monitor_v2_xst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_xst_offload_cipo : in t_mem_cipo;
-
- -- BST UDP offload bsn monitor
- reg_bsn_monitor_v2_bst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_bst_offload_cipo : in t_mem_cipo;
-
- -- Beamlet output bsn monitor
- reg_bsn_monitor_v2_beamlet_output_copi : out t_mem_copi;
- reg_bsn_monitor_v2_beamlet_output_cipo : in t_mem_cipo;
-
- -- SST UDP offload bsn monitor
- reg_bsn_monitor_v2_sst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_sst_offload_cipo : in t_mem_cipo;
-
- -- XST ring lane info
- reg_ring_lane_info_xst_copi : out t_mem_copi;
- reg_ring_lane_info_xst_cipo : in t_mem_cipo;
-
- -- XST ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_xst_copi: out t_mem_copi;
- reg_bsn_monitor_v2_ring_rx_xst_cipo: in t_mem_cipo;
-
- -- XST ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_xst_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_tx_xst_cipo : in t_mem_cipo;
-
- -- XST ring validate err
- reg_dp_block_validate_err_xst_copi : out t_mem_copi;
- reg_dp_block_validate_err_xst_cipo : in t_mem_cipo;
-
- -- XST ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_xst_copi : out t_mem_copi;
- reg_dp_block_validate_bsn_at_sync_xst_cipo : in t_mem_cipo;
-
- -- XST ring MAC
- reg_tr_10GbE_mac_copi : out t_mem_copi;
- reg_tr_10GbE_mac_cipo : in t_mem_cipo;
-
- -- XST ring ETH
- reg_tr_10GbE_eth10g_copi : out t_mem_copi;
- reg_tr_10GbE_eth10g_cipo : in t_mem_cipo;
-
- -- Scrap ram
- ram_scrap_copi : out t_mem_copi;
- ram_scrap_cipo : in t_mem_cipo;
-
- -- Jesd reset control
- jesd_ctrl_copi : out t_mem_copi;
- jesd_ctrl_cipo : in t_mem_cipo
+ -- BF bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_bf_cipo : in t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_aligned_bf_cipo : in t_mem_cipo;
+
+ -- mms_dp_scale Scale Beamlets
+ reg_bf_scale_copi : out t_mem_copi;
+ reg_bf_scale_cipo : in t_mem_cipo;
+
+ -- Beamlet Data Output header fields
+ reg_hdr_dat_copi : out t_mem_copi;
+ reg_hdr_dat_cipo : in t_mem_cipo;
+
+ -- Beamlet Data Output xonoff
+ reg_dp_xonoff_copi : out t_mem_copi;
+ reg_dp_xonoff_cipo : in t_mem_cipo;
+
+ -- BF ring lane info
+ reg_ring_lane_info_bf_copi : out t_mem_copi;
+ reg_ring_lane_info_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_bf_cipo : in t_mem_cipo;
+
+ -- BF ring validate err
+ reg_dp_block_validate_err_bf_copi : out t_mem_copi;
+ reg_dp_block_validate_err_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_bf_copi : out t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_bf_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics (BST)
+ ram_st_bst_copi : out t_mem_copi;
+ ram_st_bst_cipo : in t_mem_cipo;
+
+ -- Subband Statistics offload
+ reg_stat_enable_sst_copi : out t_mem_copi;
+ reg_stat_enable_sst_cipo : in t_mem_cipo;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_sst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_sst_cipo : in t_mem_cipo;
+
+ -- Crosslet Statistics offload
+ reg_stat_enable_xst_copi : out t_mem_copi;
+ reg_stat_enable_xst_cipo : in t_mem_cipo;
+
+ -- Crosslet Statistics header info
+ reg_stat_hdr_dat_xst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_xst_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics offload
+ reg_stat_enable_bst_copi : out t_mem_copi;
+ reg_stat_enable_bst_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics header info
+ reg_stat_hdr_dat_bst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_bst_cipo : in t_mem_cipo;
+
+ -- crosslets_info
+ reg_crosslets_info_copi : out t_mem_copi;
+ reg_crosslets_info_cipo : in t_mem_cipo;
+
+ -- crosslets_info
+ reg_nof_crosslets_copi : out t_mem_copi;
+ reg_nof_crosslets_cipo : in t_mem_cipo;
+
+ -- bsn_sync_scheduler_xsub
+ reg_bsn_sync_scheduler_xsub_copi : out t_mem_copi;
+ reg_bsn_sync_scheduler_xsub_cipo : in t_mem_cipo;
+
+ -- st_xsq (XST)
+ ram_st_xsq_copi : out t_mem_copi;
+ ram_st_xsq_cipo : in t_mem_cipo;
+
+ -- 10 GbE mac
+ reg_nw_10GbE_mac_copi : out t_mem_copi;
+ reg_nw_10GbE_mac_cipo : in t_mem_cipo;
+
+ -- 10 GbE eth
+ reg_nw_10GbE_eth10g_copi : out t_mem_copi;
+ reg_nw_10GbE_eth10g_cipo : in t_mem_cipo;
+
+ -- XST bsn aligner_v2
+ reg_bsn_align_v2_xsub_copi : out t_mem_copi;
+ reg_bsn_align_v2_xsub_cipo : in t_mem_cipo;
+
+ -- XST bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_xsub_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_xsub_cipo : in t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_xsub_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_aligned_xsub_cipo : in t_mem_cipo;
+
+ -- XST UDP offload bsn monitor
+ reg_bsn_monitor_v2_xst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_xst_offload_cipo : in t_mem_cipo;
+
+ -- BST UDP offload bsn monitor
+ reg_bsn_monitor_v2_bst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_bst_offload_cipo : in t_mem_cipo;
+
+ -- Beamlet output bsn monitor
+ reg_bsn_monitor_v2_beamlet_output_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_beamlet_output_cipo : in t_mem_cipo;
+
+ -- SST UDP offload bsn monitor
+ reg_bsn_monitor_v2_sst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_sst_offload_cipo : in t_mem_cipo;
+
+ -- XST ring lane info
+ reg_ring_lane_info_xst_copi : out t_mem_copi;
+ reg_ring_lane_info_xst_cipo : in t_mem_cipo;
+
+ -- XST ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_xst_copi: out t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_xst_cipo: in t_mem_cipo;
+
+ -- XST ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_xst_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_xst_cipo : in t_mem_cipo;
+
+ -- XST ring validate err
+ reg_dp_block_validate_err_xst_copi : out t_mem_copi;
+ reg_dp_block_validate_err_xst_cipo : in t_mem_cipo;
+
+ -- XST ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_xst_copi : out t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_xst_cipo : in t_mem_cipo;
+
+ -- XST ring MAC
+ reg_tr_10GbE_mac_copi : out t_mem_copi;
+ reg_tr_10GbE_mac_cipo : in t_mem_cipo;
+
+ -- XST ring ETH
+ reg_tr_10GbE_eth10g_copi : out t_mem_copi;
+ reg_tr_10GbE_eth10g_cipo : in t_mem_cipo;
+
+ -- Scrap ram
+ ram_scrap_copi : out t_mem_copi;
+ ram_scrap_cipo : in t_mem_cipo;
+
+ -- Jesd reset control
+ jesd_ctrl_copi : out t_mem_copi;
+ jesd_ctrl_cipo : in t_mem_cipo
);
end mmm_lofar2_unb2b_sdp_station;
@@ -344,214 +344,284 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
-- Must use exact g_mm_rd_latency = 1 instead of default 2, because JESD204B IP forces rddata = 0 after it has been read
- u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B", '1', 1)
- port map(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
+ u_mm_file_jesd204b : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B", '1', 1)
+ port map(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
+
+ u_mm_file_pio_jesd_ctrl : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_JESD_CTRL")
+ port map(mm_rst, mm_clk, jesd_ctrl_copi, jesd_ctrl_cipo );
+
+ u_mm_file_reg_dp_shiftram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
+ port map(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
+
+ u_mm_file_reg_bsn_source_v2 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
+ port map(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
+
+ u_mm_file_reg_bsn_scheduler : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
+
+ u_mm_file_reg_bsn_monitor_input : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
+
+ u_mm_file_reg_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
+ port map(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
+ u_mm_file_ram_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
+ port map(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
+
+ u_mm_file_ram_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
+ u_mm_file_reg_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
+
+ u_mm_file_ram_st_histogram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
+ port map(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
+
+ u_mm_file_reg_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
+
+ u_mm_file_ram_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
+ port map(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
+
+ u_mm_file_ram_fil_coefs : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
+ port map(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
+
+ u_mm_file_reg_si : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
+ port map(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
+
+ u_mm_file_ram_equalizer_gains : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
+ port map(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
+ u_mm_file_ram_equalizer_gains_cross : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS_CROSS")
+ port map(mm_rst, mm_clk, ram_equalizer_gains_cross_copi, ram_equalizer_gains_cross_cipo );
+
+ u_mm_file_reg_dp_selector : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
+ port map(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
+
+ u_mm_file_reg_sdp_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+ port map(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
+
+ u_mm_file_reg_ring_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
+ port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
+
+ u_mm_file_ram_ss_ss_wide : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ port map(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
+
+ u_mm_file_ram_bf_weights : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
+ port map(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
+
+ u_mm_file_reg_bf_scale : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
+ port map(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
+
+ u_mm_file_reg_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
+
+ u_mm_file_reg_dp_xonoff : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
+
+ u_mm_file_ram_st_bst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
+ port map(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
+
+ u_mm_file_reg_stat_enable_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
+ port map(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
+
+ u_mm_file_reg_stat_hdr_info_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
+
+ u_mm_file_reg_stat_enable_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
+ port map(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
+
+ u_mm_file_reg_stat_hdr_info_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
+
+ u_mm_file_reg_stat_enable_bst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
+ port map(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
+
+ u_mm_file_reg_stat_hdr_info_bst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
+
+ u_mm_file_reg_crosslets_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
+ port map(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
+
+ u_mm_file_reg_nof_crosslets : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
+ port map(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
+
+ u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
- u_mm_file_pio_jesd_ctrl : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_JESD_CTRL")
- port map(mm_rst, mm_clk, jesd_ctrl_copi, jesd_ctrl_cipo );
+ u_mm_file_ram_st_xsq : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
+ port map(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
+
+ u_mm_file_reg_nw_10GbE_mac : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
+ port map(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
+
+ u_mm_file_reg_nw_10GbE_eth10g : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
+ port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
+
+ u_mm_file_reg_bsn_align_v2_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_BF")
+ port map(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_rx_align_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_aligned_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
+
+ u_mm_file_reg_ring_lane_info_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_BF")
+ port map(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
- u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_rx_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
- u_mm_file_reg_bsn_source_v2 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
- port map(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_tx_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
- u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
+ u_mm_file_reg_dp_block_validate_err_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_BF")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
- u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
+ u_mm_file_reg_dp_block_validate_bsn_at_sync_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
- u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
- u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
+ u_mm_file_reg_bsn_align_v2_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
- u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
- u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_align_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
- u_mm_file_ram_st_histogram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
- port map(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
+ u_mm_file_reg_bsn_monitor_v2_aligned_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
- u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
+ u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
- u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
+ u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
- u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
+ u_mm_file_reg_bsn_monitor_v2_beamlet_output : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BEAMLET_OUTPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
- u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
+ u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
- u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
- u_mm_file_ram_equalizer_gains_cross : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS_CROSS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_cross_copi, ram_equalizer_gains_cross_cipo );
+ u_mm_file_reg_ring_lane_info_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
+ port map(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
- u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_XST")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
- u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_tx_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_XST")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_xst_copi, reg_bsn_monitor_v2_ring_tx_xst_cipo );
- u_mm_file_reg_ring_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
- port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
+ u_mm_file_reg_dp_block_validate_err_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_XST")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_xst_copi, reg_dp_block_validate_err_xst_cipo );
- u_mm_file_ram_ss_ss_wide : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
+ u_mm_file_reg_dp_block_validate_bsn_at_sync_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_xst_copi, reg_dp_block_validate_bsn_at_sync_xst_cipo );
- u_mm_file_ram_bf_weights : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- port map(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
+ u_mm_file_reg_tr_10GbE_mac : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
- u_mm_file_reg_bf_scale : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
- port map(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
+ u_mm_file_reg_tr_10GbE_eth10g : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
- u_mm_file_reg_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
- port map(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
-
- u_mm_file_reg_dp_xonoff : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
- port map(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
-
- u_mm_file_ram_st_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
- port map(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
-
- u_mm_file_reg_stat_enable_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
- port map(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
-
- u_mm_file_reg_stat_hdr_info_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
-
- u_mm_file_reg_stat_enable_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
- port map(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
-
- u_mm_file_reg_stat_hdr_info_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
-
- u_mm_file_reg_stat_enable_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
- port map(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
-
- u_mm_file_reg_stat_hdr_info_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
-
- u_mm_file_reg_crosslets_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
- port map(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
-
- u_mm_file_reg_nof_crosslets : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
- port map(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
-
- u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
-
- u_mm_file_ram_st_xsq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
- port map(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
-
- u_mm_file_reg_nw_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
-
- u_mm_file_reg_nw_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
-
- u_mm_file_reg_bsn_align_v2_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_BF")
- port map(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_rx_align_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_aligned_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
-
- u_mm_file_reg_ring_lane_info_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_BF")
- port map(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_ring_rx_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_ring_tx_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
-
- u_mm_file_reg_dp_block_validate_err_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_BF")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
-
- u_mm_file_reg_dp_block_validate_bsn_at_sync_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
-
- u_mm_file_reg_bsn_align_v2_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_rx_align_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_aligned_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_beamlet_output : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BEAMLET_OUTPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
-
- u_mm_file_reg_ring_lane_info_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
- port map(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_XST")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_ring_tx_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_XST")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_xst_copi, reg_bsn_monitor_v2_ring_tx_xst_cipo );
-
- u_mm_file_reg_dp_block_validate_err_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_XST")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_xst_copi, reg_dp_block_validate_err_xst_cipo );
-
- u_mm_file_reg_dp_block_validate_bsn_at_sync_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_xst_copi, reg_dp_block_validate_bsn_at_sync_xst_cipo );
-
- u_mm_file_reg_tr_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
-
- u_mm_file_reg_tr_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
-
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -627,8 +697,8 @@ begin
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
--- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
+ -- ToDo: This has changed in the peripherals package
+ -- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
rom_system_info_write_export => rom_unb_system_info_copi.wr,
rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 5b73786a97..dfe4d6ed30 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -19,562 +19,562 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_sdp_station_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_sdp_station is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_cross_clk_export : out std_logic; -- export
- ram_equalizer_gains_cross_read_export : out std_logic; -- export
- ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_cross_reset_export : out std_logic; -- export
- ram_equalizer_gains_cross_write_export : out std_logic; -- export
- ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
- ram_st_histogram_clk_export : out std_logic; -- export
- ram_st_histogram_read_export : out std_logic; -- export
- ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_histogram_reset_export : out std_logic; -- export
- ram_st_histogram_write_export : out std_logic; -- export
- ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
- ram_st_xsq_clk_export : out std_logic; -- export
- ram_st_xsq_read_export : out std_logic; -- export
- ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_xsq_reset_export : out std_logic; -- export
- ram_st_xsq_write_export : out std_logic; -- export
- ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
- reg_bsn_align_v2_bf_read_export : out std_logic; -- export
- reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
- reg_bsn_align_v2_bf_write_export : out std_logic; -- export
- reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_crosslets_info_clk_export : out std_logic; -- export
- reg_crosslets_info_read_export : out std_logic; -- export
- reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_reset_export : out std_logic; -- export
- reg_crosslets_info_write_export : out std_logic; -- export
- reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nof_crosslets_clk_export : out std_logic; -- export
- reg_nof_crosslets_read_export : out std_logic; -- export
- reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nof_crosslets_reset_export : out std_logic; -- export
- reg_nof_crosslets_write_export : out std_logic; -- export
- reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_lane_info_bf_clk_export : out std_logic; -- export
- reg_ring_lane_info_bf_read_export : out std_logic; -- export
- reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_bf_reset_export : out std_logic; -- export
- reg_ring_lane_info_bf_write_export : out std_logic; -- export
- reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ring_lane_info_xst_clk_export : out std_logic; -- export
- reg_ring_lane_info_xst_read_export : out std_logic; -- export
- reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_xst_reset_export : out std_logic; -- export
- reg_ring_lane_info_xst_write_export : out std_logic; -- export
- reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_stat_enable_bst_clk_export : out std_logic; -- export
- reg_stat_enable_bst_read_export : out std_logic; -- export
- reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_bst_reset_export : out std_logic; -- export
- reg_stat_enable_bst_write_export : out std_logic; -- export
- reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_sst_clk_export : out std_logic; -- export
- reg_stat_enable_sst_read_export : out std_logic; -- export
- reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_sst_reset_export : out std_logic; -- export
- reg_stat_enable_sst_write_export : out std_logic; -- export
- reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_xst_clk_export : out std_logic; -- export
- reg_stat_enable_xst_read_export : out std_logic; -- export
- reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_xst_reset_export : out std_logic; -- export
- reg_stat_enable_xst_write_export : out std_logic; -- export
- reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2b_sdp_station;
+ component qsys_lofar2_unb2b_sdp_station is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bf_weights_clk_export : out std_logic; -- export
+ ram_bf_weights_read_export : out std_logic; -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_bf_weights_reset_export : out std_logic; -- export
+ ram_bf_weights_write_export : out std_logic; -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_cross_clk_export : out std_logic; -- export
+ ram_equalizer_gains_cross_read_export : out std_logic; -- export
+ ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_cross_reset_export : out std_logic; -- export
+ ram_equalizer_gains_cross_write_export : out std_logic; -- export
+ ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_st_bst_clk_export : out std_logic; -- export
+ ram_st_bst_read_export : out std_logic; -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_bst_reset_export : out std_logic; -- export
+ ram_st_bst_write_export : out std_logic; -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_st_histogram_clk_export : out std_logic; -- export
+ ram_st_histogram_read_export : out std_logic; -- export
+ ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_histogram_reset_export : out std_logic; -- export
+ ram_st_histogram_write_export : out std_logic; -- export
+ ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
+ ram_st_xsq_clk_export : out std_logic; -- export
+ ram_st_xsq_read_export : out std_logic; -- export
+ ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_xsq_reset_export : out std_logic; -- export
+ ram_st_xsq_write_export : out std_logic; -- export
+ ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bf_scale_clk_export : out std_logic; -- export
+ reg_bf_scale_read_export : out std_logic; -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bf_scale_reset_export : out std_logic; -- export
+ reg_bf_scale_write_export : out std_logic; -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_read_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_write_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_v2_clk_export : out std_logic; -- export
+ reg_bsn_source_v2_read_export : out std_logic; -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_v2_reset_export : out std_logic; -- export
+ reg_bsn_source_v2_write_export : out std_logic; -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_crosslets_info_clk_export : out std_logic; -- export
+ reg_crosslets_info_read_export : out std_logic; -- export
+ reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_reset_export : out std_logic; -- export
+ reg_crosslets_info_write_export : out std_logic; -- export
+ reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_xonoff_clk_export : out std_logic; -- export
+ reg_dp_xonoff_read_export : out std_logic; -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_reset_export : out std_logic; -- export
+ reg_dp_xonoff_write_export : out std_logic; -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_clk_export : out std_logic; -- export
+ reg_hdr_dat_read_export : out std_logic; -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_reset_export : out std_logic; -- export
+ reg_hdr_dat_write_export : out std_logic; -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nof_crosslets_clk_export : out std_logic; -- export
+ reg_nof_crosslets_read_export : out std_logic; -- export
+ reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nof_crosslets_reset_export : out std_logic; -- export
+ reg_nof_crosslets_write_export : out std_logic; -- export
+ reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic; -- export
+ reg_nw_10gbe_mac_read_export : out std_logic; -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic; -- export
+ reg_nw_10gbe_mac_write_export : out std_logic; -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_lane_info_bf_clk_export : out std_logic; -- export
+ reg_ring_lane_info_bf_read_export : out std_logic; -- export
+ reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_bf_reset_export : out std_logic; -- export
+ reg_ring_lane_info_bf_write_export : out std_logic; -- export
+ reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_ring_lane_info_xst_clk_export : out std_logic; -- export
+ reg_ring_lane_info_xst_read_export : out std_logic; -- export
+ reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_xst_reset_export : out std_logic; -- export
+ reg_ring_lane_info_xst_write_export : out std_logic; -- export
+ reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_stat_enable_bst_clk_export : out std_logic; -- export
+ reg_stat_enable_bst_read_export : out std_logic; -- export
+ reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_bst_reset_export : out std_logic; -- export
+ reg_stat_enable_bst_write_export : out std_logic; -- export
+ reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_sst_clk_export : out std_logic; -- export
+ reg_stat_enable_sst_read_export : out std_logic; -- export
+ reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_sst_reset_export : out std_logic; -- export
+ reg_stat_enable_sst_write_export : out std_logic; -- export
+ reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_xst_clk_export : out std_logic; -- export
+ reg_stat_enable_xst_read_export : out std_logic; -- export
+ reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_xst_reset_export : out std_logic; -- export
+ reg_stat_enable_xst_write_export : out std_logic; -- export
+ reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2b_sdp_station;
end qsys_lofar2_unb2b_sdp_station_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
index 1556515bae..555f8d81e1 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
@@ -21,16 +21,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, lofar2_ddrctrl_lib, tech_ddr_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use diag_lib.diag_pkg.all;
entity lofar2_unb2c_ddrctrl is
generic (
@@ -255,85 +255,85 @@ begin
end process;
u_bsn_source_v2 : entity dp_lib.mms_dp_bsn_source_v2
- generic map (
- g_cross_clock_domain => true,
- g_block_size => c_bs_block_size,
- g_nof_clk_per_sync => c_bsn_nof_clk_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => st_pps,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_v2_mosi,
- reg_miso => reg_bsn_source_v2_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi,
-
- bs_restart => open
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_block_size => c_bs_block_size,
+ g_nof_clk_per_sync => c_bsn_nof_clk_per_sync,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => st_pps,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_bsn_source_v2_mosi,
+ reg_miso => reg_bsn_source_v2_miso,
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi,
+
+ bs_restart => open
+ );
u_bsn_trigger_wg : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => true,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_mosi,
- reg_miso => reg_bsn_scheduler_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
- trigger_out => trigger_wg
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_mosi,
+ reg_miso => reg_bsn_scheduler_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ trigger_out => trigger_wg
+ );
u_wg_arr : entity diag_lib.mms_diag_wg_wideband_arr
- generic map (
- g_nof_streams => c_nof_streams,
- g_cross_clock_domain => true,
- g_buf_dir => c_wg_buf_directory,
-
- -- Wideband parameters
- g_wideband_factor => 1,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => c_wg_buf_dat_w,
- g_buf_addr_w => c_wg_buf_addr_w,
- g_calc_support => true,
- g_calc_gain_w => 1,
- g_calc_dat_w => c_sdp_W_adc
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_wg_wideband_arr_mosi,
- reg_miso => reg_wg_wideband_arr_miso,
-
- buf_mosi => ram_wg_wideband_arr_mosi,
- buf_miso => ram_wg_wideband_arr_miso,
-
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
- st_restart => trigger_wg,
-
- out_sosi_arr => wg_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_cross_clock_domain => true,
+ g_buf_dir => c_wg_buf_directory,
+
+ -- Wideband parameters
+ g_wideband_factor => 1,
+
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => c_wg_buf_dat_w,
+ g_buf_addr_w => c_wg_buf_addr_w,
+ g_calc_support => true,
+ g_calc_gain_w => 1,
+ g_calc_dat_w => c_sdp_W_adc
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_wg_wideband_arr_mosi,
+ reg_miso => reg_wg_wideband_arr_miso,
+
+ buf_mosi => ram_wg_wideband_arr_mosi,
+ buf_miso => ram_wg_wideband_arr_miso,
+
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_restart => trigger_wg,
+
+ out_sosi_arr => wg_sosi_arr
+ );
gen_concat : for I in 0 to c_sdp_S_pn - 1 generate
p_sosi : process(wg_sosi_arr(I), bs_sosi)
@@ -344,397 +344,397 @@ begin
end generate;
u_stop_in_reg : entity common_lib.mms_common_reg
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_stop_in_mosi,
- reg_miso => reg_stop_in_miso,
+ reg_mosi => reg_stop_in_mosi,
+ reg_miso => reg_stop_in_miso,
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
- in_reg => stop_in_arr,
- out_reg => stop_in_arr
- );
+ in_reg => stop_in_arr,
+ out_reg => stop_in_arr
+ );
u_ddrctrl_ctrl_state_reg : entity common_lib.mms_common_reg
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_ddrctrl_ctrl_state_mosi,
- reg_miso => reg_ddrctrl_ctrl_state_miso,
+ reg_mosi => reg_ddrctrl_ctrl_state_mosi,
+ reg_miso => reg_ddrctrl_ctrl_state_miso,
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
- in_reg => ddrctrl_ctrl_state,
- out_reg => open
- );
+ in_reg => ddrctrl_ctrl_state,
+ out_reg => open
+ );
u_ddrctrl : entity lofar2_ddrctrl_lib.ddrctrl
- generic map (
- g_tech_ddr => c_tech_ddr,
- g_sim_model => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_stop_percentage => c_stop_percentage,
- g_block_size => c_bs_block_size
- )
- port map (
- clk => st_clk,
- rst => st_rst,
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- in_sosi_arr => st_sosi_arr,
- stop_in => stop_in_arr(0),
- out_sosi_arr => out_sosi_arr_ddrctrl,
- out_siso => out_siso,
- ddrctrl_ctrl_state => ddrctrl_ctrl_state,
-
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- --PHY
- phy3_in => phy3_in,
- phy3_io => phy3_io,
- phy3_ou => phy3_ou,
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU
- );
+ generic map (
+ g_tech_ddr => c_tech_ddr,
+ g_sim_model => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_stop_percentage => c_stop_percentage,
+ g_block_size => c_bs_block_size
+ )
+ port map (
+ clk => st_clk,
+ rst => st_rst,
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ in_sosi_arr => st_sosi_arr,
+ stop_in => stop_in_arr(0),
+ out_sosi_arr => out_sosi_arr_ddrctrl,
+ out_siso => out_siso,
+ ddrctrl_ctrl_state => ddrctrl_ctrl_state,
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ --PHY
+ phy3_in => phy3_in,
+ phy3_io => phy3_io,
+ phy3_ou => phy3_ou,
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU
+ );
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer_dev
- generic map (
- g_technology => g_technology,
-
- -- General
- g_nof_streams => c_nof_streams,
-
- -- DB settings
- g_data_type => c_data_type,
- g_data_w => c_word_w,
- g_buf_nof_data => c_buf_nof_words,
- g_buf_use_sync => false,
- g_use_steps => false,
- g_nof_steps => c_diag_seq_rx_reg_nof_steps
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_data_buf_mosi => reg_data_buf_mosi,
- reg_data_buf_miso => reg_data_buf_miso,
-
- ram_data_buf_mosi => ram_data_buf_mosi,
- ram_data_buf_miso => ram_data_buf_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- in_sync => st_pps,
- in_sosi_arr => in_sosi_arr_data_buf,
- out_wr_done_arr => out_wr_data_done_arr
- );
+ generic map (
+ g_technology => g_technology,
+
+ -- General
+ g_nof_streams => c_nof_streams,
+
+ -- DB settings
+ g_data_type => c_data_type,
+ g_data_w => c_word_w,
+ g_buf_nof_data => c_buf_nof_words,
+ g_buf_use_sync => false,
+ g_use_steps => false,
+ g_nof_steps => c_diag_seq_rx_reg_nof_steps
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_data_buf_mosi => reg_data_buf_mosi,
+ reg_data_buf_miso => reg_data_buf_miso,
+
+ ram_data_buf_mosi => ram_data_buf_mosi,
+ ram_data_buf_miso => ram_data_buf_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ in_sync => st_pps,
+ in_sosi_arr => in_sosi_arr_data_buf,
+ out_wr_done_arr => out_wr_data_done_arr
+ );
u_diag_bsn_buffer : entity diag_lib.mms_diag_data_buffer_dev
- generic map (
- g_technology => g_technology,
-
- -- General
- g_nof_streams => c_nof_streams,
-
- -- DB settings
- g_data_type => c_bsn_type,
- g_data_w => c_dp_stream_bsn_w,
- g_buf_nof_data => c_buf_nof_words,
- g_buf_use_sync => false,
- g_use_steps => false,
- g_nof_steps => c_diag_seq_rx_reg_nof_steps
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_data_buf_mosi => reg_bsn_buf_mosi,
- reg_data_buf_miso => reg_bsn_buf_miso,
-
- ram_data_buf_mosi => ram_bsn_buf_mosi,
- ram_data_buf_miso => ram_bsn_buf_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- in_sync => st_pps,
- in_sosi_arr => in_sosi_arr_data_buf,
- out_wr_done_arr => out_wr_bsn_done_arr
- );
+ generic map (
+ g_technology => g_technology,
+
+ -- General
+ g_nof_streams => c_nof_streams,
+
+ -- DB settings
+ g_data_type => c_bsn_type,
+ g_data_w => c_dp_stream_bsn_w,
+ g_buf_nof_data => c_buf_nof_words,
+ g_buf_use_sync => false,
+ g_use_steps => false,
+ g_nof_steps => c_diag_seq_rx_reg_nof_steps
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_data_buf_mosi => reg_bsn_buf_mosi,
+ reg_data_buf_miso => reg_bsn_buf_miso,
+
+ ram_data_buf_mosi => ram_bsn_buf_mosi,
+ ram_data_buf_miso => ram_bsn_buf_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ in_sync => st_pps,
+ in_sosi_arr => in_sosi_arr_data_buf,
+ out_wr_done_arr => out_wr_bsn_done_arr
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => st_pps,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- MB_I_REF_CLK => MB_I_REF_CLK,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- scrap ram
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . 1GbE Control Interface
--- ETH_clk => ETH_CLK(0),
--- ETH_SGIN => ETH_SGIN(0),
--- ETH_SGOUT => ETH_SGOUT(0)
-
- ETH_clk => ETH_CLK(1),
- ETH_SGIN => ETH_SGIN(1),
- ETH_SGOUT => ETH_SGOUT(1)
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => st_pps,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ MB_I_REF_CLK => MB_I_REF_CLK,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- scrap ram
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . 1GbE Control Interface
+ -- ETH_clk => ETH_CLK(0),
+ -- ETH_SGIN => ETH_SGIN(0),
+ -- ETH_SGOUT => ETH_SGOUT(0)
+
+ ETH_clk => ETH_CLK(1),
+ ETH_SGIN => ETH_SGIN(1),
+ ETH_SGOUT => ETH_SGOUT(1)
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2c_ddrctrl
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- Scrap RAM
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- bsn_source_v2
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
-
- -- bsn_scheduler
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_miso,
-
- -- wg_wideband_arr
- reg_wg_wideband_arr_mosi => reg_wg_wideband_arr_mosi,
- reg_wg_wideband_arr_miso => reg_wg_wideband_arr_miso,
- ram_wg_wideband_arr_mosi => ram_wg_wideband_arr_mosi,
- ram_wg_wideband_arr_miso => ram_wg_wideband_arr_miso,
-
- -- stop_in
- reg_stop_in_mosi => reg_stop_in_mosi,
- reg_stop_in_miso => reg_stop_in_miso,
-
- -- ddrctrl_ctrl_state
- reg_ddrctrl_ctrl_state_mosi => reg_ddrctrl_ctrl_state_mosi,
- reg_ddrctrl_ctrl_state_miso => reg_ddrctrl_ctrl_state_miso,
-
- -- io_ddr
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- data_buffer
- reg_data_buf_mosi => reg_data_buf_mosi,
- reg_data_buf_miso => reg_data_buf_miso,
- ram_data_buf_mosi => ram_data_buf_mosi,
- ram_data_buf_miso => ram_data_buf_miso,
- reg_rx_seq_data_mosi => reg_rx_seq_data_mosi,
- reg_rx_seq_data_miso => reg_rx_seq_data_miso,
-
- -- bsn_buffer
- reg_bsn_buf_mosi => reg_bsn_buf_mosi,
- reg_bsn_buf_miso => reg_bsn_buf_miso,
- ram_bsn_buf_mosi => ram_bsn_buf_mosi,
- ram_bsn_buf_miso => ram_bsn_buf_miso,
- reg_rx_seq_bsn_mosi => reg_rx_seq_bsn_mosi,
- reg_rx_seq_bsn_miso => reg_rx_seq_bsn_miso
-
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- Scrap RAM
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- bsn_source_v2
+ reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
+ reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
+
+ -- bsn_scheduler
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_miso,
+
+ -- wg_wideband_arr
+ reg_wg_wideband_arr_mosi => reg_wg_wideband_arr_mosi,
+ reg_wg_wideband_arr_miso => reg_wg_wideband_arr_miso,
+ ram_wg_wideband_arr_mosi => ram_wg_wideband_arr_mosi,
+ ram_wg_wideband_arr_miso => ram_wg_wideband_arr_miso,
+
+ -- stop_in
+ reg_stop_in_mosi => reg_stop_in_mosi,
+ reg_stop_in_miso => reg_stop_in_miso,
+
+ -- ddrctrl_ctrl_state
+ reg_ddrctrl_ctrl_state_mosi => reg_ddrctrl_ctrl_state_mosi,
+ reg_ddrctrl_ctrl_state_miso => reg_ddrctrl_ctrl_state_miso,
+
+ -- io_ddr
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- data_buffer
+ reg_data_buf_mosi => reg_data_buf_mosi,
+ reg_data_buf_miso => reg_data_buf_miso,
+ ram_data_buf_mosi => ram_data_buf_mosi,
+ ram_data_buf_miso => ram_data_buf_miso,
+ reg_rx_seq_data_mosi => reg_rx_seq_data_mosi,
+ reg_rx_seq_data_miso => reg_rx_seq_data_miso,
+
+ -- bsn_buffer
+ reg_bsn_buf_mosi => reg_bsn_buf_mosi,
+ reg_bsn_buf_miso => reg_bsn_buf_miso,
+ ram_bsn_buf_mosi => ram_bsn_buf_mosi,
+ ram_bsn_buf_miso => ram_bsn_buf_miso,
+ reg_rx_seq_bsn_mosi => reg_rx_seq_bsn_mosi,
+ reg_rx_seq_bsn_miso => reg_rx_seq_bsn_miso
+
+ );
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
index bc7d3e7547..57da25a31a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2c_ddrctrl_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2c_ddrctrl_pkg.all;
entity mmm_lofar2_unb2c_ddrctrl is
generic (
@@ -137,7 +137,7 @@ entity mmm_lofar2_unb2c_ddrctrl is
reg_rx_seq_bsn_mosi : out t_mem_mosi;
reg_rx_seq_bsn_miso : in t_mem_miso
-);
+ );
end mmm_lofar2_unb2c_ddrctrl;
architecture str of mmm_lofar2_unb2c_ddrctrl is
@@ -150,69 +150,90 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_reg_bsn_source_v2 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
- port map(mm_rst, mm_clk, reg_bsn_source_v2_mosi, reg_bsn_source_v2_miso );
+ u_mm_file_reg_bsn_source_v2 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
+ port map(mm_rst, mm_clk, reg_bsn_source_v2_mosi, reg_bsn_source_v2_miso );
- u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ u_mm_file_reg_bsn_scheduler : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
- u_mm_file_reg_wg_wideband_arr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG_WIDEBAND_ARR")
- port map(mm_rst, mm_clk, reg_wg_wideband_arr_mosi, reg_wg_wideband_arr_miso);
+ u_mm_file_reg_wg_wideband_arr : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG_WIDEBAND_ARR")
+ port map(mm_rst, mm_clk, reg_wg_wideband_arr_mosi, reg_wg_wideband_arr_miso);
- u_mm_file_ram_wg_wideband_arr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG_WIDEBAND_ARR")
- port map(mm_rst, mm_clk, ram_wg_wideband_arr_mosi, ram_wg_wideband_arr_miso);
+ u_mm_file_ram_wg_wideband_arr : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG_WIDEBAND_ARR")
+ port map(mm_rst, mm_clk, ram_wg_wideband_arr_mosi, ram_wg_wideband_arr_miso);
- u_mm_file_reg_stop_in : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STOP_IN")
- port map(mm_rst, mm_clk, reg_stop_in_mosi, reg_stop_in_miso);
+ u_mm_file_reg_stop_in : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STOP_IN")
+ port map(mm_rst, mm_clk, reg_stop_in_mosi, reg_stop_in_miso);
- u_mm_file_reg_ddrctrl_state : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DDRCTRL_CTRL_STATE")
- port map(mm_rst, mm_clk, reg_ddrctrl_ctrl_state_mosi, reg_ddrctrl_ctrl_state_miso);
+ u_mm_file_reg_ddrctrl_state : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DDRCTRL_CTRL_STATE")
+ port map(mm_rst, mm_clk, reg_ddrctrl_ctrl_state_mosi, reg_ddrctrl_ctrl_state_miso);
- u_mm_file_reg_io_ddr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
- port map(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+ u_mm_file_reg_io_ddr : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
+ port map(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
- u_mm_file_reg_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DATA_BUF")
- port map(mm_rst, mm_clk, reg_data_buf_mosi, reg_data_buf_miso);
+ u_mm_file_reg_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DATA_BUF")
+ port map(mm_rst, mm_clk, reg_data_buf_mosi, reg_data_buf_miso);
- u_mm_file_ram_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DATA_BUF")
- port map(mm_rst, mm_clk, ram_data_buf_mosi, ram_data_buf_miso);
+ u_mm_file_ram_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DATA_BUF")
+ port map(mm_rst, mm_clk, ram_data_buf_mosi, ram_data_buf_miso);
- u_mm_file_reg_rx_seq_data : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RX_SEQ_DATA")
- port map(mm_rst, mm_clk, reg_rx_seq_data_mosi, reg_rx_seq_data_miso);
+ u_mm_file_reg_rx_seq_data : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RX_SEQ_DATA")
+ port map(mm_rst, mm_clk, reg_rx_seq_data_mosi, reg_rx_seq_data_miso);
- u_mm_file_reg_bsn_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_BUF")
- port map(mm_rst, mm_clk, reg_bsn_buf_mosi, reg_bsn_buf_miso);
+ u_mm_file_reg_bsn_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_BUF")
+ port map(mm_rst, mm_clk, reg_bsn_buf_mosi, reg_bsn_buf_miso);
- u_mm_file_ram_bsn_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BSN_BUF")
- port map(mm_rst, mm_clk, ram_bsn_buf_mosi, ram_bsn_buf_miso);
+ u_mm_file_ram_bsn_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BSN_BUF")
+ port map(mm_rst, mm_clk, ram_bsn_buf_mosi, ram_bsn_buf_miso);
- u_mm_file_reg_rx_seq_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RX_SEQ_BSN")
- port map(mm_rst, mm_clk, reg_rx_seq_bsn_mosi, reg_rx_seq_bsn_miso);
+ u_mm_file_reg_rx_seq_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RX_SEQ_BSN")
+ port map(mm_rst, mm_clk, reg_rx_seq_bsn_mosi, reg_rx_seq_bsn_miso);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -431,7 +452,7 @@ begin
reg_ddrctrl_ctrl_state_readdata_export => reg_ddrctrl_ctrl_state_miso.rddata(c_word_w - 1 downto 0),
reg_ddrctrl_ctrl_state_write_export => reg_ddrctrl_ctrl_state_mosi.wr,
reg_ddrctrl_ctrl_state_writedata_export => reg_ddrctrl_ctrl_state_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
index aa9cb7c67c..db0de76e41 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
@@ -20,192 +20,192 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_ddrctrl_pkg is
- ----------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus QSYS builder
- ----------------------------------------------------------------------
+ ----------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus QSYS builder
+ ----------------------------------------------------------------------
- component qsys_lofar2_unb2c_ddrctrl is
- port (
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bsn_buf_reset_export : out std_logic; -- export
- ram_bsn_buf_clk_export : out std_logic; -- export
- ram_bsn_buf_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bsn_buf_write_export : out std_logic; -- export
- ram_bsn_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bsn_buf_read_export : out std_logic; -- export
- ram_bsn_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_data_buf_reset_export : out std_logic; -- export
- ram_data_buf_clk_export : out std_logic; -- export
- ram_data_buf_address_export : out std_logic_vector(13 downto 0); -- export
- ram_data_buf_write_export : out std_logic; -- export
- ram_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_data_buf_read_export : out std_logic; -- export
- ram_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_wideband_arr_reset_export : out std_logic; -- export
- ram_wg_wideband_arr_clk_export : out std_logic; -- export
- ram_wg_wideband_arr_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_wideband_arr_write_export : out std_logic; -- export
- ram_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_wideband_arr_read_export : out std_logic; -- export
- ram_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stop_in_reset_export : out std_logic; -- export
- reg_stop_in_clk_export : out std_logic; -- export
- reg_stop_in_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stop_in_write_export : out std_logic; -- export
- reg_stop_in_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stop_in_read_export : out std_logic; -- export
- reg_stop_in_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_reset_export : out std_logic; -- export
- reg_io_ddr_clk_export : out std_logic; -- export
- reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
- reg_io_ddr_write_export : out std_logic; -- export
- reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_read_export : out std_logic; -- export
- reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_wideband_arr_reset_export : out std_logic; -- export
- reg_wg_wideband_arr_clk_export : out std_logic; -- export
- reg_wg_wideband_arr_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_wideband_arr_write_export : out std_logic; -- export
- reg_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_wideband_arr_read_export : out std_logic; -- export
- reg_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ddrctrl_ctrl_state_reset_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_clk_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ddrctrl_ctrl_state_write_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_ddrctrl_ctrl_state_read_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_lofar2_unb2c_ddrctrl;
+ component qsys_lofar2_unb2c_ddrctrl is
+ port (
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_bsn_buf_reset_export : out std_logic; -- export
+ ram_bsn_buf_clk_export : out std_logic; -- export
+ ram_bsn_buf_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bsn_buf_write_export : out std_logic; -- export
+ ram_bsn_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_bsn_buf_read_export : out std_logic; -- export
+ ram_bsn_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_data_buf_reset_export : out std_logic; -- export
+ ram_data_buf_clk_export : out std_logic; -- export
+ ram_data_buf_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_data_buf_write_export : out std_logic; -- export
+ ram_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_data_buf_read_export : out std_logic; -- export
+ ram_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_wideband_arr_reset_export : out std_logic; -- export
+ ram_wg_wideband_arr_clk_export : out std_logic; -- export
+ ram_wg_wideband_arr_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_wideband_arr_write_export : out std_logic; -- export
+ ram_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_wideband_arr_read_export : out std_logic; -- export
+ ram_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_v2_reset_export : out std_logic; -- export
+ reg_bsn_source_v2_clk_export : out std_logic; -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_v2_write_export : out std_logic; -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_v2_read_export : out std_logic; -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stop_in_reset_export : out std_logic; -- export
+ reg_stop_in_clk_export : out std_logic; -- export
+ reg_stop_in_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stop_in_write_export : out std_logic; -- export
+ reg_stop_in_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stop_in_read_export : out std_logic; -- export
+ reg_stop_in_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_reset_export : out std_logic; -- export
+ reg_io_ddr_clk_export : out std_logic; -- export
+ reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_io_ddr_write_export : out std_logic; -- export
+ reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_read_export : out std_logic; -- export
+ reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_wideband_arr_reset_export : out std_logic; -- export
+ reg_wg_wideband_arr_clk_export : out std_logic; -- export
+ reg_wg_wideband_arr_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_wideband_arr_write_export : out std_logic; -- export
+ reg_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_wideband_arr_read_export : out std_logic; -- export
+ reg_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ddrctrl_ctrl_state_reset_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_clk_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_ddrctrl_ctrl_state_write_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_writedata_export: out std_logic_vector(31 downto 0); -- export
+ reg_ddrctrl_ctrl_state_read_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_lofar2_unb2c_ddrctrl;
end qsys_lofar2_unb2c_ddrctrl_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
index e8ebe5092f..9bc349a605 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_filterbank_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_filterbank_full is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2c_filterbank_full is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2c)
+ -- back transceivers (note only 6 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b - 1 downto c_unb2c_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_filterbank_lib.lofar2_unb2c_filterbank
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
index 82942a08d3..07e233688a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_filterbank_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_filterbank_full_256MHz is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2c_filterbank_full_256MHz is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2c)
+ -- back transceivers (note only 6 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b - 1 downto c_unb2c_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_filterbank_lib.lofar2_unb2c_filterbank
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
index a8ae459ab2..8049a33ec9 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
@@ -27,17 +27,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2c_filterbank_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2c_filterbank_pkg.all;
entity lofar2_unb2c_filterbank is
generic (
@@ -85,9 +85,9 @@ entity lofar2_unb2c_filterbank is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -259,221 +259,221 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2c_filterbank
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
+ ram_equalizer_gains_miso => ram_equalizer_gains_miso,
+ reg_dp_selector_mosi => reg_dp_selector_mosi,
+ reg_dp_selector_miso => reg_dp_selector_miso,
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
-----------------------------------------------------------------------------
-- node_adc_input_and_timing (AIT)
@@ -481,82 +481,82 @@ begin
-----------------------------------------------------------------------------
u_ait: entity lofar2_sdp_lib.node_adc_input_and_timing
- generic map(
- g_nof_streams => c_sdp_S_pn,
- g_buf_nof_data => c_sdp_ait_buf_nof_data_bsn,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => ait_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_sdp_S_pn,
+ g_buf_nof_data => c_sdp_ait_buf_nof_data_bsn,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => ait_sosi_arr
+ );
u_fsub : entity lofar2_sdp_lib.node_sdp_filterbank
- generic map(
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso
- );
+ generic map(
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
index 617e401bec..9510b4a8ec 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
@@ -20,13 +20,13 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
package lofar2_unb2c_filterbank_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
index fa4e12bb7e..476a44ff19 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2c_filterbank_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2c_filterbank_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2c_filterbank is
generic (
@@ -154,13 +154,13 @@ entity mmm_lofar2_unb2c_filterbank is
reg_si_mosi : out t_mem_mosi;
reg_si_miso : in t_mem_miso;
- -- Equalizer gains
- ram_equalizer_gains_mosi : out t_mem_mosi;
- ram_equalizer_gains_miso : in t_mem_miso;
+ -- Equalizer gains
+ ram_equalizer_gains_mosi : out t_mem_mosi;
+ ram_equalizer_gains_miso : in t_mem_miso;
- -- DP Selector
- reg_dp_selector_mosi : out t_mem_mosi;
- reg_dp_selector_miso : in t_mem_miso;
+ -- DP Selector
+ reg_dp_selector_mosi : out t_mem_mosi;
+ reg_dp_selector_miso : in t_mem_miso;
-- Scrap ram
ram_scrap_mosi : out t_mem_mosi;
@@ -178,86 +178,114 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
-
- u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
-
- u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
-
- u_mm_file_reg_bsn_source : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
- port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
-
- u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
-
- u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
-
- u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
- u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
-
- u_mm_file_ram_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
- u_mm_file_reg_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
-
- u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
- u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
-
- u_mm_file_ram_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
- port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
- u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
-
- u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
-
- u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
-
- u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
-
- u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
-
- u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
-
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_jesd204b : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
+ port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+
+ u_mm_file_reg_dp_shiftram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
+ port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+
+ u_mm_file_reg_bsn_source : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
+ port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+
+ u_mm_file_reg_bsn_scheduler : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+
+ u_mm_file_reg_bsn_monitor_input : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+
+ u_mm_file_reg_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
+ port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
+ u_mm_file_ram_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
+ port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+
+ u_mm_file_ram_diag_data_buf_jesd : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
+ u_mm_file_reg_diag_data_buf_jesd : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
+
+ u_mm_file_ram_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
+ u_mm_file_reg_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+
+ u_mm_file_ram_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
+ u_mm_file_reg_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+
+ u_mm_file_ram_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
+ port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
+
+ u_mm_file_ram_fil_coefs : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
+ port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
+
+ u_mm_file_reg_si : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
+ port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
+
+ u_mm_file_ram_equalizer_gains : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
+ port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
+
+ u_mm_file_reg_dp_selector : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
+ port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
+
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -333,9 +361,9 @@ begin
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
+ -- ToDo: This has changed in the peripherals package
rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ -- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -351,9 +379,9 @@ begin
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
+ -- ToDo: This has changed in the peripherals package
pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
--- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ -- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
index 3193b1a4e8..d9eccde95d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
@@ -19,268 +19,268 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_filterbank_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2c_filterbank is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buf_bsn_read_export : out std_logic; -- export
- ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buf_bsn_write_export : out std_logic; -- export
- ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buf_bsn_read_export : out std_logic; -- export
- reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buf_bsn_write_export : out std_logic; -- export
- reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2c_filterbank;
+ component qsys_lofar2_unb2c_filterbank is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_aduh_monitor_clk_export : out std_logic; -- export
+ ram_aduh_monitor_read_export : out std_logic; -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_aduh_monitor_reset_export : out std_logic; -- export
+ ram_aduh_monitor_write_export : out std_logic; -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2c_filterbank;
end qsys_lofar2_unb2c_filterbank_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
index 896329e2ff..b52458675f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete ring design with all 8 lanes.
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_ring_full is
generic (
@@ -85,48 +85,48 @@ end lofar2_unb2c_ring_full;
architecture str of lofar2_unb2c_ring_full is
begin
u_revision : entity lofar2_unb2c_ring_lib.lofar2_unb2c_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
index 17830917aa..c45c1b0536 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
@@ -28,12 +28,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2c_board_lib, i2c_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2c_ring_full is
end tb_lofar2_unb2c_ring_full;
@@ -94,45 +94,45 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_ring_full : entity work.lofar2_unb2c_ring_full
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX,
- QSFP_0_TX => i_QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX,
- RING_0_TX => i_RING_0_TX,
- RING_1_RX => i_RING_1_RX,
- RING_1_TX => i_RING_1_TX,
-
- -- LEDs
- QSFP_LED => open
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX,
+ QSFP_0_TX => i_QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX,
+ RING_0_TX => i_RING_0_TX,
+ RING_1_RX => i_RING_1_RX,
+ RING_1_TX => i_RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => open
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
index 991fdeb922..3284ffa9db 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
@@ -29,13 +29,13 @@
-- However only 1 ring_lane.vhd component is instantiated with lane index 0 (even).
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_ring_one is
generic (
@@ -88,48 +88,48 @@ end lofar2_unb2c_ring_one;
architecture str of lofar2_unb2c_ring_one is
begin
u_revision : entity lofar2_unb2c_ring_lib.lofar2_unb2c_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
index 0aff49975a..4df91bd715 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
@@ -28,12 +28,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2c_board_lib, i2c_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2c_ring_one is
end tb_lofar2_unb2c_ring_one;
@@ -94,45 +94,45 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_ring_one : entity work.lofar2_unb2c_ring_one
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX,
- QSFP_0_TX => i_QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX,
- RING_0_TX => i_RING_0_TX,
- RING_1_RX => i_RING_1_RX,
- RING_1_TX => i_RING_1_TX,
-
- -- LEDs
- QSFP_LED => open
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX,
+ QSFP_0_TX => i_QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX,
+ RING_0_TX => i_RING_0_TX,
+ RING_1_RX => i_RING_1_RX,
+ RING_1_TX => i_RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => open
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
index 44d0371592..b1e8e51574 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
@@ -27,21 +27,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, tr_10gbe_lib, eth_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2c_ring_pkg.all;
-use eth_lib.eth_pkg.all;
-use ring_lib.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2c_ring_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use ring_lib.ring_pkg.all;
entity lofar2_unb2c_ring is
generic (
@@ -102,7 +102,7 @@ architecture str of lofar2_unb2c_ring is
constant c_mm_clk_freq : natural := c_unb2c_board_mm_clk_freq_100M;
constant c_lofar2_sample_clk_freq : natural := c_sdp_N_clk_per_sync; -- fixed 200 MHz for LOFAR2.0 stage 1
- -- QSFP
+ -- QSFP
constant c_nof_qsfp_bus : natural := 1;
constant c_nof_streams_qsfp : natural := c_unb2c_board_tr_qsfp.bus_w * c_nof_qsfp_bus; -- 4
@@ -141,11 +141,12 @@ architecture str of lofar2_unb2c_ring is
constant c_addr_w_reg_dp_block_validate_err : natural := ceil_log2(c_nof_err_counts + 3);
constant c_addr_w_reg_dp_block_validate_bsn_at_sync : natural := ceil_log2(3);
- constant c_reg_ring_input_select : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_lanes),
- dat_w => 1,
- nof_dat => c_nof_lanes,
- init_sl => '0'); -- default use lane input = 0, 1 = local input.
+ constant c_reg_ring_input_select : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_lanes),
+ dat_w => 1,
+ nof_dat => c_nof_lanes,
+ init_sl => '0'); -- default use lane input = 0, 1 = local input.
signal gn_index : natural;
signal this_rn : std_logic_vector(c_byte_w - 1 downto 0);
@@ -327,300 +328,300 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_unb2c_board_ext_clk_freq_200M,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_copi,
- reg_remu_miso => reg_remu_cipo,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_copi,
- reg_dpmm_data_miso => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_copi,
- reg_mmdp_data_miso => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_copi,
- reg_epcs_miso => reg_epcs_cipo,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_copi,
- reg_wdi_miso => reg_wdi_cipo,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_copi,
- reg_unb_system_info_miso => reg_unb_system_info_cipo,
- rom_unb_system_info_mosi => rom_unb_system_info_copi,
- rom_unb_system_info_miso => rom_unb_system_info_cipo,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_copi,
- reg_ppsh_miso => reg_ppsh_cipo,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_copi,
- eth1g_tse_miso => eth1g_tse_cipo,
- eth1g_reg_mosi => eth1g_reg_copi,
- eth1g_reg_miso => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_copi,
- eth1g_ram_miso => eth1g_ram_cipo,
-
- ram_scrap_mosi => ram_scrap_copi,
- ram_scrap_miso => ram_scrap_cipo,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK(0),
- ETH_SGIN => ETH_SGIN(0),
- ETH_SGOUT => ETH_SGOUT(0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_unb2c_board_ext_clk_freq_200M,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
+
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK(0),
+ ETH_SGIN => ETH_SGIN(0),
+ ETH_SGOUT => ETH_SGOUT(0)
+ );
-----------------------------------------------------------------------------
-- MM controller
-----------------------------------------------------------------------------
u_mmc : entity work.mmc_lofar2_unb2c_ring
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_copi => reg_wdi_copi,
- reg_wdi_cipo => reg_wdi_cipo,
- reg_unb_system_info_copi => reg_unb_system_info_copi,
- reg_unb_system_info_cipo => reg_unb_system_info_cipo,
- rom_unb_system_info_copi => rom_unb_system_info_copi,
- rom_unb_system_info_cipo => rom_unb_system_info_cipo,
- reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
- reg_ppsh_copi => reg_ppsh_copi,
- reg_ppsh_cipo => reg_ppsh_cipo,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_copi => eth1g_tse_copi,
- eth1g_tse_cipo => eth1g_tse_cipo,
- eth1g_reg_copi => eth1g_reg_copi,
- eth1g_reg_cipo => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_copi => eth1g_ram_copi,
- eth1g_ram_cipo => eth1g_ram_cipo,
- reg_dpmm_data_copi => reg_dpmm_data_copi,
- reg_dpmm_data_cipo => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
- reg_mmdp_data_copi => reg_mmdp_data_copi,
- reg_mmdp_data_cipo => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
- reg_epcs_copi => reg_epcs_copi,
- reg_epcs_cipo => reg_epcs_cipo,
- reg_remu_copi => reg_remu_copi,
- reg_remu_cipo => reg_remu_cipo,
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi,
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo,
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi,
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo,
- reg_diag_bg_copi => reg_diag_bg_copi,
- reg_diag_bg_cipo => reg_diag_bg_cipo,
- ram_diag_bg_copi => ram_diag_bg_copi,
- ram_diag_bg_cipo => ram_diag_bg_cipo,
- reg_ring_lane_info_copi => reg_ring_lane_info_copi,
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo,
- reg_dp_xonoff_lane_copi => reg_dp_xonoff_lane_copi,
- reg_dp_xonoff_lane_cipo => reg_dp_xonoff_lane_cipo,
- reg_dp_xonoff_local_copi => reg_dp_xonoff_local_copi,
- reg_dp_xonoff_local_cipo => reg_dp_xonoff_local_cipo,
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo,
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_scrap_copi => ram_scrap_copi,
- ram_scrap_cipo => ram_scrap_cipo
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi,
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo,
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi,
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo,
+ reg_diag_bg_copi => reg_diag_bg_copi,
+ reg_diag_bg_cipo => reg_diag_bg_cipo,
+ ram_diag_bg_copi => ram_diag_bg_copi,
+ ram_diag_bg_cipo => ram_diag_bg_cipo,
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi,
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo,
+ reg_dp_xonoff_lane_copi => reg_dp_xonoff_lane_copi,
+ reg_dp_xonoff_lane_cipo => reg_dp_xonoff_lane_cipo,
+ reg_dp_xonoff_local_copi => reg_dp_xonoff_local_copi,
+ reg_dp_xonoff_local_cipo => reg_dp_xonoff_local_cipo,
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo,
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo
+ );
-----------------------------------------------------------------------------
-- MM Mux
-----------------------------------------------------------------------------
u_mem_mux_ring_lane_info : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_ring_lane_info
- )
- port map (
- mosi => reg_ring_lane_info_copi,
- miso => reg_ring_lane_info_cipo,
- mosi_arr => reg_ring_lane_info_copi_arr,
- miso_arr => reg_ring_lane_info_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_ring_lane_info
+ )
+ port map (
+ mosi => reg_ring_lane_info_copi,
+ miso => reg_ring_lane_info_cipo,
+ mosi_arr => reg_ring_lane_info_copi_arr,
+ miso_arr => reg_ring_lane_info_cipo_arr
+ );
u_mem_mux_bsn_monitor_v2_ring_rx : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_rx_copi,
- miso => reg_bsn_monitor_v2_ring_rx_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_rx_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_rx_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_rx_copi,
+ miso => reg_bsn_monitor_v2_ring_rx_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_rx_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_rx_cipo_arr
+ );
u_mem_mux_bsn_monitor_v2_ring_tx : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_tx_copi,
- miso => reg_bsn_monitor_v2_ring_tx_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_tx_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_tx_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_tx_copi,
+ miso => reg_bsn_monitor_v2_ring_tx_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_tx_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_tx_cipo_arr
+ );
u_mem_mux_dp_block_validate_err : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_dp_block_validate_err
- )
- port map (
- mosi => reg_dp_block_validate_err_copi,
- miso => reg_dp_block_validate_err_cipo,
- mosi_arr => reg_dp_block_validate_err_copi_arr,
- miso_arr => reg_dp_block_validate_err_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_dp_block_validate_err
+ )
+ port map (
+ mosi => reg_dp_block_validate_err_copi,
+ miso => reg_dp_block_validate_err_cipo,
+ mosi_arr => reg_dp_block_validate_err_copi_arr,
+ miso_arr => reg_dp_block_validate_err_cipo_arr
+ );
u_mem_mux_dp_block_validate_bsn_at_sync : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_dp_block_validate_bsn_at_sync
- )
- port map (
- mosi => reg_dp_block_validate_bsn_at_sync_copi,
- miso => reg_dp_block_validate_bsn_at_sync_cipo,
- mosi_arr => reg_dp_block_validate_bsn_at_sync_copi_arr,
- miso_arr => reg_dp_block_validate_bsn_at_sync_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_dp_block_validate_bsn_at_sync
+ )
+ port map (
+ mosi => reg_dp_block_validate_bsn_at_sync_copi,
+ miso => reg_dp_block_validate_bsn_at_sync_cipo,
+ mosi_arr => reg_dp_block_validate_bsn_at_sync_copi_arr,
+ miso_arr => reg_dp_block_validate_bsn_at_sync_cipo_arr
+ );
-----------------------------------------------------------------------------
-- MMP diag_block_gen
-----------------------------------------------------------------------------
u_mmp_diag_block_gen : entity diag_lib.mms_diag_block_gen
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
-
- reg_bg_ctrl_mosi => reg_diag_bg_copi,
- reg_bg_ctrl_miso => reg_diag_bg_cipo,
- ram_bg_data_mosi => ram_diag_bg_copi,
- ram_bg_data_miso => ram_diag_bg_cipo,
-
- out_sosi_arr(0) => local_sosi
- );
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_copi,
+ reg_bg_ctrl_miso => reg_diag_bg_cipo,
+ ram_bg_data_mosi => ram_diag_bg_copi,
+ ram_bg_data_miso => ram_diag_bg_cipo,
+
+ out_sosi_arr(0) => local_sosi
+ );
bs_sosi <= local_sosi;
-----------------------------------------------------------------------------
-- MMP dp_xonoff from_lane_sosi
-----------------------------------------------------------------------------
u_mmp_dp_xonoff_lane : entity dp_lib.mms_dp_xonoff
- generic map (
- g_nof_streams => c_nof_lanes,
- g_default_value => '1' -- default enabled, because standard behaviour is to only pass on packets from lane.
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => c_nof_lanes,
+ g_default_value => '1' -- default enabled, because standard behaviour is to only pass on packets from lane.
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_dp_xonoff_lane_copi,
- reg_miso => reg_dp_xonoff_lane_cipo,
+ reg_mosi => reg_dp_xonoff_lane_copi,
+ reg_miso => reg_dp_xonoff_lane_cipo,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- snk_out_arr => OPEN,
- snk_in_arr => from_lane_sosi_arr,
+ snk_out_arr => OPEN,
+ snk_in_arr => from_lane_sosi_arr,
- src_in_arr => dp_xonoff_lane_src_in_arr,
- src_out_arr => dp_xonoff_lane_src_out_arr
- );
+ src_in_arr => dp_xonoff_lane_src_in_arr,
+ src_out_arr => dp_xonoff_lane_src_out_arr
+ );
-----------------------------------------------------------------------------
-- MMP dp_xonoff local_sosi
@@ -630,26 +631,26 @@ begin
end generate;
u_mmp_dp_xonoff_local : entity dp_lib.mms_dp_xonoff
- generic map (
- g_nof_streams => c_nof_lanes,
- g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => c_nof_lanes,
+ g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_dp_xonoff_local_copi,
- reg_miso => reg_dp_xonoff_local_cipo,
+ reg_mosi => reg_dp_xonoff_local_copi,
+ reg_miso => reg_dp_xonoff_local_cipo,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- snk_out_arr => OPEN,
- snk_in_arr => dp_xonoff_local_snk_in_arr,
+ snk_out_arr => OPEN,
+ snk_in_arr => dp_xonoff_local_snk_in_arr,
- src_in_arr => dp_xonoff_local_src_in_arr,
- src_out_arr => dp_xonoff_local_src_out_arr
- );
+ src_in_arr => dp_xonoff_local_src_in_arr,
+ src_out_arr => dp_xonoff_local_src_out_arr
+ );
-----------------------------------------------------------------------------
-- DP Mux
@@ -661,49 +662,49 @@ begin
dp_mux_snk_in_2arr(I)(1) <= dp_xonoff_local_src_out_arr(I);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_append_channel_lo => false,
- g_sel_ctrl_invert => true,
- g_use_fifo => true,
- g_bsn_w => c_longword_w,
- g_data_w => c_lane_data_w,
- g_in_channel_w => c_byte_w,
- g_error_w => c_nof_err_counts,
- g_use_bsn => true,
- g_use_in_channel => true,
- g_use_error => true,
- g_use_sync => true,
- -- Using fifo size of 2 * packet length for both inputs of the mux as a packet might arrive on both the local and remote input.
- g_fifo_size => array_init(2 * c_lane_packet_length, 2)
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_mux_snk_out_2arr(I),
- snk_in_arr => dp_mux_snk_in_2arr(I),
-
- src_in => c_dp_siso_rdy,
- src_out => to_lane_sosi_arr(I)
- );
+ generic map (
+ g_append_channel_lo => false,
+ g_sel_ctrl_invert => true,
+ g_use_fifo => true,
+ g_bsn_w => c_longword_w,
+ g_data_w => c_lane_data_w,
+ g_in_channel_w => c_byte_w,
+ g_error_w => c_nof_err_counts,
+ g_use_bsn => true,
+ g_use_in_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ -- Using fifo size of 2 * packet length for both inputs of the mux as a packet might arrive on both the local and remote input.
+ g_fifo_size => array_init(2 * c_lane_packet_length, 2)
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_mux_snk_out_2arr(I),
+ snk_in_arr => dp_mux_snk_in_2arr(I),
+
+ src_in => c_dp_siso_rdy,
+ src_out => to_lane_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
-- Ring info
-----------------------------------------------------------------------------
u_ring_info : entity ring_lib.ring_info
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_copi => reg_ring_info_copi,
- reg_cipo => reg_ring_info_cipo,
+ reg_copi => reg_ring_info_copi,
+ reg_cipo => reg_ring_info_cipo,
- ring_info => ring_info
- );
+ ring_info => ring_info
+ );
-- Use full c_byte_w range of ID for gn_index and ring_info.O_rn
gn_index <= TO_UINT(ID);
@@ -714,50 +715,50 @@ begin
-----------------------------------------------------------------------------
gen_even_lanes: for I in 0 to c_nof_even_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 1, -- transport in positive direction.
- g_lane_data_w => c_lane_data_w,
- g_lane_packet_length => c_lane_packet_length,
- g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_nof_rx_monitors,
- g_nof_tx_monitors => c_nof_tx_monitors,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => from_lane_sosi_arr(2 * I), -- even indices
- to_lane_sosi => to_lane_sosi_arr(2 * I),
- lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I),
- lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I),
- lane_tx_cable_sosi => lane_tx_cable_even_sosi_arr(I),
- lane_tx_board_sosi => lane_tx_board_even_sosi_arr(I),
- bs_sosi => bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I),
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I),
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_previous_rn,
- tx_select => ring_info.use_cable_to_next_rn
- );
+ generic map (
+ g_lane_direction => 1, -- transport in positive direction.
+ g_lane_data_w => c_lane_data_w,
+ g_lane_packet_length => c_lane_packet_length,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_nof_rx_monitors,
+ g_nof_tx_monitors => c_nof_tx_monitors,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => from_lane_sosi_arr(2 * I), -- even indices
+ to_lane_sosi => to_lane_sosi_arr(2 * I),
+ lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I),
+ lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I),
+ lane_tx_cable_sosi => lane_tx_cable_even_sosi_arr(I),
+ lane_tx_board_sosi => lane_tx_board_even_sosi_arr(I),
+ bs_sosi => bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_previous_rn,
+ tx_select => ring_info.use_cable_to_next_rn
+ );
end generate;
-----------------------------------------------------------------------------
@@ -765,50 +766,50 @@ begin
-----------------------------------------------------------------------------
gen_odd_lanes : for I in 0 to c_nof_odd_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 0, -- transport in negative direction.
- g_lane_data_w => c_lane_data_w,
- g_lane_packet_length => c_lane_packet_length,
- g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_nof_rx_monitors,
- g_nof_tx_monitors => c_nof_tx_monitors,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => from_lane_sosi_arr(2 * I + 1), -- odd indices
- to_lane_sosi => to_lane_sosi_arr(2 * I + 1),
- lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I),
- lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I),
- lane_tx_cable_sosi => lane_tx_cable_odd_sosi_arr(I),
- lane_tx_board_sosi => lane_tx_board_odd_sosi_arr(I),
- bs_sosi => bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I + 1),
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I + 1),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I + 1),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I + 1),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I + 1),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I + 1),
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
- tx_select => ring_info.use_cable_to_previous_rn
- );
+ generic map (
+ g_lane_direction => 0, -- transport in negative direction.
+ g_lane_data_w => c_lane_data_w,
+ g_lane_packet_length => c_lane_packet_length,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_nof_rx_monitors,
+ g_nof_tx_monitors => c_nof_tx_monitors,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => from_lane_sosi_arr(2 * I + 1), -- odd indices
+ to_lane_sosi => to_lane_sosi_arr(2 * I + 1),
+ lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I),
+ lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I),
+ lane_tx_cable_sosi => lane_tx_cable_odd_sosi_arr(I),
+ lane_tx_board_sosi => lane_tx_board_odd_sosi_arr(I),
+ bs_sosi => bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I + 1),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I + 1),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I + 1),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I + 1),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I + 1),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I + 1),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
+ tx_select => ring_info.use_cable_to_previous_rn
+ );
end generate;
-----------------------------------------------------------------------------
@@ -837,45 +838,45 @@ begin
-- tr_10GbE
-----------------------------------------------------------------------------
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_mac,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill,
- g_tx_fifo_size => c_fifo_tx_size
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mac_copi,
- reg_mac_miso => reg_tr_10GbE_mac_cipo,
-
- reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
- reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => tr_10gbe_src_out_arr,
- src_in_arr => tr_10gbe_src_in_arr,
-
- snk_out_arr => tr_10gbe_snk_out_arr,
- snk_in_arr => tr_10gbe_snk_in_arr,
-
- -- Serial IO
- serial_tx_arr => tr_10gbe_serial_tx_arr,
- serial_rx_arr => tr_10gbe_serial_rx_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_mac,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill,
+ g_tx_fifo_size => c_fifo_tx_size
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mac_copi,
+ reg_mac_miso => reg_tr_10GbE_mac_cipo,
+
+ reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => tr_10gbe_src_out_arr,
+ src_in_arr => tr_10gbe_src_in_arr,
+
+ snk_out_arr => tr_10gbe_snk_out_arr,
+ snk_in_arr => tr_10gbe_snk_in_arr,
+
+ -- Serial IO
+ serial_tx_arr => tr_10gbe_serial_tx_arr,
+ serial_rx_arr => tr_10gbe_serial_rx_arr
+ );
-----------------------------------------------------------------------------
-- Seperate serial tx/rx array
@@ -903,14 +904,14 @@ begin
-- PLL
---------
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
------------
-- Front IO
@@ -920,21 +921,21 @@ begin
QSFP_0_TX <= i_QSFP_TX(0);
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
------------
-- RING IO
@@ -949,18 +950,18 @@ begin
------------
unb2_board_qsfp_leds_tx_siso_arr(0) <= tr_10gbe_snk_out_arr(0);
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
-
- tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+
+ tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
index 28a9c8341d..7061a4a105 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
@@ -20,13 +20,13 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
package lofar2_unb2c_ring_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
index 42f7512e38..5ea22afea2 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2c_ring_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2c_ring_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmc_lofar2_unb2c_ring is
generic (
@@ -153,65 +153,85 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
-
- u_mm_file_reg_dp_block_validate_err : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_copi, reg_dp_block_validate_err_cipo );
-
- u_mm_file_reg_dp_block_validate_bsn_at_sync : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_copi, reg_dp_block_validate_bsn_at_sync_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_ring_rx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_copi, reg_bsn_monitor_v2_ring_rx_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_ring_tx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_copi, reg_bsn_monitor_v2_ring_tx_cipo );
-
- u_mm_file_reg_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_copi, reg_diag_bg_cipo );
- u_mm_file_ram_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_copi, ram_diag_bg_cipo );
-
- u_mm_file_reg_ring_lane_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO")
- port map(mm_rst, mm_clk, reg_ring_lane_info_copi, reg_ring_lane_info_cipo );
-
- u_mm_file_reg_dp_xonoff_lane : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LANE")
- port map(mm_rst, mm_clk, reg_dp_xonoff_lane_copi, reg_dp_xonoff_lane_cipo );
-
- u_mm_file_reg_dp_xonoff_local : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LOCAL")
- port map(mm_rst, mm_clk, reg_dp_xonoff_local_copi, reg_dp_xonoff_local_cipo );
-
- u_mm_file_reg_ring_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
- port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo);
-
- u_mm_file_reg_tr_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
-
- u_mm_file_reg_tr_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
-
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
+
+ u_mm_file_reg_dp_block_validate_err : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_copi, reg_dp_block_validate_err_cipo );
+
+ u_mm_file_reg_dp_block_validate_bsn_at_sync : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_copi, reg_dp_block_validate_bsn_at_sync_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_ring_rx : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_copi, reg_bsn_monitor_v2_ring_rx_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_ring_tx : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_copi, reg_bsn_monitor_v2_ring_tx_cipo );
+
+ u_mm_file_reg_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_copi, reg_diag_bg_cipo );
+ u_mm_file_ram_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_copi, ram_diag_bg_cipo );
+
+ u_mm_file_reg_ring_lane_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO")
+ port map(mm_rst, mm_clk, reg_ring_lane_info_copi, reg_ring_lane_info_cipo );
+
+ u_mm_file_reg_dp_xonoff_lane : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LANE")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_lane_copi, reg_dp_xonoff_lane_cipo );
+
+ u_mm_file_reg_dp_xonoff_local : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LOCAL")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_local_copi, reg_dp_xonoff_local_cipo );
+
+ u_mm_file_reg_ring_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
+ port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo);
+
+ u_mm_file_reg_tr_10GbE_mac : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
+
+ u_mm_file_reg_tr_10GbE_eth10g : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
+
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
index 8c35d482f2..8ece4db3a7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
@@ -19,213 +19,213 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_ring_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2c_ring is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export
- ram_diag_bg_clk_export : out std_logic; -- export
- ram_diag_bg_read_export : out std_logic; -- export
- ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_reset_export : out std_logic; -- export
- ram_diag_bg_write_export : out std_logic; -- export
- ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_clk_export : out std_logic; -- export
- reg_diag_bg_read_export : out std_logic; -- export
- reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_reset_export : out std_logic; -- export
- reg_diag_bg_write_export : out std_logic; -- export
- reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export
- reg_dp_block_validate_err_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_read_export : out std_logic; -- export
- reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_write_export : out std_logic; -- export
- reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_lane_clk_export : out std_logic; -- export
- reg_dp_xonoff_lane_read_export : out std_logic; -- export
- reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_lane_reset_export : out std_logic; -- export
- reg_dp_xonoff_lane_write_export : out std_logic; -- export
- reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_local_clk_export : out std_logic; -- export
- reg_dp_xonoff_local_read_export : out std_logic; -- export
- reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_local_reset_export : out std_logic; -- export
- reg_dp_xonoff_local_write_export : out std_logic; -- export
- reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_ring_lane_info_clk_export : out std_logic; -- export
- reg_ring_lane_info_read_export : out std_logic; -- export
- reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_reset_export : out std_logic; -- export
- reg_ring_lane_info_write_export : out std_logic; -- export
- reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2c_ring;
+ component qsys_lofar2_unb2c_ring is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export
+ ram_diag_bg_clk_export : out std_logic; -- export
+ ram_diag_bg_read_export : out std_logic; -- export
+ ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_reset_export : out std_logic; -- export
+ ram_diag_bg_write_export : out std_logic; -- export
+ ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_clk_export : out std_logic; -- export
+ reg_diag_bg_read_export : out std_logic; -- export
+ reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_reset_export : out std_logic; -- export
+ reg_diag_bg_write_export : out std_logic; -- export
+ reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_dp_block_validate_err_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_xonoff_lane_clk_export : out std_logic; -- export
+ reg_dp_xonoff_lane_read_export : out std_logic; -- export
+ reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_lane_reset_export : out std_logic; -- export
+ reg_dp_xonoff_lane_write_export : out std_logic; -- export
+ reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_xonoff_local_clk_export : out std_logic; -- export
+ reg_dp_xonoff_local_read_export : out std_logic; -- export
+ reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_local_reset_export : out std_logic; -- export
+ reg_dp_xonoff_local_write_export : out std_logic; -- export
+ reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_ring_lane_info_clk_export : out std_logic; -- export
+ reg_ring_lane_info_read_export : out std_logic; -- export
+ reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_reset_export : out std_logic; -- export
+ reg_ring_lane_info_write_export : out std_logic; -- export
+ reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2c_ring;
end qsys_lofar2_unb2c_ring_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
index 8d8576c59f..f0971b1986 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
@@ -29,9 +29,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_pkg.all;
entity tb_tb_lofar2_unb2c_ring is
end tb_tb_lofar2_unb2c_ring;
@@ -42,14 +42,14 @@ architecture tb of tb_tb_lofar2_unb2c_ring is
signal tb_end_vec : std_logic_vector(c_nof_tb - 1 downto 0) := (others => '0');
signal tb_end : std_logic; -- declare tb_end as STD_LOGIC to avoid 'No objects found' error on 'when -label tb_end' in *.do file
begin
--- g_multi_tb : BOOLEAN := FALSE;
--- g_unb_nr : NATURAL := 4;
--- g_design_name : STRING := "lofar2_unb2c_ring_one";
--- g_nof_rn : NATURAL := 16;
--- g_nof_block_per_sync : NATURAL := 32;
--- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
+ -- g_multi_tb : BOOLEAN := FALSE;
+ -- g_unb_nr : NATURAL := 4;
+ -- g_design_name : STRING := "lofar2_unb2c_ring_one";
+ -- g_nof_rn : NATURAL := 16;
+ -- g_nof_block_per_sync : NATURAL := 32;
+ -- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
--- using different g_unb_nr to avoid MM file clashing.
+ -- using different g_unb_nr to avoid MM file clashing.
u_one_1 : entity work.tb_lofar2_unb2c_ring generic map(true, 0, "lofar2_unb2c_ring_one", c_nof_rn, 3, 1) port map(tb_end_vec(0)); -- access scheme 1.
u_one_2_3 : entity work.tb_lofar2_unb2c_ring generic map(true, 1, "lofar2_unb2c_ring_one", c_nof_rn, 3, 2) port map(tb_end_vec(1)); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
u_full_1 : entity work.tb_lofar2_unb2c_ring generic map(true, 2, "lofar2_unb2c_ring_full", c_nof_rn, 3, 1) port map(tb_end_vec(2)); -- access scheme 1.
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
index 0a7c377d0a..1aa3b6d07d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity disturb2_unb2c_sdp_station_full is
generic (
@@ -82,7 +82,7 @@ entity disturb2_unb2c_sdp_station_full is
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -103,59 +103,59 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
index 0bd6efeaed..90bb3bb17c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
@@ -26,13 +26,13 @@
-- Contains AIT input stage with WG, FSUB, XSUB, BF and RING, so without ADC JESD.
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity disturb2_unb2c_sdp_station_full_wg is
generic (
@@ -87,51 +87,51 @@ end disturb2_unb2c_sdp_station_full_wg;
architecture str of disturb2_unb2c_sdp_station_full_wg is
begin
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
index cde951b9a5..e6af7c560b 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_adc is
generic (
@@ -66,7 +66,7 @@ entity lofar2_unb2c_sdp_station_adc is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -87,43 +87,43 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- LEDs
- QSFP_LED => QSFP_LED,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
index 9abb13ac1d..04c11f9020 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_bf is
generic (
@@ -73,7 +73,7 @@ entity lofar2_unb2c_sdp_station_bf is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -94,50 +94,50 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
index b85519e4bd..34079fe34f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_tb_lofar2_unb2c_sdp_station_bf is
end tb_tb_lofar2_unb2c_sdp_station_bf;
@@ -37,24 +37,24 @@ architecture tb of tb_tb_lofar2_unb2c_sdp_station_bf is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
u_bf : entity work.tb_lofar2_unb2c_sdp_station_bf
- generic map (
- g_sp => 3, -- WG signal path (SP) index in range(S_pn = 12)
- g_sp_ampl => 0.5, -- WG normalized amplitude
- g_sp_phase => -110.0, -- WG phase in degrees = subband phase
- g_sp_remnant_ampl => 0.1, -- WG normalized amplitude for remnant sp
- g_sp_remnant_phase => 15.0, -- WG phase in degrees for remnant sp
- g_subband => 102, -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- g_beamlet => c_sdp_S_sub_bf - 1, -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
- g_beamlet_scale => 1.0 / 2.0**9, -- g_beamlet output scale factor
- g_bf_x_gain => 0.7, -- g_beamlet X BF weight normalized gain for g_sp
- g_bf_y_gain => 0.6, -- g_beamlet Y BF weight normalized gain for g_sp
- g_bf_x_phase => 30.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
- g_bf_y_phase => 40.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
- g_bf_remnant_x_gain => 0.05, -- g_beamlet X BF weight normalized gain for remnant sp
- g_bf_remnant_y_gain => 0.04, -- g_beamlet Y BF weight normalized gain for remnant sp
- g_bf_remnant_x_phase => 170.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
- g_bf_remnant_y_phase => -135.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
- g_read_all_SST => false, -- when FALSE only read SST for g_subband, to save sim time
- g_read_all_BST => false -- when FALSE only read BST for g_beamlet, to save sim time
- );
+ generic map (
+ g_sp => 3, -- WG signal path (SP) index in range(S_pn = 12)
+ g_sp_ampl => 0.5, -- WG normalized amplitude
+ g_sp_phase => -110.0, -- WG phase in degrees = subband phase
+ g_sp_remnant_ampl => 0.1, -- WG normalized amplitude for remnant sp
+ g_sp_remnant_phase => 15.0, -- WG phase in degrees for remnant sp
+ g_subband => 102, -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_beamlet => c_sdp_S_sub_bf - 1, -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
+ g_beamlet_scale => 1.0 / 2.0**9, -- g_beamlet output scale factor
+ g_bf_x_gain => 0.7, -- g_beamlet X BF weight normalized gain for g_sp
+ g_bf_y_gain => 0.6, -- g_beamlet Y BF weight normalized gain for g_sp
+ g_bf_x_phase => 30.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_y_phase => 40.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_bf_remnant_x_gain => 0.05, -- g_beamlet X BF weight normalized gain for remnant sp
+ g_bf_remnant_y_gain => 0.04, -- g_beamlet Y BF weight normalized gain for remnant sp
+ g_bf_remnant_x_phase => 170.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_remnant_y_phase => -135.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_read_all_SST => false, -- when FALSE only read SST for g_subband, to save sim time
+ g_read_all_BST => false -- when FALSE only read BST for g_beamlet, to save sim time
+ );
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
index 2292509910..b48b46c7da 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_bf is
generic (
@@ -83,7 +83,7 @@ entity lofar2_unb2c_sdp_station_bf is
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -104,59 +104,59 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
index 10853a63ba..41819e2537 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_fsub is
generic (
@@ -66,7 +66,7 @@ entity lofar2_unb2c_sdp_station_fsub is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -87,43 +87,43 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- LEDs
- QSFP_LED => QSFP_LED,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
index 5ee8de3495..4f23552032 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_tb_lofar2_unb2c_sdp_station_fsub is
end tb_tb_lofar2_unb2c_sdp_station_fsub;
@@ -36,34 +36,34 @@ end tb_tb_lofar2_unb2c_sdp_station_fsub;
architecture tb of tb_tb_lofar2_unb2c_sdp_station_fsub is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- Commented to save sim time in regression test
--- u_fsub_only_co : ENTITY work.tb_lofar2_unb2c_sdp_station_fsub
--- GENERIC MAP (
--- g_sp => 3, -- signal path index in range(S_pn = 12) of co-polarization
--- g_co_wg_ampl => 0.5, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
--- g_cross_wg_ampl => 0.4, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
--- g_cross_wg_phase => 90.0, -- WG phase in degrees for cross-sp, relative to co-sp
--- g_subband => 102, -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
--- g_co_subband_weight_gain => 1.0, -- subband weight normalized gain, for co-polarization in g_sp
--- g_co_subband_weight_phase => 30.0, -- subband weight phase rotation in degrees, for co-polarization in g_sp
--- g_use_cross_weight => FALSE,
--- g_sp_cross_subband_weight_gain => 0.5, -- subband weight normalized gain, for cross polarization of g_sp
--- g_sp_cross_subband_weight_phase => -10.0, -- subband weight phase rotation in degrees, for cross polarization of g_sp
--- g_read_all_SST => TRUE -- when FALSE only read SST for g_subband, to save sim time
--- );
+ -- Commented to save sim time in regression test
+ -- u_fsub_only_co : ENTITY work.tb_lofar2_unb2c_sdp_station_fsub
+ -- GENERIC MAP (
+ -- g_sp => 3, -- signal path index in range(S_pn = 12) of co-polarization
+ -- g_co_wg_ampl => 0.5, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ -- g_cross_wg_ampl => 0.4, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ -- g_cross_wg_phase => 90.0, -- WG phase in degrees for cross-sp, relative to co-sp
+ -- g_subband => 102, -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ -- g_co_subband_weight_gain => 1.0, -- subband weight normalized gain, for co-polarization in g_sp
+ -- g_co_subband_weight_phase => 30.0, -- subband weight phase rotation in degrees, for co-polarization in g_sp
+ -- g_use_cross_weight => FALSE,
+ -- g_sp_cross_subband_weight_gain => 0.5, -- subband weight normalized gain, for cross polarization of g_sp
+ -- g_sp_cross_subband_weight_phase => -10.0, -- subband weight phase rotation in degrees, for cross polarization of g_sp
+ -- g_read_all_SST => TRUE -- when FALSE only read SST for g_subband, to save sim time
+ -- );
u_fsub_use_cross : entity work.tb_lofar2_unb2c_sdp_station_fsub
- generic map (
- g_sp => 3, -- signal path index in range(S_pn = 12) of co-polarization
- g_co_wg_ampl => 0.5, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
- g_cross_wg_ampl => 0.4, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
- g_cross_wg_phase => 90.0, -- WG phase in degrees for cross-sp, relative to co-sp
- g_subband => 102, -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- g_co_subband_weight_gain => 1.0, -- subband weight normalized gain, for co-polarization in g_sp
- g_co_subband_weight_phase => 30.0, -- subband weight phase rotation in degrees, for co-polarization in g_sp
- g_use_cross_weight => true,
- g_sp_cross_subband_weight_gain => 0.5, -- subband weight normalized gain, for cross polarization of g_sp
- g_sp_cross_subband_weight_phase => -10.0, -- subband weight phase rotation in degrees, for cross polarization of g_sp
- g_read_all_SST => true -- when FALSE only read SST for g_subband, to save sim time
- );
+ generic map (
+ g_sp => 3, -- signal path index in range(S_pn = 12) of co-polarization
+ g_co_wg_ampl => 0.5, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ g_cross_wg_ampl => 0.4, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ g_cross_wg_phase => 90.0, -- WG phase in degrees for cross-sp, relative to co-sp
+ g_subband => 102, -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_co_subband_weight_gain => 1.0, -- subband weight normalized gain, for co-polarization in g_sp
+ g_co_subband_weight_phase => 30.0, -- subband weight phase rotation in degrees, for co-polarization in g_sp
+ g_use_cross_weight => true,
+ g_sp_cross_subband_weight_gain => 0.5, -- subband weight normalized gain, for cross polarization of g_sp
+ g_sp_cross_subband_weight_phase => -10.0, -- subband weight phase rotation in degrees, for cross polarization of g_sp
+ g_read_all_SST => true -- when FALSE only read SST for g_subband, to save sim time
+ );
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
index f637461c32..c864334d9c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_full is
generic (
@@ -82,7 +82,7 @@ entity lofar2_unb2c_sdp_station_full is
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -103,59 +103,59 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
index 9e7d7250d9..f9cccf6220 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
@@ -26,13 +26,13 @@
-- Contains AIT input stage with WG, FSUB, XSUB, BF and RING, so without ADC JESD.
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_full_wg is
generic (
@@ -87,51 +87,51 @@ end lofar2_unb2c_sdp_station_full_wg;
architecture str of lofar2_unb2c_sdp_station_full_wg is
begin
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
index d210c368ad..3aa7432586 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and XSUB for XST from one node.
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_xsub_one is
generic (
@@ -66,7 +66,7 @@ entity lofar2_unb2c_sdp_station_xsub_one is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -87,43 +87,43 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- LEDs
- QSFP_LED => QSFP_LED,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
index 40b0196d31..4439251d76 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB, XSUB with ring.
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_xsub_ring is
generic (
@@ -82,7 +82,7 @@ entity lofar2_unb2c_sdp_station_xsub_ring is
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -103,59 +103,59 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index 0d4176a1f2..b346b91880 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -27,20 +27,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2c_sdp_station_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2c_sdp_station_pkg.all;
+ use eth_lib.eth_pkg.all;
entity lofar2_unb2c_sdp_station is
generic (
@@ -96,9 +96,9 @@ entity lofar2_unb2c_sdp_station is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0) := (others => '0'); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic := '0'; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -470,297 +470,297 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_unb2c_board_ext_clk_freq_200M,
- g_dp_clk_use_pll => false,
- g_udp_offload => true,
- g_udp_offload_nof_streams => c_eth_nof_udp_ports
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_copi,
- reg_remu_miso => reg_remu_cipo,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_copi,
- reg_dpmm_data_miso => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_copi,
- reg_mmdp_data_miso => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_copi,
- reg_epcs_miso => reg_epcs_cipo,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_copi,
- reg_wdi_miso => reg_wdi_cipo,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_copi,
- reg_unb_system_info_miso => reg_unb_system_info_cipo,
- rom_unb_system_info_mosi => rom_unb_system_info_copi,
- rom_unb_system_info_miso => rom_unb_system_info_cipo,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_copi,
- reg_ppsh_miso => reg_ppsh_cipo,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_copi,
- eth1g_tse_miso => eth1g_tse_cipo,
- eth1g_reg_mosi => eth1g_reg_copi,
- eth1g_reg_miso => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_copi,
- eth1g_ram_miso => eth1g_ram_cipo,
-
- -- eth1g UDP streaming
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- ram_scrap_mosi => ram_scrap_copi,
- ram_scrap_miso => ram_scrap_cipo,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK(0),
- ETH_SGIN => ETH_SGIN(0),
- ETH_SGOUT => ETH_SGOUT(0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_unb2c_board_ext_clk_freq_200M,
+ g_dp_clk_use_pll => false,
+ g_udp_offload => true,
+ g_udp_offload_nof_streams => c_eth_nof_udp_ports
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
+
+ -- eth1g UDP streaming
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK(0),
+ ETH_SGIN => ETH_SGIN(0),
+ ETH_SGOUT => ETH_SGOUT(0)
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2c_sdp_station
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_copi => reg_wdi_copi,
- reg_wdi_cipo => reg_wdi_cipo,
- reg_unb_system_info_copi => reg_unb_system_info_copi,
- reg_unb_system_info_cipo => reg_unb_system_info_cipo,
- rom_unb_system_info_copi => rom_unb_system_info_copi,
- rom_unb_system_info_cipo => rom_unb_system_info_cipo,
- reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
- reg_ppsh_copi => reg_ppsh_copi,
- reg_ppsh_cipo => reg_ppsh_cipo,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_copi => eth1g_tse_copi,
- eth1g_tse_cipo => eth1g_tse_cipo,
- eth1g_reg_copi => eth1g_reg_copi,
- eth1g_reg_cipo => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_copi => eth1g_ram_copi,
- eth1g_ram_cipo => eth1g_ram_cipo,
- reg_dpmm_data_copi => reg_dpmm_data_copi,
- reg_dpmm_data_cipo => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
- reg_mmdp_data_copi => reg_mmdp_data_copi,
- reg_mmdp_data_cipo => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
- reg_epcs_copi => reg_epcs_copi,
- reg_epcs_cipo => reg_epcs_cipo,
- reg_remu_copi => reg_remu_copi,
- reg_remu_cipo => reg_remu_cipo,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_copi => jesd204b_copi,
- jesd204b_cipo => jesd204b_cipo,
- jesd_ctrl_copi => jesd_ctrl_copi,
- jesd_ctrl_cipo => jesd_ctrl_cipo,
- reg_dp_shiftram_copi => reg_dp_shiftram_copi,
- reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
- reg_wg_copi => reg_wg_copi,
- reg_wg_cipo => reg_wg_cipo,
- ram_wg_copi => ram_wg_copi,
- ram_wg_cipo => ram_wg_cipo,
- reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_copi => ram_st_histogram_copi,
- ram_st_histogram_cipo => ram_st_histogram_cipo,
- reg_aduh_monitor_copi => reg_aduh_monitor_copi,
- reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
- ram_st_sst_copi => ram_st_sst_copi,
- ram_st_sst_cipo => ram_st_sst_cipo,
- ram_fil_coefs_copi => ram_fil_coefs_copi,
- ram_fil_coefs_cipo => ram_fil_coefs_cipo,
- reg_si_copi => reg_si_copi,
- reg_si_cipo => reg_si_cipo,
- ram_equalizer_gains_copi => ram_equalizer_gains_copi,
- ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
- ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
- ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
- reg_dp_selector_copi => reg_dp_selector_copi,
- reg_dp_selector_cipo => reg_dp_selector_cipo,
- reg_sdp_info_copi => reg_sdp_info_copi,
- reg_sdp_info_cipo => reg_sdp_info_cipo,
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
- ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
- ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
- ram_bf_weights_copi => ram_bf_weights_copi,
- ram_bf_weights_cipo => ram_bf_weights_cipo,
- reg_bf_scale_copi => reg_bf_scale_copi,
- reg_bf_scale_cipo => reg_bf_scale_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_dp_xonoff_copi => reg_dp_xonoff_copi,
- reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
- ram_st_bst_copi => ram_st_bst_copi,
- ram_st_bst_cipo => ram_st_bst_cipo,
- reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
- reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
- reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
- reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
- reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
- reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
- reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
- reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
- reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
- reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
- reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
- reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
- reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
- reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
- reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
- ram_scrap_copi => ram_scrap_copi,
- ram_scrap_cipo => ram_scrap_cipo,
- reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
- reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
- reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
- reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
- reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
- reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
- reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
- reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
- reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
- reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo,
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+ reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo
+ );
-- Use full 8 bit gn_id = ID
gn_id <= ID;
@@ -769,199 +769,199 @@ begin
-- sdp nodes
-----------------------------------------------------------------------------
u_sdp_station : entity lofar2_sdp_lib.sdp_station
- generic map (
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
- g_scope_selected_subband => g_scope_selected_subband,
- g_no_jesd => c_revision_select.no_jesd,
- g_use_fsub => c_revision_select.use_fsub,
- g_use_oversample => c_revision_select.use_oversample,
- g_use_xsub => c_revision_select.use_xsub,
- g_use_bf => c_revision_select.use_bf,
- g_use_ring => c_revision_select.use_ring,
- g_P_sq => c_revision_select.P_sq
- )
- port map (
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_pps => dp_pps,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- gn_id => gn_id,
- this_bck_id => this_bck_id,
- this_chip_id => this_chip_id,
-
- SA_CLK => SA_CLK,
-
- -- jesd204b
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => JESD204B_SYNC_N,
-
- -- UDP Offload
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- -- 10 GbE
- reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
- reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
- reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
- reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
-
- -- AIT
- jesd204b_copi => jesd204b_copi,
- jesd204b_cipo => jesd204b_cipo,
- jesd_ctrl_copi => jesd_ctrl_copi,
- jesd_ctrl_cipo => jesd_ctrl_cipo,
- reg_dp_shiftram_copi => reg_dp_shiftram_copi,
- reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
- reg_wg_copi => reg_wg_copi,
- reg_wg_cipo => reg_wg_cipo,
- ram_wg_copi => ram_wg_copi,
- ram_wg_cipo => ram_wg_cipo,
- reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_copi => ram_st_histogram_copi,
- ram_st_histogram_cipo => ram_st_histogram_cipo,
- reg_aduh_monitor_copi => reg_aduh_monitor_copi,
- reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
-
- -- FSUB
- ram_st_sst_copi => ram_st_sst_copi,
- ram_st_sst_cipo => ram_st_sst_cipo,
- reg_si_copi => reg_si_copi,
- reg_si_cipo => reg_si_cipo,
- ram_fil_coefs_copi => ram_fil_coefs_copi,
- ram_fil_coefs_cipo => ram_fil_coefs_cipo,
- ram_equalizer_gains_copi => ram_equalizer_gains_copi,
- ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
- ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
- ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
- reg_dp_selector_copi => reg_dp_selector_copi,
- reg_dp_selector_cipo => reg_dp_selector_cipo,
-
- -- SDP Info
- reg_sdp_info_copi => reg_sdp_info_copi,
- reg_sdp_info_cipo => reg_sdp_info_cipo,
-
- -- RING Info
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
-
- -- XSUB
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo,
-
- -- BF
- ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
- ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
- ram_bf_weights_copi => ram_bf_weights_copi,
- ram_bf_weights_cipo => ram_bf_weights_cipo,
- reg_bf_scale_copi => reg_bf_scale_copi,
- reg_bf_scale_cipo => reg_bf_scale_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_dp_xonoff_copi => reg_dp_xonoff_copi,
- reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
- ram_st_bst_copi => ram_st_bst_copi,
- ram_st_bst_cipo => ram_st_bst_cipo,
- reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
- reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
- reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
- reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
- reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
- reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
- reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
- reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
- reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
- reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
- reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
-
- -- SST
- reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
- reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
- reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
- reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-
- -- XST
- reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
-
- reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
- reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
-
- -- BST
- reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
- reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
- reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
- reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
-
- RING_0_TX => RING_0_TX,
- RING_0_RX => RING_0_RX,
- RING_1_TX => RING_1_TX,
- RING_1_RX => RING_1_RX,
-
- -- QSFP serial
- unb2_board_front_io_serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- unb2_board_front_io_serial_rx_arr => unb2_board_front_io_serial_rx_arr,
-
- -- QSFP LEDS
- unb2_board_qsfp_leds_tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
- unb2_board_qsfp_leds_tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
- unb2_board_qsfp_leds_rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
+ g_scope_selected_subband => g_scope_selected_subband,
+ g_no_jesd => c_revision_select.no_jesd,
+ g_use_fsub => c_revision_select.use_fsub,
+ g_use_oversample => c_revision_select.use_oversample,
+ g_use_xsub => c_revision_select.use_xsub,
+ g_use_bf => c_revision_select.use_bf,
+ g_use_ring => c_revision_select.use_ring,
+ g_P_sq => c_revision_select.P_sq
+ )
+ port map (
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_pps => dp_pps,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ gn_id => gn_id,
+ this_bck_id => this_bck_id,
+ this_chip_id => this_chip_id,
+
+ SA_CLK => SA_CLK,
+
+ -- jesd204b
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => JESD204B_SYNC_N,
+
+ -- UDP Offload
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ -- 10 GbE
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+
+ -- AIT
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+
+ -- FSUB
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+
+ -- SDP Info
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
+
+ -- RING Info
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+
+ -- XSUB
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
+
+ -- BF
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+
+ -- SST
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
+ -- XST
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+
+ -- BST
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
+
+ RING_0_TX => RING_0_TX,
+ RING_0_RX => RING_0_RX,
+ RING_1_TX => RING_1_TX,
+ RING_1_RX => RING_1_RX,
+
+ -- QSFP serial
+ unb2_board_front_io_serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ unb2_board_front_io_serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+
+ -- QSFP LEDS
+ unb2_board_qsfp_leds_tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ unb2_board_qsfp_leds_tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ unb2_board_qsfp_leds_rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Interface : 10GbE
@@ -975,40 +975,40 @@ begin
-- Front IO
------------
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
------------
-- LEDs
------------
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
-
- tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
- tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
- rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+
+ tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
index 45da1f25a4..eb43a451c6 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
@@ -20,13 +20,13 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
package lofar2_unb2c_sdp_station_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
index 663256c83f..285a742eb1 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2c_sdp_station_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2c_sdp_station_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2c_sdp_station is
generic (
@@ -143,187 +143,187 @@ entity mmm_lofar2_unb2c_sdp_station is
reg_si_copi : out t_mem_copi;
reg_si_cipo : in t_mem_cipo;
- -- Equalizer gains
- ram_equalizer_gains_copi : out t_mem_copi;
- ram_equalizer_gains_cipo : in t_mem_cipo;
- ram_equalizer_gains_cross_copi : out t_mem_copi;
- ram_equalizer_gains_cross_cipo : in t_mem_cipo;
+ -- Equalizer gains
+ ram_equalizer_gains_copi : out t_mem_copi;
+ ram_equalizer_gains_cipo : in t_mem_cipo;
+ ram_equalizer_gains_cross_copi : out t_mem_copi;
+ ram_equalizer_gains_cross_cipo : in t_mem_cipo;
- -- DP Selector
- reg_dp_selector_copi : out t_mem_copi;
- reg_dp_selector_cipo : in t_mem_cipo;
+ -- DP Selector
+ reg_dp_selector_copi : out t_mem_copi;
+ reg_dp_selector_cipo : in t_mem_cipo;
- -- SDP Info
- reg_sdp_info_copi : out t_mem_copi;
- reg_sdp_info_cipo : in t_mem_cipo;
+ -- SDP Info
+ reg_sdp_info_copi : out t_mem_copi;
+ reg_sdp_info_cipo : in t_mem_cipo;
- -- RING Info
- reg_ring_info_copi : out t_mem_copi;
- reg_ring_info_cipo : in t_mem_cipo;
+ -- RING Info
+ reg_ring_info_copi : out t_mem_copi;
+ reg_ring_info_cipo : in t_mem_cipo;
- -- Beamlet Subband Select
- ram_ss_ss_wide_copi : out t_mem_copi;
- ram_ss_ss_wide_cipo : in t_mem_cipo;
+ -- Beamlet Subband Select
+ ram_ss_ss_wide_copi : out t_mem_copi;
+ ram_ss_ss_wide_cipo : in t_mem_cipo;
- -- Local BF bf weights
- ram_bf_weights_copi : out t_mem_copi;
- ram_bf_weights_cipo : in t_mem_cipo;
+ -- Local BF bf weights
+ ram_bf_weights_copi : out t_mem_copi;
+ ram_bf_weights_cipo : in t_mem_cipo;
- -- BF bsn aligner_v2
- reg_bsn_align_v2_bf_copi : out t_mem_copi;
- reg_bsn_align_v2_bf_cipo : in t_mem_cipo;
+ -- BF bsn aligner_v2
+ reg_bsn_align_v2_bf_copi : out t_mem_copi;
+ reg_bsn_align_v2_bf_cipo : in t_mem_cipo;
- -- BF bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_rx_align_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_rx_align_bf_cipo : in t_mem_cipo;
- reg_bsn_monitor_v2_aligned_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_aligned_bf_cipo : in t_mem_cipo;
-
- -- mms_dp_scale Scale Beamlets
- reg_bf_scale_copi : out t_mem_copi;
- reg_bf_scale_cipo : in t_mem_cipo;
-
- -- Beamlet Data Output header fields
- reg_hdr_dat_copi : out t_mem_copi;
- reg_hdr_dat_cipo : in t_mem_cipo;
-
- -- Beamlet Data Output xonoff
- reg_dp_xonoff_copi : out t_mem_copi;
- reg_dp_xonoff_cipo : in t_mem_cipo;
-
- -- BF ring lane info
- reg_ring_lane_info_bf_copi : out t_mem_copi;
- reg_ring_lane_info_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_rx_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_tx_bf_cipo : in t_mem_cipo;
-
- -- BF ring validate err
- reg_dp_block_validate_err_bf_copi : out t_mem_copi;
- reg_dp_block_validate_err_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_bf_copi : out t_mem_copi;
- reg_dp_block_validate_bsn_at_sync_bf_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics (BST)
- ram_st_bst_copi : out t_mem_copi;
- ram_st_bst_cipo : in t_mem_cipo;
-
- -- Subband Statistics offload
- reg_stat_enable_sst_copi : out t_mem_copi;
- reg_stat_enable_sst_cipo : in t_mem_cipo;
-
- -- Statistics header info
- reg_stat_hdr_dat_sst_copi : out t_mem_copi;
- reg_stat_hdr_dat_sst_cipo : in t_mem_cipo;
-
- -- Crosslet Statistics offload
- reg_stat_enable_xst_copi : out t_mem_copi;
- reg_stat_enable_xst_cipo : in t_mem_cipo;
-
- -- Crosslet Statistics header info
- reg_stat_hdr_dat_xst_copi : out t_mem_copi;
- reg_stat_hdr_dat_xst_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics offload
- reg_stat_enable_bst_copi : out t_mem_copi;
- reg_stat_enable_bst_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics header info
- reg_stat_hdr_dat_bst_copi : out t_mem_copi;
- reg_stat_hdr_dat_bst_cipo : in t_mem_cipo;
-
- -- crosslets_info
- reg_crosslets_info_copi : out t_mem_copi;
- reg_crosslets_info_cipo : in t_mem_cipo;
-
- -- crosslets_info
- reg_nof_crosslets_copi : out t_mem_copi;
- reg_nof_crosslets_cipo : in t_mem_cipo;
-
- -- bsn_sync_scheduler_xsub
- reg_bsn_sync_scheduler_xsub_copi : out t_mem_copi;
- reg_bsn_sync_scheduler_xsub_cipo : in t_mem_cipo;
-
- -- st_xsq (XST)
- ram_st_xsq_copi : out t_mem_copi;
- ram_st_xsq_cipo : in t_mem_cipo;
-
- -- 10 GbE mac
- reg_nw_10GbE_mac_copi : out t_mem_copi;
- reg_nw_10GbE_mac_cipo : in t_mem_cipo;
-
- -- 10 GbE eth
- reg_nw_10GbE_eth10g_copi : out t_mem_copi;
- reg_nw_10GbE_eth10g_cipo : in t_mem_cipo;
-
- -- XST bsn aligner_v2
- reg_bsn_align_v2_xsub_copi : out t_mem_copi;
- reg_bsn_align_v2_xsub_cipo : in t_mem_cipo;
-
- -- XST bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_rx_align_xsub_copi : out t_mem_copi;
- reg_bsn_monitor_v2_rx_align_xsub_cipo : in t_mem_cipo;
- reg_bsn_monitor_v2_aligned_xsub_copi : out t_mem_copi;
- reg_bsn_monitor_v2_aligned_xsub_cipo : in t_mem_cipo;
-
- -- XST UDP offload bsn monitor
- reg_bsn_monitor_v2_xst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_xst_offload_cipo : in t_mem_cipo;
-
- -- BST UDP offload bsn monitor
- reg_bsn_monitor_v2_bst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_bst_offload_cipo : in t_mem_cipo;
-
- -- Beamlet output bsn monitor
- reg_bsn_monitor_v2_beamlet_output_copi : out t_mem_copi;
- reg_bsn_monitor_v2_beamlet_output_cipo : in t_mem_cipo;
-
- -- SST UDP offload bsn monitor
- reg_bsn_monitor_v2_sst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_sst_offload_cipo : in t_mem_cipo;
-
- -- XST ring lane info
- reg_ring_lane_info_xst_copi : out t_mem_copi;
- reg_ring_lane_info_xst_cipo : in t_mem_cipo;
-
- -- XST ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_xst_copi: out t_mem_copi;
- reg_bsn_monitor_v2_ring_rx_xst_cipo: in t_mem_cipo;
-
- -- XST ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_xst_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_tx_xst_cipo : in t_mem_cipo;
-
- -- XST ring validate err
- reg_dp_block_validate_err_xst_copi : out t_mem_copi;
- reg_dp_block_validate_err_xst_cipo : in t_mem_cipo;
-
- -- XST ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_xst_copi : out t_mem_copi;
- reg_dp_block_validate_bsn_at_sync_xst_cipo : in t_mem_cipo;
-
- -- XST ring MAC
- reg_tr_10GbE_mac_copi : out t_mem_copi;
- reg_tr_10GbE_mac_cipo : in t_mem_cipo;
-
- -- XST ring ETH
- reg_tr_10GbE_eth10g_copi : out t_mem_copi;
- reg_tr_10GbE_eth10g_cipo : in t_mem_cipo;
-
- -- Scrap ram
- ram_scrap_copi : out t_mem_copi;
- ram_scrap_cipo : in t_mem_cipo;
-
- -- Jesd reset control
- jesd_ctrl_copi : out t_mem_copi;
- jesd_ctrl_cipo : in t_mem_cipo
+ -- BF bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_bf_cipo : in t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_aligned_bf_cipo : in t_mem_cipo;
+
+ -- mms_dp_scale Scale Beamlets
+ reg_bf_scale_copi : out t_mem_copi;
+ reg_bf_scale_cipo : in t_mem_cipo;
+
+ -- Beamlet Data Output header fields
+ reg_hdr_dat_copi : out t_mem_copi;
+ reg_hdr_dat_cipo : in t_mem_cipo;
+
+ -- Beamlet Data Output xonoff
+ reg_dp_xonoff_copi : out t_mem_copi;
+ reg_dp_xonoff_cipo : in t_mem_cipo;
+
+ -- BF ring lane info
+ reg_ring_lane_info_bf_copi : out t_mem_copi;
+ reg_ring_lane_info_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_bf_cipo : in t_mem_cipo;
+
+ -- BF ring validate err
+ reg_dp_block_validate_err_bf_copi : out t_mem_copi;
+ reg_dp_block_validate_err_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_bf_copi : out t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_bf_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics (BST)
+ ram_st_bst_copi : out t_mem_copi;
+ ram_st_bst_cipo : in t_mem_cipo;
+
+ -- Subband Statistics offload
+ reg_stat_enable_sst_copi : out t_mem_copi;
+ reg_stat_enable_sst_cipo : in t_mem_cipo;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_sst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_sst_cipo : in t_mem_cipo;
+
+ -- Crosslet Statistics offload
+ reg_stat_enable_xst_copi : out t_mem_copi;
+ reg_stat_enable_xst_cipo : in t_mem_cipo;
+
+ -- Crosslet Statistics header info
+ reg_stat_hdr_dat_xst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_xst_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics offload
+ reg_stat_enable_bst_copi : out t_mem_copi;
+ reg_stat_enable_bst_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics header info
+ reg_stat_hdr_dat_bst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_bst_cipo : in t_mem_cipo;
+
+ -- crosslets_info
+ reg_crosslets_info_copi : out t_mem_copi;
+ reg_crosslets_info_cipo : in t_mem_cipo;
+
+ -- crosslets_info
+ reg_nof_crosslets_copi : out t_mem_copi;
+ reg_nof_crosslets_cipo : in t_mem_cipo;
+
+ -- bsn_sync_scheduler_xsub
+ reg_bsn_sync_scheduler_xsub_copi : out t_mem_copi;
+ reg_bsn_sync_scheduler_xsub_cipo : in t_mem_cipo;
+
+ -- st_xsq (XST)
+ ram_st_xsq_copi : out t_mem_copi;
+ ram_st_xsq_cipo : in t_mem_cipo;
+
+ -- 10 GbE mac
+ reg_nw_10GbE_mac_copi : out t_mem_copi;
+ reg_nw_10GbE_mac_cipo : in t_mem_cipo;
+
+ -- 10 GbE eth
+ reg_nw_10GbE_eth10g_copi : out t_mem_copi;
+ reg_nw_10GbE_eth10g_cipo : in t_mem_cipo;
+
+ -- XST bsn aligner_v2
+ reg_bsn_align_v2_xsub_copi : out t_mem_copi;
+ reg_bsn_align_v2_xsub_cipo : in t_mem_cipo;
+
+ -- XST bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_xsub_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_xsub_cipo : in t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_xsub_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_aligned_xsub_cipo : in t_mem_cipo;
+
+ -- XST UDP offload bsn monitor
+ reg_bsn_monitor_v2_xst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_xst_offload_cipo : in t_mem_cipo;
+
+ -- BST UDP offload bsn monitor
+ reg_bsn_monitor_v2_bst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_bst_offload_cipo : in t_mem_cipo;
+
+ -- Beamlet output bsn monitor
+ reg_bsn_monitor_v2_beamlet_output_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_beamlet_output_cipo : in t_mem_cipo;
+
+ -- SST UDP offload bsn monitor
+ reg_bsn_monitor_v2_sst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_sst_offload_cipo : in t_mem_cipo;
+
+ -- XST ring lane info
+ reg_ring_lane_info_xst_copi : out t_mem_copi;
+ reg_ring_lane_info_xst_cipo : in t_mem_cipo;
+
+ -- XST ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_xst_copi: out t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_xst_cipo: in t_mem_cipo;
+
+ -- XST ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_xst_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_xst_cipo : in t_mem_cipo;
+
+ -- XST ring validate err
+ reg_dp_block_validate_err_xst_copi : out t_mem_copi;
+ reg_dp_block_validate_err_xst_cipo : in t_mem_cipo;
+
+ -- XST ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_xst_copi : out t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_xst_cipo : in t_mem_cipo;
+
+ -- XST ring MAC
+ reg_tr_10GbE_mac_copi : out t_mem_copi;
+ reg_tr_10GbE_mac_cipo : in t_mem_cipo;
+
+ -- XST ring ETH
+ reg_tr_10GbE_eth10g_copi : out t_mem_copi;
+ reg_tr_10GbE_eth10g_cipo : in t_mem_cipo;
+
+ -- Scrap ram
+ ram_scrap_copi : out t_mem_copi;
+ ram_scrap_cipo : in t_mem_cipo;
+
+ -- Jesd reset control
+ jesd_ctrl_copi : out t_mem_copi;
+ jesd_ctrl_cipo : in t_mem_cipo
);
end mmm_lofar2_unb2c_sdp_station;
@@ -337,208 +337,276 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
-- Must use exact g_mm_rd_latency = 1 instead of default 2, because JESD204B IP forces rddata = 0 after it has been read
- u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B", '1', 1)
- port map(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
+ u_mm_file_jesd204b : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B", '1', 1)
+ port map(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
+
+ u_mm_file_pio_jesd_ctrl : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_JESD_CTRL")
+ port map(mm_rst, mm_clk, jesd_ctrl_copi, jesd_ctrl_cipo );
+
+ u_mm_file_reg_dp_shiftram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
+ port map(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
+
+ u_mm_file_reg_bsn_source_v2 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
+ port map(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
+
+ u_mm_file_reg_bsn_scheduler : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
+
+ u_mm_file_reg_bsn_monitor_input : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
+
+ u_mm_file_reg_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
+ port map(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
+ u_mm_file_ram_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
+ port map(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
+
+ u_mm_file_ram_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
+ u_mm_file_reg_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
+
+ u_mm_file_ram_st_histogram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
+ port map(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
+
+ u_mm_file_reg_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
+
+ u_mm_file_ram_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
+ port map(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
+
+ u_mm_file_ram_fil_coefs : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
+ port map(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
+
+ u_mm_file_reg_si : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
+ port map(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
+
+ u_mm_file_ram_equalizer_gains : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
+ port map(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
+ u_mm_file_ram_equalizer_gains_cross : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS_CROSS")
+ port map(mm_rst, mm_clk, ram_equalizer_gains_cross_copi, ram_equalizer_gains_cross_cipo );
+
+ u_mm_file_reg_dp_selector : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
+ port map(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
+
+ u_mm_file_reg_sdp_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+ port map(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
+
+ u_mm_file_reg_ring_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
+ port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
+
+ u_mm_file_ram_ss_ss_wide : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ port map(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
+
+ u_mm_file_ram_bf_weights : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
+ port map(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
+
+ u_mm_file_reg_bf_scale : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
+ port map(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
+
+ u_mm_file_reg_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
+
+ u_mm_file_reg_dp_xonoff : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
+
+ u_mm_file_ram_st_bst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
+ port map(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
+
+ u_mm_file_reg_stat_enable_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
+ port map(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
+
+ u_mm_file_reg_stat_hdr_info_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
+
+ u_mm_file_reg_stat_enable_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
+ port map(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
+
+ u_mm_file_reg_stat_hdr_info_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
+
+ u_mm_file_reg_stat_enable_bst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
+ port map(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
+
+ u_mm_file_reg_stat_hdr_info_bst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
+
+ u_mm_file_reg_crosslets_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
+ port map(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
+
+ u_mm_file_reg_nof_crosslets : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
+ port map(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
+
+ u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
- u_mm_file_pio_jesd_ctrl : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_JESD_CTRL")
- port map(mm_rst, mm_clk, jesd_ctrl_copi, jesd_ctrl_cipo );
+ u_mm_file_ram_st_xsq : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
+ port map(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
+
+ u_mm_file_reg_nw_10GbE_mac : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
+ port map(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
+
+ u_mm_file_reg_nw_10GbE_eth10g : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
+ port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
+
+ u_mm_file_reg_bsn_align_v2_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_BF")
+ port map(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_rx_align_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_aligned_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
+
+ u_mm_file_reg_ring_lane_info_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_BF")
+ port map(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
- u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_rx_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
- u_mm_file_reg_bsn_source_v2 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
- port map(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_tx_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
- u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
+ u_mm_file_reg_dp_block_validate_err_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_BF")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
- u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
+ u_mm_file_reg_dp_block_validate_bsn_at_sync_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
- u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
- u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
+ u_mm_file_reg_bsn_align_v2_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
- u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
- u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_align_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
- u_mm_file_ram_st_histogram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
- port map(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
+ u_mm_file_reg_bsn_monitor_v2_aligned_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
- u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
+ u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
- u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
+ u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
- u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
+ u_mm_file_reg_bsn_monitor_v2_beamlet_output : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BEAMLET_OUTPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
- u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
+ u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
- u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
- u_mm_file_ram_equalizer_gains_cross : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS_CROSS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_cross_copi, ram_equalizer_gains_cross_cipo );
+ u_mm_file_reg_ring_lane_info_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
+ port map(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
- u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_XST")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
- u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_tx_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_XST")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_xst_copi, reg_bsn_monitor_v2_ring_tx_xst_cipo );
- u_mm_file_reg_ring_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
- port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
+ u_mm_file_reg_dp_block_validate_err_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_XST")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_xst_copi, reg_dp_block_validate_err_xst_cipo );
- u_mm_file_ram_ss_ss_wide : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
+ u_mm_file_reg_dp_block_validate_bsn_at_sync_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_xst_copi, reg_dp_block_validate_bsn_at_sync_xst_cipo );
- u_mm_file_ram_bf_weights : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- port map(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
+ u_mm_file_reg_tr_10GbE_mac : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
- u_mm_file_reg_bf_scale : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
- port map(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
+ u_mm_file_reg_tr_10GbE_eth10g : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
- u_mm_file_reg_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
- port map(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
-
- u_mm_file_reg_dp_xonoff : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
- port map(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
-
- u_mm_file_ram_st_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
- port map(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
-
- u_mm_file_reg_stat_enable_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
- port map(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
-
- u_mm_file_reg_stat_hdr_info_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
-
- u_mm_file_reg_stat_enable_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
- port map(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
-
- u_mm_file_reg_stat_hdr_info_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
-
- u_mm_file_reg_stat_enable_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
- port map(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
-
- u_mm_file_reg_stat_hdr_info_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
-
- u_mm_file_reg_crosslets_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
- port map(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
-
- u_mm_file_reg_nof_crosslets : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
- port map(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
-
- u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
-
- u_mm_file_ram_st_xsq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
- port map(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
-
- u_mm_file_reg_nw_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
-
- u_mm_file_reg_nw_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
-
- u_mm_file_reg_bsn_align_v2_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_BF")
- port map(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_rx_align_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_aligned_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
-
- u_mm_file_reg_ring_lane_info_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_BF")
- port map(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_ring_rx_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_ring_tx_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
-
- u_mm_file_reg_dp_block_validate_err_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_BF")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
-
- u_mm_file_reg_dp_block_validate_bsn_at_sync_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
-
- u_mm_file_reg_bsn_align_v2_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_rx_align_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_aligned_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_beamlet_output : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BEAMLET_OUTPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
-
- u_mm_file_reg_ring_lane_info_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
- port map(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_XST")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
-
- u_mm_file_reg_bsn_monitor_v2_ring_tx_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_XST")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_xst_copi, reg_bsn_monitor_v2_ring_tx_xst_cipo );
-
- u_mm_file_reg_dp_block_validate_err_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_XST")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_xst_copi, reg_dp_block_validate_err_xst_cipo );
-
- u_mm_file_reg_dp_block_validate_bsn_at_sync_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_xst_copi, reg_dp_block_validate_bsn_at_sync_xst_cipo );
-
- u_mm_file_reg_tr_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
-
- u_mm_file_reg_tr_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
-
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -598,8 +666,8 @@ begin
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
--- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
+ -- ToDo: This has changed in the peripherals package
+ -- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
rom_system_info_write_export => rom_unb_system_info_copi.wr,
rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index 3fa9fa61c5..9a0211fc9c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -19,548 +19,548 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_sdp_station_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2c_sdp_station is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_reset_export : out std_logic; -- export
- ram_st_histogram_clk_export : out std_logic; -- export
- ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
- ram_st_histogram_write_export : out std_logic; -- export
- ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_read_export : out std_logic; -- export
- ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
- ram_st_xsq_clk_export : out std_logic; -- export
- ram_st_xsq_read_export : out std_logic; -- export
- ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_xsq_reset_export : out std_logic; -- export
- ram_st_xsq_write_export : out std_logic; -- export
- ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
- reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
- reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_align_v2_bf_write_export : out std_logic; -- export
- reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_read_export : out std_logic; -- export
- reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_crosslets_info_clk_export : out std_logic; -- export
- reg_crosslets_info_read_export : out std_logic; -- export
- reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_reset_export : out std_logic; -- export
- reg_crosslets_info_write_export : out std_logic; -- export
- reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_reset_export : out std_logic; -- export
- reg_nof_crosslets_clk_export : out std_logic; -- export
- reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nof_crosslets_write_export : out std_logic; -- export
- reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_read_export : out std_logic; -- export
- reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_bf_reset_export : out std_logic; -- export
- reg_ring_lane_info_bf_clk_export : out std_logic; -- export
- reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_lane_info_bf_write_export : out std_logic; -- export
- reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_bf_read_export : out std_logic; -- export
- reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_xst_reset_export : out std_logic; -- export
- reg_ring_lane_info_xst_clk_export : out std_logic; -- export
- reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ring_lane_info_xst_write_export : out std_logic; -- export
- reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_xst_read_export : out std_logic; -- export
- reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_stat_enable_bst_clk_export : out std_logic; -- export
- reg_stat_enable_bst_read_export : out std_logic; -- export
- reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_bst_reset_export : out std_logic; -- export
- reg_stat_enable_bst_write_export : out std_logic; -- export
- reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_sst_clk_export : out std_logic; -- export
- reg_stat_enable_sst_read_export : out std_logic; -- export
- reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_sst_reset_export : out std_logic; -- export
- reg_stat_enable_sst_write_export : out std_logic; -- export
- reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_xst_clk_export : out std_logic; -- export
- reg_stat_enable_xst_read_export : out std_logic; -- export
- reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_xst_reset_export : out std_logic; -- export
- reg_stat_enable_xst_write_export : out std_logic; -- export
- reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_cross_reset_export : out std_logic; -- export
- ram_equalizer_gains_cross_clk_export : out std_logic; -- export
- ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_cross_write_export : out std_logic; -- export
- ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_cross_read_export : out std_logic; -- export
- ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_lofar2_unb2c_sdp_station;
+ component qsys_lofar2_unb2c_sdp_station is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_bf_weights_reset_export : out std_logic; -- export
+ ram_bf_weights_clk_export : out std_logic; -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bf_weights_write_export : out std_logic; -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_bf_weights_read_export : out std_logic; -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_st_bst_clk_export : out std_logic; -- export
+ ram_st_bst_read_export : out std_logic; -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_bst_reset_export : out std_logic; -- export
+ ram_st_bst_write_export : out std_logic; -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_reset_export : out std_logic; -- export
+ ram_st_histogram_clk_export : out std_logic; -- export
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_st_histogram_write_export : out std_logic; -- export
+ ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_read_export : out std_logic; -- export
+ ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
+ ram_st_xsq_clk_export : out std_logic; -- export
+ ram_st_xsq_read_export : out std_logic; -- export
+ ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_xsq_reset_export : out std_logic; -- export
+ ram_st_xsq_write_export : out std_logic; -- export
+ ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bf_scale_clk_export : out std_logic; -- export
+ reg_bf_scale_read_export : out std_logic; -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bf_scale_reset_export : out std_logic; -- export
+ reg_bf_scale_write_export : out std_logic; -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_align_v2_bf_write_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_read_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_v2_clk_export : out std_logic; -- export
+ reg_bsn_source_v2_read_export : out std_logic; -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_v2_reset_export : out std_logic; -- export
+ reg_bsn_source_v2_write_export : out std_logic; -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_crosslets_info_clk_export : out std_logic; -- export
+ reg_crosslets_info_read_export : out std_logic; -- export
+ reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_reset_export : out std_logic; -- export
+ reg_crosslets_info_write_export : out std_logic; -- export
+ reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_xonoff_clk_export : out std_logic; -- export
+ reg_dp_xonoff_read_export : out std_logic; -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_reset_export : out std_logic; -- export
+ reg_dp_xonoff_write_export : out std_logic; -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_clk_export : out std_logic; -- export
+ reg_hdr_dat_read_export : out std_logic; -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_reset_export : out std_logic; -- export
+ reg_hdr_dat_write_export : out std_logic; -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_reset_export : out std_logic; -- export
+ reg_nof_crosslets_clk_export : out std_logic; -- export
+ reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nof_crosslets_write_export : out std_logic; -- export
+ reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_read_export : out std_logic; -- export
+ reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic; -- export
+ reg_nw_10gbe_mac_read_export : out std_logic; -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic; -- export
+ reg_nw_10gbe_mac_write_export : out std_logic; -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_bf_reset_export : out std_logic; -- export
+ reg_ring_lane_info_bf_clk_export : out std_logic; -- export
+ reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_lane_info_bf_write_export : out std_logic; -- export
+ reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_bf_read_export : out std_logic; -- export
+ reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_xst_reset_export : out std_logic; -- export
+ reg_ring_lane_info_xst_clk_export : out std_logic; -- export
+ reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_ring_lane_info_xst_write_export : out std_logic; -- export
+ reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_xst_read_export : out std_logic; -- export
+ reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_stat_enable_bst_clk_export : out std_logic; -- export
+ reg_stat_enable_bst_read_export : out std_logic; -- export
+ reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_bst_reset_export : out std_logic; -- export
+ reg_stat_enable_bst_write_export : out std_logic; -- export
+ reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_sst_clk_export : out std_logic; -- export
+ reg_stat_enable_sst_read_export : out std_logic; -- export
+ reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_sst_reset_export : out std_logic; -- export
+ reg_stat_enable_sst_write_export : out std_logic; -- export
+ reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_xst_clk_export : out std_logic; -- export
+ reg_stat_enable_xst_read_export : out std_logic; -- export
+ reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_xst_reset_export : out std_logic; -- export
+ reg_stat_enable_xst_write_export : out std_logic; -- export
+ reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_cross_reset_export : out std_logic; -- export
+ ram_equalizer_gains_cross_clk_export : out std_logic; -- export
+ ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_cross_write_export : out std_logic; -- export
+ ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_cross_read_export : out std_logic; -- export
+ ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_lofar2_unb2c_sdp_station;
end qsys_lofar2_unb2c_sdp_station_pkg;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
index c784b9032b..15392c4f5e 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
@@ -28,12 +28,12 @@
--
library IEEE, dp_lib, common_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity ddrctrl_controller is
generic (
@@ -99,31 +99,31 @@ architecture rtl of ddrctrl_controller is
-- record for readability
type t_reg is record
- -- state of program
- state : t_state;
- started : std_logic;
-
- -- stopping signals
- filled_mem : std_logic;
- ready_for_set_stop : std_logic;
- stop_adr : std_logic_vector(c_adr_w - 1 downto 0);
- last_adr_to_write_to : std_logic_vector(c_adr_w - 1 downto 0);
- stop_burstsize : natural;
- stopped : std_logic;
- rst_ddrctrl_input : std_logic;
-
- -- writing signals
- wr_burst_en : std_logic;
- wr_bursts_ready : natural;
-
- -- reading signals
- outp_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
- read_adr : natural;
- rd_burst_en : std_logic;
-
- -- output
- dvr_mosi : t_mem_ctlr_mosi;
- wr_sosi : t_dp_sosi;
+ -- state of program
+ state : t_state;
+ started : std_logic;
+
+ -- stopping signals
+ filled_mem : std_logic;
+ ready_for_set_stop : std_logic;
+ stop_adr : std_logic_vector(c_adr_w - 1 downto 0);
+ last_adr_to_write_to : std_logic_vector(c_adr_w - 1 downto 0);
+ stop_burstsize : natural;
+ stopped : std_logic;
+ rst_ddrctrl_input : std_logic;
+
+ -- writing signals
+ wr_burst_en : std_logic;
+ wr_bursts_ready : natural;
+
+ -- reading signals
+ outp_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ read_adr : natural;
+ rd_burst_en : std_logic;
+
+ -- output
+ dvr_mosi : t_mem_ctlr_mosi;
+ wr_sosi : t_dp_sosi;
end record;
constant c_t_reg_init : t_reg := (RESET, '0', '0', '0', TO_UVEC(g_max_adr, c_adr_w), (others => '0'), 0, '1', '1', '0', 0, (others => '0'), 0, '1', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
@@ -143,232 +143,232 @@ begin
v.wr_sosi := inp_sosi;
case q_reg.state is
- when RESET =>
- v := c_t_reg_init;
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
- v.dvr_mosi.wr := '1';
- v.wr_sosi.valid := '1';
-
- if rst = '0' then
- v.state := STOP_READING;
- end if;
-
- when STOP_READING =>
- -- this is the last read burst, this make sure every data containing word in the memory has been read.
- if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
- v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.stopped := '0';
- v.wr_sosi.valid := '0';
- v.state := WAIT_FOR_SOP;
- v.wr_burst_en := '1';
- v.rst_ddrctrl_input := '1';
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
-
- if dvr_miso.done = '0' then
- v.rd_burst_en := '1';
- end if;
-
- when WAIT_FOR_SOP =>
- v.dvr_mosi.burstbegin := '0';
- v.rst_ddrctrl_input := '0';
- if q_reg.started = '0' and inp_sosi.eop = '1' then
- v.wr_sosi.valid := '1';
- elsif inp_sosi.sop = '1' then
- v.state := WRITING;
- else
- v.wr_sosi.valid := '0';
- end if;
-
- when WRITING =>
- -- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if q_reg.wr_bursts_ready >= 1 and dvr_miso.done = '1' and q_reg.wr_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ when RESET =>
+ v := c_t_reg_init;
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
+ v.dvr_mosi.wr := '1';
+ v.wr_sosi.valid := '1';
+
+ if rst = '0' then
+ v.state := STOP_READING;
+ end if;
+
+ when STOP_READING =>
+ -- this is the last read burst, this make sure every data containing word in the memory has been read.
+ if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
+ v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.stopped := '0';
+ v.wr_sosi.valid := '0';
+ v.state := WAIT_FOR_SOP;
+ v.wr_burst_en := '1';
+ v.rst_ddrctrl_input := '1';
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+
+ if dvr_miso.done = '0' then
+ v.rd_burst_en := '1';
+ end if;
+
+ when WAIT_FOR_SOP =>
+ v.dvr_mosi.burstbegin := '0';
+ v.rst_ddrctrl_input := '0';
+ if q_reg.started = '0' and inp_sosi.eop = '1' then
+ v.wr_sosi.valid := '1';
+ elsif inp_sosi.sop = '1' then
+ v.state := WRITING;
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.wr_sosi.valid := '0';
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
-
- if stop_in = '1' then
- v.ready_for_set_stop := '1';
- end if;
-
- if inp_adr >= c_pof_ma then
- v.filled_mem := '1';
- end if
-
- if q_reg.ready_for_set_stop = '1' and inp_sosi.eop = '1' and stop_in = '0' and v.filled_mem = '1' then
- v.state := SET_STOP;
- elsif q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
- v.state := STOP_WRITING;
- end if;
-
- when SET_STOP =>
- -- this state sets a stop address dependend on the g_stop_percentage.
- if inp_adr - c_pof_ma >= 0 then
- v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr - c_pof_ma, c_adr_w);
- else
- v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr + g_max_adr - c_pof_ma, c_adr_w);
- end if;
- v.ready_for_set_stop := '0';
- v.last_adr_to_write_to(c_adr_w - 1 downto c_bitshift_w) := v.stop_adr(c_adr_w - 1 downto c_bitshift_w);
- v.last_adr_to_write_to(c_bitshift_w - 1 downto 0) := (others => '0');
- v.stop_burstsize := TO_UINT(v.stop_adr(c_adr_w - 1 downto 0)) - TO_UINT(v.last_adr_to_write_to) + 1;
-
- -- still a write cyle
- -- if adr mod g_burstsize = 0
- -- this makes sure that only ones every 64 writes a writeburst is started.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
- if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+
+ when WRITING =>
+ -- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if q_reg.wr_bursts_ready >= 1 and dvr_miso.done = '1' and q_reg.wr_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
+ end if;
+
+ if stop_in = '1' then
+ v.ready_for_set_stop := '1';
+ end if;
+
+ if inp_adr >= c_pof_ma then
+ v.filled_mem := '1';
+ end if
+
+ if q_reg.ready_for_set_stop = '1' and inp_sosi.eop = '1' and stop_in = '0' and v.filled_mem = '1' then
+ v.state := SET_STOP;
+ elsif q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
+ v.state := STOP_WRITING;
+ end if;
+
+ when SET_STOP =>
+ -- this state sets a stop address dependend on the g_stop_percentage.
+ if inp_adr - c_pof_ma >= 0 then
+ v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr - c_pof_ma, c_adr_w);
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr + g_max_adr - c_pof_ma, c_adr_w);
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
- v.state := STOP_WRITING;
- else
- v.state := WRITING;
- end if;
-
- when STOP_WRITING =>
- -- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
- v.wr_sosi.valid := '0';
- v.dvr_mosi.burstbegin := '0';
- v.stopped := '1';
- v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
-
- -- still receiving write data.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
- if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * q_reg.wr_bursts_ready - 1), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.ready_for_set_stop := '0';
+ v.last_adr_to_write_to(c_adr_w - 1 downto c_bitshift_w) := v.stop_adr(c_adr_w - 1 downto c_bitshift_w);
+ v.last_adr_to_write_to(c_bitshift_w - 1 downto 0) := (others => '0');
+ v.stop_burstsize := TO_UINT(v.stop_adr(c_adr_w - 1 downto 0)) - TO_UINT(v.last_adr_to_write_to) + 1;
+
+ -- still a write cyle
+ -- if adr mod g_burstsize = 0
+ -- this makes sure that only ones every 64 writes a writeburst is started.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
+ end if;
+ if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.burstbegin := '0';
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if dvr_miso.done = '1' and q_reg.dvr_mosi.burstbegin = '0' and q_reg.wr_burst_en = '0' and q_reg.wr_bursts_ready = 0 then
- v.state := LAST_WRITE_BURST;
- end if;
-
- when LAST_WRITE_BURST =>
- -- this state stops the writing by generatign one last write burst which empties wr_fifo.
- if dvr_miso.done = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
- v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.state := START_READING;
- v.rd_burst_en := '1';
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- when START_READING =>
- -- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
- v.dvr_mosi.burstbegin := '0';
- v.outp_bsn := TO_UVEC(TO_UINT(inp_sosi.bsn) - g_bim, c_dp_stream_bsn_w);
-
- if dvr_miso.done = '1' and v.rd_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize - q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + q_reg.stop_burstsize, c_adr_w);
- v.rd_burst_en := '0';
- v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + g_burstsize;
- end if;
-
- -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
- if dvr_miso.done = '0' and q_reg.rd_burst_en = '0' then
- v.rd_burst_en := '1';
- v.state := READING;
- end if;
-
- when READING =>
- -- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
- if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
- v.dvr_mosi.burstbegin := '1';
- v.rd_burst_en := '0';
- if q_reg.read_adr > g_max_adr - g_burstsize then
- v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
- v.read_adr := 0;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
+ v.state := STOP_WRITING;
else
- v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
- v.read_adr := q_reg.read_adr + g_burstsize;
+ v.state := WRITING;
end if;
- else
+
+ when STOP_WRITING =>
+ -- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
+ v.wr_sosi.valid := '0';
v.dvr_mosi.burstbegin := '0';
- end if;
+ v.stopped := '1';
+ v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
+
+ -- still receiving write data.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
+ end if;
+ if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * q_reg.wr_bursts_ready - 1), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
- -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
- if dvr_miso.done = '0' then
- v.rd_burst_en := '1';
- end if;
+ if dvr_miso.done = '1' and q_reg.dvr_mosi.burstbegin = '0' and q_reg.wr_burst_en = '0' and q_reg.wr_bursts_ready = 0 then
+ v.state := LAST_WRITE_BURST;
+ end if;
- -- goes to STOP_reading when this read burst was from the burstblock before q_reg.stop_adr
- if q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0) = TO_UVEC(q_reg.read_adr, c_adr_w) then
- v.state := STOP_READING;
- end if;
+ when LAST_WRITE_BURST =>
+ -- this state stops the writing by generatign one last write burst which empties wr_fifo.
+ if dvr_miso.done = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
+ v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.state := START_READING;
+ v.rd_burst_en := '1';
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ when START_READING =>
+ -- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
+ v.dvr_mosi.burstbegin := '0';
+ v.outp_bsn := TO_UVEC(TO_UINT(inp_sosi.bsn) - g_bim, c_dp_stream_bsn_w);
+
+ if dvr_miso.done = '1' and v.rd_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize - q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + q_reg.stop_burstsize, c_adr_w);
+ v.rd_burst_en := '0';
+ v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + g_burstsize;
+ end if;
+
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ if dvr_miso.done = '0' and q_reg.rd_burst_en = '0' then
+ v.rd_burst_en := '1';
+ v.state := READING;
+ end if;
+
+ when READING =>
+ -- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
+ if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.dvr_mosi.burstbegin := '1';
+ v.rd_burst_en := '0';
+ if q_reg.read_adr > g_max_adr - g_burstsize then
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := 0;
+ else
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := q_reg.read_adr + g_burstsize;
+ end if;
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ if dvr_miso.done = '0' then
+ v.rd_burst_en := '1';
+ end if;
+
+ -- goes to STOP_reading when this read burst was from the burstblock before q_reg.stop_adr
+ if q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0) = TO_UVEC(q_reg.read_adr, c_adr_w) then
+ v.state := STOP_READING;
+ end if;
end case;
if rst = '1' then
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index bc766c0ba8..aac5fef2dc 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -33,16 +33,16 @@
-- The maximum value of the address is determend by g_tech_ddr.
library IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use io_ddr_lib.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use io_ddr_lib.all;
entity ddrctrl is
generic (
@@ -148,174 +148,174 @@ begin
-- input to io_ddr
u_ddrctrl_input : entity work.ddrctrl_input
- generic map(
- g_tech_ddr => g_tech_ddr,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_max_adr => c_nof_adr,
- g_bim => c_bim,
- g_of_pb => c_of_pb,
- g_block_size => g_block_size
- )
- port map(
- clk => clk,
- rst => rst,
- rst_ddrctrl_input_ac => rst_ddrctrl_input_ac,
- in_sosi_arr => in_sosi_arr,
- in_stop => stop,
- out_sosi => out_sosi,
- out_adr => out_adr,
- out_bsn_adr => inp_bsn_adr,
- out_data_stopped => data_stopped
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_max_adr => c_nof_adr,
+ g_bim => c_bim,
+ g_of_pb => c_of_pb,
+ g_block_size => g_block_size
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+ rst_ddrctrl_input_ac => rst_ddrctrl_input_ac,
+ in_sosi_arr => in_sosi_arr,
+ in_stop => stop,
+ out_sosi => out_sosi,
+ out_adr => out_adr,
+ out_bsn_adr => inp_bsn_adr,
+ out_data_stopped => data_stopped
+ );
-- functions as a fifo buffer for input data into the sdram stick. also manages input to sdram stick.
u_io_ddr : entity io_ddr_lib.io_ddr
- generic map(
- g_sim_model => g_sim_model,
- g_technology => g_technology,
- g_tech_ddr => g_tech_ddr,
- g_cross_domain_dvr_ctlr => false,
- g_wr_data_w => c_io_ddr_data_w,
- g_wr_fifo_depth => c_wr_fifo_depth,
- g_rd_fifo_depth => c_rd_fifo_depth,
- g_rd_data_w => c_io_ddr_data_w,
- g_wr_flush_mode => "VAL",
- g_wr_flush_use_channel => false,
- g_wr_flush_start_channel => 0,
- g_wr_flush_nof_channels => 1
+ generic map(
+ g_sim_model => g_sim_model,
+ g_technology => g_technology,
+ g_tech_ddr => g_tech_ddr,
+ g_cross_domain_dvr_ctlr => false,
+ g_wr_data_w => c_io_ddr_data_w,
+ g_wr_fifo_depth => c_wr_fifo_depth,
+ g_rd_fifo_depth => c_rd_fifo_depth,
+ g_rd_data_w => c_io_ddr_data_w,
+ g_wr_flush_mode => "VAL",
+ g_wr_flush_use_channel => false,
+ g_wr_flush_start_channel => 0,
+ g_wr_flush_nof_channels => 1
)
port map(
- -- DDR reference clock
- ctlr_ref_clk => ctlr_ref_clk,
- ctlr_ref_rst => ctlr_ref_rst,
+ -- DDR reference clock
+ ctlr_ref_clk => ctlr_ref_clk,
+ ctlr_ref_rst => ctlr_ref_rst,
- -- DDR controller clock domain
- ctlr_clk_out => ctrl_clk,
- ctlr_rst_out => ctrl_rst,
+ -- DDR controller clock domain
+ ctlr_clk_out => ctrl_clk,
+ ctlr_rst_out => ctrl_rst,
- ctlr_clk_in => ctrl_clk,
- ctlr_rst_in => ctrl_rst,
+ ctlr_clk_in => ctrl_clk,
+ ctlr_rst_in => ctrl_rst,
- -- MM clock + reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ -- MM clock + reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
- state_vec => state_vec,
- ctlr_wr_flush_en_o => ctlr_wr_flush_en,
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+ state_vec => state_vec,
+ ctlr_wr_flush_en_o => ctlr_wr_flush_en,
- -- Driver clock domain
- dvr_clk => clk,
- dvr_rst => rst,
+ -- Driver clock domain
+ dvr_clk => clk,
+ dvr_rst => rst,
- dvr_miso => dvr_miso,
- dvr_mosi => dvr_mosi,
+ dvr_miso => dvr_miso,
+ dvr_mosi => dvr_mosi,
- -- Write FIFO clock domain
- wr_clk => clk,
- wr_rst => rst,
+ -- Write FIFO clock domain
+ wr_clk => clk,
+ wr_rst => rst,
- wr_fifo_usedw => wr_fifo_usedw,
- wr_sosi => wr_sosi,
- wr_siso => open,
+ wr_fifo_usedw => wr_fifo_usedw,
+ wr_sosi => wr_sosi,
+ wr_siso => open,
- -- Read FIFO clock domain
- rd_clk => clk,
- rd_rst => rst,
+ -- Read FIFO clock domain
+ rd_clk => clk,
+ rd_rst => rst,
- rd_fifo_usedw => rd_fifo_usedw,
- rd_sosi => rd_sosi,
- rd_siso => rd_siso,
+ rd_fifo_usedw => rd_fifo_usedw,
+ rd_sosi => rd_sosi,
+ rd_siso => rd_siso,
- term_ctrl_out => term_ctrl_out,
- term_ctrl_in => term_ctrl_in,
+ term_ctrl_out => term_ctrl_out,
+ term_ctrl_in => term_ctrl_in,
- -- DDR3 PHY external interface
- phy3_in => phy3_in,
- phy3_io => phy3_io,
- phy3_ou => phy3_ou,
+ -- DDR3 PHY external interface
+ phy3_in => phy3_in,
+ phy3_io => phy3_io,
+ phy3_ou => phy3_ou,
- -- DDR4 PHY external interface
- phy4_in => phy4_in,
- phy4_io => phy4_io,
- phy4_ou => phy4_ou
- );
+ -- DDR4 PHY external interface
+ phy4_in => phy4_in,
+ phy4_io => phy4_io,
+ phy4_ou => phy4_ou
+ );
-- reading ddr memory
u_ddrctrl_output : entity work.ddrctrl_output
- generic map(
- g_technology => g_technology,
- g_tech_ddr => g_tech_ddr,
- g_sim_model => g_sim_model,
- g_in_data_w => c_io_ddr_data_w,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_block_size => g_block_size,
- g_bim => c_bim
- )
- port map(
- clk => clk,
- rst => rst,
-
- in_sosi => rd_sosi,
- in_bsn => bsn_co,
-
- out_sosi_arr => out_sosi_arr,
- out_siso => out_siso,
- out_ready => rd_ready
- );
+ generic map(
+ g_technology => g_technology,
+ g_tech_ddr => g_tech_ddr,
+ g_sim_model => g_sim_model,
+ g_in_data_w => c_io_ddr_data_w,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_block_size => g_block_size,
+ g_bim => c_bim
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+
+ in_sosi => rd_sosi,
+ in_bsn => bsn_co,
+
+ out_sosi_arr => out_sosi_arr,
+ out_siso => out_siso,
+ out_ready => rd_ready
+ );
-- controller of ddrctrl
u_ddrctrl_controller : entity work.ddrctrl_controller
- generic map(
- g_tech_ddr => g_tech_ddr,
- g_stop_percentage => g_stop_percentage,
- g_nof_streams => g_nof_streams,
- g_out_data_w => g_data_w,
- g_wr_data_w => c_io_ddr_data_w,
- g_rd_fifo_depth => c_rd_fifo_depth,
- g_rd_data_w => c_io_ddr_data_w,
- g_block_size => g_block_size,
- g_wr_fifo_uw_w => c_wr_fifo_uw_w,
- g_rd_fifo_uw_w => c_rd_fifo_uw_w,
- g_max_adr => c_nof_adr,
- g_burstsize => c_burstsize,
- g_last_burstsize => c_last_burstsize,
- g_adr_per_b => c_adr_per_b,
- g_bim => c_bim
- )
- port map(
- clk => clk,
- rst => rst,
-
- -- ddrctrl_input
- inp_of => out_of,
- inp_sosi => out_sosi,
- inp_adr => out_adr,
- inp_bsn_adr => inp_bsn_adr,
- inp_data_stopped => data_stopped,
- rst_ddrctrl_input_ac => rst_ddrctrl_input_ac,
-
- -- io_ddr
- dvr_mosi => dvr_mosi,
- dvr_miso => dvr_miso,
- wr_sosi => wr_sosi,
- wr_siso => c_dp_siso_rdy,
- wr_fifo_usedw => wr_fifo_usedw,
- rd_fifo_usedw => rd_fifo_usedw,
- ctlr_wr_flush_en => ctlr_wr_flush_en,
- flush_state => state_vec,
-
- -- ddrctrl_output
- outp_bsn => bsn_co,
-
- -- ddrctrl_controller
- stop_in => stop_in,
- stop_out => stop,
- ddrctrl_ctrl_state => ddrctrl_ctrl_state_local
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr,
+ g_stop_percentage => g_stop_percentage,
+ g_nof_streams => g_nof_streams,
+ g_out_data_w => g_data_w,
+ g_wr_data_w => c_io_ddr_data_w,
+ g_rd_fifo_depth => c_rd_fifo_depth,
+ g_rd_data_w => c_io_ddr_data_w,
+ g_block_size => g_block_size,
+ g_wr_fifo_uw_w => c_wr_fifo_uw_w,
+ g_rd_fifo_uw_w => c_rd_fifo_uw_w,
+ g_max_adr => c_nof_adr,
+ g_burstsize => c_burstsize,
+ g_last_burstsize => c_last_burstsize,
+ g_adr_per_b => c_adr_per_b,
+ g_bim => c_bim
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+
+ -- ddrctrl_input
+ inp_of => out_of,
+ inp_sosi => out_sosi,
+ inp_adr => out_adr,
+ inp_bsn_adr => inp_bsn_adr,
+ inp_data_stopped => data_stopped,
+ rst_ddrctrl_input_ac => rst_ddrctrl_input_ac,
+
+ -- io_ddr
+ dvr_mosi => dvr_mosi,
+ dvr_miso => dvr_miso,
+ wr_sosi => wr_sosi,
+ wr_siso => c_dp_siso_rdy,
+ wr_fifo_usedw => wr_fifo_usedw,
+ rd_fifo_usedw => rd_fifo_usedw,
+ ctlr_wr_flush_en => ctlr_wr_flush_en,
+ flush_state => state_vec,
+
+ -- ddrctrl_output
+ outp_bsn => bsn_co,
+
+ -- ddrctrl_controller
+ stop_in => stop_in,
+ stop_out => stop,
+ ddrctrl_ctrl_state => ddrctrl_ctrl_state_local
+ );
end str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 69b4c10a71..8b073543c5 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -28,12 +28,12 @@
--
library IEEE, dp_lib, common_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity ddrctrl_controller is
generic (
@@ -124,34 +124,34 @@ architecture rtl of ddrctrl_controller is
-- record for readability
type t_reg is record
- -- state of program
- state : t_state;
- started : std_logic;
-
- -- stopping flush
- timer : natural;
-
- -- stopping signals
- ready_for_set_stop : std_logic;
- stop_adr : std_logic_vector(c_adr_w - 1 downto 0);
- last_adr_to_write_to : std_logic_vector(c_adr_w - 1 downto 0);
- stop_burstsize : natural;
- stopped : std_logic;
- rst_ddrctrl_input_ac : std_logic;
-
- -- writing signals
- wr_burst_en : std_logic;
- wr_bursts_ready : natural;
-
- -- reading signals
- outp_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
- read_adr : natural;
- rd_burst_en : std_logic;
-
- -- output
- dvr_mosi : t_mem_ctlr_mosi;
- wr_sosi : t_dp_sosi;
- ddrctrl_ctrl_state : std_logic_vector(32 - 1 downto 0);
+ -- state of program
+ state : t_state;
+ started : std_logic;
+
+ -- stopping flush
+ timer : natural;
+
+ -- stopping signals
+ ready_for_set_stop : std_logic;
+ stop_adr : std_logic_vector(c_adr_w - 1 downto 0);
+ last_adr_to_write_to : std_logic_vector(c_adr_w - 1 downto 0);
+ stop_burstsize : natural;
+ stopped : std_logic;
+ rst_ddrctrl_input_ac : std_logic;
+
+ -- writing signals
+ wr_burst_en : std_logic;
+ wr_bursts_ready : natural;
+
+ -- reading signals
+ outp_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ read_adr : natural;
+ rd_burst_en : std_logic;
+
+ -- output
+ dvr_mosi : t_mem_ctlr_mosi;
+ wr_sosi : t_dp_sosi;
+ ddrctrl_ctrl_state : std_logic_vector(32 - 1 downto 0);
end record;
constant c_t_reg_init : t_reg := (RESET, '0', 4, '0', TO_UVEC(g_max_adr, c_adr_w), (others => '0'), 0, '1', '1', '0', 0, (others => '0'), 0, '1', c_mem_ctlr_mosi_rst, c_dp_sosi_init, (others => '0'));
@@ -173,276 +173,276 @@ begin
--v.ddrctrl_ctrl_state(c_high_adr_ndx DOWNTO c_low_adr_ndx) := TO_UVEC(inp_adr, 32)(c_adr_ndx_w-1 DOWNTO 0);
case q_reg.state is
- when RESET =>
- v := c_t_reg_init;
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(0, c_state_ndx_w);
-
- if rst = '0' and wr_siso.ready = '1' then
- v.state := STOP_FLUSH;
- v.timer := 0;
- end if;
-
- when STOP_FLUSH =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(1, c_state_ndx_w);
- v.wr_sosi.valid := '0';
- if flush_state = "10" then
- v.dvr_mosi.burstbegin := '1';
+ when RESET =>
+ v := c_t_reg_init;
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(0, c_state_ndx_w);
+
+ if rst = '0' and wr_siso.ready = '1' then
+ v.state := STOP_FLUSH;
+ v.timer := 0;
+ end if;
+
+ when STOP_FLUSH =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(1, c_state_ndx_w);
+ v.wr_sosi.valid := '0';
+ if flush_state = "10" then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
+ v.dvr_mosi.wr := '1';
+ elsif flush_state = "11" and q_reg.timer = 0 then
+ v.wr_sosi.valid := '1';
+ v.timer := 127;
+ end if;
+
+ if q_reg.timer > 0 and rst = '0' then
+ v.timer := q_reg.timer - 1;
+ end if;
+
+ if flush_state = "01" then
+ v.state := WAIT_FOR_SOP;
+ v.stopped := '0';
+ end if;
+
+ when STOP_READING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(2, c_state_ndx_w);
+ -- this is the last read burst, this make sure every data containing word in the memory has been read.
+ if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
+ v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.stopped := '0';
+ v.wr_sosi.valid := '1';
+ v.state := WAIT_FOR_SOP;
+ v.wr_burst_en := '1';
+ v.rst_ddrctrl_input_ac := '1';
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+
+ if dvr_miso.done = '0' then
+ v.rd_burst_en := '1';
+ end if;
+
+ when WAIT_FOR_SOP =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(3, c_state_ndx_w);
+ v.dvr_mosi.burstbegin := '0';
v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
v.dvr_mosi.wr := '1';
- elsif flush_state = "11" and q_reg.timer = 0 then
- v.wr_sosi.valid := '1';
- v.timer := 127;
- end if;
-
- if q_reg.timer > 0 and rst = '0' then
- v.timer := q_reg.timer - 1;
- end if;
-
- if flush_state = "01" then
- v.state := WAIT_FOR_SOP;
- v.stopped := '0';
- end if;
-
- when STOP_READING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(2, c_state_ndx_w);
- -- this is the last read burst, this make sure every data containing word in the memory has been read.
- if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
- v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.stopped := '0';
- v.wr_sosi.valid := '1';
- v.state := WAIT_FOR_SOP;
- v.wr_burst_en := '1';
- v.rst_ddrctrl_input_ac := '1';
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
-
- if dvr_miso.done = '0' then
- v.rd_burst_en := '1';
- end if;
-
- when WAIT_FOR_SOP =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(3, c_state_ndx_w);
- v.dvr_mosi.burstbegin := '0';
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
- v.rst_ddrctrl_input_ac := '0';
- if q_reg.started = '0' and inp_sosi.eop = '1' then
- v.wr_sosi.valid := '0';
- elsif inp_sosi.sop = '1' then
- v.state := WRITING;
- else
- v.wr_sosi.valid := '0';
- end if;
-
- when WRITING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(4, c_state_ndx_w);
- -- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if q_reg.wr_bursts_ready >= 1 and dvr_miso.done = '1' and q_reg.wr_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.rd := '0';
+ v.rst_ddrctrl_input_ac := '0';
+ if q_reg.started = '0' and inp_sosi.eop = '1' then
+ v.wr_sosi.valid := '0';
+ elsif inp_sosi.sop = '1' then
+ v.state := WRITING;
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.wr_sosi.valid := '0';
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
-
- if stop_in = '1' then
- v.ready_for_set_stop := '1';
- end if;
-
- if q_reg.ready_for_set_stop = '1' and inp_sosi.eop = '1' and stop_in = '0' then
- v.state := SET_STOP;
- elsif q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
- v.state := STOP_WRITING;
- end if;
-
- when SET_STOP =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(5, c_state_ndx_w);
- -- this state sets a stop address dependend on the g_stop_percentage.
- if inp_adr - c_pof_ma >= 0 then
- v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr - c_pof_ma, c_adr_w);
- else
- v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr + g_max_adr - c_pof_ma, c_adr_w);
- end if;
- v.ready_for_set_stop := '0';
- if v.stop_adr(c_adr_w - 1 downto 0) = c_stop_adr_zeros(c_adr_w - 1 downto 0) then
- v.last_adr_to_write_to(c_adr_w - 1 downto 0) := TO_UVEC(g_max_adr - g_last_burstsize, c_adr_w);
- else
- v.last_adr_to_write_to(c_adr_w - 1 downto c_bitshift_w) := v.stop_adr(c_adr_w - 1 downto c_bitshift_w);
- end if;
- v.last_adr_to_write_to(c_bitshift_w - 1 downto 0) := (others => '0');
- v.stop_burstsize := TO_UINT(INCR_UVEC(INCR_UVEC(v.stop_adr(c_adr_w - 1 downto 0), -1 * TO_UINT(v.last_adr_to_write_to)),1));
-
- -- still a write cyle
- -- if adr mod g_burstsize = 0
- -- this makes sure that only ones every 64 writes a writeburst is started.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
- if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+
+ when WRITING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(4, c_state_ndx_w);
+ -- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if q_reg.wr_bursts_ready >= 1 and dvr_miso.done = '1' and q_reg.wr_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
+ end if;
+
+ if stop_in = '1' then
+ v.ready_for_set_stop := '1';
+ end if;
+
+ if q_reg.ready_for_set_stop = '1' and inp_sosi.eop = '1' and stop_in = '0' then
+ v.state := SET_STOP;
+ elsif q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
+ v.state := STOP_WRITING;
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
- v.state := STOP_WRITING;
- else
- v.state := WRITING;
- end if;
-
- when STOP_WRITING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(6, c_state_ndx_w);
- -- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
- v.wr_sosi.valid := '0';
- v.dvr_mosi.burstbegin := '0';
- v.stopped := '1';
- v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
-
- -- still receiving write data.
- v.wr_bursts_ready := TO_UINT(INCR_UVEC(wr_fifo_usedw, 2)(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
- if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * q_reg.wr_bursts_ready - 1), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+
+ when SET_STOP =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(5, c_state_ndx_w);
+ -- this state sets a stop address dependend on the g_stop_percentage.
+ if inp_adr - c_pof_ma >= 0 then
+ v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr - c_pof_ma, c_adr_w);
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr + g_max_adr - c_pof_ma, c_adr_w);
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if dvr_miso.done = '1' and q_reg.dvr_mosi.burstbegin = '0' and q_reg.wr_burst_en = '0' and q_reg.wr_bursts_ready = 0 and inp_data_stopped = '1' and TO_UINT(wr_fifo_usedw) <= q_reg.stop_burstsize then
- v.state := LAST_WRITE_BURST;
- end if;
-
- when LAST_WRITE_BURST =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(7, c_state_ndx_w);
- -- this state stops the writing by generatign one last write burst which empties wr_fifo.
- v.wr_sosi.valid := '0';
- if dvr_miso.done = '1' then
- if TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) >= g_max_adr then
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(0, c_adr_w);
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.ready_for_set_stop := '0';
+ if v.stop_adr(c_adr_w - 1 downto 0) = c_stop_adr_zeros(c_adr_w - 1 downto 0) then
+ v.last_adr_to_write_to(c_adr_w - 1 downto 0) := TO_UVEC(g_max_adr - g_last_burstsize, c_adr_w);
else
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
- v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.last_adr_to_write_to(c_adr_w - 1 downto c_bitshift_w) := v.stop_adr(c_adr_w - 1 downto c_bitshift_w);
+ end if;
+ v.last_adr_to_write_to(c_bitshift_w - 1 downto 0) := (others => '0');
+ v.stop_burstsize := TO_UINT(INCR_UVEC(INCR_UVEC(v.stop_adr(c_adr_w - 1 downto 0), -1 * TO_UINT(v.last_adr_to_write_to)),1));
+
+ -- still a write cyle
+ -- if adr mod g_burstsize = 0
+ -- this makes sure that only ones every 64 writes a writeburst is started.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
end if;
- v.dvr_mosi.burstbegin := '1';
- v.state := START_READING;
- v.rd_burst_en := '1';
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- when START_READING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(8, c_state_ndx_w);
- -- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
- v.dvr_mosi.burstbegin := '0';
- v.outp_bsn := INCR_UVEC(inp_sosi.bsn, -1 * g_bim);
- v.wr_sosi.valid := '0';
-
- if dvr_miso.done = '1' and v.rd_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
- if TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + q_reg.stop_burstsize >= g_max_adr then
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(0, c_adr_w);
- v.read_adr := g_burstsize;
+ if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
else
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize - q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := INCR_UVEC(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0), q_reg.stop_burstsize);
- v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + g_burstsize;
+ v.dvr_mosi.burstbegin := '0';
end if;
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
- v.rd_burst_en := '0';
- end if;
-
- -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
- if dvr_miso.done = '0' and q_reg.rd_burst_en = '0' then
- v.rd_burst_en := '1';
- v.state := READING;
- end if;
-
- when READING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(9, c_state_ndx_w);
- v.wr_sosi.valid := '0';
- -- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
- if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
- v.dvr_mosi.burstbegin := '1';
- v.rd_burst_en := '0';
- if q_reg.read_adr > g_max_adr - g_burstsize then
- v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
- v.read_adr := 0;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
+ v.state := STOP_WRITING;
else
- v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
- v.read_adr := q_reg.read_adr + g_burstsize;
+ v.state := WRITING;
end if;
- else
+
+ when STOP_WRITING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(6, c_state_ndx_w);
+ -- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
+ v.wr_sosi.valid := '0';
v.dvr_mosi.burstbegin := '0';
- end if;
+ v.stopped := '1';
+ v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
+
+ -- still receiving write data.
+ v.wr_bursts_ready := TO_UINT(INCR_UVEC(wr_fifo_usedw, 2)(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
+ end if;
+ if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * q_reg.wr_bursts_ready - 1), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if dvr_miso.done = '1' and q_reg.dvr_mosi.burstbegin = '0' and q_reg.wr_burst_en = '0' and q_reg.wr_bursts_ready = 0 and inp_data_stopped = '1' and TO_UINT(wr_fifo_usedw) <= q_reg.stop_burstsize then
+ v.state := LAST_WRITE_BURST;
+ end if;
+
+ when LAST_WRITE_BURST =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(7, c_state_ndx_w);
+ -- this state stops the writing by generatign one last write burst which empties wr_fifo.
+ v.wr_sosi.valid := '0';
+ if dvr_miso.done = '1' then
+ if TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) >= g_max_adr then
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(0, c_adr_w);
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
+ v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ end if;
+ v.dvr_mosi.burstbegin := '1';
+ v.state := START_READING;
+ v.rd_burst_en := '1';
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ when START_READING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(8, c_state_ndx_w);
+ -- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
+ v.dvr_mosi.burstbegin := '0';
+ v.outp_bsn := INCR_UVEC(inp_sosi.bsn, -1 * g_bim);
+ v.wr_sosi.valid := '0';
+
+ if dvr_miso.done = '1' and v.rd_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
+ if TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + q_reg.stop_burstsize >= g_max_adr then
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(0, c_adr_w);
+ v.read_adr := g_burstsize;
+ else
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize - q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := INCR_UVEC(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0), q_reg.stop_burstsize);
+ v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + g_burstsize;
+ end if;
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.rd_burst_en := '0';
+ end if;
+
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ if dvr_miso.done = '0' and q_reg.rd_burst_en = '0' then
+ v.rd_burst_en := '1';
+ v.state := READING;
+ end if;
+
+ when READING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(9, c_state_ndx_w);
+ v.wr_sosi.valid := '0';
+ -- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
+ if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.dvr_mosi.burstbegin := '1';
+ v.rd_burst_en := '0';
+ if q_reg.read_adr > g_max_adr - g_burstsize then
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := 0;
+ else
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := q_reg.read_adr + g_burstsize;
+ end if;
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
- -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
- if dvr_miso.done = '0' then
- v.rd_burst_en := '1';
- end if;
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ if dvr_miso.done = '0' then
+ v.rd_burst_en := '1';
+ end if;
- -- goes to STOP_reading when this read burst was from the burstblock before q_reg.stop_adr
- if q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0) = TO_UVEC(q_reg.read_adr, c_adr_w) then
- v.state := STOP_READING;
- end if;
+ -- goes to STOP_reading when this read burst was from the burstblock before q_reg.stop_adr
+ if q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0) = TO_UVEC(q_reg.read_adr, c_adr_w) then
+ v.state := STOP_READING;
+ end if;
end case;
if rst = '1' then
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
index a0f0eea2bd..984eb5a6b6 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
@@ -33,13 +33,13 @@
-- The maximum value of the address is determend by g_tech_ddr.
library IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_input is
generic (
@@ -79,47 +79,47 @@ begin
-- makes one data vector out of all the data from the t_dp_sosi_arr
u_ddrctrl_input_pack : entity work.ddrctrl_input_pack
- generic map(
- g_nof_streams => g_nof_streams, -- number of input streams
- g_data_w => g_data_w -- data with of input data vectors
- )
- port map(
- in_sosi_arr => in_sosi_arr, -- input data
- out_sosi => sosi_p_rp -- output data
- );
+ generic map(
+ g_nof_streams => g_nof_streams, -- number of input streams
+ g_data_w => g_data_w -- data with of input data vectors
+ )
+ port map(
+ in_sosi_arr => in_sosi_arr, -- input data
+ out_sosi => sosi_p_rp -- output data
+ );
-- resizes the input data vector so that the output data vector can be stored into the ddr memory
u_ddrctrl_input_repack : entity work.ddrctrl_input_repack
- generic map(
- g_tech_ddr => g_tech_ddr, -- type of memory
- g_in_data_w => c_out_data_w, -- the input data with
- g_bim => g_bim,
- g_of_pb => g_of_pb,
- g_block_size => g_block_size
- )
- port map(
- clk => clk,
- rst => rst,
- in_sosi => sosi_p_rp, -- input data
- in_stop => in_stop,
- out_sosi => sosi_rp_ac, -- output data
- out_data_stopped => data_stopped_rp_ac
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr, -- type of memory
+ g_in_data_w => c_out_data_w, -- the input data with
+ g_bim => g_bim,
+ g_of_pb => g_of_pb,
+ g_block_size => g_block_size
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+ in_sosi => sosi_p_rp, -- input data
+ in_stop => in_stop,
+ out_sosi => sosi_rp_ac, -- output data
+ out_data_stopped => data_stopped_rp_ac
+ );
-- creates address by counting input valids
u_ddrctrl_input_address_counter : entity work.ddrctrl_input_address_counter
- generic map(
- g_tech_ddr => g_tech_ddr, -- type of memory
- g_max_adr => g_max_adr
- )
- port map(
- clk => clk,
- rst => rst_ddrctrl_input_ac,
- in_sosi => sosi_rp_ac, -- input data
- in_data_stopped => data_stopped_rp_ac,
- out_sosi => out_sosi, -- output data
- out_adr => adr,
- out_bsn_adr => out_bsn_adr,
- out_data_stopped => out_data_stopped
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr, -- type of memory
+ g_max_adr => g_max_adr
+ )
+ port map(
+ clk => clk,
+ rst => rst_ddrctrl_input_ac,
+ in_sosi => sosi_rp_ac, -- input data
+ in_data_stopped => data_stopped_rp_ac,
+ out_sosi => out_sosi, -- output data
+ out_adr => adr,
+ out_bsn_adr => out_bsn_adr,
+ out_data_stopped => out_data_stopped
+ );
end str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
index d5e7bd5d7f..a341325be4 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
@@ -30,13 +30,13 @@
-- The maximum value of the address is determend by g_tech_ddr.
library IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_input_address_counter is
generic (
@@ -64,14 +64,14 @@ architecture rtl of ddrctrl_input_address_counter is
-- record for readability
type t_reg is record
- state : t_state;
- bsn_passed : std_logic;
- out_sosi : t_dp_sosi;
- out_bsn_adr : natural;
- out_data_stopped : std_logic;
- s_in_sosi : t_dp_sosi;
- s_in_data_stopped : std_logic;
- s_adr : natural;
+ state : t_state;
+ bsn_passed : std_logic;
+ out_sosi : t_dp_sosi;
+ out_bsn_adr : natural;
+ out_data_stopped : std_logic;
+ s_in_sosi : t_dp_sosi;
+ s_in_data_stopped : std_logic;
+ s_adr : natural;
end record;
constant c_t_reg_init : t_reg := (RESET, '0', c_dp_sosi_init, 0, '0', c_dp_sosi_init, '0', 0);
@@ -85,7 +85,7 @@ begin
-- Increments the address each time in_sosi.valid = '1', if address = g_max_adr the address is reset to 0.
p_adr : process(rst, in_sosi, in_data_stopped, q_reg)
- variable v : t_reg;
+ variable v : t_reg;
begin
v := q_reg;
@@ -96,32 +96,32 @@ begin
v.s_in_data_stopped := in_data_stopped;
case q_reg.state is
- when RESET =>
- v := c_t_reg_init;
+ when RESET =>
+ v := c_t_reg_init;
- if q_reg.s_in_sosi.sop = '1' then
- v.out_bsn_adr := v.s_adr;
- end if;
+ if q_reg.s_in_sosi.sop = '1' then
+ v.out_bsn_adr := v.s_adr;
+ end if;
- when COUNTING =>
- v.s_adr := q_reg.s_adr + 1;
+ when COUNTING =>
+ v.s_adr := q_reg.s_adr + 1;
- if q_reg.s_in_sosi.sop = '1' then
- v.out_bsn_adr := v.s_adr;
- end if;
+ if q_reg.s_in_sosi.sop = '1' then
+ v.out_bsn_adr := v.s_adr;
+ end if;
- when MAX =>
- v.s_adr := 0;
+ when MAX =>
+ v.s_adr := 0;
- if q_reg.s_in_sosi.sop = '1' then
- v.out_bsn_adr := v.s_adr;
- end if;
+ if q_reg.s_in_sosi.sop = '1' then
+ v.out_bsn_adr := v.s_adr;
+ end if;
- when IDLE =>
- -- after a reset wait for a sop so the memory will be filled with whole blocks.
- if in_sosi.sop = '1' then
- v.bsn_passed := '1';
- end if;
+ when IDLE =>
+ -- after a reset wait for a sop so the memory will be filled with whole blocks.
+ if in_sosi.sop = '1' then
+ v.bsn_passed := '1';
+ end if;
end case;
if rst = '1' then
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
index 4895077bd3..3fa17620bd 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
@@ -28,8 +28,8 @@
-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_input_pack is
generic (
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
index 2c232e370e..8696d7ffb9 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
@@ -30,9 +30,9 @@
-- The output vector must be larger than the input vector.
library IEEE, dp_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity ddrctrl_input_repack is
generic (
@@ -63,16 +63,16 @@ architecture rtl of ddrctrl_input_repack is
-- record for readability
type t_reg is record
- state : t_state; -- the state the process is currently in;
- c_v : std_logic_vector(k_c_v_w - 1 downto 0); -- the vector that stores the input data until the data is put into the output data vector
- c_v_count : natural; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
- q_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
- q_sop : std_logic;
- s_input_cnt : natural;
- out_of : natural;
- out_data_count : std_logic; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
- out_sosi : t_dp_sosi; -- this is the sosi stream that contains the data
- out_data_stopped : std_logic; -- this signal is '1' when there is no more data comming form ddrctrl_input_pack
+ state : t_state; -- the state the process is currently in;
+ c_v : std_logic_vector(k_c_v_w - 1 downto 0); -- the vector that stores the input data until the data is put into the output data vector
+ c_v_count : natural; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
+ q_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ q_sop : std_logic;
+ s_input_cnt : natural;
+ out_of : natural;
+ out_data_count : std_logic; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
+ out_sosi : t_dp_sosi; -- this is the sosi stream that contains the data
+ out_data_stopped : std_logic; -- this signal is '1' when there is no more data comming form ddrctrl_input_pack
end record;
constant c_t_reg_init : t_reg := (RESET, (others => '0'), 0, (others => '0'), '0', 0, 0, '0', c_dp_sosi_init, '0');
@@ -91,69 +91,69 @@ begin
v := q_reg;
case q_reg.state is
- when FILL_VECTOR => -- if the input data doesn't exceeds the output data vector width
- v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
- v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
- v.out_sosi.valid := '0'; -- out_sosi.valid 0
- v.s_input_cnt := q_reg.s_input_cnt + 1;
- v.out_sosi.sop := '0';
- v.out_sosi.eop := '0';
- v.out_data_stopped := '0';
-
- when FIRST_OUTPUT => -- if the input data exceeds output data vector width but not the c_v width
- v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
- v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
- v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(c_out_data_w - 1 downto 0); -- fill out_sosi.data with 1st part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- v.out_data_count := '1'; -- increase the counter of out_sosi.data with 1
- v.s_input_cnt := q_reg.s_input_cnt + 1;
- v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := q_reg.q_bsn(c_dp_stream_bsn_w - 1 downto 0);
- v.out_sosi.sop := q_reg.q_sop;
- v.out_sosi.eop := '0';
- v.out_data_stopped := '0';
-
- when OVERFLOW_OUTPUT => -- if the input data exceeds the output data vector width and the c_v width
- v.out_of := q_reg.out_of + (g_in_data_w * (q_reg.c_v_count + 1)) - (c_out_data_w * 2); -- check how much overflow there is and safe it in out_of
- v.c_v(k_c_v_w - 1 downto k_c_v_w - (g_in_data_w - v.out_of)) := in_sosi.data(g_in_data_w - v.out_of - 1 downto 0); -- fill the rest of c_v untill the end
- v.c_v(v.out_of - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto g_in_data_w - v.out_of); -- fill the start of c_v untill the out_of
- v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(k_c_v_w - 1 downto c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- v.c_v_count := 0; -- reset counter
- v.out_data_count := '0'; -- reset counter
- v.s_input_cnt := q_reg.s_input_cnt + 1;
- v.q_sop := '0';
- v.out_sosi.sop := '0';
- v.out_sosi.eop := '0';
- v.out_data_stopped := '0';
-
- when BSN =>
-
- v.c_v(k_c_v_w - 1 downto ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of)) := (others => '0');
- v.out_of := 0;
- if ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of < c_out_data_w * 1) then
+ when FILL_VECTOR => -- if the input data doesn't exceeds the output data vector width
+ v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
+ v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
+ v.out_sosi.valid := '0'; -- out_sosi.valid 0
+ v.s_input_cnt := q_reg.s_input_cnt + 1;
+ v.out_sosi.sop := '0';
+ v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
+
+ when FIRST_OUTPUT => -- if the input data exceeds output data vector width but not the c_v width
+ v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
+ v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(c_out_data_w - 1 downto 0); -- fill out_sosi.data with 1st part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- else
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ v.out_data_count := '1'; -- increase the counter of out_sosi.data with 1
+ v.s_input_cnt := q_reg.s_input_cnt + 1;
+ v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := q_reg.q_bsn(c_dp_stream_bsn_w - 1 downto 0);
+ v.out_sosi.sop := q_reg.q_sop;
+ v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
+
+ when OVERFLOW_OUTPUT => -- if the input data exceeds the output data vector width and the c_v width
+ v.out_of := q_reg.out_of + (g_in_data_w * (q_reg.c_v_count + 1)) - (c_out_data_w * 2); -- check how much overflow there is and safe it in out_of
+ v.c_v(k_c_v_w - 1 downto k_c_v_w - (g_in_data_w - v.out_of)) := in_sosi.data(g_in_data_w - v.out_of - 1 downto 0); -- fill the rest of c_v untill the end
+ v.c_v(v.out_of - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto g_in_data_w - v.out_of); -- fill the start of c_v untill the out_of
v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(k_c_v_w - 1 downto c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- end if;
-
- -- BSN_INPUT
- v.q_bsn := in_sosi.bsn; -- a bsn number is saved when the bsn changes
- v.q_sop := '1'; -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
- v.c_v(g_in_data_w - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
- v.c_v_count := 1; -- increase the counter of c_v with 1
- v.out_data_count := '0';
- v.out_sosi.eop := '1';
-
- when RESET =>
- v := c_t_reg_init;
- v.q_bsn(c_dp_stream_bsn_w - 1 downto 0) := in_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0);
-
- when STOP =>
- v.out_sosi.valid := '0';
- v.q_sop := '0';
- v.out_data_stopped := '1';
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ v.c_v_count := 0; -- reset counter
+ v.out_data_count := '0'; -- reset counter
+ v.s_input_cnt := q_reg.s_input_cnt + 1;
+ v.q_sop := '0';
+ v.out_sosi.sop := '0';
+ v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
+
+ when BSN =>
+
+ v.c_v(k_c_v_w - 1 downto ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of)) := (others => '0');
+ v.out_of := 0;
+ if ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of < c_out_data_w * 1) then
+ v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(c_out_data_w - 1 downto 0); -- fill out_sosi.data with 1st part of c_v
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ else
+ v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(k_c_v_w - 1 downto c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ end if;
+
+ -- BSN_INPUT
+ v.q_bsn := in_sosi.bsn; -- a bsn number is saved when the bsn changes
+ v.q_sop := '1'; -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
+ v.c_v(g_in_data_w - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
+ v.c_v_count := 1; -- increase the counter of c_v with 1
+ v.out_data_count := '0';
+ v.out_sosi.eop := '1';
+
+ when RESET =>
+ v := c_t_reg_init;
+ v.q_bsn(c_dp_stream_bsn_w - 1 downto 0) := in_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0);
+
+ when STOP =>
+ v.out_sosi.valid := '0';
+ v.q_sop := '0';
+ v.out_data_stopped := '1';
end case;
if rst = '1' then
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
index 69fee61b01..d2e7923982 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
@@ -30,13 +30,13 @@
-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
library IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_output is
generic (
@@ -70,77 +70,77 @@ architecture str of ddrctrl_output is
-- signals for connecting the components
signal sosi : t_dp_sosi := c_dp_sosi_init;
signal out_sosi : t_dp_sosi := c_dp_sosi_init;
--- SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init;
--- SIGNAL fifo_snk_in_sosi : t_dp_sosi := c_dp_sosi_init;
+ -- SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init;
+ -- SIGNAL fifo_snk_in_sosi : t_dp_sosi := c_dp_sosi_init;
signal q_out_siso : t_dp_siso := c_dp_siso_rst;
signal q_q_out_siso : t_dp_siso := c_dp_siso_rst;
signal unpack_state_off : std_logic := '0';
--- SIGNAL siso : t_dp_siso := c_dp_siso_rst;
--- SIGNAL fifo_src_out_sosi : t_dp_sosi := c_dp_sosi_init;
--- SIGNAL fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(c_fifo_size)-1 DOWNTO 0) := (OTHERS => '0');
+ -- SIGNAL siso : t_dp_siso := c_dp_siso_rst;
+ -- SIGNAL fifo_src_out_sosi : t_dp_sosi := c_dp_sosi_init;
+ -- SIGNAL fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(c_fifo_size)-1 DOWNTO 0) := (OTHERS => '0');
begin
-- makes one data vector out of all the data from the t_dp_sosi_arr
u_ddrctrl_output_unpack : entity work.ddrctrl_output_unpack
- generic map(
- g_tech_ddr => g_tech_ddr,
- g_in_data_w => g_in_data_w,
- g_out_data_w => c_out_data_w,
- g_block_size => g_block_size,
- g_bim => g_bim
- )
- port map(
- clk => clk,
- rst => rst,
- in_sosi => in_sosi, -- input data
- in_bsn => in_bsn,
- out_siso => out_siso,
- out_sosi => out_sosi, -- output data
- out_ready => out_ready,
- state_off => unpack_state_off
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr,
+ g_in_data_w => g_in_data_w,
+ g_out_data_w => c_out_data_w,
+ g_block_size => g_block_size,
+ g_bim => g_bim
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+ in_sosi => in_sosi, -- input data
+ in_bsn => in_bsn,
+ out_siso => out_siso,
+ out_sosi => out_sosi, -- output data
+ out_ready => out_ready,
+ state_off => unpack_state_off
+ );
-- resizes the input data vector so that the output data vector can be stored into the ddr memory
u_ddrctrl_output_repack : entity work.ddrctrl_output_repack
- generic map(
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w
- )
- port map(
- in_sosi => sosi,
- out_sosi_arr => out_sosi_arr
- );
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w
+ )
+ port map(
+ in_sosi => sosi,
+ out_sosi_arr => out_sosi_arr
+ );
--- u_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
--- GENERIC MAP (
--- g_technology => g_technology,
--- g_wr_data_w => c_out_data_w,
--- g_rd_data_w => c_out_data_w,
--- g_use_ctrl => FALSE,
--- g_wr_fifo_size => c_fifo_size,
--- g_wr_fifo_af_margin => 0,
--- g_rd_fifo_rl => 0
--- )
--- PORT MAP (
--- wr_rst => rst,
--- wr_clk => clk,
--- rd_rst => rst,
--- rd_clk => clk,
---
--- snk_out => OPEN,
--- snk_in => fifo_snk_in_sosi,
---
--- wr_ful => OPEN,
--- wr_usedw => fifo_usedw,
--- rd_usedw => OPEN,
--- rd_emp => OPEN,
---
--- src_in => siso,
--- src_out => fifo_src_out_sosi
--- );
+ -- u_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
+ -- GENERIC MAP (
+ -- g_technology => g_technology,
+ -- g_wr_data_w => c_out_data_w,
+ -- g_rd_data_w => c_out_data_w,
+ -- g_use_ctrl => FALSE,
+ -- g_wr_fifo_size => c_fifo_size,
+ -- g_wr_fifo_af_margin => 0,
+ -- g_rd_fifo_rl => 0
+ -- )
+ -- PORT MAP (
+ -- wr_rst => rst,
+ -- wr_clk => clk,
+ -- rd_rst => rst,
+ -- rd_clk => clk,
+ --
+ -- snk_out => OPEN,
+ -- snk_in => fifo_snk_in_sosi,
+ --
+ -- wr_ful => OPEN,
+ -- wr_usedw => fifo_usedw,
+ -- rd_usedw => OPEN,
+ -- rd_emp => OPEN,
+ --
+ -- src_in => siso,
+ -- src_out => fifo_src_out_sosi
+ -- );
p_out_siso_ready : process(out_siso, clk, out_sosi, q_out_siso)
- variable sosi_valid : std_logic := '0';
+ variable sosi_valid : std_logic := '0';
begin
if out_siso.ready = '0' and not (q_out_siso.ready = out_siso.ready) then
sosi <= out_sosi;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
index 02b993e2c3..bfb462d1ea 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
@@ -29,9 +29,9 @@
-- The output vector must be larger than the input vector.
library IEEE, dp_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
entity ddrctrl_output_repack is
generic (
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
index b9e56f78f1..46c1d4c447 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
@@ -32,10 +32,10 @@
-- The output vector must be larger than the input vector.
library IEEE, dp_lib, tech_ddr_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
entity ddrctrl_output_unpack is
generic (
@@ -65,17 +65,17 @@ architecture rtl of ddrctrl_output_unpack is
-- record for readability
type t_reg is record
- state : t_state;
- a_of : natural;
- op_data_cnt : natural;
- delay_data : std_logic_vector(g_in_data_w - 1 downto 0);
- dd_fresh : std_logic;
- valid_data : std_logic;
- c_v : std_logic_vector(c_v_w - 1 downto 0);
- bsn_cnt : natural;
- out_sosi : t_dp_sosi;
- out_ready : std_logic;
- state_off : std_logic;
+ state : t_state;
+ a_of : natural;
+ op_data_cnt : natural;
+ delay_data : std_logic_vector(g_in_data_w - 1 downto 0);
+ dd_fresh : std_logic;
+ valid_data : std_logic;
+ c_v : std_logic_vector(c_v_w - 1 downto 0);
+ bsn_cnt : natural;
+ out_sosi : t_dp_sosi;
+ out_ready : std_logic;
+ state_off : std_logic;
end record;
constant c_t_reg_init : t_reg := (RESET, 0, 0, (others => '0'), '0', '0', (others => '0'), 0, c_dp_sosi_init, '0', '0');
@@ -95,92 +95,92 @@ begin
if out_siso.ready = '1' or q_reg.state = OFF or q_reg.state = IDLE or q_reg.state = RESET or rst = '1' then
case q_reg.state is
- when READING =>
- -- generating output from the data already present in c_v
- v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
- v.out_sosi.valid := '1';
- v.bsn_cnt := q_reg.bsn_cnt + 1;
- v.op_data_cnt := q_reg.op_data_cnt + 1;
-
- if q_reg.out_sosi.eop = '1' then
- v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
- v.out_sosi.eop := '0';
- v.out_sosi.sop := '1';
- v.bsn_cnt := 0;
- elsif q_reg.out_sosi.sop = '1' then
- v.out_sosi.sop := '0';
- end if;
-
- when OVER_HALF =>
- -- generating output data from c_v but past the halfway point of c_v so there needs to be new data added
- if q_reg.valid_data = '1' then
- -- generate output from the middle of c_v
+ when READING =>
+ -- generating output from the data already present in c_v
v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
v.out_sosi.valid := '1';
v.bsn_cnt := q_reg.bsn_cnt + 1;
+ v.op_data_cnt := q_reg.op_data_cnt + 1;
+
+ if q_reg.out_sosi.eop = '1' then
+ v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
+ v.out_sosi.eop := '0';
+ v.out_sosi.sop := '1';
+ v.bsn_cnt := 0;
+ elsif q_reg.out_sosi.sop = '1' then
+ v.out_sosi.sop := '0';
+ end if;
+
+ when OVER_HALF =>
+ -- generating output data from c_v but past the halfway point of c_v so there needs to be new data added
+ if q_reg.valid_data = '1' then
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt + 1;
+ -- put the second half of c_v into the first half of c_v
+ v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
+ v.valid_data := '0';
+ v.a_of := ((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of) - g_in_data_w;
+ v.op_data_cnt := 0;
+ elsif q_reg.valid_data = '0' then
+ -- there is no data ready.
+ end if;
+
+ if q_reg.out_sosi.sop = '1' then
+ v.out_sosi.sop := '0';
+ end if;
+
+ when FIRST_READ =>
-- put the second half of c_v into the first half of c_v
v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
v.valid_data := '0';
- v.a_of := ((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of) - g_in_data_w;
- v.op_data_cnt := 0;
- elsif q_reg.valid_data = '0' then
- -- there is no data ready.
- end if;
-
- if q_reg.out_sosi.sop = '1' then
- v.out_sosi.sop := '0';
- end if;
-
- when FIRST_READ =>
- -- put the second half of c_v into the first half of c_v
- v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
- v.valid_data := '0';
-
- -- fills the first half of c_v and generates output from it.
- v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
- v.out_sosi.data(g_out_data_w - 1 downto 0) := v.c_v(g_out_data_w - 1 downto 0);
- v.out_sosi.valid := '1';
- v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := in_bsn(c_dp_stream_bsn_w - 1 downto 0);
- v.out_sosi.sop := '1';
- v.out_sosi.eop := '0';
- v.bsn_cnt := 0;
- v.op_data_cnt := 1;
-
- when BSN =>
- -- generating output data from c_v but past the halfway point of c_v so there needs to be new data added also increases the bsn output
- v.out_sosi.valid := '0';
- if q_reg.valid_data = '1' then
- -- generate output from the middle of c_v
- v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
- v.out_sosi.valid := '1';
- v.bsn_cnt := q_reg.bsn_cnt + 1;
- -- put the second half of c_v into the first half of c_v
+
+ -- fills the first half of c_v and generates output from it.
v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
- v.valid_data := '0';
- v.op_data_cnt := 0;
- elsif (g_out_data_w * (v.op_data_cnt + 1)) + q_reg.a_of < g_in_data_w then
- -- generate output from the middle of c_v
- v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
+ v.out_sosi.data(g_out_data_w - 1 downto 0) := v.c_v(g_out_data_w - 1 downto 0);
v.out_sosi.valid := '1';
- v.bsn_cnt := q_reg.bsn_cnt + 1;
- end if;
-
- v.out_sosi.eop := '1';
- v.a_of := 0;
- v.bsn_cnt := q_reg.bsn_cnt + 1;
-
- when RESET =>
- v := c_t_reg_init;
-
- when IDLE =>
- -- the statemachine goes to Idle when its finished or when its waiting on other components.
- v.out_sosi.valid := '0';
-
- when OFF =>
- -- the stamachine has a state off so it knows when to go to first read, it can't go to first read from IDLE
- v.out_sosi := c_dp_sosi_init;
- v.bsn_cnt := 0;
- v.state_off := '1';
+ v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := in_bsn(c_dp_stream_bsn_w - 1 downto 0);
+ v.out_sosi.sop := '1';
+ v.out_sosi.eop := '0';
+ v.bsn_cnt := 0;
+ v.op_data_cnt := 1;
+
+ when BSN =>
+ -- generating output data from c_v but past the halfway point of c_v so there needs to be new data added also increases the bsn output
+ v.out_sosi.valid := '0';
+ if q_reg.valid_data = '1' then
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt + 1;
+ -- put the second half of c_v into the first half of c_v
+ v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
+ v.valid_data := '0';
+ v.op_data_cnt := 0;
+ elsif (g_out_data_w * (v.op_data_cnt + 1)) + q_reg.a_of < g_in_data_w then
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt + 1;
+ end if;
+
+ v.out_sosi.eop := '1';
+ v.a_of := 0;
+ v.bsn_cnt := q_reg.bsn_cnt + 1;
+
+ when RESET =>
+ v := c_t_reg_init;
+
+ when IDLE =>
+ -- the statemachine goes to Idle when its finished or when its waiting on other components.
+ v.out_sosi.valid := '0';
+
+ when OFF =>
+ -- the stamachine has a state off so it knows when to go to first read, it can't go to first read from IDLE
+ v.out_sosi := c_dp_sosi_init;
+ v.bsn_cnt := 0;
+ v.state_off := '1';
end case;
else
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 999afc3545..e95badb7ca 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -23,15 +23,15 @@
-- > run -a
library IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_ddrctrl is
generic (
@@ -154,7 +154,7 @@ begin
-- excecuting test
p_test : process
- variable out_siso_ready : natural := 0;
+ variable out_siso_ready : natural := 0;
begin
-- start the test
out_siso.ready <= '1';
@@ -250,31 +250,31 @@ begin
-- DUT
u_ddrctrl : entity work.ddrctrl
- generic map (
- g_tech_ddr => c_tech_ddr,
- g_sim_model => c_sim_model,
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_stop_percentage => g_stop_percentage,
- g_block_size => g_block_size
- )
- port map (
- clk => clk,
- rst => rst,
- ctlr_ref_clk => clk,
- ctlr_ref_rst => rst,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- in_sosi_arr => in_sosi_arr,
- stop_in => stop_in,
- out_sosi_arr => out_sosi_arr,
- out_siso => out_siso,
-
- --PHY
- phy3_io => phy3_io,
- phy3_ou => phy3_ou,
- phy4_io => phy4_io,
- phy4_ou => phy4_ou
- );
+ generic map (
+ g_tech_ddr => c_tech_ddr,
+ g_sim_model => c_sim_model,
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_stop_percentage => g_stop_percentage,
+ g_block_size => g_block_size
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ ctlr_ref_clk => clk,
+ ctlr_ref_rst => rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ in_sosi_arr => in_sosi_arr,
+ stop_in => stop_in,
+ out_sosi_arr => out_sosi_arr,
+ out_siso => out_siso,
+
+ --PHY
+ phy3_io => phy3_io,
+ phy3_ou => phy3_ou,
+ phy4_io => phy4_io,
+ phy4_ou => phy4_ou
+ );
end tb;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index 107e1a0588..5dc337d404 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -27,13 +27,13 @@
-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
library IEEE, common_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, st_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_adc_input_and_timing is
generic (
@@ -187,35 +187,35 @@ begin
-----------------------------------------------------------------------------
u_jesd204b: entity tech_jesd204b_lib.tech_jesd204b
- generic map(
- g_sim => false, -- do not use g_sim, because JESD204B IP does support mm_clk in sim
- g_nof_streams => c_sdp_S_pn,
- g_nof_sync_n => c_sdp_N_sync_jesd,
- g_jesd_freq => c_sdp_jesd204b_freq
- )
- port map(
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n_arr => jesd204b_sync_n,
-
- rx_sosi_arr => rx_sosi_arr,
- rx_clk => rx_clk,
- rx_rst => rx_rst,
- rx_sysref => rx_sysref,
-
- jesd204b_disable_arr => jesd204b_disable_arr,
-
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst_jesd,
-
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
-
- -- Serial
- serial_tx_arr => open,
- serial_rx_arr => JESD204B_SERIAL_DATA(c_sdp_S_pn - 1 downto 0)
- );
+ generic map(
+ g_sim => false, -- do not use g_sim, because JESD204B IP does support mm_clk in sim
+ g_nof_streams => c_sdp_S_pn,
+ g_nof_sync_n => c_sdp_N_sync_jesd,
+ g_jesd_freq => c_sdp_jesd204b_freq
+ )
+ port map(
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n_arr => jesd204b_sync_n,
+
+ rx_sosi_arr => rx_sosi_arr,
+ rx_clk => rx_clk,
+ rx_rst => rx_rst,
+ rx_sysref => rx_sysref,
+
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst_jesd,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => JESD204B_SERIAL_DATA(c_sdp_S_pn - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- Time delay: dp_shiftram
@@ -236,119 +236,119 @@ begin
end process;
u_dp_shiftram : entity dp_lib.dp_shiftram
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_nof_words => c_sdp_V_sample_delay,
- g_data_w => c_sdp_W_adc,
- g_use_sync_in => true
- )
- port map (
- dp_rst => rx_rst,
- dp_clk => rx_clk,
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_nof_words => c_sdp_V_sample_delay,
+ g_data_w => c_sdp_W_adc,
+ g_use_sync_in => true
+ )
+ port map (
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- sync_in => bs_sosi.sync,
+ sync_in => bs_sosi.sync,
- reg_mosi => reg_dp_shiftram_mosi,
- reg_miso => reg_dp_shiftram_miso,
+ reg_mosi => reg_dp_shiftram_mosi,
+ reg_miso => reg_dp_shiftram_miso,
- snk_in_arr => dp_shiftram_snk_in_arr,
+ snk_in_arr => dp_shiftram_snk_in_arr,
- src_out_arr => ant_sosi_arr
- );
+ src_out_arr => ant_sosi_arr
+ );
end generate;
-----------------------------------------------------------------------------
-- Timestamp
-----------------------------------------------------------------------------
u_bsn_source_v2 : entity dp_lib.mms_dp_bsn_source_v2
- generic map (
- g_cross_clock_domain => true,
- g_block_size => c_bs_block_size,
- g_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- dp_pps => rx_sysref,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_v2_mosi,
- reg_miso => reg_bsn_source_v2_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi,
-
- bs_restart => rx_bsn_source_restart,
- bs_new_interval => rx_bsn_source_new_interval,
- bs_nof_clk_per_sync => rx_bsn_source_nof_clk_per_sync
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_block_size => c_bs_block_size,
+ g_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ dp_pps => rx_sysref,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_bsn_source_v2_mosi,
+ reg_miso => reg_bsn_source_v2_miso,
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi,
+
+ bs_restart => rx_bsn_source_restart,
+ bs_new_interval => rx_bsn_source_new_interval,
+ bs_nof_clk_per_sync => rx_bsn_source_nof_clk_per_sync
+ );
u_bsn_trigger_wg : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => true,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_miso => reg_bsn_scheduler_wg_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
- trigger_out => trigger_wg
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ trigger_out => trigger_wg
+ );
-----------------------------------------------------------------------------
-- WG (Test Signal Generator)
-----------------------------------------------------------------------------
u_wg_arr : entity diag_lib.mms_diag_wg_wideband_arr
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_cross_clock_domain => true,
- g_buf_dir => c_wg_buf_directory,
-
- -- Wideband parameters
- g_wideband_factor => 1,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => c_wg_buf_dat_w,
- g_buf_addr_w => c_wg_buf_addr_w,
- g_calc_support => true,
- g_calc_gain_w => 1,
- g_calc_dat_w => c_sdp_W_adc
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_wg_mosi,
- reg_miso => reg_wg_miso,
-
- buf_mosi => ram_wg_mosi,
- buf_miso => ram_wg_miso,
-
- -- Streaming clock domain
- st_rst => rx_rst,
- st_clk => rx_clk,
- st_restart => trigger_wg,
-
- out_sosi_arr => wg_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_cross_clock_domain => true,
+ g_buf_dir => c_wg_buf_directory,
+
+ -- Wideband parameters
+ g_wideband_factor => 1,
+
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => c_wg_buf_dat_w,
+ g_buf_addr_w => c_wg_buf_addr_w,
+ g_calc_support => true,
+ g_calc_gain_w => 1,
+ g_calc_dat_w => c_sdp_W_adc
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_wg_mosi,
+ reg_miso => reg_wg_miso,
+
+ buf_mosi => ram_wg_mosi,
+ buf_miso => ram_wg_miso,
+
+ -- Streaming clock domain
+ st_rst => rx_rst,
+ st_clk => rx_clk,
+ st_restart => trigger_wg,
+
+ out_sosi_arr => wg_sosi_arr
+ );
-----------------------------------------------------------------------------
-- ADC/WG Mux (Input Select)
@@ -391,101 +391,101 @@ begin
-- BSN monitor (Block Checker)
---------------------------------------------------------------------------------------
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- They're all the same
- g_sync_timeout => c_bs_sync_timeout,
- g_bsn_w => c_bs_bsn_w,
- g_log_first_bsn => false
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_input_mosi,
- reg_miso => reg_bsn_monitor_input_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- in_sosi_arr => st_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- They're all the same
+ g_sync_timeout => c_bs_sync_timeout,
+ g_bsn_w => c_bs_bsn_w,
+ g_log_first_bsn => false
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_input_mosi,
+ reg_miso => reg_bsn_monitor_input_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ in_sosi_arr => st_sosi_arr(0 downto 0)
+ );
-----------------------------------------------------------------------------
-- Monitor ADU/WG output
-----------------------------------------------------------------------------
u_aduh_monitor : entity aduh_lib.mms_aduh_monitor_arr
- generic map (
- g_cross_clock_domain => true,
- g_nof_streams => c_sdp_S_pn,
- g_symbol_w => c_sdp_W_adc,
- g_nof_symbols_per_data => 1, -- Wideband factor is 1
- g_nof_accumulations => g_bsn_nof_clk_per_sync
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
- reg_miso => reg_aduh_monitor_miso,
- buf_mosi => c_mem_mosi_rst, -- Unused
- buf_miso => OPEN,
-
- -- Streaming clock domain
- st_rst => rx_rst,
- st_clk => rx_clk,
-
- in_sosi_arr => st_sosi_arr
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_nof_streams => c_sdp_S_pn,
+ g_symbol_w => c_sdp_W_adc,
+ g_nof_symbols_per_data => 1, -- Wideband factor is 1
+ g_nof_accumulations => g_bsn_nof_clk_per_sync
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
+ reg_miso => reg_aduh_monitor_miso,
+ buf_mosi => c_mem_mosi_rst, -- Unused
+ buf_miso => OPEN,
+
+ -- Streaming clock domain
+ st_rst => rx_rst,
+ st_clk => rx_clk,
+
+ in_sosi_arr => st_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Diagnostic Data Buffer
-----------------------------------------------------------------------------
u_diag_data_buffer_bsn : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_data_w => c_sdp_W_adc,
- g_buf_nof_data => g_buf_nof_data,
- g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
- ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
- reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
- reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
-
- in_sosi_arr => st_sosi_arr,
- in_sync => st_sosi_arr(0).sync
- );
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_data_w => c_sdp_W_adc,
+ g_buf_nof_data => g_buf_nof_data,
+ g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
+
+ in_sosi_arr => st_sosi_arr,
+ in_sync => st_sosi_arr(0).sync
+ );
-----------------------------------------------------------------------------
-- ST Histogram
-----------------------------------------------------------------------------
u_st_histogram : entity st_lib.mmp_st_histogram
- generic map (
- g_nof_instances => c_sdp_S_pn,
- g_data_w => c_sdp_W_adc,
- g_nof_bins => c_sdp_V_si_histogram,
- g_nof_data_per_sync => g_bsn_nof_clk_per_sync,
- g_nof_data_per_sync_diff => c_sdp_N_fft / 2
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- ram_copi => ram_st_histogram_mosi,
- ram_cipo => ram_st_histogram_miso,
-
- snk_in_arr => st_sosi_arr
- );
+ generic map (
+ g_nof_instances => c_sdp_S_pn,
+ g_data_w => c_sdp_W_adc,
+ g_nof_bins => c_sdp_V_si_histogram,
+ g_nof_data_per_sync => g_bsn_nof_clk_per_sync,
+ g_nof_data_per_sync_diff => c_sdp_N_fft / 2
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ ram_copi => ram_st_histogram_mosi,
+ ram_cipo => ram_st_histogram_miso,
+
+ snk_in_arr => st_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Output Stage
@@ -530,36 +530,36 @@ begin
-- in mms_dp_bsn_monitor, and from rx_clk to dp_clk here. No need to go via
-- u_dp_fifo_dc_arr, use common_reg_cross_domain instead to save logic and/or RAM.
u_dp_nof_block_per_sync : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => rx_rst,
- in_clk => rx_clk,
- in_dat => rx_bsn_source_nof_clk_per_sync,
- out_rst => dp_rst,
- out_clk => dp_clk,
- out_dat => dp_bsn_source_nof_clk_per_sync
- );
+ port map (
+ in_rst => rx_rst,
+ in_clk => rx_clk,
+ in_dat => rx_bsn_source_nof_clk_per_sync,
+ out_rst => dp_rst,
+ out_clk => dp_clk,
+ out_dat => dp_bsn_source_nof_clk_per_sync
+ );
-----------------------------------------------------------------------------
-- JESD Control register
-----------------------------------------------------------------------------
u_mm_jesd_ctrl_reg : entity common_lib.common_reg_r_w
- generic map (
- g_reg => c_sdp_mm_jesd_ctrl_reg,
- g_init_reg => (others => '0')
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- control side
- wr_en => jesd_ctrl_mosi.wr,
- wr_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- wr_dat => jesd_ctrl_mosi.wrdata(c_sdp_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_en => jesd_ctrl_mosi.rd,
- rd_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- rd_dat => jesd_ctrl_miso.rddata(c_sdp_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_val => OPEN,
- -- data side
- out_reg => mm_jesd_ctrl_reg_wr,
- in_reg => mm_jesd_ctrl_reg_rd
- );
+ generic map (
+ g_reg => c_sdp_mm_jesd_ctrl_reg,
+ g_init_reg => (others => '0')
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- control side
+ wr_en => jesd_ctrl_mosi.wr,
+ wr_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ wr_dat => jesd_ctrl_mosi.wrdata(c_sdp_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_en => jesd_ctrl_mosi.rd,
+ rd_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ rd_dat => jesd_ctrl_miso.rddata(c_sdp_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_val => OPEN,
+ -- data side
+ out_reg => mm_jesd_ctrl_reg_wr,
+ in_reg => mm_jesd_ctrl_reg_rd
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
index a2ea28949b..eab3e249a1 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
@@ -30,13 +30,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_beamformer is
generic (
@@ -147,74 +147,74 @@ begin
-- Beamlet Subband Select
---------------------------------------------------------------
u_reorder_col_wide : entity reorder_lib.reorder_col_wide
- generic map (
- g_wb_factor => c_sdp_P_pfb, -- g_wb_factor is only used for number of parallel streams
- g_dsp_data_w => g_subband_raw_dat_w,
- g_nof_ch_in => c_sdp_N_sub * c_sdp_Q_fft,
- g_nof_ch_sel => c_sdp_S_sub_bf * c_sdp_Q_fft,
- g_select_file_prefix => c_bf_select_file_prefix,
- g_use_complex => true
- )
- port map(
- input_sosi_arr => in_sosi_arr,
- output_sosi_arr => bsel_sosi_arr,
-
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst
- );
+ generic map (
+ g_wb_factor => c_sdp_P_pfb, -- g_wb_factor is only used for number of parallel streams
+ g_dsp_data_w => g_subband_raw_dat_w,
+ g_nof_ch_in => c_sdp_N_sub * c_sdp_Q_fft,
+ g_nof_ch_sel => c_sdp_S_sub_bf * c_sdp_Q_fft,
+ g_select_file_prefix => c_bf_select_file_prefix,
+ g_use_complex => true
+ )
+ port map(
+ input_sosi_arr => in_sosi_arr,
+ output_sosi_arr => bsel_sosi_arr,
+
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst
+ );
---------------------------------------------------------------
-- Local BF
---------------------------------------------------------------
u_sdp_beamformer_local : entity work.sdp_beamformer_local
- generic map (
- g_bf_weights_file_name => c_bf_weights_file_name,
- g_raw_dat_w => g_subband_raw_dat_w,
- g_raw_fraction_w => g_subband_raw_fraction_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
-
- in_sosi_arr => bsel_sosi_arr,
- out_sosi => local_bf_sosi
- );
+ generic map (
+ g_bf_weights_file_name => c_bf_weights_file_name,
+ g_raw_dat_w => g_subband_raw_dat_w,
+ g_raw_fraction_w => g_subband_raw_fraction_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+
+ in_sosi_arr => bsel_sosi_arr,
+ out_sosi => local_bf_sosi
+ );
---------------------------------------------------------------
-- Remote BF
---------------------------------------------------------------
u_sdp_beamformer_remote : entity work.sdp_beamformer_remote
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- rn_index => rn_index,
- local_bf_sosi => local_bf_sosi,
- from_ri_sosi => from_ri_sosi,
- to_ri_sosi => to_ri_sosi,
- bf_sum_sosi => bf_sum_sosi,
-
- reg_bsn_align_copi => reg_bsn_align_copi,
- reg_bsn_align_cipo => reg_bsn_align_cipo,
-
- reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
- reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
-
- reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
- reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo
- );
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ rn_index => rn_index,
+ local_bf_sosi => local_bf_sosi,
+ from_ri_sosi => from_ri_sosi,
+ to_ri_sosi => to_ri_sosi,
+ bf_sum_sosi => bf_sum_sosi,
+
+ reg_bsn_align_copi => reg_bsn_align_copi,
+ reg_bsn_align_cipo => reg_bsn_align_cipo,
+
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
+
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo
+ );
---------------------------------------------------------------
-- Scale Beamlets
@@ -253,82 +253,82 @@ begin
-- Beamlet Data Output (BDO)
---------------------------------------------------------------
u_sdp_beamformer_output : entity work.sdp_beamformer_output
- generic map(
- g_beamset_id => g_beamset_id
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_sosi => bf_out_sosi,
- out_sosi => mon_bf_udp_sosi,
- out_siso => bf_udp_siso,
-
- beamlet_scale => beamlet_scale,
- sdp_info => sdp_info,
- gn_id => gn_id,
-
- eth_src_mac => bdo_eth_src_mac,
- ip_src_addr => bdo_ip_src_addr,
- udp_src_port => bdo_udp_src_port,
-
- hdr_fields_out => bdo_hdr_fields_out,
-
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso
- );
+ generic map(
+ g_beamset_id => g_beamset_id
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_sosi => bf_out_sosi,
+ out_sosi => mon_bf_udp_sosi,
+ out_siso => bf_udp_siso,
+
+ beamlet_scale => beamlet_scale,
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+
+ eth_src_mac => bdo_eth_src_mac,
+ ip_src_addr => bdo_ip_src_addr,
+ udp_src_port => bdo_udp_src_port,
+
+ hdr_fields_out => bdo_hdr_fields_out,
+
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso
+ );
bf_udp_sosi <= mon_bf_udp_sosi;
u_bsn_mon_udp : entity dp_lib.mms_dp_bsn_monitor_v2
- generic map (
- g_nof_streams => 1,
- g_cross_clock_domain => true,
- g_sync_timeout => c_sdp_N_clk_sync_timeout,
- g_bsn_w => c_dp_stream_bsn_w,
- g_error_bi => 0,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_cnt_latency_w => c_word_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_miso => reg_bsn_monitor_v2_beamlet_output_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ref_sync => ref_sync,
-
- in_sosi_arr(0) => mon_bf_udp_sosi
- );
+ generic map (
+ g_nof_streams => 1,
+ g_cross_clock_domain => true,
+ g_sync_timeout => c_sdp_N_clk_sync_timeout,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_miso => reg_bsn_monitor_v2_beamlet_output_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => ref_sync,
+
+ in_sosi_arr(0) => mon_bf_udp_sosi
+ );
---------------------------------------------------------------
-- Beamlet Statistics (BST)
---------------------------------------------------------------
u_beamlet_stats : entity st_lib.st_sst
- generic map(
- g_nof_stat => c_sdp_S_sub_bf * c_sdp_N_pol_bf,
- g_in_data_w => c_sdp_W_beamlet_sum,
- g_stat_data_w => c_longword_w,
- g_stat_data_sz => c_longword_sz / c_word_sz,
- g_stat_multiplex => c_sdp_N_pol_bf
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_complex => bf_sum_sosi,
- ram_st_sst_mosi => master_mem_mux_mosi,
- ram_st_sst_miso => master_mem_mux_miso
- );
+ generic map(
+ g_nof_stat => c_sdp_S_sub_bf * c_sdp_N_pol_bf,
+ g_in_data_w => c_sdp_W_beamlet_sum,
+ g_stat_data_w => c_longword_w,
+ g_stat_data_sz => c_longword_sz / c_word_sz,
+ g_stat_multiplex => c_sdp_N_pol_bf
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_complex => bf_sum_sosi,
+ ram_st_sst_mosi => master_mem_mux_mosi,
+ ram_st_sst_miso => master_mem_mux_miso
+ );
---------------------------------------------------------------
-- MM master multiplexer
@@ -340,62 +340,62 @@ begin
ram_st_offload_miso <= master_miso_arr(1);
u_mem_master_mux : entity mm_lib.mm_master_mux
- generic map (
- g_nof_masters => c_nof_masters,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
- )
- port map (
- mm_clk => mm_clk,
-
- master_mosi_arr => master_mosi_arr,
- master_miso_arr => master_miso_arr,
- mux_mosi => master_mem_mux_mosi,
- mux_miso => master_mem_mux_miso
- );
+ generic map (
+ g_nof_masters => c_nof_masters,
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ )
+ port map (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => master_mosi_arr,
+ master_miso_arr => master_miso_arr,
+ mux_mosi => master_mem_mux_mosi,
+ mux_miso => master_mem_mux_miso
+ );
---------------------------------------------------------------
-- BST UDP offload
---------------------------------------------------------------
u_sdp_bst_udp_offload: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => "BST",
- g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
- g_beamset_id => g_beamset_id
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_statistics_type => "BST",
+ g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
+ g_beamset_id => g_beamset_id
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- master_mosi => ram_st_offload_mosi,
- master_miso => ram_st_offload_miso,
+ master_mosi => ram_st_offload_mosi,
+ master_miso => ram_st_offload_miso,
- reg_enable_mosi => reg_stat_enable_mosi,
- reg_enable_miso => reg_stat_enable_miso,
+ reg_enable_mosi => reg_stat_enable_mosi,
+ reg_enable_miso => reg_stat_enable_miso,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
- reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- in_sosi => bf_sum_sosi,
- new_interval => dp_bsn_source_new_interval,
+ in_sosi => bf_sum_sosi,
+ new_interval => dp_bsn_source_new_interval,
- out_sosi => bst_udp_sosi,
- out_siso => bst_udp_siso,
+ out_sosi => bst_udp_sosi,
+ out_siso => bst_udp_siso,
- eth_src_mac => stat_eth_src_mac,
- udp_src_port => stat_udp_src_port,
- ip_src_addr => stat_ip_src_addr,
+ eth_src_mac => stat_eth_src_mac,
+ udp_src_port => stat_udp_src_port,
+ ip_src_addr => stat_ip_src_addr,
- gn_index => TO_UINT(gn_id),
- ring_info => ring_info,
- sdp_info => sdp_info,
- weighted_subbands_flag => '1' -- because BF uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
- );
+ gn_index => TO_UINT(gn_id),
+ ring_info => ring_info,
+ sdp_info => sdp_info,
+ weighted_subbands_flag => '1' -- because BF uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
+ );
---------------------------------------------------------------
-- SIGNAL SCOPES
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index fb263f5b4c..878a9244c7 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -32,13 +32,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_correlator is
generic (
@@ -98,16 +98,16 @@ architecture str of node_sdp_correlator is
constant c_block_size_longwords : natural := ceil_div(c_block_size, 2); -- 32b -> 64b
constant c_data_w : natural := c_sdp_W_crosslet * c_nof_complex;
--- The size for 1 block is probably already enough as the number of blocks received
--- on the remote input of the mux probably have enough gap time in between. Just
--- to be sure to not run into issues in the future, the fifo size is increased to
--- buffer the maximum nof blocks per block period.
+ -- The size for 1 block is probably already enough as the number of blocks received
+ -- on the remote input of the mux probably have enough gap time in between. Just
+ -- to be sure to not run into issues in the future, the fifo size is increased to
+ -- buffer the maximum nof blocks per block period.
constant c_mux_fifo_size : natural := 2**ceil_log2(g_P_sq * c_block_size_longwords);
--- c_fifo_fill_size should be at least 2 * c_block_size_longwords as dp_repack_data
--- repacks from 64bit to 32bit. Chosing 3x to have some room.
+ -- c_fifo_fill_size should be at least 2 * c_block_size_longwords as dp_repack_data
+ -- repacks from 64bit to 32bit. Chosing 3x to have some room.
constant c_fifo_fill_size : natural := 2**ceil_log2(3 * c_block_size_longwords);
--- crosslet statistics offload
+ -- crosslet statistics offload
signal ram_st_offload_copi : t_mem_copi := c_mem_copi_rst;
signal ram_st_offload_cipo : t_mem_cipo := c_mem_cipo_rst;
@@ -146,57 +146,57 @@ begin
---------------------------------------------------------------
gen_requantize : for I in 0 to c_sdp_P_pfb - 1 generate
u_dp_requantize : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => g_subband_raw_fraction_w,
- g_lsb_round => true, -- round subband fraction
- g_lsb_round_clip => false,
- g_msb_clip => true, -- clip subband overflow
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => 1,
- g_pipeline_remove_msb => 1,
- g_in_dat_w => g_subband_raw_dat_w,
- g_out_dat_w => c_sdp_W_crosslet
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => in_sosi_arr(I),
- src_out => quant_sosi_arr(I)
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => g_subband_raw_fraction_w,
+ g_lsb_round => true, -- round subband fraction
+ g_lsb_round_clip => false,
+ g_msb_clip => true, -- clip subband overflow
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => 1,
+ g_pipeline_remove_msb => 1,
+ g_in_dat_w => g_subband_raw_dat_w,
+ g_out_dat_w => c_sdp_W_crosslet
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => in_sosi_arr(I),
+ src_out => quant_sosi_arr(I)
+ );
end generate;
---------------------------------------------------------------
-- Crosslet Subband Select
---------------------------------------------------------------
u_crosslets_subband_select : entity work.sdp_crosslets_subband_select
- generic map (
- g_N_crosslets => c_sdp_N_crosslets_max,
- g_ctrl_interval_size_min => sel_a_b(g_sim, g_sim_sdp.xst_nof_clk_per_sync_min, c_sdp_xst_nof_clk_per_sync_min)
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ generic map (
+ g_N_crosslets => c_sdp_N_crosslets_max,
+ g_ctrl_interval_size_min => sel_a_b(g_sim, g_sim_sdp.xst_nof_clk_per_sync_min, c_sdp_xst_nof_clk_per_sync_min)
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- in_sosi_arr => quant_sosi_arr,
- out_sosi => xsel_sosi,
+ in_sosi_arr => quant_sosi_arr,
+ out_sosi => xsel_sosi,
- new_interval => new_interval,
+ new_interval => new_interval,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_crosslets_info_mosi => reg_crosslets_info_copi,
- reg_crosslets_info_miso => reg_crosslets_info_cipo,
+ reg_crosslets_info_mosi => reg_crosslets_info_copi,
+ reg_crosslets_info_miso => reg_crosslets_info_cipo,
- reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_cipo,
+ reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_cipo,
- cur_crosslets_info_rec => OPEN,
- prev_crosslets_info_rec => prev_crosslets_info_rec
- );
+ cur_crosslets_info_rec => OPEN,
+ prev_crosslets_info_rec => prev_crosslets_info_rec
+ );
-- Use xsel_sosi as local bsn and sync reference since the sync
-- is generated by the bsn_sync_scheduler in sdp_crosslets_subband_select.
@@ -214,110 +214,110 @@ begin
end process;
u_dp_repack_data_local : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_data_w,
- g_in_nof_words => c_longword_w / c_data_w,
- g_out_dat_w => c_longword_w,
- g_out_nof_words => 1,
- g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => xsel_data_sosi,
- src_out => local_sosi
- );
+ generic map (
+ g_in_dat_w => c_data_w,
+ g_in_nof_words => c_longword_w / c_data_w,
+ g_out_dat_w => c_longword_w,
+ g_out_nof_words => 1,
+ g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => xsel_data_sosi,
+ src_out => local_sosi
+ );
---------------------------------------------------------------
-- ring_mux
---------------------------------------------------------------
u_ring_mux : entity ring_lib.ring_mux
- generic map (
- g_bsn_w => c_dp_stream_bsn_w,
- g_data_w => c_longword_w,
- g_channel_w => c_word_w,
- g_use_error => false,
- g_fifo_size => array_init(c_mux_fifo_size, 2)
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- remote_sosi => from_ri_sosi,
- local_sosi => local_sosi,
- mux_sosi => ring_mux_sosi,
- mux_siso => ring_mux_siso
- );
+ generic map (
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_data_w => c_longword_w,
+ g_channel_w => c_word_w,
+ g_use_error => false,
+ g_fifo_size => array_init(c_mux_fifo_size, 2)
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ remote_sosi => from_ri_sosi,
+ local_sosi => local_sosi,
+ mux_sosi => ring_mux_sosi,
+ mux_siso => ring_mux_siso
+ );
to_ri_sosi <= ring_mux_sosi;
-- fill fifo to remove gaps
u_dp_fifo_fill_eop : entity dp_lib.dp_fifo_fill_eop
- generic map (
- g_data_w => c_longword_w,
- g_bsn_w => c_dp_stream_bsn_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_error => true,
- g_use_sync => true,
- g_fifo_fill => c_block_size_longwords,
- g_fifo_size => c_fifo_fill_size
- )
- port map (
- wr_rst => dp_rst,
- wr_clk => dp_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
-
- snk_out => ring_mux_siso,
- snk_in => ring_mux_sosi,
-
- src_in => dp_fifo_fill_siso,
- src_out => dp_fifo_fill_sosi
- );
+ generic map (
+ g_data_w => c_longword_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_error_w => c_dp_stream_error_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ g_fifo_fill => c_block_size_longwords,
+ g_fifo_size => c_fifo_fill_size
+ )
+ port map (
+ wr_rst => dp_rst,
+ wr_clk => dp_clk,
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+
+ snk_out => ring_mux_siso,
+ snk_in => ring_mux_sosi,
+
+ src_in => dp_fifo_fill_siso,
+ src_out => dp_fifo_fill_sosi
+ );
---------------------------------------------------------------
-- Repack 64b to 32b
---------------------------------------------------------------
u_dp_repack_data_rx : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_longword_w,
- g_in_nof_words => 1,
- g_out_dat_w => c_data_w,
- g_out_nof_words => c_longword_w / c_data_w,
- g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_fifo_fill_sosi,
- snk_out => dp_fifo_fill_siso,
- src_out => rx_sosi
- );
+ generic map (
+ g_in_dat_w => c_longword_w,
+ g_in_nof_words => 1,
+ g_out_dat_w => c_data_w,
+ g_out_nof_words => c_longword_w / c_data_w,
+ g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => dp_fifo_fill_sosi,
+ snk_out => dp_fifo_fill_siso,
+ src_out => rx_sosi
+ );
---------------------------------------------------------------
-- dp_demux
---------------------------------------------------------------
u_dp_demux : entity dp_lib.dp_demux
- generic map (
- g_mode => 0,
- g_nof_output => g_P_sq,
- g_remove_channel_lo => false,
- g_sel_ctrl_invert => true -- TRUE when indexed (g_nof_input-1 DOWNTO 0)
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => rx_sosi,
- src_out_arr => dispatch_invert_sosi_arr
- );
+ generic map (
+ g_mode => 0,
+ g_nof_output => g_P_sq,
+ g_remove_channel_lo => false,
+ g_sel_ctrl_invert => true -- TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => rx_sosi,
+ src_out_arr => dispatch_invert_sosi_arr
+ );
dispatch_sosi_arr <= func_dp_stream_arr_reverse_range(dispatch_invert_sosi_arr);
@@ -325,71 +325,71 @@ begin
-- dp_bsn_aligner_v2
---------------------------------------------------------------
u_mmp_dp_bsn_align_v2 : entity dp_lib.mmp_dp_bsn_align_v2
- generic map(
- -- for dp_bsn_align_v2
- g_nof_streams => g_P_sq,
- g_bsn_latency_max => 2,
- g_nof_aligners_max => 1, -- 1 for Access scheme 3.
- g_block_size => c_block_size,
- g_data_w => c_data_w,
- g_use_mm_output => true,
- g_rd_latency => 1, -- Required for st_xst
- -- for mms_dp_bsn_monitor_v2
- g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout_xsub, -- Using c_sdp_N_clk_sync_timeout_xsub as g_nof_clk_per_sync is used for BSN monitor timeout.
- g_nof_input_bsn_monitors => g_P_sq,
- g_use_bsn_output_monitor => true
+ generic map(
+ -- for dp_bsn_align_v2
+ g_nof_streams => g_P_sq,
+ g_bsn_latency_max => 2,
+ g_nof_aligners_max => 1, -- 1 for Access scheme 3.
+ g_block_size => c_block_size,
+ g_data_w => c_data_w,
+ g_use_mm_output => true,
+ g_rd_latency => 1, -- Required for st_xst
+ -- for mms_dp_bsn_monitor_v2
+ g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout_xsub, -- Using c_sdp_N_clk_sync_timeout_xsub as g_nof_clk_per_sync is used for BSN monitor timeout.
+ g_nof_input_bsn_monitors => g_P_sq,
+ g_use_bsn_output_monitor => true
)
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_bsn_align_copi => reg_bsn_align_copi,
- reg_bsn_align_cipo => reg_bsn_align_cipo,
+ reg_bsn_align_copi => reg_bsn_align_copi,
+ reg_bsn_align_cipo => reg_bsn_align_cipo,
- reg_input_monitor_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
- reg_input_monitor_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
+ reg_input_monitor_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
+ reg_input_monitor_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
- reg_output_monitor_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
- reg_output_monitor_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
+ reg_output_monitor_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
+ reg_output_monitor_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- Streaming input
- in_sosi_arr => dispatch_sosi_arr,
+ -- Streaming input
+ in_sosi_arr => dispatch_sosi_arr,
- -- Output via local MM interface in dp_clk domain, when g_use_mm_output = TRUE.
- mm_sosi => crosslets_sosi,
- mm_copi => crosslets_copi,
- mm_cipo_arr => crosslets_cipo_arr
- );
+ -- Output via local MM interface in dp_clk domain, when g_use_mm_output = TRUE.
+ mm_sosi => crosslets_sosi,
+ mm_copi => crosslets_copi,
+ mm_cipo_arr => crosslets_cipo_arr
+ );
---------------------------------------------------------------
-- Crosslets Statistics (XST)
---------------------------------------------------------------
u_crosslets_stats : entity st_lib.st_xst
- generic map(
- g_nof_streams => g_P_sq,
- g_nof_crosslets => c_sdp_N_crosslets_max,
- g_nof_signal_inputs => c_sdp_S_pn,
- g_in_data_w => c_sdp_W_crosslet,
- g_stat_data_w => c_longword_w,
- g_stat_data_sz => c_longword_sz / c_word_sz
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_sosi => crosslets_sosi,
- mm_mosi => crosslets_copi,
- mm_miso_arr => crosslets_cipo_arr,
-
- ram_st_xsq_mosi => controller_mem_mux_copi,
- ram_st_xsq_miso => controller_mem_mux_cipo
- );
+ generic map(
+ g_nof_streams => g_P_sq,
+ g_nof_crosslets => c_sdp_N_crosslets_max,
+ g_nof_signal_inputs => c_sdp_S_pn,
+ g_in_data_w => c_sdp_W_crosslet,
+ g_stat_data_w => c_longword_w,
+ g_stat_data_sz => c_longword_sz / c_word_sz
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_sosi => crosslets_sosi,
+ mm_mosi => crosslets_copi,
+ mm_miso_arr => crosslets_cipo_arr,
+
+ ram_st_xsq_mosi => controller_mem_mux_copi,
+ ram_st_xsq_miso => controller_mem_mux_cipo
+ );
---------------------------------------------------------------
-- MM controller multiplexer
@@ -401,94 +401,94 @@ begin
ram_st_offload_cipo <= controller_cipo_arr(1);
u_mem_controller_mux : entity mm_lib.mm_master_mux
- generic map (
- g_nof_masters => c_nof_controllers,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
- )
- port map (
- mm_clk => mm_clk,
-
- master_mosi_arr => controller_copi_arr,
- master_miso_arr => controller_cipo_arr,
- mux_mosi => controller_mem_mux_copi,
- mux_miso => controller_mem_mux_cipo
- );
+ generic map (
+ g_nof_masters => c_nof_controllers,
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ )
+ port map (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => controller_copi_arr,
+ master_miso_arr => controller_cipo_arr,
+ mux_mosi => controller_mem_mux_copi,
+ mux_miso => controller_mem_mux_cipo
+ );
---------------------------------------------------------------
-- REG_NOF_CROSSLETS
---------------------------------------------------------------
u_nof_crosslets : entity common_lib.mms_common_reg
- generic map(
- g_mm_reg => c_sdp_mm_reg_nof_crosslets
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- MM bus access in memory-mapped clock domain
- reg_mosi => reg_nof_crosslets_copi,
- reg_miso => reg_nof_crosslets_cipo,
-
- in_reg => nof_crosslets,
- out_reg => nof_crosslets_reg
- );
+ generic map(
+ g_mm_reg => c_sdp_mm_reg_nof_crosslets
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- MM bus access in memory-mapped clock domain
+ reg_mosi => reg_nof_crosslets_copi,
+ reg_miso => reg_nof_crosslets_cipo,
+
+ in_reg => nof_crosslets,
+ out_reg => nof_crosslets_reg
+ );
-- Force nof crosslets to max nof crosslets if a higher value is written or to 1 if a lower value is written via MM.
nof_crosslets <= TO_UVEC(1, c_sdp_nof_crosslets_reg_w) when TO_UINT(nof_crosslets_reg) < 1 else
nof_crosslets_reg when TO_UINT(nof_crosslets_reg) <= c_sdp_N_crosslets_max else
- TO_UVEC(c_sdp_N_crosslets_max, c_sdp_nof_crosslets_reg_w);
-
- ---------------------------------------------------------------
- -- XST UDP offload
- ---------------------------------------------------------------
- xst_udp_sosi <= mon_xst_udp_sosi_arr(0);
-
- u_sdp_xst_udp_offload: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => "XST",
- g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
- g_P_sq => g_P_sq,
- g_crosslets_direction => 1, -- = lane direction
- g_bsn_monitor_sync_timeout => c_sdp_N_clk_sync_timeout_xsub
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- master_mosi => ram_st_offload_copi,
- master_miso => ram_st_offload_cipo,
-
- reg_enable_mosi => reg_stat_enable_copi,
- reg_enable_miso => reg_stat_enable_cipo,
-
- reg_hdr_dat_mosi => reg_stat_hdr_dat_copi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_cipo,
-
- reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
-
- in_sosi => crosslets_sosi,
- new_interval => new_interval,
-
- out_sosi => mon_xst_udp_sosi_arr(0),
- out_siso => xst_udp_siso,
-
- eth_src_mac => stat_eth_src_mac,
- udp_src_port => stat_udp_src_port,
- ip_src_addr => stat_ip_src_addr,
-
- gn_index => TO_UINT(gn_id),
- ring_info => ring_info,
- sdp_info => sdp_info,
- weighted_subbands_flag => '1', -- because XSub uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
-
- nof_crosslets => nof_crosslets, -- from MM
- prev_crosslets_info_rec => prev_crosslets_info_rec
- );
+ TO_UVEC(c_sdp_N_crosslets_max, c_sdp_nof_crosslets_reg_w);
+
+ ---------------------------------------------------------------
+ -- XST UDP offload
+ ---------------------------------------------------------------
+ xst_udp_sosi <= mon_xst_udp_sosi_arr(0);
+
+ u_sdp_xst_udp_offload: entity work.sdp_statistics_offload
+ generic map (
+ g_statistics_type => "XST",
+ g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
+ g_P_sq => g_P_sq,
+ g_crosslets_direction => 1, -- = lane direction
+ g_bsn_monitor_sync_timeout => c_sdp_N_clk_sync_timeout_xsub
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ master_mosi => ram_st_offload_copi,
+ master_miso => ram_st_offload_cipo,
+
+ reg_enable_mosi => reg_stat_enable_copi,
+ reg_enable_miso => reg_stat_enable_cipo,
+
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_copi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_cipo,
+
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+
+ in_sosi => crosslets_sosi,
+ new_interval => new_interval,
+
+ out_sosi => mon_xst_udp_sosi_arr(0),
+ out_siso => xst_udp_siso,
+
+ eth_src_mac => stat_eth_src_mac,
+ udp_src_port => stat_udp_src_port,
+ ip_src_addr => stat_ip_src_addr,
+
+ gn_index => TO_UINT(gn_id),
+ ring_info => ring_info,
+ sdp_info => sdp_info,
+ weighted_subbands_flag => '1', -- because XSub uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
+
+ nof_crosslets => nof_crosslets, -- from MM
+ prev_crosslets_info_rec => prev_crosslets_info_rec
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index 691a5a916f..bc7b68a2c3 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -53,16 +53,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, rTwoSDF_lib, fft_lib, wpfb_lib, filter_lib, si_lib, st_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use filter_lib.fil_pkg.all;
-use fft_lib.fft_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use filter_lib.fil_pkg.all;
+ use fft_lib.fft_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_filterbank is
generic (
@@ -126,75 +126,75 @@ architecture str of node_sdp_filterbank is
-- . applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/
-- Subband gains file can be generated by sdp/src/python/sdp_hex.py
constant c_gains_file_name : string := "data/gains_1024_complex_" &
- natural'image(c_sdp_W_sub_weight) & "b" &
- natural'image(c_sdp_W_sub_weight_fraction) & "f_unit";
+ natural'image(c_sdp_W_sub_weight) & "b" &
+ natural'image(c_sdp_W_sub_weight_fraction) & "f_unit";
- constant c_nof_masters : positive := 2; -- for M&C MM access and for statistics offload MM access
+ constant c_nof_masters : positive := 2; -- for M&C MM access and for statistics offload MM access
- constant c_fft : t_fft := func_wpfb_map_wpfb_parameters_to_fft(g_wpfb);
- constant c_subband_raw_dat_w : natural := func_fft_raw_dat_w(c_fft);
- constant c_subband_raw_fraction_w : natural := func_fft_raw_fraction_w(c_fft);
+ constant c_fft : t_fft := func_wpfb_map_wpfb_parameters_to_fft(g_wpfb);
+ constant c_subband_raw_dat_w : natural := func_fft_raw_dat_w(c_fft);
+ constant c_subband_raw_fraction_w : natural := func_fft_raw_fraction_w(c_fft);
- constant c_si_pipeline : natural := 1;
+ constant c_si_pipeline : natural := 1;
- signal ram_st_sst_mosi_arr : t_mem_mosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_mem_mosi_rst);
- signal ram_st_sst_miso_arr : t_mem_miso_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_mem_miso_rst);
+ signal ram_st_sst_mosi_arr : t_mem_mosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_mem_mosi_rst);
+ signal ram_st_sst_miso_arr : t_mem_miso_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_mem_miso_rst);
- -- Subband statistics
- signal ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
- signal ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
+ -- Subband statistics
+ signal ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
+ signal ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
- signal master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
- signal master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
- signal master_mosi_arr : t_mem_mosi_arr(0 to c_nof_masters - 1) := (others => c_mem_mosi_rst);
- signal master_miso_arr : t_mem_miso_arr(0 to c_nof_masters - 1) := (others => c_mem_miso_rst);
+ signal master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
+ signal master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
+ signal master_mosi_arr : t_mem_mosi_arr(0 to c_nof_masters - 1) := (others => c_mem_mosi_rst);
+ signal master_miso_arr : t_mem_miso_arr(0 to c_nof_masters - 1) := (others => c_mem_miso_rst);
- signal si_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal si_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_in_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_fil_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_out_raw_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_out_quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_in_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_fil_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_out_raw_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_out_quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal subband_equalizer_raw_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal subband_equalizer_quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal subband_equalizer_raw_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal subband_equalizer_quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal scope_wpfb_unit_out_quant_sosi_arr : t_dp_sosi_integer_arr(c_sdp_S_pn - 1 downto 0);
- signal scope_equalizer_quant_sosi_arr : t_dp_sosi_integer_arr(c_sdp_S_pn - 1 downto 0);
+ signal scope_wpfb_unit_out_quant_sosi_arr : t_dp_sosi_integer_arr(c_sdp_S_pn - 1 downto 0);
+ signal scope_equalizer_quant_sosi_arr : t_dp_sosi_integer_arr(c_sdp_S_pn - 1 downto 0);
- signal dp_selector_quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal dp_selector_quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal selector_en : std_logic;
- signal weighted_subbands_flag : std_logic;
+ signal selector_en : std_logic;
+ signal weighted_subbands_flag : std_logic;
- signal dp_bsn_source_restart_pipe : std_logic;
+ signal dp_bsn_source_restart_pipe : std_logic;
- -- debug signals to view parameters in Wave Window
- signal dbg_g_wpfb : t_wpfb := g_wpfb;
- signal dbg_c_subband_raw_dat_w : natural := c_subband_raw_dat_w;
- signal dbg_c_subband_raw_fraction_w : natural := c_subband_raw_fraction_w;
+ -- debug signals to view parameters in Wave Window
+ signal dbg_g_wpfb : t_wpfb := g_wpfb;
+ signal dbg_c_subband_raw_dat_w : natural := c_subband_raw_dat_w;
+ signal dbg_c_subband_raw_fraction_w : natural := c_subband_raw_fraction_w;
begin
---------------------------------------------------------------
-- SPECTRAL INVERSION
---------------------------------------------------------------
u_si_arr : entity si_lib.si_arr
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_pipeline => c_si_pipeline,
- g_dat_w => c_sdp_W_adc
- )
- port map(
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => si_sosi_arr,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst
- );
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_pipeline => c_si_pipeline,
+ g_dat_w => c_sdp_W_adc
+ )
+ port map(
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => si_sosi_arr,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst
+ );
---------------------------------------------------------------
-- POLY-PHASE FILTERBANK
@@ -211,42 +211,42 @@ begin
-- pipeline bsn restart signal to keep dp_bsn_source_restart aligned with si_sosi_arr
u_common_pipeline_sl : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_si_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_dat => dp_bsn_source_restart,
- out_dat => dp_bsn_source_restart_pipe
- );
+ generic map (
+ g_pipeline => c_si_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => dp_bsn_source_restart,
+ out_dat => dp_bsn_source_restart_pipe
+ );
-- PFB
u_wpfb_unit_dev : entity wpfb_lib.wpfb_unit_dev
- generic map (
- g_wpfb => g_wpfb,
- g_use_prefilter => true,
- g_stats_ena => false,
- g_use_bg => false,
- g_coefs_file_prefix => c_coefs_file_prefix,
- g_restart_on_valid => false
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
-
- in_sosi_arr => wpfb_unit_in_sosi_arr,
- fil_sosi_arr => wpfb_unit_fil_sosi_arr,
- out_quant_sosi_arr => wpfb_unit_out_quant_sosi_arr,
- out_raw_sosi_arr => wpfb_unit_out_raw_sosi_arr,
-
- dp_bsn_source_restart => dp_bsn_source_restart_pipe
- );
+ generic map (
+ g_wpfb => g_wpfb,
+ g_use_prefilter => true,
+ g_stats_ena => false,
+ g_use_bg => false,
+ g_coefs_file_prefix => c_coefs_file_prefix,
+ g_restart_on_valid => false
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+
+ in_sosi_arr => wpfb_unit_in_sosi_arr,
+ fil_sosi_arr => wpfb_unit_fil_sosi_arr,
+ out_quant_sosi_arr => wpfb_unit_out_quant_sosi_arr,
+ out_raw_sosi_arr => wpfb_unit_out_raw_sosi_arr,
+
+ dp_bsn_source_restart => dp_bsn_source_restart_pipe
+ );
---------------------------------------------------------------
-- SUBBAND EQUALIZER
@@ -341,7 +341,7 @@ begin
-- SUBBAND STATISTICS
---------------------------------------------------------------
gen_stats_streams: for I in 0 to c_sdp_P_pfb - 1 generate
- u_subband_stats : entity st_lib.st_sst
+ u_subband_stats : entity st_lib.st_sst
generic map(
g_nof_stat => c_sdp_N_sub * c_sdp_Q_fft,
g_in_data_w => c_sdp_W_subband,
@@ -366,16 +366,16 @@ begin
-- Combine the internal array of mm interfaces for the subband
-- statistics to one array.
u_mem_mux_sst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_P_pfb,
- g_mult_addr_w => ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * g_wpfb.stat_data_sz)
- )
- port map (
- mosi => master_mem_mux_mosi,
- miso => master_mem_mux_miso,
- mosi_arr => ram_st_sst_mosi_arr,
- miso_arr => ram_st_sst_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_P_pfb,
+ g_mult_addr_w => ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * g_wpfb.stat_data_sz)
+ )
+ port map (
+ mosi => master_mem_mux_mosi,
+ miso => master_mem_mux_miso,
+ mosi_arr => ram_st_sst_mosi_arr,
+ miso_arr => ram_st_sst_miso_arr
+ );
-- Connect 2 mm_masters to the common_mem_mux output
master_mosi_arr(0) <= ram_st_sst_mosi; -- MM access via QSYS MM bus
@@ -384,18 +384,18 @@ begin
ram_st_offload_miso <= master_miso_arr(1);
u_mem_master_mux : entity mm_lib.mm_master_mux
- generic map (
- g_nof_masters => c_nof_masters,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
- )
- port map (
- mm_clk => mm_clk,
-
- master_mosi_arr => master_mosi_arr,
- master_miso_arr => master_miso_arr,
- mux_mosi => master_mem_mux_mosi,
- mux_miso => master_mem_mux_miso
- );
+ generic map (
+ g_nof_masters => c_nof_masters,
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ )
+ port map (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => master_mosi_arr,
+ master_miso_arr => master_miso_arr,
+ mux_mosi => master_mem_mux_mosi,
+ mux_miso => master_mem_mux_miso
+ );
---------------------------------------------------------------
-- STATISTICS OFFLOAD
@@ -403,41 +403,41 @@ begin
weighted_subbands_flag <= not selector_en when rising_edge(dp_clk);
u_sdp_sst_udp_offload: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => "SST",
- g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time)
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_statistics_type => "SST",
+ g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time)
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- master_mosi => ram_st_offload_mosi,
- master_miso => ram_st_offload_miso,
+ master_mosi => ram_st_offload_mosi,
+ master_miso => ram_st_offload_miso,
- reg_enable_mosi => reg_enable_mosi,
- reg_enable_miso => reg_enable_miso,
+ reg_enable_mosi => reg_enable_mosi,
+ reg_enable_miso => reg_enable_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
- in_sosi => dp_selector_quant_sosi_arr(0),
- new_interval => dp_bsn_source_new_interval,
+ in_sosi => dp_selector_quant_sosi_arr(0),
+ new_interval => dp_bsn_source_new_interval,
- out_sosi => sst_udp_sosi,
- out_siso => sst_udp_siso,
+ out_sosi => sst_udp_sosi,
+ out_siso => sst_udp_siso,
- eth_src_mac => eth_src_mac,
- udp_src_port => udp_src_port,
- ip_src_addr => ip_src_addr,
+ eth_src_mac => eth_src_mac,
+ udp_src_port => udp_src_port,
+ ip_src_addr => ip_src_addr,
- gn_index => TO_UINT(gn_id),
- sdp_info => sdp_info,
- weighted_subbands_flag => weighted_subbands_flag
- );
+ gn_index => TO_UINT(gn_id),
+ sdp_info => sdp_info,
+ weighted_subbands_flag => weighted_subbands_flag
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
index 3e9de6c4ba..6f3c98e40c 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
@@ -37,17 +37,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, diag_lib, rTwoSDF_lib, common_mult_lib, fft_lib, wpfb_lib, filter_lib, si_lib, st_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use filter_lib.fil_pkg.all;
-use fft_lib.fft_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use filter_lib.fil_pkg.all;
+ use fft_lib.fft_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_oversampled_filterbank is
generic (
@@ -105,135 +105,137 @@ architecture str of node_sdp_oversampled_filterbank is
-- See node_sdp_filterbank for location and genetion of hex files
constant c_coefs_file_prefix : string := "data/Coeffs16384Kaiser-quant_1wb";
constant c_gains_file_name : string := "data/gains_1024_complex_" &
- natural'image(c_sdp_W_sub_weight) & "b" &
- natural'image(c_sdp_W_sub_weight_fraction) & "f_unit";
-
- constant c_fft : t_fft := func_wpfb_map_wpfb_parameters_to_fft(g_wpfb);
- constant c_fft_complex : t_fft := func_wpfb_map_wpfb_parameters_to_fft(g_wpfb_complex);
- constant c_subband_raw_dat_w : natural := func_fft_raw_dat_w(c_fft);
- constant c_subband_raw_fraction_w : natural := func_fft_raw_fraction_w(c_fft);
- constant c_complex_subband_raw_dat_w : natural := func_fft_raw_dat_w(c_fft_complex);
- constant c_complex_subband_raw_fraction_w : natural := func_fft_raw_fraction_w(c_fft_complex);
- constant c_dat_w_diff : integer := c_complex_subband_raw_dat_w - c_subband_raw_dat_w; -- = -1 which is used to shift 1 bit to the left.
-
- constant c_nof_masters : positive := 2;
-
- constant c_si_pipeline : natural := 1;
- constant c_complex_mult_pipeline : natural := 3;
- constant c_complex_pfb_pipeline : natural := 2;
- constant c_pipeline_remove_lsb : natural := 1; -- to easy timing closure
-
- -- Use WG as local oscillator, buf contains 16b sin and 16b cos
- -- . c_sdp_W_local_oscillator = 16b
- -- . c_sdp_W_local_oscillator_fraction = 16b - 1 sign bit = 15b
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => ceil_log2(2 * c_sdp_N_fft),
- dat_w => c_nof_complex * c_sdp_W_local_oscillator,
- nof_dat => c_sdp_R_os * c_sdp_N_fft,
- init_sl => '0');
-
- constant c_buf_file : string := "data/freq_shift_half_subband_2048x16_im_re.hex";
-
- constant c_wg_ctrl : t_diag_wg := (TO_UVEC(c_diag_wg_mode_repeat, c_diag_wg_mode_w),
- TO_UVEC(c_buf.nof_dat, c_diag_wg_nofsamples_w),
- (others => '0'),
- (others => '0'),
- (others => '0'));
- constant c_wg_phase_offset : natural := 6; -- Compensate for WG start latency. In nof samples.
-
- constant c_fil_coefs_mem_addr_w : natural := ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
-
- signal ram_fil_coefs_mosi_arr : t_mem_mosi_arr(c_sdp_R_os - 1 downto 0) := (others => c_mem_mosi_rst);
- signal ram_fil_coefs_miso_arr : t_mem_miso_arr(c_sdp_R_os - 1 downto 0) := (others => c_mem_miso_rst);
-
- signal ram_st_sst_mosi_arr : t_mem_mosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_mem_mosi_rst);
- signal ram_st_sst_miso_arr : t_mem_miso_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_mem_miso_rst);
-
- -- Subband statistics
- signal ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
- signal ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
-
- signal master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
- signal master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
- signal master_mosi_arr : t_mem_mosi_arr(0 to c_nof_masters - 1) := (others => c_mem_mosi_rst);
- signal master_miso_arr : t_mem_miso_arr(0 to c_nof_masters - 1) := (others => c_mem_miso_rst);
-
- -- WG as local oscillator (LO)
- signal wg_rddata : std_logic_vector(c_buf.dat_w - 1 downto 0);
- signal wg_rdval : std_logic;
- signal wg_address : std_logic_vector(c_buf.adr_w - 1 downto 0);
- signal wg_rom_address : std_logic_vector(c_buf.adr_w - 1 downto 0);
- signal wg_rd : std_logic;
- signal wg_out_dat : std_logic_vector(c_buf.dat_w - 1 downto 0);
-
- -- Spectral Inversion (SI)
- signal si_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
- signal si_sosi_0_piped : t_dp_sosi := c_dp_sosi_rst;
-
- -- Real input FFT
- signal wpfb_unit_in_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_fil_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_out_quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_out_raw_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
-
- -- Mixer to shift f_sub/2
- signal mixer_complex_mult_src_out_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
- signal mixer_complex_requantize_src_out_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
-
- -- Complex input FFT (from LO mixer)
- signal wpfb_unit_complex_in_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_complex_fil_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_complex_out_quant_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_complex_out_raw_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
-
- -- Remove negative frequencies
- signal wpfb_complex_out_resized_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
-
- -- Interleave positive frequencies per factor Q_fft = 2, like with output of real input FFT
- signal wpfb_complex_out_fifo_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_complex_out_fifo_siso_arr : t_dp_siso_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_siso_rst);
- signal wpfb_complex_out_resized_sosi_2arr : t_dp_sosi_2arr_2(c_sdp_P_pfb - 1 downto 0) := (others => (others => c_dp_sosi_rst));
- signal wpfb_complex_out_resized_siso_2arr : t_dp_siso_2arr_2(c_sdp_P_pfb - 1 downto 0) := (others => (others => c_dp_siso_rst));
- signal wpfb_complex_out_interleaved_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
-
- signal subband_equalizer_in_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal subband_equalizer_quant_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal subband_equalizer_raw_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal dp_selector_out_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal dp_selector_pipe_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
-
- signal scope_equalizer_in_sosi_arr : t_dp_sosi_integer_arr(c_sdp_R_os * c_sdp_S_pn - 1 downto 0);
- signal scope_equalizer_out_sosi_arr : t_dp_sosi_integer_arr(c_sdp_R_os * c_sdp_S_pn - 1 downto 0);
-
- signal selector_en : std_logic;
- signal weighted_subbands_flag : std_logic;
-
- signal dp_bsn_source_restart_pipe : std_logic;
- signal dp_bsn_source_restart_delayed : std_logic;
- signal dp_bsn_source_restart_wg : std_logic;
- signal dp_bsn_source_restart_pipe_complex : std_logic;
+ natural'image(c_sdp_W_sub_weight) & "b" &
+ natural'image(c_sdp_W_sub_weight_fraction) & "f_unit";
+
+ constant c_fft : t_fft := func_wpfb_map_wpfb_parameters_to_fft(g_wpfb);
+ constant c_fft_complex : t_fft := func_wpfb_map_wpfb_parameters_to_fft(g_wpfb_complex);
+ constant c_subband_raw_dat_w : natural := func_fft_raw_dat_w(c_fft);
+ constant c_subband_raw_fraction_w : natural := func_fft_raw_fraction_w(c_fft);
+ constant c_complex_subband_raw_dat_w : natural := func_fft_raw_dat_w(c_fft_complex);
+ constant c_complex_subband_raw_fraction_w : natural := func_fft_raw_fraction_w(c_fft_complex);
+ constant c_dat_w_diff : integer := c_complex_subband_raw_dat_w - c_subband_raw_dat_w; -- = -1 which is used to shift 1 bit to the left.
+
+ constant c_nof_masters : positive := 2;
+
+ constant c_si_pipeline : natural := 1;
+ constant c_complex_mult_pipeline : natural := 3;
+ constant c_complex_pfb_pipeline : natural := 2;
+ constant c_pipeline_remove_lsb : natural := 1; -- to easy timing closure
+
+ -- Use WG as local oscillator, buf contains 16b sin and 16b cos
+ -- . c_sdp_W_local_oscillator = 16b
+ -- . c_sdp_W_local_oscillator_fraction = 16b - 1 sign bit = 15b
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(2 * c_sdp_N_fft),
+ dat_w => c_nof_complex * c_sdp_W_local_oscillator,
+ nof_dat => c_sdp_R_os * c_sdp_N_fft,
+ init_sl => '0');
+
+ constant c_buf_file : string := "data/freq_shift_half_subband_2048x16_im_re.hex";
+
+ constant c_wg_ctrl : t_diag_wg := (
+ TO_UVEC(c_diag_wg_mode_repeat, c_diag_wg_mode_w),
+ TO_UVEC(c_buf.nof_dat, c_diag_wg_nofsamples_w),
+ (others => '0'),
+ (others => '0'),
+ (others => '0'));
+ constant c_wg_phase_offset : natural := 6; -- Compensate for WG start latency. In nof samples.
+
+ constant c_fil_coefs_mem_addr_w : natural := ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
+
+ signal ram_fil_coefs_mosi_arr : t_mem_mosi_arr(c_sdp_R_os - 1 downto 0) := (others => c_mem_mosi_rst);
+ signal ram_fil_coefs_miso_arr : t_mem_miso_arr(c_sdp_R_os - 1 downto 0) := (others => c_mem_miso_rst);
+
+ signal ram_st_sst_mosi_arr : t_mem_mosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_mem_mosi_rst);
+ signal ram_st_sst_miso_arr : t_mem_miso_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_mem_miso_rst);
+
+ -- Subband statistics
+ signal ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
+ signal ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
+
+ signal master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
+ signal master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
+ signal master_mosi_arr : t_mem_mosi_arr(0 to c_nof_masters - 1) := (others => c_mem_mosi_rst);
+ signal master_miso_arr : t_mem_miso_arr(0 to c_nof_masters - 1) := (others => c_mem_miso_rst);
+
+ -- WG as local oscillator (LO)
+ signal wg_rddata : std_logic_vector(c_buf.dat_w - 1 downto 0);
+ signal wg_rdval : std_logic;
+ signal wg_address : std_logic_vector(c_buf.adr_w - 1 downto 0);
+ signal wg_rom_address : std_logic_vector(c_buf.adr_w - 1 downto 0);
+ signal wg_rd : std_logic;
+ signal wg_out_dat : std_logic_vector(c_buf.dat_w - 1 downto 0);
+
+ -- Spectral Inversion (SI)
+ signal si_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal si_sosi_0_piped : t_dp_sosi := c_dp_sosi_rst;
+
+ -- Real input FFT
+ signal wpfb_unit_in_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_fil_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_out_quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_out_raw_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ -- Mixer to shift f_sub/2
+ signal mixer_complex_mult_src_out_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal mixer_complex_requantize_src_out_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ -- Complex input FFT (from LO mixer)
+ signal wpfb_unit_complex_in_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_complex_fil_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_complex_out_quant_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_complex_out_raw_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ -- Remove negative frequencies
+ signal wpfb_complex_out_resized_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ -- Interleave positive frequencies per factor Q_fft = 2, like with output of real input FFT
+ signal wpfb_complex_out_fifo_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_complex_out_fifo_siso_arr : t_dp_siso_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_siso_rst);
+ signal wpfb_complex_out_resized_sosi_2arr : t_dp_sosi_2arr_2(c_sdp_P_pfb - 1 downto 0) := (others => (others => c_dp_sosi_rst));
+ signal wpfb_complex_out_resized_siso_2arr : t_dp_siso_2arr_2(c_sdp_P_pfb - 1 downto 0) := (others => (others => c_dp_siso_rst));
+ signal wpfb_complex_out_interleaved_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ signal subband_equalizer_in_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal subband_equalizer_quant_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal subband_equalizer_raw_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal dp_selector_out_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal dp_selector_pipe_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ signal scope_equalizer_in_sosi_arr : t_dp_sosi_integer_arr(c_sdp_R_os * c_sdp_S_pn - 1 downto 0);
+ signal scope_equalizer_out_sosi_arr : t_dp_sosi_integer_arr(c_sdp_R_os * c_sdp_S_pn - 1 downto 0);
+
+ signal selector_en : std_logic;
+ signal weighted_subbands_flag : std_logic;
+
+ signal dp_bsn_source_restart_pipe : std_logic;
+ signal dp_bsn_source_restart_delayed : std_logic;
+ signal dp_bsn_source_restart_wg : std_logic;
+ signal dp_bsn_source_restart_pipe_complex : std_logic;
begin
---------------------------------------------------------------
-- SPECTRAL INVERSION
---------------------------------------------------------------
u_si_arr : entity si_lib.si_arr
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_pipeline => c_si_pipeline,
- g_dat_w => c_sdp_W_adc
- )
- port map(
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => si_sosi_arr,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst
- );
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_pipeline => c_si_pipeline,
+ g_dat_w => c_sdp_W_adc
+ )
+ port map(
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => si_sosi_arr,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst
+ );
---------------------------------------------------------------
-- POLY-PHASE FILTERBANK
@@ -251,42 +253,42 @@ begin
-- pipeline bsn restart signal to keep dp_bsn_source_restart aligned with si_sosi_arr
u_common_pipeline_sl : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_si_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_dat => dp_bsn_source_restart,
- out_dat => dp_bsn_source_restart_pipe
- );
+ generic map (
+ g_pipeline => c_si_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => dp_bsn_source_restart,
+ out_dat => dp_bsn_source_restart_pipe
+ );
-- PFB
u_wpfb_unit_dev : entity wpfb_lib.wpfb_unit_dev
- generic map (
- g_wpfb => g_wpfb,
- g_use_prefilter => true,
- g_stats_ena => false,
- g_use_bg => false,
- g_coefs_file_prefix => c_coefs_file_prefix,
- g_restart_on_valid => false
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_fil_coefs_mosi => ram_fil_coefs_mosi_arr(0),
- ram_fil_coefs_miso => ram_fil_coefs_miso_arr(0),
-
- in_sosi_arr => wpfb_unit_in_sosi_arr,
- fil_sosi_arr => wpfb_unit_fil_sosi_arr,
- out_quant_sosi_arr => wpfb_unit_out_quant_sosi_arr,
- out_raw_sosi_arr => wpfb_unit_out_raw_sosi_arr,
-
- dp_bsn_source_restart => dp_bsn_source_restart_pipe
- );
+ generic map (
+ g_wpfb => g_wpfb,
+ g_use_prefilter => true,
+ g_stats_ena => false,
+ g_use_bg => false,
+ g_coefs_file_prefix => c_coefs_file_prefix,
+ g_restart_on_valid => false
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi_arr(0),
+ ram_fil_coefs_miso => ram_fil_coefs_miso_arr(0),
+
+ in_sosi_arr => wpfb_unit_in_sosi_arr,
+ fil_sosi_arr => wpfb_unit_fil_sosi_arr,
+ out_quant_sosi_arr => wpfb_unit_out_quant_sosi_arr,
+ out_raw_sosi_arr => wpfb_unit_out_raw_sosi_arr,
+
+ dp_bsn_source_restart => dp_bsn_source_restart_pipe
+ );
---------------------------------------------------------------
-- POLY-PHASE COMPLEX FILTERBANK
@@ -295,18 +297,18 @@ begin
-- real part is in LSB and imaginary part in MSB.
-- Waveform buffer
u_buf : entity common_lib.common_rom
- generic map (
- g_ram => c_buf,
- g_init_file => c_buf_file
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- rd_adr => wg_address,
- rd_en => wg_rd,
- rd_val => wg_rdval,
- rd_dat => wg_rddata
- );
+ generic map (
+ g_ram => c_buf,
+ g_init_file => c_buf_file
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ rd_adr => wg_address,
+ rd_en => wg_rd,
+ rd_val => wg_rdval,
+ rd_dat => wg_rddata
+ );
-- Waveform generator as local oscillator.
p_lo_restart : process(dp_clk, dp_rst)
@@ -327,101 +329,101 @@ begin
end process;
u_lo_wg : entity diag_lib.diag_wg
- generic map (
- g_buf_dat_w => c_buf.dat_w,
- g_buf_addr_w => c_buf.adr_w,
- g_rate_offset => c_wg_phase_offset,
- g_calc_support => false
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- restart => dp_bsn_source_restart_wg,
-
- buf_rddat => wg_rddata,
- buf_rdval => wg_rdval,
- buf_addr => wg_address,
- buf_rden => wg_rd,
-
- ctrl => c_wg_ctrl,
-
- out_dat => wg_out_dat,
- out_val => open
- );
-
- -- Complex mult
- gen_complex_mult: for I in 0 to c_sdp_S_pn - 1 generate
- u_common_complex_mult : entity common_mult_lib.common_complex_mult
generic map (
- g_in_a_w => c_sdp_W_local_oscillator, -- = 16
- g_in_b_w => c_sdp_W_adc, -- = 14
- g_out_p_w => c_sdp_W_local_oscillator + c_sdp_W_adc, -- = 16 + 14 = 30
- g_conjugate_b => false
+ g_buf_dat_w => c_buf.dat_w,
+ g_buf_addr_w => c_buf.adr_w,
+ g_rate_offset => c_wg_phase_offset,
+ g_calc_support => false
)
port map (
- clk => dp_clk,
- clken => '1',
- rst => dp_rst,
- in_ar => wg_out_dat(c_sdp_W_local_oscillator - 1 downto 0),
- in_ai => wg_out_dat(2 * c_sdp_W_local_oscillator - 1 downto c_sdp_W_local_oscillator),
- in_br => si_sosi_arr(I).data(c_sdp_W_adc - 1 downto 0),
- in_bi => (others => '0'),
- in_val => si_sosi_arr(I).valid,
- out_pr => mixer_complex_mult_src_out_arr(I).re(c_sdp_W_local_oscillator + c_sdp_W_adc - 1 downto 0),
- out_pi => mixer_complex_mult_src_out_arr(I).im(c_sdp_W_local_oscillator + c_sdp_W_adc - 1 downto 0),
- out_val => mixer_complex_mult_src_out_arr(I).valid
+ rst => dp_rst,
+ clk => dp_clk,
+ restart => dp_bsn_source_restart_wg,
+
+ buf_rddat => wg_rddata,
+ buf_rdval => wg_rdval,
+ buf_addr => wg_address,
+ buf_rden => wg_rd,
+
+ ctrl => c_wg_ctrl,
+
+ out_dat => wg_out_dat,
+ out_val => open
);
+ -- Complex mult
+ gen_complex_mult: for I in 0 to c_sdp_S_pn - 1 generate
+ u_common_complex_mult : entity common_mult_lib.common_complex_mult
+ generic map (
+ g_in_a_w => c_sdp_W_local_oscillator, -- = 16
+ g_in_b_w => c_sdp_W_adc, -- = 14
+ g_out_p_w => c_sdp_W_local_oscillator + c_sdp_W_adc, -- = 16 + 14 = 30
+ g_conjugate_b => false
+ )
+ port map (
+ clk => dp_clk,
+ clken => '1',
+ rst => dp_rst,
+ in_ar => wg_out_dat(c_sdp_W_local_oscillator - 1 downto 0),
+ in_ai => wg_out_dat(2 * c_sdp_W_local_oscillator - 1 downto c_sdp_W_local_oscillator),
+ in_br => si_sosi_arr(I).data(c_sdp_W_adc - 1 downto 0),
+ in_bi => (others => '0'),
+ in_val => si_sosi_arr(I).valid,
+ out_pr => mixer_complex_mult_src_out_arr(I).re(c_sdp_W_local_oscillator + c_sdp_W_adc - 1 downto 0),
+ out_pi => mixer_complex_mult_src_out_arr(I).im(c_sdp_W_local_oscillator + c_sdp_W_adc - 1 downto 0),
+ out_val => mixer_complex_mult_src_out_arr(I).valid
+ );
+
--requantize
u_dp_requantize : entity dp_lib.dp_requantize
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_sdp_W_local_oscillator_fraction,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => 0,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => c_sdp_W_local_oscillator + c_sdp_W_adc,
+ g_out_dat_w => c_sdp_W_adc
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => mixer_complex_mult_src_out_arr(I),
+ -- ST source
+ src_out => mixer_complex_requantize_src_out_arr(I)
+ );
+ end generate;
+
+ -- Pipeline to compensate for complex mult and dp_requantize.
+ u_dp_pipeline : entity dp_lib.dp_pipeline
generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_sdp_W_local_oscillator_fraction,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => true,
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => 0,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => c_sdp_W_local_oscillator + c_sdp_W_adc,
- g_out_dat_w => c_sdp_W_adc
+ g_pipeline => c_complex_mult_pipeline
)
port map (
rst => dp_rst,
clk => dp_clk,
-- ST sink
- snk_in => mixer_complex_mult_src_out_arr(I),
+ snk_in => si_sosi_arr(0),
-- ST source
- src_out => mixer_complex_requantize_src_out_arr(I)
+ src_out => si_sosi_0_piped
);
- end generate;
-
- -- Pipeline to compensate for complex mult and dp_requantize.
- u_dp_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => c_complex_mult_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => si_sosi_arr(0),
- -- ST source
- src_out => si_sosi_0_piped
- );
-- pipeline bsn restart signal to keep dp_bsn_source_restart aligned with si_sosi_arr
u_common_pipeline_sl_cplx : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_complex_mult_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_dat => dp_bsn_source_restart_pipe,
- out_dat => dp_bsn_source_restart_pipe_complex
- );
+ generic map (
+ g_pipeline => c_complex_mult_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => dp_bsn_source_restart_pipe,
+ out_dat => dp_bsn_source_restart_pipe_complex
+ );
process(mixer_complex_requantize_src_out_arr, si_sosi_0_piped)
begin
for I in 0 to c_sdp_S_pn - 1 loop
@@ -433,30 +435,30 @@ begin
-- PFB complex
u_wpfb_unit_dev_complex : entity wpfb_lib.wpfb_unit_dev
- generic map (
- g_wpfb => g_wpfb_complex,
- g_use_prefilter => true,
- g_stats_ena => false,
- g_use_bg => false,
- g_coefs_file_prefix => c_coefs_file_prefix,
- g_restart_on_valid => false
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_fil_coefs_mosi => ram_fil_coefs_mosi_arr(1),
- ram_fil_coefs_miso => ram_fil_coefs_miso_arr(1),
-
- in_sosi_arr => wpfb_unit_complex_in_sosi_arr,
- fil_sosi_arr => wpfb_unit_complex_fil_sosi_arr,
- out_quant_sosi_arr => wpfb_unit_complex_out_quant_sosi_arr,
- out_raw_sosi_arr => wpfb_unit_complex_out_raw_sosi_arr,
-
- dp_bsn_source_restart => dp_bsn_source_restart_pipe_complex
- );
+ generic map (
+ g_wpfb => g_wpfb_complex,
+ g_use_prefilter => true,
+ g_stats_ena => false,
+ g_use_bg => false,
+ g_coefs_file_prefix => c_coefs_file_prefix,
+ g_restart_on_valid => false
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi_arr(1),
+ ram_fil_coefs_miso => ram_fil_coefs_miso_arr(1),
+
+ in_sosi_arr => wpfb_unit_complex_in_sosi_arr,
+ fil_sosi_arr => wpfb_unit_complex_fil_sosi_arr,
+ out_quant_sosi_arr => wpfb_unit_complex_out_quant_sosi_arr,
+ out_raw_sosi_arr => wpfb_unit_complex_out_raw_sosi_arr,
+
+ dp_bsn_source_restart => dp_bsn_source_restart_pipe_complex
+ );
---------------------------------------------------------------
-- Interleave for PFB complex
@@ -493,7 +495,7 @@ begin
snk_in => wpfb_complex_out_resized_sosi_arr(I),
src_out => wpfb_complex_out_fifo_sosi_arr(I),
src_in => wpfb_complex_out_fifo_siso_arr(I)
- );
+ );
end generate;
-- rewire 1d array of 1 X S_pn to 2d array of 2 X P_pfb
@@ -516,7 +518,7 @@ begin
snk_in_arr => wpfb_complex_out_resized_sosi_2arr(I),
snk_out_arr => wpfb_complex_out_resized_siso_2arr(I),
src_out => wpfb_complex_out_interleaved_sosi_arr(I)
- );
+ );
-- Align data width of wpfb_complex output with wpfb_real output as the real wpfb
-- has an extra bit that is used for the FFT seperate function which the complex FFT
@@ -550,16 +552,16 @@ begin
-- COMBINE MEMORY MAPPED INTERFACES OF RAM_FIL_COEFS
---------------------------------------------------------------
u_mem_mux_coef : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_R_os,
- g_mult_addr_w => c_fil_coefs_mem_addr_w
- )
- port map (
- mosi => ram_fil_coefs_mosi,
- miso => ram_fil_coefs_miso,
- mosi_arr => ram_fil_coefs_mosi_arr,
- miso_arr => ram_fil_coefs_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_R_os,
+ g_mult_addr_w => c_fil_coefs_mem_addr_w
+ )
+ port map (
+ mosi => ram_fil_coefs_mosi,
+ miso => ram_fil_coefs_miso,
+ mosi_arr => ram_fil_coefs_mosi_arr,
+ miso_arr => ram_fil_coefs_miso_arr
+ );
---------------------------------------------------------------
-- SUBBAND EQUALIZER
@@ -702,16 +704,16 @@ begin
-- Combine the internal array of mm interfaces for the subband
-- statistics to one array.
u_mem_mux_sst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_R_os * c_sdp_P_pfb,
- g_mult_addr_w => ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * g_wpfb.stat_data_sz)
- )
- port map (
- mosi => master_mem_mux_mosi,
- miso => master_mem_mux_miso,
- mosi_arr => ram_st_sst_mosi_arr,
- miso_arr => ram_st_sst_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_R_os * c_sdp_P_pfb,
+ g_mult_addr_w => ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * g_wpfb.stat_data_sz)
+ )
+ port map (
+ mosi => master_mem_mux_mosi,
+ miso => master_mem_mux_miso,
+ mosi_arr => ram_st_sst_mosi_arr,
+ miso_arr => ram_st_sst_miso_arr
+ );
-- Connect 2 mm_masters to the common_mem_mux output
master_mosi_arr(0) <= ram_st_sst_mosi; -- MM access via QSYS MM bus
@@ -720,18 +722,18 @@ begin
ram_st_offload_miso <= master_miso_arr(1);
u_mem_master_mux : entity mm_lib.mm_master_mux
- generic map (
- g_nof_masters => c_nof_masters,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
- )
- port map (
- mm_clk => mm_clk,
-
- master_mosi_arr => master_mosi_arr,
- master_miso_arr => master_miso_arr,
- mux_mosi => master_mem_mux_mosi,
- mux_miso => master_mem_mux_miso
- );
+ generic map (
+ g_nof_masters => c_nof_masters,
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ )
+ port map (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => master_mosi_arr,
+ master_miso_arr => master_miso_arr,
+ mux_mosi => master_mem_mux_mosi,
+ mux_miso => master_mem_mux_miso
+ );
---------------------------------------------------------------
-- STATISTICS OFFLOAD
@@ -739,41 +741,41 @@ begin
weighted_subbands_flag <= not selector_en when rising_edge(dp_clk);
u_sdp_sst_udp_offload: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => "SST_OS",
- g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time)
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_statistics_type => "SST_OS",
+ g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time)
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- master_mosi => ram_st_offload_mosi,
- master_miso => ram_st_offload_miso,
+ master_mosi => ram_st_offload_mosi,
+ master_miso => ram_st_offload_miso,
- reg_enable_mosi => reg_enable_mosi,
- reg_enable_miso => reg_enable_miso,
+ reg_enable_mosi => reg_enable_mosi,
+ reg_enable_miso => reg_enable_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
- in_sosi => dp_selector_out_sosi_arr(0),
- new_interval => dp_bsn_source_new_interval,
+ in_sosi => dp_selector_out_sosi_arr(0),
+ new_interval => dp_bsn_source_new_interval,
- out_sosi => sst_udp_sosi,
- out_siso => sst_udp_siso,
+ out_sosi => sst_udp_sosi,
+ out_siso => sst_udp_siso,
- eth_src_mac => eth_src_mac,
- udp_src_port => udp_src_port,
- ip_src_addr => ip_src_addr,
+ eth_src_mac => eth_src_mac,
+ udp_src_port => udp_src_port,
+ ip_src_addr => ip_src_addr,
- gn_index => TO_UINT(gn_id),
- sdp_info => sdp_info,
- weighted_subbands_flag => weighted_subbands_flag
- );
+ gn_index => TO_UINT(gn_id),
+ sdp_info => sdp_info,
+ weighted_subbands_flag => weighted_subbands_flag
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
index 8281d80b1b..e8d62d624f 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
@@ -31,11 +31,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_beamformer_local is
generic (
@@ -135,17 +135,17 @@ begin
---------------------------------------------------------------
gen_deinterleave_x_pol : for I in 0 to c_sdp_P_pfb - 1 generate
u_dp_deinterleave_x_pol : entity dp_lib.dp_deinterleave_one_to_n
- generic map(
- g_nof_outputs => c_sdp_Q_fft
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => bf_weights_x_sosi_arr(I),
- src_out_arr(0) => deinterleaved_x_sosi_arr(c_sdp_Q_fft * I),
- src_out_arr(1) => deinterleaved_x_sosi_arr(c_sdp_Q_fft * I + 1)
- );
+ generic map(
+ g_nof_outputs => c_sdp_Q_fft
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => bf_weights_x_sosi_arr(I),
+ src_out_arr(0) => deinterleaved_x_sosi_arr(c_sdp_Q_fft * I),
+ src_out_arr(1) => deinterleaved_x_sosi_arr(c_sdp_Q_fft * I + 1)
+ );
end generate;
---------------------------------------------------------------
@@ -153,17 +153,17 @@ begin
---------------------------------------------------------------
gen_deinterleave_y_pol : for I in 0 to c_sdp_P_pfb - 1 generate
u_dp_deinterleave_y_pol : entity dp_lib.dp_deinterleave_one_to_n
- generic map(
- g_nof_outputs => c_sdp_Q_fft
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => bf_weights_y_sosi_arr(I),
- src_out_arr(0) => deinterleaved_y_sosi_arr(c_sdp_Q_fft * I),
- src_out_arr(1) => deinterleaved_y_sosi_arr(c_sdp_Q_fft * I + 1)
- );
+ generic map(
+ g_nof_outputs => c_sdp_Q_fft
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => bf_weights_y_sosi_arr(I),
+ src_out_arr(0) => deinterleaved_y_sosi_arr(c_sdp_Q_fft * I),
+ src_out_arr(1) => deinterleaved_y_sosi_arr(c_sdp_Q_fft * I + 1)
+ );
end generate;
---------------------------------------------------------------
@@ -171,48 +171,48 @@ begin
---------------------------------------------------------------
gen_interleave : for I in 0 to c_sdp_S_pn - 1 generate
u_dp_interleave : entity dp_lib.dp_interleave_n_to_one
+ generic map(
+ g_nof_inputs => c_sdp_N_pol_bf
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in_arr(0) => deinterleaved_x_sosi_arr(I),
+ snk_in_arr(1) => deinterleaved_y_sosi_arr(I),
+ src_out => interleave_out_sosi_arr(I)
+ );
+ end generate;
+
+ ---------------------------------------------------------------
+ -- ADD
+ ---------------------------------------------------------------
+ u_dp_complex_add : entity dp_lib.dp_complex_add
generic map(
- g_nof_inputs => c_sdp_N_pol_bf
+ g_nof_inputs => c_sdp_S_pn,
+ g_data_w => c_product_w
)
port map(
rst => dp_rst,
clk => dp_clk,
- snk_in_arr(0) => deinterleaved_x_sosi_arr(I),
- snk_in_arr(1) => deinterleaved_y_sosi_arr(I),
- src_out => interleave_out_sosi_arr(I)
+ snk_in_arr => interleave_out_sosi_arr,
+ src_out => complex_add_out_sosi
);
- end generate;
-
- ---------------------------------------------------------------
- -- ADD
- ---------------------------------------------------------------
- u_dp_complex_add : entity dp_lib.dp_complex_add
- generic map(
- g_nof_inputs => c_sdp_S_pn,
- g_data_w => c_product_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in_arr => interleave_out_sosi_arr,
- src_out => complex_add_out_sosi
- );
---------------------------------------------------------------
-- DP PIPELINE IN_SOSI FIELDS
---------------------------------------------------------------
u_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => c_total_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => in_sosi_arr(0),
- src_out => pipelined_in_sosi
- );
+ generic map (
+ g_pipeline => c_total_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => in_sosi_arr(0),
+ src_out => pipelined_in_sosi
+ );
---------------------------------------------------------------
-- COMBINE OUTPUT WITH PIPELINED IN_SOSI
@@ -228,25 +228,25 @@ begin
-- REQUANTIZE
---------------------------------------------------------------
u_dp_requantize : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_sdp_W_bf_weight_fraction + g_raw_fraction_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false, -- wrap beamlet overflow
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => 1,
- g_pipeline_remove_msb => 0, -- no msb clipping, so no need for pipeline
- g_in_dat_w => c_complex_adder_sum_w,
- g_out_dat_w => c_sdp_W_beamlet_sum
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => dp_requantize_in_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_sdp_W_bf_weight_fraction + g_raw_fraction_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false, -- wrap beamlet overflow
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => 1,
+ g_pipeline_remove_msb => 0, -- no msb clipping, so no need for pipeline
+ g_in_dat_w => c_complex_adder_sum_w,
+ g_out_dat_w => c_sdp_W_beamlet_sum
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => dp_requantize_in_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
index 210c308c65..f8540524bb 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
@@ -31,20 +31,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_beamformer_output is
generic (
g_beamset_id : natural := 0
- );
+ );
port (
dp_clk : in std_logic;
dp_rst : in std_logic;
@@ -135,7 +135,7 @@ begin
v_ref_time := v_ref_time + c_sdp_block_period * 1 ns;
end if;
elsif NOW > v_ref_time + 1 * c_sdp_cep_nof_blocks_per_packet * c_sdp_block_period * 1 ns and
- NOW < v_ref_time + 4 * c_sdp_cep_nof_blocks_per_packet * c_sdp_block_period * 1 ns then
+ NOW < v_ref_time + 4 * c_sdp_cep_nof_blocks_per_packet * c_sdp_block_period * 1 ns then
-- Disturb BSN to cause merged payload error. Expected results for the merged blocks:
-- . index 0 : First merged block bsn ok and payload_error = '0'.
-- . index 1 : bsn still ok, but payload error = '1', due to bsn++ after first block
@@ -157,64 +157,65 @@ begin
-- . We don't need to flow control the source because we're going from 16b->64b
-------------------------------------------------------------------------------
u_dp_repack_data : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_data_w,
- g_in_nof_words => 4,
- g_out_dat_w => c_longword_w,
- g_out_nof_words => 1
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
-
- snk_in => snk_in_concat,
- snk_out => OPEN,
-
- src_out => dp_repack_data_src_out,
- src_in => c_dp_siso_rdy
- );
+ generic map (
+ g_in_dat_w => c_data_w,
+ g_in_nof_words => 4,
+ g_out_dat_w => c_longword_w,
+ g_out_nof_words => 1
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in => snk_in_concat,
+ snk_out => OPEN,
+
+ src_out => dp_repack_data_src_out,
+ src_in => c_dp_siso_rdy
+ );
-------------------------------------------------------------------------------
-- dp_packet_merge
-------------------------------------------------------------------------------
u_dp_packet_merge : entity dp_lib.dp_packet_merge
- generic map(
- g_nof_pkt => c_sdp_cep_nof_blocks_per_packet,
- g_bsn_increment => 1
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => OPEN,
- snk_in => dp_repack_data_src_out,
-
- src_in => c_dp_siso_rdy,
- src_out => dp_packet_merge_src_out
- );
+ generic map(
+ g_nof_pkt => c_sdp_cep_nof_blocks_per_packet,
+ g_bsn_increment => 1
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => OPEN,
+ snk_in => dp_repack_data_src_out,
+
+ src_in => c_dp_siso_rdy,
+ src_out => dp_packet_merge_src_out
+ );
-------------------------------------------------------------------------------
-- FIFO
-------------------------------------------------------------------------------
u_dp_fifo_fill_eop_sc : entity dp_lib.dp_fifo_fill_eop_sc
- generic map ( -- pass on dp_packet_merge_src_out.err via u_common_fifo_sc_err
- g_data_w => c_longword_w,
- g_empty_w => c_byte_w,
- g_use_empty => true,
- g_use_bsn => true,
- g_bsn_w => 64,
- g_use_sync => true,
- g_fifo_size => c_fifo_size,
- g_fifo_fill => c_fifo_fill,
- g_fifo_rl => 1
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
- snk_in => dp_packet_merge_src_out,
- src_out => dp_fifo_merge_src_out,
- src_in => dp_fifo_merge_src_in
- );
+ generic map (
+ -- pass on dp_packet_merge_src_out.err via u_common_fifo_sc_err
+ g_data_w => c_longword_w,
+ g_empty_w => c_byte_w,
+ g_use_empty => true,
+ g_use_bsn => true,
+ g_bsn_w => 64,
+ g_use_sync => true,
+ g_fifo_size => c_fifo_size,
+ g_fifo_fill => c_fifo_fill,
+ g_fifo_rl => 1
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+ snk_in => dp_packet_merge_src_out,
+ src_out => dp_fifo_merge_src_out,
+ src_in => dp_fifo_merge_src_in
+ );
-- Simple fifo to store the payload error bit at eop of FIFO input to be used at sop of FIFO
-- output, so that payload_err can then be used in the packet header.
@@ -222,34 +223,34 @@ begin
-- Choose g_nof_words > c_sdp_N_beamsets to have some margin compared to c_fifo_size of the
-- data FIFO.
u_common_fifo_sc_err : entity common_lib.common_fifo_sc
- generic map (
- g_dat_w => 1,
- g_nof_words => c_sdp_N_beamsets + 2
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- wr_dat => dp_packet_merge_src_out.err(0 downto 0),
- wr_req => dp_packet_merge_src_out.eop,
- rd_dat => payload_err,
- rd_req => dp_fifo_merge_src_out.sop
- );
+ generic map (
+ g_dat_w => 1,
+ g_nof_words => c_sdp_N_beamsets + 2
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ wr_dat => dp_packet_merge_src_out.err(0 downto 0),
+ wr_req => dp_packet_merge_src_out.eop,
+ rd_dat => payload_err,
+ rd_req => dp_fifo_merge_src_out.sop
+ );
-- Pipeline FIFO output to align payload_err at dp_pipeline_src_out.sop
u_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out => dp_fifo_merge_src_in,
- snk_in => dp_fifo_merge_src_out,
- -- ST source
- src_in => dp_pipeline_src_in,
- src_out => dp_pipeline_src_out
- );
+ generic map (
+ g_pipeline => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => dp_fifo_merge_src_in,
+ snk_in => dp_fifo_merge_src_out,
+ -- ST source
+ src_in => dp_pipeline_src_in,
+ src_out => dp_pipeline_src_out
+ );
-------------------------------------------------------------------------------
-- Assemble offload info
@@ -341,87 +342,87 @@ begin
-- dp_offload_tx_v3
-------------------------------------------------------------------------------
u_dp_offload_tx_v3 : entity dp_lib.dp_offload_tx_v3
- generic map (
- g_nof_streams => 1,
- g_data_w => c_longword_w,
- g_symbol_w => c_byte_w,
- g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
- g_hdr_field_sel => c_sdp_cep_hdr_field_sel,
- g_pipeline_ready => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
-
- snk_in_arr(0) => dp_pipeline_src_out,
- snk_out_arr(0) => dp_pipeline_src_in,
-
- src_out_arr(0) => dp_offload_tx_src_out,
- src_in_arr(0) => dp_offload_tx_src_in,
-
- hdr_fields_in_arr(0) => dp_offload_tx_hdr_fields,
- hdr_fields_out_arr(0) => hdr_fields_out
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_longword_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_hdr_field_sel => c_sdp_cep_hdr_field_sel,
+ g_pipeline_ready => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+
+ snk_in_arr(0) => dp_pipeline_src_out,
+ snk_out_arr(0) => dp_pipeline_src_in,
+
+ src_out_arr(0) => dp_offload_tx_src_out,
+ src_in_arr(0) => dp_offload_tx_src_in,
+
+ hdr_fields_in_arr(0) => dp_offload_tx_hdr_fields,
+ hdr_fields_out_arr(0) => hdr_fields_out
+ );
-------------------------------------------------------------------------------
-- tr_10GbE_ip_checksum
-------------------------------------------------------------------------------
u_tr_10GbE_ip_checksum : entity tr_10GbE_lib.tr_10GbE_ip_checksum
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- snk_in => dp_offload_tx_src_out,
- snk_out => dp_offload_tx_src_in,
+ snk_in => dp_offload_tx_src_out,
+ snk_out => dp_offload_tx_src_in,
- src_out => ip_checksum_src_out,
- src_in => ip_checksum_src_in
- );
+ src_out => ip_checksum_src_out,
+ src_in => ip_checksum_src_in
+ );
-------------------------------------------------------------------------------
-- dp_pipeline_ready to ease timing closure
-------------------------------------------------------------------------------
u_dp_pipeline_ready : entity dp_lib.dp_pipeline_ready
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => ip_checksum_src_in,
- snk_in => ip_checksum_src_out,
- src_in => dp_pipeline_ready_src_in,
- src_out => dp_pipeline_ready_src_out
- );
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => ip_checksum_src_in,
+ snk_in => ip_checksum_src_out,
+ src_in => dp_pipeline_ready_src_in,
+ src_out => dp_pipeline_ready_src_out
+ );
-------------------------------------------------------------------------------
-- mms_dp_xonoff
-------------------------------------------------------------------------------
u_mms_dp_xonoff : entity dp_lib.mms_dp_xonoff
- generic map(
- g_default_value => '0'
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_dp_xonoff_mosi,
- reg_miso => reg_dp_xonoff_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- ST sinks
- snk_out_arr(0) => dp_pipeline_ready_src_in,
- snk_in_arr(0) => dp_pipeline_ready_src_out,
- -- ST source
- src_in_arr(0) => out_siso,
- src_out_arr(0) => out_sosi
- );
+ generic map(
+ g_default_value => '0'
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_xonoff_mosi,
+ reg_miso => reg_dp_xonoff_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- ST sinks
+ snk_out_arr(0) => dp_pipeline_ready_src_in,
+ snk_in_arr(0) => dp_pipeline_ready_src_out,
+ -- ST source
+ src_in_arr(0) => out_siso,
+ src_out_arr(0) => out_sosi
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
index 11f74388b5..2105f6edf9 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
@@ -30,11 +30,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_beamformer_remote is
port (
@@ -87,84 +87,84 @@ begin
-- FIFO
---------------------------------------------------------------
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
- generic map (
- g_data_w => c_longword_w,
- g_bsn_w => c_dp_stream_bsn_w,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => c_fifo_size
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => from_ri_sosi,
- src_in => dp_fifo_siso,
- src_out => dp_fifo_sosi
- );
+ generic map (
+ g_data_w => c_longword_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => c_fifo_size
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => from_ri_sosi,
+ src_in => dp_fifo_siso,
+ src_out => dp_fifo_sosi
+ );
---------------------------------------------------------------
-- Repack 64b to 36b
---------------------------------------------------------------
u_dp_repack_data_rx : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_longword_w,
- g_in_nof_words => 9, -- 9/16 = 36/64
- g_out_dat_w => c_data_w,
- g_out_nof_words => 16, -- 9/16 = 36/64
- g_pipeline_ready => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_fifo_sosi,
- snk_out => dp_fifo_siso,
- src_out => dispatch_sosi_arr(1)
- );
+ generic map (
+ g_in_dat_w => c_longword_w,
+ g_in_nof_words => 9, -- 9/16 = 36/64
+ g_out_dat_w => c_data_w,
+ g_out_nof_words => 16, -- 9/16 = 36/64
+ g_pipeline_ready => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => dp_fifo_sosi,
+ snk_out => dp_fifo_siso,
+ src_out => dispatch_sosi_arr(1)
+ );
---------------------------------------------------------------
-- dp_bsn_aligner_v2
---------------------------------------------------------------
u_mmp_dp_bsn_align_v2 : entity dp_lib.mmp_dp_bsn_align_v2
- generic map(
- -- for dp_bsn_align_v2
- g_nof_streams => c_dual,
- g_bsn_latency_max => 2, -- max 2 blocks latency
- g_nof_aligners_max => c_sdp_N_pn_max,
- g_block_size => c_block_size,
- g_data_w => c_data_w,
- g_use_mm_output => false,
- g_rd_latency => 1,
- -- for mms_dp_bsn_monitor_v2
- g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout, -- Using c_sdp_N_clk_sync_timeout as g_nof_clk_per_sync is used for BSN monitor timeout.
- g_nof_input_bsn_monitors => c_dual,
- g_use_bsn_output_monitor => true
+ generic map(
+ -- for dp_bsn_align_v2
+ g_nof_streams => c_dual,
+ g_bsn_latency_max => 2, -- max 2 blocks latency
+ g_nof_aligners_max => c_sdp_N_pn_max,
+ g_block_size => c_block_size,
+ g_data_w => c_data_w,
+ g_use_mm_output => false,
+ g_rd_latency => 1,
+ -- for mms_dp_bsn_monitor_v2
+ g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout, -- Using c_sdp_N_clk_sync_timeout as g_nof_clk_per_sync is used for BSN monitor timeout.
+ g_nof_input_bsn_monitors => c_dual,
+ g_use_bsn_output_monitor => true
)
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_bsn_align_copi => reg_bsn_align_copi,
- reg_bsn_align_cipo => reg_bsn_align_cipo,
+ reg_bsn_align_copi => reg_bsn_align_copi,
+ reg_bsn_align_cipo => reg_bsn_align_cipo,
- reg_input_monitor_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
- reg_input_monitor_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
+ reg_input_monitor_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
+ reg_input_monitor_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
- reg_output_monitor_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
- reg_output_monitor_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
+ reg_output_monitor_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
+ reg_output_monitor_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- node_index => rn_index,
+ node_index => rn_index,
- -- Streaming input
- in_sosi_arr => dispatch_sosi_arr,
- out_sosi_arr => beamlets_data_sosi_arr
- );
+ -- Streaming input
+ in_sosi_arr => dispatch_sosi_arr,
+ out_sosi_arr => beamlets_data_sosi_arr
+ );
-- repacking beamlets data to re/im field.
p_wire_beamlets_sosi : process(beamlets_data_sosi_arr)
@@ -181,17 +181,17 @@ begin
-- ADD local + remote
---------------------------------------------------------------
u_dp_complex_add : entity dp_lib.dp_complex_add
- generic map(
- g_nof_inputs => c_dual,
- g_data_w => c_sdp_W_beamlet_sum
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in_arr => beamlets_sosi_arr,
- src_out => i_bf_sum_sosi
- );
+ generic map(
+ g_nof_inputs => c_dual,
+ g_data_w => c_sdp_W_beamlet_sum
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in_arr => beamlets_sosi_arr,
+ src_out => i_bf_sum_sosi
+ );
---------------------------------------------------------------
-- Local output
@@ -211,18 +211,18 @@ begin
end process;
u_dp_repack_data_local : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_data_w,
- g_in_nof_words => 16, -- 16/9 = 64/36
- g_out_dat_w => c_longword_w,
- g_out_nof_words => 9, -- 16/9 = 64/36
- g_pipeline_ready => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => bf_sum_data_sosi,
- src_out => to_ri_sosi
- );
+ generic map (
+ g_in_dat_w => c_data_w,
+ g_in_nof_words => 16, -- 16/9 = 64/36
+ g_out_dat_w => c_longword_w,
+ g_out_nof_words => 9, -- 16/9 = 64/36
+ g_pipeline_ready => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => bf_sum_data_sosi,
+ src_out => to_ri_sosi
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
index 567bc51fb6..f5e351adef 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
@@ -35,11 +35,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_bf_weights is
generic (
@@ -118,31 +118,31 @@ begin
-- Gain
---------------------------------------------------------------
u_mms_dp_gain_serial_arr : entity dp_lib.mms_dp_gain_serial_arr
- generic map (
- g_nof_streams => c_sdp_N_pol_bf * c_sdp_P_pfb,
- g_nof_gains => c_sdp_Q_fft * c_sdp_S_sub_bf,
- g_complex_data => true,
- g_complex_gain => true,
- g_gain_w => c_sdp_W_bf_weight,
- g_in_dat_w => g_raw_dat_w,
- g_out_dat_w => c_gain_out_dat_w,
- g_gains_file_name => g_gains_file_name
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_nof_streams => c_sdp_N_pol_bf * c_sdp_P_pfb,
+ g_nof_gains => c_sdp_Q_fft * c_sdp_S_sub_bf,
+ g_complex_data => true,
+ g_complex_gain => true,
+ g_gain_w => c_sdp_W_bf_weight,
+ g_in_dat_w => g_raw_dat_w,
+ g_out_dat_w => c_gain_out_dat_w,
+ g_gains_file_name => g_gains_file_name
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- MM interface
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso,
+ -- MM interface
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
- -- ST interface
- gains_rd_address => gains_rd_address,
+ -- ST interface
+ gains_rd_address => gains_rd_address,
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => out_sosi_arr
- );
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => out_sosi_arr
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
index 9296c03492..a26b43953b 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
@@ -45,12 +45,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, reorder_lib, st_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_crosslets_subband_select is
generic (
@@ -130,48 +130,48 @@ begin
-- BSN sync scheduler
---------------------------------------------------------------
u_mmp_dp_bsn_sync_scheduler_arr : entity dp_lib.mmp_dp_bsn_sync_scheduler_arr
- generic map (
- g_nof_streams => c_sdp_P_pfb,
- g_block_size => c_sdp_N_fft,
- g_ctrl_interval_size_min => g_ctrl_interval_size_min
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_sync_scheduler_xsub_mosi,
- reg_miso => reg_bsn_sync_scheduler_xsub_miso,
-
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
-
- out_start => start_trigger,
- out_start_interval => new_interval
- );
+ generic map (
+ g_nof_streams => c_sdp_P_pfb,
+ g_block_size => c_sdp_N_fft,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_miso => reg_bsn_sync_scheduler_xsub_miso,
+
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
+
+ out_start => start_trigger,
+ out_start_interval => new_interval
+ );
---------------------------------------------------------------
-- Crosslets info
---------------------------------------------------------------
u_crosslets_info : entity common_lib.mms_common_reg
- generic map(
- g_mm_reg => c_sdp_mm_reg_crosslets_info
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- MM bus access in memory-mapped clock domain
- reg_mosi => reg_crosslets_info_mosi,
- reg_miso => reg_crosslets_info_miso,
-
- in_reg => crosslets_info_reg_in,
- out_reg => crosslets_info_reg
- );
+ generic map(
+ g_mm_reg => c_sdp_mm_reg_crosslets_info
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- MM bus access in memory-mapped clock domain
+ reg_mosi => reg_crosslets_info_mosi,
+ reg_miso => reg_crosslets_info_miso,
+
+ in_reg => crosslets_info_reg_in,
+ out_reg => crosslets_info_reg
+ );
p_set_unused_crosslets : process(cur_crosslets_info)
begin
@@ -266,62 +266,62 @@ begin
col_select_mosi <= r.col_select_mosi;
-- pipeline to time row select
u_pipe_row_select : entity common_lib.common_pipeline
- generic map(
- g_pipeline => c_row_select_pipeline,
- g_in_dat_w => c_row_select_slv_w,
- g_out_dat_w => c_row_select_slv_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- in_dat => r.row_select_slv,
- out_dat => row_select_slv
- );
+ generic map(
+ g_pipeline => c_row_select_pipeline,
+ g_in_dat_w => c_row_select_slv_w,
+ g_out_dat_w => c_row_select_slv_w
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => r.row_select_slv,
+ out_dat => row_select_slv
+ );
---------------------------------------------------------------
-- Crosslet Select
---------------------------------------------------------------
u_reorder_col_wide_select : entity reorder_lib.reorder_col_wide_select
- generic map (
- g_nof_inputs => c_sdp_P_pfb,
- g_dsp_data_w => c_sdp_W_crosslet,
- g_nof_ch_in => c_sdp_N_sub * c_sdp_Q_fft,
- g_nof_ch_sel => g_N_crosslets * c_sdp_S_pn
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped
- col_select_mosi => col_select_mosi,
- col_select_miso => col_select_miso,
-
- -- Streaming
- input_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
-
- output_sosi_arr => col_sosi_arr
- );
+ generic map (
+ g_nof_inputs => c_sdp_P_pfb,
+ g_dsp_data_w => c_sdp_W_crosslet,
+ g_nof_ch_in => c_sdp_N_sub * c_sdp_Q_fft,
+ g_nof_ch_sel => g_N_crosslets * c_sdp_S_pn
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped
+ col_select_mosi => col_select_mosi,
+ col_select_miso => col_select_miso,
+
+ -- Streaming
+ input_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
+
+ output_sosi_arr => col_sosi_arr
+ );
u_reorder_row_select : entity reorder_lib.reorder_row_select
- generic map (
- g_dsp_data_w => c_sdp_W_crosslet,
- g_nof_inputs => c_sdp_P_pfb,
- g_nof_outputs => 1,
- g_pipeline_in => 0,
- g_pipeline_in_m => 1,
- g_pipeline_out => 1
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_select => row_select_slv,
-
- -- Streaming
- input_sosi_arr => col_sosi_arr,
-
- output_sosi_arr(0) => row_sosi
- );
+ generic map (
+ g_dsp_data_w => c_sdp_W_crosslet,
+ g_nof_inputs => c_sdp_P_pfb,
+ g_nof_outputs => 1,
+ g_pipeline_in => 0,
+ g_pipeline_in_m => 1,
+ g_pipeline_out => 1
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_select => row_select_slv,
+
+ -- Streaming
+ input_sosi_arr => col_sosi_arr,
+
+ output_sosi_arr(0) => row_sosi
+ );
---------------------------------------------------------------
-- Out Crosslet info pipeline
@@ -334,48 +334,48 @@ begin
-- pipeline for alignment with sync
u_common_pipeline_cur : entity common_lib.common_pipeline
- generic map(
- g_pipeline => c_crosslets_info_dly,
- g_in_dat_w => c_sdp_crosslets_info_reg_w,
- g_out_dat_w => c_sdp_crosslets_info_reg_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- in_en => row_sosi.sync,
- in_dat => active_crosslets_info,
- out_dat => cur_crosslets_info
- );
+ generic map(
+ g_pipeline => c_crosslets_info_dly,
+ g_in_dat_w => c_sdp_crosslets_info_reg_w,
+ g_out_dat_w => c_sdp_crosslets_info_reg_w
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ in_en => row_sosi.sync,
+ in_dat => active_crosslets_info,
+ out_dat => cur_crosslets_info
+ );
u_common_pipeline_prev : entity common_lib.common_pipeline
- generic map(
- g_pipeline => c_crosslets_info_dly,
- g_in_dat_w => c_sdp_crosslets_info_reg_w,
- g_out_dat_w => c_sdp_crosslets_info_reg_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- in_en => row_sosi.sync,
- in_dat => cur_crosslets_info,
- out_dat => prev_crosslets_info
- );
+ generic map(
+ g_pipeline => c_crosslets_info_dly,
+ g_in_dat_w => c_sdp_crosslets_info_reg_w,
+ g_out_dat_w => c_sdp_crosslets_info_reg_w
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ in_en => row_sosi.sync,
+ in_dat => cur_crosslets_info,
+ out_dat => prev_crosslets_info
+ );
---------------------------------------------------------------
-- Out sosi pipeline
---------------------------------------------------------------
u_dp_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => c_out_sosi_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => row_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_pipeline => c_out_sosi_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => row_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
-- Map crosslets_info slv to record for easier view in Wave window
crosslets_info_rec <= func_sdp_map_crosslets_info(crosslets_info_reg);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
index ba93d5bf24..7af75ff31a 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
@@ -33,11 +33,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_info is
port (
@@ -65,21 +65,21 @@ architecture str of sdp_info is
signal block_period: std_logic_vector(15 downto 0);
begin
u_mm_fields: entity work.sdp_info_reg
- port map (
+ port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
- -- sdp info
- sdp_info_ro => sdp_info_ro,
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info_ro => sdp_info_ro,
+ sdp_info => sdp_info
+ );
-- f_adc : '0' => 160M, '1' => 200M
-- fsub_type: '0' => critical sampled PFB, '1' => oversampled PFB
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
index 3feac6001a..2037a3e5f4 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
@@ -33,11 +33,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_info_reg is
port (
@@ -58,16 +58,17 @@ entity sdp_info_reg is
end sdp_info_reg;
architecture str of sdp_info_reg is
- constant c_field_arr : t_common_field_arr(8 downto 0) :=
- ( (field_name_pad("antenna_field_index"), "RW", 6, field_default(0)), -- = station_info[15:10]
- (field_name_pad("station_id"), "RW", 10, field_default(0)), -- = station_info[9:0]
- (field_name_pad("antenna_band_index"), "RW", 1, field_default(0)),
- (field_name_pad("observation_id"), "RW", 32, field_default(0)),
- (field_name_pad("nyquist_zone_index"), "RW", 2, field_default(0)),
- (field_name_pad("f_adc"), "RO", 1, field_default(0)),
- (field_name_pad("fsub_type"), "RO", 1, field_default(0)),
- (field_name_pad("beam_repositioning_flag"), "RW", 1, field_default(0)),
- (field_name_pad("block_period"), "RO", 16, field_default(0)) );
+ constant c_field_arr : t_common_field_arr(
+ 8 downto 0) :=
+ ( (field_name_pad("antenna_field_index"), "RW", 6, field_default(0)), -- = station_info[15:10]
+ (field_name_pad("station_id"), "RW", 10, field_default(0)), -- = station_info[9:0]
+ (field_name_pad("antenna_band_index"), "RW", 1, field_default(0)),
+ (field_name_pad("observation_id"), "RW", 32, field_default(0)),
+ (field_name_pad("nyquist_zone_index"), "RW", 2, field_default(0)),
+ (field_name_pad("f_adc"), "RO", 1, field_default(0)),
+ (field_name_pad("fsub_type"), "RO", 1, field_default(0)),
+ (field_name_pad("beam_repositioning_flag"), "RW", 1, field_default(0)),
+ (field_name_pad("block_period"), "RO", 16, field_default(0)) );
signal mm_fields_in : std_logic_vector(field_slv_in_len(c_field_arr) - 1 downto 0);
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_field_arr) - 1 downto 0);
@@ -89,25 +90,25 @@ begin
end process;
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi,
- mm_miso => reg_miso,
+ mm_mosi => reg_mosi,
+ mm_miso => reg_miso,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_in => mm_fields_in,
- slv_in_val => '1',
+ slv_in => mm_fields_in,
+ slv_in_val => '1',
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
-- add "RO" fields to mm_fields
mm_fields_in(field_hi(c_field_arr, "f_adc") downto field_lo(c_field_arr, "f_adc")) <= slv(sdp_info_rd.f_adc);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index e9dc687166..28770a8cf1 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -28,18 +28,18 @@
-- . [1] https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+SDP+Parameter+definitions
-------------------------------------------------------------------------------
library IEEE, common_lib, rTwoSDF_lib, fft_lib, filter_lib, wpfb_lib, diag_lib, tech_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use diag_lib.diag_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use fft_lib.fft_pkg.all;
-use filter_lib.fil_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use tech_jesd204b_lib.tech_jesd204b_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use fft_lib.fft_pkg.all;
+ use filter_lib.fil_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use tech_jesd204b_lib.tech_jesd204b_pkg.all;
package sdp_pkg is
-------------------------------------------------
@@ -59,9 +59,9 @@ package sdp_pkg is
end record;
constant c_sdp_info_rst : t_sdp_info :=
- ( (others => '0'), (others => '0'), '0', (others => '0'), (others => '0'),
- '0', '0', '0',
- (others => '0') );
+ ( (others => '0'), (others => '0'), '0', (others => '0'), (others => '0'),
+ '0', '0', '0',
+ (others => '0') );
-------------------------------------------------
-- SDP specific parameters as defined in [1]
@@ -219,11 +219,11 @@ package sdp_pkg is
constant c_sdp_wpfb_subbands : t_wpfb :=
(1, c_sdp_N_fft, 0, c_sdp_P_pfb,
- c_sdp_N_taps, c_sdp_W_fil_backoff, c_sdp_W_adc, c_sdp_W_fft_in_dat, c_sdp_W_fir_coef,
- true, false, true,
- c_sdp_W_fft_in_dat, c_sdp_W_subband, c_sdp_W_fft_out_gain, c_sdp_W_fft_stage_dat, c_sdp_W_fft_guard, true,
- c_sdp_W_stat_data, c_sdp_W_statistic_sz, c_sdp_N_int_sub_hi,
- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- = c_wpfb_lofar2_subbands_l2ts_18b
+ c_sdp_N_taps, c_sdp_W_fil_backoff, c_sdp_W_adc, c_sdp_W_fft_in_dat, c_sdp_W_fir_coef,
+ true, false, true,
+ c_sdp_W_fft_in_dat, c_sdp_W_subband, c_sdp_W_fft_out_gain, c_sdp_W_fft_stage_dat, c_sdp_W_fft_guard, true,
+ c_sdp_W_stat_data, c_sdp_W_statistic_sz, c_sdp_N_int_sub_hi,
+ c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- = c_wpfb_lofar2_subbands_l2ts_18b
constant c_sdp_wpfb_complex_subbands : t_wpfb := func_wpfb_map_real_input_wpfb_parameters_to_complex_input(c_sdp_wpfb_subbands);
@@ -286,59 +286,60 @@ package sdp_pkg is
-- and default hdr_fields_in_arr = 0 or via MM controlled and field_default(0).
-- eth ip udp app
constant c_sdp_stat_hdr_field_sel : std_logic_vector(c_sdp_stat_nof_hdr_fields - 1 downto 0) := "1" & "101" & "111011111001" & "0100" & "0100" & "00000000" & "1000000" & "0"; -- current
---CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "1"&"101"&"111011111001"&"0101"&"0100"&"00000000"&"0000100"&"0"; -- previous 26 nov 2021
---CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "0"&"100"&"000000010001"&"0100"&"0100"&"00000000"&"1000000"&"0"; -- initial
+ --CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "1"&"101"&"111011111001"&"0101"&"0100"&"00000000"&"0000100"&"0"; -- previous 26 nov 2021
+ --CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "0"&"100"&"000000010001"&"0100"&"0100"&"00000000"&"1000000"&"0"; -- initial
-- Default use destination MAC/IP/UDP = 0, so these have to be MM programmed before
-- statistics offload packets can be send.
- constant c_sdp_stat_hdr_field_arr : t_common_field_arr(c_sdp_stat_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("word_align" ), "RW", 16, field_default(0) ), -- Tx TSE IP will strip these 2 padding bytes
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ), -- c_sdp_stat_eth_dst_mac
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
-
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ), -- differs for SST, BST, XST so set by data path
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_sdp_stat_ip_dst_addr
-
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_sdp_stat_udp_dst_port
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ), -- differs for SST, BST, XST so set by data path
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
-
- ( field_name_pad("sdp_marker" ), "RW", 8, field_default(0) ), -- differs for SST, BST, XST so set by data path
- ( field_name_pad("sdp_version_id" ), "RW", 8, field_default(c_sdp_stat_version_id) ),
- ( field_name_pad("sdp_observation_id" ), "RW", 32, field_default(0) ),
- ( field_name_pad("sdp_station_info" ), "RW", 16, field_default(0) ),
-
- ( field_name_pad("sdp_source_info_antenna_band_id" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_nyquist_zone_id" ), "RW", 2, field_default(0) ),
- ( field_name_pad("sdp_source_info_f_adc" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_fsub_type" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_payload_error" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_beam_repositioning_flag" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_weighted_subbands_flag" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_gn_id" ), "RW", 8, field_default(0) ),
-
- ( field_name_pad("sdp_reserved" ), "RW", 8, field_default(0) ),
- ( field_name_pad("sdp_integration_interval" ), "RW", 24, field_default(0) ),
- ( field_name_pad("sdp_data_id" ), "RW", 32, field_default(0) ),
- ( field_name_pad("sdp_nof_signal_inputs" ), "RW", 8, field_default(0) ),
- ( field_name_pad("sdp_nof_bytes_per_statistic" ), "RW", 8, field_default(c_sdp_nof_bytes_per_statistic) ),
- ( field_name_pad("sdp_nof_statistics_per_packet" ), "RW", 16, field_default(0) ),
- ( field_name_pad("sdp_block_period" ), "RW", 16, field_default(c_sdp_block_period) ),
-
- ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
- );
+ constant c_sdp_stat_hdr_field_arr : t_common_field_arr(
+ c_sdp_stat_nof_hdr_fields - 1 downto 0) := (
+ ( field_name_pad("word_align" ), "RW", 16, field_default(0) ), -- Tx TSE IP will strip these 2 padding bytes
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ), -- c_sdp_stat_eth_dst_mac
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
+
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ), -- differs for SST, BST, XST so set by data path
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_sdp_stat_ip_dst_addr
+
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_sdp_stat_udp_dst_port
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ), -- differs for SST, BST, XST so set by data path
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+
+ ( field_name_pad("sdp_marker" ), "RW", 8, field_default(0) ), -- differs for SST, BST, XST so set by data path
+ ( field_name_pad("sdp_version_id" ), "RW", 8, field_default(c_sdp_stat_version_id) ),
+ ( field_name_pad("sdp_observation_id" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("sdp_station_info" ), "RW", 16, field_default(0) ),
+
+ ( field_name_pad("sdp_source_info_antenna_band_id" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_nyquist_zone_id" ), "RW", 2, field_default(0) ),
+ ( field_name_pad("sdp_source_info_f_adc" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_fsub_type" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_payload_error" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_beam_repositioning_flag" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_weighted_subbands_flag" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_gn_id" ), "RW", 8, field_default(0) ),
+
+ ( field_name_pad("sdp_reserved" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("sdp_integration_interval" ), "RW", 24, field_default(0) ),
+ ( field_name_pad("sdp_data_id" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("sdp_nof_signal_inputs" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("sdp_nof_bytes_per_statistic" ), "RW", 8, field_default(c_sdp_nof_bytes_per_statistic) ),
+ ( field_name_pad("sdp_nof_statistics_per_packet" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("sdp_block_period" ), "RW", 16, field_default(c_sdp_block_period) ),
+
+ ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
+ );
constant c_sdp_reg_stat_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_sdp_stat_hdr_field_arr, c_word_w));
type t_sdp_network_stat_header is record
@@ -419,58 +420,59 @@ package sdp_pkg is
-- Remarks: see remarks at c_sdp_stat_nof_hdr_fields.
-- eth ip udp app
constant c_sdp_cep_hdr_field_sel : std_logic_vector(c_sdp_cep_nof_hdr_fields - 1 downto 0) := "111" & "111111111011" & "1110" & "1100" & "100000010" & "100110" & "0"; -- current
---CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111001"&"0111"&"1100"&"100000010"&"000110"&"0"; -- previous 27 sep 2022
---CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "100"&"000000010001"&"0100"&"0100"&"100000000"&"101000"&"0"; -- initial
+ --CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111001"&"0111"&"1100"&"100000010"&"000110"&"0"; -- previous 27 sep 2022
+ --CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "100"&"000000010001"&"0100"&"0100"&"100000000"&"101000"&"0"; -- initial
-- Default use source MAC/IP/UDP = 0 and destination MAC/IP/UDP = 0, so these have to be MM programmed
-- before beamlet output packets can be send.
- constant c_sdp_cep_hdr_field_arr : t_common_field_arr(c_sdp_cep_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ), -- c_sdp_cep_eth_dst_mac
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
-
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(c_sdp_cep_ip_total_length) ),
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_sdp_cep_ip_dst_addr
-
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_sdp_cep_udp_dst_port
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(c_sdp_cep_udp_total_length) ),
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
-
- ( field_name_pad("sdp_marker" ), "RW", 8, field_default(c_sdp_marker_beamlets) ),
- ( field_name_pad("sdp_version_id" ), "RW", 8, field_default(c_sdp_cep_version_id) ),
- ( field_name_pad("sdp_observation_id" ), "RW", 32, field_default(0) ),
- ( field_name_pad("sdp_station_info" ), "RW", 16, field_default(0) ),
-
- ( field_name_pad("sdp_source_info_reserved" ), "RW", 5, field_default(0) ),
- ( field_name_pad("sdp_source_info_antenna_band_id" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_nyquist_zone_id" ), "RW", 2, field_default(0) ),
- ( field_name_pad("sdp_source_info_f_adc" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_fsub_type" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_payload_error" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_beam_repositioning_flag"), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_beamlet_width" ), "RW", 4, field_default(c_sdp_W_beamlet) ),
- ( field_name_pad("sdp_source_info_gn_id" ), "RW", 8, field_default(0) ),
-
- ( field_name_pad("sdp_reserved" ), "RW", 32, field_default(0) ),
- ( field_name_pad("sdp_beamlet_scale" ), "RW", 16, field_default(c_sdp_unit_beamlet_scale) ),
- ( field_name_pad("sdp_beamlet_index" ), "RW", 16, field_default(0) ),
- ( field_name_pad("sdp_nof_blocks_per_packet" ), "RW", 8, field_default(c_sdp_cep_nof_blocks_per_packet) ),
- ( field_name_pad("sdp_nof_beamlets_per_block" ), "RW", 16, field_default(c_sdp_cep_nof_beamlets_per_block) ),
- ( field_name_pad("sdp_block_period" ), "RW", 16, field_default(c_sdp_block_period) ),
-
- ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
- );
+ constant c_sdp_cep_hdr_field_arr : t_common_field_arr(
+ c_sdp_cep_nof_hdr_fields - 1 downto 0) := (
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ), -- c_sdp_cep_eth_dst_mac
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
+
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(c_sdp_cep_ip_total_length) ),
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_sdp_cep_ip_dst_addr
+
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_sdp_cep_udp_dst_port
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(c_sdp_cep_udp_total_length) ),
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+
+ ( field_name_pad("sdp_marker" ), "RW", 8, field_default(c_sdp_marker_beamlets) ),
+ ( field_name_pad("sdp_version_id" ), "RW", 8, field_default(c_sdp_cep_version_id) ),
+ ( field_name_pad("sdp_observation_id" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("sdp_station_info" ), "RW", 16, field_default(0) ),
+
+ ( field_name_pad("sdp_source_info_reserved" ), "RW", 5, field_default(0) ),
+ ( field_name_pad("sdp_source_info_antenna_band_id" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_nyquist_zone_id" ), "RW", 2, field_default(0) ),
+ ( field_name_pad("sdp_source_info_f_adc" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_fsub_type" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_payload_error" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_beam_repositioning_flag"), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_beamlet_width" ), "RW", 4, field_default(c_sdp_W_beamlet) ),
+ ( field_name_pad("sdp_source_info_gn_id" ), "RW", 8, field_default(0) ),
+
+ ( field_name_pad("sdp_reserved" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("sdp_beamlet_scale" ), "RW", 16, field_default(c_sdp_unit_beamlet_scale) ),
+ ( field_name_pad("sdp_beamlet_index" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("sdp_nof_blocks_per_packet" ), "RW", 8, field_default(c_sdp_cep_nof_blocks_per_packet) ),
+ ( field_name_pad("sdp_nof_beamlets_per_block" ), "RW", 16, field_default(c_sdp_cep_nof_beamlets_per_block) ),
+ ( field_name_pad("sdp_block_period" ), "RW", 16, field_default(c_sdp_block_period) ),
+
+ ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
+ );
constant c_sdp_reg_cep_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
type t_sdp_network_cep_header is record
@@ -520,11 +522,12 @@ package sdp_pkg is
-- JESD204B
constant c_sdp_jesd204b_freq : string := "200MHz";
- constant c_sdp_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0'); -- PIO_JESD_CTRL
+ constant c_sdp_mm_jesd_ctrl_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0'); -- PIO_JESD_CTRL
-- AIT MM address widths
constant c_sdp_jesd204b_addr_w : natural := ceil_log2(c_sdp_S_pn) + tech_jesd204b_port_span_w; -- = 4 + 8
@@ -575,11 +578,12 @@ package sdp_pkg is
-- XSUB
constant c_sdp_crosslets_index_w : natural := ceil_log2(c_sdp_N_sub);
- constant c_sdp_mm_reg_crosslets_info : t_c_mem := (latency => 1,
- adr_w => 4,
- dat_w => c_sdp_crosslets_index_w,
- nof_dat => 16, -- 15 offsets + 1 step
- init_sl => '0');
+ constant c_sdp_mm_reg_crosslets_info : t_c_mem := (
+ latency => 1,
+ adr_w => 4,
+ dat_w => c_sdp_crosslets_index_w,
+ nof_dat => 16, -- 15 offsets + 1 step
+ init_sl => '0');
constant c_sdp_crosslets_info_reg_w : natural := c_sdp_mm_reg_crosslets_info.nof_dat * c_sdp_mm_reg_crosslets_info.dat_w;
constant c_sdp_crosslets_info_nof_offsets : natural := c_sdp_mm_reg_crosslets_info.nof_dat - 1;
@@ -590,11 +594,12 @@ package sdp_pkg is
constant c_sdp_crosslets_info_rst : t_sdp_crosslets_info := (offset_arr => (others => 0), step => 0);
- constant c_sdp_mm_reg_nof_crosslets : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => ceil_log2(c_sdp_N_crosslets_max + 1),
- nof_dat => 1,
- init_sl => '0'); -- Default = 1
+ constant c_sdp_mm_reg_nof_crosslets : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => ceil_log2(c_sdp_N_crosslets_max + 1),
+ nof_dat => 1,
+ init_sl => '0'); -- Default = 1
constant c_sdp_nof_crosslets_reg_w : natural := c_sdp_mm_reg_nof_crosslets.nof_dat * c_sdp_mm_reg_nof_crosslets.dat_w;
constant c_sdp_xst_nof_clk_per_sync_min : natural := c_sdp_N_clk_per_sync / 10; -- 0.1 second
@@ -676,7 +681,7 @@ package sdp_pkg is
function func_sdp_map_crosslets_info(info_rec : t_sdp_crosslets_info) return std_logic_vector; -- map all c_sdp_N_crosslets_max offsets
function func_sdp_step_crosslets_info(info_rec : t_sdp_crosslets_info) return t_sdp_crosslets_info; -- step all c_sdp_N_crosslets_max offsets
-end package sdp_pkg;
+ end package sdp_pkg;
package body sdp_pkg is
function func_sdp_gn_index_to_pn_index(gn_index : natural) return natural is
@@ -718,53 +723,53 @@ package body sdp_pkg is
constant c_marker_xst : natural := 88; -- = 0x58 = 'X'
begin
return sel_a_b(g_statistics_type = "BST", c_marker_bst,
- sel_a_b(g_statistics_type = "XST", c_marker_xst,
- c_marker_sst)); -- SST, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_marker_xst,
+ c_marker_sst)); -- SST, SST_OS
end func_sdp_get_stat_marker;
function func_sdp_get_stat_nof_signal_inputs(g_statistics_type : string) return natural is
begin
return sel_a_b(g_statistics_type = "BST", 0, -- not applicable for BST, so use 0,
- sel_a_b(g_statistics_type = "XST", c_sdp_S_pn,
- 1)); -- SST, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_sdp_S_pn,
+ 1)); -- SST, SST_OS
end func_sdp_get_stat_nof_signal_inputs;
function func_sdp_get_stat_from_mm_user_size(g_statistics_type : string) return natural is
- -- see sdp_statistics_offload.vhd for description
+ -- see sdp_statistics_offload.vhd for description
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_W_statistic_sz, -- = 2, so preserve X, Y order
- sel_a_b(g_statistics_type = "XST", c_sdp_W_statistic_sz, -- = 2, so preserve Re, Im order
- c_sdp_W_statistic_sz)); -- = 2, SST, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_sdp_W_statistic_sz, -- = 2, so preserve Re, Im order
+ c_sdp_W_statistic_sz)); -- = 2, SST, SST_OS
end func_sdp_get_stat_from_mm_user_size;
function func_sdp_get_stat_from_mm_data_size(g_statistics_type : string) return natural is
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_N_pol_bf * c_sdp_W_statistic_sz, -- = 4
- sel_a_b(g_statistics_type = "XST", c_nof_complex * c_sdp_W_statistic_sz, -- = 4
- c_sdp_W_statistic_sz)); -- = 2, SST, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_nof_complex * c_sdp_W_statistic_sz, -- = 4
+ c_sdp_W_statistic_sz)); -- = 2, SST, SST_OS
end func_sdp_get_stat_from_mm_data_size;
function func_sdp_get_stat_from_mm_step_size(g_statistics_type : string) return natural is
constant c_data_size : natural := func_sdp_get_stat_from_mm_data_size(g_statistics_type);
begin
return sel_a_b(g_statistics_type = "BST", c_data_size, -- = 4
- sel_a_b(g_statistics_type = "XST", c_data_size, -- = 4
- c_data_size * c_sdp_Q_fft)); -- = 4, SST, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_data_size, -- = 4
+ c_data_size * c_sdp_Q_fft)); -- = 4, SST, SST_OS
end func_sdp_get_stat_from_mm_step_size;
function func_sdp_get_stat_from_mm_nof_data(g_statistics_type : string) return natural is
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_S_sub_bf, -- = 488
- sel_a_b(g_statistics_type = "XST", c_sdp_X_sq, -- = 144
- c_sdp_N_sub)); -- = 512, SST, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_sdp_X_sq, -- = 144
+ c_sdp_N_sub)); -- = 512, SST, SST_OS
end func_sdp_get_stat_from_mm_nof_data;
-- nof_statistics_per_packet = mm_nof_data * mm_data_size / c_sdp_W_statistic_sz
function func_sdp_get_stat_nof_statistics_per_packet(g_statistics_type : string) return natural is
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_S_sub_bf * c_sdp_N_pol_bf, -- = 976
- sel_a_b(g_statistics_type = "XST", c_sdp_X_sq * c_nof_complex, -- = 288
- c_sdp_N_sub)); -- = 512, SST, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_sdp_X_sq * c_nof_complex, -- = 288
+ c_sdp_N_sub)); -- = 512, SST, SST_OS
end func_sdp_get_stat_nof_statistics_per_packet;
function func_sdp_get_stat_app_total_length(g_statistics_type : string) return natural is
@@ -801,16 +806,16 @@ package body sdp_pkg is
constant c_gn_index : std_logic_vector(7 downto 0) := TO_UVEC(gn_index, 8);
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_bst_udp_src_port_15_8 & c_gn_index, -- BST = 0xD1 & gn_index
- sel_a_b(g_statistics_type = "XST", c_sdp_xst_udp_src_port_15_8 & c_gn_index, -- XST = 0xD2 & gn_index
- c_sdp_sst_udp_src_port_15_8 & c_gn_index)); -- SST = 0xD0 & gn_index, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_sdp_xst_udp_src_port_15_8 & c_gn_index, -- XST = 0xD2 & gn_index
+ c_sdp_sst_udp_src_port_15_8 & c_gn_index)); -- SST = 0xD0 & gn_index, SST_OS
end func_sdp_get_stat_udp_src_port;
function func_sdp_get_stat_nof_packets(g_statistics_type : string; S_pn, P_sq, N_crosslets : natural) return natural is
begin
return sel_a_b(g_statistics_type = "BST", 1,
- sel_a_b(g_statistics_type = "XST", P_sq * N_crosslets,
- sel_a_b(g_statistics_type = "SST", S_pn,
- c_sdp_R_os * S_pn))); -- SST_OS
+ sel_a_b(g_statistics_type = "XST", P_sq * N_crosslets,
+ sel_a_b(g_statistics_type = "SST", S_pn,
+ c_sdp_R_os * S_pn))); -- SST_OS
end func_sdp_get_stat_nof_packets;
function func_sdp_get_stat_nof_packets(g_statistics_type : string) return natural is
@@ -993,4 +998,4 @@ package body sdp_pkg is
return v_info;
end func_sdp_step_crosslets_info;
-end sdp_pkg;
+ end sdp_pkg;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
index d6d46c4f05..3067c85964 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
@@ -32,10 +32,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_scope is
generic (
@@ -68,17 +68,17 @@ begin
sim_only : if g_sim = true generate
gen_deinterleave : for I in 0 to g_nof_input - 1 generate
u_dp_deinterleave : entity dp_lib.dp_deinterleave_one_to_n
- generic map(
- g_pipeline => 0,
- g_nof_outputs => g_n_deinterleave
- )
- port map(
- rst => rst,
- clk => clk,
+ generic map(
+ g_pipeline => 0,
+ g_nof_outputs => g_n_deinterleave
+ )
+ port map(
+ rst => rst,
+ clk => clk,
- snk_in => sp_sosi_arr(I),
- src_out_arr => deinterleaved_sosi_2arr_n(I)
- );
+ snk_in => sp_sosi_arr(I),
+ src_out_arr => deinterleaved_sosi_2arr_n(I)
+ );
gen_flat : for J in 0 to g_n_deinterleave-1 generate
deinterleaved_sosi_arr(g_n_deinterleave * I + J) <= deinterleaved_sosi_2arr_n(I)(J);
@@ -107,18 +107,18 @@ begin
-- SIGNAL SCOPE
---------------------------------------------------------------
u_dp_wideband_sp_arr_scope : entity dp_lib.dp_wideband_sp_arr_scope
- generic map (
- g_sim => g_sim,
- g_use_sclk => false,
- g_complex => true,
- g_nof_streams => g_nof_input * g_n_deinterleave,
- g_wideband_factor => 1,
- g_dat_w => g_dat_w
- )
- port map (
- DCLK => clk,
- sp_sosi_arr => selected_sosi_arr,
- scope_sosi_arr => scope_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_use_sclk => false,
+ g_complex => true,
+ g_nof_streams => g_nof_input * g_n_deinterleave,
+ g_wideband_factor => 1,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ DCLK => clk,
+ sp_sosi_arr => selected_sosi_arr,
+ scope_sosi_arr => scope_sosi_arr
+ );
end generate;
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index e4c4679001..eabc6bf689 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -38,19 +38,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, diag_lib, dp_lib, tech_jesd204b_lib, fft_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, nw_10GbE_lib, eth_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use fft_lib.fft_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use work.sdp_pkg.all;
-use eth_lib.eth_pkg.all;
-use ring_lib.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use fft_lib.fft_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use work.sdp_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use ring_lib.ring_pkg.all;
entity sdp_station is
generic (
@@ -86,9 +86,9 @@ entity sdp_station is
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -616,41 +616,41 @@ begin
xst_udp_src_port <= c_sdp_xst_udp_src_port_15_8 & gn_id;
u_sdp_info : entity work.sdp_info
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_sdp_info_copi,
- reg_miso => reg_sdp_info_cipo,
+ reg_mosi => reg_sdp_info_copi,
+ reg_miso => reg_sdp_info_cipo,
- -- inputs from other blocks
- f_adc => c_f_adc,
- fsub_type => c_fsub_type,
+ -- inputs from other blocks
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
- -- sdp info
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info => sdp_info
+ );
-----------------------------------------------------------------------------
-- Ring info
-----------------------------------------------------------------------------
u_ring_info : entity ring_lib.ring_info
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_copi => reg_ring_info_copi,
- reg_cipo => reg_ring_info_cipo,
+ reg_copi => reg_ring_info_copi,
+ reg_cipo => reg_ring_info_cipo,
- ring_info => ring_info
- );
+ ring_info => ring_info
+ );
this_rn <= TO_UVEC(gn_index - TO_UINT(ring_info.O_rn), c_byte_w) when rising_edge(dp_clk); -- Using register to ease timing closure.
@@ -659,56 +659,56 @@ begin
-- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
-----------------------------------------------------------------------------
u_ait: entity work.node_sdp_adc_input_and_timing
- generic map(
- g_sim => g_sim,
- g_no_jesd => g_no_jesd,
- g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
- dp_pps => dp_pps,
-
- -- mm control buses
- jesd_ctrl_mosi => jesd_ctrl_copi,
- jesd_ctrl_miso => jesd_ctrl_cipo,
- jesd204b_mosi => jesd204b_copi,
- jesd204b_miso => jesd204b_cipo,
- reg_dp_shiftram_mosi => reg_dp_shiftram_copi,
- reg_dp_shiftram_miso => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_cipo,
- reg_wg_mosi => reg_wg_copi,
- reg_wg_miso => reg_wg_cipo,
- ram_wg_mosi => ram_wg_copi,
- ram_wg_miso => ram_wg_cipo,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_mosi => ram_st_histogram_copi,
- ram_st_histogram_miso => ram_st_histogram_cipo,
- reg_aduh_monitor_mosi => reg_aduh_monitor_copi,
- reg_aduh_monitor_miso => reg_aduh_monitor_cipo,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => ait_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart,
- dp_bsn_source_new_interval => dp_bsn_source_new_interval
- );
+ generic map(
+ g_sim => g_sim,
+ g_no_jesd => g_no_jesd,
+ g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_pps => dp_pps,
+
+ -- mm control buses
+ jesd_ctrl_mosi => jesd_ctrl_copi,
+ jesd_ctrl_miso => jesd_ctrl_cipo,
+ jesd204b_mosi => jesd204b_copi,
+ jesd204b_miso => jesd204b_cipo,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_mosi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_miso => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_cipo,
+ reg_wg_mosi => reg_wg_copi,
+ reg_wg_miso => reg_wg_cipo,
+ ram_wg_mosi => ram_wg_copi,
+ ram_wg_miso => ram_wg_cipo,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_mosi => ram_st_histogram_copi,
+ ram_st_histogram_miso => ram_st_histogram_cipo,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_cipo,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => ait_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+ dp_bsn_source_new_interval => dp_bsn_source_new_interval
+ );
-----------------------------------------------------------------------------
-- node_sdp_filterbank (FSUB)
@@ -716,54 +716,54 @@ begin
gen_use_fsub : if g_use_fsub generate
gen_use_no_oversample : if not g_use_oversample generate -- Use normal filterbank
u_fsub : entity work.node_sdp_filterbank
- generic map(
- g_sim => g_sim,
- g_sim_sdp => g_sim_sdp,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- fsub_raw_sosi_arr => fsub_raw_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart,
- dp_bsn_source_new_interval => dp_bsn_source_new_interval,
-
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_copi,
- reg_si_miso => reg_si_cipo,
- ram_st_sst_mosi => ram_st_sst_copi,
- ram_st_sst_miso => ram_st_sst_cipo,
- ram_fil_coefs_mosi => ram_fil_coefs_copi,
- ram_fil_coefs_miso => ram_fil_coefs_cipo,
- ram_gains_mosi => ram_equalizer_gains_copi,
- ram_gains_miso => ram_equalizer_gains_cipo,
- ram_gains_cross_mosi => ram_equalizer_gains_cross_copi,
- ram_gains_cross_miso => ram_equalizer_gains_cross_cipo,
- reg_selector_mosi => reg_dp_selector_copi,
- reg_selector_miso => reg_dp_selector_cipo,
-
- reg_enable_mosi => reg_stat_enable_sst_copi,
- reg_enable_miso => reg_stat_enable_sst_cipo,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_copi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_sst_cipo,
-
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_sdp => g_sim_sdp,
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ fsub_raw_sosi_arr => fsub_raw_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+ dp_bsn_source_new_interval => dp_bsn_source_new_interval,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_copi,
+ reg_si_miso => reg_si_cipo,
+ ram_st_sst_mosi => ram_st_sst_copi,
+ ram_st_sst_miso => ram_st_sst_cipo,
+ ram_fil_coefs_mosi => ram_fil_coefs_copi,
+ ram_fil_coefs_miso => ram_fil_coefs_cipo,
+ ram_gains_mosi => ram_equalizer_gains_copi,
+ ram_gains_miso => ram_equalizer_gains_cipo,
+ ram_gains_cross_mosi => ram_equalizer_gains_cross_copi,
+ ram_gains_cross_miso => ram_equalizer_gains_cross_cipo,
+ reg_selector_mosi => reg_dp_selector_copi,
+ reg_selector_miso => reg_dp_selector_cipo,
+
+ reg_enable_mosi => reg_stat_enable_sst_copi,
+ reg_enable_miso => reg_stat_enable_sst_cipo,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_copi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_sst_cipo,
+
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
+ );
gen_bf_sosi : for I in 0 to c_sdp_N_beamsets - 1 generate
-- Wire same subbands to all beamsets
@@ -776,55 +776,55 @@ begin
-----------------------------------------------------------------------------
gen_use_oversample : if g_use_oversample generate -- use oversampled filterbank instead of normal filterbank
u_fsub : entity work.node_sdp_oversampled_filterbank
- generic map(
- g_sim => g_sim,
- g_sim_sdp => g_sim_sdp,
- g_wpfb => g_wpfb,
- g_wpfb_complex => g_wpfb_complex,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- fsub_raw_sosi_arr => fsub_oversampled_raw_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart,
- dp_bsn_source_new_interval => dp_bsn_source_new_interval,
-
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_copi,
- reg_si_miso => reg_si_cipo,
- ram_st_sst_mosi => ram_st_sst_copi,
- ram_st_sst_miso => ram_st_sst_cipo,
- ram_fil_coefs_mosi => ram_fil_coefs_copi,
- ram_fil_coefs_miso => ram_fil_coefs_cipo,
- ram_gains_mosi => ram_equalizer_gains_copi,
- ram_gains_miso => ram_equalizer_gains_cipo,
- ram_gains_cross_mosi => ram_equalizer_gains_cross_copi,
- ram_gains_cross_miso => ram_equalizer_gains_cross_cipo,
- reg_selector_mosi => reg_dp_selector_copi,
- reg_selector_miso => reg_dp_selector_cipo,
-
- reg_enable_mosi => reg_stat_enable_sst_copi,
- reg_enable_miso => reg_stat_enable_sst_cipo,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_copi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_sst_cipo,
-
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_sdp => g_sim_sdp,
+ g_wpfb => g_wpfb,
+ g_wpfb_complex => g_wpfb_complex,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ fsub_raw_sosi_arr => fsub_oversampled_raw_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+ dp_bsn_source_new_interval => dp_bsn_source_new_interval,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_copi,
+ reg_si_miso => reg_si_cipo,
+ ram_st_sst_mosi => ram_st_sst_copi,
+ ram_st_sst_miso => ram_st_sst_cipo,
+ ram_fil_coefs_mosi => ram_fil_coefs_copi,
+ ram_fil_coefs_miso => ram_fil_coefs_cipo,
+ ram_gains_mosi => ram_equalizer_gains_copi,
+ ram_gains_miso => ram_equalizer_gains_cipo,
+ ram_gains_cross_mosi => ram_equalizer_gains_cross_copi,
+ ram_gains_cross_miso => ram_equalizer_gains_cross_cipo,
+ reg_selector_mosi => reg_dp_selector_copi,
+ reg_selector_miso => reg_dp_selector_cipo,
+
+ reg_enable_mosi => reg_stat_enable_sst_copi,
+ reg_enable_miso => reg_stat_enable_sst_cipo,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_copi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_sst_cipo,
+
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
+ );
-- Lower part contains normal subbands, higher part contains shifted subbands.
-- . Use normal subbands for subband correlator
@@ -842,60 +842,60 @@ begin
-----------------------------------------------------------------------------
gen_use_xsub : if g_use_xsub generate
u_xsub : entity work.node_sdp_correlator
- generic map(
- g_sim => g_sim,
- g_sim_sdp => g_sim_sdp,
- g_P_sq => g_P_sq,
- g_subband_raw_dat_w => c_subband_raw_dat_w,
- g_subband_raw_fraction_w => c_subband_raw_fraction_w
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_raw_sosi_arr,
-
- xst_udp_sosi => udp_tx_sosi_arr(1),
- xst_udp_siso => udp_tx_siso_arr(1),
-
- from_ri_sosi => xst_from_ri_sosi,
- to_ri_sosi => xst_to_ri_sosi,
-
- xst_bs_sosi => xst_bs_sosi,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo,
-
- reg_stat_enable_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_cipo => reg_stat_hdr_dat_xst_cipo,
-
- reg_bsn_align_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
-
- sdp_info => sdp_info,
- ring_info => ring_info,
- gn_id => gn_id,
- stat_eth_src_mac => stat_eth_src_mac,
- stat_ip_src_addr => stat_ip_src_addr,
- stat_udp_src_port => xst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_sdp => g_sim_sdp,
+ g_P_sq => g_P_sq,
+ g_subband_raw_dat_w => c_subband_raw_dat_w,
+ g_subband_raw_fraction_w => c_subband_raw_fraction_w
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_raw_sosi_arr,
+
+ xst_udp_sosi => udp_tx_sosi_arr(1),
+ xst_udp_siso => udp_tx_siso_arr(1),
+
+ from_ri_sosi => xst_from_ri_sosi,
+ to_ri_sosi => xst_to_ri_sosi,
+
+ xst_bs_sosi => xst_bs_sosi,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
+
+ reg_stat_enable_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_cipo => reg_stat_hdr_dat_xst_cipo,
+
+ reg_bsn_align_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+
+ sdp_info => sdp_info,
+ ring_info => ring_info,
+ gn_id => gn_id,
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => xst_udp_src_port
+ );
end generate;
-----------------------------------------------------------------------------
@@ -905,229 +905,229 @@ begin
-- Beamformers
gen_bf : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
u_bf : entity work.node_sdp_beamformer
- generic map(
- g_sim => g_sim,
- g_sim_sdp => g_sim_sdp,
- g_beamset_id => beamset_id,
- g_scope_selected_beamlet => g_scope_selected_subband,
- g_subband_raw_dat_w => c_subband_raw_dat_w,
- g_subband_raw_fraction_w => c_subband_raw_fraction_w
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_raw_sosi_2arr(beamset_id),
- from_ri_sosi => bf_from_ri_sosi_arr(beamset_id),
- to_ri_sosi => bf_to_ri_sosi_arr(beamset_id),
- bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
- bf_udp_siso => bf_udp_siso_arr(beamset_id),
- bst_udp_sosi => udp_tx_sosi_arr(2 + beamset_id),
- bst_udp_siso => udp_tx_siso_arr(2 + beamset_id),
-
- dp_bsn_source_new_interval => dp_bsn_source_new_interval,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_copi_arr(beamset_id),
- ram_ss_ss_wide_miso => ram_ss_ss_wide_cipo_arr(beamset_id),
- ram_bf_weights_mosi => ram_bf_weights_copi_arr(beamset_id),
- ram_bf_weights_miso => ram_bf_weights_cipo_arr(beamset_id),
- reg_bf_scale_mosi => reg_bf_scale_copi_arr(beamset_id),
- reg_bf_scale_miso => reg_bf_scale_cipo_arr(beamset_id),
- reg_hdr_dat_mosi => reg_hdr_dat_copi_arr(beamset_id),
- reg_hdr_dat_miso => reg_hdr_dat_cipo_arr(beamset_id),
- reg_dp_xonoff_mosi => reg_dp_xonoff_copi_arr(beamset_id),
- reg_dp_xonoff_miso => reg_dp_xonoff_cipo_arr(beamset_id),
- ram_st_bst_mosi => ram_st_bst_copi_arr(beamset_id),
- ram_st_bst_miso => ram_st_bst_cipo_arr(beamset_id),
- reg_stat_enable_mosi => reg_stat_enable_bst_copi_arr(beamset_id),
- reg_stat_enable_miso => reg_stat_enable_bst_cipo_arr(beamset_id),
- reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_copi_arr(beamset_id),
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_cipo_arr(beamset_id),
- reg_bsn_align_copi => reg_bsn_align_v2_bf_copi_arr(beamset_id),
- reg_bsn_align_cipo => reg_bsn_align_v2_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_bf_copi_arr(beamset_id),
- reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_bf_copi_arr(beamset_id),
- reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi_arr(beamset_id),
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi_arr(beamset_id),
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo_arr(beamset_id),
-
- sdp_info => sdp_info,
- ring_info => ring_info,
- gn_id => gn_id,
-
- bdo_eth_src_mac => cep_eth_src_mac,
- bdo_ip_src_addr => cep_ip_src_addr,
- bdo_udp_src_port => cep_udp_src_port,
- bdo_hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id),
-
- stat_eth_src_mac => stat_eth_src_mac,
- stat_ip_src_addr => stat_ip_src_addr,
- stat_udp_src_port => bst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_sdp => g_sim_sdp,
+ g_beamset_id => beamset_id,
+ g_scope_selected_beamlet => g_scope_selected_subband,
+ g_subband_raw_dat_w => c_subband_raw_dat_w,
+ g_subband_raw_fraction_w => c_subband_raw_fraction_w
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_raw_sosi_2arr(beamset_id),
+ from_ri_sosi => bf_from_ri_sosi_arr(beamset_id),
+ to_ri_sosi => bf_to_ri_sosi_arr(beamset_id),
+ bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
+ bf_udp_siso => bf_udp_siso_arr(beamset_id),
+ bst_udp_sosi => udp_tx_sosi_arr(2 + beamset_id),
+ bst_udp_siso => udp_tx_siso_arr(2 + beamset_id),
+
+ dp_bsn_source_new_interval => dp_bsn_source_new_interval,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_copi_arr(beamset_id),
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_cipo_arr(beamset_id),
+ ram_bf_weights_mosi => ram_bf_weights_copi_arr(beamset_id),
+ ram_bf_weights_miso => ram_bf_weights_cipo_arr(beamset_id),
+ reg_bf_scale_mosi => reg_bf_scale_copi_arr(beamset_id),
+ reg_bf_scale_miso => reg_bf_scale_cipo_arr(beamset_id),
+ reg_hdr_dat_mosi => reg_hdr_dat_copi_arr(beamset_id),
+ reg_hdr_dat_miso => reg_hdr_dat_cipo_arr(beamset_id),
+ reg_dp_xonoff_mosi => reg_dp_xonoff_copi_arr(beamset_id),
+ reg_dp_xonoff_miso => reg_dp_xonoff_cipo_arr(beamset_id),
+ ram_st_bst_mosi => ram_st_bst_copi_arr(beamset_id),
+ ram_st_bst_miso => ram_st_bst_cipo_arr(beamset_id),
+ reg_stat_enable_mosi => reg_stat_enable_bst_copi_arr(beamset_id),
+ reg_stat_enable_miso => reg_stat_enable_bst_cipo_arr(beamset_id),
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_copi_arr(beamset_id),
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_cipo_arr(beamset_id),
+ reg_bsn_align_copi => reg_bsn_align_v2_bf_copi_arr(beamset_id),
+ reg_bsn_align_cipo => reg_bsn_align_v2_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo_arr(beamset_id),
+
+ sdp_info => sdp_info,
+ ring_info => ring_info,
+ gn_id => gn_id,
+
+ bdo_eth_src_mac => cep_eth_src_mac,
+ bdo_ip_src_addr => cep_ip_src_addr,
+ bdo_udp_src_port => cep_udp_src_port,
+ bdo_hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id),
+
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => bst_udp_src_port
+ );
end generate;
-- MM multiplexing
u_mem_mux_ram_ss_ss_wide : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_ss_ss_wide
- )
- port map (
- mosi => ram_ss_ss_wide_copi,
- miso => ram_ss_ss_wide_cipo,
- mosi_arr => ram_ss_ss_wide_copi_arr,
- miso_arr => ram_ss_ss_wide_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_ss_ss_wide
+ )
+ port map (
+ mosi => ram_ss_ss_wide_copi,
+ miso => ram_ss_ss_wide_cipo,
+ mosi_arr => ram_ss_ss_wide_copi_arr,
+ miso_arr => ram_ss_ss_wide_cipo_arr
+ );
u_mem_mux_ram_bf_weights : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_bf_weights
- )
- port map (
- mosi => ram_bf_weights_copi,
- miso => ram_bf_weights_cipo,
- mosi_arr => ram_bf_weights_copi_arr,
- miso_arr => ram_bf_weights_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_bf_weights
+ )
+ port map (
+ mosi => ram_bf_weights_copi,
+ miso => ram_bf_weights_cipo,
+ mosi_arr => ram_bf_weights_copi_arr,
+ miso_arr => ram_bf_weights_cipo_arr
+ );
u_mem_mux_reg_bsn_align_v2_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bsn_align_v2_bf
- )
- port map (
- mosi => reg_bsn_align_v2_bf_copi,
- miso => reg_bsn_align_v2_bf_cipo,
- mosi_arr => reg_bsn_align_v2_bf_copi_arr,
- miso_arr => reg_bsn_align_v2_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bsn_align_v2_bf
+ )
+ port map (
+ mosi => reg_bsn_align_v2_bf_copi,
+ miso => reg_bsn_align_v2_bf_cipo,
+ mosi_arr => reg_bsn_align_v2_bf_copi_arr,
+ miso_arr => reg_bsn_align_v2_bf_cipo_arr
+ );
u_mem_mux_reg_bf_scale : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bf_scale
- )
- port map (
- mosi => reg_bf_scale_copi,
- miso => reg_bf_scale_cipo,
- mosi_arr => reg_bf_scale_copi_arr,
- miso_arr => reg_bf_scale_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bf_scale
+ )
+ port map (
+ mosi => reg_bf_scale_copi,
+ miso => reg_bf_scale_cipo,
+ mosi_arr => reg_bf_scale_copi_arr,
+ miso_arr => reg_bf_scale_cipo_arr
+ );
u_mem_mux_reg_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_hdr_dat
- )
- port map (
- mosi => reg_hdr_dat_copi,
- miso => reg_hdr_dat_cipo,
- mosi_arr => reg_hdr_dat_copi_arr,
- miso_arr => reg_hdr_dat_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_hdr_dat
+ )
+ port map (
+ mosi => reg_hdr_dat_copi,
+ miso => reg_hdr_dat_cipo,
+ mosi_arr => reg_hdr_dat_copi_arr,
+ miso_arr => reg_hdr_dat_cipo_arr
+ );
u_mem_mux_reg_dp_xonoff : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_dp_xonoff
- )
- port map (
- mosi => reg_dp_xonoff_copi,
- miso => reg_dp_xonoff_cipo,
- mosi_arr => reg_dp_xonoff_copi_arr,
- miso_arr => reg_dp_xonoff_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_dp_xonoff
+ )
+ port map (
+ mosi => reg_dp_xonoff_copi,
+ miso => reg_dp_xonoff_cipo,
+ mosi_arr => reg_dp_xonoff_copi_arr,
+ miso_arr => reg_dp_xonoff_cipo_arr
+ );
u_mem_mux_ram_st_bst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_st_bst
- )
- port map (
- mosi => ram_st_bst_copi,
- miso => ram_st_bst_cipo,
- mosi_arr => ram_st_bst_copi_arr,
- miso_arr => ram_st_bst_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_st_bst
+ )
+ port map (
+ mosi => ram_st_bst_copi,
+ miso => ram_st_bst_cipo,
+ mosi_arr => ram_st_bst_copi_arr,
+ miso_arr => ram_st_bst_cipo_arr
+ );
u_mem_mux_reg_stat_enable_bst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_stat_enable_addr_w
- )
- port map (
- mosi => reg_stat_enable_bst_copi,
- miso => reg_stat_enable_bst_cipo,
- mosi_arr => reg_stat_enable_bst_copi_arr,
- miso_arr => reg_stat_enable_bst_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_stat_enable_addr_w
+ )
+ port map (
+ mosi => reg_stat_enable_bst_copi,
+ miso => reg_stat_enable_bst_cipo,
+ mosi_arr => reg_stat_enable_bst_copi_arr,
+ miso_arr => reg_stat_enable_bst_cipo_arr
+ );
u_mem_mux_reg_stat_hdr_dat_bst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_stat_hdr_dat_addr_w
- )
- port map (
- mosi => reg_stat_hdr_dat_bst_copi,
- miso => reg_stat_hdr_dat_bst_cipo,
- mosi_arr => reg_stat_hdr_dat_bst_copi_arr,
- miso_arr => reg_stat_hdr_dat_bst_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_stat_hdr_dat_addr_w
+ )
+ port map (
+ mosi => reg_stat_hdr_dat_bst_copi,
+ miso => reg_stat_hdr_dat_bst_cipo,
+ mosi_arr => reg_stat_hdr_dat_bst_copi_arr,
+ miso_arr => reg_stat_hdr_dat_bst_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_rx_align_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_rx_align_bf
- )
- port map (
- mosi => reg_bsn_monitor_v2_rx_align_bf_copi,
- miso => reg_bsn_monitor_v2_rx_align_bf_cipo,
- mosi_arr => reg_bsn_monitor_v2_rx_align_bf_copi_arr,
- miso_arr => reg_bsn_monitor_v2_rx_align_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_rx_align_bf
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ miso => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_rx_align_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_rx_align_bf_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_aligned_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_aligned_bf_copi,
- miso => reg_bsn_monitor_v2_aligned_bf_cipo,
- mosi_arr => reg_bsn_monitor_v2_aligned_bf_copi_arr,
- miso_arr => reg_bsn_monitor_v2_aligned_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_aligned_bf_copi,
+ miso => reg_bsn_monitor_v2_aligned_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_aligned_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_aligned_bf_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_bst_offload : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_bst_offload_copi,
- miso => reg_bsn_monitor_v2_bst_offload_cipo,
- mosi_arr => reg_bsn_monitor_v2_bst_offload_copi_arr,
- miso_arr => reg_bsn_monitor_v2_bst_offload_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_bst_offload_copi,
+ miso => reg_bsn_monitor_v2_bst_offload_cipo,
+ mosi_arr => reg_bsn_monitor_v2_bst_offload_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_bst_offload_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_beamlet_output : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_beamlet_output_copi,
- miso => reg_bsn_monitor_v2_beamlet_output_cipo,
- mosi_arr => reg_bsn_monitor_v2_beamlet_output_copi_arr,
- miso_arr => reg_bsn_monitor_v2_beamlet_output_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_beamlet_output_copi,
+ miso => reg_bsn_monitor_v2_beamlet_output_cipo,
+ mosi_arr => reg_bsn_monitor_v2_beamlet_output_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_beamlet_output_cipo_arr
+ );
-----------------------------------------------------------------------------
-- DP MUX to multiplex the c_sdp_N_beamsets via one beamlet output 10GbE link
@@ -1138,137 +1138,85 @@ begin
nw_10GbE_hdr_fields_in_arr(0) <= bf_10GbE_hdr_fields_out_arr(0);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_nof_input => c_sdp_N_beamsets,
- g_sel_ctrl_invert => true,
- g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
+ generic map (
+ g_nof_input => c_sdp_N_beamsets,
+ g_sel_ctrl_invert => true,
+ g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
- snk_in_arr => bf_udp_sosi_arr,
- snk_out_arr => bf_udp_siso_arr,
+ snk_in_arr => bf_udp_sosi_arr,
+ snk_out_arr => bf_udp_siso_arr,
- src_out => nw_10gbe_beamlet_output_snk_in_arr(0),
- src_in => nw_10gbe_beamlet_output_snk_out_arr(0)
- );
+ src_out => nw_10gbe_beamlet_output_snk_in_arr(0),
+ src_in => nw_10gbe_beamlet_output_snk_out_arr(0)
+ );
---------------
-- nw_10GbE beamlet output via front_io QSFP[1]
---------------
u_nw_10GbE_beamlet_output: entity nw_10GbE_lib.nw_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_10GbE_beamlet_output,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill_beamlet_output,
- g_tx_fifo_size => c_fifo_tx_size_beamlet_output,
- g_ip_hdr_field_arr => c_sdp_cep_hdr_field_arr,
- g_xon_backpressure => true
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_10GbE_beamlet_output,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill_beamlet_output,
+ g_tx_fifo_size => c_fifo_tx_size_beamlet_output,
+ g_ip_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_xon_backpressure => true
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mac_mosi => reg_nw_10GbE_mac_copi,
- reg_mac_miso => reg_nw_10GbE_mac_cipo,
+ reg_mac_mosi => reg_nw_10GbE_mac_copi,
+ reg_mac_miso => reg_nw_10GbE_mac_cipo,
- reg_eth10g_mosi => reg_nw_10GbE_eth10g_copi,
- reg_eth10g_miso => reg_nw_10GbE_eth10g_cipo,
+ reg_eth10g_mosi => reg_nw_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_nw_10GbE_eth10g_cipo,
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
- snk_out_arr => nw_10gbe_beamlet_output_snk_out_arr,
- snk_in_arr => nw_10gbe_beamlet_output_snk_in_arr,
+ snk_out_arr => nw_10gbe_beamlet_output_snk_out_arr,
+ snk_in_arr => nw_10gbe_beamlet_output_snk_in_arr,
- src_out_arr => nw_10gbe_beamlet_output_src_out_arr,
- src_in_arr => nw_10gbe_beamlet_output_src_in_arr,
+ src_out_arr => nw_10gbe_beamlet_output_src_out_arr,
+ src_in_arr => nw_10gbe_beamlet_output_src_in_arr,
- -- Serial IO
- serial_tx_arr => unb2_board_front_io_serial_tx_arr(c_nof_10GbE_beamlet_output + c_quad - 1 downto c_quad),
- serial_rx_arr => unb2_board_front_io_serial_rx_arr(c_nof_10GbE_beamlet_output + c_quad - 1 downto c_quad),
+ -- Serial IO
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr(c_nof_10GbE_beamlet_output + c_quad - 1 downto c_quad),
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr(c_nof_10GbE_beamlet_output + c_quad - 1 downto c_quad),
- hdr_fields_in_arr => nw_10GbE_hdr_fields_in_arr
- );
+ hdr_fields_in_arr => nw_10GbE_hdr_fields_in_arr
+ );
end generate;
gen_use_ring : if g_use_ring generate
gen_xst_ring : if g_use_xsub generate
u_ring_lane_xst : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 1, -- transport in positive direction.
- g_lane_data_w => c_longword_w,
- g_lane_packet_length => c_lane_payload_nof_longwords_xst,
- g_lane_total_nof_packets_w => c_lane_total_nof_packets_w,
- g_use_dp_layer => true,
- g_nof_rx_monitors => c_sdp_N_pn_max,
- g_nof_tx_monitors => c_sdp_N_pn_max,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => xst_from_ri_sosi,
- to_lane_sosi => xst_to_ri_sosi,
- lane_rx_cable_sosi => lane_rx_cable_sosi_arr(0),
- lane_rx_board_sosi => lane_rx_board_sosi_arr(0),
- lane_tx_cable_sosi => lane_tx_cable_sosi_arr(0),
- lane_tx_board_sosi => lane_tx_board_sosi_arr(0),
- bs_sosi => xst_bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_previous_rn,
- tx_select => ring_info.use_cable_to_next_rn
- );
- end generate;
-
- gen_bf_ring : if g_use_bf generate
- bf_bs_sosi <= fsub_raw_sosi_arr(0);
-
- gen_beamset_ring : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
- u_ring_lane_bf : entity ring_lib.ring_lane
generic map (
g_lane_direction => 1, -- transport in positive direction.
g_lane_data_w => c_longword_w,
- g_lane_packet_length => c_lane_payload_nof_longwords_bf,
+ g_lane_packet_length => c_lane_payload_nof_longwords_xst,
g_lane_total_nof_packets_w => c_lane_total_nof_packets_w,
g_use_dp_layer => true,
- g_nof_rx_monitors => 1,
- g_nof_tx_monitors => 1,
+ g_nof_rx_monitors => c_sdp_N_pn_max,
+ g_nof_tx_monitors => c_sdp_N_pn_max,
g_err_bi => c_err_bi,
g_nof_err_counts => c_nof_err_counts,
g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
@@ -1282,91 +1230,143 @@ begin
dp_clk => dp_clk,
dp_rst => dp_rst,
- from_lane_sosi => bf_from_ri_sosi_arr(beamset_id),
- to_lane_sosi => bf_to_ri_sosi_arr(beamset_id),
- lane_rx_cable_sosi => lane_rx_cable_sosi_arr(1 + beamset_id),
- lane_rx_board_sosi => lane_rx_board_sosi_arr(1 + beamset_id),
- lane_tx_cable_sosi => lane_tx_cable_sosi_arr(1 + beamset_id),
- lane_tx_board_sosi => lane_tx_board_sosi_arr(1 + beamset_id),
- bs_sosi => bf_bs_sosi, -- used for bsn and sync
-
- reg_ring_lane_info_copi => reg_ring_lane_info_bf_copi_arr(beamset_id),
- reg_ring_lane_info_cipo => reg_ring_lane_info_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_bf_copi_arr(beamset_id),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_bf_copi_arr(beamset_id),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr(beamset_id),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_bf_copi_arr(beamset_id),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_bf_cipo_arr(beamset_id),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_bf_copi_arr(beamset_id),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr(beamset_id),
+ from_lane_sosi => xst_from_ri_sosi,
+ to_lane_sosi => xst_to_ri_sosi,
+ lane_rx_cable_sosi => lane_rx_cable_sosi_arr(0),
+ lane_rx_board_sosi => lane_rx_board_sosi_arr(0),
+ lane_tx_cable_sosi => lane_tx_cable_sosi_arr(0),
+ lane_tx_board_sosi => lane_tx_board_sosi_arr(0),
+ bs_sosi => xst_bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
this_rn => this_rn,
N_rn => ring_info.N_rn,
rx_select => ring_info.use_cable_to_previous_rn,
tx_select => ring_info.use_cable_to_next_rn
);
+ end generate;
+
+ gen_bf_ring : if g_use_bf generate
+ bf_bs_sosi <= fsub_raw_sosi_arr(0);
+
+ gen_beamset_ring : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
+ u_ring_lane_bf : entity ring_lib.ring_lane
+ generic map (
+ g_lane_direction => 1, -- transport in positive direction.
+ g_lane_data_w => c_longword_w,
+ g_lane_packet_length => c_lane_payload_nof_longwords_bf,
+ g_lane_total_nof_packets_w => c_lane_total_nof_packets_w,
+ g_use_dp_layer => true,
+ g_nof_rx_monitors => 1,
+ g_nof_tx_monitors => 1,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => bf_from_ri_sosi_arr(beamset_id),
+ to_lane_sosi => bf_to_ri_sosi_arr(beamset_id),
+ lane_rx_cable_sosi => lane_rx_cable_sosi_arr(1 + beamset_id),
+ lane_rx_board_sosi => lane_rx_board_sosi_arr(1 + beamset_id),
+ lane_tx_cable_sosi => lane_tx_cable_sosi_arr(1 + beamset_id),
+ lane_tx_board_sosi => lane_tx_board_sosi_arr(1 + beamset_id),
+ bs_sosi => bf_bs_sosi, -- used for bsn and sync
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_bf_copi_arr(beamset_id),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr(beamset_id),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_bf_copi_arr(beamset_id),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_bf_cipo_arr(beamset_id),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_bf_copi_arr(beamset_id),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr(beamset_id),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_previous_rn,
+ tx_select => ring_info.use_cable_to_next_rn
+ );
end generate;
u_mem_mux_reg_ring_lane_info_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_ring_lane_info_bf
- )
- port map (
- mosi => reg_ring_lane_info_bf_copi,
- miso => reg_ring_lane_info_bf_cipo,
- mosi_arr => reg_ring_lane_info_bf_copi_arr,
- miso_arr => reg_ring_lane_info_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_ring_lane_info_bf
+ )
+ port map (
+ mosi => reg_ring_lane_info_bf_copi,
+ miso => reg_ring_lane_info_bf_cipo,
+ mosi_arr => reg_ring_lane_info_bf_copi_arr,
+ miso_arr => reg_ring_lane_info_bf_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_ring_rx_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- miso => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_rx_bf_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ miso => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_rx_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_ring_tx_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- miso => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_tx_bf_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ miso => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_tx_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr
+ );
u_mem_mux_reg_dp_block_validate_err_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_dp_block_validate_err_addr_w
- )
- port map (
- mosi => reg_dp_block_validate_err_bf_copi,
- miso => reg_dp_block_validate_err_bf_cipo,
- mosi_arr => reg_dp_block_validate_err_bf_copi_arr,
- miso_arr => reg_dp_block_validate_err_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_dp_block_validate_err_addr_w
+ )
+ port map (
+ mosi => reg_dp_block_validate_err_bf_copi,
+ miso => reg_dp_block_validate_err_bf_cipo,
+ mosi_arr => reg_dp_block_validate_err_bf_copi_arr,
+ miso_arr => reg_dp_block_validate_err_bf_cipo_arr
+ );
u_mem_mux_reg_dp_block_validate_bsn_at_sync_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w
- )
- port map (
- mosi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- miso => reg_dp_block_validate_bsn_at_sync_bf_cipo,
- mosi_arr => reg_dp_block_validate_bsn_at_sync_bf_copi_arr,
- miso_arr => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w
+ )
+ port map (
+ mosi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ miso => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+ mosi_arr => reg_dp_block_validate_bsn_at_sync_bf_copi_arr,
+ miso_arr => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr
+ );
end generate;
-----------------------------------------------------------------------------
@@ -1390,45 +1390,45 @@ begin
-- tr_10GbE ring via front_io QSFP[0]
-----------------------------------------------------------------------------
u_tr_10GbE_ring: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_ring_nof_mac_ip,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill_ring,
- g_tx_fifo_size => c_fifo_tx_size_ring
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_ring_nof_mac_ip,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill_ring,
+ g_tx_fifo_size => c_fifo_tx_size_ring
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_mac_copi,
- reg_mac_miso => reg_tr_10GbE_mac_cipo,
+ reg_mac_mosi => reg_tr_10GbE_mac_copi,
+ reg_mac_miso => reg_tr_10GbE_mac_cipo,
- reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
- reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
+ reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- src_out_arr => tr_10gbe_ring_src_out_arr,
- src_in_arr => tr_10gbe_ring_src_in_arr,
+ src_out_arr => tr_10gbe_ring_src_out_arr,
+ src_in_arr => tr_10gbe_ring_src_in_arr,
- snk_out_arr => tr_10gbe_ring_snk_out_arr,
- snk_in_arr => tr_10gbe_ring_snk_in_arr,
+ snk_out_arr => tr_10gbe_ring_snk_out_arr,
+ snk_in_arr => tr_10gbe_ring_snk_in_arr,
- -- Serial IO
- serial_tx_arr => tr_10gbe_ring_serial_tx_arr,
- serial_rx_arr => tr_10gbe_ring_serial_rx_arr
- );
+ -- Serial IO
+ serial_tx_arr => tr_10gbe_ring_serial_tx_arr,
+ serial_rx_arr => tr_10gbe_ring_serial_rx_arr
+ );
-----------------------------------------------------------------------------
-- Seperate serial tx/rx array
@@ -1457,14 +1457,14 @@ begin
-- PLL
---------
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
------------
-- LEDs
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index 858a12ce9f..0e95600253 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -98,14 +98,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib, dp_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_statistics_offload is
generic (
@@ -517,13 +517,13 @@ begin
v.instance_count := 0; -- only used for XST
v.instance_address := 0; -- only used for XST
- -- The dp_sop = '1' when the packet has been read from statistics memory
- -- and is about to get out of the dp_fifo_fill_eop in
- -- u_dp_block_from_mm_dc. This ensures that the dp_sop identifies the
- -- sop of the offload packet. At the dp_sop:
- -- . the dp_header_info per packet offload can be released
- -- . the next packet offload can be prepared
- --
+ -- The dp_sop = '1' when the packet has been read from statistics memory
+ -- and is about to get out of the dp_fifo_fill_eop in
+ -- u_dp_block_from_mm_dc. This ensures that the dp_sop identifies the
+ -- sop of the offload packet. At the dp_sop:
+ -- . the dp_header_info per packet offload can be released
+ -- . the next packet offload can be prepared
+ --
elsif dp_sop = '1' then
-- Release dp_header_info for current packet offload
v.dp_header_info := dp_header_info;
@@ -592,48 +592,48 @@ begin
in_trigger <= in_sosi.sync and not reg_new_interval;
u_mms_common_variable_delay : entity common_lib.mms_common_variable_delay
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- reg_enable_mosi => reg_enable_mosi,
- reg_enable_miso => reg_enable_miso,
-
- delay => p.nof_cycles_dly,
- trigger => in_trigger,
- trigger_en => trigger_en,
- trigger_dly => trigger_offload
- );
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ reg_enable_mosi => reg_enable_mosi,
+ reg_enable_miso => reg_enable_miso,
+
+ delay => p.nof_cycles_dly,
+ trigger => in_trigger,
+ trigger_en => trigger_en,
+ trigger_dly => trigger_offload
+ );
u_dp_block_from_mm_dc : entity dp_lib.dp_block_from_mm_dc
- generic map (
- g_user_size => c_mm_user_size,
- g_data_size => c_mm_data_size,
- g_step_size => c_mm_step_size,
- g_nof_data => c_mm_nof_data,
- g_word_w => c_word_w,
- g_reverse_word_order => g_reverse_word_order,
- g_bsn_w => c_dp_stream_bsn_w,
- g_bsn_incr_enable => false -- all offload block have same bsn_at_sync
- )
- port map(
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- start_pulse => r.start_pulse,
- sync_in => r.start_sync,
- bsn_at_sync => hdr_input.bsn_at_sync,
- start_address => r.start_address,
- mm_mosi => master_mosi,
- mm_miso => master_miso,
- out_sop => dp_sop, -- = dp_block_from_mm_src_out.sop
- out_sosi => dp_block_from_mm_src_out,
- out_siso => dp_block_from_mm_src_in
- );
+ generic map (
+ g_user_size => c_mm_user_size,
+ g_data_size => c_mm_data_size,
+ g_step_size => c_mm_step_size,
+ g_nof_data => c_mm_nof_data,
+ g_word_w => c_word_w,
+ g_reverse_word_order => g_reverse_word_order,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_bsn_incr_enable => false -- all offload block have same bsn_at_sync
+ )
+ port map(
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ start_pulse => r.start_pulse,
+ sync_in => r.start_sync,
+ bsn_at_sync => hdr_input.bsn_at_sync,
+ start_address => r.start_address,
+ mm_mosi => master_mosi,
+ mm_miso => master_miso,
+ out_sop => dp_sop, -- = dp_block_from_mm_src_out.sop
+ out_sosi => dp_block_from_mm_src_out,
+ out_siso => dp_block_from_mm_src_in
+ );
-- The dp_sop is the sop of the packet that is about to be offloaded by
-- u_dp_offload_tx_v3. The r.dp_header_info must be available at the
@@ -644,16 +644,16 @@ begin
-- u_dp_pipeline_ready.
u_dp_pipeline_ready : entity dp_lib.dp_pipeline_ready
- port map(
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out => dp_block_from_mm_src_in,
- snk_in => dp_block_from_mm_src_out,
- -- ST source
- src_in => dp_offload_snk_out,
- src_out => dp_offload_snk_in
- );
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => dp_block_from_mm_src_in,
+ snk_in => dp_block_from_mm_src_out,
+ -- ST source
+ src_in => dp_offload_snk_out,
+ src_out => dp_offload_snk_in
+ );
-- The hdr_input.bsn_at_sync is passed on via r.dp_header_info so that
-- u_dp_offload_tx_v3 can put it in the udp_sosi header.
@@ -663,27 +663,27 @@ begin
-- is in fact not used, but useful to have in udp_sosi.sync (e.g. for the
-- tb).
u_dp_offload_tx_v3: entity dp_lib.dp_offload_tx_v3
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => c_word_w,
- g_symbol_w => c_word_w,
- g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
- g_hdr_field_sel => c_sdp_stat_hdr_field_sel,
- g_pipeline_ready => true
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- snk_in_arr(0) => dp_offload_snk_in,
- snk_out_arr(0) => dp_offload_snk_out,
- src_out_arr(0) => udp_sosi,
- src_in_arr(0) => out_siso,
- hdr_fields_in_arr(0) => r.dp_header_info
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_word_w,
+ g_symbol_w => c_word_w,
+ g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
+ g_hdr_field_sel => c_sdp_stat_hdr_field_sel,
+ g_pipeline_ready => true
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+ snk_in_arr(0) => dp_offload_snk_in,
+ snk_out_arr(0) => dp_offload_snk_out,
+ src_out_arr(0) => udp_sosi,
+ src_in_arr(0) => out_siso,
+ hdr_fields_in_arr(0) => r.dp_header_info
+ );
-- Debug signal, r_dp_header_rec must be available at the r_dp_header_sop
r_dp_header_sop <= dp_offload_snk_in.sop;
@@ -692,28 +692,28 @@ begin
out_sosi <= udp_sosi;
u_bsn_mon_udp : entity dp_lib.mms_dp_bsn_monitor_v2
- generic map (
- g_nof_streams => 1,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bsn_monitor_sync_timeout,
- g_bsn_w => c_dp_stream_bsn_w,
- g_error_bi => 0,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_cnt_latency_w => c_word_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_v2_offload_copi,
- reg_miso => reg_bsn_monitor_v2_offload_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ref_sync => in_sosi.sync,
-
- in_sosi_arr(0) => udp_sosi
- );
+ generic map (
+ g_nof_streams => 1,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bsn_monitor_sync_timeout,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_offload_copi,
+ reg_miso => reg_bsn_monitor_v2_offload_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => in_sosi.sync,
+
+ in_sosi_arr(0) => udp_sosi
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
index c42b95e49f..dbc1d39382 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
@@ -49,11 +49,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_subband_equalizer is
generic (
@@ -112,18 +112,18 @@ begin
-- g_reverse_len - 1 +
-- g_pipeline_mux_in + g_pipeline_mux_out = 1 + 0 + 2-1 + 0 + 1 = 3
u_pipeline_co_pol : entity dp_lib.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => 3
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => in_raw_sosi_arr,
- -- ST source
- src_out_arr => in_pipe_raw_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => 3
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => in_raw_sosi_arr,
+ -- ST source
+ src_out_arr => in_pipe_raw_sosi_arr
+ );
-- The input subband data order is fsub[S_pn/Q_fft]_[N_sub][Q_fft] and
-- the [Q_fft] = [N_pol] index contains the X and Y polarizations.
@@ -132,23 +132,23 @@ begin
-- in_pipeline_raw_sosi_arr.
gen_cross_pol : for I in 0 to g_nof_streams - 1 generate
u_cross_pol : entity dp_lib.dp_reverse_n_data
- generic map (
- g_pipeline_demux_in => 1, -- serial to parallel section
- g_pipeline_demux_out => 0,
- g_pipeline_mux_in => 0, -- parallel to serial section
- g_pipeline_mux_out => 1,
- g_reverse_len => c_sdp_N_pol, -- = 2
- g_data_w => g_raw_dat_w * c_nof_complex,
- g_use_complex => true,
- g_signed => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_pipeline_demux_in => 1, -- serial to parallel section
+ g_pipeline_demux_out => 0,
+ g_pipeline_mux_in => 0, -- parallel to serial section
+ g_pipeline_mux_out => 1,
+ g_reverse_len => c_sdp_N_pol, -- = 2
+ g_data_w => g_raw_dat_w * c_nof_complex,
+ g_use_complex => true,
+ g_signed => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- snk_in => in_raw_sosi_arr(I),
- src_out => in_cross_raw_sosi_arr(I)
- );
+ snk_in => in_raw_sosi_arr(I),
+ src_out => in_cross_raw_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -156,30 +156,30 @@ begin
-----------------------------------------------------------------------------
-- Total pipeline of sdp_subband_weights is: 5
u_sdp_subband_weigths : entity work.sdp_subband_weights
- generic map (
- g_gains_file_name => g_gains_file_name, -- for co polarization
- g_nof_streams => g_nof_streams,
- g_raw_dat_w => g_raw_dat_w
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ generic map (
+ g_gains_file_name => g_gains_file_name, -- for co polarization
+ g_nof_streams => g_nof_streams,
+ g_raw_dat_w => g_raw_dat_w
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- in_raw_sosi_arr => in_pipe_raw_sosi_arr,
- in_cross_raw_sosi_arr => in_cross_raw_sosi_arr,
+ in_raw_sosi_arr => in_pipe_raw_sosi_arr,
+ in_cross_raw_sosi_arr => in_cross_raw_sosi_arr,
- weighted_raw_sosi_arr => weighted_raw_sosi_arr,
- weighted_cross_raw_sosi_arr => weighted_cross_raw_sosi_arr,
+ weighted_raw_sosi_arr => weighted_raw_sosi_arr,
+ weighted_cross_raw_sosi_arr => weighted_cross_raw_sosi_arr,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso,
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
- ram_gains_cross_mosi => ram_gains_cross_mosi,
- ram_gains_cross_miso => ram_gains_cross_miso
- );
+ ram_gains_cross_mosi => ram_gains_cross_mosi,
+ ram_gains_cross_miso => ram_gains_cross_miso
+ );
-----------------------------------------------------------------------------
-- Sum co + cross
@@ -191,17 +191,17 @@ begin
in_raw_sosi_2arr_2(I)(1) <= weighted_cross_raw_sosi_arr(I);
u_dp_complex_add : entity dp_lib.dp_complex_add
- generic map(
- g_nof_inputs => c_sdp_N_pol,
- g_data_w => c_gain_out_dat_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
+ generic map(
+ g_nof_inputs => c_sdp_N_pol,
+ g_data_w => c_gain_out_dat_w
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
- snk_in_arr => in_raw_sosi_2arr_2(I),
- src_out => sum_raw_sosi_arr(I)
- );
+ snk_in_arr => in_raw_sosi_2arr_2(I),
+ src_out => sum_raw_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -216,51 +216,51 @@ begin
-- g_raw_fraction_w, so that the output width remains the same as the input
-- width g_raw_dat_w.
u_dp_requantize_out_raw : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_sdp_W_sub_weight_fraction,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => true, -- clip subband overflow
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => c_pipeline_remove_lsb,
- g_pipeline_remove_msb => c_pipeline_remove_msb,
- g_in_dat_w => c_gain_out_dat_w,
- g_out_dat_w => g_raw_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => sum_raw_sosi_arr(I),
- -- ST source
- src_out => out_raw_sosi_arr(I)
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_sdp_W_sub_weight_fraction,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => true, -- clip subband overflow
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => c_pipeline_remove_lsb,
+ g_pipeline_remove_msb => c_pipeline_remove_msb,
+ g_in_dat_w => c_gain_out_dat_w,
+ g_out_dat_w => g_raw_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => sum_raw_sosi_arr(I),
+ -- ST source
+ src_out => out_raw_sosi_arr(I)
+ );
-- For quant output round the entire fraction, so that the output width
-- becomes c_quant_dat_w.
u_dp_requantize_out_quant : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_sdp_W_sub_weight_fraction + g_raw_fraction_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => true, -- clip subband overflow
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => c_pipeline_remove_lsb,
- g_pipeline_remove_msb => c_pipeline_remove_msb,
- g_in_dat_w => c_gain_out_dat_w,
- g_out_dat_w => c_quant_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => sum_raw_sosi_arr(I),
- -- ST source
- src_out => out_quant_sosi_arr(I)
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_sdp_W_sub_weight_fraction + g_raw_fraction_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => true, -- clip subband overflow
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => c_pipeline_remove_lsb,
+ g_pipeline_remove_msb => c_pipeline_remove_msb,
+ g_in_dat_w => c_gain_out_dat_w,
+ g_out_dat_w => c_quant_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => sum_raw_sosi_arr(I),
+ -- ST source
+ src_out => out_quant_sosi_arr(I)
+ );
end generate;
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
index 75cbf8a89d..1c83ea4461 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
@@ -39,11 +39,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_subband_weights is
generic (
@@ -129,60 +129,60 @@ begin
-- Gain
-----------------------------------------------------------------------------
u_gains_co : entity dp_lib.mms_dp_gain_serial_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_gains => c_sdp_Q_fft * c_sdp_N_sub,
- g_complex_data => true,
- g_complex_gain => true,
- g_gain_w => c_sdp_W_sub_weight,
- g_in_dat_w => g_raw_dat_w,
- g_out_dat_w => c_gain_out_dat_w,
- g_gains_file_name => g_gains_file_name
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso,
-
- -- ST interface
- gains_rd_address => gains_rd_address,
-
- in_sosi_arr => in_raw_sosi_arr,
- out_sosi_arr => weighted_raw_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_gains => c_sdp_Q_fft * c_sdp_N_sub,
+ g_complex_data => true,
+ g_complex_gain => true,
+ g_gain_w => c_sdp_W_sub_weight,
+ g_in_dat_w => g_raw_dat_w,
+ g_out_dat_w => c_gain_out_dat_w,
+ g_gains_file_name => g_gains_file_name
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
+
+ -- ST interface
+ gains_rd_address => gains_rd_address,
+
+ in_sosi_arr => in_raw_sosi_arr,
+ out_sosi_arr => weighted_raw_sosi_arr
+ );
u_gains_cross : entity dp_lib.mms_dp_gain_serial_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_gains => c_sdp_Q_fft * c_sdp_N_sub,
- g_complex_data => true,
- g_complex_gain => true,
- g_gain_w => c_sdp_W_sub_weight,
- g_in_dat_w => g_raw_dat_w,
- g_out_dat_w => c_gain_out_dat_w,
- g_gains_file_name => "UNUSED"
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_gains_mosi => ram_gains_cross_mosi,
- ram_gains_miso => ram_gains_cross_miso,
-
- -- ST interface
- gains_rd_address => gains_rd_address,
-
- in_sosi_arr => in_cross_raw_sosi_arr,
- out_sosi_arr => weighted_cross_raw_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_gains => c_sdp_Q_fft * c_sdp_N_sub,
+ g_complex_data => true,
+ g_complex_gain => true,
+ g_gain_w => c_sdp_W_sub_weight,
+ g_in_dat_w => g_raw_dat_w,
+ g_out_dat_w => c_gain_out_dat_w,
+ g_gains_file_name => "UNUSED"
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_gains_mosi => ram_gains_cross_mosi,
+ ram_gains_miso => ram_gains_cross_miso,
+
+ -- ST interface
+ gains_rd_address => gains_rd_address,
+
+ in_sosi_arr => in_cross_raw_sosi_arr,
+ out_sosi_arr => weighted_cross_raw_sosi_arr
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
index 39f4fb1d94..9c003bdff9 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
@@ -33,15 +33,15 @@
-- and cur_crosslets_info of the dut by comparing it to the expected output.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.sdp_pkg.all;
entity tb_sdp_crosslets_subband_select is
end tb_sdp_crosslets_subband_select;
@@ -278,28 +278,28 @@ begin
end process;
u_dut : entity work.sdp_crosslets_subband_select
- generic map (
- g_N_crosslets => c_N_crosslets,
- g_ctrl_interval_size_min => 1
- )
- port map (
- dp_rst => rst,
- dp_clk => clk,
-
- mm_rst => rst,
- mm_clk => mm_clk,
-
- reg_crosslets_info_mosi => mm_mosi,
- reg_crosslets_info_miso => mm_miso,
-
- reg_bsn_sync_scheduler_xsub_mosi => mm_trigger_mosi,
- reg_bsn_sync_scheduler_xsub_miso => mm_trigger_miso,
-
- -- Streaming
- in_sosi_arr => in_sosi_arr,
- out_sosi => out_sosi,
-
- cur_crosslets_info_rec => cur_crosslets_info_rec,
- prev_crosslets_info_rec => prev_crosslets_info_rec
- );
+ generic map (
+ g_N_crosslets => c_N_crosslets,
+ g_ctrl_interval_size_min => 1
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => clk,
+
+ mm_rst => rst,
+ mm_clk => mm_clk,
+
+ reg_crosslets_info_mosi => mm_mosi,
+ reg_crosslets_info_miso => mm_miso,
+
+ reg_bsn_sync_scheduler_xsub_mosi => mm_trigger_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => mm_trigger_miso,
+
+ -- Streaming
+ in_sosi_arr => in_sosi_arr,
+ out_sosi => out_sosi,
+
+ cur_crosslets_info_rec => cur_crosslets_info_rec,
+ prev_crosslets_info_rec => prev_crosslets_info_rec
+ );
end tb;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
index ef323ac858..3255912c7a 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
@@ -34,12 +34,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.sdp_pkg.all;
entity tb_sdp_info is
end tb_sdp_info;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
index 47cc9348b2..d9cad5efa4 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
@@ -26,10 +26,10 @@
-- Description:
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use work.sdp_pkg.all;
package tb_sdp_pkg is
-----------------------------------------------------------------------------
@@ -41,40 +41,43 @@ package tb_sdp_pkg is
-----------------------------------------------------------------------------
-- Statistics offload
-----------------------------------------------------------------------------
- function func_sdp_compose_stat_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- g_statistics_type : string;
- weighted_subbands_flag : std_logic;
- gn_index : natural;
- nof_block_per_sync : natural;
- sst_signal_input : natural;
- beamlet_index : natural;
- subband_index : natural;
- xst_signal_input_A : natural;
- xst_signal_input_B : natural;
- dp_bsn : natural) return t_sdp_stat_header;
+ function func_sdp_compose_stat_header(
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ g_statistics_type : string;
+ weighted_subbands_flag : std_logic;
+ gn_index : natural;
+ nof_block_per_sync : natural;
+ sst_signal_input : natural;
+ beamlet_index : natural;
+ subband_index : natural;
+ xst_signal_input_A : natural;
+ xst_signal_input_B : natural;
+ dp_bsn : natural) return t_sdp_stat_header;
function func_sdp_verify_stat_header(g_statistics_type : string; in_hdr, exp_hdr : t_sdp_stat_header) return boolean;
-----------------------------------------------------------------------------
-- Beamlet output via 10GbE to CEP (= central processor)
-----------------------------------------------------------------------------
- function func_sdp_compose_cep_header(ip_src_addr : std_logic_vector;
- ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- dp_bsn : natural) return t_sdp_cep_header;
-
- function func_sdp_compose_cep_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- dp_bsn : natural) return t_sdp_cep_header;
+ function func_sdp_compose_cep_header(
+ ip_src_addr : std_logic_vector;
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ dp_bsn : natural) return t_sdp_cep_header;
+
+ function func_sdp_compose_cep_header(
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ dp_bsn : natural) return t_sdp_cep_header;
function func_sdp_verify_cep_header(in_hdr, exp_hdr : t_sdp_cep_header) return boolean;
@@ -88,9 +91,10 @@ package tb_sdp_pkg is
-- . sp_weight = (sp_esub_gain, sp_esub_phase)
-- . cross_phasor = (cross_subband_ampl, cross_subband_phase)
-- . cross_weight = (cross_esub_gain, cross_esub_phase)
- function func_sdp_subband_equalizer(sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
- cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
- return t_real_arr; -- 0:3 = ampl, phase, re, im
+ function func_sdp_subband_equalizer(
+ sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
+ cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
+ return t_real_arr; -- 0:3 = ampl, phase, re, im
-----------------------------------------------------------------------------
-- Beamformer (BF)
@@ -98,11 +102,12 @@ package tb_sdp_pkg is
-- Model the SDP beamformer for one signal input (sp) and nof_rem remnant signal inputs (rem)
-- . for local beamformer on one node use nof_rem = S_pn - 1
-- . for remote beamformer with nof_rn ring nodes use nof_rem = nof_rn * S_pn - 1
- function func_sdp_beamformer(sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
- rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
- nof_rem : natural)
- return t_real_arr; -- 0:3 = ampl, phase, re, im
-end package tb_sdp_pkg;
+ function func_sdp_beamformer(
+ sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
+ rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
+ nof_rem : natural)
+ return t_real_arr; -- 0:3 = ampl, phase, re, im
+ end package tb_sdp_pkg;
package body tb_sdp_pkg is
function func_sdp_gn_index_to_mac_15_0(gn_index : natural) return std_logic_vector is
@@ -121,19 +126,20 @@ package body tb_sdp_pkg is
return c_ip_15_0;
end func_sdp_gn_index_to_ip_15_0;
- function func_sdp_compose_stat_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- g_statistics_type : string;
- weighted_subbands_flag : std_logic;
- gn_index : natural;
- nof_block_per_sync : natural;
- sst_signal_input : natural;
- beamlet_index : natural;
- subband_index : natural;
- xst_signal_input_A : natural;
- xst_signal_input_B : natural;
- dp_bsn : natural) return t_sdp_stat_header is
- -- Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on gn_index
+ function func_sdp_compose_stat_header(
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ g_statistics_type : string;
+ weighted_subbands_flag : std_logic;
+ gn_index : natural;
+ nof_block_per_sync : natural;
+ sst_signal_input : natural;
+ beamlet_index : natural;
+ subband_index : natural;
+ xst_signal_input_A : natural;
+ xst_signal_input_B : natural;
+ dp_bsn : natural) return t_sdp_stat_header is
+ -- Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on gn_index
constant c_mac_15_0 : std_logic_vector(15 downto 0) := func_sdp_gn_index_to_mac_15_0(gn_index);
constant c_ip_15_0 : std_logic_vector(15 downto 0) := func_sdp_gn_index_to_ip_15_0(gn_index);
@@ -277,15 +283,16 @@ package body tb_sdp_pkg is
return true;
end func_sdp_verify_stat_header;
- function func_sdp_compose_cep_header(ip_src_addr : std_logic_vector;
- ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- dp_bsn : natural) return t_sdp_cep_header is
- -- Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on gn_index
+ function func_sdp_compose_cep_header(
+ ip_src_addr : std_logic_vector;
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ dp_bsn : natural) return t_sdp_cep_header is
+ -- Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on gn_index
constant c_mac_15_0 : std_logic_vector(15 downto 0) := func_sdp_gn_index_to_mac_15_0(gn_index);
variable v_hdr : t_sdp_cep_header;
begin
@@ -341,25 +348,26 @@ package body tb_sdp_pkg is
return v_hdr;
end func_sdp_compose_cep_header;
- function func_sdp_compose_cep_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- dp_bsn : natural) return t_sdp_cep_header is
- -- Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on gn_index
+ function func_sdp_compose_cep_header(
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ dp_bsn : natural) return t_sdp_cep_header is
+ -- Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on gn_index
constant c_ip_15_0 : std_logic_vector(15 downto 0) := func_sdp_gn_index_to_ip_15_0(gn_index);
constant c_ip_src_addr : std_logic_vector(31 downto 0) := c_sdp_cep_ip_src_addr_31_16 & c_ip_15_0;
begin
return func_sdp_compose_cep_header(c_ip_src_addr,
- ip_header_checksum,
- sdp_info,
- gn_index,
- payload_error,
- beamlet_scale,
- beamlet_index,
- dp_bsn);
+ ip_header_checksum,
+ sdp_info,
+ gn_index,
+ payload_error,
+ beamlet_scale,
+ beamlet_index,
+ dp_bsn);
end func_sdp_compose_cep_header;
function func_sdp_verify_cep_header(in_hdr, exp_hdr : t_sdp_cep_header) return boolean is
@@ -419,9 +427,10 @@ package body tb_sdp_pkg is
return true;
end func_sdp_verify_cep_header;
- function func_sdp_subband_equalizer(sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
- cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
- return t_real_arr is -- 0:3 = ampl, phase, re, im
+ function func_sdp_subband_equalizer(
+ sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
+ cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
+ return t_real_arr is -- 0:3 = ampl, phase, re, im
variable v_sp_ampl, v_sp_phase, v_sp_re, v_sp_im : real;
variable v_cross_ampl, v_cross_phase, v_cross_re, v_cross_im : real;
variable v_sum_ampl, v_sum_phase, v_sum_re, v_sum_im : real;
@@ -443,10 +452,11 @@ package body tb_sdp_pkg is
return v_tuple;
end;
- function func_sdp_beamformer(sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
- rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
- nof_rem : natural)
- return t_real_arr is -- 0:3 = ampl, phase, re, im
+ function func_sdp_beamformer(
+ sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
+ rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
+ nof_rem : natural)
+ return t_real_arr is -- 0:3 = ampl, phase, re, im
variable v_nof_rem : real := real(nof_rem); -- BF for one sp and nof_rem remnant signal inputs
variable v_sp_ampl, v_sp_phase, v_sp_re, v_sp_im : real;
variable v_rem_ampl, v_rem_phase, v_rem_re, v_rem_im : real;
@@ -469,4 +479,4 @@ package body tb_sdp_pkg is
return v_tuple;
end;
-end tb_sdp_pkg;
+ end tb_sdp_pkg;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
index 235b962b49..620b869c3b 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
@@ -37,24 +37,24 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_str_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.sdp_pkg.all;
-use work.tb_sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.sdp_pkg.all;
+ use work.tb_sdp_pkg.all;
entity tb_sdp_statistics_offload is
generic (
-- All
g_fast_mm_clk : boolean := true; -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
- -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
+ -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
g_statistics_type : string := "XST";
g_offload_time : natural := 50;
g_reverse_word_order : boolean := true; -- when TRUE then stream LSB word after MSB word.
@@ -98,22 +98,24 @@ architecture tb of tb_sdp_statistics_offload is
constant c_exp_ip_header_checksum : natural := 0; -- 0 in this local tb, calculated by IO eth when used in design
- constant c_exp_sdp_info : t_sdp_info := (TO_UVEC(7, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"FFFFFFFF", -- observation_id
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
- );
-
- constant c_exp_ring_info : t_ring_info := (TO_UVEC(g_O_rn, 8), -- GN index of first GN in ring
- TO_UVEC(g_N_rn, 8), -- number of GN in ring
- '0', -- use_cable_to_next_rn
- '0' -- use_cable_to_previous_rn
- );
+ constant c_exp_sdp_info : t_sdp_info := (
+ TO_UVEC(7, 6), -- antenna_field_index
+ TO_UVEC(601, 10), -- station_id
+ '0', -- antenna_band_index
+ x"FFFFFFFF", -- observation_id
+ b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0', -- beam_repositioning_flag
+ x"1400" -- block_period = 5120
+ );
+
+ constant c_exp_ring_info : t_ring_info := (
+ TO_UVEC(g_O_rn, 8), -- GN index of first GN in ring
+ TO_UVEC(g_N_rn, 8), -- number of GN in ring
+ '0', -- use_cable_to_next_rn
+ '0' -- use_cable_to_previous_rn
+ );
constant c_beamlet_index : natural := g_beamset_id * c_sdp_S_sub_bf;
@@ -396,17 +398,17 @@ begin
exp_xst_signal_input_B <= (source_gn mod c_sdp_N_pn_max) * c_sdp_S_pn;
exp_sdp_stat_header <= func_sdp_compose_stat_header(c_exp_ip_header_checksum,
- exp_sdp_info,
- g_statistics_type,
- weighted_subbands_flag,
- gn_index,
- c_nof_block_per_sync,
- exp_sst_signal_input,
- c_beamlet_index,
- exp_subband_index,
- exp_xst_signal_input_A,
- exp_xst_signal_input_B,
- exp_dp_bsn);
+ exp_sdp_info,
+ g_statistics_type,
+ weighted_subbands_flag,
+ gn_index,
+ c_nof_block_per_sync,
+ exp_sst_signal_input,
+ c_beamlet_index,
+ exp_subband_index,
+ exp_xst_signal_input_A,
+ exp_xst_signal_input_B,
+ exp_dp_bsn);
rx_sdp_stat_header <= func_sdp_map_stat_header(rx_hdr_fields_raw);
@@ -488,7 +490,7 @@ begin
W := rx_valid_cnt; -- range c_packet_size = 1024 32bit Words
S := W / c_sdp_W_statistic_sz; -- range c_nof_statistics_per_packet = 512 Statistic values
D := S; -- range c_mm_nof_data = 512 Data values, because
- -- c_mm_data_size / c_sdp_W_statistic_sz = 1
+ -- c_mm_data_size / c_sdp_W_statistic_sz = 1
U := S; -- range c_sdp_N_sub = 512 SST values
I := W mod c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
P := rx_packet_cnt mod c_rx_nof_packets; -- range c_nof_packets_max = 12 = c_sdp_S_pn packets
@@ -520,7 +522,7 @@ begin
W := rx_valid_cnt; -- range c_packet_size = 1952
S := W / c_sdp_W_statistic_sz; -- range c_nof_statistics_per_packet = 976 Statistic values
D := S / c_sdp_N_pol_bf; -- range c_mm_nof_data = 488 Data values, because
- -- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_sdp_N_pol_bf
+ -- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_sdp_N_pol_bf
B := D; -- range c_sdp_S_sub_bf = 488 dual polarization BST values
I := W mod c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
P := rx_packet_cnt mod c_rx_nof_packets; -- range c_nof_packets_max = 1 packet
@@ -561,7 +563,7 @@ begin
W := rx_valid_cnt; -- range c_packet_size = 576
S := W / c_sdp_W_statistic_sz; -- range c_nof_statistics_per_packet = 288 Statistic values
D := S / c_nof_complex; -- range c_mm_nof_data = 144 Data values, because
- -- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_nof_complex
+ -- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_nof_complex
X := D; -- range c_sdp_X_sq = 144 complex XST values
I := W mod c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
P := rx_packet_cnt mod c_rx_nof_packets; -- range c_nof_packets_max = c_nof_used_P_sq * g_nof_crosslets packets
@@ -595,100 +597,100 @@ begin
end process;
u_ram: entity common_lib.common_ram_crw_crw
- generic map (
- g_ram => c_ram_buf
- )
- port map (
- -- MM write port clock domain.
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_wr_en,
- wr_dat_a => ram_wr_data,
- adr_a => ram_wr_addr,
-
- -- DP read only port clock domain.
- rst_b => mm_rst,
- clk_b => mm_clk,
- adr_b => master_mosi.address(c_ram_buf.adr_w - 1 downto 0),
- rd_en_b => master_mosi.rd,
- rd_dat_b => master_miso.rddata(c_ram_buf.dat_w - 1 downto 0),
- rd_val_b => master_miso.rdval
- );
+ generic map (
+ g_ram => c_ram_buf
+ )
+ port map (
+ -- MM write port clock domain.
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_wr_en,
+ wr_dat_a => ram_wr_data,
+ adr_a => ram_wr_addr,
+
+ -- DP read only port clock domain.
+ rst_b => mm_rst,
+ clk_b => mm_clk,
+ adr_b => master_mosi.address(c_ram_buf.adr_w - 1 downto 0),
+ rd_en_b => master_mosi.rd,
+ rd_dat_b => master_miso.rddata(c_ram_buf.dat_w - 1 downto 0),
+ rd_val_b => master_miso.rdval
+ );
u_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_word_w,
- g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => offload_rx_hdr_dat_miso,
-
- snk_in_arr(0) => sdp_offload_sosi,
- snk_out_arr(0) => sdp_offload_siso,
-
- src_out_arr(0) => rx_offload_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_word_w,
+ g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => offload_rx_hdr_dat_miso,
+
+ snk_in_arr(0) => sdp_offload_sosi,
+ snk_out_arr(0) => sdp_offload_siso,
+
+ src_out_arr(0) => rx_offload_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
-- SDP info
u_dut: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => g_statistics_type,
- g_offload_time => g_offload_time,
- g_reverse_word_order => g_reverse_word_order,
- g_beamset_id => g_beamset_id,
- g_P_sq => g_P_sq,
- g_crosslets_direction => g_crosslets_direction
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- MM
- master_mosi => master_mosi,
- master_miso => master_miso,
-
- reg_enable_mosi => enable_mosi,
- reg_enable_miso => enable_miso,
-
- reg_hdr_dat_mosi => hdr_dat_mosi,
- reg_hdr_dat_miso => hdr_dat_miso,
-
- -- ST
- in_sosi => in_sosi,
- new_interval => new_interval,
-
- out_sosi => sdp_offload_sosi,
- out_siso => sdp_offload_siso,
-
- -- Inputs from other blocks
- eth_src_mac => c_node_eth_src_mac,
- udp_src_port => c_node_udp_src_port,
- ip_src_addr => c_node_ip_src_addr,
-
- gn_index => gn_index,
- ring_info => c_exp_ring_info,
- sdp_info => c_exp_sdp_info,
- weighted_subbands_flag => weighted_subbands_flag,
-
- nof_crosslets => c_mm_nof_crosslets,
- prev_crosslets_info_rec => in_crosslets_info_rec
- );
+ generic map (
+ g_statistics_type => g_statistics_type,
+ g_offload_time => g_offload_time,
+ g_reverse_word_order => g_reverse_word_order,
+ g_beamset_id => g_beamset_id,
+ g_P_sq => g_P_sq,
+ g_crosslets_direction => g_crosslets_direction
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- MM
+ master_mosi => master_mosi,
+ master_miso => master_miso,
+
+ reg_enable_mosi => enable_mosi,
+ reg_enable_miso => enable_miso,
+
+ reg_hdr_dat_mosi => hdr_dat_mosi,
+ reg_hdr_dat_miso => hdr_dat_miso,
+
+ -- ST
+ in_sosi => in_sosi,
+ new_interval => new_interval,
+
+ out_sosi => sdp_offload_sosi,
+ out_siso => sdp_offload_siso,
+
+ -- Inputs from other blocks
+ eth_src_mac => c_node_eth_src_mac,
+ udp_src_port => c_node_udp_src_port,
+ ip_src_addr => c_node_ip_src_addr,
+
+ gn_index => gn_index,
+ ring_info => c_exp_ring_info,
+ sdp_info => c_exp_sdp_info,
+ weighted_subbands_flag => weighted_subbands_flag,
+
+ nof_crosslets => c_mm_nof_crosslets,
+ prev_crosslets_info_rec => in_crosslets_info_rec
+ );
-- Verify crosslets_info functions
assert c_crosslets_info_rec = func_sdp_map_crosslets_info(c_crosslets_info_slv) report "Error in func_sdp_map_crosslets_info()" severity FAILURE;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
index c325ba9be2..8e3b09a1a5 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
@@ -28,7 +28,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_sdp_statistics_offload is
end tb_tb_sdp_statistics_offload;
@@ -36,22 +36,22 @@ end tb_tb_sdp_statistics_offload;
architecture tb of tb_tb_sdp_statistics_offload is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- -- All
--- g_fast_mm_clk : BOOLEAN := TRUE; -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
--- -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
--- g_statistics_type : STRING := "SST";
--- g_offload_time : NATURAL := 500;
--- g_reverse_word_order : BOOLEAN := TRUE -- when TRUE then stream LSB word after MSB word.
--- g_gn_index : NATURAL := 1; -- global node (GN) index, use > 0 to see effect of g_offload_time
--- g_nof_sync : NATURAL := 3;
--- -- BST
--- g_beamset_id : NATURAL := 0;
--- -- XST
--- g_O_rn : NATURAL := 0; -- GN index of first ring node (RN)
--- g_N_rn : NATURAL := 16; -- <= c_sdp_N_rn_max = 16, number of nodes in ring
--- g_P_sq : NATURAL := c_sdp_P_sq
--- g_nof_crosslets : NATURAL := 1;
--- g_crosslets_direction : INTEGER := 1; -- +1 or -1
+ -- -- All
+ -- g_fast_mm_clk : BOOLEAN := TRUE; -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
+ -- -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
+ -- g_statistics_type : STRING := "SST";
+ -- g_offload_time : NATURAL := 500;
+ -- g_reverse_word_order : BOOLEAN := TRUE -- when TRUE then stream LSB word after MSB word.
+ -- g_gn_index : NATURAL := 1; -- global node (GN) index, use > 0 to see effect of g_offload_time
+ -- g_nof_sync : NATURAL := 3;
+ -- -- BST
+ -- g_beamset_id : NATURAL := 0;
+ -- -- XST
+ -- g_O_rn : NATURAL := 0; -- GN index of first ring node (RN)
+ -- g_N_rn : NATURAL := 16; -- <= c_sdp_N_rn_max = 16, number of nodes in ring
+ -- g_P_sq : NATURAL := c_sdp_P_sq
+ -- g_nof_crosslets : NATURAL := 1;
+ -- g_crosslets_direction : INTEGER := 1; -- +1 or -1
u_sst : entity work.tb_sdp_statistics_offload generic map( true, "SST", 50, true, 3, 3);
u_sst_no_reverse : entity work.tb_sdp_statistics_offload generic map( true, "SST", 50, false, 3, 3);
diff --git a/applications/rdma_demo/src/vhdl/rdma_demo_eth_tester_wrapper.vhd b/applications/rdma_demo/src/vhdl/rdma_demo_eth_tester_wrapper.vhd
index 8a099df82c..a5bc2dee39 100644
--- a/applications/rdma_demo/src/vhdl/rdma_demo_eth_tester_wrapper.vhd
+++ b/applications/rdma_demo/src/vhdl/rdma_demo_eth_tester_wrapper.vhd
@@ -31,16 +31,16 @@
-- vivado using the AXI AMM Bridge IP.
library IEEE, common_lib, dp_lib, axi4_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_components_pkg.all;
-use axi4_lib.axi4_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use eth_lib.eth_tester_pkg.all;
-use work.rdma_demo_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_components_pkg.all;
+ use axi4_lib.axi4_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use eth_lib.eth_tester_pkg.all;
+ use work.rdma_demo_pkg.all;
entity rdma_demo_eth_tester_wrapper is
port (
@@ -147,7 +147,7 @@ entity rdma_demo_eth_tester_wrapper is
reg_strobe_total_count_rx_avs_write : in std_logic;
reg_strobe_total_count_rx_avs_writedata : in std_logic_vector(32 - 1 downto 0)
- );
+ );
end rdma_demo_eth_tester_wrapper;
architecture str of rdma_demo_eth_tester_wrapper is
@@ -183,91 +183,91 @@ architecture str of rdma_demo_eth_tester_wrapper is
signal st_rst : std_logic := '0';
begin
u_eth_tester : entity eth_lib.eth_tester
- generic map (
- g_nof_octet_generate => c_rdma_demo_nof_octet_generate_100gbe,
- g_nof_octet_output => c_rdma_demo_nof_octet_output_100gbe,
- g_use_eth_header => false,
- g_use_ip_udp_header => false,
- g_use_dp_header => true,
- g_hdr_field_arr => c_rdma_demo_dp_hdr_field_arr,
- g_hdr_field_sel => c_rdma_demo_dp_hdr_field_sel,
- g_remove_crc => false
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
- st_pps => st_pps,
-
- -- UDP transmit interface
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port,
-
- tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
-
- tx_udp_sosi_arr => tx_udp_sosi_arr,
- tx_udp_siso_arr => tx_udp_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => rx_udp_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- reg_bg_ctrl_copi => reg_bg_ctrl_copi,
- reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
- reg_dp_split_copi => reg_dp_split_copi,
- reg_dp_split_cipo => reg_dp_split_cipo,
-
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
- );
+ generic map (
+ g_nof_octet_generate => c_rdma_demo_nof_octet_generate_100gbe,
+ g_nof_octet_output => c_rdma_demo_nof_octet_output_100gbe,
+ g_use_eth_header => false,
+ g_use_ip_udp_header => false,
+ g_use_dp_header => true,
+ g_hdr_field_arr => c_rdma_demo_dp_hdr_field_arr,
+ g_hdr_field_sel => c_rdma_demo_dp_hdr_field_sel,
+ g_remove_crc => false
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_pps => st_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => eth_src_mac,
+ ip_src_addr => ip_src_addr,
+ udp_src_port => udp_src_port,
+
+ tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
+
+ tx_udp_sosi_arr => tx_udp_sosi_arr,
+ tx_udp_siso_arr => tx_udp_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => rx_udp_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ reg_bg_ctrl_copi => reg_bg_ctrl_copi,
+ reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
+ reg_dp_split_copi => reg_dp_split_copi,
+ reg_dp_split_cipo => reg_dp_split_cipo,
+
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
+ );
-- DP to AXI4
u_axi4_tx_udp : entity axi4_lib.axi4_stream_dp_bridge
- generic map (
- g_axi4_rl => 0,
- g_dp_rl => 1,
- g_active_low_rst => true
- )
- port map (
- in_clk => st_clk,
- in_rst => aresetn,
-
- dp_rst => st_rst,
-
- dp_in_sosi => tx_udp_sosi_arr(0),
- dp_in_siso => tx_udp_siso_arr(0),
-
- axi4_out_sosi => tx_udp_axi4_sosi,
- axi4_out_siso => tx_udp_axi4_siso
- );
+ generic map (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => true
+ )
+ port map (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ dp_rst => st_rst,
+
+ dp_in_sosi => tx_udp_sosi_arr(0),
+ dp_in_siso => tx_udp_siso_arr(0),
+
+ axi4_out_sosi => tx_udp_axi4_sosi,
+ axi4_out_siso => tx_udp_axi4_siso
+ );
u_axi4_rx_udp : entity axi4_lib.axi4_stream_dp_bridge
- generic map (
- g_axi4_rl => 0,
- g_dp_rl => 1,
- g_active_low_rst => true
- )
- port map (
- in_clk => st_clk,
- in_rst => aresetn,
-
- axi4_in_sosi => rx_udp_axi4_sosi,
- axi4_in_siso => rx_udp_axi4_siso,
-
- dp_out_sosi => rx_udp_sosi_arr(0),
- dp_out_siso => rx_udp_siso_arr(0)
- );
+ generic map (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => true
+ )
+ port map (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ axi4_in_sosi => rx_udp_axi4_sosi,
+ axi4_in_siso => rx_udp_axi4_siso,
+
+ dp_out_sosi => rx_udp_sosi_arr(0),
+ dp_out_siso => rx_udp_siso_arr(0)
+ );
-- Wire Records to IN/OUT ports.
-- tx_udp
diff --git a/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd b/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd
index ebb8993efb..dae2fd4c54 100644
--- a/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd
+++ b/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd
@@ -23,11 +23,11 @@
-- Description:
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
package rdma_demo_pkg is
constant c_rdma_demo_nof_octet_generate_100gbe : natural := 64;
@@ -54,12 +54,13 @@ package rdma_demo_pkg is
constant c_rdma_demo_dp_nof_hdr_fields : natural := 4;
constant c_rdma_demo_dp_hdr_field_sel : std_logic_vector(c_rdma_demo_dp_nof_hdr_fields - 1 downto 0) := "0100";
- constant c_rdma_demo_dp_hdr_field_arr : t_common_field_arr(c_rdma_demo_dp_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("dp_length" ), "RW", 16, field_default(0) ),
- ( field_name_pad("dp_reserved"), "RW", 15, field_default(0) ),
- ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
- ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
- );
+ constant c_rdma_demo_dp_hdr_field_arr : t_common_field_arr(
+ c_rdma_demo_dp_nof_hdr_fields - 1 downto 0) := (
+ ( field_name_pad("dp_length" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("dp_reserved"), "RW", 15, field_default(0) ),
+ ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
+ );
constant c_rdma_demo_dp_reg_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_rdma_demo_dp_hdr_field_arr, c_word_w));
constant c_rdma_demo_dp_reg_hdr_dat_addr_span : natural := 2**c_rdma_demo_dp_reg_hdr_dat_addr_w;
@@ -70,45 +71,46 @@ package rdma_demo_pkg is
constant c_rdma_demo_roce_nof_hdr_fields : natural := 12 + 4 + 13 + 3 + 1;
constant c_rdma_demo_roce_hdr_field_sel : std_logic_vector(c_rdma_demo_roce_nof_hdr_fields - 1 downto 0) := "111011111001" & "0100" & "1111111111111" & "111" & "1";
- constant c_rdma_demo_roce_hdr_field_arr : t_common_field_arr(c_rdma_demo_roce_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_eth_tester_ip_dst_addr
+ constant c_rdma_demo_roce_hdr_field_arr : t_common_field_arr(
+ c_rdma_demo_roce_nof_hdr_fields - 1 downto 0) := (
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_eth_tester_ip_dst_addr
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_eth_tester_udp_dst_port
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_eth_tester_udp_dst_port
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("bth_opcode" ), "RW", 8, field_default(0) ),
- ( field_name_pad("bth_se" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_m" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_pad" ), "RW", 2, field_default(0) ),
- ( field_name_pad("bth_tver" ), "RW", 4, field_default(0) ),
- ( field_name_pad("bth_partition_key" ), "RW", 16, field_default(0) ),
- ( field_name_pad("bth_fres" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_bres" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_reserved_a" ), "RW", 6, field_default(0) ),
- ( field_name_pad("bth_dest_qp" ), "RW", 16, field_default(0) ),
- ( field_name_pad("bth_ack_req" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_reserved_b" ), "RW", 7, field_default(0) ),
- ( field_name_pad("bth_psn" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("bth_opcode" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("bth_se" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_m" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_pad" ), "RW", 2, field_default(0) ),
+ ( field_name_pad("bth_tver" ), "RW", 4, field_default(0) ),
+ ( field_name_pad("bth_partition_key" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("bth_fres" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_bres" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_reserved_a" ), "RW", 6, field_default(0) ),
+ ( field_name_pad("bth_dest_qp" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("bth_ack_req" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_reserved_b" ), "RW", 7, field_default(0) ),
+ ( field_name_pad("bth_psn" ), "RW", 32, field_default(0) ),
- ( field_name_pad("reth_virtual_address"), "RW", 64, field_default(0) ),
- ( field_name_pad("reth_r_key" ), "RW", 32, field_default(0) ),
- ( field_name_pad("reth_dma_length" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("reth_virtual_address"), "RW", 64, field_default(0) ),
+ ( field_name_pad("reth_r_key" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("reth_dma_length" ), "RW", 32, field_default(0) ),
- ( field_name_pad("immediate_data" ), "RW", 32, field_default(0) )
- );
+ ( field_name_pad("immediate_data" ), "RW", 32, field_default(0) )
+ );
constant c_rdma_demo_roce_reg_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_rdma_demo_roce_hdr_field_arr, c_word_w));
constant c_rdma_demo_roce_reg_hdr_dat_addr_span : natural := 2**c_rdma_demo_roce_reg_hdr_dat_addr_w;
diff --git a/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd b/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd
index 8b050864ca..263fc55e65 100644
--- a/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd
+++ b/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd
@@ -32,16 +32,16 @@
-- vivado using the AXI AMM Bridge IP.
library IEEE, common_lib, dp_lib, axi4_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_components_pkg.all;
-use axi4_lib.axi4_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use eth_lib.eth_tester_pkg.all;
-use work.rdma_demo_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_components_pkg.all;
+ use axi4_lib.axi4_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use eth_lib.eth_tester_pkg.all;
+ use work.rdma_demo_pkg.all;
entity rdma_demo_roce_tester_wrapper is
port (
@@ -148,7 +148,7 @@ entity rdma_demo_roce_tester_wrapper is
reg_strobe_total_count_rx_avs_write : in std_logic;
reg_strobe_total_count_rx_avs_writedata : in std_logic_vector(32 - 1 downto 0)
- );
+ );
end rdma_demo_roce_tester_wrapper;
architecture str of rdma_demo_roce_tester_wrapper is
@@ -185,94 +185,94 @@ architecture str of rdma_demo_roce_tester_wrapper is
signal st_rst : std_logic := '0';
begin
u_eth_tester : entity eth_lib.eth_tester
- generic map (
- g_nof_octet_generate => c_rdma_demo_nof_octet_generate_100gbe,
- g_nof_octet_output => c_rdma_demo_nof_octet_output_100gbe,
- g_use_eth_header => false,
- g_use_ip_udp_header => true,
- g_use_dp_header => false,
- g_hdr_calc_ip_crc => true,
- g_hdr_field_arr => c_rdma_demo_roce_hdr_field_arr,
- g_hdr_field_sel => c_rdma_demo_roce_hdr_field_sel,
- -- Add icrc length here as g_hdr_app_len is used to calculate the total packet length.
- g_hdr_app_len => c_rdma_demo_roce_hdr_len + c_rdma_demo_roce_icrc_len,
- g_remove_crc => false
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
- st_pps => st_pps,
-
- -- UDP transmit interface
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port,
-
- tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
-
- tx_udp_sosi_arr => tx_udp_sosi_arr,
- tx_udp_siso_arr => tx_udp_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => rx_udp_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- reg_bg_ctrl_copi => reg_bg_ctrl_copi,
- reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
- reg_dp_split_copi => reg_dp_split_copi,
- reg_dp_split_cipo => reg_dp_split_cipo,
-
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
- );
+ generic map (
+ g_nof_octet_generate => c_rdma_demo_nof_octet_generate_100gbe,
+ g_nof_octet_output => c_rdma_demo_nof_octet_output_100gbe,
+ g_use_eth_header => false,
+ g_use_ip_udp_header => true,
+ g_use_dp_header => false,
+ g_hdr_calc_ip_crc => true,
+ g_hdr_field_arr => c_rdma_demo_roce_hdr_field_arr,
+ g_hdr_field_sel => c_rdma_demo_roce_hdr_field_sel,
+ -- Add icrc length here as g_hdr_app_len is used to calculate the total packet length.
+ g_hdr_app_len => c_rdma_demo_roce_hdr_len + c_rdma_demo_roce_icrc_len,
+ g_remove_crc => false
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_pps => st_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => eth_src_mac,
+ ip_src_addr => ip_src_addr,
+ udp_src_port => udp_src_port,
+
+ tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
+
+ tx_udp_sosi_arr => tx_udp_sosi_arr,
+ tx_udp_siso_arr => tx_udp_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => rx_udp_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ reg_bg_ctrl_copi => reg_bg_ctrl_copi,
+ reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
+ reg_dp_split_copi => reg_dp_split_copi,
+ reg_dp_split_cipo => reg_dp_split_cipo,
+
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
+ );
-- DP to AXI4
u_axi4_tx_udp : entity axi4_lib.axi4_stream_dp_bridge
- generic map (
- g_axi4_rl => 0,
- g_dp_rl => 1,
- g_active_low_rst => true
- )
- port map (
- in_clk => st_clk,
- in_rst => aresetn,
-
- dp_rst => st_rst,
-
- dp_in_sosi => tx_udp_sosi_arr(0),
- dp_in_siso => tx_udp_siso_arr(0),
-
- axi4_out_sosi => tx_udp_axi4_sosi,
- axi4_out_siso => tx_udp_axi4_siso
- );
+ generic map (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => true
+ )
+ port map (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ dp_rst => st_rst,
+
+ dp_in_sosi => tx_udp_sosi_arr(0),
+ dp_in_siso => tx_udp_siso_arr(0),
+
+ axi4_out_sosi => tx_udp_axi4_sosi,
+ axi4_out_siso => tx_udp_axi4_siso
+ );
u_axi4_rx_udp : entity axi4_lib.axi4_stream_dp_bridge
- generic map (
- g_axi4_rl => 0,
- g_dp_rl => 1,
- g_active_low_rst => true
- )
- port map (
- in_clk => st_clk,
- in_rst => aresetn,
-
- axi4_in_sosi => rx_udp_axi4_sosi,
- axi4_in_siso => rx_udp_axi4_siso,
-
- dp_out_sosi => rx_udp_sosi_arr(0),
- dp_out_siso => rx_udp_siso_arr(0)
- );
+ generic map (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => true
+ )
+ port map (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ axi4_in_sosi => rx_udp_axi4_sosi,
+ axi4_in_siso => rx_udp_axi4_siso,
+
+ dp_out_sosi => rx_udp_sosi_arr(0),
+ dp_out_siso => rx_udp_siso_arr(0)
+ );
-- Wire Records to IN/OUT ports.
-- tx_udp
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
index 6dd6746142..d441834384 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
@@ -22,9 +22,9 @@
-- . Collection of functions for the ring design
-- --------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package ring_pkg is
function nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : natural) return integer;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
index d13377d1b3..92d6a8d788 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
@@ -31,19 +31,19 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, tech_pll_lib, dp_lib, diag_lib, mm_lib, ta2_channel_cross_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_mm_io_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.ring_pkg.all;
-use work.top_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.ring_pkg.all;
+ use work.top_components_pkg.all;
entity top is
generic (
@@ -396,21 +396,21 @@ begin
QSFP_0_TX <= i_QSFP_TX(0);
u_unb2b_board_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
- --green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- --red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX -- ,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX -- ,
- --QSFP_LED => QSFP_LED
- );
+ --QSFP_LED => QSFP_LED
+ );
------------------------
-- qsfp LEDs controller
@@ -418,21 +418,21 @@ begin
unb2b_board_qsfp_leds_tx_src_in_arr(0).xon <= ta2_unb2b_10GbE_qsfp_snk_out_arr(0).xon;
u_unb2b_board_qsfp_leds : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
-
- tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ );
gen_leds : for i in 0 to c_nof_qsfp_bus - 1 generate
QSFP_LED(i * 2) <= qsfp_green_led_arr(i);
@@ -458,17 +458,17 @@ begin
-- PLL
--------
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => c_tech_arria10_e1sg
- )
- port map (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => clk_156,
- clk_312 => clk_312,
- rst_156 => rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg
+ )
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => clk_156,
+ clk_312 => clk_312,
+ rst_156 => rst_156,
+ rst_312 => open
+ );
----------
-- 10GbE
@@ -511,128 +511,128 @@ begin
-- tr_10GbE
u_ta2_unb2b_10GbE : entity ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
- generic map (
- g_nof_mac => c_max_nof_mac,
- g_use_err => true,
- g_use_pll => true
- )
- port map (
- mm_clk => '0', -- mm_clk,
- mm_rst => mm_rst,
-
- clk_ref_r => SA_CLK,
-
- tx_serial_r => ta2_unb2b_10GbE_tx_serial_r,
- rx_serial_r => ta2_unb2b_10GbE_rx_serial_r,
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- src_out_arr => ta2_unb2b_10GbE_src_out_arr,
- src_in_arr => ta2_unb2b_10GbE_src_in_arr,
- snk_out_arr => ta2_unb2b_10GbE_snk_out_arr,
- snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
- );
+ generic map (
+ g_nof_mac => c_max_nof_mac,
+ g_use_err => true,
+ g_use_pll => true
+ )
+ port map (
+ mm_clk => '0', -- mm_clk,
+ mm_rst => mm_rst,
+
+ clk_ref_r => SA_CLK,
+
+ tx_serial_r => ta2_unb2b_10GbE_tx_serial_r,
+ rx_serial_r => ta2_unb2b_10GbE_rx_serial_r,
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ src_out_arr => ta2_unb2b_10GbE_src_out_arr,
+ src_in_arr => ta2_unb2b_10GbE_src_in_arr,
+ snk_out_arr => ta2_unb2b_10GbE_snk_out_arr,
+ snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
+ );
--------------------------------------
-- Monitoring & Control UNB protocol
--------------------------------------
u_ta2_unb2b_mm_io : entity ta2_unb2b_mm_io_lib.ta2_unb2b_mm_io
- generic map(
- g_use_opencl => true
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- mm_mosi => reg_ta2_unb2b_mm_io_mosi,
- mm_miso => reg_ta2_unb2b_mm_io_miso,
-
- snk_in => ta2_unb2b_mm_io_snk_in,
- snk_out => ta2_unb2b_mm_io_snk_out,
- src_out => ta2_unb2b_mm_io_src_out,
- src_in => ta2_unb2b_mm_io_src_in
- );
+ generic map(
+ g_use_opencl => true
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ mm_mosi => reg_ta2_unb2b_mm_io_mosi,
+ mm_miso => reg_ta2_unb2b_mm_io_miso,
+
+ snk_in => ta2_unb2b_mm_io_snk_in,
+ snk_out => ta2_unb2b_mm_io_snk_out,
+ src_out => ta2_unb2b_mm_io_src_out,
+ src_in => ta2_unb2b_mm_io_src_in
+ );
-----------------------------------------------------------------------------
-- kernel clock crossing for from/to lane sosi
-----------------------------------------------------------------------------
u_ta2_channel_cross_lanes : entity ta2_channel_cross_lib.ta2_channel_cross
- generic map(
- g_nof_streams => g_nof_lanes,
- g_nof_bytes => c_longword_sz,
- g_reverse_bytes => true,
- g_use_bsn => true,
- g_use_sync => true,
- g_use_channel => true
- )
- port map(
- dp_clk => st_clk,
- dp_rst => st_rst,
- dp_src_out_arr => from_lane_sosi_arr(g_nof_lanes - 1 downto 0),
- dp_src_in_arr => from_lane_siso_arr(g_nof_lanes - 1 downto 0),
- dp_snk_out_arr => to_lane_siso_arr(g_nof_lanes - 1 downto 0),
- dp_snk_in_arr => to_lane_sosi_arr(g_nof_lanes - 1 downto 0),
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- kernel_src_out_arr => kernel_to_lane_sosi_arr(g_nof_lanes - 1 downto 0),
- kernel_src_in_arr => kernel_to_lane_siso_arr(g_nof_lanes - 1 downto 0),
- kernel_snk_out_arr => kernel_from_lane_siso_arr(g_nof_lanes - 1 downto 0),
- kernel_snk_in_arr => kernel_from_lane_sosi_arr(g_nof_lanes - 1 downto 0)
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_nof_bytes => c_longword_sz,
+ g_reverse_bytes => true,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_use_channel => true
+ )
+ port map(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+ dp_src_out_arr => from_lane_sosi_arr(g_nof_lanes - 1 downto 0),
+ dp_src_in_arr => from_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ dp_snk_out_arr => to_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ dp_snk_in_arr => to_lane_sosi_arr(g_nof_lanes - 1 downto 0),
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ kernel_src_out_arr => kernel_to_lane_sosi_arr(g_nof_lanes - 1 downto 0),
+ kernel_src_in_arr => kernel_to_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ kernel_snk_out_arr => kernel_from_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ kernel_snk_in_arr => kernel_from_lane_sosi_arr(g_nof_lanes - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- kernel clock crossing for bs sosi
-----------------------------------------------------------------------------
u_ta2_channel_cross_bs_sosi : entity ta2_channel_cross_lib.ta2_channel_cross
- generic map(
- g_nof_streams => 1,
- g_nof_bytes => c_word_sz,
- g_reverse_bytes => true,
- g_use_bsn => true,
- g_use_sync => true
- )
- port map(
- dp_clk => st_clk,
- dp_rst => st_rst,
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- dp_snk_in_arr(0) => bs_sosi,
- kernel_src_out_arr(0) => kernel_bs_sosi
- );
+ generic map(
+ g_nof_streams => 1,
+ g_nof_bytes => c_word_sz,
+ g_reverse_bytes => true,
+ g_use_bsn => true,
+ g_use_sync => true
+ )
+ port map(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ dp_snk_in_arr(0) => bs_sosi,
+ kernel_src_out_arr(0) => kernel_bs_sosi
+ );
-----------------------------------------------------------------------------
-- kernel clock crossing for rx_monitors
-----------------------------------------------------------------------------
u_ta2_channel_cross_rx_monitor : entity ta2_channel_cross_lib.ta2_channel_cross
- generic map(
- g_nof_streams => g_nof_lanes,
- g_nof_bytes => c_longword_sz,
- g_reverse_bytes => true,
- g_use_bsn => true,
- g_use_sync => true,
- g_use_channel => true
- )
- port map(
- dp_clk => st_clk,
- dp_rst => st_rst,
-
- dp_src_out_arr => rx_monitor_sosi_arr(g_nof_lanes - 1 downto 0),
- dp_src_in_arr => rx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- kernel_snk_out_arr => kernel_rx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
- kernel_snk_in_arr => kernel_rx_monitor_sosi_arr(g_nof_lanes - 1 downto 0)
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_nof_bytes => c_longword_sz,
+ g_reverse_bytes => true,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_use_channel => true
+ )
+ port map(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+
+ dp_src_out_arr => rx_monitor_sosi_arr(g_nof_lanes - 1 downto 0),
+ dp_src_in_arr => rx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ kernel_snk_out_arr => kernel_rx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
+ kernel_snk_in_arr => kernel_rx_monitor_sosi_arr(g_nof_lanes - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- kernel clock crossing for tx_monitors
@@ -643,27 +643,27 @@ begin
end generate;
u_ta2_channel_cross_tx_monitor : entity ta2_channel_cross_lib.ta2_channel_cross
- generic map(
- g_nof_streams => g_nof_lanes,
- g_nof_bytes => c_longword_sz,
- g_reverse_bytes => true,
- g_use_bsn => true,
- g_use_sync => true,
- g_use_channel => true
- )
- port map(
- dp_clk => st_clk,
- dp_rst => st_rst,
-
- dp_src_out_arr => tx_monitor_sosi_arr(g_nof_lanes - 1 downto 0),
- dp_src_in_arr => tx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- kernel_snk_out_arr => kernel_tx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
- kernel_snk_in_arr => kernel_tx_monitor_sosi_arr(g_nof_lanes - 1 downto 0)
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_nof_bytes => c_longword_sz,
+ g_reverse_bytes => true,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_use_channel => true
+ )
+ port map(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+
+ dp_src_out_arr => tx_monitor_sosi_arr(g_nof_lanes - 1 downto 0),
+ dp_src_in_arr => tx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ kernel_snk_out_arr => kernel_tx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
+ kernel_snk_in_arr => kernel_tx_monitor_sosi_arr(g_nof_lanes - 1 downto 0)
+ );
rx_monitor_siso_arr <= dp_demux_rx_monitor_siso_arr;
tx_monitor_siso_arr <= dp_demux_tx_monitor_siso_arr;
@@ -683,189 +683,189 @@ begin
-- demux rx_monitor inputs
-----------------------------------------------------------------------------
u_dp_demux_rx_monitor : entity dp_lib.dp_demux
- generic map(
- g_nof_output => g_nof_rx_monitors,
- g_sel_ctrl_invert => true
- )
- port map(
- rst => st_rst,
- clk => st_clk,
-
- snk_out => dp_demux_rx_monitor_siso_arr(I),
- snk_in => dp_demux_rx_monitor_sosi_arr(I),
-
- src_in_arr => rx_monitor_siso_2arr(I),
- src_out_arr => rx_monitor_sosi_2arr(I)
- );
+ generic map(
+ g_nof_output => g_nof_rx_monitors,
+ g_sel_ctrl_invert => true
+ )
+ port map(
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => dp_demux_rx_monitor_siso_arr(I),
+ snk_in => dp_demux_rx_monitor_sosi_arr(I),
+
+ src_in_arr => rx_monitor_siso_2arr(I),
+ src_out_arr => rx_monitor_sosi_2arr(I)
+ );
-----------------------------------------------------------------------------
-- rx_monitors
-----------------------------------------------------------------------------
u_mms_dp_bsn_monitor_v2_rx : entity dp_lib.mms_dp_bsn_monitor_v2
- generic map(
- g_nof_streams => g_nof_rx_monitors
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_v2_rx_mosi_arr(I),
- reg_miso => reg_bsn_monitor_v2_rx_miso_arr(I),
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- ref_sync => bs_sosi.sync,
-
- in_siso_arr => rx_monitor_siso_2arr(I),
- in_sosi_arr => rx_monitor_sosi_2arr(I)
- );
+ generic map(
+ g_nof_streams => g_nof_rx_monitors
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_rx_mosi_arr(I),
+ reg_miso => reg_bsn_monitor_v2_rx_miso_arr(I),
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ ref_sync => bs_sosi.sync,
+
+ in_siso_arr => rx_monitor_siso_2arr(I),
+ in_sosi_arr => rx_monitor_sosi_2arr(I)
+ );
-----------------------------------------------------------------------------
-- demux tx_monitor inputs
-----------------------------------------------------------------------------
u_dp_demux_tx_monitor : entity dp_lib.dp_demux
- generic map(
- g_nof_output => g_nof_tx_monitors,
- g_sel_ctrl_invert => true
- )
- port map(
- rst => st_rst,
- clk => st_clk,
+ generic map(
+ g_nof_output => g_nof_tx_monitors,
+ g_sel_ctrl_invert => true
+ )
+ port map(
+ rst => st_rst,
+ clk => st_clk,
- snk_out => dp_demux_tx_monitor_siso_arr(I),
- snk_in => dp_demux_tx_monitor_sosi_arr(I),
+ snk_out => dp_demux_tx_monitor_siso_arr(I),
+ snk_in => dp_demux_tx_monitor_sosi_arr(I),
- src_in_arr => tx_monitor_siso_2arr(I),
- src_out_arr => tx_monitor_sosi_2arr(I)
- );
+ src_in_arr => tx_monitor_siso_2arr(I),
+ src_out_arr => tx_monitor_sosi_2arr(I)
+ );
-----------------------------------------------------------------------------
-- tx_monitors
-----------------------------------------------------------------------------
u_mms_dp_bsn_monitor_v2_tx : entity dp_lib.mms_dp_bsn_monitor_v2
- generic map(
- g_nof_streams => g_nof_tx_monitors
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_v2_tx_mosi_arr(I),
- reg_miso => reg_bsn_monitor_v2_tx_miso_arr(I),
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- ref_sync => bs_sosi.sync,
-
- in_siso_arr => tx_monitor_siso_2arr(I),
- in_sosi_arr => tx_monitor_sosi_2arr(I)
- );
+ generic map(
+ g_nof_streams => g_nof_tx_monitors
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_tx_mosi_arr(I),
+ reg_miso => reg_bsn_monitor_v2_tx_miso_arr(I),
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ ref_sync => bs_sosi.sync,
+
+ in_siso_arr => tx_monitor_siso_2arr(I),
+ in_sosi_arr => tx_monitor_sosi_2arr(I)
+ );
end generate;
u_common_mem_mux_rx_monitors : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_lanes,
- g_mult_addr_w => ceil_log2(g_nof_rx_monitors) + 3
- )
- port map (
- mosi => reg_bsn_monitor_v2_rx_mosi,
- miso => reg_bsn_monitor_v2_rx_miso,
- mosi_arr => reg_bsn_monitor_v2_rx_mosi_arr,
- miso_arr => reg_bsn_monitor_v2_rx_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_lanes,
+ g_mult_addr_w => ceil_log2(g_nof_rx_monitors) + 3
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_rx_mosi,
+ miso => reg_bsn_monitor_v2_rx_miso,
+ mosi_arr => reg_bsn_monitor_v2_rx_mosi_arr,
+ miso_arr => reg_bsn_monitor_v2_rx_miso_arr
+ );
u_common_mem_mux_tx_monitors : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_lanes,
- g_mult_addr_w => ceil_log2(g_nof_tx_monitors) + 3
- )
- port map (
- mosi => reg_bsn_monitor_v2_tx_mosi,
- miso => reg_bsn_monitor_v2_tx_miso,
- mosi_arr => reg_bsn_monitor_v2_tx_mosi_arr,
- miso_arr => reg_bsn_monitor_v2_tx_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_lanes,
+ g_mult_addr_w => ceil_log2(g_nof_tx_monitors) + 3
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_tx_mosi,
+ miso => reg_bsn_monitor_v2_tx_miso,
+ mosi_arr => reg_bsn_monitor_v2_tx_mosi_arr,
+ miso_arr => reg_bsn_monitor_v2_tx_miso_arr
+ );
-----------------------------------------------------------------------------
-- Design part, mms_diag_block_gen
-----------------------------------------------------------------------------
u_mms_diag_block_gen : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => g_nof_lanes,
- g_use_bg_buffer_ram => true,
- g_buf_dat_w => 32, -- BG is limited to 32 bits data
- g_buf_addr_w => 7,
- g_file_name_prefix => "data/bf_in_data"
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => st_rst,
- dp_clk => st_clk,
- en_sync => st_pps,
-
- -- MM interface
- reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
- reg_bg_ctrl_miso => reg_bg_ctrl_miso,
- ram_bg_data_mosi => ram_bg_data_mosi,
- ram_bg_data_miso => ram_bg_data_miso,
-
- -- ST interface
- out_siso_arr => local_siso_arr,
- out_sosi_arr => local_sosi_arr
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_use_bg_buffer_ram => true,
+ g_buf_dat_w => 32, -- BG is limited to 32 bits data
+ g_buf_addr_w => 7,
+ g_file_name_prefix => "data/bf_in_data"
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ en_sync => st_pps,
+
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
+ reg_bg_ctrl_miso => reg_bg_ctrl_miso,
+ ram_bg_data_mosi => ram_bg_data_mosi,
+ ram_bg_data_miso => ram_bg_data_miso,
+
+ -- ST interface
+ out_siso_arr => local_siso_arr,
+ out_sosi_arr => local_sosi_arr
+ );
bs_sosi <= local_sosi_arr(0);
u_mms_dp_xonoff_bg : entity dp_lib.mms_dp_xonoff
- generic map(
- g_nof_streams => g_nof_lanes,
- g_combine_streams => false,
- g_default_value => '0'
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_dp_xonoff_bg_mosi,
- reg_miso => reg_dp_xonoff_bg_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- -- ST sinks
- snk_out_arr => local_siso_arr,
- snk_in_arr => local_sosi_arr,
- -- ST source
- src_in_arr => dp_xonoff_bg_siso_arr,
- src_out_arr => dp_xonoff_bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_combine_streams => false,
+ g_default_value => '0'
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_xonoff_bg_mosi,
+ reg_miso => reg_dp_xonoff_bg_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ -- ST sinks
+ snk_out_arr => local_siso_arr,
+ snk_in_arr => local_sosi_arr,
+ -- ST source
+ src_in_arr => dp_xonoff_bg_siso_arr,
+ src_out_arr => dp_xonoff_bg_sosi_arr
+ );
u_mms_dp_xonoff_from_lane : entity dp_lib.mms_dp_xonoff
- generic map(
- g_nof_streams => g_nof_lanes,
- g_combine_streams => false,
- g_default_value => '1'
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_dp_xonoff_from_lane_mosi,
- reg_miso => reg_dp_xonoff_from_lane_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- -- ST sinks
- snk_out_arr => from_lane_siso_arr(g_nof_lanes - 1 downto 0),
- snk_in_arr => from_lane_sosi_arr(g_nof_lanes - 1 downto 0),
- -- ST source
- src_in_arr => dp_xonoff_from_lane_siso_arr(g_nof_lanes - 1 downto 0),
- src_out_arr => dp_xonoff_from_lane_sosi_arr(g_nof_lanes - 1 downto 0)
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_combine_streams => false,
+ g_default_value => '1'
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_xonoff_from_lane_mosi,
+ reg_miso => reg_dp_xonoff_from_lane_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ -- ST sinks
+ snk_out_arr => from_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ snk_in_arr => from_lane_sosi_arr(g_nof_lanes - 1 downto 0),
+ -- ST source
+ src_in_arr => dp_xonoff_from_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ src_out_arr => dp_xonoff_from_lane_sosi_arr(g_nof_lanes - 1 downto 0)
+ );
gen_streams : for I in 0 to g_nof_lanes - 1 generate
-- Multiplex the inputs:
@@ -878,28 +878,28 @@ begin
mux_snk_in_2arr_2(I)(1) <= dp_xonoff_bg_sosi_arr(I);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_technology => g_technology,
- -- MUX
- g_mode => 0,
- g_nof_input => 2,
- g_append_channel_lo => false,
- g_sel_ctrl_invert => true, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
- -- Input FIFO
- g_use_fifo => false,
- g_fifo_size => array_init(1024, 2), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, 2) -- must match g_nof_input, even when g_use_fifo=FALSE
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- -- ST sinks
- snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
- snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
- -- ST source
- src_in => to_lane_siso_arr(I),
- src_out => to_lane_sosi_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ -- MUX
+ g_mode => 0,
+ g_nof_input => 2,
+ g_append_channel_lo => false,
+ g_sel_ctrl_invert => true, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ -- Input FIFO
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, 2), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, 2) -- must match g_nof_input, even when g_use_fifo=FALSE
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- ST sinks
+ snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
+ snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
+ -- ST source
+ src_in => to_lane_siso_arr(I),
+ src_out => to_lane_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -908,263 +908,263 @@ begin
gn_index <= TO_UINT(ID(c_sdp_W_gn_id - 1 downto 0));
this_rn_id <= TO_UVEC(gn_index - TO_UINT(sdp_info.O_rn), c_sdp_W_gn_id);
u_sdp_info : entity lofar2_sdp_lib.sdp_info
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
- dp_clk => st_clk,
- dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_rst => st_rst,
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
- -- inputs from other blocks
- gn_index => gn_index,
- f_adc => '1',
- fsub_type => '0',
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => '1',
+ fsub_type => '0',
- -- sdp info
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info => sdp_info
+ );
-----------------------------------------------------------------------------
-- Freeze wrapper instantiation
-----------------------------------------------------------------------------
gen_opencl: if g_sim = false generate
- freeze_wrapper_inst : freeze_wrapper
- port map(
- board_kernel_clk_clk => board_kernel_clk_clk,
- board_kernel_clk2x_clk => board_kernel_clk2x_clk,
- board_kernel_reset_reset_n => board_kernel_reset_reset_n_in,
- board_kernel_irq_irq => board_kernel_irq_irq,
- board_kernel_cra_waitrequest => board_kernel_cra_waitrequest,
- board_kernel_cra_readdata => board_kernel_cra_readdata,
- board_kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
- board_kernel_cra_burstcount => board_kernel_cra_burstcount,
- board_kernel_cra_writedata => board_kernel_cra_writedata,
- board_kernel_cra_address => board_kernel_cra_address,
- board_kernel_cra_write => board_kernel_cra_write,
- board_kernel_cra_read => board_kernel_cra_read,
- board_kernel_cra_byteenable => board_kernel_cra_byteenable,
- board_kernel_cra_debugaccess => board_kernel_cra_debugaccess,
-
- board_kernel_register_mem_address => board_kernel_register_mem_address,
- board_kernel_register_mem_clken => board_kernel_register_mem_clken,
- board_kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
- board_kernel_register_mem_write => board_kernel_register_mem_write,
- board_kernel_register_mem_readdata => board_kernel_register_mem_readdata,
- board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
- board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
-
- board_kernel_stream_src_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).valid,
- board_kernel_stream_src_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(0).ready,
- board_kernel_stream_snk_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).valid,
- board_kernel_stream_snk_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(0).ready,
-
- board_kernel_stream_src_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).valid,
- board_kernel_stream_src_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(1).ready,
- board_kernel_stream_snk_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).valid,
- board_kernel_stream_snk_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(1).ready,
-
- board_kernel_stream_src_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).valid,
- board_kernel_stream_src_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(2).ready,
- board_kernel_stream_snk_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).valid,
- board_kernel_stream_snk_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(2).ready,
-
- board_kernel_stream_src_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).valid,
- board_kernel_stream_src_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(3).ready,
- board_kernel_stream_snk_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).valid,
- board_kernel_stream_snk_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(3).ready,
-
- board_kernel_stream_src_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).valid,
- board_kernel_stream_src_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(4).ready,
- board_kernel_stream_snk_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).valid,
- board_kernel_stream_snk_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(4).ready,
-
- board_kernel_stream_src_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).valid,
- board_kernel_stream_src_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(5).ready,
- board_kernel_stream_snk_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).valid,
- board_kernel_stream_snk_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(5).ready,
-
- board_kernel_stream_src_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).valid,
- board_kernel_stream_src_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(6).ready,
- board_kernel_stream_snk_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).valid,
- board_kernel_stream_snk_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(6).ready,
-
- board_kernel_stream_src_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).valid,
- board_kernel_stream_src_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(7).ready,
- board_kernel_stream_snk_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).valid,
- board_kernel_stream_snk_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(7).ready,
-
- board_kernel_stream_src_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(0).valid,
- board_kernel_stream_src_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(0).ready,
- board_kernel_stream_snk_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).valid,
- board_kernel_stream_snk_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(0).ready,
-
- board_kernel_stream_src_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_src_out_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(1).valid,
- board_kernel_stream_src_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(1).ready,
- board_kernel_stream_snk_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).valid,
- board_kernel_stream_snk_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(1).ready,
-
- board_kernel_stream_src_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_src_out_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(2).valid,
- board_kernel_stream_src_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(2).ready,
- board_kernel_stream_snk_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).valid,
- board_kernel_stream_snk_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(2).ready,
-
- board_kernel_stream_src_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_src_out_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(3).valid,
- board_kernel_stream_src_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(3).ready,
- board_kernel_stream_snk_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).valid,
- board_kernel_stream_snk_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(3).ready,
-
- board_kernel_stream_src_lane_0_data => kernel_to_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_0_valid => kernel_to_lane_sosi_arr(0).valid,
- board_kernel_stream_src_lane_0_ready => kernel_to_lane_siso_arr(0).ready,
- board_kernel_stream_snk_lane_0_data => kernel_from_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_0_valid => kernel_from_lane_sosi_arr(0).valid,
- board_kernel_stream_snk_lane_0_ready => kernel_from_lane_siso_arr(0).ready,
-
- board_kernel_stream_src_lane_1_data => kernel_to_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_1_valid => kernel_to_lane_sosi_arr(1).valid,
- board_kernel_stream_src_lane_1_ready => kernel_to_lane_siso_arr(1).ready,
- board_kernel_stream_snk_lane_1_data => kernel_from_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_1_valid => kernel_from_lane_sosi_arr(1).valid,
- board_kernel_stream_snk_lane_1_ready => kernel_from_lane_siso_arr(1).ready,
-
- board_kernel_stream_src_lane_2_data => kernel_to_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_2_valid => kernel_to_lane_sosi_arr(2).valid,
- board_kernel_stream_src_lane_2_ready => kernel_to_lane_siso_arr(2).ready,
- board_kernel_stream_snk_lane_2_data => kernel_from_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_2_valid => kernel_from_lane_sosi_arr(2).valid,
- board_kernel_stream_snk_lane_2_ready => kernel_from_lane_siso_arr(2).ready,
-
- board_kernel_stream_src_lane_3_data => kernel_to_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_3_valid => kernel_to_lane_sosi_arr(3).valid,
- board_kernel_stream_src_lane_3_ready => kernel_to_lane_siso_arr(3).ready,
- board_kernel_stream_snk_lane_3_data => kernel_from_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_3_valid => kernel_from_lane_sosi_arr(3).valid,
- board_kernel_stream_snk_lane_3_ready => kernel_from_lane_siso_arr(3).ready,
-
- board_kernel_stream_src_lane_4_data => kernel_to_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_4_valid => kernel_to_lane_sosi_arr(4).valid,
- board_kernel_stream_src_lane_4_ready => kernel_to_lane_siso_arr(4).ready,
- board_kernel_stream_snk_lane_4_data => kernel_from_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_4_valid => kernel_from_lane_sosi_arr(4).valid,
- board_kernel_stream_snk_lane_4_ready => kernel_from_lane_siso_arr(4).ready,
-
- board_kernel_stream_src_lane_5_data => kernel_to_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_5_valid => kernel_to_lane_sosi_arr(5).valid,
- board_kernel_stream_src_lane_5_ready => kernel_to_lane_siso_arr(5).ready,
- board_kernel_stream_snk_lane_5_data => kernel_from_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_5_valid => kernel_from_lane_sosi_arr(5).valid,
- board_kernel_stream_snk_lane_5_ready => kernel_from_lane_siso_arr(5).ready,
-
- board_kernel_stream_src_lane_6_data => kernel_to_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_6_valid => kernel_to_lane_sosi_arr(6).valid,
- board_kernel_stream_src_lane_6_ready => kernel_to_lane_siso_arr(6).ready,
- board_kernel_stream_snk_lane_6_data => kernel_from_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_6_valid => kernel_from_lane_sosi_arr(6).valid,
- board_kernel_stream_snk_lane_6_ready => kernel_from_lane_siso_arr(6).ready,
-
- board_kernel_stream_src_lane_7_data => kernel_to_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_7_valid => kernel_to_lane_sosi_arr(7).valid,
- board_kernel_stream_src_lane_7_ready => kernel_to_lane_siso_arr(7).ready,
- board_kernel_stream_snk_lane_7_data => kernel_from_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_7_valid => kernel_from_lane_sosi_arr(7).valid,
- board_kernel_stream_snk_lane_7_ready => kernel_from_lane_siso_arr(7).ready,
-
- board_kernel_stream_snk_rx_monitor_0_data => kernel_rx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_0_valid => kernel_rx_monitor_sosi_arr(0).valid,
- board_kernel_stream_snk_rx_monitor_0_ready => kernel_rx_monitor_siso_arr(0).ready,
- board_kernel_stream_snk_tx_monitor_0_data => kernel_tx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_0_valid => kernel_tx_monitor_sosi_arr(0).valid,
- board_kernel_stream_snk_tx_monitor_0_ready => kernel_tx_monitor_siso_arr(0).ready,
-
- board_kernel_stream_snk_rx_monitor_1_data => kernel_rx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_1_valid => kernel_rx_monitor_sosi_arr(1).valid,
- board_kernel_stream_snk_rx_monitor_1_ready => kernel_rx_monitor_siso_arr(1).ready,
- board_kernel_stream_snk_tx_monitor_1_data => kernel_tx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_1_valid => kernel_tx_monitor_sosi_arr(1).valid,
- board_kernel_stream_snk_tx_monitor_1_ready => kernel_tx_monitor_siso_arr(1).ready,
-
- board_kernel_stream_snk_rx_monitor_2_data => kernel_rx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_2_valid => kernel_rx_monitor_sosi_arr(2).valid,
- board_kernel_stream_snk_rx_monitor_2_ready => kernel_rx_monitor_siso_arr(2).ready,
- board_kernel_stream_snk_tx_monitor_2_data => kernel_tx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_2_valid => kernel_tx_monitor_sosi_arr(2).valid,
- board_kernel_stream_snk_tx_monitor_2_ready => kernel_tx_monitor_siso_arr(2).ready,
-
- board_kernel_stream_snk_rx_monitor_3_data => kernel_rx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_3_valid => kernel_rx_monitor_sosi_arr(3).valid,
- board_kernel_stream_snk_rx_monitor_3_ready => kernel_rx_monitor_siso_arr(3).ready,
- board_kernel_stream_snk_tx_monitor_3_data => kernel_tx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_3_valid => kernel_tx_monitor_sosi_arr(3).valid,
- board_kernel_stream_snk_tx_monitor_3_ready => kernel_tx_monitor_siso_arr(3).ready,
-
- board_kernel_stream_snk_rx_monitor_4_data => kernel_rx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_4_valid => kernel_rx_monitor_sosi_arr(4).valid,
- board_kernel_stream_snk_rx_monitor_4_ready => kernel_rx_monitor_siso_arr(4).ready,
- board_kernel_stream_snk_tx_monitor_4_data => kernel_tx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_4_valid => kernel_tx_monitor_sosi_arr(4).valid,
- board_kernel_stream_snk_tx_monitor_4_ready => kernel_tx_monitor_siso_arr(4).ready,
-
- board_kernel_stream_snk_rx_monitor_5_data => kernel_rx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_5_valid => kernel_rx_monitor_sosi_arr(5).valid,
- board_kernel_stream_snk_rx_monitor_5_ready => kernel_rx_monitor_siso_arr(5).ready,
- board_kernel_stream_snk_tx_monitor_5_data => kernel_tx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_5_valid => kernel_tx_monitor_sosi_arr(5).valid,
- board_kernel_stream_snk_tx_monitor_5_ready => kernel_tx_monitor_siso_arr(5).ready,
-
- board_kernel_stream_snk_rx_monitor_6_data => kernel_rx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_6_valid => kernel_rx_monitor_sosi_arr(6).valid,
- board_kernel_stream_snk_rx_monitor_6_ready => kernel_rx_monitor_siso_arr(6).ready,
- board_kernel_stream_snk_tx_monitor_6_data => kernel_tx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_6_valid => kernel_tx_monitor_sosi_arr(6).valid,
- board_kernel_stream_snk_tx_monitor_6_ready => kernel_tx_monitor_siso_arr(6).ready,
-
- board_kernel_stream_snk_rx_monitor_7_data => kernel_rx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_7_valid => kernel_rx_monitor_sosi_arr(7).valid,
- board_kernel_stream_snk_rx_monitor_7_ready => kernel_rx_monitor_siso_arr(7).ready,
- board_kernel_stream_snk_tx_monitor_7_data => kernel_tx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_7_valid => kernel_tx_monitor_sosi_arr(7).valid,
- board_kernel_stream_snk_tx_monitor_7_ready => kernel_tx_monitor_siso_arr(7).ready,
-
- board_kernel_stream_src_bs_data => kernel_bs_sosi.data(c_kernel_bs_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_bs_valid => kernel_bs_sosi.valid,
- board_kernel_stream_src_bs_ready => OPEN,
-
- board_kernel_stream_src_mm_io_data => ta2_unb2b_mm_io_src_out.data(c_kernel_mm_io_mosi_channel_w - 1 downto 0),
- board_kernel_stream_src_mm_io_valid => ta2_unb2b_mm_io_src_out.valid,
- board_kernel_stream_src_mm_io_ready => ta2_unb2b_mm_io_src_in.ready,
- board_kernel_stream_snk_mm_io_data => ta2_unb2b_mm_io_snk_in.data(c_kernel_mm_io_miso_channel_w - 1 downto 0),
- board_kernel_stream_snk_mm_io_valid => ta2_unb2b_mm_io_snk_in.valid,
- board_kernel_stream_snk_mm_io_ready => ta2_unb2b_mm_io_snk_out.ready
+ freeze_wrapper_inst : freeze_wrapper
+ port map(
+ board_kernel_clk_clk => board_kernel_clk_clk,
+ board_kernel_clk2x_clk => board_kernel_clk2x_clk,
+ board_kernel_reset_reset_n => board_kernel_reset_reset_n_in,
+ board_kernel_irq_irq => board_kernel_irq_irq,
+ board_kernel_cra_waitrequest => board_kernel_cra_waitrequest,
+ board_kernel_cra_readdata => board_kernel_cra_readdata,
+ board_kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
+ board_kernel_cra_burstcount => board_kernel_cra_burstcount,
+ board_kernel_cra_writedata => board_kernel_cra_writedata,
+ board_kernel_cra_address => board_kernel_cra_address,
+ board_kernel_cra_write => board_kernel_cra_write,
+ board_kernel_cra_read => board_kernel_cra_read,
+ board_kernel_cra_byteenable => board_kernel_cra_byteenable,
+ board_kernel_cra_debugaccess => board_kernel_cra_debugaccess,
+
+ board_kernel_register_mem_address => board_kernel_register_mem_address,
+ board_kernel_register_mem_clken => board_kernel_register_mem_clken,
+ board_kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
+ board_kernel_register_mem_write => board_kernel_register_mem_write,
+ board_kernel_register_mem_readdata => board_kernel_register_mem_readdata,
+ board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
+ board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
+
+ board_kernel_stream_src_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).valid,
+ board_kernel_stream_src_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(0).ready,
+ board_kernel_stream_snk_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).valid,
+ board_kernel_stream_snk_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(0).ready,
+
+ board_kernel_stream_src_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).valid,
+ board_kernel_stream_src_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(1).ready,
+ board_kernel_stream_snk_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).valid,
+ board_kernel_stream_snk_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(1).ready,
+
+ board_kernel_stream_src_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).valid,
+ board_kernel_stream_src_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(2).ready,
+ board_kernel_stream_snk_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).valid,
+ board_kernel_stream_snk_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(2).ready,
+
+ board_kernel_stream_src_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).valid,
+ board_kernel_stream_src_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(3).ready,
+ board_kernel_stream_snk_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).valid,
+ board_kernel_stream_snk_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(3).ready,
+
+ board_kernel_stream_src_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).valid,
+ board_kernel_stream_src_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(4).ready,
+ board_kernel_stream_snk_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).valid,
+ board_kernel_stream_snk_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(4).ready,
+
+ board_kernel_stream_src_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).valid,
+ board_kernel_stream_src_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(5).ready,
+ board_kernel_stream_snk_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).valid,
+ board_kernel_stream_snk_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(5).ready,
+
+ board_kernel_stream_src_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).valid,
+ board_kernel_stream_src_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(6).ready,
+ board_kernel_stream_snk_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).valid,
+ board_kernel_stream_snk_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(6).ready,
+
+ board_kernel_stream_src_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).valid,
+ board_kernel_stream_src_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(7).ready,
+ board_kernel_stream_snk_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).valid,
+ board_kernel_stream_snk_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(7).ready,
+
+ board_kernel_stream_src_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(0).valid,
+ board_kernel_stream_src_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(0).ready,
+ board_kernel_stream_snk_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).valid,
+ board_kernel_stream_snk_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(0).ready,
+
+ board_kernel_stream_src_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_src_out_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(1).valid,
+ board_kernel_stream_src_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(1).ready,
+ board_kernel_stream_snk_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).valid,
+ board_kernel_stream_snk_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(1).ready,
+
+ board_kernel_stream_src_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_src_out_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(2).valid,
+ board_kernel_stream_src_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(2).ready,
+ board_kernel_stream_snk_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).valid,
+ board_kernel_stream_snk_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(2).ready,
+
+ board_kernel_stream_src_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_src_out_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(3).valid,
+ board_kernel_stream_src_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(3).ready,
+ board_kernel_stream_snk_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).valid,
+ board_kernel_stream_snk_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(3).ready,
+
+ board_kernel_stream_src_lane_0_data => kernel_to_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_0_valid => kernel_to_lane_sosi_arr(0).valid,
+ board_kernel_stream_src_lane_0_ready => kernel_to_lane_siso_arr(0).ready,
+ board_kernel_stream_snk_lane_0_data => kernel_from_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_0_valid => kernel_from_lane_sosi_arr(0).valid,
+ board_kernel_stream_snk_lane_0_ready => kernel_from_lane_siso_arr(0).ready,
+
+ board_kernel_stream_src_lane_1_data => kernel_to_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_1_valid => kernel_to_lane_sosi_arr(1).valid,
+ board_kernel_stream_src_lane_1_ready => kernel_to_lane_siso_arr(1).ready,
+ board_kernel_stream_snk_lane_1_data => kernel_from_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_1_valid => kernel_from_lane_sosi_arr(1).valid,
+ board_kernel_stream_snk_lane_1_ready => kernel_from_lane_siso_arr(1).ready,
+
+ board_kernel_stream_src_lane_2_data => kernel_to_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_2_valid => kernel_to_lane_sosi_arr(2).valid,
+ board_kernel_stream_src_lane_2_ready => kernel_to_lane_siso_arr(2).ready,
+ board_kernel_stream_snk_lane_2_data => kernel_from_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_2_valid => kernel_from_lane_sosi_arr(2).valid,
+ board_kernel_stream_snk_lane_2_ready => kernel_from_lane_siso_arr(2).ready,
+
+ board_kernel_stream_src_lane_3_data => kernel_to_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_3_valid => kernel_to_lane_sosi_arr(3).valid,
+ board_kernel_stream_src_lane_3_ready => kernel_to_lane_siso_arr(3).ready,
+ board_kernel_stream_snk_lane_3_data => kernel_from_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_3_valid => kernel_from_lane_sosi_arr(3).valid,
+ board_kernel_stream_snk_lane_3_ready => kernel_from_lane_siso_arr(3).ready,
+
+ board_kernel_stream_src_lane_4_data => kernel_to_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_4_valid => kernel_to_lane_sosi_arr(4).valid,
+ board_kernel_stream_src_lane_4_ready => kernel_to_lane_siso_arr(4).ready,
+ board_kernel_stream_snk_lane_4_data => kernel_from_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_4_valid => kernel_from_lane_sosi_arr(4).valid,
+ board_kernel_stream_snk_lane_4_ready => kernel_from_lane_siso_arr(4).ready,
+
+ board_kernel_stream_src_lane_5_data => kernel_to_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_5_valid => kernel_to_lane_sosi_arr(5).valid,
+ board_kernel_stream_src_lane_5_ready => kernel_to_lane_siso_arr(5).ready,
+ board_kernel_stream_snk_lane_5_data => kernel_from_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_5_valid => kernel_from_lane_sosi_arr(5).valid,
+ board_kernel_stream_snk_lane_5_ready => kernel_from_lane_siso_arr(5).ready,
+
+ board_kernel_stream_src_lane_6_data => kernel_to_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_6_valid => kernel_to_lane_sosi_arr(6).valid,
+ board_kernel_stream_src_lane_6_ready => kernel_to_lane_siso_arr(6).ready,
+ board_kernel_stream_snk_lane_6_data => kernel_from_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_6_valid => kernel_from_lane_sosi_arr(6).valid,
+ board_kernel_stream_snk_lane_6_ready => kernel_from_lane_siso_arr(6).ready,
+
+ board_kernel_stream_src_lane_7_data => kernel_to_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_7_valid => kernel_to_lane_sosi_arr(7).valid,
+ board_kernel_stream_src_lane_7_ready => kernel_to_lane_siso_arr(7).ready,
+ board_kernel_stream_snk_lane_7_data => kernel_from_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_7_valid => kernel_from_lane_sosi_arr(7).valid,
+ board_kernel_stream_snk_lane_7_ready => kernel_from_lane_siso_arr(7).ready,
+
+ board_kernel_stream_snk_rx_monitor_0_data => kernel_rx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_0_valid => kernel_rx_monitor_sosi_arr(0).valid,
+ board_kernel_stream_snk_rx_monitor_0_ready => kernel_rx_monitor_siso_arr(0).ready,
+ board_kernel_stream_snk_tx_monitor_0_data => kernel_tx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_0_valid => kernel_tx_monitor_sosi_arr(0).valid,
+ board_kernel_stream_snk_tx_monitor_0_ready => kernel_tx_monitor_siso_arr(0).ready,
+
+ board_kernel_stream_snk_rx_monitor_1_data => kernel_rx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_1_valid => kernel_rx_monitor_sosi_arr(1).valid,
+ board_kernel_stream_snk_rx_monitor_1_ready => kernel_rx_monitor_siso_arr(1).ready,
+ board_kernel_stream_snk_tx_monitor_1_data => kernel_tx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_1_valid => kernel_tx_monitor_sosi_arr(1).valid,
+ board_kernel_stream_snk_tx_monitor_1_ready => kernel_tx_monitor_siso_arr(1).ready,
+
+ board_kernel_stream_snk_rx_monitor_2_data => kernel_rx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_2_valid => kernel_rx_monitor_sosi_arr(2).valid,
+ board_kernel_stream_snk_rx_monitor_2_ready => kernel_rx_monitor_siso_arr(2).ready,
+ board_kernel_stream_snk_tx_monitor_2_data => kernel_tx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_2_valid => kernel_tx_monitor_sosi_arr(2).valid,
+ board_kernel_stream_snk_tx_monitor_2_ready => kernel_tx_monitor_siso_arr(2).ready,
+
+ board_kernel_stream_snk_rx_monitor_3_data => kernel_rx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_3_valid => kernel_rx_monitor_sosi_arr(3).valid,
+ board_kernel_stream_snk_rx_monitor_3_ready => kernel_rx_monitor_siso_arr(3).ready,
+ board_kernel_stream_snk_tx_monitor_3_data => kernel_tx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_3_valid => kernel_tx_monitor_sosi_arr(3).valid,
+ board_kernel_stream_snk_tx_monitor_3_ready => kernel_tx_monitor_siso_arr(3).ready,
+
+ board_kernel_stream_snk_rx_monitor_4_data => kernel_rx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_4_valid => kernel_rx_monitor_sosi_arr(4).valid,
+ board_kernel_stream_snk_rx_monitor_4_ready => kernel_rx_monitor_siso_arr(4).ready,
+ board_kernel_stream_snk_tx_monitor_4_data => kernel_tx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_4_valid => kernel_tx_monitor_sosi_arr(4).valid,
+ board_kernel_stream_snk_tx_monitor_4_ready => kernel_tx_monitor_siso_arr(4).ready,
+
+ board_kernel_stream_snk_rx_monitor_5_data => kernel_rx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_5_valid => kernel_rx_monitor_sosi_arr(5).valid,
+ board_kernel_stream_snk_rx_monitor_5_ready => kernel_rx_monitor_siso_arr(5).ready,
+ board_kernel_stream_snk_tx_monitor_5_data => kernel_tx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_5_valid => kernel_tx_monitor_sosi_arr(5).valid,
+ board_kernel_stream_snk_tx_monitor_5_ready => kernel_tx_monitor_siso_arr(5).ready,
+
+ board_kernel_stream_snk_rx_monitor_6_data => kernel_rx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_6_valid => kernel_rx_monitor_sosi_arr(6).valid,
+ board_kernel_stream_snk_rx_monitor_6_ready => kernel_rx_monitor_siso_arr(6).ready,
+ board_kernel_stream_snk_tx_monitor_6_data => kernel_tx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_6_valid => kernel_tx_monitor_sosi_arr(6).valid,
+ board_kernel_stream_snk_tx_monitor_6_ready => kernel_tx_monitor_siso_arr(6).ready,
+
+ board_kernel_stream_snk_rx_monitor_7_data => kernel_rx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_7_valid => kernel_rx_monitor_sosi_arr(7).valid,
+ board_kernel_stream_snk_rx_monitor_7_ready => kernel_rx_monitor_siso_arr(7).ready,
+ board_kernel_stream_snk_tx_monitor_7_data => kernel_tx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_7_valid => kernel_tx_monitor_sosi_arr(7).valid,
+ board_kernel_stream_snk_tx_monitor_7_ready => kernel_tx_monitor_siso_arr(7).ready,
+
+ board_kernel_stream_src_bs_data => kernel_bs_sosi.data(c_kernel_bs_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_bs_valid => kernel_bs_sosi.valid,
+ board_kernel_stream_src_bs_ready => OPEN,
+
+ board_kernel_stream_src_mm_io_data => ta2_unb2b_mm_io_src_out.data(c_kernel_mm_io_mosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_mm_io_valid => ta2_unb2b_mm_io_src_out.valid,
+ board_kernel_stream_src_mm_io_ready => ta2_unb2b_mm_io_src_in.ready,
+ board_kernel_stream_snk_mm_io_data => ta2_unb2b_mm_io_snk_in.data(c_kernel_mm_io_miso_channel_w - 1 downto 0),
+ board_kernel_stream_snk_mm_io_valid => ta2_unb2b_mm_io_snk_in.valid,
+ board_kernel_stream_snk_mm_io_ready => ta2_unb2b_mm_io_snk_out.ready
- );
+ );
i_kernel_rst <= not board_kernel_reset_reset_n; -- qsys output used to reset all OpenCL BSP components
end generate;
@@ -1173,164 +1173,170 @@ begin
i_kernel_rst <= not i_reset_n;
board_kernel_clk_clk <= st_clk;
- u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
- u_mm_file_reg_dp_xonoff_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_BG")
- port map(mm_rst, mm_clk, reg_dp_xonoff_bg_mosi, reg_dp_xonoff_bg_miso );
- u_mm_file_reg_dp_xonoff_from_lane: mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_FROM_LANE")
- port map(mm_rst, mm_clk, reg_dp_xonoff_from_lane_mosi, reg_dp_xonoff_from_lane_miso );
- u_mm_file_reg_bsn_monitor_rx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_mosi, reg_bsn_monitor_v2_rx_miso );
- u_mm_file_reg_bsn_monitor_tx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_mosi, reg_bsn_monitor_v2_tx_miso );
- u_mm_file_reg_bg_ctrl : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_RING")
- port map(mm_rst, mm_clk, reg_bg_ctrl_mosi, reg_bg_ctrl_miso );
+ u_mm_file_reg_sdp_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+ port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+ u_mm_file_reg_dp_xonoff_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_BG")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_bg_mosi, reg_dp_xonoff_bg_miso );
+ u_mm_file_reg_dp_xonoff_from_lane: mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_FROM_LANE")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_from_lane_mosi, reg_dp_xonoff_from_lane_miso );
+ u_mm_file_reg_bsn_monitor_rx : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_mosi, reg_bsn_monitor_v2_rx_miso );
+ u_mm_file_reg_bsn_monitor_tx : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_mosi, reg_bsn_monitor_v2_tx_miso );
+ u_mm_file_reg_bg_ctrl : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_RING")
+ port map(mm_rst, mm_clk, reg_bg_ctrl_mosi, reg_bg_ctrl_miso );
end generate;
i_reset_n <= not mm_rst; -- First reset OpenCL components in qsys (board)
-- Kernel should start later than BSP. Delaying the reset from the qsys output to form the reset of the OpenCL kernel.
-- This way it is ensured the OpenCL kernel does not start reading/writing data before the components in the OpenCL BSP are ready.
u_common_areset : entity common_lib.common_areset
- generic map (
- g_rst_level => '0',
- g_delay_len => 9
- )
- port map (
- in_rst => i_kernel_rst,
- clk => board_kernel_clk_clk,
- out_rst => board_kernel_reset_reset_n_in
- );
------------------------------------------------------------------------------
+ generic map (
+ g_rst_level => '0',
+ g_delay_len => 9
+ )
+ port map (
+ in_rst => i_kernel_rst,
+ clk => board_kernel_clk_clk,
+ out_rst => board_kernel_reset_reset_n_in
+ );
+ -----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl_unb2b_board : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => st_pps,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- RAM scrap
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => st_pps,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- RAM scrap
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- Board qsys
-----------------------------------------------------------------------------
gen_board: if g_sim = false generate
- board_inst : board
- port map (
+ board_inst : board
+ port map (
clk_clk => mm_clk,
reset_reset_n => i_reset_n,
@@ -1513,6 +1519,6 @@ begin
reg_ta2_unb2b_mm_io_write_export => reg_ta2_unb2b_mm_io_mosi.wr,
reg_ta2_unb2b_mm_io_writedata_export => reg_ta2_unb2b_mm_io_mosi.wrdata(c_word_w - 1 downto 0),
reg_ta2_unb2b_mm_io_waitrequest_export => reg_ta2_unb2b_mm_io_miso.waitrequest
- );
+ );
end generate;
end str;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
index deca506ed8..991ef58a40 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
@@ -25,212 +25,212 @@
-- . Contains components instantiated by top.vhd
-- --------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package top_components_pkg is
- component board is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- kernel_clk_clk : out std_logic; -- clk
- kernel_reset_reset_n : out std_logic; -- reset_n
- kernel_clk2x_clk : out std_logic; -- clk
- kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
- kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
- kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
- kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
- kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
- kernel_cra_address : out std_logic_vector(29 downto 0); -- address
- kernel_cra_write : out std_logic; -- write
- kernel_cra_read : out std_logic; -- read
- kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
- kernel_cra_debugaccess : out std_logic; -- debugaccess
- kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
- kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_rx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_tx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_tx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_tx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_ring_reset_export : out std_logic; -- export
- ram_diag_bg_ring_clk_export : out std_logic; -- export
- ram_diag_bg_ring_address_export : out std_logic_vector(9 downto 0); -- export
- ram_diag_bg_ring_write_export : out std_logic; -- export
- ram_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_ring_read_export : out std_logic; -- export
- ram_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_ring_reset_export : out std_logic; -- export
- reg_diag_bg_ring_clk_export : out std_logic; -- export
- reg_diag_bg_ring_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_ring_write_export : out std_logic; -- export
- reg_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_ring_read_export : out std_logic; -- export
- reg_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_bg_reset_export : out std_logic; -- export
- reg_dp_xonoff_bg_clk_export : out std_logic; -- export
- reg_dp_xonoff_bg_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_xonoff_bg_write_export : out std_logic; -- export
- reg_dp_xonoff_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_bg_read_export : out std_logic; -- export
- reg_dp_xonoff_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_from_lane_reset_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_clk_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_xonoff_from_lane_write_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_from_lane_read_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
- reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component board;
+ component board is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ kernel_clk_clk : out std_logic; -- clk
+ kernel_reset_reset_n : out std_logic; -- reset_n
+ kernel_clk2x_clk : out std_logic; -- clk
+ kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
+ kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
+ kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
+ kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
+ kernel_cra_address : out std_logic_vector(29 downto 0); -- address
+ kernel_cra_write : out std_logic; -- write
+ kernel_cra_read : out std_logic; -- read
+ kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
+ kernel_cra_debugaccess : out std_logic; -- debugaccess
+ kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
+ kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_rx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_tx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_tx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_tx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_ring_reset_export : out std_logic; -- export
+ ram_diag_bg_ring_clk_export : out std_logic; -- export
+ ram_diag_bg_ring_address_export : out std_logic_vector(9 downto 0); -- export
+ ram_diag_bg_ring_write_export : out std_logic; -- export
+ ram_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_ring_read_export : out std_logic; -- export
+ ram_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_ring_reset_export : out std_logic; -- export
+ reg_diag_bg_ring_clk_export : out std_logic; -- export
+ reg_diag_bg_ring_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_ring_write_export : out std_logic; -- export
+ reg_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_ring_read_export : out std_logic; -- export
+ reg_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_bg_reset_export : out std_logic; -- export
+ reg_dp_xonoff_bg_clk_export : out std_logic; -- export
+ reg_dp_xonoff_bg_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_xonoff_bg_write_export : out std_logic; -- export
+ reg_dp_xonoff_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_bg_read_export : out std_logic; -- export
+ reg_dp_xonoff_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_from_lane_reset_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_clk_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_xonoff_from_lane_write_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_from_lane_read_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component board;
component freeze_wrapper is
port (
@@ -463,7 +463,7 @@ package top_components_pkg is
board_kernel_stream_snk_mm_io_data : out std_logic_vector(31 downto 0);
board_kernel_stream_snk_mm_io_valid : out std_logic;
board_kernel_stream_snk_mm_io_ready : out std_logic
- );
+ );
end component freeze_wrapper;
end top_components_pkg;
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
index 3af8c3fc2f..8194075076 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
@@ -32,17 +32,17 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, tech_ddr_lib, ta2_unb2b_40GbE_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_1gbe_lib, ta2_unb2b_mm_io_lib, ta2_unb2b_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_component_pkg.all;
-use work.top_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_component_pkg.all;
+ use work.top_components_pkg.all;
entity top is
generic (
@@ -104,7 +104,7 @@ entity top is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_ring.bus_w - 1 downto 0);
- -- back transceivers
+ -- back transceivers
BCK_RX : in std_logic_vector(0 downto 0);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -302,10 +302,10 @@ architecture str of top is
signal board_kernel_mem0_read : std_logic; -- := 'X'; -- write
signal board_kernel_mem0_byteenable : std_logic_vector(63 downto 0); -- := (others => 'X'); -- byteenable
signal board_kernel_mem0_debugaccess : std_logic; -- := 'X'; -- write
--- SIGNAL amm_readdata : std_logic_vector(575 downto 0); -- readdata
--- SIGNAL amm_burstcount : std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
--- SIGNAL amm_writedata : std_logic_vector(575 downto 0); -- := (others => 'X'); -- address
--- SIGNAL amm_byteenable : std_logic_vector(71 downto 0); -- := (others => 'X'); -- byteenable
+ -- SIGNAL amm_readdata : std_logic_vector(575 downto 0); -- readdata
+ -- SIGNAL amm_burstcount : std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
+ -- SIGNAL amm_writedata : std_logic_vector(575 downto 0); -- := (others => 'X'); -- address
+ -- SIGNAL amm_byteenable : std_logic_vector(71 downto 0); -- := (others => 'X'); -- byteenable
signal board_kernel_register_mem_address : std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
signal board_kernel_register_mem_clken : std_logic; -- := 'X'; -- clken
@@ -356,21 +356,21 @@ begin
QSFP_1_TX <= i_QSFP_TX(1);
u_unb2b_board_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
- --green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- --red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX -- ,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX -- ,
- --QSFP_LED => QSFP_LED
- );
+ --QSFP_LED => QSFP_LED
+ );
------------------------
-- qsfp LEDs controller
@@ -382,21 +382,21 @@ begin
unb2b_board_qsfp_leds_tx_src_in_arr(12).xon <= ta2_unb2b_40GbE_snk_out_arr(2).xon;
u_unb2b_board_qsfp_leds : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus + c_nof_ring_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
-
- tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus + c_nof_ring_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus + c_nof_ring_bus - 1 downto 0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus + c_nof_ring_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus + c_nof_ring_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus + c_nof_ring_bus - 1 downto 0)
+ );
gen_leds : for i in 0 to c_nof_qsfp_bus + c_nof_ring_bus - 1 generate
QSFP_LED(i * 2) <= qsfp_green_led_arr(i);
@@ -412,15 +412,15 @@ begin
RING_1_TX <= i_RING_TX(1);
u_ring_io : entity unb2b_board_lib.unb2b_board_ring_io
- generic map (
- g_nof_ring_bus => c_nof_ring_bus
- )
- port map (
- serial_tx_arr => unb2b_board_ring_io_serial_tx_arr,
- serial_rx_arr => unb2b_board_ring_io_serial_rx_arr,
- RING_RX => i_RING_RX,
- RING_TX => i_RING_TX
- );
+ generic map (
+ g_nof_ring_bus => c_nof_ring_bus
+ )
+ port map (
+ serial_tx_arr => unb2b_board_ring_io_serial_tx_arr,
+ serial_rx_arr => unb2b_board_ring_io_serial_rx_arr,
+ RING_RX => i_RING_RX,
+ RING_TX => i_RING_TX
+ );
---------
-- 40GbE
@@ -438,26 +438,26 @@ begin
ta2_unb2b_40GbE_rx_serial_r(11 downto 8) <= unb2b_board_ring_io_serial_rx_arr(3 + c_ring_bus_w downto c_ring_bus_w);
u_ta2_unb2b_40GbE : entity ta2_unb2b_40GbE_lib.ta2_unb2b_40GbE
- generic map (
- g_nof_mac => c_nof_40GbE_IP
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_nof_mac => c_nof_40GbE_IP
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- clk_ref_r => SA_CLK,
+ clk_ref_r => SA_CLK,
- tx_serial_r => ta2_unb2b_40GbE_tx_serial_r,
- rx_serial_r => ta2_unb2b_40GbE_rx_serial_r,
+ tx_serial_r => ta2_unb2b_40GbE_tx_serial_r,
+ rx_serial_r => ta2_unb2b_40GbE_rx_serial_r,
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- src_out_arr => ta2_unb2b_40GbE_src_out_arr,
- src_in_arr => ta2_unb2b_40GbE_src_in_arr,
- snk_out_arr => ta2_unb2b_40GbE_snk_out_arr,
- snk_in_arr => ta2_unb2b_40GbE_snk_in_arr
- );
+ src_out_arr => ta2_unb2b_40GbE_src_out_arr,
+ src_in_arr => ta2_unb2b_40GbE_src_in_arr,
+ snk_out_arr => ta2_unb2b_40GbE_snk_out_arr,
+ snk_in_arr => ta2_unb2b_40GbE_snk_in_arr
+ );
----------
-- 10GbE
@@ -467,100 +467,100 @@ begin
ta2_unb2b_10GbE_rx_serial_r(0) <= unb2b_board_front_io_serial_rx_arr(0);
u_ta2_unb2b_10GbE : entity ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
- generic map (
- g_nof_mac => c_nof_10GbE_IP
- )
- port map (
- mm_clk => '0', -- mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_nof_mac => c_nof_10GbE_IP
+ )
+ port map (
+ mm_clk => '0', -- mm_clk,
+ mm_rst => mm_rst,
- clk_ref_r => SA_CLK,
+ clk_ref_r => SA_CLK,
- tx_serial_r => ta2_unb2b_10GbE_tx_serial_r,
- rx_serial_r => ta2_unb2b_10GbE_rx_serial_r,
+ tx_serial_r => ta2_unb2b_10GbE_tx_serial_r,
+ rx_serial_r => ta2_unb2b_10GbE_rx_serial_r,
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- src_out_arr => ta2_unb2b_10GbE_src_out_arr,
- src_in_arr => ta2_unb2b_10GbE_src_in_arr,
- snk_out_arr => ta2_unb2b_10GbE_snk_out_arr,
- snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
- );
+ src_out_arr => ta2_unb2b_10GbE_src_out_arr,
+ src_in_arr => ta2_unb2b_10GbE_src_in_arr,
+ snk_out_arr => ta2_unb2b_10GbE_snk_out_arr,
+ snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
+ );
-----------------------------
-- 1GbE Monitoring & Control
-----------------------------
u_ta2_unb2b_1GbE : entity ta2_unb2b_1GbE_lib.ta2_unb2b_1GbE
- port map (
- st_clk => st_clk,
- st_rst => st_rst,
+ port map (
+ st_clk => st_clk,
+ st_rst => st_rst,
- udp_tx_sosi => eth1g_udp_tx_sosi_arr(0),
- udp_tx_siso => eth1g_udp_tx_siso_arr(0),
- udp_rx_sosi => eth1g_udp_rx_sosi_arr(0),
- udp_rx_siso => eth1g_udp_rx_siso_arr(0),
+ udp_tx_sosi => eth1g_udp_tx_sosi_arr(0),
+ udp_tx_siso => eth1g_udp_tx_siso_arr(0),
+ udp_rx_sosi => eth1g_udp_rx_sosi_arr(0),
+ udp_rx_siso => eth1g_udp_rx_siso_arr(0),
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- src_out => ta2_unb2b_1GbE_src_out,
- src_in => ta2_unb2b_1GbE_src_in,
- snk_out => ta2_unb2b_1GbE_snk_out,
- snk_in => ta2_unb2b_1GbE_snk_in
- );
+ src_out => ta2_unb2b_1GbE_src_out,
+ src_in => ta2_unb2b_1GbE_src_in,
+ snk_out => ta2_unb2b_1GbE_snk_out,
+ snk_in => ta2_unb2b_1GbE_snk_in
+ );
--------------------------------------
-- Monitoring & Control UNB protocol
--------------------------------------
u_ta2_unb2b_mm_io : entity ta2_unb2b_mm_io_lib.ta2_unb2b_mm_io
- generic map(
- g_use_opencl => true
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_use_opencl => true
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- mm_mosi => reg_ta2_unb2b_mm_io_mosi,
- mm_miso => reg_ta2_unb2b_mm_io_miso,
+ mm_mosi => reg_ta2_unb2b_mm_io_mosi,
+ mm_miso => reg_ta2_unb2b_mm_io_miso,
- snk_in => ta2_unb2b_mm_io_snk_in,
- snk_out => ta2_unb2b_mm_io_snk_out,
- src_out => ta2_unb2b_mm_io_src_out,
- src_in => ta2_unb2b_mm_io_src_in
+ snk_in => ta2_unb2b_mm_io_snk_in,
+ snk_out => ta2_unb2b_mm_io_snk_out,
+ src_out => ta2_unb2b_mm_io_src_out,
+ src_in => ta2_unb2b_mm_io_src_in
- );
+ );
----------
-- ADC
----------
u_ta2_unb2b_jesd204b : entity ta2_unb2b_jesd204b_lib.ta2_unb2b_jesd204b
- generic map(
- g_nof_streams => c_nof_ADC
- )
- port map(
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_nof_streams => c_nof_ADC
+ )
+ port map(
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- jesd204b_mosi => reg_ta2_unb2b_jesd204b_mosi,
- jesd204b_miso => reg_ta2_unb2b_jesd204b_miso,
+ jesd204b_mosi => reg_ta2_unb2b_jesd204b_mosi,
+ jesd204b_miso => reg_ta2_unb2b_jesd204b_miso,
- -- JESD204B external signals
- jesd204b_refclk => BCK_REF_CLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n_arr => JESD204B_SYNC,
+ -- JESD204B external signals
+ jesd204b_refclk => BCK_REF_CLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n_arr => JESD204B_SYNC,
- serial_rx_arr => BCK_RX,
+ serial_rx_arr => BCK_RX,
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- src_out_arr => ta2_unb2b_ADC_src_out_arr,
- src_in_arr => ta2_unb2b_ADC_src_in_arr
- );
+ src_out_arr => ta2_unb2b_ADC_src_out_arr,
+ src_in_arr => ta2_unb2b_ADC_src_in_arr
+ );
----------
-- DDR4
@@ -695,340 +695,340 @@ begin
-- Kernel should start later than BSP
u_common_areset : entity common_lib.common_areset
- generic map (
- g_rst_level => '0',
- g_delay_len => 9
- )
- port map (
- in_rst => i_kernel_rst,
- clk => board_kernel_clk_clk,
- out_rst => board_kernel_reset_reset_n_in
- );
+ generic map (
+ g_rst_level => '0',
+ g_delay_len => 9
+ )
+ port map (
+ in_rst => i_kernel_rst,
+ clk => board_kernel_clk_clk,
+ out_rst => board_kernel_reset_reset_n_in
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl_unb2b_board : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_udp_offload => c_use_1GbE_udp_offload,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-
- -- RAM scrap
- ram_scrap_mosi => c_mem_mosi_rst,
- ram_scrap_miso => OPEN,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_udp_offload => c_use_1GbE_udp_offload,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+
+ -- RAM scrap
+ ram_scrap_mosi => c_mem_mosi_rst,
+ ram_scrap_miso => OPEN,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- Board qsys
-----------------------------------------------------------------------------
board_inst : board
port map (
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- kernel_clk_clk => board_kernel_clk_clk,
- kernel_clk2x_clk => board_kernel_clk2x_clk,
- kernel_reset_reset_n => board_kernel_reset_reset_n,
-
- kernel_interface_sw_reset_in_reset => mm_rst,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 4 downto 0), -- temp fix
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 2 downto 0), -- temp fix
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_ta2_unb2b_jesd204b_address_export => reg_ta2_unb2b_jesd204b_mosi.address(7 downto 0),
- reg_ta2_unb2b_jesd204b_read_export => reg_ta2_unb2b_jesd204b_mosi.rd,
- reg_ta2_unb2b_jesd204b_readdata_export => reg_ta2_unb2b_jesd204b_miso.rddata(c_word_w - 1 downto 0),
- reg_ta2_unb2b_jesd204b_write_export => reg_ta2_unb2b_jesd204b_mosi.wr,
- reg_ta2_unb2b_jesd204b_writedata_export => reg_ta2_unb2b_jesd204b_mosi.wrdata(c_word_w - 1 downto 0),
- reg_ta2_unb2b_jesd204b_waitrequest_export => reg_ta2_unb2b_jesd204b_miso.waitrequest,
-
- kernel_cra_waitrequest => board_kernel_cra_waitrequest,
- kernel_cra_readdata => board_kernel_cra_readdata,
- kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
- kernel_cra_burstcount => board_kernel_cra_burstcount,
- kernel_cra_writedata => board_kernel_cra_writedata,
- kernel_cra_address => board_kernel_cra_address,
- kernel_cra_write => board_kernel_cra_write,
- kernel_cra_read => board_kernel_cra_read,
- kernel_cra_byteenable => board_kernel_cra_byteenable,
- kernel_cra_debugaccess => board_kernel_cra_debugaccess,
-
- kernel_irq_irq => board_kernel_irq_irq,
-
- kernel_register_mem_address => board_kernel_register_mem_address,
- kernel_register_mem_clken => board_kernel_register_mem_clken,
- kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
- kernel_register_mem_write => board_kernel_register_mem_write,
- kernel_register_mem_readdata => board_kernel_register_mem_readdata,
- kernel_register_mem_writedata => board_kernel_register_mem_writedata,
- kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
-
- reg_ta2_unb2b_mm_io_address_export => reg_ta2_unb2b_mm_io_mosi.address(7 downto 0),
- reg_ta2_unb2b_mm_io_read_export => reg_ta2_unb2b_mm_io_mosi.rd,
- reg_ta2_unb2b_mm_io_readdata_export => reg_ta2_unb2b_mm_io_miso.rddata(c_word_w - 1 downto 0),
- reg_ta2_unb2b_mm_io_write_export => reg_ta2_unb2b_mm_io_mosi.wr,
- reg_ta2_unb2b_mm_io_writedata_export => reg_ta2_unb2b_mm_io_mosi.wrdata(c_word_w - 1 downto 0),
- reg_ta2_unb2b_mm_io_waitrequest_export => reg_ta2_unb2b_mm_io_miso.waitrequest,
-
- kernel_mem0_waitrequest => board_kernel_mem0_waitrequest,
- kernel_mem0_readdata => board_kernel_mem0_readdata,
- kernel_mem0_readdatavalid => board_kernel_mem0_readdatavalid,
- kernel_mem0_burstcount => board_kernel_mem0_burstcount,
- kernel_mem0_writedata => board_kernel_mem0_writedata,
- kernel_mem0_address => board_kernel_mem0_address,
- kernel_mem0_write => board_kernel_mem0_write,
- kernel_mem0_read => board_kernel_mem0_read,
- kernel_mem0_byteenable => board_kernel_mem0_byteenable,
- kernel_mem0_debugaccess => board_kernel_mem0_debugaccess,
-
- ddr4a_pll_ref_clk => MB_I_REF_CLK,
- ddr4a_oct_oct_rzqin => MB_I_IN.oct_rzqin,
- ddr4a_mem_ck => MB_I_OU.ck(g_tech_ddr.ck_w - 1 downto 0),
- ddr4a_mem_ck_n => MB_I_OU.ck_n(g_tech_ddr.ck_w - 1 downto 0),
- ddr4a_mem_a => MB_I_OU.a(g_tech_ddr.a_w - 1 downto 0),
- sl(ddr4a_mem_act_n) => MB_I_OU.act_n,
- ddr4a_mem_ba => MB_I_OU.ba(g_tech_ddr.ba_w - 1 downto 0),
- ddr4a_mem_bg => MB_I_OU.bg(g_tech_ddr.bg_w - 1 downto 0),
- ddr4a_mem_cke => MB_I_OU.cke(g_tech_ddr.cke_w - 1 downto 0),
- ddr4a_mem_cs_n => MB_I_OU.cs_n(g_tech_ddr.cs_w - 1 downto 0),
- ddr4a_mem_odt => MB_I_OU.odt(g_tech_ddr.odt_w - 1 downto 0),
- sl(ddr4a_mem_reset_n) => MB_I_OU.reset_n,
- sl(ddr4a_mem_par) => MB_I_OU.par,
- ddr4a_mem_alert_n => slv(MB_I_IN.alert_n),
- ddr4a_mem_dqs => MB_I_IO.dqs(g_tech_ddr.dqs_w - 1 downto 0),
- ddr4a_mem_dqs_n => MB_I_IO.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
- ddr4a_mem_dq => MB_I_IO.dq(g_tech_ddr.dq_w - 1 downto 0),
- ddr4a_mem_dbi_n => MB_I_IO.dbi_n(g_tech_ddr.dbi_w - 1 downto 0)
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ kernel_clk_clk => board_kernel_clk_clk,
+ kernel_clk2x_clk => board_kernel_clk2x_clk,
+ kernel_reset_reset_n => board_kernel_reset_reset_n,
+
+ kernel_interface_sw_reset_in_reset => mm_rst,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 4 downto 0), -- temp fix
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 2 downto 0), -- temp fix
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_ta2_unb2b_jesd204b_address_export => reg_ta2_unb2b_jesd204b_mosi.address(7 downto 0),
+ reg_ta2_unb2b_jesd204b_read_export => reg_ta2_unb2b_jesd204b_mosi.rd,
+ reg_ta2_unb2b_jesd204b_readdata_export => reg_ta2_unb2b_jesd204b_miso.rddata(c_word_w - 1 downto 0),
+ reg_ta2_unb2b_jesd204b_write_export => reg_ta2_unb2b_jesd204b_mosi.wr,
+ reg_ta2_unb2b_jesd204b_writedata_export => reg_ta2_unb2b_jesd204b_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_ta2_unb2b_jesd204b_waitrequest_export => reg_ta2_unb2b_jesd204b_miso.waitrequest,
+
+ kernel_cra_waitrequest => board_kernel_cra_waitrequest,
+ kernel_cra_readdata => board_kernel_cra_readdata,
+ kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
+ kernel_cra_burstcount => board_kernel_cra_burstcount,
+ kernel_cra_writedata => board_kernel_cra_writedata,
+ kernel_cra_address => board_kernel_cra_address,
+ kernel_cra_write => board_kernel_cra_write,
+ kernel_cra_read => board_kernel_cra_read,
+ kernel_cra_byteenable => board_kernel_cra_byteenable,
+ kernel_cra_debugaccess => board_kernel_cra_debugaccess,
+
+ kernel_irq_irq => board_kernel_irq_irq,
+
+ kernel_register_mem_address => board_kernel_register_mem_address,
+ kernel_register_mem_clken => board_kernel_register_mem_clken,
+ kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
+ kernel_register_mem_write => board_kernel_register_mem_write,
+ kernel_register_mem_readdata => board_kernel_register_mem_readdata,
+ kernel_register_mem_writedata => board_kernel_register_mem_writedata,
+ kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
+
+ reg_ta2_unb2b_mm_io_address_export => reg_ta2_unb2b_mm_io_mosi.address(7 downto 0),
+ reg_ta2_unb2b_mm_io_read_export => reg_ta2_unb2b_mm_io_mosi.rd,
+ reg_ta2_unb2b_mm_io_readdata_export => reg_ta2_unb2b_mm_io_miso.rddata(c_word_w - 1 downto 0),
+ reg_ta2_unb2b_mm_io_write_export => reg_ta2_unb2b_mm_io_mosi.wr,
+ reg_ta2_unb2b_mm_io_writedata_export => reg_ta2_unb2b_mm_io_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_ta2_unb2b_mm_io_waitrequest_export => reg_ta2_unb2b_mm_io_miso.waitrequest,
+
+ kernel_mem0_waitrequest => board_kernel_mem0_waitrequest,
+ kernel_mem0_readdata => board_kernel_mem0_readdata,
+ kernel_mem0_readdatavalid => board_kernel_mem0_readdatavalid,
+ kernel_mem0_burstcount => board_kernel_mem0_burstcount,
+ kernel_mem0_writedata => board_kernel_mem0_writedata,
+ kernel_mem0_address => board_kernel_mem0_address,
+ kernel_mem0_write => board_kernel_mem0_write,
+ kernel_mem0_read => board_kernel_mem0_read,
+ kernel_mem0_byteenable => board_kernel_mem0_byteenable,
+ kernel_mem0_debugaccess => board_kernel_mem0_debugaccess,
+
+ ddr4a_pll_ref_clk => MB_I_REF_CLK,
+ ddr4a_oct_oct_rzqin => MB_I_IN.oct_rzqin,
+ ddr4a_mem_ck => MB_I_OU.ck(g_tech_ddr.ck_w - 1 downto 0),
+ ddr4a_mem_ck_n => MB_I_OU.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ ddr4a_mem_a => MB_I_OU.a(g_tech_ddr.a_w - 1 downto 0),
+ sl(ddr4a_mem_act_n) => MB_I_OU.act_n,
+ ddr4a_mem_ba => MB_I_OU.ba(g_tech_ddr.ba_w - 1 downto 0),
+ ddr4a_mem_bg => MB_I_OU.bg(g_tech_ddr.bg_w - 1 downto 0),
+ ddr4a_mem_cke => MB_I_OU.cke(g_tech_ddr.cke_w - 1 downto 0),
+ ddr4a_mem_cs_n => MB_I_OU.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ ddr4a_mem_odt => MB_I_OU.odt(g_tech_ddr.odt_w - 1 downto 0),
+ sl(ddr4a_mem_reset_n) => MB_I_OU.reset_n,
+ sl(ddr4a_mem_par) => MB_I_OU.par,
+ ddr4a_mem_alert_n => slv(MB_I_IN.alert_n),
+ ddr4a_mem_dqs => MB_I_IO.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ ddr4a_mem_dqs_n => MB_I_IO.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ ddr4a_mem_dq => MB_I_IO.dq(g_tech_ddr.dq_w - 1 downto 0),
+ ddr4a_mem_dbi_n => MB_I_IO.dbi_n(g_tech_ddr.dbi_w - 1 downto 0)
);
end str;
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
index fa7090c8ba..bb76b22f5f 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
@@ -25,199 +25,199 @@
-- . Contains components instantiated by top.vhd
-- --------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package top_components_pkg is
- component board is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- kernel_register_mem_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address
- kernel_register_mem_clken : in std_logic := 'X'; -- clken
- kernel_register_mem_chipselect : in std_logic := 'X'; -- chipselect
- kernel_register_mem_write : in std_logic := 'X'; -- write
- kernel_register_mem_readdata : out std_logic_vector(255 downto 0); -- readdata
- kernel_register_mem_writedata : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
- kernel_register_mem_byteenable : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- kernel_clk_clk : out std_logic; -- clk
- kernel_reset_reset_n : out std_logic; -- reset_n
- kernel_clk2x_clk : out std_logic; -- clk
- kernel_mem0_waitrequest : out std_logic; -- waitrequest
- kernel_mem0_readdata : out std_logic_vector(511 downto 0); -- readdata
- kernel_mem0_readdatavalid : out std_logic; -- readdatavalid
- kernel_mem0_burstcount : in std_logic_vector(4 downto 0) := (others => 'X'); -- burstcount
- kernel_mem0_writedata : in std_logic_vector(511 downto 0) := (others => 'X'); -- writedata
- kernel_mem0_address : in std_logic_vector(32 downto 0) := (others => 'X'); -- address
- kernel_mem0_write : in std_logic := 'X'; -- write
- kernel_mem0_read : in std_logic := 'X'; -- read
- kernel_mem0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
- kernel_mem0_debugaccess : in std_logic := 'X'; -- debugaccess
- kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
- kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
- kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
- kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
- kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
- kernel_cra_address : out std_logic_vector(29 downto 0); -- address
- kernel_cra_write : out std_logic; -- write
- kernel_cra_read : out std_logic; -- read
- kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
- kernel_cra_debugaccess : out std_logic; -- debugaccess
- kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
- kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
- ddr4a_pll_ref_clk : in std_logic := 'X'; -- clk
- ddr4a_oct_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- ddr4a_mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- ddr4a_mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- ddr4a_mem_a : out std_logic_vector(16 downto 0); -- mem_a
- ddr4a_mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- ddr4a_mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- ddr4a_mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- ddr4a_mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- ddr4a_mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- ddr4a_mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- ddr4a_mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- ddr4a_mem_par : out std_logic_vector(0 downto 0); -- mem_par
- ddr4a_mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- ddr4a_mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
- ddr4a_mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
- ddr4a_mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
- ddr4a_mem_dbi_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dbi_n
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_jesd204b_address_export : out std_logic_vector(7 downto 0); -- export
- reg_ta2_unb2b_jesd204b_clk_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_read_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ta2_unb2b_jesd204b_reset_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_waitrequest_export : in std_logic := 'X'; -- export
- reg_ta2_unb2b_jesd204b_write_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
- reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component board;
+ component board is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ kernel_register_mem_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address
+ kernel_register_mem_clken : in std_logic := 'X'; -- clken
+ kernel_register_mem_chipselect : in std_logic := 'X'; -- chipselect
+ kernel_register_mem_write : in std_logic := 'X'; -- write
+ kernel_register_mem_readdata : out std_logic_vector(255 downto 0); -- readdata
+ kernel_register_mem_writedata : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
+ kernel_register_mem_byteenable : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ kernel_clk_clk : out std_logic; -- clk
+ kernel_reset_reset_n : out std_logic; -- reset_n
+ kernel_clk2x_clk : out std_logic; -- clk
+ kernel_mem0_waitrequest : out std_logic; -- waitrequest
+ kernel_mem0_readdata : out std_logic_vector(511 downto 0); -- readdata
+ kernel_mem0_readdatavalid : out std_logic; -- readdatavalid
+ kernel_mem0_burstcount : in std_logic_vector(4 downto 0) := (others => 'X'); -- burstcount
+ kernel_mem0_writedata : in std_logic_vector(511 downto 0) := (others => 'X'); -- writedata
+ kernel_mem0_address : in std_logic_vector(32 downto 0) := (others => 'X'); -- address
+ kernel_mem0_write : in std_logic := 'X'; -- write
+ kernel_mem0_read : in std_logic := 'X'; -- read
+ kernel_mem0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
+ kernel_mem0_debugaccess : in std_logic := 'X'; -- debugaccess
+ kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
+ kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
+ kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
+ kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
+ kernel_cra_address : out std_logic_vector(29 downto 0); -- address
+ kernel_cra_write : out std_logic; -- write
+ kernel_cra_read : out std_logic; -- read
+ kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
+ kernel_cra_debugaccess : out std_logic; -- debugaccess
+ kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
+ kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
+ ddr4a_pll_ref_clk : in std_logic := 'X'; -- clk
+ ddr4a_oct_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ ddr4a_mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ ddr4a_mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ ddr4a_mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ ddr4a_mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ ddr4a_mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ ddr4a_mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ ddr4a_mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ ddr4a_mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ ddr4a_mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ ddr4a_mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ ddr4a_mem_par : out std_logic_vector(0 downto 0); -- mem_par
+ ddr4a_mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
+ ddr4a_mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
+ ddr4a_mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
+ ddr4a_mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
+ ddr4a_mem_dbi_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dbi_n
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_jesd204b_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_ta2_unb2b_jesd204b_clk_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_read_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ta2_unb2b_jesd204b_reset_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_waitrequest_export : in std_logic := 'X'; -- export
+ reg_ta2_unb2b_jesd204b_write_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component board;
component freeze_wrapper is
port (
@@ -300,7 +300,7 @@ package top_components_pkg is
board_kernel_stream_src_ADC_data : in std_logic_vector(15 downto 0);
board_kernel_stream_src_ADC_valid : in std_logic;
board_kernel_stream_src_ADC_ready : out std_logic
- );
+ );
end component freeze_wrapper;
end top_components_pkg;
diff --git a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
index 931a44d841..27f18d3477 100644
--- a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
+++ b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
@@ -61,10 +61,10 @@
-- in mind that IO channels must be a multiple of 8 bits (bytes).
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
entity ta2_channel_cross is
generic (
@@ -128,56 +128,56 @@ begin
assert g_nof_bytes <= 32 report "g_nof_bytes of ta2_channel_cross is configured higher than 32" severity ERROR;
gen_streams: for stream in 0 to g_nof_streams - 1 generate
- -- dp_snk_in -> kernel_src_out
+ -- dp_snk_in -> kernel_src_out
---------------------------------------------------------------------------------------
-- TX FIFO: dp_clk -> kernel_clk
---------------------------------------------------------------------------------------
u_dp_fifo_dc_tx : entity dp_lib.dp_fifo_dc
- generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_bsn_w,
- g_empty_w => c_empty_w,
- g_channel_w => c_channel_w,
- g_error_w => c_err_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => true,
- g_use_channel => g_use_channel,
- g_use_error => g_use_err,
- g_use_sync => g_use_sync,
- g_fifo_size => g_fifo_size
- )
- port map (
- wr_rst => dp_rst,
- wr_clk => dp_clk,
- rd_rst => kernel_reset,
- rd_clk => kernel_clk,
-
- snk_out => dp_snk_out_arr(stream),
- snk_in => dp_snk_in_arr(stream),
-
- src_in => dp_latency_adapter_tx_snk_out_arr(stream),
- src_out => dp_latency_adapter_tx_snk_in_arr(stream)
- );
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_bsn_w,
+ g_empty_w => c_empty_w,
+ g_channel_w => c_channel_w,
+ g_error_w => c_err_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => true,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_err,
+ g_use_sync => g_use_sync,
+ g_fifo_size => g_fifo_size
+ )
+ port map (
+ wr_rst => dp_rst,
+ wr_clk => dp_clk,
+ rd_rst => kernel_reset,
+ rd_clk => kernel_clk,
+
+ snk_out => dp_snk_out_arr(stream),
+ snk_in => dp_snk_in_arr(stream),
+
+ src_in => dp_latency_adapter_tx_snk_out_arr(stream),
+ src_out => dp_latency_adapter_tx_snk_in_arr(stream)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_latency_adapter_tx_snk_in_arr(stream),
- snk_out => dp_latency_adapter_tx_snk_out_arr(stream),
+ snk_in => dp_latency_adapter_tx_snk_in_arr(stream),
+ snk_out => dp_latency_adapter_tx_snk_out_arr(stream),
- src_out => dp_latency_adapter_tx_src_out_arr(stream),
- src_in => dp_latency_adapter_tx_src_in_arr(stream)
- );
+ src_out => dp_latency_adapter_tx_src_out_arr(stream),
+ src_in => dp_latency_adapter_tx_src_in_arr(stream)
+ );
----------------------------------------------------------------------------
-- Data mapping
@@ -190,7 +190,7 @@ begin
end generate;
gen_no_reverse_rx_bytes : if not g_reverse_bytes generate
- kernel_src_out_arr(stream).data(c_data_w - 1 downto 0) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_data_w - 1 downto 0);
+ kernel_src_out_arr(stream).data(c_data_w - 1 downto 0) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_data_w - 1 downto 0);
end generate;
-- Assign control signals to correct data fields.
@@ -255,49 +255,49 @@ begin
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 0,
- g_out_latency => 1
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_latency_adapter_rx_snk_in_arr(stream),
- snk_out => dp_latency_adapter_rx_snk_out_arr(stream),
+ snk_in => dp_latency_adapter_rx_snk_in_arr(stream),
+ snk_out => dp_latency_adapter_rx_snk_out_arr(stream),
- src_out => dp_latency_adapter_rx_src_out_arr(stream),
- src_in => dp_latency_adapter_rx_src_in_arr(stream)
- );
+ src_out => dp_latency_adapter_rx_src_out_arr(stream),
+ src_in => dp_latency_adapter_rx_src_in_arr(stream)
+ );
---------------------------------------------------------------------------------------
-- RX FIFO: kernel_clk -> dp_clk
---------------------------------------------------------------------------------------
u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
- generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_bsn_w,
- g_empty_w => c_empty_w,
- g_channel_w => c_channel_w,
- g_error_w => c_err_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => true,
- g_use_channel => g_use_channel,
- g_use_error => g_use_err,
- g_use_sync => g_use_sync,
- g_fifo_size => g_fifo_size
- )
- port map (
- wr_rst => kernel_reset,
- wr_clk => kernel_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
-
- snk_out => dp_latency_adapter_rx_src_in_arr(stream),
- snk_in => dp_latency_adapter_rx_src_out_arr(stream),
-
- src_in => dp_src_in_arr(stream),
- src_out => dp_src_out_arr(stream)
- );
- end generate;
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_bsn_w,
+ g_empty_w => c_empty_w,
+ g_channel_w => c_channel_w,
+ g_error_w => c_err_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => true,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_err,
+ g_use_sync => g_use_sync,
+ g_fifo_size => g_fifo_size
+ )
+ port map (
+ wr_rst => kernel_reset,
+ wr_clk => kernel_clk,
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+
+ snk_out => dp_latency_adapter_rx_src_in_arr(stream),
+ snk_in => dp_latency_adapter_rx_src_out_arr(stream),
+
+ src_in => dp_src_in_arr(stream),
+ src_out => dp_src_out_arr(stream)
+ );
+ end generate;
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
index be705c1148..d04bd12819 100644
--- a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
@@ -54,12 +54,12 @@
-- +-----------+---------+--------------------------------------------------------+
library IEEE, common_lib, dp_lib, tech_pll_lib, technology_lib, tech_eth_10g_lib, tech_mac_10g_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
entity ta2_unb2b_10GbE is
generic (
@@ -137,17 +137,17 @@ begin
--------
g_pll : if g_use_pll generate
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => c_tech_arria10_e1sg
- )
- port map (
- refclk_644 => clk_ref_r,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg
+ )
+ port map (
+ refclk_644 => clk_ref_r,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
end generate;
gen_no_pll : if not g_use_pll generate
@@ -161,32 +161,32 @@ begin
---------------------------------------------------------------------------------------
-- Apply the clocks from top level down such that they have their rising_edge() aligned without any delta-delay
u_tech_eth_10g_clocks : entity tech_eth_10g_lib.tech_eth_10g_clocks
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_nof_channels => g_nof_mac
- )
- port map (
- -- Input clocks
- -- . Reference
- tr_ref_clk_644 => clk_ref_r,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
-
- -- Output clocks
- -- . Reference
- eth_ref_clk_644 => eth_ref_clk_644,
- eth_ref_clk_312 => eth_ref_clk_312,
- eth_ref_clk_156 => eth_ref_clk_156,
- eth_ref_rst_156 => eth_ref_rst_156,
-
- -- . Data
- eth_tx_clk_arr => eth_tx_clk_arr,
- eth_tx_rst_arr => eth_tx_rst_arr,
-
- eth_rx_clk_arr => eth_rx_clk_arr,
- eth_rx_rst_arr => eth_rx_rst_arr
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_nof_channels => g_nof_mac
+ )
+ port map (
+ -- Input clocks
+ -- . Reference
+ tr_ref_clk_644 => clk_ref_r,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
+
+ -- Output clocks
+ -- . Reference
+ eth_ref_clk_644 => eth_ref_clk_644,
+ eth_ref_clk_312 => eth_ref_clk_312,
+ eth_ref_clk_156 => eth_ref_clk_156,
+ eth_ref_rst_156 => eth_ref_rst_156,
+
+ -- . Data
+ eth_tx_clk_arr => eth_tx_clk_arr,
+ eth_tx_rst_arr => eth_tx_rst_arr,
+
+ eth_rx_clk_arr => eth_rx_clk_arr,
+ eth_rx_rst_arr => eth_rx_rst_arr
+ );
gen_mac: for mac in 0 to g_nof_mac - 1 generate
----------------------------------------------------------------------------
@@ -213,104 +213,104 @@ begin
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 0,
- g_out_latency => 1
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_latency_adapter_tx_snk_in_arr(mac),
- snk_out => dp_latency_adapter_tx_snk_out_arr(mac),
+ snk_in => dp_latency_adapter_tx_snk_in_arr(mac),
+ snk_out => dp_latency_adapter_tx_snk_out_arr(mac),
- src_out => dp_latency_adapter_tx_src_out_arr(mac),
- src_in => dp_latency_adapter_tx_src_in_arr(mac)
- );
+ src_out => dp_latency_adapter_tx_src_out_arr(mac),
+ src_in => dp_latency_adapter_tx_src_in_arr(mac)
+ );
-----------------------------------------------------------------------------
-- RX XON frame control
-----------------------------------------------------------------------------
u_dp_xonoff : entity dp_lib.dp_xonoff
- port map (
- rst => kernel_reset,
- clk => kernel_clk,
+ port map (
+ rst => kernel_reset,
+ clk => kernel_clk,
- in_siso => dp_latency_adapter_tx_src_in_arr(mac),
- in_sosi => dp_latency_adapter_tx_src_out_arr(mac),
+ in_siso => dp_latency_adapter_tx_src_in_arr(mac),
+ in_sosi => dp_latency_adapter_tx_src_out_arr(mac),
- out_siso => dp_xonoff_src_in_arr(mac),
- out_sosi => dp_xonoff_src_out_arr(mac)
- );
+ out_siso => dp_xonoff_src_in_arr(mac),
+ out_sosi => dp_xonoff_src_out_arr(mac)
+ );
---------------------------------------------------------------------------------------
-- FIFO FILL with fill level/eop trigger so we can deliver packets to the MAC fast enough
---------------------------------------------------------------------------------------
u_dp_fifo_fill_tx_eop : entity dp_lib.dp_fifo_fill_eop
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_use_dual_clock => true,
- g_data_w => c_xgmii_data_w,
- g_empty_w => c_tech_mac_10g_empty_w,
- g_use_empty => true,
- g_fifo_fill => c_tx_fifo_fill,
- g_fifo_size => c_tx_fifo_size
- )
- port map (
- wr_rst => kernel_reset,
- wr_clk => kernel_clk,
- rd_rst => eth_tx_rst_arr(mac),
- rd_clk => eth_tx_clk_arr(mac),
-
- snk_out => dp_xonoff_src_in_arr(mac),
- snk_in => dp_xonoff_src_out_arr(mac),
-
- src_in => dp_fifo_fill_tx_src_in_arr(mac),
- src_out => dp_fifo_fill_tx_src_out_arr(mac)
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_use_dual_clock => true,
+ g_data_w => c_xgmii_data_w,
+ g_empty_w => c_tech_mac_10g_empty_w,
+ g_use_empty => true,
+ g_fifo_fill => c_tx_fifo_fill,
+ g_fifo_size => c_tx_fifo_size
+ )
+ port map (
+ wr_rst => kernel_reset,
+ wr_clk => kernel_clk,
+ rd_rst => eth_tx_rst_arr(mac),
+ rd_clk => eth_tx_clk_arr(mac),
+
+ snk_out => dp_xonoff_src_in_arr(mac),
+ snk_in => dp_xonoff_src_out_arr(mac),
+
+ src_in => dp_fifo_fill_tx_src_in_arr(mac),
+ src_out => dp_fifo_fill_tx_src_out_arr(mac)
+ );
---------------------------------------------------------------------------------------
-- RX FIFO: rx_clk -> dp_clk
---------------------------------------------------------------------------------------
u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_data_w => c_xgmii_data_w,
- g_empty_w => c_tech_mac_10g_empty_w,
- g_use_empty => true,
- g_fifo_size => c_rx_fifo_size
- )
- port map (
- wr_rst => eth_rx_rst_arr(mac),
- wr_clk => eth_rx_clk_arr(mac),
- rd_rst => kernel_reset,
- rd_clk => kernel_clk,
-
- snk_out => mac_10g_src_in_arr(mac),
- snk_in => mac_10g_src_out_arr(mac),
-
- src_in => dp_fifo_dc_rx_src_in_arr(mac),
- src_out => dp_fifo_dc_rx_src_out_arr(mac)
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_data_w => c_xgmii_data_w,
+ g_empty_w => c_tech_mac_10g_empty_w,
+ g_use_empty => true,
+ g_fifo_size => c_rx_fifo_size
+ )
+ port map (
+ wr_rst => eth_rx_rst_arr(mac),
+ wr_clk => eth_rx_clk_arr(mac),
+ rd_rst => kernel_reset,
+ rd_clk => kernel_clk,
+
+ snk_out => mac_10g_src_in_arr(mac),
+ snk_in => mac_10g_src_out_arr(mac),
+
+ src_in => dp_fifo_dc_rx_src_in_arr(mac),
+ src_out => dp_fifo_dc_rx_src_out_arr(mac)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_fifo_dc_rx_src_out_arr(mac),
- snk_out => dp_fifo_dc_rx_src_in_arr(mac),
+ snk_in => dp_fifo_dc_rx_src_out_arr(mac),
+ snk_out => dp_fifo_dc_rx_src_in_arr(mac),
- src_out => dp_latency_adapter_rx_src_out_arr(mac),
- src_in => dp_latency_adapter_rx_src_in_arr(mac)
- );
+ src_out => dp_latency_adapter_rx_src_out_arr(mac),
+ src_in => dp_latency_adapter_rx_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- Data mapping
@@ -331,41 +331,41 @@ begin
src_out_arr(mac).valid <= dp_latency_adapter_rx_src_out_arr(mac).valid;
dp_latency_adapter_rx_src_in_arr(mac).ready <= src_in_arr(mac).ready;
dp_latency_adapter_rx_src_in_arr(mac).xon <= '1';
- end generate;
+ end generate;
---------------------------------------------------------------------------------------
-- ETH MAC + PHY
---------------------------------------------------------------------------------------
u_tech_eth_10g : entity tech_eth_10g_lib.tech_eth_10g
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_sim => c_sim,
- g_sim_level => 1, -- 0 = use IP; 1 = use fast serdes model
- g_nof_channels => g_nof_mac,
- g_direction => "TX_RX",
- g_pre_header_padding => false
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => eth_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
- tr_ref_clk_312 => eth_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => eth_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => eth_ref_rst_156, -- for 10GBASE-R or for XAUI
-
- -- MM
- mm_clk => '0',
- mm_rst => '0',
-
- -- ST
- tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr, -- 64 bit data @ 156 MHz
- tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr,
-
- rx_src_out_arr => mac_10g_src_out_arr, -- 64 bit data @ 156 MHz
- rx_src_in_arr => mac_10g_src_in_arr,
-
- -- PHY serial IO
- -- . 10GBASE-R (single lane)
- serial_tx_arr => tx_serial_r,
- serial_rx_arr => rx_serial_r
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_sim => c_sim,
+ g_sim_level => 1, -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels => g_nof_mac,
+ g_direction => "TX_RX",
+ g_pre_header_padding => false
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => eth_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_312 => eth_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => eth_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => eth_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM
+ mm_clk => '0',
+ mm_rst => '0',
+
+ -- ST
+ tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr, -- 64 bit data @ 156 MHz
+ tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr,
+
+ rx_src_out_arr => mac_10g_src_out_arr, -- 64 bit data @ 156 MHz
+ rx_src_in_arr => mac_10g_src_in_arr,
+
+ -- PHY serial IO
+ -- . 10GBASE-R (single lane)
+ serial_tx_arr => tx_serial_r,
+ serial_rx_arr => rx_serial_r
+ );
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
index cd1da96996..2c70b0b5d0 100644
--- a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
@@ -44,11 +44,11 @@
-- | [38:39] | empty | On EOP, this field indicates how many bytes are unused |
-- +-----------+---------+--------------------------------------------------------+
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
entity ta2_unb2b_1GbE is
port (
@@ -92,8 +92,8 @@ architecture str of ta2_unb2b_1GbE is
signal dp_xonoff_src_out : t_dp_sosi;
signal dp_xonoff_src_in : t_dp_siso;
begin
--------------------------------------------------------
- -- Mapping Data from OpenCL kernel to 1GbE Interface --
+ -------------------------------------------------------
+ -- Mapping Data from OpenCL kernel to 1GbE Interface --
-------------------------------------------------------
----------------------------------------------------------------------------
@@ -116,42 +116,42 @@ begin
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 0,
- g_out_latency => 1
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_latency_adapter_tx_snk_in,
- snk_out => dp_latency_adapter_tx_snk_out,
-
- src_out => dp_latency_adapter_tx_src_out,
- src_in => dp_latency_adapter_tx_src_in
- );
+ generic map (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
+
+ snk_in => dp_latency_adapter_tx_snk_in,
+ snk_out => dp_latency_adapter_tx_snk_out,
+
+ src_out => dp_latency_adapter_tx_src_out,
+ src_in => dp_latency_adapter_tx_src_in
+ );
-----------------------------------------------------------------------------
-- TX XON frame control
-----------------------------------------------------------------------------
u_dp_xonoff : entity dp_lib.dp_xonoff
- port map (
- rst => kernel_reset,
- clk => kernel_clk,
+ port map (
+ rst => kernel_reset,
+ clk => kernel_clk,
- in_siso => dp_latency_adapter_tx_src_in,
- in_sosi => dp_latency_adapter_tx_src_out,
+ in_siso => dp_latency_adapter_tx_src_in,
+ in_sosi => dp_latency_adapter_tx_src_out,
- out_siso => dp_xonoff_src_in,
- out_sosi => dp_xonoff_src_out
- );
+ out_siso => dp_xonoff_src_in,
+ out_sosi => dp_xonoff_src_out
+ );
-----------------------------------------------------------------------------
-- TX dual clock FIFO
-----------------------------------------------------------------------------
- u_dp_fifo_dc_tx : entity dp_lib.dp_fifo_dc
+ u_dp_fifo_dc_tx : entity dp_lib.dp_fifo_dc
generic map (
g_technology => c_tech_arria10_e1sg,
g_data_w => c_word_w,
@@ -172,14 +172,14 @@ begin
src_out => udp_tx_sosi
);
--------------------------------------------------------
- -- Mapping Data from 1GbE Interface to OpenCL kernel --
+ -------------------------------------------------------
+ -- Mapping Data from 1GbE Interface to OpenCL kernel --
-------------------------------------------------------
-----------------------------------------------------------------------------
-- TX dual clock FIFO
-----------------------------------------------------------------------------
- u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
+ u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
generic map (
g_technology => c_tech_arria10_e1sg,
g_data_w => c_word_w,
@@ -204,20 +204,20 @@ begin
-- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_fifo_dc_rx_src_out,
- snk_out => dp_fifo_dc_rx_src_in,
-
- src_out => dp_latency_adapter_rx_src_out,
- src_in => dp_latency_adapter_rx_src_in
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
+
+ snk_in => dp_fifo_dc_rx_src_out,
+ snk_out => dp_fifo_dc_rx_src_in,
+
+ src_out => dp_latency_adapter_rx_src_out,
+ src_in => dp_latency_adapter_rx_src_in
+ );
----------------------------------------------------------------------------
-- Data mapping
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
index 1083a6bc15..a312fdb2f6 100644
--- a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
@@ -24,7 +24,7 @@
-- Purpose:
-- . Instantiates ta2_unb2b_1GbE component
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity ta2_unb2b_1GbE_ip_wrapper is
port (
@@ -66,68 +66,68 @@ architecture str of ta2_unb2b_1GbE_ip_wrapper is
-- ta2_unb2b_1GbE Component
----------------------------------------------------------------------------
component ta2_unb2b_1GbE is
- port (
- st_clk : in std_logic;
- st_rst : in std_logic;
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_data : out std_logic_vector(39 downto 0);
- udp_tx_sosi_valid : out std_logic;
- udp_tx_sosi_sop : out std_logic;
- udp_tx_sosi_eop : out std_logic;
- udp_tx_sosi_empty : out std_logic_vector(1 downto 0);
- udp_tx_siso_ready : in std_logic;
- udp_tx_siso_xon : in std_logic;
-
- udp_rx_sosi_data : in std_logic_vector(39 downto 0);
- udp_rx_sosi_valid : in std_logic;
- udp_rx_sosi_sop : in std_logic;
- udp_rx_sosi_eop : in std_logic;
- udp_rx_sosi_empty : in std_logic_vector(1 downto 0);
- udp_rx_siso_ready : out std_logic;
- udp_rx_siso_xon : out std_logic;
-
- kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
- kernel_reset : in std_logic;
-
- kernel_src_data : out std_logic_vector(39 downto 0); -- RX Data to kernel
- kernel_src_valid : out std_logic; -- RX data valid signal to kernel
- kernel_src_ready : in std_logic; -- Flow control from kernel
-
- kernel_snk_data : in std_logic_vector(39 downto 0); -- TX Data from kernel
- kernel_snk_valid : in std_logic; -- TX data valid signal from kernel
- kernel_snk_ready : out std_logic -- Flow control towards kernel
- );
+ port (
+ st_clk : in std_logic;
+ st_rst : in std_logic;
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_data : out std_logic_vector(39 downto 0);
+ udp_tx_sosi_valid : out std_logic;
+ udp_tx_sosi_sop : out std_logic;
+ udp_tx_sosi_eop : out std_logic;
+ udp_tx_sosi_empty : out std_logic_vector(1 downto 0);
+ udp_tx_siso_ready : in std_logic;
+ udp_tx_siso_xon : in std_logic;
+
+ udp_rx_sosi_data : in std_logic_vector(39 downto 0);
+ udp_rx_sosi_valid : in std_logic;
+ udp_rx_sosi_sop : in std_logic;
+ udp_rx_sosi_eop : in std_logic;
+ udp_rx_sosi_empty : in std_logic_vector(1 downto 0);
+ udp_rx_siso_ready : out std_logic;
+ udp_rx_siso_xon : out std_logic;
+
+ kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
+ kernel_reset : in std_logic;
+
+ kernel_src_data : out std_logic_vector(39 downto 0); -- RX Data to kernel
+ kernel_src_valid : out std_logic; -- RX data valid signal to kernel
+ kernel_src_ready : in std_logic; -- Flow control from kernel
+
+ kernel_snk_data : in std_logic_vector(39 downto 0); -- TX Data from kernel
+ kernel_snk_valid : in std_logic; -- TX data valid signal from kernel
+ kernel_snk_ready : out std_logic -- Flow control towards kernel
+ );
end component ta2_unb2b_1GbE;
begin
u_ta2_unb2b_1GbE : ta2_unb2b_1GbE
- port map (
- st_clk => st_clk,
- st_rst => st_rst,
-
- udp_tx_sosi_data => udp_tx_sosi_data,
- udp_tx_sosi_valid => udp_tx_sosi_valid,
- udp_tx_sosi_sop => udp_tx_sosi_sop,
- udp_tx_sosi_eop => udp_tx_sosi_eop,
- udp_tx_sosi_empty => udp_tx_sosi_empty,
- udp_tx_siso_ready => udp_tx_siso_ready,
- udp_tx_siso_xon => udp_tx_siso_xon,
-
- udp_rx_sosi_data => udp_rx_sosi_data,
- udp_rx_sosi_valid => udp_rx_sosi_valid,
- udp_rx_sosi_sop => udp_rx_sosi_sop,
- udp_rx_sosi_eop => udp_rx_sosi_eop,
- udp_rx_sosi_empty => udp_rx_sosi_empty,
- udp_rx_siso_ready => udp_rx_siso_ready,
- udp_rx_siso_xon => udp_rx_siso_xon,
-
- kernel_clk => kernel_clk,
- kernel_reset => kernel_reset,
- kernel_src_data => kernel_src_data ,
- kernel_src_valid => kernel_src_valid,
- kernel_src_ready => kernel_src_ready,
- kernel_snk_data => kernel_snk_data,
- kernel_snk_valid => kernel_snk_valid,
- kernel_snk_ready => kernel_snk_ready
- );
+ port map (
+ st_clk => st_clk,
+ st_rst => st_rst,
+
+ udp_tx_sosi_data => udp_tx_sosi_data,
+ udp_tx_sosi_valid => udp_tx_sosi_valid,
+ udp_tx_sosi_sop => udp_tx_sosi_sop,
+ udp_tx_sosi_eop => udp_tx_sosi_eop,
+ udp_tx_sosi_empty => udp_tx_sosi_empty,
+ udp_tx_siso_ready => udp_tx_siso_ready,
+ udp_tx_siso_xon => udp_tx_siso_xon,
+
+ udp_rx_sosi_data => udp_rx_sosi_data,
+ udp_rx_sosi_valid => udp_rx_sosi_valid,
+ udp_rx_sosi_sop => udp_rx_sosi_sop,
+ udp_rx_sosi_eop => udp_rx_sosi_eop,
+ udp_rx_sosi_empty => udp_rx_sosi_empty,
+ udp_rx_siso_ready => udp_rx_siso_ready,
+ udp_rx_siso_xon => udp_rx_siso_xon,
+
+ kernel_clk => kernel_clk,
+ kernel_reset => kernel_reset,
+ kernel_src_data => kernel_src_data ,
+ kernel_src_valid => kernel_src_valid,
+ kernel_src_ready => kernel_src_ready,
+ kernel_snk_data => kernel_snk_data,
+ kernel_snk_valid => kernel_snk_valid,
+ kernel_snk_ready => kernel_snk_ready
+ );
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
index 44b951b237..fdeaf6d4df 100644
--- a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
@@ -51,9 +51,9 @@
-- | 259:263 | empty | On EOP, this field indicates how many bytes are unused |
-- +-----------+---------+--------------------------------------------------------+
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity ta2_unb2b_40GbE is
generic (
@@ -152,118 +152,118 @@ architecture str of ta2_unb2b_40GbE is
-- ATX PLL Component
----------------------------------------------------------------------------
component arria10_40g_atx_pll is
- port (
- pll_cal_busy : out std_logic; -- pll_cal_busy
- pll_locked : out std_logic; -- pll_locked
- pll_powerdown : in std_logic := 'X'; -- pll_powerdown
- pll_refclk0 : in std_logic := 'X'; -- clk
- tx_serial_clk : out std_logic -- clk
- );
+ port (
+ pll_cal_busy : out std_logic; -- pll_cal_busy
+ pll_locked : out std_logic; -- pll_locked
+ pll_powerdown : in std_logic := 'X'; -- pll_powerdown
+ pll_refclk0 : in std_logic := 'X'; -- clk
+ tx_serial_clk : out std_logic -- clk
+ );
end component arria10_40g_atx_pll;
----------------------------------------------------------------------------
-- 40G ETH IP Component
----------------------------------------------------------------------------
component arria10_40g_mac is
- port (
- l4_rx_error : out std_logic_vector(5 downto 0); -- l4_rx_error
- l4_rx_status : out std_logic_vector(2 downto 0); -- l4_rx_status
- l4_rx_valid : out std_logic; -- l4_rx_valid
- l4_rx_startofpacket : out std_logic; -- l4_rx_startofpacket
- l4_rx_endofpacket : out std_logic; -- l4_rx_endofpacket
- l4_rx_data : out std_logic_vector(255 downto 0); -- l4_rx_data
- l4_rx_empty : out std_logic_vector(4 downto 0); -- l4_rx_empty
- l4_rx_fcs_error : out std_logic; -- l4_rx_fcs_error
- l4_rx_fcs_valid : out std_logic; -- l4_rx_fcs_valid
- l4_tx_startofpacket : in std_logic := 'X'; -- l4_tx_startofpacket
- l4_tx_endofpacket : in std_logic := 'X'; -- l4_tx_endofpacket
- l4_tx_valid : in std_logic := 'X'; -- l4_tx_valid
- l4_tx_ready : out std_logic; -- l4_tx_ready
- l4_tx_empty : in std_logic_vector(4 downto 0) := (others => 'X'); -- l4_tx_empty
- l4_tx_data : in std_logic_vector(255 downto 0) := (others => 'X'); -- l4_tx_data
- l4_tx_error : in std_logic := 'X'; -- l4_tx_error
- clk_ref : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk_ref
- clk_rxmac : out std_logic_vector(0 downto 0); -- clk_rxmac
- clk_status : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk_status
- clk_txmac : out std_logic_vector(0 downto 0); -- clk_txmac
- reconfig_address : in std_logic_vector(11 downto 0) := (others => 'X'); -- reconfig_address
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_clk
- reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_read
- reconfig_readdata : out std_logic_vector(31 downto 0); -- reconfig_readdata
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_reset
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- reconfig_waitrequest
- reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_write
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- reconfig_writedata
- reset_async : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset_async
- reset_status : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset_status
- rx_pcs_ready : out std_logic_vector(0 downto 0); -- rx_pcs_ready
- rx_serial : in std_logic_vector(3 downto 0) := (others => 'X'); -- rx_serial
- rx_inc_octetsOK : out std_logic_vector(15 downto 0); -- rx_inc_octetsOK
- rx_inc_octetsOK_valid : out std_logic_vector(0 downto 0); -- rx_inc_octetsOK_valid
- rx_inc_runt : out std_logic_vector(0 downto 0); -- rx_inc_runt
- rx_inc_64 : out std_logic_vector(0 downto 0); -- rx_inc_64
- rx_inc_127 : out std_logic_vector(0 downto 0); -- rx_inc_127
- rx_inc_255 : out std_logic_vector(0 downto 0); -- rx_inc_255
- rx_inc_511 : out std_logic_vector(0 downto 0); -- rx_inc_511
- rx_inc_1023 : out std_logic_vector(0 downto 0); -- rx_inc_1023
- rx_inc_1518 : out std_logic_vector(0 downto 0); -- rx_inc_1518
- rx_inc_max : out std_logic_vector(0 downto 0); -- rx_inc_max
- rx_inc_over : out std_logic_vector(0 downto 0); -- rx_inc_over
- rx_inc_mcast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_mcast_data_err
- rx_inc_mcast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_mcast_data_ok
- rx_inc_bcast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_bcast_data_err
- rx_inc_bcast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_bcast_data_ok
- rx_inc_ucast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_ucast_data_err
- rx_inc_ucast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_ucast_data_ok
- rx_inc_mcast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_mcast_ctrl
- rx_inc_bcast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_bcast_ctrl
- rx_inc_ucast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_ucast_ctrl
- rx_inc_pause : out std_logic_vector(0 downto 0); -- rx_inc_pause
- rx_inc_fcs_err : out std_logic_vector(0 downto 0); -- rx_inc_fcs_err
- rx_inc_fragment : out std_logic_vector(0 downto 0); -- rx_inc_fragment
- rx_inc_jabber : out std_logic_vector(0 downto 0); -- rx_inc_jabber
- rx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0); -- rx_inc_sizeok_fcserr
- rx_inc_pause_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_pause_ctrl_err
- rx_inc_mcast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_mcast_ctrl_err
- rx_inc_bcast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_bcast_ctrl_err
- rx_inc_ucast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_ucast_ctrl_err
- status_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- status_write
- status_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- status_read
- status_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- status_addr
- status_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- status_writedata
- status_readdata : out std_logic_vector(31 downto 0); -- status_readdata
- status_readdata_valid : out std_logic_vector(0 downto 0); -- status_readdata_valid
- status_waitrequest : out std_logic_vector(0 downto 0); -- status_waitrequest
- status_read_timeout : out std_logic_vector(0 downto 0); -- status_read_timeout
- tx_lanes_stable : out std_logic_vector(0 downto 0); -- tx_lanes_stable
- tx_pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_pll_locked
- tx_serial : out std_logic_vector(3 downto 0); -- tx_serial
- tx_serial_clk : in std_logic_vector(3 downto 0) := (others => 'X'); -- tx_serial_clk
- tx_inc_octetsOK : out std_logic_vector(15 downto 0); -- tx_inc_octetsOK
- tx_inc_octetsOK_valid : out std_logic_vector(0 downto 0); -- tx_inc_octetsOK_valid
- tx_inc_64 : out std_logic_vector(0 downto 0); -- tx_inc_64
- tx_inc_127 : out std_logic_vector(0 downto 0); -- tx_inc_127
- tx_inc_255 : out std_logic_vector(0 downto 0); -- tx_inc_255
- tx_inc_511 : out std_logic_vector(0 downto 0); -- tx_inc_511
- tx_inc_1023 : out std_logic_vector(0 downto 0); -- tx_inc_1023
- tx_inc_1518 : out std_logic_vector(0 downto 0); -- tx_inc_1518
- tx_inc_max : out std_logic_vector(0 downto 0); -- tx_inc_max
- tx_inc_over : out std_logic_vector(0 downto 0); -- tx_inc_over
- tx_inc_mcast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_mcast_data_err
- tx_inc_mcast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_mcast_data_ok
- tx_inc_bcast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_bcast_data_err
- tx_inc_bcast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_bcast_data_ok
- tx_inc_ucast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_ucast_data_err
- tx_inc_ucast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_ucast_data_ok
- tx_inc_mcast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_mcast_ctrl
- tx_inc_bcast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_bcast_ctrl
- tx_inc_ucast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_ucast_ctrl
- tx_inc_pause : out std_logic_vector(0 downto 0); -- tx_inc_pause
- tx_inc_fcs_err : out std_logic_vector(0 downto 0); -- tx_inc_fcs_err
- tx_inc_fragment : out std_logic_vector(0 downto 0); -- tx_inc_fragment
- tx_inc_jabber : out std_logic_vector(0 downto 0); -- tx_inc_jabber
- tx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0) -- tx_inc_sizeok_fcserr
- );
+ port (
+ l4_rx_error : out std_logic_vector(5 downto 0); -- l4_rx_error
+ l4_rx_status : out std_logic_vector(2 downto 0); -- l4_rx_status
+ l4_rx_valid : out std_logic; -- l4_rx_valid
+ l4_rx_startofpacket : out std_logic; -- l4_rx_startofpacket
+ l4_rx_endofpacket : out std_logic; -- l4_rx_endofpacket
+ l4_rx_data : out std_logic_vector(255 downto 0); -- l4_rx_data
+ l4_rx_empty : out std_logic_vector(4 downto 0); -- l4_rx_empty
+ l4_rx_fcs_error : out std_logic; -- l4_rx_fcs_error
+ l4_rx_fcs_valid : out std_logic; -- l4_rx_fcs_valid
+ l4_tx_startofpacket : in std_logic := 'X'; -- l4_tx_startofpacket
+ l4_tx_endofpacket : in std_logic := 'X'; -- l4_tx_endofpacket
+ l4_tx_valid : in std_logic := 'X'; -- l4_tx_valid
+ l4_tx_ready : out std_logic; -- l4_tx_ready
+ l4_tx_empty : in std_logic_vector(4 downto 0) := (others => 'X'); -- l4_tx_empty
+ l4_tx_data : in std_logic_vector(255 downto 0) := (others => 'X'); -- l4_tx_data
+ l4_tx_error : in std_logic := 'X'; -- l4_tx_error
+ clk_ref : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk_ref
+ clk_rxmac : out std_logic_vector(0 downto 0); -- clk_rxmac
+ clk_status : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk_status
+ clk_txmac : out std_logic_vector(0 downto 0); -- clk_txmac
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => 'X'); -- reconfig_address
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_clk
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_read
+ reconfig_readdata : out std_logic_vector(31 downto 0); -- reconfig_readdata
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_reset
+ reconfig_waitrequest : out std_logic_vector(0 downto 0); -- reconfig_waitrequest
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_write
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- reconfig_writedata
+ reset_async : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset_async
+ reset_status : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset_status
+ rx_pcs_ready : out std_logic_vector(0 downto 0); -- rx_pcs_ready
+ rx_serial : in std_logic_vector(3 downto 0) := (others => 'X'); -- rx_serial
+ rx_inc_octetsOK : out std_logic_vector(15 downto 0); -- rx_inc_octetsOK
+ rx_inc_octetsOK_valid : out std_logic_vector(0 downto 0); -- rx_inc_octetsOK_valid
+ rx_inc_runt : out std_logic_vector(0 downto 0); -- rx_inc_runt
+ rx_inc_64 : out std_logic_vector(0 downto 0); -- rx_inc_64
+ rx_inc_127 : out std_logic_vector(0 downto 0); -- rx_inc_127
+ rx_inc_255 : out std_logic_vector(0 downto 0); -- rx_inc_255
+ rx_inc_511 : out std_logic_vector(0 downto 0); -- rx_inc_511
+ rx_inc_1023 : out std_logic_vector(0 downto 0); -- rx_inc_1023
+ rx_inc_1518 : out std_logic_vector(0 downto 0); -- rx_inc_1518
+ rx_inc_max : out std_logic_vector(0 downto 0); -- rx_inc_max
+ rx_inc_over : out std_logic_vector(0 downto 0); -- rx_inc_over
+ rx_inc_mcast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_mcast_data_err
+ rx_inc_mcast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_mcast_data_ok
+ rx_inc_bcast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_bcast_data_err
+ rx_inc_bcast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_bcast_data_ok
+ rx_inc_ucast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_ucast_data_err
+ rx_inc_ucast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_ucast_data_ok
+ rx_inc_mcast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_mcast_ctrl
+ rx_inc_bcast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_bcast_ctrl
+ rx_inc_ucast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_ucast_ctrl
+ rx_inc_pause : out std_logic_vector(0 downto 0); -- rx_inc_pause
+ rx_inc_fcs_err : out std_logic_vector(0 downto 0); -- rx_inc_fcs_err
+ rx_inc_fragment : out std_logic_vector(0 downto 0); -- rx_inc_fragment
+ rx_inc_jabber : out std_logic_vector(0 downto 0); -- rx_inc_jabber
+ rx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0); -- rx_inc_sizeok_fcserr
+ rx_inc_pause_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_pause_ctrl_err
+ rx_inc_mcast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_mcast_ctrl_err
+ rx_inc_bcast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_bcast_ctrl_err
+ rx_inc_ucast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_ucast_ctrl_err
+ status_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- status_write
+ status_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- status_read
+ status_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- status_addr
+ status_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- status_writedata
+ status_readdata : out std_logic_vector(31 downto 0); -- status_readdata
+ status_readdata_valid : out std_logic_vector(0 downto 0); -- status_readdata_valid
+ status_waitrequest : out std_logic_vector(0 downto 0); -- status_waitrequest
+ status_read_timeout : out std_logic_vector(0 downto 0); -- status_read_timeout
+ tx_lanes_stable : out std_logic_vector(0 downto 0); -- tx_lanes_stable
+ tx_pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_pll_locked
+ tx_serial : out std_logic_vector(3 downto 0); -- tx_serial
+ tx_serial_clk : in std_logic_vector(3 downto 0) := (others => 'X'); -- tx_serial_clk
+ tx_inc_octetsOK : out std_logic_vector(15 downto 0); -- tx_inc_octetsOK
+ tx_inc_octetsOK_valid : out std_logic_vector(0 downto 0); -- tx_inc_octetsOK_valid
+ tx_inc_64 : out std_logic_vector(0 downto 0); -- tx_inc_64
+ tx_inc_127 : out std_logic_vector(0 downto 0); -- tx_inc_127
+ tx_inc_255 : out std_logic_vector(0 downto 0); -- tx_inc_255
+ tx_inc_511 : out std_logic_vector(0 downto 0); -- tx_inc_511
+ tx_inc_1023 : out std_logic_vector(0 downto 0); -- tx_inc_1023
+ tx_inc_1518 : out std_logic_vector(0 downto 0); -- tx_inc_1518
+ tx_inc_max : out std_logic_vector(0 downto 0); -- tx_inc_max
+ tx_inc_over : out std_logic_vector(0 downto 0); -- tx_inc_over
+ tx_inc_mcast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_mcast_data_err
+ tx_inc_mcast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_mcast_data_ok
+ tx_inc_bcast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_bcast_data_err
+ tx_inc_bcast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_bcast_data_ok
+ tx_inc_ucast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_ucast_data_err
+ tx_inc_ucast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_ucast_data_ok
+ tx_inc_mcast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_mcast_ctrl
+ tx_inc_bcast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_bcast_ctrl
+ tx_inc_ucast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_ucast_ctrl
+ tx_inc_pause : out std_logic_vector(0 downto 0); -- tx_inc_pause
+ tx_inc_fcs_err : out std_logic_vector(0 downto 0); -- tx_inc_fcs_err
+ tx_inc_fragment : out std_logic_vector(0 downto 0); -- tx_inc_fragment
+ tx_inc_jabber : out std_logic_vector(0 downto 0); -- tx_inc_jabber
+ tx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0) -- tx_inc_sizeok_fcserr
+ );
end component arria10_40g_mac;
begin
gen_mac: for mac in 0 to g_nof_mac - 1 generate
@@ -287,84 +287,84 @@ begin
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (downstream).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx_a : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 0,
- g_out_latency => 1
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_latency_adapter_tx_a_snk_in_arr(mac),
- snk_out => dp_latency_adapter_tx_a_snk_out_arr(mac),
+ snk_in => dp_latency_adapter_tx_a_snk_in_arr(mac),
+ snk_out => dp_latency_adapter_tx_a_snk_out_arr(mac),
- src_out => dp_latency_adapter_tx_a_src_out_arr(mac),
- src_in => dp_latency_adapter_tx_a_src_in_arr(mac)
- );
+ src_out => dp_latency_adapter_tx_a_src_out_arr(mac),
+ src_in => dp_latency_adapter_tx_a_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- dp_xonoff: discard all TX frames until 40G MAC TX side is ready
----------------------------------------------------------------------------
u_dp_xonoff : entity dp_lib.dp_xonoff
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- in_sosi => dp_latency_adapter_tx_a_src_out_arr(mac),
- in_siso => dp_latency_adapter_tx_a_src_in_arr(mac),
+ in_sosi => dp_latency_adapter_tx_a_src_out_arr(mac),
+ in_siso => dp_latency_adapter_tx_a_src_in_arr(mac),
- out_sosi => dp_xonoff_src_out_arr(mac),
- out_siso => dp_xonoff_src_in_arr(mac) -- flush control via out_siso.xon
- );
+ out_sosi => dp_xonoff_src_out_arr(mac),
+ out_siso => dp_xonoff_src_in_arr(mac) -- flush control via out_siso.xon
+ );
----------------------------------------------------------------------------
-- TX FIFO
----------------------------------------------------------------------------
u_dp_fifo_fill_eop : entity dp_lib.dp_fifo_fill_eop
- generic map (
- g_data_w => c_data_w,
- g_use_dual_clock => true,
- g_empty_w => 8,
- g_use_empty => true,
- g_use_bsn => false,
- g_bsn_w => 64,
- g_use_channel => false,
- g_use_sync => false,
- g_fifo_size => c_tx_fifo_size,
- g_fifo_fill => c_tx_fifo_fill
- )
- port map (
- wr_clk => kernel_clk,
- wr_rst => kernel_reset,
+ generic map (
+ g_data_w => c_data_w,
+ g_use_dual_clock => true,
+ g_empty_w => 8,
+ g_use_empty => true,
+ g_use_bsn => false,
+ g_bsn_w => 64,
+ g_use_channel => false,
+ g_use_sync => false,
+ g_fifo_size => c_tx_fifo_size,
+ g_fifo_fill => c_tx_fifo_fill
+ )
+ port map (
+ wr_clk => kernel_clk,
+ wr_rst => kernel_reset,
- rd_clk => clk_txmac_arr(mac),
- rd_rst => rst_txmac_arr(mac),
+ rd_clk => clk_txmac_arr(mac),
+ rd_rst => rst_txmac_arr(mac),
- snk_in => dp_xonoff_src_out_arr(mac),
- snk_out => dp_xonoff_src_in_arr(mac),
+ snk_in => dp_xonoff_src_out_arr(mac),
+ snk_out => dp_xonoff_src_in_arr(mac),
- src_out => dp_fifo_fill_eop_src_out_arr(mac),
- src_in => dp_fifo_fill_eop_src_in_arr(mac)
- );
+ src_out => dp_fifo_fill_eop_src_out_arr(mac),
+ src_in => dp_fifo_fill_eop_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (upstream) to RL=0 (MAC TX interface).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx_b : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => clk_txmac_arr(mac),
- rst => rst_txmac_arr(mac),
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => clk_txmac_arr(mac),
+ rst => rst_txmac_arr(mac),
- snk_in => dp_fifo_fill_eop_src_out_arr(mac),
- snk_out => dp_fifo_fill_eop_src_in_arr(mac),
+ snk_in => dp_fifo_fill_eop_src_out_arr(mac),
+ snk_out => dp_fifo_fill_eop_src_in_arr(mac),
- src_out => dp_latency_adapter_tx_b_src_out_arr(mac),
- src_in => dp_latency_adapter_tx_b_src_in_arr(mac)
- );
+ src_out => dp_latency_adapter_tx_b_src_out_arr(mac),
+ src_in => dp_latency_adapter_tx_b_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- 40G MAC IP
@@ -373,112 +373,112 @@ begin
dp_latency_adapter_tx_b_src_in_arr(mac) <= l4_tx_siso_arr(mac);
u_arria10_40g_mac : arria10_40g_mac
- port map (
- reset_async(0) => mm_rst,
- clk_txmac(0) => clk_txmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
- clk_rxmac(0) => clk_rxmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
- clk_ref(0) => clk_ref_r,
- rx_pcs_ready(0) => rx_pcs_ready_arr(mac),
-
- tx_serial_clk => serial_clk_2arr(mac),
- tx_pll_locked(0) => pll_locked_arr(mac),
-
- clk_status(0) => mm_clk,
- reset_status(0) => mm_rst,
- status_addr => (others => '0'),
- status_read => (others => '0'),
- status_write => (others => '0'),
- status_writedata => (others => '0'),
--- status_readdata => status_readdata_eth,
--- status_read_timeout => status_read_timeout,
--- status_readdata_valid => status_readdata_valid_eth,
-
- reconfig_clk(0) => mm_clk,
- reconfig_reset(0) => mm_rst,
- reconfig_write => (others => '0'),
- reconfig_read => (others => '0'),
- reconfig_address => (others => '0'),
- reconfig_writedata => (others => '0'),
--- reconfig_readdata => reco_readdata[31:0],
--- reconfig_waitrequest => reco_waitrequest,
-
- l4_tx_data => l4_tx_sosi_arr(mac).data(255 downto 0),
- l4_tx_empty => l4_tx_sosi_arr(mac).empty(4 downto 0),
- l4_tx_startofpacket => l4_tx_sosi_arr(mac).sop,
- l4_tx_endofpacket => l4_tx_sosi_arr(mac).eop,
- l4_tx_ready => l4_tx_siso_arr(mac).ready,
- l4_tx_valid => l4_tx_sosi_arr(mac).valid,
- l4_tx_error => '0',
-
- l4_rx_data => l4_rx_sosi_arr(mac).data(255 downto 0),
- l4_rx_empty => l4_rx_sosi_arr(mac).empty(4 downto 0),
- l4_rx_startofpacket => l4_rx_sosi_arr(mac).sop,
- l4_rx_endofpacket => l4_rx_sosi_arr(mac).eop,
- -- l4_rx_error => ,
- l4_rx_valid => l4_rx_sosi_arr(mac).valid,
-
- -- l4_rx_status (),
- -- l4_rx_fcs_error (),
- -- l4_rx_fcs_valid (),
- -- rx_inc_octetsOK (),
- -- rx_inc_octetsOK_valid (),
- -- rx_inc_runt (),
- -- rx_inc_64 (),
- -- rx_inc_127 (),
- -- rx_inc_255 (),
- -- rx_inc_511 (),
- -- rx_inc_1023 (),
- -- rx_inc_1518 (),
- -- rx_inc_max (),
- -- rx_inc_over (),
- -- rx_inc_mcast_data_err (),
- -- rx_inc_mcast_data_ok (),
- -- rx_inc_bcast_data_err (),
- -- rx_inc_bcast_data_ok (),
- -- rx_inc_ucast_data_err (),
- -- rx_inc_ucast_data_ok (),
- -- rx_inc_mcast_ctrl (),
- -- rx_inc_bcast_ctrl (),
- -- rx_inc_ucast_ctrl (),
- -- rx_inc_pause (),
- -- rx_inc_fcs_err (),
- -- rx_inc_fragment (),
- -- rx_inc_jabber (),
- -- rx_inc_sizeok_fcserr (),
- -- rx_inc_pause_ctrl_err (),
- -- rx_inc_mcast_ctrl_err (),
- -- rx_inc_bcast_ctrl_err (),
- -- rx_inc_ucast_ctrl_err (),
- -- status_waitrequest (),
- tx_lanes_stable(0) => l4_tx_siso_arr(mac).xon,
- -- tx_inc_octetsOK (),
- -- tx_inc_octetsOK_valid (),
- -- tx_inc_64 (),
- -- tx_inc_127 (),
- -- tx_inc_255 (),
- -- tx_inc_511 (),
- -- tx_inc_1023 (),
- -- tx_inc_1518 (),
- -- tx_inc_max (),
- -- tx_inc_over (),
- -- tx_inc_mcast_data_err (),
- -- tx_inc_mcast_data_ok (),
- -- tx_inc_bcast_data_err (),
- -- tx_inc_bcast_data_ok (),
- -- tx_inc_ucast_data_err (),
- -- tx_inc_ucast_data_ok (),
- -- tx_inc_mcast_ctrl (),
- -- tx_inc_bcast_ctrl (),
- -- tx_inc_ucast_ctrl (),
- -- tx_inc_pause (),
- -- tx_inc_fcs_err (),
- -- tx_inc_fragment (),
- -- tx_inc_jabber (),
- -- tx_inc_sizeok_fcserr (),
-
- tx_serial => tx_serial_r(4 * (mac + 1) - 1 downto 4 * mac),
- rx_serial => rx_serial_r(4 * (mac + 1) - 1 downto 4 * mac)
- );
+ port map (
+ reset_async(0) => mm_rst,
+ clk_txmac(0) => clk_txmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
+ clk_rxmac(0) => clk_rxmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
+ clk_ref(0) => clk_ref_r,
+ rx_pcs_ready(0) => rx_pcs_ready_arr(mac),
+
+ tx_serial_clk => serial_clk_2arr(mac),
+ tx_pll_locked(0) => pll_locked_arr(mac),
+
+ clk_status(0) => mm_clk,
+ reset_status(0) => mm_rst,
+ status_addr => (others => '0'),
+ status_read => (others => '0'),
+ status_write => (others => '0'),
+ status_writedata => (others => '0'),
+ -- status_readdata => status_readdata_eth,
+ -- status_read_timeout => status_read_timeout,
+ -- status_readdata_valid => status_readdata_valid_eth,
+
+ reconfig_clk(0) => mm_clk,
+ reconfig_reset(0) => mm_rst,
+ reconfig_write => (others => '0'),
+ reconfig_read => (others => '0'),
+ reconfig_address => (others => '0'),
+ reconfig_writedata => (others => '0'),
+ -- reconfig_readdata => reco_readdata[31:0],
+ -- reconfig_waitrequest => reco_waitrequest,
+
+ l4_tx_data => l4_tx_sosi_arr(mac).data(255 downto 0),
+ l4_tx_empty => l4_tx_sosi_arr(mac).empty(4 downto 0),
+ l4_tx_startofpacket => l4_tx_sosi_arr(mac).sop,
+ l4_tx_endofpacket => l4_tx_sosi_arr(mac).eop,
+ l4_tx_ready => l4_tx_siso_arr(mac).ready,
+ l4_tx_valid => l4_tx_sosi_arr(mac).valid,
+ l4_tx_error => '0',
+
+ l4_rx_data => l4_rx_sosi_arr(mac).data(255 downto 0),
+ l4_rx_empty => l4_rx_sosi_arr(mac).empty(4 downto 0),
+ l4_rx_startofpacket => l4_rx_sosi_arr(mac).sop,
+ l4_rx_endofpacket => l4_rx_sosi_arr(mac).eop,
+ -- l4_rx_error => ,
+ l4_rx_valid => l4_rx_sosi_arr(mac).valid,
+
+ -- l4_rx_status (),
+ -- l4_rx_fcs_error (),
+ -- l4_rx_fcs_valid (),
+ -- rx_inc_octetsOK (),
+ -- rx_inc_octetsOK_valid (),
+ -- rx_inc_runt (),
+ -- rx_inc_64 (),
+ -- rx_inc_127 (),
+ -- rx_inc_255 (),
+ -- rx_inc_511 (),
+ -- rx_inc_1023 (),
+ -- rx_inc_1518 (),
+ -- rx_inc_max (),
+ -- rx_inc_over (),
+ -- rx_inc_mcast_data_err (),
+ -- rx_inc_mcast_data_ok (),
+ -- rx_inc_bcast_data_err (),
+ -- rx_inc_bcast_data_ok (),
+ -- rx_inc_ucast_data_err (),
+ -- rx_inc_ucast_data_ok (),
+ -- rx_inc_mcast_ctrl (),
+ -- rx_inc_bcast_ctrl (),
+ -- rx_inc_ucast_ctrl (),
+ -- rx_inc_pause (),
+ -- rx_inc_fcs_err (),
+ -- rx_inc_fragment (),
+ -- rx_inc_jabber (),
+ -- rx_inc_sizeok_fcserr (),
+ -- rx_inc_pause_ctrl_err (),
+ -- rx_inc_mcast_ctrl_err (),
+ -- rx_inc_bcast_ctrl_err (),
+ -- rx_inc_ucast_ctrl_err (),
+ -- status_waitrequest (),
+ tx_lanes_stable(0) => l4_tx_siso_arr(mac).xon,
+ -- tx_inc_octetsOK (),
+ -- tx_inc_octetsOK_valid (),
+ -- tx_inc_64 (),
+ -- tx_inc_127 (),
+ -- tx_inc_255 (),
+ -- tx_inc_511 (),
+ -- tx_inc_1023 (),
+ -- tx_inc_1518 (),
+ -- tx_inc_max (),
+ -- tx_inc_over (),
+ -- tx_inc_mcast_data_err (),
+ -- tx_inc_mcast_data_ok (),
+ -- tx_inc_bcast_data_err (),
+ -- tx_inc_bcast_data_ok (),
+ -- tx_inc_ucast_data_err (),
+ -- tx_inc_ucast_data_ok (),
+ -- tx_inc_mcast_ctrl (),
+ -- tx_inc_bcast_ctrl (),
+ -- tx_inc_ucast_ctrl (),
+ -- tx_inc_pause (),
+ -- tx_inc_fcs_err (),
+ -- tx_inc_fragment (),
+ -- tx_inc_jabber (),
+ -- tx_inc_sizeok_fcserr (),
+
+ tx_serial => tx_serial_r(4 * (mac + 1) - 1 downto 4 * mac),
+ rx_serial => rx_serial_r(4 * (mac + 1) - 1 downto 4 * mac)
+ );
-- No latency adapter needed as the RX MAC does not have a ready input
----------------------------------------------------------------------------
@@ -486,48 +486,48 @@ begin
----------------------------------------------------------------------------
rst_rxmac_arr(mac) <= not rx_pcs_ready_arr(mac);
u_dp_fifo_dc : entity dp_lib.dp_fifo_dc
- generic map (
- g_data_w => c_data_w,
- g_empty_w => 8,
- g_use_empty => true,
- g_use_bsn => false,
- g_bsn_w => 64,
- g_use_channel => false,
- g_use_sync => false,
- g_fifo_size => c_rx_fifo_size
- )
- port map (
- wr_clk => clk_rxmac_arr(mac),
- wr_rst => rst_rxmac_arr(mac),
+ generic map (
+ g_data_w => c_data_w,
+ g_empty_w => 8,
+ g_use_empty => true,
+ g_use_bsn => false,
+ g_bsn_w => 64,
+ g_use_channel => false,
+ g_use_sync => false,
+ g_fifo_size => c_rx_fifo_size
+ )
+ port map (
+ wr_clk => clk_rxmac_arr(mac),
+ wr_rst => rst_rxmac_arr(mac),
- rd_clk => kernel_clk,
- rd_rst => kernel_reset,
+ rd_clk => kernel_clk,
+ rd_rst => kernel_reset,
- snk_in => l4_rx_sosi_arr(mac),
- snk_out => OPEN,
+ snk_in => l4_rx_sosi_arr(mac),
+ snk_out => OPEN,
- src_out => dp_fifo_dc_src_out_arr(mac),
- src_in => dp_fifo_dc_src_in_arr(mac)
- );
+ src_out => dp_fifo_dc_src_out_arr(mac),
+ src_in => dp_fifo_dc_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (dp_fifo_dc) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_fifo_dc_src_out_arr(mac),
- snk_out => dp_fifo_dc_src_in_arr(mac),
+ snk_in => dp_fifo_dc_src_out_arr(mac),
+ snk_out => dp_fifo_dc_src_in_arr(mac),
- src_out => dp_latency_adapter_rx_src_out_arr(mac),
- src_in => dp_latency_adapter_rx_src_in_arr(mac)
- );
+ src_out => dp_latency_adapter_rx_src_out_arr(mac),
+ src_in => dp_latency_adapter_rx_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- Data mapping
@@ -550,15 +550,15 @@ begin
-------------------------------------------------------------------------------
u_common_areset_txmac : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 3
- )
- port map (
- in_rst => kernel_reset,
- clk => clk_txmac_arr(mac),
- out_rst => rst_txmac_arr(mac)
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 3
+ )
+ port map (
+ in_rst => kernel_reset,
+ clk => clk_txmac_arr(mac),
+ out_rst => rst_txmac_arr(mac)
+ );
-------------------------------------------------------------------------------
-- PLL for clock generation, every mac needs its own, due to clock nework limitations
diff --git a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
index 4e29874e8d..6d152164ae 100644
--- a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
+++ b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
@@ -32,11 +32,11 @@
-- . This core was developed for use on the Uniboard2b.
-- . The curret implementation only works with ddr4_8g_1600m
library IEEE, common_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_component_pkg.all;
entity ta2_unb2b_ddr is
generic (
@@ -194,154 +194,154 @@ architecture str of ta2_unb2b_ddr is
-- MM Pipe stage component
component ta2_unb2b_ddr_pipe_stage is
- generic (
- DATA_WIDTH : integer := 32;
- SYMBOL_WIDTH : integer := 8;
- HDL_ADDR_WIDTH : integer := 10;
- BURSTCOUNT_WIDTH : integer := 1;
- PIPELINE_COMMAND : integer := 1;
- PIPELINE_RESPONSE : integer := 1;
- SYNC_RESET : integer := 0
- );
- port (
- clk : in std_logic := 'X'; -- clk
- m0_waitrequest : in std_logic := 'X'; -- waitrequest
- m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- readdata
- m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
- m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0); -- burstcount
- m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- writedata
- m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0); -- address
- m0_write : out std_logic; -- write
- m0_read : out std_logic; -- read
- m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
- m0_debugaccess : out std_logic; -- debugaccess
- reset : in std_logic := 'X'; -- reset
- s0_waitrequest : out std_logic; -- waitrequest
- s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- readdata
- s0_readdatavalid : out std_logic; -- readdatavalid
- s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X'); -- burstcount
- s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- writedata
- s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X'); -- address
- s0_write : in std_logic := 'X'; -- write
- s0_read : in std_logic := 'X'; -- read
- s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
- s0_debugaccess : in std_logic := 'X' -- debugaccess
- );
- end component ta2_unb2b_ddr_pipe_stage;
-
- -- MM clock cross component
- component ta2_unb2b_ddr_clock_cross is
- generic (
- DATA_WIDTH : integer := 32;
- SYMBOL_WIDTH : integer := 8;
- HDL_ADDR_WIDTH : integer := 10;
- BURSTCOUNT_WIDTH : integer := 1;
- COMMAND_FIFO_DEPTH : integer := 4;
- RESPONSE_FIFO_DEPTH : integer := 4;
- MASTER_SYNC_DEPTH : integer := 2;
- SLAVE_SYNC_DEPTH : integer := 2
- );
- port (
- m0_waitrequest : in std_logic := 'X'; -- waitrequest
- m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- readdata
- m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
- m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0); -- burstcount
- m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- writedata
- m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0); -- address
- m0_write : out std_logic; -- write
- m0_read : out std_logic; -- read
- m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
- m0_debugaccess : out std_logic; -- debugaccess
- m0_clk : in std_logic := 'X'; -- clk
- m0_reset : in std_logic := 'X'; -- reset
- s0_waitrequest : out std_logic; -- waitrequest
- s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- readdata
- s0_readdatavalid : out std_logic; -- readdatavalid
- s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X'); -- burstcount
- s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- writedata
- s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X'); -- address
- s0_write : in std_logic := 'X'; -- write
- s0_read : in std_logic := 'X'; -- read
- s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
- s0_debugaccess : in std_logic := 'X'; -- debugaccess
- s0_clk : in std_logic := 'X'; -- clk
- s0_reset : in std_logic := 'X' -- reset
- );
- end component ta2_unb2b_ddr_clock_cross;
+ generic (
+ DATA_WIDTH : integer := 32;
+ SYMBOL_WIDTH : integer := 8;
+ HDL_ADDR_WIDTH : integer := 10;
+ BURSTCOUNT_WIDTH : integer := 1;
+ PIPELINE_COMMAND : integer := 1;
+ PIPELINE_RESPONSE : integer := 1;
+ SYNC_RESET : integer := 0
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0); -- burstcount
+ m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- writedata
+ m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0); -- address
+ m0_write : out std_logic; -- write
+ m0_read : out std_logic; -- read
+ m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ reset : in std_logic := 'X'; -- reset
+ s0_waitrequest : out std_logic; -- waitrequest
+ s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- readdata
+ s0_readdatavalid : out std_logic; -- readdatavalid
+ s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X'); -- burstcount
+ s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- writedata
+ s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X'); -- address
+ s0_write : in std_logic := 'X'; -- write
+ s0_read : in std_logic := 'X'; -- read
+ s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
+ s0_debugaccess : in std_logic := 'X' -- debugaccess
+ );
+ end component ta2_unb2b_ddr_pipe_stage;
+
+ -- MM clock cross component
+ component ta2_unb2b_ddr_clock_cross is
+ generic (
+ DATA_WIDTH : integer := 32;
+ SYMBOL_WIDTH : integer := 8;
+ HDL_ADDR_WIDTH : integer := 10;
+ BURSTCOUNT_WIDTH : integer := 1;
+ COMMAND_FIFO_DEPTH : integer := 4;
+ RESPONSE_FIFO_DEPTH : integer := 4;
+ MASTER_SYNC_DEPTH : integer := 2;
+ SLAVE_SYNC_DEPTH : integer := 2
+ );
+ port (
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0); -- burstcount
+ m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- writedata
+ m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0); -- address
+ m0_write : out std_logic; -- write
+ m0_read : out std_logic; -- read
+ m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_clk : in std_logic := 'X'; -- clk
+ m0_reset : in std_logic := 'X'; -- reset
+ s0_waitrequest : out std_logic; -- waitrequest
+ s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- readdata
+ s0_readdatavalid : out std_logic; -- readdatavalid
+ s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X'); -- burstcount
+ s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- writedata
+ s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X'); -- address
+ s0_write : in std_logic := 'X'; -- write
+ s0_read : in std_logic := 'X'; -- read
+ s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
+ s0_debugaccess : in std_logic := 'X'; -- debugaccess
+ s0_clk : in std_logic := 'X'; -- clk
+ s0_reset : in std_logic := 'X' -- reset
+ );
+ end component ta2_unb2b_ddr_clock_cross;
begin
gen_MB_I : if g_use_MB_I generate
u_mb_I_clock_cross : ta2_unb2b_ddr_clock_cross
- generic map (
- DATA_WIDTH => c_data_w,
- SYMBOL_WIDTH => c_symbol_w,
- HDL_ADDR_WIDTH => c_addr_w,
- BURSTCOUNT_WIDTH => c_burstcount_w,
- COMMAND_FIFO_DEPTH => c_command_fifo_depth,
- RESPONSE_FIFO_DEPTH => c_response_fifo_depth,
- MASTER_SYNC_DEPTH => c_master_sync_depth,
- SLAVE_SYNC_DEPTH => c_slave_sync_depth
- )
- port map (
- m0_waitrequest => mb_I_pipe_stage_s0_waitrequest,
- m0_readdata => mb_I_pipe_stage_s0_readdata,
- m0_readdatavalid => mb_I_pipe_stage_s0_readdatavalid,
- m0_burstcount => mb_I_pipe_stage_s0_burstcount,
- m0_writedata => mb_I_pipe_stage_s0_writedata,
- m0_address => mb_I_pipe_stage_s0_address,
- m0_write => mb_I_pipe_stage_s0_write,
- m0_read => mb_I_pipe_stage_s0_read,
- m0_byteenable => mb_I_pipe_stage_s0_byteenable,
- m0_debugaccess => mb_I_pipe_stage_s0_debugaccess,
- m0_clk => mb_I_emif_usr_clk,
- m0_reset => mb_I_emif_usr_reset,
- s0_waitrequest => mem0_waitrequest,
- s0_readdata => mem0_readdata,
- s0_readdatavalid => mem0_readdatavalid,
- s0_burstcount => mem0_burstcount,
- s0_writedata => mem0_writedata,
- s0_address => mem0_address,
- s0_write => mem0_write,
- s0_read => mem0_read,
- s0_byteenable => mem0_byteenable,
- s0_debugaccess => mem0_debugaccess,
- s0_clk => kernel_clk,
- s0_reset => kernel_reset
- );
+ generic map (
+ DATA_WIDTH => c_data_w,
+ SYMBOL_WIDTH => c_symbol_w,
+ HDL_ADDR_WIDTH => c_addr_w,
+ BURSTCOUNT_WIDTH => c_burstcount_w,
+ COMMAND_FIFO_DEPTH => c_command_fifo_depth,
+ RESPONSE_FIFO_DEPTH => c_response_fifo_depth,
+ MASTER_SYNC_DEPTH => c_master_sync_depth,
+ SLAVE_SYNC_DEPTH => c_slave_sync_depth
+ )
+ port map (
+ m0_waitrequest => mb_I_pipe_stage_s0_waitrequest,
+ m0_readdata => mb_I_pipe_stage_s0_readdata,
+ m0_readdatavalid => mb_I_pipe_stage_s0_readdatavalid,
+ m0_burstcount => mb_I_pipe_stage_s0_burstcount,
+ m0_writedata => mb_I_pipe_stage_s0_writedata,
+ m0_address => mb_I_pipe_stage_s0_address,
+ m0_write => mb_I_pipe_stage_s0_write,
+ m0_read => mb_I_pipe_stage_s0_read,
+ m0_byteenable => mb_I_pipe_stage_s0_byteenable,
+ m0_debugaccess => mb_I_pipe_stage_s0_debugaccess,
+ m0_clk => mb_I_emif_usr_clk,
+ m0_reset => mb_I_emif_usr_reset,
+ s0_waitrequest => mem0_waitrequest,
+ s0_readdata => mem0_readdata,
+ s0_readdatavalid => mem0_readdatavalid,
+ s0_burstcount => mem0_burstcount,
+ s0_writedata => mem0_writedata,
+ s0_address => mem0_address,
+ s0_write => mem0_write,
+ s0_read => mem0_read,
+ s0_byteenable => mem0_byteenable,
+ s0_debugaccess => mem0_debugaccess,
+ s0_clk => kernel_clk,
+ s0_reset => kernel_reset
+ );
u_mb_I_pipe_stage : ta2_unb2b_ddr_pipe_stage
- generic map (
- DATA_WIDTH => c_data_w,
- SYMBOL_WIDTH => c_symbol_w,
- HDL_ADDR_WIDTH => c_addr_w,
- BURSTCOUNT_WIDTH => c_burstcount_w,
- PIPELINE_COMMAND => c_pipeline_command,
- PIPELINE_RESPONSE => c_pipeline_response,
- SYNC_RESET => c_sync_reset
- )
- port map (
- clk => mb_I_emif_usr_clk, -- clk.clk
- m0_waitrequest => mb_I_pipe_stage_m0_waitrequest,
- m0_readdata => mb_I_pipe_stage_m0_readdata,
- m0_readdatavalid => mb_I_pipe_stage_m0_readdatavalid,
- m0_burstcount => mb_I_pipe_stage_m0_burstcount,
- m0_writedata => mb_I_pipe_stage_m0_writedata,
- m0_address => mb_I_pipe_stage_m0_address,
- m0_write => mb_I_pipe_stage_m0_write,
- m0_read => mb_I_pipe_stage_m0_read,
- m0_byteenable => mb_I_pipe_stage_m0_byteenable,
- m0_debugaccess => mb_I_pipe_stage_m0_debugaccess,
- reset => mb_I_emif_usr_reset, -- reset.reset
- s0_waitrequest => mb_I_pipe_stage_s0_waitrequest, -- s0.waitrequest
- s0_readdata => mb_I_pipe_stage_s0_readdata, -- .readdata
- s0_readdatavalid => mb_I_pipe_stage_s0_readdatavalid, -- .readdatavalid
- s0_burstcount => mb_I_pipe_stage_s0_burstcount, -- .burstcount
- s0_writedata => mb_I_pipe_stage_s0_writedata, -- .writedata
- s0_address => mb_I_pipe_stage_s0_address, -- .address
- s0_write => mb_I_pipe_stage_s0_write, -- .write
- s0_read => mb_I_pipe_stage_s0_read, -- .read
- s0_byteenable => mb_I_pipe_stage_s0_byteenable, -- .byteenable
- s0_debugaccess => mb_I_pipe_stage_s0_debugaccess -- .debugaccess
- );
+ generic map (
+ DATA_WIDTH => c_data_w,
+ SYMBOL_WIDTH => c_symbol_w,
+ HDL_ADDR_WIDTH => c_addr_w,
+ BURSTCOUNT_WIDTH => c_burstcount_w,
+ PIPELINE_COMMAND => c_pipeline_command,
+ PIPELINE_RESPONSE => c_pipeline_response,
+ SYNC_RESET => c_sync_reset
+ )
+ port map (
+ clk => mb_I_emif_usr_clk, -- clk.clk
+ m0_waitrequest => mb_I_pipe_stage_m0_waitrequest,
+ m0_readdata => mb_I_pipe_stage_m0_readdata,
+ m0_readdatavalid => mb_I_pipe_stage_m0_readdatavalid,
+ m0_burstcount => mb_I_pipe_stage_m0_burstcount,
+ m0_writedata => mb_I_pipe_stage_m0_writedata,
+ m0_address => mb_I_pipe_stage_m0_address,
+ m0_write => mb_I_pipe_stage_m0_write,
+ m0_read => mb_I_pipe_stage_m0_read,
+ m0_byteenable => mb_I_pipe_stage_m0_byteenable,
+ m0_debugaccess => mb_I_pipe_stage_m0_debugaccess,
+ reset => mb_I_emif_usr_reset, -- reset.reset
+ s0_waitrequest => mb_I_pipe_stage_s0_waitrequest, -- s0.waitrequest
+ s0_readdata => mb_I_pipe_stage_s0_readdata, -- .readdata
+ s0_readdatavalid => mb_I_pipe_stage_s0_readdatavalid, -- .readdatavalid
+ s0_burstcount => mb_I_pipe_stage_s0_burstcount, -- .burstcount
+ s0_writedata => mb_I_pipe_stage_s0_writedata, -- .writedata
+ s0_address => mb_I_pipe_stage_s0_address, -- .address
+ s0_write => mb_I_pipe_stage_s0_write, -- .write
+ s0_read => mb_I_pipe_stage_s0_read, -- .read
+ s0_byteenable => mb_I_pipe_stage_s0_byteenable, -- .byteenable
+ s0_debugaccess => mb_I_pipe_stage_s0_debugaccess -- .debugaccess
+ );
mb_I_pipe_stage_m0_waitrequest <= not mb_I_amm_ready_0;
mb_I_pipe_stage_m0_readdatavalid <= mb_I_amm_readdatavalid_0;
@@ -375,14 +375,14 @@ begin
mem_ck => mb_I_ou.ck(g_ddr_MB_I.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
mem_ck_n => mb_I_ou.ck_n(g_ddr_MB_I.ck_w - 1 downto 0), -- .mem_ck_n
mem_a => mb_I_ou.a(g_ddr_MB_I.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => mb_I_ou.act_n, -- .mem_act_n
+ sl(mem_act_n) => mb_I_ou.act_n, -- .mem_act_n
mem_ba => mb_I_ou.ba(g_ddr_MB_I.ba_w - 1 downto 0), -- .mem_ba
mem_bg => mb_I_ou.bg(g_ddr_MB_I.bg_w - 1 downto 0), -- .mem_bg
mem_cke => mb_I_ou.cke(g_ddr_MB_I.cke_w - 1 downto 0), -- .mem_cke
mem_cs_n => mb_I_ou.cs_n(g_ddr_MB_I.cs_w - 1 downto 0), -- .mem_cs_n
mem_odt => mb_I_ou.odt(g_ddr_MB_I.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => mb_I_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => mb_I_ou.par, -- .mem_par
+ sl(mem_reset_n) => mb_I_ou.reset_n, -- .mem_reset_n
+ sl(mem_par) => mb_I_ou.par, -- .mem_par
mem_alert_n => slv(mb_I_in.alert_n), -- .mem_alert_n
mem_dqs => mb_I_io.dqs(g_ddr_MB_I.dqs_w - 1 downto 0), -- .mem_dqs
mem_dqs_n => mb_I_io.dqs_n(g_ddr_MB_I.dqs_w - 1 downto 0), -- .mem_dqs_n
@@ -399,77 +399,77 @@ begin
gen_MB_II : if g_use_MB_II generate
u_mb_II_clock_cross : ta2_unb2b_ddr_clock_cross
- generic map (
- DATA_WIDTH => c_data_w,
- SYMBOL_WIDTH => c_symbol_w,
- HDL_ADDR_WIDTH => c_addr_w,
- BURSTCOUNT_WIDTH => c_burstcount_w,
- COMMAND_FIFO_DEPTH => c_command_fifo_depth,
- RESPONSE_FIFO_DEPTH => c_response_fifo_depth,
- MASTER_SYNC_DEPTH => c_master_sync_depth,
- SLAVE_SYNC_DEPTH => c_slave_sync_depth
- )
- port map (
- m0_waitrequest => mb_II_pipe_stage_s0_waitrequest,
- m0_readdata => mb_II_pipe_stage_s0_readdata,
- m0_readdatavalid => mb_II_pipe_stage_s0_readdatavalid,
- m0_burstcount => mb_II_pipe_stage_s0_burstcount,
- m0_writedata => mb_II_pipe_stage_s0_writedata,
- m0_address => mb_II_pipe_stage_s0_address,
- m0_write => mb_II_pipe_stage_s0_write,
- m0_read => mb_II_pipe_stage_s0_read,
- m0_byteenable => mb_II_pipe_stage_s0_byteenable,
- m0_debugaccess => mb_II_pipe_stage_s0_debugaccess,
- m0_clk => mb_II_emif_usr_clk,
- m0_reset => mb_II_emif_usr_reset,
- s0_waitrequest => mem1_waitrequest,
- s0_readdata => mem1_readdata,
- s0_readdatavalid => mem1_readdatavalid,
- s0_burstcount => mem1_burstcount,
- s0_writedata => mem1_writedata,
- s0_address => mem1_address,
- s0_write => mem1_write,
- s0_read => mem1_read,
- s0_byteenable => mem1_byteenable,
- s0_debugaccess => mem1_debugaccess,
- s0_clk => kernel_clk,
- s0_reset => kernel_reset
- );
+ generic map (
+ DATA_WIDTH => c_data_w,
+ SYMBOL_WIDTH => c_symbol_w,
+ HDL_ADDR_WIDTH => c_addr_w,
+ BURSTCOUNT_WIDTH => c_burstcount_w,
+ COMMAND_FIFO_DEPTH => c_command_fifo_depth,
+ RESPONSE_FIFO_DEPTH => c_response_fifo_depth,
+ MASTER_SYNC_DEPTH => c_master_sync_depth,
+ SLAVE_SYNC_DEPTH => c_slave_sync_depth
+ )
+ port map (
+ m0_waitrequest => mb_II_pipe_stage_s0_waitrequest,
+ m0_readdata => mb_II_pipe_stage_s0_readdata,
+ m0_readdatavalid => mb_II_pipe_stage_s0_readdatavalid,
+ m0_burstcount => mb_II_pipe_stage_s0_burstcount,
+ m0_writedata => mb_II_pipe_stage_s0_writedata,
+ m0_address => mb_II_pipe_stage_s0_address,
+ m0_write => mb_II_pipe_stage_s0_write,
+ m0_read => mb_II_pipe_stage_s0_read,
+ m0_byteenable => mb_II_pipe_stage_s0_byteenable,
+ m0_debugaccess => mb_II_pipe_stage_s0_debugaccess,
+ m0_clk => mb_II_emif_usr_clk,
+ m0_reset => mb_II_emif_usr_reset,
+ s0_waitrequest => mem1_waitrequest,
+ s0_readdata => mem1_readdata,
+ s0_readdatavalid => mem1_readdatavalid,
+ s0_burstcount => mem1_burstcount,
+ s0_writedata => mem1_writedata,
+ s0_address => mem1_address,
+ s0_write => mem1_write,
+ s0_read => mem1_read,
+ s0_byteenable => mem1_byteenable,
+ s0_debugaccess => mem1_debugaccess,
+ s0_clk => kernel_clk,
+ s0_reset => kernel_reset
+ );
u_mb_II_pipe_stage : ta2_unb2b_ddr_pipe_stage
- generic map (
- DATA_WIDTH => c_data_w,
- SYMBOL_WIDTH => c_symbol_w,
- HDL_ADDR_WIDTH => c_addr_w,
- BURSTCOUNT_WIDTH => c_burstcount_w,
- PIPELINE_COMMAND => c_pipeline_command,
- PIPELINE_RESPONSE => c_pipeline_response,
- SYNC_RESET => c_sync_reset
- )
- port map (
- clk => mb_II_emif_usr_clk, -- clk.clk
- m0_waitrequest => mb_II_pipe_stage_m0_waitrequest,
- m0_readdata => mb_II_pipe_stage_m0_readdata,
- m0_readdatavalid => mb_II_pipe_stage_m0_readdatavalid,
- m0_burstcount => mb_II_pipe_stage_m0_burstcount,
- m0_writedata => mb_II_pipe_stage_m0_writedata,
- m0_address => mb_II_pipe_stage_m0_address,
- m0_write => mb_II_pipe_stage_m0_write,
- m0_read => mb_II_pipe_stage_m0_read,
- m0_byteenable => mb_II_pipe_stage_m0_byteenable,
- m0_debugaccess => mb_II_pipe_stage_m0_debugaccess,
- reset => mb_II_emif_usr_reset, -- reset.reset
- s0_waitrequest => mb_II_pipe_stage_s0_waitrequest, -- s0.waitrequest
- s0_readdata => mb_II_pipe_stage_s0_readdata, -- .readdata
- s0_readdatavalid => mb_II_pipe_stage_s0_readdatavalid, -- .readdatavalid
- s0_burstcount => mb_II_pipe_stage_s0_burstcount, -- .burstcount
- s0_writedata => mb_II_pipe_stage_s0_writedata, -- .writedata
- s0_address => mb_II_pipe_stage_s0_address, -- .address
- s0_write => mb_II_pipe_stage_s0_write, -- .write
- s0_read => mb_II_pipe_stage_s0_read, -- .read
- s0_byteenable => mb_II_pipe_stage_s0_byteenable, -- .byteenable
- s0_debugaccess => mb_II_pipe_stage_s0_debugaccess -- .debugaccess
- );
+ generic map (
+ DATA_WIDTH => c_data_w,
+ SYMBOL_WIDTH => c_symbol_w,
+ HDL_ADDR_WIDTH => c_addr_w,
+ BURSTCOUNT_WIDTH => c_burstcount_w,
+ PIPELINE_COMMAND => c_pipeline_command,
+ PIPELINE_RESPONSE => c_pipeline_response,
+ SYNC_RESET => c_sync_reset
+ )
+ port map (
+ clk => mb_II_emif_usr_clk, -- clk.clk
+ m0_waitrequest => mb_II_pipe_stage_m0_waitrequest,
+ m0_readdata => mb_II_pipe_stage_m0_readdata,
+ m0_readdatavalid => mb_II_pipe_stage_m0_readdatavalid,
+ m0_burstcount => mb_II_pipe_stage_m0_burstcount,
+ m0_writedata => mb_II_pipe_stage_m0_writedata,
+ m0_address => mb_II_pipe_stage_m0_address,
+ m0_write => mb_II_pipe_stage_m0_write,
+ m0_read => mb_II_pipe_stage_m0_read,
+ m0_byteenable => mb_II_pipe_stage_m0_byteenable,
+ m0_debugaccess => mb_II_pipe_stage_m0_debugaccess,
+ reset => mb_II_emif_usr_reset, -- reset.reset
+ s0_waitrequest => mb_II_pipe_stage_s0_waitrequest, -- s0.waitrequest
+ s0_readdata => mb_II_pipe_stage_s0_readdata, -- .readdata
+ s0_readdatavalid => mb_II_pipe_stage_s0_readdatavalid, -- .readdatavalid
+ s0_burstcount => mb_II_pipe_stage_s0_burstcount, -- .burstcount
+ s0_writedata => mb_II_pipe_stage_s0_writedata, -- .writedata
+ s0_address => mb_II_pipe_stage_s0_address, -- .address
+ s0_write => mb_II_pipe_stage_s0_write, -- .write
+ s0_read => mb_II_pipe_stage_s0_read, -- .read
+ s0_byteenable => mb_II_pipe_stage_s0_byteenable, -- .byteenable
+ s0_debugaccess => mb_II_pipe_stage_s0_debugaccess -- .debugaccess
+ );
mb_II_pipe_stage_m0_waitrequest <= not mb_II_amm_ready_0;
mb_II_pipe_stage_m0_readdatavalid <= mb_II_amm_readdatavalid_0;
@@ -503,14 +503,14 @@ begin
mem_ck => mb_II_ou.ck(g_ddr_MB_II.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
mem_ck_n => mb_II_ou.ck_n(g_ddr_MB_II.ck_w - 1 downto 0), -- .mem_ck_n
mem_a => mb_II_ou.a(g_ddr_MB_II.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => mb_II_ou.act_n, -- .mem_act_n
+ sl(mem_act_n) => mb_II_ou.act_n, -- .mem_act_n
mem_ba => mb_II_ou.ba(g_ddr_MB_II.ba_w - 1 downto 0), -- .mem_ba
mem_bg => mb_II_ou.bg(g_ddr_MB_II.bg_w - 1 downto 0), -- .mem_bg
mem_cke => mb_II_ou.cke(g_ddr_MB_II.cke_w - 1 downto 0), -- .mem_cke
mem_cs_n => mb_II_ou.cs_n(g_ddr_MB_II.cs_w - 1 downto 0), -- .mem_cs_n
mem_odt => mb_II_ou.odt(g_ddr_MB_II.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => mb_II_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => mb_II_ou.par, -- .mem_par
+ sl(mem_reset_n) => mb_II_ou.reset_n, -- .mem_reset_n
+ sl(mem_par) => mb_II_ou.par, -- .mem_par
mem_alert_n => slv(mb_II_in.alert_n), -- .mem_alert_n
mem_dqs => mb_II_io.dqs(g_ddr_MB_II.dqs_w - 1 downto 0), -- .mem_dqs
mem_dqs_n => mb_II_io.dqs_n(g_ddr_MB_II.dqs_w - 1 downto 0), -- .mem_dqs_n
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
index c5d1073de0..5042bdb687 100644
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
@@ -42,12 +42,12 @@
-- | [0:15] | payload | ADC channel 0 sample |
-- +-----------+---------+--------------------------------------------------------+
library IEEE, common_lib, dp_lib, tech_pll_lib, technology_lib, tech_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
entity ta2_unb2b_jesd204b is
generic (
@@ -105,32 +105,32 @@ begin
jesd204b_disable_arr <= (others => '0');
u_jesd204b: entity tech_jesd204b_lib.tech_jesd204b
- generic map(
- g_sim => c_sim,
- g_nof_streams => c_nof_streams_jesd204b
- )
- port map(
- jesd204b_refclk => jesd204b_refclk,
- jesd204b_sysref => jesd204b_sysref,
- jesd204b_sync_n_arr => i_jesd204b_sync_n_arr,
-
- jesd204b_disable_arr => jesd204b_disable_arr,
-
- rx_sosi_arr => jesd204b_rx_sosi_arr,
- rx_clk => jesd204b_rx_clk,
- rx_rst => jesd204b_rx_rst,
-
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
-
- -- Serial
- serial_tx_arr => open,
- serial_rx_arr => jesd204b_serial_rx_arr
- );
+ generic map(
+ g_sim => c_sim,
+ g_nof_streams => c_nof_streams_jesd204b
+ )
+ port map(
+ jesd204b_refclk => jesd204b_refclk,
+ jesd204b_sysref => jesd204b_sysref,
+ jesd204b_sync_n_arr => i_jesd204b_sync_n_arr,
+
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ rx_sosi_arr => jesd204b_rx_sosi_arr,
+ rx_clk => jesd204b_rx_clk,
+ rx_rst => jesd204b_rx_rst,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => jesd204b_serial_rx_arr
+ );
gen_streams: for stream in 0 to g_nof_streams - 1 generate
---------------------------------------------------------------------------------------
@@ -143,45 +143,45 @@ begin
dp_fifo_dc_rx_snk_in_arr(stream).valid <= dp_fifo_dc_rx_snk_out_arr(stream).ready and jesd204b_rx_sosi_arr(stream).valid;
u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_data_w => 16,
- g_empty_w => 1,
- g_use_empty => false,
- g_use_ctrl => false,
- g_fifo_size => c_rx_fifo_size
- )
- port map (
- wr_rst => jesd204b_rx_rst,
- wr_clk => jesd204b_rx_clk,
- rd_rst => kernel_reset,
- rd_clk => kernel_clk,
-
- snk_out => dp_fifo_dc_rx_snk_out_arr(stream),
- snk_in => dp_fifo_dc_rx_snk_in_arr(stream),
-
- src_in => dp_fifo_dc_rx_src_in_arr(stream),
- src_out => dp_fifo_dc_rx_src_out_arr(stream)
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_data_w => 16,
+ g_empty_w => 1,
+ g_use_empty => false,
+ g_use_ctrl => false,
+ g_fifo_size => c_rx_fifo_size
+ )
+ port map (
+ wr_rst => jesd204b_rx_rst,
+ wr_clk => jesd204b_rx_clk,
+ rd_rst => kernel_reset,
+ rd_clk => kernel_clk,
+
+ snk_out => dp_fifo_dc_rx_snk_out_arr(stream),
+ snk_in => dp_fifo_dc_rx_snk_in_arr(stream),
+
+ src_in => dp_fifo_dc_rx_src_in_arr(stream),
+ src_out => dp_fifo_dc_rx_src_out_arr(stream)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_fifo_dc_rx_src_out_arr(stream),
- snk_out => dp_fifo_dc_rx_src_in_arr(stream),
-
- src_out => dp_latency_adapter_rx_src_out_arr(stream),
- src_in => dp_latency_adapter_rx_src_in_arr(stream)
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
+
+ snk_in => dp_fifo_dc_rx_src_out_arr(stream),
+ snk_out => dp_fifo_dc_rx_src_in_arr(stream),
+
+ src_out => dp_latency_adapter_rx_src_out_arr(stream),
+ src_in => dp_latency_adapter_rx_src_in_arr(stream)
+ );
----------------------------------------------------------------------------
-- Data mapping
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
index 102c3f0ec1..4c38c3384d 100644
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
@@ -24,7 +24,7 @@
-- Purpose:
-- . Instantiates ta2_unb2b_10GbE component
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity ta2_unb2b_jesd204b_ip_wrapper is
port (
@@ -91,23 +91,23 @@ architecture str of ta2_unb2b_jesd204b_ip_wrapper is
end component ta2_unb2b_jesd204b;
begin
u_ta2_unb2b_jesd204b : ta2_unb2b_jesd204b
- port map (
- config_clk => config_clk,
- config_reset => config_reset,
- jesd204b_mosi_address => jesd204b_mosi_address,
- jesd204b_mosi_wrdata => jesd204b_mosi_wrdata,
- jesd204b_mosi_wr => jesd204b_mosi_wr,
- jesd204b_mosi_rd => jesd204b_mosi_rd,
- jesd204b_miso_rddata => jesd204b_miso_rddata,
- jesd204b_miso_waitrequest => jesd204b_miso_waitrequest,
- jesd204b_refclk => jesd204b_refclk,
- jesd204b_sysref => jesd204b_sysref,
- jesd204b_sync_n_arr => jesd204b_sync_n_arr,
- serial_rx_arr => serial_rx_arr,
- kernel_clk => kernel_clk,
- kernel_reset => kernel_reset,
- kernel_src_data => kernel_src_data,
- kernel_src_valid => kernel_src_valid,
- kernel_src_ready => kernel_src_ready
- );
+ port map (
+ config_clk => config_clk,
+ config_reset => config_reset,
+ jesd204b_mosi_address => jesd204b_mosi_address,
+ jesd204b_mosi_wrdata => jesd204b_mosi_wrdata,
+ jesd204b_mosi_wr => jesd204b_mosi_wr,
+ jesd204b_mosi_rd => jesd204b_mosi_rd,
+ jesd204b_miso_rddata => jesd204b_miso_rddata,
+ jesd204b_miso_waitrequest => jesd204b_miso_waitrequest,
+ jesd204b_refclk => jesd204b_refclk,
+ jesd204b_sysref => jesd204b_sysref,
+ jesd204b_sync_n_arr => jesd204b_sync_n_arr,
+ serial_rx_arr => serial_rx_arr,
+ kernel_clk => kernel_clk,
+ kernel_reset => kernel_reset,
+ kernel_src_data => kernel_src_data,
+ kernel_src_valid => kernel_src_valid,
+ kernel_src_ready => kernel_src_ready
+ );
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
index f73837193b..01f2ae959f 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
@@ -61,12 +61,12 @@
-- registers are rddata = wrdata.
-- --------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
entity ta2_unb2b_mm_io is
generic (
@@ -146,7 +146,7 @@ begin
-----------------------------------------------------------------------------
-- dual clock FIFOs
-----------------------------------------------------------------------------
- u_dp_fifo_dc_wr : entity dp_lib.dp_fifo_dc
+ u_dp_fifo_dc_wr : entity dp_lib.dp_fifo_dc
generic map (
g_technology => c_tech_arria10_e1sg,
g_data_w => c_wr_data_w,
@@ -169,7 +169,7 @@ begin
src_out => out_sosi
);
- u_dp_fifo_dc_rd : entity dp_lib.dp_fifo_dc
+ u_dp_fifo_dc_rd : entity dp_lib.dp_fifo_dc
generic map (
g_technology => c_tech_arria10_e1sg,
g_data_w => c_rd_data_w,
@@ -192,68 +192,68 @@ begin
src_out => rd_sosi
);
-gen_no_opencl : if not g_use_opencl generate
- -- simulate an OpenCL kernel response (rl=0)
- p_is_reading : process(kernel_clk)
- begin
- if rising_edge(kernel_clk) then
- if cnt >= c_cnt_max then
- cnt <= 0;
- is_reading <= false;
- else
- cnt <= cnt + 1;
- end if;
- if in_sosi.valid = '1' then
- is_reading <= true;
- cnt <= 0;
+ gen_no_opencl : if not g_use_opencl generate
+ -- simulate an OpenCL kernel response (rl=0)
+ p_is_reading : process(kernel_clk)
+ begin
+ if rising_edge(kernel_clk) then
+ if cnt >= c_cnt_max then
+ cnt <= 0;
+ is_reading <= false;
+ else
+ cnt <= cnt + 1;
+ end if;
+ if in_sosi.valid = '1' then
+ is_reading <= true;
+ cnt <= 0;
+ end if;
end if;
- end if;
- end process;
+ end process;
- p_stim_st : process(out_sosi, in_siso, is_reading)
- begin
- in_sosi.valid <= '0';
- if out_sosi.valid = '1' then
- if out_sosi.data(64) = '1' then -- Write request
- if TO_UINT(out_sosi.data(63 downto 56)) = 0 then
- reg_a <= out_sosi.data(31 downto 0);
- elsif TO_UINT(out_sosi.data(63 downto 56)) = 1 then
- reg_b <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 1, 8) & out_sosi.data(23 downto 0); -- wrdata +1 to make distinguishable
- elsif TO_UINT(out_sosi.data(63 downto 56)) = 2 then
- reg_c <= out_sosi.data(31 downto 0);
- elsif TO_UINT(out_sosi.data(63 downto 56)) = 3 then
- reg_d <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 2, 8) & out_sosi.data(23 downto 0); -- wrdata +2 to make distinguishable
- end if;
- out_siso.ready <= '1';
- else -- read request
- if not is_reading then
- out_siso.ready <= '1';
- in_sosi.valid <= '1';
+ p_stim_st : process(out_sosi, in_siso, is_reading)
+ begin
+ in_sosi.valid <= '0';
+ if out_sosi.valid = '1' then
+ if out_sosi.data(64) = '1' then -- Write request
if TO_UINT(out_sosi.data(63 downto 56)) = 0 then
- in_sosi.data(31 downto 0) <= reg_a;
+ reg_a <= out_sosi.data(31 downto 0);
elsif TO_UINT(out_sosi.data(63 downto 56)) = 1 then
- in_sosi.data(31 downto 0) <= reg_b;
+ reg_b <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 1, 8) & out_sosi.data(23 downto 0); -- wrdata +1 to make distinguishable
elsif TO_UINT(out_sosi.data(63 downto 56)) = 2 then
- in_sosi.data(31 downto 0) <= reg_c;
+ reg_c <= out_sosi.data(31 downto 0);
elsif TO_UINT(out_sosi.data(63 downto 56)) = 3 then
- in_sosi.data(31 downto 0) <= reg_d;
- else
- in_sosi.data(31 downto 0) <= (others => '0');
+ reg_d <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 2, 8) & out_sosi.data(23 downto 0); -- wrdata +2 to make distinguishable
+ end if;
+ out_siso.ready <= '1';
+ else -- read request
+ if not is_reading then
+ out_siso.ready <= '1';
+ in_sosi.valid <= '1';
+ if TO_UINT(out_sosi.data(63 downto 56)) = 0 then
+ in_sosi.data(31 downto 0) <= reg_a;
+ elsif TO_UINT(out_sosi.data(63 downto 56)) = 1 then
+ in_sosi.data(31 downto 0) <= reg_b;
+ elsif TO_UINT(out_sosi.data(63 downto 56)) = 2 then
+ in_sosi.data(31 downto 0) <= reg_c;
+ elsif TO_UINT(out_sosi.data(63 downto 56)) = 3 then
+ in_sosi.data(31 downto 0) <= reg_d;
+ else
+ in_sosi.data(31 downto 0) <= (others => '0');
+ end if;
end if;
end if;
end if;
- end if;
- end process;
+ end process;
- src_out <= c_dp_sosi_rst;
- snk_out <= c_dp_siso_rdy;
-end generate;
+ src_out <= c_dp_sosi_rst;
+ snk_out <= c_dp_siso_rdy;
+ end generate;
-gen_opencl : if g_use_opencl generate
- src_out <= out_sosi;
- out_siso <= src_in;
- snk_out <= in_siso;
- in_sosi <= snk_in;
-end generate;
+ gen_opencl : if g_use_opencl generate
+ src_out <= out_sosi;
+ out_siso <= src_in;
+ snk_out <= in_siso;
+ in_sosi <= snk_in;
+ end generate;
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
index 262dbfdd93..062957000e 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
@@ -27,15 +27,15 @@
-- . Usage -> as 10; run -a
-- --------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_ta2_unb2b_mm_io is
end tb_ta2_unb2b_mm_io;
@@ -72,28 +72,28 @@ begin
end process;
u_dut : entity work.ta2_unb2b_mm_io
- generic map(
- g_use_opencl => false
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => rst,
- mm_clk => clk,
-
- mm_mosi => mm_mosi,
- mm_miso => mm_miso,
-
- -- Streaming clock domain
- kernel_reset => rst,
- kernel_clk => clk,
-
- -- ST sinks
- snk_out => in_siso,
- snk_in => in_sosi,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map(
+ g_use_opencl => false
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => rst,
+ mm_clk => clk,
+
+ mm_mosi => mm_mosi,
+ mm_miso => mm_miso,
+
+ -- Streaming clock domain
+ kernel_reset => rst,
+ kernel_clk => clk,
+
+ -- ST sinks
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
p_stim_mm : process
begin
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
index e669d24a75..05c62f6125 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
@@ -27,16 +27,16 @@
-- the MM interface
library IEEE, common_lib, unb1_board_lib, dp_lib, i2c_lib, ppsh_lib, aduh_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.unb1_bn_capture_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use i2c_lib.i2c_commander_aduh_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.unb1_bn_capture_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use i2c_lib.i2c_commander_aduh_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
entity node_unb1_bn_capture is
generic (
@@ -187,129 +187,129 @@ begin
-- . input from 4 signal paths A, B, C and D of 8b @ 800 MSps each
-- . output 4 signal streams via sp_sosi_arr with 4 samples per 32b data word
u_input: entity work.unb1_bn_capture_input
- generic map (
- g_sim => g_sim,
- g_bn_capture => g_bn_capture,
- g_use_phy => g_use_phy,
- g_nof_dp_phs_clk => g_nof_dp_phs_clk,
- g_ai => g_ai
- )
- port map (
- -- ADC Interface
- -- . ADU_AB
- ADC_BI_A => ADC_BI_A,
- ADC_BI_B => ADC_BI_B,
- ADC_BI_A_CLK => ADC_BI_A_CLK,
- ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST,
-
- -- . ADU_CD
- ADC_BI_C => ADC_BI_C,
- ADC_BI_D => ADC_BI_D,
- ADC_BI_D_CLK => ADC_BI_D_CLK,
- ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
-
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec,
- dp_pps => dp_pps,
-
- -- MM bsn source
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
-
- -- MM bsn schedule WG
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
-
- -- MM aduh quad
- reg_adc_quad_mosi => reg_adc_quad_mosi,
- reg_adc_quad_miso => reg_adc_quad_miso,
-
- -- MM wideband waveform generator ports [A, B, C, B]
- reg_wg_mosi_arr => reg_wg_mosi_arr,
- reg_wg_miso_arr => reg_wg_miso_arr,
- ram_wg_mosi_arr => ram_wg_mosi_arr,
- ram_wg_miso_arr => ram_wg_miso_arr,
-
- -- MM DP shiftram
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
-
- -- MM signal path data monitors [A, B, C, B]
- reg_mon_mosi_arr => reg_mon_mosi_arr,
- reg_mon_miso_arr => reg_mon_miso_arr,
- ram_mon_mosi_arr => ram_mon_mosi_arr,
- ram_mon_miso_arr => ram_mon_miso_arr,
-
- -- Streaming output (can be from ADU or from internal WG)
- sp_sosi_arr => i_sp_sosi_arr,
- sp_siso_arr => sp_siso_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_bn_capture => g_bn_capture,
+ g_use_phy => g_use_phy,
+ g_nof_dp_phs_clk => g_nof_dp_phs_clk,
+ g_ai => g_ai
+ )
+ port map (
+ -- ADC Interface
+ -- . ADU_AB
+ ADC_BI_A => ADC_BI_A,
+ ADC_BI_B => ADC_BI_B,
+ ADC_BI_A_CLK => ADC_BI_A_CLK,
+ ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST,
+
+ -- . ADU_CD
+ ADC_BI_C => ADC_BI_C,
+ ADC_BI_D => ADC_BI_D,
+ ADC_BI_D_CLK => ADC_BI_D_CLK,
+ ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
+
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec,
+ dp_pps => dp_pps,
+
+ -- MM bsn source
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+
+ -- MM bsn schedule WG
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- MM aduh quad
+ reg_adc_quad_mosi => reg_adc_quad_mosi,
+ reg_adc_quad_miso => reg_adc_quad_miso,
+
+ -- MM wideband waveform generator ports [A, B, C, B]
+ reg_wg_mosi_arr => reg_wg_mosi_arr,
+ reg_wg_miso_arr => reg_wg_miso_arr,
+ ram_wg_mosi_arr => ram_wg_mosi_arr,
+ ram_wg_miso_arr => ram_wg_miso_arr,
+
+ -- MM DP shiftram
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+
+ -- MM signal path data monitors [A, B, C, B]
+ reg_mon_mosi_arr => reg_mon_mosi_arr,
+ reg_mon_miso_arr => reg_mon_miso_arr,
+ ram_mon_mosi_arr => ram_mon_mosi_arr,
+ ram_mon_miso_arr => ram_mon_miso_arr,
+
+ -- Streaming output (can be from ADU or from internal WG)
+ sp_sosi_arr => i_sp_sosi_arr,
+ sp_siso_arr => sp_siso_arr
+ );
------------------------------------------------------------------------------
-- 2a) I2C control for ADU AB
------------------------------------------------------------------------------
u_i2c_adu_ab : entity i2c_lib.i2c_commander
- generic map (
- g_sim => g_sim,
- g_i2c_cmdr => c_i2c_cmdr_aduh_protocol_commander,
- g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm), -- use full address range in sim to avoid warnings
- g_i2c_phy => func_i2c_calculate_phy(g_bn_capture.mm_clk_freq / 10**6),
- g_protocol_ram_init_file => "data/adu_protocol_ram_init.hex",
- g_use_result_ram => c_use_result_ram
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- sync => '1',
-
- -- Memory Mapped slave interfaces
- commander_mosi => reg_commander_mosi_arr(0),
- commander_miso => reg_commander_miso_arr(0),
- protocol_mosi => ram_protocol_mosi_arr(0),
- protocol_miso => ram_protocol_miso_arr(0),
- result_mosi => ram_result_mosi_arr(0),
- result_miso => ram_result_miso_arr(0),
-
- -- I2C interface
- scl => ADC_AB_SCL,
- sda => ADC_AB_SDA
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_cmdr => c_i2c_cmdr_aduh_protocol_commander,
+ g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm), -- use full address range in sim to avoid warnings
+ g_i2c_phy => func_i2c_calculate_phy(g_bn_capture.mm_clk_freq / 10**6),
+ g_protocol_ram_init_file => "data/adu_protocol_ram_init.hex",
+ g_use_result_ram => c_use_result_ram
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ sync => '1',
+
+ -- Memory Mapped slave interfaces
+ commander_mosi => reg_commander_mosi_arr(0),
+ commander_miso => reg_commander_miso_arr(0),
+ protocol_mosi => ram_protocol_mosi_arr(0),
+ protocol_miso => ram_protocol_miso_arr(0),
+ result_mosi => ram_result_mosi_arr(0),
+ result_miso => ram_result_miso_arr(0),
+
+ -- I2C interface
+ scl => ADC_AB_SCL,
+ sda => ADC_AB_SDA
+ );
------------------------------------------------------------------------------
-- 2b) I2C control for ADU CD
------------------------------------------------------------------------------
u_i2c_adu_cd : entity i2c_lib.i2c_commander
- generic map (
- g_sim => g_sim,
- g_i2c_cmdr => c_i2c_cmdr_aduh_protocol_commander,
- g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm), -- use full address range in sim to avoid warnings
- g_i2c_phy => func_i2c_calculate_phy(g_bn_capture.mm_clk_freq / 10**6),
- g_protocol_ram_init_file => "data/adu_protocol_ram_init.hex",
- g_use_result_ram => c_use_result_ram
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- sync => '1',
-
- -- Memory Mapped slave interfaces
- commander_mosi => reg_commander_mosi_arr(1),
- commander_miso => reg_commander_miso_arr(1),
- protocol_mosi => ram_protocol_mosi_arr(1),
- protocol_miso => ram_protocol_miso_arr(1),
- result_mosi => ram_result_mosi_arr(1),
- result_miso => ram_result_miso_arr(1),
-
- -- I2C interface
- scl => ADC_CD_SCL,
- sda => ADC_CD_SDA
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_cmdr => c_i2c_cmdr_aduh_protocol_commander,
+ g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm), -- use full address range in sim to avoid warnings
+ g_i2c_phy => func_i2c_calculate_phy(g_bn_capture.mm_clk_freq / 10**6),
+ g_protocol_ram_init_file => "data/adu_protocol_ram_init.hex",
+ g_use_result_ram => c_use_result_ram
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ sync => '1',
+
+ -- Memory Mapped slave interfaces
+ commander_mosi => reg_commander_mosi_arr(1),
+ commander_miso => reg_commander_miso_arr(1),
+ protocol_mosi => ram_protocol_mosi_arr(1),
+ protocol_miso => ram_protocol_miso_arr(1),
+ result_mosi => ram_result_mosi_arr(1),
+ result_miso => ram_result_miso_arr(1),
+
+ -- I2C interface
+ scl => ADC_CD_SCL,
+ sda => ADC_CD_SDA
+ );
------------------------------------------------------------------------------
-- 3) Feed each SP through a flusher that is controlled by a scheduler
@@ -317,79 +317,79 @@ begin
gen_flushers: for i in 0 to g_ai.nof_sp - 1 generate
u_dp_flush: entity dp_lib.dp_flush
- generic map (
- g_framed_xon => true,
- g_framed_xoff => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => i_sp_sosi_arr(i),
- snk_out => sp_siso_arr(i),
- -- ST source
- src_in => scheduled_sp_siso_arr(i),
- src_out => scheduled_sp_sosi_arr(i),
- -- Enable flush
- flush_en => sp_flush_en
- );
+ generic map (
+ g_framed_xon => true,
+ g_framed_xoff => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => i_sp_sosi_arr(i),
+ snk_out => sp_siso_arr(i),
+ -- ST source
+ src_in => scheduled_sp_siso_arr(i),
+ src_out => scheduled_sp_sosi_arr(i),
+ -- Enable flush
+ flush_en => sp_flush_en
+ );
end generate;
-- Convert the schedulers trigger on/off pulses to flush disable/enable level
u_sp_flush_switch : entity common_lib.common_switch
- generic map (
- g_rst_level => '1',
- g_priority_lo => false,
- g_or_high => false,
- g_and_low => false
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- switch_high => dp_bsn_trigger_sp_off,
- switch_low => dp_bsn_trigger_sp_on,
- out_level => sp_flush_en
- );
+ generic map (
+ g_rst_level => '1',
+ g_priority_lo => false,
+ g_or_high => false,
+ g_and_low => false
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ switch_high => dp_bsn_trigger_sp_off,
+ switch_low => dp_bsn_trigger_sp_on,
+ out_level => sp_flush_en
+ );
u_bsn_trigger_sp_on : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- g_bsn_w => c_dp_stream_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_sp_on_mosi,
- reg_miso => reg_bsn_scheduler_sp_on_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
- trigger_out => dp_bsn_trigger_sp_on
- );
+ generic map (
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ g_bsn_w => c_dp_stream_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_sp_on_mosi,
+ reg_miso => reg_bsn_scheduler_sp_on_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
+ trigger_out => dp_bsn_trigger_sp_on
+ );
u_bsn_trigger_sp_off : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- g_bsn_w => c_dp_stream_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_sp_off_mosi,
- reg_miso => reg_bsn_scheduler_sp_off_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
- trigger_out => dp_bsn_trigger_sp_off
- );
+ generic map (
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ g_bsn_w => c_dp_stream_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_sp_off_mosi,
+ reg_miso => reg_bsn_scheduler_sp_off_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
+ trigger_out => dp_bsn_trigger_sp_off
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
index 39f0e51e18..e972dbe38c 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
@@ -22,18 +22,18 @@
-- Purpose: Capture ADC samples from ADU on a BN
library IEEE, common_lib, unb1_board_lib, dp_lib, ppsh_lib, eth_lib, tech_tse_lib, aduh_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
-use work.unb1_bn_capture_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
+ use work.unb1_bn_capture_pkg.all;
entity unb1_bn_capture is
generic (
@@ -192,547 +192,547 @@ begin
-----------------------------------------------------------------------------
u_sopc : entity work.sopc_unb1_bn_capture
- port map (
- -- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => mm_clk, -- PLL clk[0] = 50 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => OPEN, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_source
- coe_clk_export_from_the_reg_bsn_source => OPEN,
- coe_reset_export_from_the_reg_bsn_source => OPEN,
- coe_address_export_from_the_reg_bsn_source => reg_bsn_source_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_source_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_bsn_source => reg_bsn_source_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_source => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_bsn_source => reg_bsn_source_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_source => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_scheduler_wg
- coe_clk_export_from_the_reg_bsn_scheduler_wg => OPEN,
- coe_reset_export_from_the_reg_bsn_scheduler_wg => OPEN,
- coe_address_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.address(0), -- reg_bsn_scheduler_adr_w = 1
- coe_read_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_adc_quad
- coe_clk_export_from_the_reg_adc_quad => OPEN,
- coe_reset_export_from_the_reg_adc_quad => OPEN,
- coe_address_export_from_the_reg_adc_quad => reg_adc_quad_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_adc_quad_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_adc_quad => reg_adc_quad_mosi.rd,
- coe_readdata_export_to_the_reg_adc_quad => reg_adc_quad_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_adc_quad => reg_adc_quad_mosi.wr,
- coe_writedata_export_from_the_reg_adc_quad => reg_adc_quad_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_wg_0
- coe_clk_export_from_the_reg_diag_wg_0 => OPEN,
- coe_reset_export_from_the_reg_diag_wg_0 => OPEN,
- coe_address_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).rd,
- coe_readdata_export_to_the_reg_diag_wg_0 => reg_wg_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).wr,
- coe_writedata_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_wg_1
- coe_clk_export_from_the_reg_diag_wg_1 => OPEN,
- coe_reset_export_from_the_reg_diag_wg_1 => OPEN,
- coe_address_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).rd,
- coe_readdata_export_to_the_reg_diag_wg_1 => reg_wg_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).wr,
- coe_writedata_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_wg_2
- coe_clk_export_from_the_reg_diag_wg_2 => OPEN,
- coe_reset_export_from_the_reg_diag_wg_2 => OPEN,
- coe_address_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).rd,
- coe_readdata_export_to_the_reg_diag_wg_2 => reg_wg_miso_arr(2).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).wr,
- coe_writedata_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_wg_3
- coe_clk_export_from_the_reg_diag_wg_3 => OPEN,
- coe_reset_export_from_the_reg_diag_wg_3 => OPEN,
- coe_address_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).rd,
- coe_readdata_export_to_the_reg_diag_wg_3 => reg_wg_miso_arr(3).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).wr,
- coe_writedata_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_wg_0
- coe_clk_export_from_the_ram_diag_wg_0 => OPEN,
- coe_reset_export_from_the_ram_diag_wg_0 => OPEN,
- coe_address_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).rd,
- coe_readdata_export_to_the_ram_diag_wg_0 => ram_wg_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).wr,
- coe_writedata_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_wg_1
- coe_clk_export_from_the_ram_diag_wg_1 => OPEN,
- coe_reset_export_from_the_ram_diag_wg_1 => OPEN,
- coe_address_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).rd,
- coe_readdata_export_to_the_ram_diag_wg_1 => ram_wg_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).wr,
- coe_writedata_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_wg_2
- coe_clk_export_from_the_ram_diag_wg_2 => OPEN,
- coe_reset_export_from_the_ram_diag_wg_2 => OPEN,
- coe_address_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).rd,
- coe_readdata_export_to_the_ram_diag_wg_2 => ram_wg_miso_arr(2).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).wr,
- coe_writedata_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_wg_3
- coe_clk_export_from_the_ram_diag_wg_3 => OPEN,
- coe_reset_export_from_the_ram_diag_wg_3 => OPEN,
- coe_address_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).rd,
- coe_readdata_export_to_the_ram_diag_wg_3 => ram_wg_miso_arr(3).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).wr,
- coe_writedata_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dp_shiftram
- coe_clk_export_from_the_reg_dp_shiftram => OPEN,
- coe_reset_export_from_the_reg_dp_shiftram => OPEN,
- coe_address_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.address(c_reg_dp_shiftram_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.rd,
- coe_readdata_export_to_the_reg_dp_shiftram => reg_dp_shiftram_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.wr,
- coe_writedata_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_aduh_mon_0
- coe_clk_export_from_the_reg_aduh_mon_0 => OPEN,
- coe_reset_export_from_the_reg_aduh_mon_0 => OPEN,
- coe_address_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).rd,
- coe_readdata_export_to_the_reg_aduh_mon_0 => reg_mon_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).wr,
- coe_writedata_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_aduh_mon_1
- coe_clk_export_from_the_reg_aduh_mon_1 => OPEN,
- coe_reset_export_from_the_reg_aduh_mon_1 => OPEN,
- coe_address_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).rd,
- coe_readdata_export_to_the_reg_aduh_mon_1 => reg_mon_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).wr,
- coe_writedata_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_aduh_mon_2
- coe_clk_export_from_the_reg_aduh_mon_2 => OPEN,
- coe_reset_export_from_the_reg_aduh_mon_2 => OPEN,
- coe_address_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).rd,
- coe_readdata_export_to_the_reg_aduh_mon_2 => reg_mon_miso_arr(2).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).wr,
- coe_writedata_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_aduh_mon_3
- coe_clk_export_from_the_reg_aduh_mon_3 => OPEN,
- coe_reset_export_from_the_reg_aduh_mon_3 => OPEN,
- coe_address_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).rd,
- coe_readdata_export_to_the_reg_aduh_mon_3 => reg_mon_miso_arr(3).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).wr,
- coe_writedata_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_aduh_mon_0
- coe_clk_export_from_the_ram_aduh_mon_0 => OPEN,
- coe_reset_export_from_the_ram_aduh_mon_0 => OPEN,
- coe_address_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).rd,
- coe_readdata_export_to_the_ram_aduh_mon_0 => ram_mon_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).wr,
- coe_writedata_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_aduh_mon_1
- coe_clk_export_from_the_ram_aduh_mon_1 => OPEN,
- coe_reset_export_from_the_ram_aduh_mon_1 => OPEN,
- coe_address_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).rd,
- coe_readdata_export_to_the_ram_aduh_mon_1 => ram_mon_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).wr,
- coe_writedata_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_aduh_mon_2
- coe_clk_export_from_the_ram_aduh_mon_2 => OPEN,
- coe_reset_export_from_the_ram_aduh_mon_2 => OPEN,
- coe_address_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).rd,
- coe_readdata_export_to_the_ram_aduh_mon_2 => ram_mon_miso_arr(2).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).wr,
- coe_writedata_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_aduh_mon_3
- coe_clk_export_from_the_ram_aduh_mon_3 => OPEN,
- coe_reset_export_from_the_ram_aduh_mon_3 => OPEN,
- coe_address_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).rd,
- coe_readdata_export_to_the_ram_aduh_mon_3 => ram_mon_miso_arr(3).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).wr,
- coe_writedata_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_adu_i2c_commander_ab
- coe_clk_export_from_the_reg_adu_i2c_commander_ab => OPEN,
- coe_reset_export_from_the_reg_adu_i2c_commander_ab => OPEN,
- coe_address_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_i2c_commander_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).rd,
- coe_readdata_export_to_the_reg_adu_i2c_commander_ab => reg_commander_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).wr,
- coe_writedata_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_adu_i2c_commander_cd
- coe_clk_export_from_the_reg_adu_i2c_commander_cd => OPEN,
- coe_reset_export_from_the_reg_adu_i2c_commander_cd => OPEN,
- coe_address_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_i2c_commander_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).rd,
- coe_readdata_export_to_the_reg_adu_i2c_commander_cd => reg_commander_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).wr,
- coe_writedata_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_adu_i2c_protocol_ab
- coe_clk_export_from_the_ram_adu_i2c_protocol_ab => OPEN,
- coe_reset_export_from_the_ram_adu_i2c_protocol_ab => OPEN,
- coe_address_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_protocol_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).rd,
- coe_readdata_export_to_the_ram_adu_i2c_protocol_ab => ram_protocol_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).wr,
- coe_writedata_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_adu_i2c_protocol_cd
- coe_clk_export_from_the_ram_adu_i2c_protocol_cd => OPEN,
- coe_reset_export_from_the_ram_adu_i2c_protocol_cd => OPEN,
- coe_address_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_protocol_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).rd,
- coe_readdata_export_to_the_ram_adu_i2c_protocol_cd => ram_protocol_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).wr,
- coe_writedata_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_adu_i2c_result_ab
- coe_clk_export_from_the_ram_adu_i2c_result_ab => OPEN,
- coe_reset_export_from_the_ram_adu_i2c_result_ab => OPEN,
- coe_address_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_result_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).rd,
- coe_readdata_export_to_the_ram_adu_i2c_result_ab => ram_result_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).wr,
- coe_writedata_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_adu_i2c_result_cd
- coe_clk_export_from_the_ram_adu_i2c_result_cd => OPEN,
- coe_reset_export_from_the_ram_adu_i2c_result_cd => OPEN,
- coe_address_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_result_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).rd,
- coe_readdata_export_to_the_ram_adu_i2c_result_cd => ram_result_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).wr,
- coe_writedata_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_scheduler_sp_on
- coe_clk_export_from_the_reg_bsn_scheduler_sp_on => OPEN,
- coe_reset_export_from_the_reg_bsn_scheduler_sp_on => OPEN,
- coe_address_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.address(0),
- coe_read_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_scheduler_sp_off
- coe_clk_export_from_the_reg_bsn_scheduler_sp_off => OPEN,
- coe_reset_export_from_the_reg_bsn_scheduler_sp_off => OPEN,
- coe_address_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.address(0),
- coe_read_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => pout_debug_wave,
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ -- 1) global signals:
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => mm_clk, -- PLL clk[0] = 50 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => OPEN, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_source
+ coe_clk_export_from_the_reg_bsn_source => OPEN,
+ coe_reset_export_from_the_reg_bsn_source => OPEN,
+ coe_address_export_from_the_reg_bsn_source => reg_bsn_source_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_source_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_bsn_source => reg_bsn_source_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_source => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_bsn_source => reg_bsn_source_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_source => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_scheduler_wg
+ coe_clk_export_from_the_reg_bsn_scheduler_wg => OPEN,
+ coe_reset_export_from_the_reg_bsn_scheduler_wg => OPEN,
+ coe_address_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.address(0), -- reg_bsn_scheduler_adr_w = 1
+ coe_read_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_adc_quad
+ coe_clk_export_from_the_reg_adc_quad => OPEN,
+ coe_reset_export_from_the_reg_adc_quad => OPEN,
+ coe_address_export_from_the_reg_adc_quad => reg_adc_quad_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_adc_quad_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_adc_quad => reg_adc_quad_mosi.rd,
+ coe_readdata_export_to_the_reg_adc_quad => reg_adc_quad_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_adc_quad => reg_adc_quad_mosi.wr,
+ coe_writedata_export_from_the_reg_adc_quad => reg_adc_quad_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_wg_0
+ coe_clk_export_from_the_reg_diag_wg_0 => OPEN,
+ coe_reset_export_from_the_reg_diag_wg_0 => OPEN,
+ coe_address_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).rd,
+ coe_readdata_export_to_the_reg_diag_wg_0 => reg_wg_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).wr,
+ coe_writedata_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_wg_1
+ coe_clk_export_from_the_reg_diag_wg_1 => OPEN,
+ coe_reset_export_from_the_reg_diag_wg_1 => OPEN,
+ coe_address_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).rd,
+ coe_readdata_export_to_the_reg_diag_wg_1 => reg_wg_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).wr,
+ coe_writedata_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_wg_2
+ coe_clk_export_from_the_reg_diag_wg_2 => OPEN,
+ coe_reset_export_from_the_reg_diag_wg_2 => OPEN,
+ coe_address_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).rd,
+ coe_readdata_export_to_the_reg_diag_wg_2 => reg_wg_miso_arr(2).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).wr,
+ coe_writedata_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_wg_3
+ coe_clk_export_from_the_reg_diag_wg_3 => OPEN,
+ coe_reset_export_from_the_reg_diag_wg_3 => OPEN,
+ coe_address_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).rd,
+ coe_readdata_export_to_the_reg_diag_wg_3 => reg_wg_miso_arr(3).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).wr,
+ coe_writedata_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_wg_0
+ coe_clk_export_from_the_ram_diag_wg_0 => OPEN,
+ coe_reset_export_from_the_ram_diag_wg_0 => OPEN,
+ coe_address_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).rd,
+ coe_readdata_export_to_the_ram_diag_wg_0 => ram_wg_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).wr,
+ coe_writedata_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_wg_1
+ coe_clk_export_from_the_ram_diag_wg_1 => OPEN,
+ coe_reset_export_from_the_ram_diag_wg_1 => OPEN,
+ coe_address_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).rd,
+ coe_readdata_export_to_the_ram_diag_wg_1 => ram_wg_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).wr,
+ coe_writedata_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_wg_2
+ coe_clk_export_from_the_ram_diag_wg_2 => OPEN,
+ coe_reset_export_from_the_ram_diag_wg_2 => OPEN,
+ coe_address_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).rd,
+ coe_readdata_export_to_the_ram_diag_wg_2 => ram_wg_miso_arr(2).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).wr,
+ coe_writedata_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_wg_3
+ coe_clk_export_from_the_ram_diag_wg_3 => OPEN,
+ coe_reset_export_from_the_ram_diag_wg_3 => OPEN,
+ coe_address_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).rd,
+ coe_readdata_export_to_the_ram_diag_wg_3 => ram_wg_miso_arr(3).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).wr,
+ coe_writedata_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dp_shiftram
+ coe_clk_export_from_the_reg_dp_shiftram => OPEN,
+ coe_reset_export_from_the_reg_dp_shiftram => OPEN,
+ coe_address_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.address(c_reg_dp_shiftram_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.rd,
+ coe_readdata_export_to_the_reg_dp_shiftram => reg_dp_shiftram_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.wr,
+ coe_writedata_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_aduh_mon_0
+ coe_clk_export_from_the_reg_aduh_mon_0 => OPEN,
+ coe_reset_export_from_the_reg_aduh_mon_0 => OPEN,
+ coe_address_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).rd,
+ coe_readdata_export_to_the_reg_aduh_mon_0 => reg_mon_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).wr,
+ coe_writedata_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_aduh_mon_1
+ coe_clk_export_from_the_reg_aduh_mon_1 => OPEN,
+ coe_reset_export_from_the_reg_aduh_mon_1 => OPEN,
+ coe_address_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).rd,
+ coe_readdata_export_to_the_reg_aduh_mon_1 => reg_mon_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).wr,
+ coe_writedata_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_aduh_mon_2
+ coe_clk_export_from_the_reg_aduh_mon_2 => OPEN,
+ coe_reset_export_from_the_reg_aduh_mon_2 => OPEN,
+ coe_address_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).rd,
+ coe_readdata_export_to_the_reg_aduh_mon_2 => reg_mon_miso_arr(2).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).wr,
+ coe_writedata_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_aduh_mon_3
+ coe_clk_export_from_the_reg_aduh_mon_3 => OPEN,
+ coe_reset_export_from_the_reg_aduh_mon_3 => OPEN,
+ coe_address_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).rd,
+ coe_readdata_export_to_the_reg_aduh_mon_3 => reg_mon_miso_arr(3).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).wr,
+ coe_writedata_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_aduh_mon_0
+ coe_clk_export_from_the_ram_aduh_mon_0 => OPEN,
+ coe_reset_export_from_the_ram_aduh_mon_0 => OPEN,
+ coe_address_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).rd,
+ coe_readdata_export_to_the_ram_aduh_mon_0 => ram_mon_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).wr,
+ coe_writedata_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_aduh_mon_1
+ coe_clk_export_from_the_ram_aduh_mon_1 => OPEN,
+ coe_reset_export_from_the_ram_aduh_mon_1 => OPEN,
+ coe_address_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).rd,
+ coe_readdata_export_to_the_ram_aduh_mon_1 => ram_mon_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).wr,
+ coe_writedata_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_aduh_mon_2
+ coe_clk_export_from_the_ram_aduh_mon_2 => OPEN,
+ coe_reset_export_from_the_ram_aduh_mon_2 => OPEN,
+ coe_address_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).rd,
+ coe_readdata_export_to_the_ram_aduh_mon_2 => ram_mon_miso_arr(2).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).wr,
+ coe_writedata_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_aduh_mon_3
+ coe_clk_export_from_the_ram_aduh_mon_3 => OPEN,
+ coe_reset_export_from_the_ram_aduh_mon_3 => OPEN,
+ coe_address_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).rd,
+ coe_readdata_export_to_the_ram_aduh_mon_3 => ram_mon_miso_arr(3).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).wr,
+ coe_writedata_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_adu_i2c_commander_ab
+ coe_clk_export_from_the_reg_adu_i2c_commander_ab => OPEN,
+ coe_reset_export_from_the_reg_adu_i2c_commander_ab => OPEN,
+ coe_address_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_i2c_commander_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).rd,
+ coe_readdata_export_to_the_reg_adu_i2c_commander_ab => reg_commander_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).wr,
+ coe_writedata_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_adu_i2c_commander_cd
+ coe_clk_export_from_the_reg_adu_i2c_commander_cd => OPEN,
+ coe_reset_export_from_the_reg_adu_i2c_commander_cd => OPEN,
+ coe_address_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_i2c_commander_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).rd,
+ coe_readdata_export_to_the_reg_adu_i2c_commander_cd => reg_commander_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).wr,
+ coe_writedata_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_adu_i2c_protocol_ab
+ coe_clk_export_from_the_ram_adu_i2c_protocol_ab => OPEN,
+ coe_reset_export_from_the_ram_adu_i2c_protocol_ab => OPEN,
+ coe_address_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_protocol_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).rd,
+ coe_readdata_export_to_the_ram_adu_i2c_protocol_ab => ram_protocol_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).wr,
+ coe_writedata_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_adu_i2c_protocol_cd
+ coe_clk_export_from_the_ram_adu_i2c_protocol_cd => OPEN,
+ coe_reset_export_from_the_ram_adu_i2c_protocol_cd => OPEN,
+ coe_address_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_protocol_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).rd,
+ coe_readdata_export_to_the_ram_adu_i2c_protocol_cd => ram_protocol_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).wr,
+ coe_writedata_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_adu_i2c_result_ab
+ coe_clk_export_from_the_ram_adu_i2c_result_ab => OPEN,
+ coe_reset_export_from_the_ram_adu_i2c_result_ab => OPEN,
+ coe_address_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_result_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).rd,
+ coe_readdata_export_to_the_ram_adu_i2c_result_ab => ram_result_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).wr,
+ coe_writedata_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_adu_i2c_result_cd
+ coe_clk_export_from_the_ram_adu_i2c_result_cd => OPEN,
+ coe_reset_export_from_the_ram_adu_i2c_result_cd => OPEN,
+ coe_address_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_result_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).rd,
+ coe_readdata_export_to_the_ram_adu_i2c_result_cd => ram_result_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).wr,
+ coe_writedata_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_scheduler_sp_on
+ coe_clk_export_from_the_reg_bsn_scheduler_sp_on => OPEN,
+ coe_reset_export_from_the_reg_bsn_scheduler_sp_on => OPEN,
+ coe_address_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.address(0),
+ coe_read_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_scheduler_sp_off
+ coe_clk_export_from_the_reg_bsn_scheduler_sp_off => OPEN,
+ coe_reset_export_from_the_reg_bsn_scheduler_sp_off => OPEN,
+ coe_address_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.address(0),
+ coe_read_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => pout_debug_wave,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
--- u_ctrl : ENTITY unb_common_lib.ctrl_unb_common
--- GENERIC MAP (
--- -- General
--- g_sim => g_sim,
--- g_design_name => g_design_name,
--- g_fw_version => g_fw_version,
--- g_stamp_date => g_stamp_date,
--- g_stamp_time => g_stamp_time,
--- g_stamp_svn => g_stamp_svn,
--- g_design_note => g_design_note,
--- g_mm_clk_freq => g_bn_capture.mm_clk_freq, -- must match PLL setting in sopc_bn_capture
--- g_dp_clk_freq => g_bn_capture.dp_clk_freq,
--- g_dp_phs_clk_vec_w => g_nof_dp_phs_clk,
--- -- Use PHY Interface
--- g_use_phy => g_use_phy,
--- -- Auxiliary Interface
--- g_aux => g_aux
--- )
+ -- u_ctrl : ENTITY unb_common_lib.ctrl_unb_common
+ -- GENERIC MAP (
+ -- -- General
+ -- g_sim => g_sim,
+ -- g_design_name => g_design_name,
+ -- g_fw_version => g_fw_version,
+ -- g_stamp_date => g_stamp_date,
+ -- g_stamp_time => g_stamp_time,
+ -- g_stamp_svn => g_stamp_svn,
+ -- g_design_note => g_design_note,
+ -- g_mm_clk_freq => g_bn_capture.mm_clk_freq, -- must match PLL setting in sopc_bn_capture
+ -- g_dp_clk_freq => g_bn_capture.dp_clk_freq,
+ -- g_dp_phs_clk_vec_w => g_nof_dp_phs_clk,
+ -- -- Use PHY Interface
+ -- g_use_phy => g_use_phy,
+ -- -- Auxiliary Interface
+ -- g_aux => g_aux
+ -- )
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_dp_phs_clk_vec_w => c_nof_dp_phs_clk,
- g_dp_clk_use_pll => c_dp_clk_use_pll,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux
- )
- port map (
- -- System
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec, -- divided and phase shifted dp_clk
-
- this_chip_id => this_chip_id,
-
- -- PIOs
- pout_debug_wave => pout_debug_wave,
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- ppsh
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_dp_phs_clk_vec_w => c_nof_dp_phs_clk,
+ g_dp_clk_use_pll => c_dp_clk_use_pll,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- System
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec, -- divided and phase shifted dp_clk
+
+ this_chip_id => this_chip_id,
+
+ -- PIOs
+ pout_debug_wave => pout_debug_wave,
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- ppsh
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- Specific node function
-----------------------------------------------------------------------------
u_node : entity work.node_unb1_bn_capture
- generic map (
- -- General
- g_sim => g_sim,
- -- BN capture specific
- g_bn_capture => c_bn_capture,
- -- Use PHY Interface
- g_use_phy => c_use_phy,
- -- Auxiliary Interface
- g_aux => c_unb1_board_aux,
- -- ADC Interface
- g_nof_dp_phs_clk => c_nof_dp_phs_clk,
- g_ai => c_ai
- )
- port map (
- --
- -- >>> SOPC system with conduit peripheral MM bus
- --
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec,
- dp_pps => dp_pps,
-
- ext_clk => CLK,
-
- -- MM bsn source
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
-
- -- MM bsn schedule WG
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
-
- -- MM aduh quad
- reg_adc_quad_mosi => reg_adc_quad_mosi,
- reg_adc_quad_miso => reg_adc_quad_miso,
-
- -- MM wideband waveform generator registers [0,1,2,3] for signal paths [A,B,C,D]
- reg_wg_mosi_arr => reg_wg_mosi_arr,
- reg_wg_miso_arr => reg_wg_miso_arr,
- ram_wg_mosi_arr => ram_wg_mosi_arr,
- ram_wg_miso_arr => ram_wg_miso_arr,
-
- -- MM DP shiftram
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
-
- -- MM signal path monitors for [A, B, C, D]
- reg_mon_mosi_arr => reg_mon_mosi_arr,
- reg_mon_miso_arr => reg_mon_miso_arr,
- ram_mon_mosi_arr => ram_mon_mosi_arr,
- ram_mon_miso_arr => ram_mon_miso_arr,
-
- -- MM registers [0,1] for I2C access with ADUs [AB,CD]
- reg_commander_mosi_arr => reg_commander_mosi_arr,
- reg_commander_miso_arr => reg_commander_miso_arr,
- ram_protocol_mosi_arr => ram_protocol_mosi_arr,
- ram_protocol_miso_arr => ram_protocol_miso_arr,
- ram_result_mosi_arr => ram_result_mosi_arr,
- ram_result_miso_arr => ram_result_miso_arr,
-
- -- MM registers to enable and disable signal path
- reg_bsn_scheduler_sp_on_mosi => reg_bsn_scheduler_sp_on_mosi,
- reg_bsn_scheduler_sp_on_miso => reg_bsn_scheduler_sp_on_miso,
- reg_bsn_scheduler_sp_off_mosi => reg_bsn_scheduler_sp_off_mosi,
- reg_bsn_scheduler_sp_off_miso => reg_bsn_scheduler_sp_off_miso,
- --
- -- >>> Node FPGA pins
- --
- -- ADC Interface
- ADC_BI_A => ADC_BI_A,
- ADC_BI_B => ADC_BI_B,
- ADC_BI_A_CLK => ADC_BI_A_CLK,
- ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST,
- ADC_BI_C => ADC_BI_C,
- ADC_BI_D => ADC_BI_D,
- ADC_BI_D_CLK => ADC_BI_D_CLK,
- ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
- ADC_AB_SCL => ADC_AB_SCL, -- I2C AB
- ADC_AB_SDA => ADC_AB_SDA,
- ADC_CD_SCL => ADC_CD_SCL, -- I2C CD
- ADC_CD_SDA => ADC_CD_SDA
- );
+ generic map (
+ -- General
+ g_sim => g_sim,
+ -- BN capture specific
+ g_bn_capture => c_bn_capture,
+ -- Use PHY Interface
+ g_use_phy => c_use_phy,
+ -- Auxiliary Interface
+ g_aux => c_unb1_board_aux,
+ -- ADC Interface
+ g_nof_dp_phs_clk => c_nof_dp_phs_clk,
+ g_ai => c_ai
+ )
+ port map (
+ --
+ -- >>> SOPC system with conduit peripheral MM bus
+ --
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec,
+ dp_pps => dp_pps,
+
+ ext_clk => CLK,
+
+ -- MM bsn source
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+
+ -- MM bsn schedule WG
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- MM aduh quad
+ reg_adc_quad_mosi => reg_adc_quad_mosi,
+ reg_adc_quad_miso => reg_adc_quad_miso,
+
+ -- MM wideband waveform generator registers [0,1,2,3] for signal paths [A,B,C,D]
+ reg_wg_mosi_arr => reg_wg_mosi_arr,
+ reg_wg_miso_arr => reg_wg_miso_arr,
+ ram_wg_mosi_arr => ram_wg_mosi_arr,
+ ram_wg_miso_arr => ram_wg_miso_arr,
+
+ -- MM DP shiftram
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+
+ -- MM signal path monitors for [A, B, C, D]
+ reg_mon_mosi_arr => reg_mon_mosi_arr,
+ reg_mon_miso_arr => reg_mon_miso_arr,
+ ram_mon_mosi_arr => ram_mon_mosi_arr,
+ ram_mon_miso_arr => ram_mon_miso_arr,
+
+ -- MM registers [0,1] for I2C access with ADUs [AB,CD]
+ reg_commander_mosi_arr => reg_commander_mosi_arr,
+ reg_commander_miso_arr => reg_commander_miso_arr,
+ ram_protocol_mosi_arr => ram_protocol_mosi_arr,
+ ram_protocol_miso_arr => ram_protocol_miso_arr,
+ ram_result_mosi_arr => ram_result_mosi_arr,
+ ram_result_miso_arr => ram_result_miso_arr,
+
+ -- MM registers to enable and disable signal path
+ reg_bsn_scheduler_sp_on_mosi => reg_bsn_scheduler_sp_on_mosi,
+ reg_bsn_scheduler_sp_on_miso => reg_bsn_scheduler_sp_on_miso,
+ reg_bsn_scheduler_sp_off_mosi => reg_bsn_scheduler_sp_off_mosi,
+ reg_bsn_scheduler_sp_off_miso => reg_bsn_scheduler_sp_off_miso,
+ --
+ -- >>> Node FPGA pins
+ --
+ -- ADC Interface
+ ADC_BI_A => ADC_BI_A,
+ ADC_BI_B => ADC_BI_B,
+ ADC_BI_A_CLK => ADC_BI_A_CLK,
+ ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST,
+ ADC_BI_C => ADC_BI_C,
+ ADC_BI_D => ADC_BI_D,
+ ADC_BI_D_CLK => ADC_BI_D_CLK,
+ ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
+ ADC_AB_SCL => ADC_AB_SCL, -- I2C AB
+ ADC_AB_SDA => ADC_AB_SDA,
+ ADC_CD_SCL => ADC_CD_SCL, -- I2C CD
+ ADC_CD_SDA => ADC_CD_SDA
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
index 79c2b14005..e78436e54e 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
@@ -22,17 +22,17 @@
-- Purpose: Capture input from two ADU or use WG data and attach timestamp.
library IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, ppsh_lib, aduh_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.unb1_bn_capture_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.unb1_bn_capture_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
entity unb1_bn_capture_input is
generic (
@@ -145,82 +145,82 @@ begin
use_adc : if g_use_phy.adc /= 0 generate
u_aduh_quad : entity aduh_lib.mms_aduh_quad
- generic map (
- -- General
- g_sim => g_sim,
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- -- ADC Interface
- g_nof_dp_phs_clk => g_nof_dp_phs_clk,
- g_ai => g_ai
- )
- port map (
- -- ADC Interface
- -- . ADU_AB
- ADC_BI_A => ADC_BI_A,
- ADC_BI_B => ADC_BI_B,
- ADC_BI_A_CLK => ADC_BI_A_CLK, -- lvds clock from ADU_AB
- ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST, -- release synchronises ADU_AB DCLK divider
-
- -- . ADU_CD
- ADC_BI_C => ADC_BI_C,
- ADC_BI_D => ADC_BI_D,
- ADC_BI_D_CLK => ADC_BI_D_CLK, -- lvds clock from ADU_CD
- ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST, -- release synchronises ADU_CD DCLK divider
-
- -- MM clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_adc_quad_mosi,
- reg_miso => reg_adc_quad_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec,
-
- -- . data
- aduh_sosi_arr => aduh_sosi_arr
- );
+ generic map (
+ -- General
+ g_sim => g_sim,
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ -- ADC Interface
+ g_nof_dp_phs_clk => g_nof_dp_phs_clk,
+ g_ai => g_ai
+ )
+ port map (
+ -- ADC Interface
+ -- . ADU_AB
+ ADC_BI_A => ADC_BI_A,
+ ADC_BI_B => ADC_BI_B,
+ ADC_BI_A_CLK => ADC_BI_A_CLK, -- lvds clock from ADU_AB
+ ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST, -- release synchronises ADU_AB DCLK divider
+
+ -- . ADU_CD
+ ADC_BI_C => ADC_BI_C,
+ ADC_BI_D => ADC_BI_D,
+ ADC_BI_D_CLK => ADC_BI_D_CLK, -- lvds clock from ADU_CD
+ ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST, -- release synchronises ADU_CD DCLK divider
+
+ -- MM clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_adc_quad_mosi,
+ reg_miso => reg_adc_quad_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec,
+
+ -- . data
+ aduh_sosi_arr => aduh_sosi_arr
+ );
end generate;
gen_wg : for I in 0 to g_ai.nof_sp - 1 generate
u_sp : entity diag_lib.mms_diag_wg_wideband
- generic map (
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- g_buf_dir => c_wg_buf_directory,
-
- -- Wideband parameters
- g_wideband_factor => c_wideband_factor,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => c_wg_buf_dat_w,
- g_buf_addr_w => c_wg_buf_addr_w,
- g_calc_support => true,
- g_calc_gain_w => 1,
- g_calc_dat_w => c_wg_buf_dat_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_wg_mosi_arr(I),
- reg_miso => reg_wg_miso_arr(I),
-
- buf_mosi => ram_wg_mosi_arr(I),
- buf_miso => ram_wg_miso_arr(I),
-
- -- Streaming clock domain
- st_rst => dp_rst,
- st_clk => dp_clk,
- st_restart => dp_bsn_trigger_wg,
-
- out_ovr => wg_ovr( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ),
- out_dat => wg_dat( (I + 1) * c_wideband_factor * c_wg_buf_dat_w - 1 downto I * c_wideband_factor * c_wg_buf_dat_w),
- out_val => wg_val( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ),
- out_sync => wg_sync((I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor )
- );
+ generic map (
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ g_buf_dir => c_wg_buf_directory,
+
+ -- Wideband parameters
+ g_wideband_factor => c_wideband_factor,
+
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => c_wg_buf_dat_w,
+ g_buf_addr_w => c_wg_buf_addr_w,
+ g_calc_support => true,
+ g_calc_gain_w => 1,
+ g_calc_dat_w => c_wg_buf_dat_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_wg_mosi_arr(I),
+ reg_miso => reg_wg_miso_arr(I),
+
+ buf_mosi => ram_wg_mosi_arr(I),
+ buf_miso => ram_wg_miso_arr(I),
+
+ -- Streaming clock domain
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+ st_restart => dp_bsn_trigger_wg,
+
+ out_ovr => wg_ovr( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ),
+ out_dat => wg_dat( (I + 1) * c_wideband_factor * c_wg_buf_dat_w - 1 downto I * c_wideband_factor * c_wg_buf_dat_w),
+ out_val => wg_val( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ),
+ out_sync => wg_sync((I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor )
+ );
-- wires
-- . all wideband samples will be valid in parallel, so using vector_or() or vector_and() is fine
@@ -229,7 +229,7 @@ begin
wg_sosi_arr(I).valid <= vector_or(wg_val( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ));
wg_sosi_arr(I).sync <= vector_or(wg_sync((I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ));
wg_sosi_arr(I).err <= TO_DP_ERROR(c_unb1_board_ok) when
- vector_or(wg_ovr( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor )) = '0' else
+ vector_or(wg_ovr( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor )) = '0' else
TO_DP_ERROR(2**c_unb1_board_error_adc_bi); -- pass ADC or WG overflow info on as an error signal
end generate;
@@ -273,75 +273,75 @@ begin
-- is ensured by g_use_sync_in=TRUE and bs_sosi.sync.
-----------------------------------------------------------------------------
u_dp_shiftram : entity dp_lib.dp_shiftram
- generic map (
- g_nof_streams => g_ai.nof_sp, -- 4 signal paths
- g_nof_words => 2048,
- g_data_w => c_wideband_factor * g_ai.port_w, -- 4 concatenated timesamples
- g_use_sync_in => true
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_nof_streams => g_ai.nof_sp, -- 4 signal paths
+ g_nof_words => 2048,
+ g_data_w => c_wideband_factor * g_ai.port_w, -- 4 concatenated timesamples
+ g_use_sync_in => true
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- sync_in => bs_sosi.sync,
+ sync_in => bs_sosi.sync,
- reg_mosi => reg_dp_shiftram_mosi,
- reg_miso => reg_dp_shiftram_miso,
+ reg_mosi => reg_dp_shiftram_mosi,
+ reg_miso => reg_dp_shiftram_miso,
- snk_in_arr => func_dp_stream_arr_reverse_range(mux_sosi_arr),
+ snk_in_arr => func_dp_stream_arr_reverse_range(mux_sosi_arr),
- func_dp_stream_arr_reverse_range(src_out_arr) => dp_shiftram_src_out_arr
- );
+ func_dp_stream_arr_reverse_range(src_out_arr) => dp_shiftram_src_out_arr
+ );
-----------------------------------------------------------------------------
-- Timestamp
-----------------------------------------------------------------------------
u_bsn_sosi : entity dp_lib.mms_dp_bsn_source
- generic map (
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- g_block_size => c_bs_block_size,
- g_nof_block_per_sync => c_bs_nof_block_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_mosi,
- reg_miso => reg_bsn_source_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi
- );
+ generic map (
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ g_block_size => c_bs_block_size,
+ g_nof_block_per_sync => c_bs_nof_block_per_sync,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_bsn_source_mosi,
+ reg_miso => reg_bsn_source_miso,
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi
+ );
u_bsn_trigger_wg : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_miso => reg_bsn_scheduler_wg_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
- trigger_out => dp_bsn_trigger_wg
- );
+ generic map (
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ trigger_out => dp_bsn_trigger_wg
+ );
gen_sosi_ctrl : for I in 0 to g_ai.nof_sp - 1 generate
p_sosi : process(dp_shiftram_src_out_arr, bs_sosi)
@@ -366,17 +366,17 @@ begin
-----------------------------------------------------------------------------
gen_sp_siso_rdy : for I in 0 to g_ai.nof_sp - 1 generate
u_dp_ready : entity dp_lib.dp_ready
- generic map (
- g_ready_latency => 1
+ generic map (
+ g_ready_latency => 1
)
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- snk_in => dp_shiftram_src_out_timestamped_arr(I),
+ snk_in => dp_shiftram_src_out_timestamped_arr(I),
- src_out => sp_sosi_arr(I),
- src_in => sp_siso_arr(I)
+ src_out => sp_sosi_arr(I),
+ src_in => sp_siso_arr(I)
);
end generate;
@@ -385,42 +385,42 @@ begin
-----------------------------------------------------------------------------
gen_mon : for I in 0 to g_ai.nof_sp - 1 generate
u_sp : entity aduh_lib.mms_aduh_monitor
- generic map (
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- g_symbol_w => g_ai.port_w,
- g_nof_symbols_per_data => c_wideband_factor, -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
- g_nof_accumulations => g_bn_capture.sp.nof_samples_per_sync, -- integration time in symbols, defines internal accumulator widths
- g_buffer_nof_symbols => g_bn_capture.sp.monitor_buffer_nof_samples,
- g_buffer_use_sync => g_bn_capture.sp.monitor_buffer_use_sync
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ g_symbol_w => g_ai.port_w,
+ g_nof_symbols_per_data => c_wideband_factor, -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_accumulations => g_bn_capture.sp.nof_samples_per_sync, -- integration time in symbols, defines internal accumulator widths
+ g_buffer_nof_symbols => g_bn_capture.sp.monitor_buffer_nof_samples,
+ g_buffer_use_sync => g_bn_capture.sp.monitor_buffer_use_sync
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_mon_mosi_arr(I), -- read only access to the signal path data mean sum and power sum registers
- reg_miso => reg_mon_miso_arr(I),
- buf_mosi => ram_mon_mosi_arr(I), -- read and overwrite access to the signal path data buffers
- buf_miso => ram_mon_miso_arr(I),
+ reg_mosi => reg_mon_mosi_arr(I), -- read only access to the signal path data mean sum and power sum registers
+ reg_miso => reg_mon_miso_arr(I),
+ buf_mosi => ram_mon_mosi_arr(I), -- read and overwrite access to the signal path data buffers
+ buf_miso => ram_mon_miso_arr(I),
- -- Streaming clock domain
- st_rst => dp_rst,
- st_clk => dp_clk,
+ -- Streaming clock domain
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- in_sosi => dp_shiftram_src_out_timestamped_arr(I)
- );
+ in_sosi => dp_shiftram_src_out_timestamped_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
-- Scope monitor for Wave Window
-----------------------------------------------------------------------------
u_quad_scope : entity aduh_lib.aduh_quad_scope
- generic map (
- g_sim => g_sim,
- g_ai => g_ai
- )
- port map (
- DCLK => dp_clk,
- sp_sosi_arr => dp_shiftram_src_out_timestamped_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_ai => g_ai
+ )
+ port map (
+ DCLK => dp_clk,
+ sp_sosi_arr => dp_shiftram_src_out_timestamped_arr
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
index c6706e2421..cce61474f6 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
@@ -22,10 +22,10 @@
-- Purpose: Multiplex the 4 signal streams into 1 wide stream
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity bn_capture_mux is
generic (
@@ -43,69 +43,69 @@ entity bn_capture_mux is
-- ST sinks (input signal paths)
in_siso_arr : out t_dp_siso_arr(0 to g_nof_input - 1);
in_sosi_arr : in t_dp_sosi_arr(0 to g_nof_input - 1); -- = [0:3] = Signal Paths [A[31:0], B[31:0], C[31:0], D[31:0]]
- -- and e.g. A[31:0] = [A(t0), A(t1), A(t2), A(t3)], so 4 8b samples in time per one 32b word
+ -- and e.g. A[31:0] = [A(t0), A(t1), A(t2), A(t3)], so 4 8b samples in time per one 32b word
-- ST source (multiplexed output signal paths)
mux_wide_siso : in t_dp_siso := c_dp_siso_rdy;
mux_wide_sosi : out t_dp_sosi -- = Signal Paths A[255:0], B[255:0], C[255:0], D[255:0] multiplexed in time
- -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 8b samples in time per one 256b word
+ -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 8b samples in time per one 256b word
);
end bn_capture_mux;
architecture str of bn_capture_mux is
signal wide_siso_arr : t_dp_siso_arr(0 to g_nof_input - 1);
signal wide_sosi_arr : t_dp_sosi_arr(0 to g_nof_input - 1); -- = [0:3] = Signal Paths [A,B,C,D]
- -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 800M samples in time per one 256b word
+ -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 800M samples in time per one 256b word
begin
gen_fifo : for I in 0 to g_nof_input - 1 generate
u_n2w : entity dp_lib.dp_fifo_dc_mixed_widths
+ generic map (
+ g_wr_data_w => g_in_data_w,
+ g_rd_data_w => g_mux_data_w,
+ g_use_ctrl => true,
+ g_wr_fifo_size => g_in_fifo_size,
+ g_rd_fifo_rl => 1
+ )
+ port map (
+ wr_rst => in_rst,
+ wr_clk => in_clk,
+ rd_rst => mux_wide_rst,
+ rd_clk => mux_wide_clk,
+ -- ST sink
+ snk_out => in_siso_arr(I),
+ snk_in => in_sosi_arr(I),
+ -- Monitor FIFO filling
+ wr_usedw => OPEN,
+ rd_usedw => OPEN,
+ rd_emp => OPEN,
+ -- ST source
+ src_in => wide_siso_arr(I),
+ src_out => wide_sosi_arr(I)
+ );
+ end generate;
+
+ gen_mux : entity dp_lib.dp_mux
generic map (
- g_wr_data_w => g_in_data_w,
- g_rd_data_w => g_mux_data_w,
- g_use_ctrl => true,
- g_wr_fifo_size => g_in_fifo_size,
- g_rd_fifo_rl => 1
+ g_data_w => g_mux_data_w,
+ g_empty_w => 1,
+ g_in_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_in_channel => false,
+ g_use_error => false,
+ g_mode => 1,
+ g_nof_input => g_nof_input,
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_nof_input), -- dummy value must match g_nof_input
+ g_fifo_fill => array_init( 0, g_nof_input) -- dummy value must match g_nof_input
)
port map (
- wr_rst => in_rst,
- wr_clk => in_clk,
- rd_rst => mux_wide_rst,
- rd_clk => mux_wide_clk,
- -- ST sink
- snk_out => in_siso_arr(I),
- snk_in => in_sosi_arr(I),
- -- Monitor FIFO filling
- wr_usedw => OPEN,
- rd_usedw => OPEN,
- rd_emp => OPEN,
+ rst => mux_wide_rst,
+ clk => mux_wide_clk,
+ -- ST sinks
+ snk_out_arr => wide_siso_arr,
+ snk_in_arr => wide_sosi_arr,
-- ST source
- src_in => wide_siso_arr(I),
- src_out => wide_sosi_arr(I)
+ src_in => mux_wide_siso,
+ src_out => mux_wide_sosi
);
- end generate;
-
- gen_mux : entity dp_lib.dp_mux
- generic map (
- g_data_w => g_mux_data_w,
- g_empty_w => 1,
- g_in_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_in_channel => false,
- g_use_error => false,
- g_mode => 1,
- g_nof_input => g_nof_input,
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_input), -- dummy value must match g_nof_input
- g_fifo_fill => array_init( 0, g_nof_input) -- dummy value must match g_nof_input
- )
- port map (
- rst => mux_wide_rst,
- clk => mux_wide_clk,
- -- ST sinks
- snk_out_arr => wide_siso_arr,
- snk_in_arr => wide_sosi_arr,
- -- ST source
- src_in => mux_wide_siso,
- src_out => mux_wide_sosi
- );
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
index ced8c5739b..b42901526b 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
package unb1_bn_capture_pkg is
-- Signal path input
@@ -46,9 +46,10 @@ package unb1_bn_capture_pkg is
sp : t_c_bn_capture_sp;
end record;
- constant c_bn_capture : t_c_bn_capture := (c_unb1_board_mm_clk_freq_50M, -- must match PLL setting in sopc_bn_capture
- c_unb1_board_ext_clk_freq_200M,
- c_bn_capture_sp);
+ constant c_bn_capture : t_c_bn_capture := (
+ c_unb1_board_mm_clk_freq_50M, -- must match PLL setting in sopc_bn_capture
+ c_unb1_board_ext_clk_freq_200M,
+ c_bn_capture_sp);
end unb1_bn_capture_pkg;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
index 97a864cc1c..2ea77e1042 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
@@ -22,12 +22,12 @@
-- Purpose: Store the 4 multiplexed signal streams into one DDR3 and readback
library IEEE, common_lib, unb_common_lib, dp_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity bn_capture_storage is
generic (
@@ -57,7 +57,7 @@ entity bn_capture_storage is
-- ST sink (multiplexed input signal paths)
mux_wide_siso : out t_dp_siso := c_dp_siso_rdy;
mux_wide_sosi : in t_dp_sosi; -- = Signal Paths A[255:0], B[255:0], C[255:0], D[255:0] multiplexed in time
- -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 8b samples in time per one 256b word
+ -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 8b samples in time per one 256b word
-- MM registers
ctrl_mosi : in t_mem_mosi := c_mem_mosi_rst;
ctrl_miso : out t_mem_miso;
@@ -110,56 +110,56 @@ begin
phy_rst <= i_phy_rst;
u_ddr3 : entity ddr3_lib.ddr3
- generic map(
- g_sim => g_sim,
- g_phy => 0,
- g_ddr => g_ddr,
- g_mts => 800,
- g_wr_data_w => c_ddr3_ctlr_data_w,
- g_rd_data_w => c_word_w,
- g_wr_fifo_depth => c_wr_fifo_depth,
- g_rd_fifo_depth => c_rd_fifo_depth / 8,
- g_wr_use_ctrl => true
- )
- port map (
- ctlr_ref_clk => ext_clk,
- ctlr_rst => dp_rst,
-
- ctlr_gen_clk => i_phy_clk,
- ctlr_gen_rst => i_phy_rst,
- ctlr_gen_clk_2x => phy_clk_2x,
- ctlr_gen_rst_2x => phy_rst_2x,
-
- ctlr_init_done => ctlr_init_done,
- ctlr_rdy => ctlr_rdy,
-
- dvr_start_addr => dvr_start_addr,
- dvr_end_addr => dvr_end_addr,
-
- dvr_en => dvr_en,
- dvr_wr_not_rd => dvr_wr_not_rd,
- dvr_done => dvr_done,
- --dvr_flush => dvr_flush,
-
- wr_clk => dp_clk,
- wr_rst => dp_rst,
-
- wr_sosi => mux_wide_sosi,
- wr_siso => mux_wide_siso,
-
- -- ddr3 rd FIFO ST interface to the dp->mm adapter
- rd_sosi => rd_sosi,
- rd_siso => rd_siso,
-
- rd_clk => mm_clk,
- rd_rst => mm_rst,
-
- rd_fifo_usedw => rd_usedw,
-
- phy_in => ddr3_in,
- phy_io => ddr3_io,
- phy_ou => ddr3_ou
- );
+ generic map(
+ g_sim => g_sim,
+ g_phy => 0,
+ g_ddr => g_ddr,
+ g_mts => 800,
+ g_wr_data_w => c_ddr3_ctlr_data_w,
+ g_rd_data_w => c_word_w,
+ g_wr_fifo_depth => c_wr_fifo_depth,
+ g_rd_fifo_depth => c_rd_fifo_depth / 8,
+ g_wr_use_ctrl => true
+ )
+ port map (
+ ctlr_ref_clk => ext_clk,
+ ctlr_rst => dp_rst,
+
+ ctlr_gen_clk => i_phy_clk,
+ ctlr_gen_rst => i_phy_rst,
+ ctlr_gen_clk_2x => phy_clk_2x,
+ ctlr_gen_rst_2x => phy_rst_2x,
+
+ ctlr_init_done => ctlr_init_done,
+ ctlr_rdy => ctlr_rdy,
+
+ dvr_start_addr => dvr_start_addr,
+ dvr_end_addr => dvr_end_addr,
+
+ dvr_en => dvr_en,
+ dvr_wr_not_rd => dvr_wr_not_rd,
+ dvr_done => dvr_done,
+ --dvr_flush => dvr_flush,
+
+ wr_clk => dp_clk,
+ wr_rst => dp_rst,
+
+ wr_sosi => mux_wide_sosi,
+ wr_siso => mux_wide_siso,
+
+ -- ddr3 rd FIFO ST interface to the dp->mm adapter
+ rd_sosi => rd_sosi,
+ rd_siso => rd_siso,
+
+ rd_clk => mm_clk,
+ rd_rst => mm_rst,
+
+ rd_fifo_usedw => rd_usedw,
+
+ phy_in => ddr3_in,
+ phy_io => ddr3_io,
+ phy_ou => ddr3_ou
+ );
-- Flush ddr3 module's FIFO (keep sinking the stream but simply discard the
-- data) after reset to prevent ddr3 write fifo from filling up - which would
@@ -200,22 +200,22 @@ begin
end process;
u_dp_fifo_to_mm : entity dp_lib.dp_fifo_to_mm
- generic map(
- g_fifo_size => c_rd_fifo_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
-
- snk_out => rd_siso,
- snk_in => rd_sosi,
- usedw => rd_usedw, -- used words from rd FIFO
-
- mm_rd => mm_rd,
- mm_rddata => mm_rd_data,
- mm_rdval => mm_rd_val,
- mm_usedw => mm_rd_usedw -- resized to 32 bits
- );
+ generic map(
+ g_fifo_size => c_rd_fifo_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ snk_out => rd_siso,
+ snk_in => rd_sosi,
+ usedw => rd_usedw, -- used words from rd FIFO
+
+ mm_rd => mm_rd,
+ mm_rddata => mm_rd_data,
+ mm_rdval => mm_rd_val,
+ mm_usedw => mm_rd_usedw -- resized to 32 bits
+ );
-- DDR3 streaming read output to mm bus
data_miso.rddata(c_word_w - 1 downto 0) <= mm_rd_data;
@@ -223,28 +223,28 @@ begin
mm_rd <= data_mosi.rd;
u_storage_reg : entity work.bn_capture_storage_reg
- generic map(
- g_ddr => g_ddr
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => i_phy_rst,
- st_clk => i_phy_clk,
-
- sla_in => ctrl_mosi,
- sla_out => ctrl_miso,
-
- st_en_evt => dvr_en,
- st_wr_not_rd => dvr_wr_not_rd,
-
- st_start_addr => dvr_start_addr,
- st_end_addr => dvr_end_addr,
-
- st_done => dvr_done,
- st_init_done => ctlr_init_done,
- st_ctlr_rdy => ctlr_rdy,
-
- mm_rd_usedw => mm_rd_usedw
- );
+ generic map(
+ g_ddr => g_ddr
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => i_phy_rst,
+ st_clk => i_phy_clk,
+
+ sla_in => ctrl_mosi,
+ sla_out => ctrl_miso,
+
+ st_en_evt => dvr_en,
+ st_wr_not_rd => dvr_wr_not_rd,
+
+ st_start_addr => dvr_start_addr,
+ st_end_addr => dvr_end_addr,
+
+ st_done => dvr_done,
+ st_init_done => ctlr_init_done,
+ st_ctlr_rdy => ctlr_rdy,
+
+ mm_rd_usedw => mm_rd_usedw
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
index ded28ec91c..b9c55cee50 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity bn_capture_storage_reg is
generic (
g_ddr : t_c_ddr3_phy
- );
+ );
port (
-- Clocks and reset
mm_rst : in std_logic; -- reset synchronous with mm_clk
@@ -53,15 +53,16 @@ entity bn_capture_storage_reg is
-- MM registers
mm_rd_usedw : in std_logic_vector(31 downto 0)
- );
+ );
end bn_capture_storage_reg;
architecture rtl of bn_capture_storage_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(8),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 8,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(8),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 8,
+ init_sl => '0');
-- Registers in mm_clk domain
signal mm_en_evt : std_logic;
signal mm_wr_not_rd : std_logic;
@@ -116,7 +117,7 @@ begin
when others => null; -- unused MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -154,59 +155,59 @@ begin
------------------------------------------------------------------------------
u_spulse_en_evt : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_en_evt,
- in_busy => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => st_en_evt
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_en_evt,
+ in_busy => OPEN,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => st_en_evt
+ );
u_async_wr_not_rd : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- din => mm_wr_not_rd,
- dout => st_wr_not_rd
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ din => mm_wr_not_rd,
+ dout => st_wr_not_rd
+ );
u_async_done : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_done,
- dout => mm_done
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_done,
+ dout => mm_done
+ );
u_async_init_done : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_init_done,
- dout => mm_init_done
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_init_done,
+ dout => mm_init_done
+ );
u_async_rdy : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_ctlr_rdy,
- dout => mm_ctlr_rdy
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_ctlr_rdy,
+ dout => mm_ctlr_rdy
+ );
-- Address range should be set before asserting the DDR3 enable bit.
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
index 1cf7b5d6fb..9bbcc1e317 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
@@ -35,20 +35,20 @@
-- . Set g_use_phy = (0, 0, 0, 0, 1, 0, 1, 0)
library IEEE, common_lib, dp_lib, i2c_lib, unb1_board_lib, diag_lib, aduh_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use work.unb1_bn_capture_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
-use i2c_lib.i2c_dev_unb_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use work.unb1_bn_capture_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
+ use i2c_lib.i2c_dev_unb_pkg.all;
entity tb_bn_capture is
generic (
@@ -74,9 +74,10 @@ architecture tb of tb_bn_capture is
constant c_fw_version : t_unb_fw_version := (1, 0);
constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 1024 * 1024, 1024, true); -- 800 MSps, block size 1024 samples, nof blocks per sync interval, monitor buffer nof samples using sync
- constant c_bn_capture : t_c_bn_capture := (c_unb_mm_clk_freq_50M,
- c_unb_ext_clk_freq_200M,
- c_bn_capture_sp_sim);
+ constant c_bn_capture : t_c_bn_capture := (
+ c_unb_mm_clk_freq_50M,
+ c_unb_ext_clk_freq_200M,
+ c_bn_capture_sp_sim);
constant c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g; -- use c_ddr3_phy_4g or c_ddr3_phy_1g dependent on what was generated with the MegaWizard
@@ -171,14 +172,14 @@ begin
sens_sda <= 'H'; -- pull up
u_sens_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_max1618_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_max1618_temp
- );
+ generic map (
+ g_address => c_max1618_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_max1618_temp
+ );
VERSION <= c_version;
ID <= c_id_bn0;
@@ -188,69 +189,69 @@ begin
------------------------------------------------------------------------------
dut : entity work.bn_capture
- generic map (
- -- General
- g_sim => c_sim,
- g_fw_version => c_fw_version,
- -- BN capture specific
- g_bn_capture => c_bn_capture,
- -- Use PHY Interface
- g_use_phy => g_use_phy,
- -- Auxiliary Interface
- g_aux => c_unb_aux,
- -- DDR3 Interface
- g_ddr => c_ddr,
- -- ADC Interface
- g_nof_dp_phs_clk => c_nof_dp_phs_clk,
- g_ai => c_ai
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- SO-DIMM Memory Bank I = ddr3_I
- MB_I_IN => MB_I_in,
- MB_I_IO => MB_I_io,
- MB_I_OU => MB_I_ou,
-
- -- SO-DIMM Memory Bank II = ddr3_II
- MB_II_IN => MB_II_in,
- MB_II_IO => MB_II_io,
- MB_II_OU => MB_II_ou,
-
- -- ADC Interface
- ADC_BI_A => DIG_A,
- ADC_BI_B => DIG_B,
- ADC_BI_A_CLK => DCLK_AB,
- ADC_BI_A_CLK_RST => DCLK_RST_AB,
- ADC_BI_C => DIG_C,
- ADC_BI_D => DIG_D,
- ADC_BI_D_CLK => DCLK_CD,
- ADC_BI_D_CLK_RST => DCLK_RST_CD,
-
- ADC_AB_SCL => ADC_AB_SCL,
- ADC_AB_SDA => ADC_AB_SDA,
- ADC_CD_SCL => ADC_CD_SCL,
- ADC_CD_SDA => ADC_CD_SDA
- );
+ generic map (
+ -- General
+ g_sim => c_sim,
+ g_fw_version => c_fw_version,
+ -- BN capture specific
+ g_bn_capture => c_bn_capture,
+ -- Use PHY Interface
+ g_use_phy => g_use_phy,
+ -- Auxiliary Interface
+ g_aux => c_unb_aux,
+ -- DDR3 Interface
+ g_ddr => c_ddr,
+ -- ADC Interface
+ g_nof_dp_phs_clk => c_nof_dp_phs_clk,
+ g_ai => c_ai
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- SO-DIMM Memory Bank I = ddr3_I
+ MB_I_IN => MB_I_in,
+ MB_I_IO => MB_I_io,
+ MB_I_OU => MB_I_ou,
+
+ -- SO-DIMM Memory Bank II = ddr3_II
+ MB_II_IN => MB_II_in,
+ MB_II_IO => MB_II_io,
+ MB_II_OU => MB_II_ou,
+
+ -- ADC Interface
+ ADC_BI_A => DIG_A,
+ ADC_BI_B => DIG_B,
+ ADC_BI_A_CLK => DCLK_AB,
+ ADC_BI_A_CLK_RST => DCLK_RST_AB,
+ ADC_BI_C => DIG_C,
+ ADC_BI_D => DIG_D,
+ ADC_BI_D_CLK => DCLK_CD,
+ ADC_BI_D_CLK_RST => DCLK_RST_CD,
+
+ ADC_AB_SCL => ADC_AB_SCL,
+ ADC_AB_SDA => ADC_AB_SDA,
+ ADC_CD_SCL => ADC_CD_SCL,
+ ADC_CD_SDA => ADC_CD_SDA
+ );
-----------------------------------------------------------------------------
-- ADU0 model and ADU1 model for BN port A,B and C,D
@@ -272,36 +273,36 @@ begin
-- National ADC
u_adc_AB : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_A),
- AQ => TO_SINT(ANA_B),
- AOVR => ANA_OVR,
- CLK => SCLK,
- DCLK => DCLK_AB,
- DCLK_RST => DCLK_RST_AB,
- DI => DIG_A,
- DQ => DIG_B,
- OVR => DIG_OVR_AB,
- SCL => ADC_AB_SCL,
- SDA => ADC_AB_SDA,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_A),
+ AQ => TO_SINT(ANA_B),
+ AOVR => ANA_OVR,
+ CLK => SCLK,
+ DCLK => DCLK_AB,
+ DCLK_RST => DCLK_RST_AB,
+ DI => DIG_A,
+ DQ => DIG_B,
+ OVR => DIG_OVR_AB,
+ SCL => ADC_AB_SCL,
+ SDA => ADC_AB_SDA,
+ test_pattern_en => test_pattern_en
+ );
u_adc_CD : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_C),
- AQ => TO_SINT(ANA_D),
- AOVR => ANA_OVR,
- CLK => SCLK,
- DCLK => DCLK_CD,
- DCLK_RST => DCLK_RST_CD,
- DI => DIG_C,
- DQ => DIG_D,
- OVR => DIG_OVR_CD,
- SCL => ADC_CD_SCL,
- SDA => ADC_CD_SDA,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_C),
+ AQ => TO_SINT(ANA_D),
+ AOVR => ANA_OVR,
+ CLK => SCLK,
+ DCLK => DCLK_CD,
+ DCLK_RST => DCLK_RST_CD,
+ DI => DIG_C,
+ DQ => DIG_D,
+ OVR => DIG_OVR_CD,
+ SCL => ADC_CD_SCL,
+ SDA => ADC_CD_SDA,
+ test_pattern_en => test_pattern_en
+ );
------------------------------------------------------------------------------
-- 1GbE Loopback model
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
index 3c4226b3cc..7faca03883 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
@@ -49,19 +49,19 @@
-- that the tb has run.
library IEEE, common_lib, dp_lib, diag_lib, aduh_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use work.unb1_bn_capture_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use work.unb1_bn_capture_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity tb_unb1_bn_capture_input is
end tb_unb1_bn_capture_input;
@@ -70,9 +70,10 @@ architecture tb of tb_unb1_bn_capture_input is
constant c_sim : boolean := true;
constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 48 * 1024, 4 * 1024, true); -- 800 MSps, block size 1024 samples, 48 blocks per sync interval, monitor buffer 4096 samples using sync
- constant c_bn_capture : t_c_bn_capture := (c_unb1_board_mm_clk_freq_50M,
- c_unb1_board_ext_clk_freq_200M,
- c_bn_capture_sp_sim);
+ constant c_bn_capture : t_c_bn_capture := (
+ c_unb1_board_mm_clk_freq_50M,
+ c_unb1_board_ext_clk_freq_200M,
+ c_bn_capture_sp_sim);
constant c_ram_wg_dat_w : natural := c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_dat_w;
constant c_ram_wg_size : natural := 2**c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w;
@@ -456,7 +457,7 @@ begin
-- Read ADUH monitor buffer at BSN
for K in 0 to c_bsn_schedule_nof_events - 1 loop
while unsigned(current_bsn) < c_bsn_schedule_aduh_monitor + K * c_nof_block_per_sync loop
- proc_common_wait_some_cycles(mm_clk, 1);
+ proc_common_wait_some_cycles(mm_clk, 1);
end loop;
-- Read the RAM waveform buffer for all 4 wideband waveform generators
@@ -513,90 +514,90 @@ begin
-- National ADC
u_adc_AB : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_A),
- AQ => TO_SINT(ANA_B),
- CLK => SCLK,
- DCLK => DCLK_AB,
- DCLK_RST => DCLK_RST_AB,
- DI => DIG_A,
- DQ => DIG_B,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_A),
+ AQ => TO_SINT(ANA_B),
+ CLK => SCLK,
+ DCLK => DCLK_AB,
+ DCLK_RST => DCLK_RST_AB,
+ DI => DIG_A,
+ DQ => DIG_B,
+ test_pattern_en => test_pattern_en
+ );
u_adc_CD : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_C),
- AQ => TO_SINT(ANA_D),
- CLK => SCLK,
- DCLK => DCLK_CD,
- DCLK_RST => DCLK_RST_CD,
- DI => DIG_C,
- DQ => DIG_D,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_C),
+ AQ => TO_SINT(ANA_D),
+ CLK => SCLK,
+ DCLK => DCLK_CD,
+ DCLK_RST => DCLK_RST_CD,
+ DI => DIG_C,
+ DQ => DIG_D,
+ test_pattern_en => test_pattern_en
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
dut : entity work.unb1_bn_capture_input
- generic map (
- g_sim => c_sim,
- g_bn_capture => c_bn_capture,
- g_nof_dp_phs_clk => dp_phs_clk_vec'LENGTH,
- g_ai => c_ai
- )
- port map (
- -- ADC Interface
- -- . ADU_AB
- ADC_BI_A => DIG_A,
- ADC_BI_B => DIG_B,
- ADC_BI_A_CLK => DCLK_AB,
- ADC_BI_A_CLK_RST => DCLK_RST_AB,
-
- -- . ADU_CD
- ADC_BI_C => DIG_C,
- ADC_BI_D => DIG_D,
- ADC_BI_D_CLK => DCLK_CD,
- ADC_BI_D_CLK_RST => DCLK_RST_CD,
-
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec,
- dp_pps => dp_pps,
-
- -- MM bsn source
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
-
- -- MM bsn schedule WG
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
-
- -- MM aduh quad
- reg_adc_quad_mosi => reg_adc_quad_mosi,
- reg_adc_quad_miso => reg_adc_quad_miso,
-
- -- MM waveform generators
- reg_wg_mosi_arr => reg_wg_mosi_arr,
- reg_wg_miso_arr => reg_wg_miso_arr,
- ram_wg_mosi_arr => ram_wg_mosi_arr,
- ram_wg_miso_arr => ram_wg_miso_arr,
-
- -- MM signal path monitors
- reg_mon_mosi_arr => reg_mon_mosi_arr,
- reg_mon_miso_arr => reg_mon_miso_arr,
- ram_mon_mosi_arr => ram_mon_mosi_arr,
- ram_mon_miso_arr => ram_mon_miso_arr,
-
- -- Streaming output (can be from ADU or from internal WG)
- sp_sosi_arr => sp_sosi_arr,
- sp_siso_arr => sp_siso_arr
- );
+ generic map (
+ g_sim => c_sim,
+ g_bn_capture => c_bn_capture,
+ g_nof_dp_phs_clk => dp_phs_clk_vec'LENGTH,
+ g_ai => c_ai
+ )
+ port map (
+ -- ADC Interface
+ -- . ADU_AB
+ ADC_BI_A => DIG_A,
+ ADC_BI_B => DIG_B,
+ ADC_BI_A_CLK => DCLK_AB,
+ ADC_BI_A_CLK_RST => DCLK_RST_AB,
+
+ -- . ADU_CD
+ ADC_BI_C => DIG_C,
+ ADC_BI_D => DIG_D,
+ ADC_BI_D_CLK => DCLK_CD,
+ ADC_BI_D_CLK_RST => DCLK_RST_CD,
+
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec,
+ dp_pps => dp_pps,
+
+ -- MM bsn source
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+
+ -- MM bsn schedule WG
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- MM aduh quad
+ reg_adc_quad_mosi => reg_adc_quad_mosi,
+ reg_adc_quad_miso => reg_adc_quad_miso,
+
+ -- MM waveform generators
+ reg_wg_mosi_arr => reg_wg_mosi_arr,
+ reg_wg_miso_arr => reg_wg_miso_arr,
+ ram_wg_mosi_arr => ram_wg_mosi_arr,
+ ram_wg_miso_arr => ram_wg_miso_arr,
+
+ -- MM signal path monitors
+ reg_mon_mosi_arr => reg_mon_mosi_arr,
+ reg_mon_miso_arr => reg_mon_miso_arr,
+ ram_mon_mosi_arr => ram_mon_mosi_arr,
+ ram_mon_miso_arr => ram_mon_miso_arr,
+
+ -- Streaming output (can be from ADU or from internal WG)
+ sp_sosi_arr => sp_sosi_arr,
+ sp_siso_arr => sp_siso_arr
+ );
------------------------------------------------------------------------------
-- Verify
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
index f1ac60af9f..3b24196253 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, diag_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity node_unb1_bn_terminal_bg is
generic(
@@ -133,28 +133,28 @@ begin
-----------------------------------------------------------------------------
gen_bg : if g_use_bg = true generate
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => g_usr_nof_streams,
- g_buf_dat_w => g_usr_data_w,
- g_buf_addr_w => ceil_log2(g_usr_block_len),
- g_file_name_prefix => "UNUSED"
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => g_usr_nof_streams,
+ g_buf_dat_w => g_usr_data_w,
+ g_buf_addr_w => ceil_log2(g_usr_block_len),
+ g_file_name_prefix => "UNUSED"
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
end generate;
no_bg : if g_use_bg = false generate
@@ -191,55 +191,55 @@ begin
back_tx_usr_sosi_2arr <= bg_sosi_2arr;
u_terminals_back: entity unb1_board_lib.unb1_board_terminals_back
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_nof_bus => c_unb1_board_nof_uniboard, -- = 4 Uniboard in subrack, this UniBoard and 3 other UniBoards, so each UniBoard can be indexed by logical index 3:0
- -- User
- g_usr_use_complex => true,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_block_len,
- g_usr_nof_streams => c_mesh_usr_nof_input,
- -- Phy
- g_phy_nof_serial => g_back_nof_serial,
- g_phy_gx_mbps => g_back_gx_mbps,
- g_phy_rx_fifo_size => c_bram_m9k_fifo_depth,
- -- Tx
- g_tx_input_use_fifo => true,
- -- Rx
- g_rx_output_use_fifo => false, -- no need for Rx output FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_timeout_w => c_rx_timeout_w
- )
- port map (
- bck_id => bck_id,
-
- tr_clk => tr_back_clk,
- cal_clk => cal_clk,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- User I/O side (4 uniboards)(4 i/o streams)
- tx_usr_siso_2arr => back_tx_usr_siso_2arr,
- tx_usr_sosi_2arr => back_tx_usr_sosi_2arr,
- rx_usr_siso_2arr => back_rx_usr_siso_2arr,
- rx_usr_sosi_2arr => back_rx_usr_sosi_2arr,
-
- -- Serial (tr_nonbonded)
- tx_serial_2arr => back_tx_serial_2arr, -- Tx
- rx_serial_2arr => back_rx_serial_2arr, -- Rx
-
- -- MM Control
- reg_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
-
- reg_diagnostics_mosi => reg_back_diagnostics_mosi,
- reg_diagnostics_miso => reg_back_diagnostics_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_nof_bus => c_unb1_board_nof_uniboard, -- = 4 Uniboard in subrack, this UniBoard and 3 other UniBoards, so each UniBoard can be indexed by logical index 3:0
+ -- User
+ g_usr_use_complex => true,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_block_len,
+ g_usr_nof_streams => c_mesh_usr_nof_input,
+ -- Phy
+ g_phy_nof_serial => g_back_nof_serial,
+ g_phy_gx_mbps => g_back_gx_mbps,
+ g_phy_rx_fifo_size => c_bram_m9k_fifo_depth,
+ -- Tx
+ g_tx_input_use_fifo => true,
+ -- Rx
+ g_rx_output_use_fifo => false, -- no need for Rx output FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_timeout_w => c_rx_timeout_w
+ )
+ port map (
+ bck_id => bck_id,
+
+ tr_clk => tr_back_clk,
+ cal_clk => cal_clk,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- User I/O side (4 uniboards)(4 i/o streams)
+ tx_usr_siso_2arr => back_tx_usr_siso_2arr,
+ tx_usr_sosi_2arr => back_tx_usr_sosi_2arr,
+ rx_usr_siso_2arr => back_rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => back_rx_usr_sosi_2arr,
+
+ -- Serial (tr_nonbonded)
+ tx_serial_2arr => back_tx_serial_2arr, -- Tx
+ rx_serial_2arr => back_rx_serial_2arr, -- Rx
+
+ -- MM Control
+ reg_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
+
+ reg_diagnostics_mosi => reg_back_diagnostics_mosi,
+ reg_diagnostics_miso => reg_back_diagnostics_miso
+ );
-----------------------------------------------------------------------------
-- Back terminals -> transpose -> mesh terminals
@@ -253,63 +253,63 @@ begin
-----------------------------------------------------------------------------
gen_mesh: if g_use_mesh = true generate
u_terminals_mesh : entity unb1_board_lib.unb1_board_terminals_mesh
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_node_type => e_bn,
- g_nof_bus => c_unb1_board_nof_fn, -- 4 to 4 nodes in mesh
- -- User
- g_usr_use_complex => true,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_block_len,
- g_usr_nof_streams => c_mesh_usr_nof_input,
- -- Phy
- g_phy_nof_serial => g_mesh_nof_serial,
- g_phy_gx_mbps => g_mesh_gx_mbps,
- g_phy_rx_fifo_size => c_bram_m9k_fifo_depth,
- g_phy_ena_reorder => g_mesh_ena_reorder,
- -- Tx
- g_use_tx => true, -- user Tx must be TRUE for BG in BN,
- g_tx_input_use_fifo => true, -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
- -- Rx
- g_use_rx => g_mesh_use_rx, -- optionally do support diag Rx
- g_rx_output_use_fifo => false, -- no user Rx
- -- Monitoring
- g_mon_select => g_mesh_mon_select,
- g_mon_nof_words => g_mesh_mon_nof_words,
- g_mon_use_sync => g_mesh_mon_use_sync
- )
- port map (
- chip_id => chip_id,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_sync => dp_pps,
- tr_clk => tr_mesh_clk,
- cal_clk => cal_clk,
-
- -- User interface (4 nodes)(4 input streams)
- tx_usr_siso_2arr => mesh_tx_usr_siso_2arr,
- tx_usr_sosi_2arr => mesh_tx_usr_sosi_2arr, -- Tx (user Rx from FN to BN is unused)
-
- -- Serial mesh interface (tr_nonbonded)
- tx_serial_2arr => mesh_tx_serial_2arr, -- Tx
- rx_serial_2arr => mesh_rx_serial_2arr, -- Rx
-
- -- MM Control
- reg_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
-
- reg_diagnostics_mosi => reg_mesh_diagnostics_mosi,
- reg_diagnostics_miso => reg_mesh_diagnostics_miso,
-
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_node_type => e_bn,
+ g_nof_bus => c_unb1_board_nof_fn, -- 4 to 4 nodes in mesh
+ -- User
+ g_usr_use_complex => true,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_block_len,
+ g_usr_nof_streams => c_mesh_usr_nof_input,
+ -- Phy
+ g_phy_nof_serial => g_mesh_nof_serial,
+ g_phy_gx_mbps => g_mesh_gx_mbps,
+ g_phy_rx_fifo_size => c_bram_m9k_fifo_depth,
+ g_phy_ena_reorder => g_mesh_ena_reorder,
+ -- Tx
+ g_use_tx => true, -- user Tx must be TRUE for BG in BN,
+ g_tx_input_use_fifo => true, -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ -- Rx
+ g_use_rx => g_mesh_use_rx, -- optionally do support diag Rx
+ g_rx_output_use_fifo => false, -- no user Rx
+ -- Monitoring
+ g_mon_select => g_mesh_mon_select,
+ g_mon_nof_words => g_mesh_mon_nof_words,
+ g_mon_use_sync => g_mesh_mon_use_sync
+ )
+ port map (
+ chip_id => chip_id,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_sync => dp_pps,
+ tr_clk => tr_mesh_clk,
+ cal_clk => cal_clk,
+
+ -- User interface (4 nodes)(4 input streams)
+ tx_usr_siso_2arr => mesh_tx_usr_siso_2arr,
+ tx_usr_sosi_2arr => mesh_tx_usr_sosi_2arr, -- Tx (user Rx from FN to BN is unused)
+
+ -- Serial mesh interface (tr_nonbonded)
+ tx_serial_2arr => mesh_tx_serial_2arr, -- Tx
+ rx_serial_2arr => mesh_rx_serial_2arr, -- Rx
+
+ -- MM Control
+ reg_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
+
+ reg_diagnostics_mosi => reg_mesh_diagnostics_mosi,
+ reg_diagnostics_miso => reg_mesh_diagnostics_miso,
+
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
+ );
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
index a5254c63ff..5dfb737045 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb1_bn_terminal_bg is
generic (
@@ -40,7 +40,7 @@ entity unb1_bn_terminal_bg is
g_stamp_svn : natural := 0 -- SVN revision
);
port (
- -- GENERAL
+ -- GENERAL
CLK : in std_logic; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
@@ -86,17 +86,17 @@ end unb1_bn_terminal_bg;
architecture str of unb1_bn_terminal_bg is
constant c_fw_version : t_unb1_board_fw_version := (1, 0); -- firmware version x.y
- -- Use PHY Interface
- -- TYPE t_c_unb_use_phy IS RECORD
- -- eth1g : NATURAL;
- -- tr_front: NATURAL;
- -- tr_mesh : NATURAL;
- -- tr_back : NATURAL;
- -- ddr3_I : NATURAL;
- -- ddr3_II : NATURAL;
- -- adc : NATURAL;
- -- wdi : NATURAL;
- -- END RECORD;
+ -- Use PHY Interface
+ -- TYPE t_c_unb_use_phy IS RECORD
+ -- eth1g : NATURAL;
+ -- tr_front: NATURAL;
+ -- tr_mesh : NATURAL;
+ -- tr_back : NATURAL;
+ -- ddr3_I : NATURAL;
+ -- ddr3_II : NATURAL;
+ -- adc : NATURAL;
+ -- wdi : NATURAL;
+ -- END RECORD;
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 1, 1, 0, 0, 0, 1);
-- Transceivers Interface
constant c_tr_mesh : t_c_unb1_board_tr := c_unb1_board_tr_mesh;
@@ -147,7 +147,7 @@ architecture str of unb1_bn_terminal_bg is
signal rom_unb_system_info_mosi : t_mem_mosi;
signal rom_unb_system_info_miso : t_mem_miso;
- -- WDI override
+ -- WDI override
signal reg_wdi_mosi : t_mem_mosi;
signal reg_wdi_miso : t_mem_miso;
@@ -205,304 +205,304 @@ begin
-----------------------------------------------------------------------------
u_sopc : entity work.sopc_unb1_bn_terminal_bg
- port map (
- -- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
-
- -- the_altpll_0
- areset_to_the_altpll_0 => '0',
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_tr_nonbonded_mesh
- coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
- coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.rd,
- coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
- coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.wr,
- coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diagnostics_mesh
- coe_address_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
- coe_read_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.rd,
- coe_readdata_export_to_the_reg_diagnostics_mesh => reg_mesh_diagnostics_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
- coe_write_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.wr,
- coe_writedata_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buffer
- coe_address_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
- coe_read_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
- coe_write_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_tr_nonbonded_back
- coe_address_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_tr_nonbonded_back => OPEN,
- coe_read_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.rd,
- coe_readdata_export_to_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_tr_nonbonded_back => OPEN,
- coe_write_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.wr,
- coe_writedata_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diagnostics_back
- coe_address_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diagnostics_back => OPEN,
- coe_read_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.rd,
- coe_readdata_export_to_the_reg_diagnostics_back => reg_back_diagnostics_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diagnostics_back => OPEN,
- coe_write_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.wr,
- coe_writedata_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => pout_debug_wave,
-
- -- the_pio_pps
- in_port_to_the_pio_pps => pin_pps,
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ -- 1) global signals:
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+
+ -- the_altpll_0
+ areset_to_the_altpll_0 => '0',
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_tr_nonbonded_mesh
+ coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
+ coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
+ coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diagnostics_mesh
+ coe_address_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
+ coe_read_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.rd,
+ coe_readdata_export_to_the_reg_diagnostics_mesh => reg_mesh_diagnostics_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
+ coe_write_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.wr,
+ coe_writedata_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buffer
+ coe_address_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_read_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_write_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_tr_nonbonded_back
+ coe_address_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_tr_nonbonded_back => OPEN,
+ coe_read_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_tr_nonbonded_back => OPEN,
+ coe_write_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diagnostics_back
+ coe_address_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diagnostics_back => OPEN,
+ coe_read_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.rd,
+ coe_readdata_export_to_the_reg_diagnostics_back => reg_back_diagnostics_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diagnostics_back => OPEN,
+ coe_write_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.wr,
+ coe_writedata_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => pout_debug_wave,
+
+ -- the_pio_pps
+ in_port_to_the_pio_pps => pin_pps,
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_aux
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_aux
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- Design function
-----------------------------------------------------------------------------
u_node_bn_terminal_bg : entity work.node_unb1_bn_terminal_bg
- generic map(
- g_sim => g_sim,
- -- Application interface
- g_use_bg => true,
- g_usr_nof_streams => c_usr_nof_streams,
- g_usr_block_len => c_usr_block_len,
- -- Terminals interface
- g_use_mesh => c_use_mesh,
- g_use_back => g_rev_multi_unb,
- g_mesh_nof_serial => c_mesh_nof_serial,
- g_mesh_use_rx => c_mesh_use_rx,
- g_mesh_gx_mbps => c_mesh_gx_mbps,
- g_mesh_mon_select => c_mesh_mon_select,
- g_mesh_mon_nof_words => c_mesh_mon_nof_words,
- g_mesh_mon_use_sync => c_mesh_mon_use_sync,
- g_mesh_ena_reorder => true,
- -- Auxiliary Interface
- g_aux => c_aux
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => SB_CLK,
- tr_back_clk => SA_CLK,
- cal_clk => cal_clk,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id,
-
- in_sosi_arr => in_sosi_arr,
- in_siso_arr => in_siso_arr,
-
- -- MM interface
- -- . block generator
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- -- . tr_nonbonded mesh
- reg_mesh_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
- reg_mesh_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
- reg_mesh_diagnostics_mosi => reg_mesh_diagnostics_mosi,
- reg_mesh_diagnostics_miso => reg_mesh_diagnostics_miso,
-
- -- . tr_nonbonded back
- reg_back_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
- reg_back_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
- reg_back_diagnostics_mosi => reg_back_diagnostics_mosi,
- reg_back_diagnostics_miso => reg_back_diagnostics_miso,
-
- -- . diag_data_buffer mesh
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
-
- -- Mesh interface
- mesh_tx_serial_2arr => mesh_tx_serial_2arr,
- mesh_rx_serial_2arr => mesh_rx_serial_2arr,
-
- -- Back interface
- back_tx_serial_2arr => back_tx_serial_2arr,
- back_rx_serial_2arr => back_rx_serial_2arr
- );
+ generic map(
+ g_sim => g_sim,
+ -- Application interface
+ g_use_bg => true,
+ g_usr_nof_streams => c_usr_nof_streams,
+ g_usr_block_len => c_usr_block_len,
+ -- Terminals interface
+ g_use_mesh => c_use_mesh,
+ g_use_back => g_rev_multi_unb,
+ g_mesh_nof_serial => c_mesh_nof_serial,
+ g_mesh_use_rx => c_mesh_use_rx,
+ g_mesh_gx_mbps => c_mesh_gx_mbps,
+ g_mesh_mon_select => c_mesh_mon_select,
+ g_mesh_mon_nof_words => c_mesh_mon_nof_words,
+ g_mesh_mon_use_sync => c_mesh_mon_use_sync,
+ g_mesh_ena_reorder => true,
+ -- Auxiliary Interface
+ g_aux => c_aux
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => SB_CLK,
+ tr_back_clk => SA_CLK,
+ cal_clk => cal_clk,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id,
+
+ in_sosi_arr => in_sosi_arr,
+ in_siso_arr => in_siso_arr,
+
+ -- MM interface
+ -- . block generator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ -- . tr_nonbonded mesh
+ reg_mesh_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
+ reg_mesh_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
+ reg_mesh_diagnostics_mosi => reg_mesh_diagnostics_mosi,
+ reg_mesh_diagnostics_miso => reg_mesh_diagnostics_miso,
+
+ -- . tr_nonbonded back
+ reg_back_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
+ reg_back_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
+ reg_back_diagnostics_mosi => reg_back_diagnostics_mosi,
+ reg_back_diagnostics_miso => reg_back_diagnostics_miso,
+
+ -- . diag_data_buffer mesh
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+
+ -- Mesh interface
+ mesh_tx_serial_2arr => mesh_tx_serial_2arr,
+ mesh_rx_serial_2arr => mesh_rx_serial_2arr,
+
+ -- Back interface
+ back_tx_serial_2arr => back_tx_serial_2arr,
+ back_rx_serial_2arr => back_rx_serial_2arr
+ );
-----------------------------------------------------------------------------
-- Wires
@@ -514,42 +514,42 @@ begin
gen_tr_mesh : if c_use_phy.tr_mesh /= 0 generate
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => mesh_tx_serial_2arr,
- rx_serial_2arr => mesh_rx_serial_2arr,
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_TX,
- FN_BN_0_RX => FN_BN_0_RX,
- FN_BN_1_TX => FN_BN_1_TX,
- FN_BN_1_RX => FN_BN_1_RX,
- FN_BN_2_TX => FN_BN_2_TX,
- FN_BN_2_RX => FN_BN_2_RX,
- FN_BN_3_TX => FN_BN_3_TX,
- FN_BN_3_RX => FN_BN_3_RX
- );
+ generic map (
+ g_bus_w => c_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => mesh_tx_serial_2arr,
+ rx_serial_2arr => mesh_rx_serial_2arr,
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX
+ );
end generate;
gen_tr_back : if c_use_phy.tr_back /= 0 generate
u_back_io : entity unb1_board_lib.unb1_board_back_io
- generic map (
- g_bus_w => c_tr_back.bus_w
- )
- port map (
- tx_serial_2arr => back_tx_serial_2arr,
- rx_serial_2arr => back_rx_serial_2arr,
-
- -- Serial I/O
- BN_BI_0_TX => BN_BI_0_TX,
- BN_BI_0_RX => BN_BI_0_RX,
- BN_BI_1_TX => BN_BI_1_TX,
- BN_BI_1_RX => BN_BI_1_RX,
- BN_BI_2_TX => BN_BI_2_TX,
- BN_BI_2_RX => BN_BI_2_RX
- );
+ generic map (
+ g_bus_w => c_tr_back.bus_w
+ )
+ port map (
+ tx_serial_2arr => back_tx_serial_2arr,
+ rx_serial_2arr => back_rx_serial_2arr,
+
+ -- Serial I/O
+ BN_BI_0_TX => BN_BI_0_TX,
+ BN_BI_0_RX => BN_BI_0_RX,
+ BN_BI_1_TX => BN_BI_1_TX,
+ BN_BI_1_RX => BN_BI_1_RX,
+ BN_BI_2_TX => BN_BI_2_TX,
+ BN_BI_2_RX => BN_BI_2_RX
+ );
end generate;
-end;
+ end;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
index 65c1746710..d30ebfb240 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
@@ -28,17 +28,17 @@
-- behaviour in the Wave window.
library IEEE, common_lib, dp_lib, diag_lib, bf_lib, unb1_board_lib, diagnostics_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use bf_lib.bf_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use diagnostics_lib.tb_diagnostics_trnb_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use bf_lib.bf_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use diagnostics_lib.tb_diagnostics_trnb_pkg.all;
entity tb_node_unb1_bn_terminal_bg is
generic (
@@ -213,27 +213,27 @@ begin
-- GENERATE BLOCK GENERATOR FOR STIMULI ON SOSI PORT
---------------------------------------------------------------
u_block_generator : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => g_bf.nof_input_streams,
- g_buf_dat_w => c_nof_complex * g_bf.in_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
- g_file_index_arr => g_bg_data_file_index_arr,
- g_file_name_prefix => g_bg_data_file_name
- )
- port map(
- -- Clocks and Reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => '1',
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => open,
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => open,
- out_siso_arr => in_siso_arr,
- out_sosi_arr => in_sosi_arr
- );
+ generic map(
+ g_nof_streams => g_bf.nof_input_streams,
+ g_buf_dat_w => c_nof_complex * g_bf.in_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_file_index_arr => g_bg_data_file_index_arr,
+ g_file_name_prefix => g_bg_data_file_name
+ )
+ port map(
+ -- Clocks and Reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => '1',
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => open,
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => open,
+ out_siso_arr => in_siso_arr,
+ out_sosi_arr => in_sosi_arr
+ );
----------------------------------------------------------------------------
-- Stimuli for TRNB diagnostics
@@ -257,15 +257,15 @@ begin
while true loop
proc_diagnostics_trnb_run_and_verify(g_chip_id,
- c_nof_gx,
- c_nof_gx_mask,
- c_gx_link_delay,
- g_diagnostics_on_interval,
- g_diagnostics_off_interval,
- c_mm_clk_1us,
- mm_clk,
- reg_mesh_diagnostics_miso,
- reg_mesh_diagnostics_mosi);
+ c_nof_gx,
+ c_nof_gx_mask,
+ c_gx_link_delay,
+ g_diagnostics_on_interval,
+ g_diagnostics_off_interval,
+ c_mm_clk_1us,
+ mm_clk,
+ reg_mesh_diagnostics_miso,
+ reg_mesh_diagnostics_mosi);
end loop;
end if;
@@ -277,73 +277,73 @@ begin
------------------------------------------------------------------------------
u_dut : entity work.node_unb1_bn_terminal_bg
- generic map (
- g_sim => c_sim,
- g_sim_level => g_sim_level,
- -- Application interface
- g_use_bg => g_use_bg,
--- g_bg_data_file_index_arr => g_bg_data_file_index_arr,
--- g_bg_data_file_prefix => g_bg_data_file_name,
- g_use_back => g_use_back,
-
- -- Terminals interface
- g_mesh_nof_serial => g_mesh_nof_serial,
- g_mesh_use_rx => g_mesh_use_rx,
- g_mesh_gx_mbps => g_mesh_gx_mbps,
- g_mesh_mon_select => g_mesh_mon_select,
- g_mesh_mon_nof_words => g_mesh_mon_nof_words,
- g_mesh_mon_use_sync => g_mesh_mon_use_sync,
- g_mesh_ena_reorder => g_mesh_ena_reorder,
- -- Auxiliary Interface
- g_aux => c_unb1_board_aux
- )
- port map (
- -- System
- chip_id => TO_UVEC(g_chip_id, c_unb1_board_nof_chip_w), -- BN chip ID 4, 5, 6, 7
- bck_id => TO_UVEC(g_bck_id, c_unb1_board_nof_uniboard_w), -- Backplane ID 0,1,2,3
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => tr_clk,
- tr_back_clk => tr_clk,
- cal_clk => cal_clk,
-
- -- Streaming data input
- in_sosi_arr => in_sosi_arr,
- in_siso_arr => in_siso_arr,
-
- -- MM registers
- -- . block generator
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- -- . tr_nonbonded
- reg_mesh_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
- reg_mesh_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
- reg_mesh_diagnostics_mosi => reg_mesh_diagnostics_mosi,
- reg_mesh_diagnostics_miso => reg_mesh_diagnostics_miso,
-
- reg_back_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
- reg_back_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
- reg_back_diagnostics_mosi => reg_back_diagnostics_mosi,
- reg_back_diagnostics_miso => reg_back_diagnostics_miso,
-
- -- . rx terminals monitor buffers
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
-
- -- Mesh interface level
- -- . Serial (tr_nonbonded)
- mesh_tx_serial_2arr => mesh_tx_serial_2arr,
- mesh_rx_serial_2arr => mesh_rx_serial_2arr,
-
- -- Back interface level
- -- . Serial (tr_nonbonded)
- back_tx_serial_2arr => back_tx_serial_2arr,
- back_rx_serial_2arr => back_rx_serial_2arr
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_level => g_sim_level,
+ -- Application interface
+ g_use_bg => g_use_bg,
+ -- g_bg_data_file_index_arr => g_bg_data_file_index_arr,
+ -- g_bg_data_file_prefix => g_bg_data_file_name,
+ g_use_back => g_use_back,
+
+ -- Terminals interface
+ g_mesh_nof_serial => g_mesh_nof_serial,
+ g_mesh_use_rx => g_mesh_use_rx,
+ g_mesh_gx_mbps => g_mesh_gx_mbps,
+ g_mesh_mon_select => g_mesh_mon_select,
+ g_mesh_mon_nof_words => g_mesh_mon_nof_words,
+ g_mesh_mon_use_sync => g_mesh_mon_use_sync,
+ g_mesh_ena_reorder => g_mesh_ena_reorder,
+ -- Auxiliary Interface
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- System
+ chip_id => TO_UVEC(g_chip_id, c_unb1_board_nof_chip_w), -- BN chip ID 4, 5, 6, 7
+ bck_id => TO_UVEC(g_bck_id, c_unb1_board_nof_uniboard_w), -- Backplane ID 0,1,2,3
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => tr_clk,
+ tr_back_clk => tr_clk,
+ cal_clk => cal_clk,
+
+ -- Streaming data input
+ in_sosi_arr => in_sosi_arr,
+ in_siso_arr => in_siso_arr,
+
+ -- MM registers
+ -- . block generator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ -- . tr_nonbonded
+ reg_mesh_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
+ reg_mesh_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
+ reg_mesh_diagnostics_mosi => reg_mesh_diagnostics_mosi,
+ reg_mesh_diagnostics_miso => reg_mesh_diagnostics_miso,
+
+ reg_back_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
+ reg_back_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
+ reg_back_diagnostics_mosi => reg_back_diagnostics_mosi,
+ reg_back_diagnostics_miso => reg_back_diagnostics_miso,
+
+ -- . rx terminals monitor buffers
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+
+ -- Mesh interface level
+ -- . Serial (tr_nonbonded)
+ mesh_tx_serial_2arr => mesh_tx_serial_2arr,
+ mesh_rx_serial_2arr => mesh_rx_serial_2arr,
+
+ -- Back interface level
+ -- . Serial (tr_nonbonded)
+ back_tx_serial_2arr => back_tx_serial_2arr,
+ back_rx_serial_2arr => back_rx_serial_2arr
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
index b521c00a23..0b6b3c5956 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
@@ -32,12 +32,12 @@
-- Observe in Wave window that rx_usr_sosi_2arr is delayed tx_usr_sosi_2arr
library IEEE, common_lib, dp_lib, bf_lib, unb_common_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use bf_lib.bf_pkg.all;
-use unb_common_lib.unb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use bf_lib.bf_pkg.all;
+ use unb_common_lib.unb_common_pkg.all;
entity tb_tb_node_bn_terminal_bg is
generic (
@@ -63,33 +63,33 @@ architecture tb of tb_tb_node_bn_terminal_bg is
signal mesh_rx_serial_2arr : t_unb_mesh_sl_2arr;
begin
u_tb_node_bn_terminal_bg : entity work.tb_node_bn_terminal_bg
- generic map (
- -- Tb
- g_sim_level => 1, -- 0 = simulate GX IP, 1 = use fast serial behavioural model
- g_nof_sync => g_nof_sync,
- g_chip_id => 4,
- -- Application
- g_bf => c_bf,
- g_bg_data_file_index_arr => array_init(0, 16, 1),
- g_bg_data_file_name => "../../../../../../modules/Lofar/diag/src/data/bf_in_data",
- -- Diagnostics - TRNB
- g_diagnostics_en => g_diagnostics_en,
- -- Terminals interface
- g_mesh_nof_serial => c_mesh_nof_serial,
- g_mesh_use_rx => c_mesh_use_rx,
- g_mesh_ena_reorder => c_mesh_ena_reorder
- )
- port map (
- tb_clk => tb_clk,
- tb_end => tb_end,
-
- -- Timing
- dp_pps => dp_pps,
-
- -- Serial (tr_nonbonded)
- mesh_tx_serial_2arr => mesh_tx_serial_2arr,
- mesh_rx_serial_2arr => mesh_rx_serial_2arr
- );
+ generic map (
+ -- Tb
+ g_sim_level => 1, -- 0 = simulate GX IP, 1 = use fast serial behavioural model
+ g_nof_sync => g_nof_sync,
+ g_chip_id => 4,
+ -- Application
+ g_bf => c_bf,
+ g_bg_data_file_index_arr => array_init(0, 16, 1),
+ g_bg_data_file_name => "../../../../../../modules/Lofar/diag/src/data/bf_in_data",
+ -- Diagnostics - TRNB
+ g_diagnostics_en => g_diagnostics_en,
+ -- Terminals interface
+ g_mesh_nof_serial => c_mesh_nof_serial,
+ g_mesh_use_rx => c_mesh_use_rx,
+ g_mesh_ena_reorder => c_mesh_ena_reorder
+ )
+ port map (
+ tb_clk => tb_clk,
+ tb_end => tb_end,
+
+ -- Timing
+ dp_pps => dp_pps,
+
+ -- Serial (tr_nonbonded)
+ mesh_tx_serial_2arr => mesh_tx_serial_2arr,
+ mesh_rx_serial_2arr => mesh_rx_serial_2arr
+ );
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
index 45beb6d4fd..b9a60e6ac7 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
@@ -20,19 +20,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, dp_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
entity mmm_unb1_ddr3 is
generic (
@@ -167,41 +167,53 @@ begin
i_cal_clk <= not i_cal_clk after c_cal_clk_period / 2;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_reg_io_ddr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
- port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso );
+ u_mm_file_reg_io_ddr : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
+ port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso );
- u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso );
+ u_mm_file_reg_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF")
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso );
- u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso );
+ u_mm_file_ram_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF")
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso );
- u_mm_file_reg_diag_bg_ctrl : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_CTRL")
- port map(mm_rst, i_mm_clk, reg_diag_bg_ctrl_mosi, reg_diag_bg_ctrl_miso );
+ u_mm_file_reg_diag_bg_ctrl : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_CTRL")
+ port map(mm_rst, i_mm_clk, reg_diag_bg_ctrl_mosi, reg_diag_bg_ctrl_miso );
- u_mm_file_ram_diag_bg_data : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_DATA")
- port map(mm_rst, i_mm_clk, ram_diag_bg_data_mosi, ram_diag_bg_data_miso );
+ u_mm_file_ram_diag_bg_data : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_DATA")
+ port map(mm_rst, i_mm_clk, ram_diag_bg_data_mosi, ram_diag_bg_data_miso );
- u_mm_file_reg_diag_tx_seq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ")
- port map(mm_rst, i_mm_clk, reg_diag_tx_seq_mosi, reg_diag_tx_seq_miso );
+ u_mm_file_reg_diag_tx_seq : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ")
+ port map(mm_rst, i_mm_clk, reg_diag_tx_seq_mosi, reg_diag_tx_seq_miso );
- u_mm_file_reg_diag_rx_seq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ")
- port map(mm_rst, i_mm_clk, reg_diag_rx_seq_mosi, reg_diag_rx_seq_miso );
+ u_mm_file_reg_diag_rx_seq : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ")
+ port map(mm_rst, i_mm_clk, reg_diag_rx_seq_mosi, reg_diag_rx_seq_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -243,152 +255,152 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_ddr3
- port map (
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => i_cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
-
- -- the_altpll_0
- areset_to_the_altpll_0 => '0',
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => pout_debug_wave,
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_io_ddr
- coe_clk_export_from_the_reg_io_ddr => OPEN,
- coe_reset_export_from_the_reg_io_ddr => OPEN,
- coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(c_mm_reg_io_ddr_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
- coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
- coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg_data
- coe_clk_export_from_the_ram_diag_bg_data => OPEN,
- coe_reset_export_from_the_ram_diag_bg_data => OPEN,
- coe_address_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.address(c_mm_ram_diag_bg_data_addr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg_data => ram_diag_bg_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buf
- coe_clk_export_from_the_ram_diag_data_buf => OPEN,
- coe_reset_export_from_the_ram_diag_data_buf => OPEN,
- coe_address_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.address(c_mm_ram_diag_data_buf_addr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buf => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg_ctrl
- coe_clk_export_from_the_reg_diag_bg_ctrl => OPEN,
- coe_reset_export_from_the_reg_diag_bg_ctrl => OPEN,
- coe_address_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.address(c_mm_reg_diag_bg_ctrl_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buf
- coe_clk_export_from_the_reg_diag_data_buf => OPEN,
- coe_reset_export_from_the_reg_diag_data_buf => OPEN,
- coe_address_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.address(c_mm_reg_diag_data_buf_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buf => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_rx_seq
- coe_clk_export_from_the_reg_diag_rx_seq => OPEN,
- coe_reset_export_from_the_reg_diag_rx_seq => OPEN,
- coe_address_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.address(c_mm_reg_diag_rx_seq_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.rd,
- coe_readdata_export_to_the_reg_diag_rx_seq => reg_diag_rx_seq_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wr,
- coe_writedata_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_tx_seq
- coe_clk_export_from_the_reg_diag_tx_seq => OPEN,
- coe_reset_export_from_the_reg_diag_tx_seq => OPEN,
- coe_address_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.address(c_mm_reg_diag_tx_seq_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.rd,
- coe_readdata_export_to_the_reg_diag_tx_seq => reg_diag_tx_seq_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wr,
- coe_writedata_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => i_cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+
+ -- the_altpll_0
+ areset_to_the_altpll_0 => '0',
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => pout_debug_wave,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_io_ddr
+ coe_clk_export_from_the_reg_io_ddr => OPEN,
+ coe_reset_export_from_the_reg_io_ddr => OPEN,
+ coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(c_mm_reg_io_ddr_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
+ coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
+ coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg_data
+ coe_clk_export_from_the_ram_diag_bg_data => OPEN,
+ coe_reset_export_from_the_ram_diag_bg_data => OPEN,
+ coe_address_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.address(c_mm_ram_diag_bg_data_addr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg_data => ram_diag_bg_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buf
+ coe_clk_export_from_the_ram_diag_data_buf => OPEN,
+ coe_reset_export_from_the_ram_diag_data_buf => OPEN,
+ coe_address_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.address(c_mm_ram_diag_data_buf_addr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buf => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg_ctrl
+ coe_clk_export_from_the_reg_diag_bg_ctrl => OPEN,
+ coe_reset_export_from_the_reg_diag_bg_ctrl => OPEN,
+ coe_address_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.address(c_mm_reg_diag_bg_ctrl_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buf
+ coe_clk_export_from_the_reg_diag_data_buf => OPEN,
+ coe_reset_export_from_the_reg_diag_data_buf => OPEN,
+ coe_address_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.address(c_mm_reg_diag_data_buf_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buf => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_rx_seq
+ coe_clk_export_from_the_reg_diag_rx_seq => OPEN,
+ coe_reset_export_from_the_reg_diag_rx_seq => OPEN,
+ coe_address_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.address(c_mm_reg_diag_rx_seq_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_rx_seq => reg_diag_rx_seq_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_tx_seq
+ coe_clk_export_from_the_reg_diag_tx_seq => OPEN,
+ coe_reset_export_from_the_reg_diag_tx_seq => OPEN,
+ coe_address_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.address(c_mm_reg_diag_tx_seq_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_tx_seq => reg_diag_tx_seq_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
index 4467803f06..e3175650c1 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, diagnostics_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity node_unb1_ddr3 is
generic (
@@ -111,77 +111,77 @@ architecture str of node_unb1_ddr3 is
signal in_sosi_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0);
begin
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map(
- -- System
- g_technology => g_technology,
- g_dp_data_w => g_st_dat_w,
- g_dp_seq_dat_w => c_seq_dat_w,
- g_dp_wr_fifo_depth => c_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => g_tech_ddr,
- -- DIAG data buffer
- g_db_use_db => c_use_db,
- g_db_buf_nof_data => c_buf_nof_data
- )
- port map(
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => ddr_ref_clk,
- ctlr_ref_rst => ddr_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_out_clk,
- ctlr_rst_out => ddr_out_rst,
-
- ctlr_clk_in => dp_clk,
- ctlr_rst_in => dp_rst,
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR3 pass on termination control from master to slave controller
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
- -- DDR3 PHY external interface
- phy3_in => MB_I_in,
- phy3_io => MB_I_io,
- phy3_ou => MB_I_ou,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso
- );
+ generic map(
+ -- System
+ g_technology => g_technology,
+ g_dp_data_w => g_st_dat_w,
+ g_dp_seq_dat_w => c_seq_dat_w,
+ g_dp_wr_fifo_depth => c_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_rd_fifo_depth,
+ -- IO_DDR
+ g_io_tech_ddr => g_tech_ddr,
+ -- DIAG data buffer
+ g_db_use_db => c_use_db,
+ g_db_buf_nof_data => c_buf_nof_data
+ )
+ port map(
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => ddr_ref_clk,
+ ctlr_ref_rst => ddr_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_out_clk,
+ ctlr_rst_out => ddr_out_rst,
+
+ ctlr_clk_in => dp_clk,
+ ctlr_rst_in => dp_rst,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR3 pass on termination control from master to slave controller
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ -- DDR3 PHY external interface
+ phy3_in => MB_I_in,
+ phy3_io => MB_I_io,
+ phy3_ou => MB_I_ou,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
index 80af69d3f7..6518fb09df 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, technology_lib, tech_ddr_lib, io_ddr_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_ddr3 is
generic (
@@ -76,17 +76,17 @@ architecture str of unb1_ddr3 is
constant c_design_name : string := "unb1_ddr3";
constant c_design_note : string := "DDR3 reference design";
constant c_fw_version : t_unb1_board_fw_version := (0, 3); -- firmware version x.y
- -- Use PHY Interface
- -- TYPE t_c_unb_use_phy IS RECORD
- -- eth1g : NATURAL;
- -- tr_front: NATURAL;
- -- tr_mesh : NATURAL;
- -- tr_back : NATURAL;
- -- ddr3_I : NATURAL;
- -- ddr3_II : NATURAL;
- -- adc : NATURAL;
- -- wdi : NATURAL;
- -- END RECORD;
+ -- Use PHY Interface
+ -- TYPE t_c_unb_use_phy IS RECORD
+ -- eth1g : NATURAL;
+ -- tr_front: NATURAL;
+ -- tr_mesh : NATURAL;
+ -- tr_back : NATURAL;
+ -- ddr3_I : NATURAL;
+ -- ddr3_II : NATURAL;
+ -- adc : NATURAL;
+ -- wdi : NATURAL;
+ -- END RECORD;
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 0, 0, 1, 0, 0, 1);
constant c_aux : t_c_unb1_board_aux := c_unb1_board_aux;
constant c_app_led_en : boolean := true;
@@ -142,9 +142,9 @@ architecture str of unb1_ddr3 is
signal eth1g_reg_interrupt : std_logic; -- Interrupt
signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
signal eth1g_ram_miso : t_mem_miso;
--- SIGNAL eth1g_led : t_tech_tse_led;
+ -- SIGNAL eth1g_led : t_tech_tse_led;
- -- . UniBoard I2C sens
+ -- . UniBoard I2C sens
signal reg_unb_sens_mosi : t_mem_mosi;
signal reg_unb_sens_miso : t_mem_miso;
@@ -174,243 +174,243 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- -- General
- g_sim => g_sim,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_name => c_design_name,
- g_design_note => c_design_note,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_dp_clk_use_pll => false,
- g_app_led_red => c_app_led_en,
- g_app_led_green => c_app_led_en,
- g_use_phy => c_use_phy,
- g_aux => c_aux
- )
- port map (
- --
- -- >>> SOPC system with conduit peripheral MM bus
- --
- -- System
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => OPEN,
- dp_clk => OPEN,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => OPEN,
-
- app_led_red => app_led_red,
- app_led_green => app_led_green,
-
- -- PIOs
- pout_debug_wave => pout_debug_wave,
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- --
- -- >>> Ctrl FPGA pins
- --
- -- General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ -- General
+ g_sim => g_sim,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_name => c_design_name,
+ g_design_note => c_design_note,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_dp_clk_use_pll => false,
+ g_app_led_red => c_app_led_en,
+ g_app_led_green => c_app_led_en,
+ g_use_phy => c_use_phy,
+ g_aux => c_aux
+ )
+ port map (
+ --
+ -- >>> SOPC system with conduit peripheral MM bus
+ --
+ -- System
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => OPEN,
+ dp_clk => OPEN,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => OPEN,
+
+ app_led_red => app_led_red,
+ app_led_green => app_led_green,
+
+ -- PIOs
+ pout_debug_wave => pout_debug_wave,
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ --
+ -- >>> Ctrl FPGA pins
+ --
+ -- General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
u_mmm : entity work.mmm_unb1_ddr3
- generic map(
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map (
- -- GENERAL
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- cal_clk => cal_clk,
-
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- DDR3
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Data Buffer Control
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- Data Buffer Data
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-
- -- Block Generator Control
- reg_diag_bg_ctrl_mosi => reg_diag_bg_ctrl_mosi,
- reg_diag_bg_ctrl_miso => reg_diag_bg_ctrl_miso,
-
- -- Block Generator Data
- ram_diag_bg_data_mosi => ram_diag_bg_data_mosi,
- ram_diag_bg_data_miso => ram_diag_bg_data_miso,
-
- -- TX Sequencer
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
-
- -- RX Sequencer
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map (
+ -- GENERAL
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ cal_clk => cal_clk,
+
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- DDR3
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Data Buffer Control
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- Data Buffer Data
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+
+ -- Block Generator Control
+ reg_diag_bg_ctrl_mosi => reg_diag_bg_ctrl_mosi,
+ reg_diag_bg_ctrl_miso => reg_diag_bg_ctrl_miso,
+
+ -- Block Generator Data
+ ram_diag_bg_data_mosi => ram_diag_bg_data_mosi,
+ ram_diag_bg_data_miso => ram_diag_bg_data_miso,
+
+ -- TX Sequencer
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ -- RX Sequencer
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso
+ );
u_areset_ddr_ref_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 40
- )
- port map(
- clk => CLK,
- in_rst => mm_rst,
- out_rst => ddr_ref_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ port map(
+ clk => CLK,
+ in_rst => mm_rst,
+ out_rst => ddr_ref_rst
+ );
u_node : entity work.node_unb1_ddr3
- generic map (
- g_sim => g_sim,
- g_technology => c_technology,
- g_tech_ddr => c_tech_ddr,
- g_st_dat_w => g_st_dat_w
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ddr_ref_clk => CLK,
- ddr_ref_rst => ddr_ref_rst,
-
- -- Clock outputs
- ddr_out_clk => dp_clk,
- ddr_out_rst => dp_rst,
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Data Buffer Control
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- Data Buffer Data
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-
- -- Block Generator Control
- reg_diag_bg_ctrl_mosi => reg_diag_bg_ctrl_mosi,
- reg_diag_bg_ctrl_miso => reg_diag_bg_ctrl_miso,
-
- -- Block Generator Data
- ram_diag_bg_data_mosi => ram_diag_bg_data_mosi,
- ram_diag_bg_data_miso => ram_diag_bg_data_miso,
-
- -- TX Sequencer
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
-
- -- RX Sequencer
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
-
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => c_technology,
+ g_tech_ddr => c_tech_ddr,
+ g_st_dat_w => g_st_dat_w
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ddr_ref_clk => CLK,
+ ddr_ref_rst => ddr_ref_rst,
+
+ -- Clock outputs
+ ddr_out_clk => dp_clk,
+ ddr_out_rst => dp_rst,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Data Buffer Control
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- Data Buffer Data
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+
+ -- Block Generator Control
+ reg_diag_bg_ctrl_mosi => reg_diag_bg_ctrl_mosi,
+ reg_diag_bg_ctrl_miso => reg_diag_bg_ctrl_miso,
+
+ -- Block Generator Data
+ ram_diag_bg_data_mosi => ram_diag_bg_data_mosi,
+ ram_diag_bg_data_miso => ram_diag_bg_data_miso,
+
+ -- TX Sequencer
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ -- RX Sequencer
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
index 55751e463f..53af01aa6c 100644
--- a/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
@@ -31,20 +31,20 @@
-- > python tc_unb1_ddr3_seq.py --sim --unb 0 --fn 3 --rep 3
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib, tech_ddr_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
entity tb_unb1_ddr3 is
generic (
@@ -71,7 +71,7 @@ architecture tb of tb_unb1_ddr3 is
constant c_ext_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
- -- SO-DIMM Memory Bank I = ddr3_I
+ -- SO-DIMM Memory Bank I = ddr3_I
signal MB_I_in : t_tech_ddr3_phy_in;
signal MB_I_io : t_tech_ddr3_phy_io;
signal MB_I_ou : t_tech_ddr3_phy_ou;
@@ -96,7 +96,7 @@ architecture tb of tb_unb1_ddr3 is
signal sens_scl : std_logic;
signal sens_sda : std_logic;
begin
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
clk <= not clk after c_ext_clk_period / 2; -- External clock (200 MHz)
@@ -123,51 +123,51 @@ begin
------------------------------------------------------------------------------
dut : entity work.unb1_ddr3
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- -- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
- g_st_dat_w => c_st_dat_w
-
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- SO-DIMM Memory Bank I = ddr3_I
- MB_I_IN => MB_I_in,
- MB_I_IO => MB_I_io,
- MB_I_OU => MB_I_ou
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ -- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
+ g_st_dat_w => c_st_dat_w
+
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- SO-DIMM Memory Bank I = ddr3_I
+ MB_I_IN => MB_I_in,
+ MB_I_IO => MB_I_io,
+ MB_I_OU => MB_I_ou
+ );
------------------------------------------------------------------------------
-- DDR3 memory model
------------------------------------------------------------------------------
u_tech_ddr_memory_model : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr
- )
- port map (
- mem3_in => MB_I_ou,
- mem3_io => MB_I_io,
- mem3_ou => MB_I_in
- );
+ generic map (
+ g_tech_ddr => c_ddr
+ )
+ port map (
+ mem3_in => MB_I_ou,
+ mem3_io => MB_I_io,
+ mem3_ou => MB_I_in
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
index f2880d95ff..d57b0475cf 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
@@ -20,20 +20,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb1_ddr3_reorder_dual_rank is
- generic (
- g_design_name : string := "unb1_ddr3_reorder_dual_rank";
- g_design_note : string := "Reference Reorder";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7; -- Back node 3
- g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master
- );
+ generic (
+ g_design_name : string := "unb1_ddr3_reorder_dual_rank";
+ g_design_note : string := "Reference Reorder";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7; -- Back node 3
+ g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master
+ );
end tb_unb1_ddr3_reorder_dual_rank;
architecture tb of tb_unb1_ddr3_reorder_dual_rank is
@@ -45,5 +45,5 @@ begin
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_tech_ddr => g_tech_ddr
- );
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
index 5622c88c07..d119750585 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_ddr3_reorder_dual_rank is
generic (
@@ -73,35 +73,35 @@ end unb1_ddr3_reorder_dual_rank;
architecture str of unb1_ddr3_reorder_dual_rank is
begin
u_revision : entity work.unb1_ddr3_reorder
- generic map(
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_use_MB_I => g_use_MB_I,
- g_tech_ddr => g_tech_ddr,
- g_aux => g_aux
- )
- port map(
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
- );
+ generic map(
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_use_MB_I => g_use_MB_I,
+ g_tech_ddr => g_tech_ddr,
+ g_aux => g_aux
+ )
+ port map(
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
index 01306cde2b..f72f1cf435 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
@@ -20,20 +20,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb1_ddr3_reorder_single_rank is
- generic (
- g_design_name : string := "unb1_ddr3_reorder_single_rank";
- g_design_note : string := "Reference Reorder";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7; -- Back node 3
- g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master
- );
+ generic (
+ g_design_name : string := "unb1_ddr3_reorder_single_rank";
+ g_design_note : string := "Reference Reorder";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7; -- Back node 3
+ g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master
+ );
end tb_unb1_ddr3_reorder_single_rank;
architecture tb of tb_unb1_ddr3_reorder_single_rank is
@@ -45,5 +45,5 @@ begin
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_tech_ddr => g_tech_ddr
- );
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
index 5bd73002e0..79dae4235c 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_ddr3_reorder_single_rank is
generic (
@@ -73,35 +73,35 @@ end unb1_ddr3_reorder_single_rank;
architecture str of unb1_ddr3_reorder_single_rank is
begin
u_revision : entity work.unb1_ddr3_reorder
- generic map(
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_use_MB_I => g_use_MB_I,
- g_tech_ddr => g_tech_ddr,
- g_aux => g_aux
- )
- port map(
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
- );
+ generic map(
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_use_MB_I => g_use_MB_I,
+ g_tech_ddr => g_tech_ddr,
+ g_aux => g_aux
+ )
+ port map(
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
index 34532416bb..7151b74665 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
@@ -20,24 +20,24 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, dp_lib, reorder_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use reorder_lib.reorder_pkg.all;
-use technology_lib.technology_select_pkg.all;
---USE tech_ddr_lib.tech_ddr_pkg.ALL;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use reorder_lib.reorder_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ --USE tech_ddr_lib.tech_ddr_pkg.ALL;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity mmm_unb1_ddr3_reorder is
generic (
@@ -46,7 +46,7 @@ entity mmm_unb1_ddr3_reorder is
g_sim_node_nr : natural := 0;
g_nof_streams : natural := 4;
g_reorder_seq : t_reorder_seq := c_reorder_seq
- );
+ );
port (
-- GENERAL
xo_clk : in std_logic;
@@ -174,47 +174,61 @@ begin
i_cal_clk <= not i_cal_clk after c_cal_clk_period / 2;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_reg_diag_tx_seq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ")
- port map(mm_rst, i_mm_clk, reg_diag_tx_seq_mosi, reg_diag_tx_seq_miso );
+ u_mm_file_reg_diag_tx_seq : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ")
+ port map(mm_rst, i_mm_clk, reg_diag_tx_seq_mosi, reg_diag_tx_seq_miso );
- u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+ u_mm_file_ram_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
- u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+ u_mm_file_reg_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
- u_mm_file_reg_diag_rx_seq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ")
- port map(mm_rst, i_mm_clk, reg_diag_rx_seq_mosi, reg_diag_rx_seq_miso );
+ u_mm_file_reg_diag_rx_seq : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ")
+ port map(mm_rst, i_mm_clk, reg_diag_rx_seq_mosi, reg_diag_rx_seq_miso );
- u_mm_file_ram_ss_ss_transp : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
+ u_mm_file_ram_ss_ss_transp : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ port map(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
- u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso);
+ u_mm_file_reg_bsn_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+ port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso);
- u_mm_file_reg_io_ddr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
- port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+ u_mm_file_reg_io_ddr : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
+ port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -238,10 +252,10 @@ begin
p_switch : process(mm_bus_switch, eth1g_reg_proc_mosi, i_eth1g_reg_mosi)
begin
if mm_bus_switch = '1' then
- eth1g_reg_mosi <= eth1g_reg_proc_mosi;
- else
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
- end if;
+ eth1g_reg_mosi <= eth1g_reg_proc_mosi;
+ else
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -256,170 +270,170 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_ddr3_reorder
- port map (
- clk_0 => xo_clk,
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk,
- tse_clk => i_tse_clk,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb_common.
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg: entry for the register space of the block generator
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_rx_seq: entry for the register space of the rx sequencer
- coe_clk_export_from_the_reg_diag_rx_seq => OPEN,
- coe_reset_export_from_the_reg_diag_rx_seq => OPEN,
- coe_address_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.address(c_reg_diag_rx_seq_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.rd,
- coe_readdata_export_to_the_reg_diag_rx_seq => reg_diag_rx_seq_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wr,
- coe_writedata_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_tx_seq: entry for the register space of the tx sequencer
- coe_clk_export_from_the_reg_diag_tx_seq => OPEN,
- coe_reset_export_from_the_reg_diag_tx_seq => OPEN,
- coe_address_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.address(c_reg_diag_tx_seq_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.rd,
- coe_readdata_export_to_the_reg_diag_tx_seq => reg_diag_tx_seq_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wr,
- coe_writedata_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg: entry for the ram space of the block generator
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buf: register space for the databuffer
- coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
- coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
- coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_reg_diag_data_buf_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buf: ram space for the databuffer
- coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
- coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
- coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_ram_diag_data_buf_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_ss_ss_transp: ram space for the subband select unit
- coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
- coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
- coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.rd,
- coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_transp_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wr,
- coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(1 downto 0),
- coe_clk_export_from_the_reg_io_ddr => OPEN,
- coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
- coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_io_ddr => OPEN,
- coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
- coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(3 + c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_bsn_monitor => OPEN,
- coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_bsn_monitor => OPEN,
- coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => i_tse_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb_common.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg: entry for the register space of the block generator
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_rx_seq: entry for the register space of the rx sequencer
+ coe_clk_export_from_the_reg_diag_rx_seq => OPEN,
+ coe_reset_export_from_the_reg_diag_rx_seq => OPEN,
+ coe_address_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.address(c_reg_diag_rx_seq_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_rx_seq => reg_diag_rx_seq_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_tx_seq: entry for the register space of the tx sequencer
+ coe_clk_export_from_the_reg_diag_tx_seq => OPEN,
+ coe_reset_export_from_the_reg_diag_tx_seq => OPEN,
+ coe_address_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.address(c_reg_diag_tx_seq_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_tx_seq => reg_diag_tx_seq_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg: entry for the ram space of the block generator
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buf: register space for the databuffer
+ coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_reg_diag_data_buf_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buf: ram space for the databuffer
+ coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_ram_diag_data_buf_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_ss_ss_transp: ram space for the subband select unit
+ coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.rd,
+ coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_transp_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wr,
+ coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(1 downto 0),
+ coe_clk_export_from_the_reg_io_ddr => OPEN,
+ coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
+ coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_io_ddr => OPEN,
+ coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
+ coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(3 + c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_bsn_monitor => OPEN,
+ coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_bsn_monitor => OPEN,
+ coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
index 2af884041a..95f652be5a 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, reorder_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use reorder_lib.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use reorder_lib.reorder_pkg.all;
entity node_unb1_ddr3_reorder is
generic (
@@ -43,7 +43,7 @@ entity node_unb1_ddr3_reorder is
g_frame_size_out : natural := 176;
g_reorder_seq : t_reorder_seq := c_reorder_seq
);
-port (
+ port (
-- System
mm_rst : in std_logic;
mm_clk : in std_logic;
@@ -139,27 +139,27 @@ architecture str of node_unb1_ddr3_reorder is
signal bsn_sosi_arr : t_dp_sosi_arr(3 downto 0) := (others => c_dp_sosi_rst);
begin
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => c_nof_bsn_streams, -- Check one input and one output stream
- g_cross_clock_domain => true,
- g_bsn_w => c_dp_stream_bsn_w,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_log_first_bsn => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- -- Streaming clock domain
- dp_rst => ddr_out_rst_i,
- dp_clk => ddr_out_clk_i,
- in_siso_arr => (others => c_dp_siso_rdy),
- in_sosi_arr => bsn_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_bsn_streams, -- Check one input and one output stream
+ g_cross_clock_domain => true,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_log_first_bsn => true
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ -- Streaming clock domain
+ dp_rst => ddr_out_rst_i,
+ dp_clk => ddr_out_clk_i,
+ in_siso_arr => (others => c_dp_siso_rdy),
+ in_sosi_arr => bsn_sosi_arr
+ );
bsn_sosi_arr(0) <= bg_sosi_arr(0);
bsn_sosi_arr(1) <= to_mem_sosi;
@@ -170,113 +170,113 @@ begin
-- TRANSPOSE UNIT
------------------------------------------------------------------------------
u_transpose: entity reorder_lib.reorder_transpose
- generic map(
- g_nof_streams => g_nof_streams,
- g_in_dat_w => g_in_dat_w,
- g_frame_size_in => g_frame_size_in,
- g_frame_size_out => g_frame_size_out,
- g_use_complex => c_use_complex,
- g_ena_pre_transp => g_ena_pre_transp,
- g_reorder_seq => g_reorder_seq
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => ddr_out_rst_i,
- dp_clk => ddr_out_clk_i,
-
- -- ST sink
- snk_out_arr => bg_siso_arr,
- snk_in_arr => bg_sosi_arr,
-
- -- ST source
- src_in_arr => db_siso_arr,
- src_out_arr => db_sosi_arr,
-
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- -- Control interface to the external memory
- dvr_miso => ctlr_dvr_miso,
- dvr_mosi => ctlr_dvr_mosi,
-
- -- Data interface to the external memory
- to_mem_src_out => to_mem_sosi,
- to_mem_src_in => to_mem_siso,
-
- from_mem_snk_in => from_mem_sosi,
- from_mem_snk_out => from_mem_siso
-
- );
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_in_dat_w => g_in_dat_w,
+ g_frame_size_in => g_frame_size_in,
+ g_frame_size_out => g_frame_size_out,
+ g_use_complex => c_use_complex,
+ g_ena_pre_transp => g_ena_pre_transp,
+ g_reorder_seq => g_reorder_seq
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => ddr_out_rst_i,
+ dp_clk => ddr_out_clk_i,
+
+ -- ST sink
+ snk_out_arr => bg_siso_arr,
+ snk_in_arr => bg_sosi_arr,
+
+ -- ST source
+ src_in_arr => db_siso_arr,
+ src_out_arr => db_sosi_arr,
+
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- Control interface to the external memory
+ dvr_miso => ctlr_dvr_miso,
+ dvr_mosi => ctlr_dvr_mosi,
+
+ -- Data interface to the external memory
+ to_mem_src_out => to_mem_sosi,
+ to_mem_src_in => to_mem_siso,
+
+ from_mem_snk_in => from_mem_sosi,
+ from_mem_snk_out => from_mem_siso
+
+ );
------------------------------------------------------------------------------
-- DDR3 MODULE 0, MB_I
------------------------------------------------------------------------------
u_ddr_mem_ctrl : entity io_ddr_lib.io_ddr
- generic map(
- g_technology => g_tech_select_default,
- g_tech_ddr => g_tech_ddr,
- g_cross_domain_dvr_ctlr => false,
- g_wr_data_w => c_data_w,
- g_wr_fifo_depth => c_fifo_depth,
- g_rd_fifo_depth => c_fifo_depth,
- g_rd_data_w => c_data_w,
- g_wr_flush_mode => "SYN",
- g_wr_flush_use_channel => false,
- g_wr_flush_start_channel => 0,
- g_wr_flush_nof_channels => 1
- )
- port map (
- -- DDR reference clock
- ctlr_ref_clk => ddr_ref_clk,
- ctlr_ref_rst => ddr_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_out_clk_i, -- output clock of the ddr controller is used as DP clk.
- ctlr_rst_out => ddr_out_rst_i,
-
- ctlr_clk_in => ddr_out_clk_i,
- ctlr_rst_in => ddr_out_rst_i,
-
- -- MM clock + reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- MM register map for DDR controller status info
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Driver clock domain
- dvr_clk => ddr_out_clk_i,
- dvr_rst => ddr_out_rst_i,
-
- dvr_miso => ctlr_dvr_miso,
- dvr_mosi => ctlr_dvr_mosi,
-
- -- Write FIFO clock domain
- wr_clk => ddr_out_clk_i,
- wr_rst => ddr_out_rst_i,
-
- wr_fifo_usedw => OPEN,
- wr_sosi => to_mem_sosi,
- wr_siso => to_mem_siso,
-
- -- Read FIFO clock domain
- rd_clk => ddr_out_clk_i,
- rd_rst => ddr_out_rst_i,
-
- rd_fifo_usedw => OPEN,
- rd_sosi => from_mem_sosi,
- rd_siso => from_mem_siso,
-
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
- phy3_in => MB_I_IN,
- phy3_io => MB_I_IO,
- phy3_ou => MB_I_OU
- );
+ generic map(
+ g_technology => g_tech_select_default,
+ g_tech_ddr => g_tech_ddr,
+ g_cross_domain_dvr_ctlr => false,
+ g_wr_data_w => c_data_w,
+ g_wr_fifo_depth => c_fifo_depth,
+ g_rd_fifo_depth => c_fifo_depth,
+ g_rd_data_w => c_data_w,
+ g_wr_flush_mode => "SYN",
+ g_wr_flush_use_channel => false,
+ g_wr_flush_start_channel => 0,
+ g_wr_flush_nof_channels => 1
+ )
+ port map (
+ -- DDR reference clock
+ ctlr_ref_clk => ddr_ref_clk,
+ ctlr_ref_rst => ddr_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_out_clk_i, -- output clock of the ddr controller is used as DP clk.
+ ctlr_rst_out => ddr_out_rst_i,
+
+ ctlr_clk_in => ddr_out_clk_i,
+ ctlr_rst_in => ddr_out_rst_i,
+
+ -- MM clock + reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- MM register map for DDR controller status info
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Driver clock domain
+ dvr_clk => ddr_out_clk_i,
+ dvr_rst => ddr_out_rst_i,
+
+ dvr_miso => ctlr_dvr_miso,
+ dvr_mosi => ctlr_dvr_mosi,
+
+ -- Write FIFO clock domain
+ wr_clk => ddr_out_clk_i,
+ wr_rst => ddr_out_rst_i,
+
+ wr_fifo_usedw => OPEN,
+ wr_sosi => to_mem_sosi,
+ wr_siso => to_mem_siso,
+
+ -- Read FIFO clock domain
+ rd_clk => ddr_out_clk_i,
+ rd_rst => ddr_out_rst_i,
+
+ rd_fifo_usedw => OPEN,
+ rd_sosi => from_mem_sosi,
+ rd_siso => from_mem_siso,
+
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ phy3_in => MB_I_IN,
+ phy3_io => MB_I_IO,
+ phy3_ou => MB_I_OU
+ );
ddr_out_clk <= ddr_out_clk_i;
ddr_out_rst <= ddr_out_rst_i;
@@ -285,68 +285,68 @@ begin
-- DIAG Block Generator
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- -- Generate configurations
- g_use_usr_input => false,
- g_use_bg => true,
- g_use_tx_seq => true,
- -- General
- g_nof_streams => g_nof_streams,
- -- BG settings
- g_use_bg_buffer_ram => false,
- -- Tx_seq
- g_seq_dat_w => c_data_w
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => ddr_out_rst_i,
- dp_clk => ddr_out_clk_i,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map (
+ -- Generate configurations
+ g_use_usr_input => false,
+ g_use_bg => true,
+ g_use_tx_seq => true,
+ -- General
+ g_nof_streams => g_nof_streams,
+ -- BG settings
+ g_use_bg_buffer_ram => false,
+ -- Tx_seq
+ g_seq_dat_w => c_data_w
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => ddr_out_rst_i,
+ dp_clk => ddr_out_clk_i,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
-----------------------------------------------------------------------------
-- DIAG Rx seq with optional Data Buffer
-----------------------------------------------------------------------------
u_mms_diag_data_buffer: entity diag_lib.mms_diag_data_buffer
- generic map (
- -- Generate configurations
- g_use_db => c_use_db,
- g_use_rx_seq => c_use_rx_seq,
- -- General
- g_nof_streams => g_nof_streams,
- -- DB settings
- g_data_type => e_data, -- define the sosi field that gets stored: e_data=data, e_complex=im&re, e_real=re, e_imag=im,
- g_data_w => c_data_w,
- g_buf_nof_data => c_buf_nof_data,
- g_buf_use_sync => c_buf_use_sync, -- when TRUE start filling the buffer at the in_sync, else after the last word was read,
- -- Rx_seq
- g_use_steps => c_use_steps,
- g_seq_dat_w => c_data_w
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => ddr_out_rst_i,
- dp_clk => ddr_out_clk_i,
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- -- ST interface
- in_sosi_arr => db_sosi_arr
- );
+ generic map (
+ -- Generate configurations
+ g_use_db => c_use_db,
+ g_use_rx_seq => c_use_rx_seq,
+ -- General
+ g_nof_streams => g_nof_streams,
+ -- DB settings
+ g_data_type => e_data, -- define the sosi field that gets stored: e_data=data, e_complex=im&re, e_real=re, e_imag=im,
+ g_data_w => c_data_w,
+ g_buf_nof_data => c_buf_nof_data,
+ g_buf_use_sync => c_buf_use_sync, -- when TRUE start filling the buffer at the in_sync, else after the last word was read,
+ -- Rx_seq
+ g_use_steps => c_use_steps,
+ g_seq_dat_w => c_data_w
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => ddr_out_rst_i,
+ dp_clk => ddr_out_clk_i,
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ -- ST interface
+ in_sosi_arr => db_sosi_arr
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
index a0f4448402..9dac90343e 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
@@ -20,18 +20,18 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, technology_lib, tech_ddr_lib, diag_lib, reorder_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use eth_lib.eth_pkg.all;
-use diag_lib.diag_pkg.all;
-use reorder_lib.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use reorder_lib.reorder_pkg.all;
entity unb1_ddr3_reorder is
generic (
@@ -95,12 +95,13 @@ architecture str of unb1_ddr3_reorder is
constant c_nof_blocks : natural := sel_a_b(g_sim, 16, 800000);
constant c_nof_streams : natural := 1;
constant c_in_dat_w : natural := 64;
- constant c_reorder_seq_conf : t_reorder_seq := (c_wr_chunksize,
- c_rd_chunksize,
- c_rd_nof_chunks,
- c_rd_interval,
- c_gapsize,
- c_nof_blocks);
+ constant c_reorder_seq_conf : t_reorder_seq := (
+ c_wr_chunksize,
+ c_rd_chunksize,
+ c_rd_nof_chunks,
+ c_rd_interval,
+ c_gapsize,
+ c_nof_blocks);
-- System
signal cs_sim : std_logic;
@@ -173,7 +174,7 @@ architecture str of unb1_ddr3_reorder is
signal reg_io_ddr_mosi : t_mem_mosi;
signal reg_io_ddr_miso : t_mem_miso;
- -- . UniBoard I2C sens
+ -- . UniBoard I2C sens
signal reg_unb_sens_mosi : t_mem_mosi;
signal reg_unb_sens_miso : t_mem_miso;
@@ -192,262 +193,262 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- -- General
- g_sim => g_sim,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_dp_clk_use_pll => false,
- g_app_led_red => c_app_led_en,
- g_app_led_green => c_app_led_en,
- g_use_phy => c_use_phy,
- g_aux => c_aux
- )
- port map (
- --
- -- >>> SOPC system with conduit peripheral MM bus
- --
- -- System
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => OPEN, -- dp_rst,
- dp_clk => OPEN, -- dp_clk, -- dp_clk is now generated in the DDR controller
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => OPEN,
-
- app_led_red => app_led_red,
- app_led_green => app_led_green,
-
- -- PIOs
- pout_debug_wave => pout_debug_wave,
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ -- General
+ g_sim => g_sim,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_dp_clk_use_pll => false,
+ g_app_led_red => c_app_led_en,
+ g_app_led_green => c_app_led_en,
+ g_use_phy => c_use_phy,
+ g_aux => c_aux
+ )
+ port map (
+ --
+ -- >>> SOPC system with conduit peripheral MM bus
+ --
+ -- System
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => OPEN, -- dp_rst,
+ dp_clk => OPEN, -- dp_clk, -- dp_clk is now generated in the DDR controller
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => OPEN,
+
+ app_led_red => app_led_red,
+ app_led_green => app_led_green,
+
+ -- PIOs
+ pout_debug_wave => pout_debug_wave,
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
u_mmm : entity work.mmm_unb1_ddr3_reorder
- generic map(
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_nof_streams => c_nof_streams,
- g_reorder_seq => c_reorder_seq_conf
- )
- port map (
- -- GENERAL
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- cal_clk => cal_clk,
-
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- Blockgenerator
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
-
- -- TX Sequencer
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
-
- -- DDR3 transpose
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- Databuffers
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- RX Sequencer
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
-
- -- BSN monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- -- IO DDR register map
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso
-
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_nof_streams => c_nof_streams,
+ g_reorder_seq => c_reorder_seq_conf
+ )
+ port map (
+ -- GENERAL
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ cal_clk => cal_clk,
+
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- Blockgenerator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+
+ -- TX Sequencer
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ -- DDR3 transpose
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- Databuffers
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- RX Sequencer
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ -- BSN monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ -- IO DDR register map
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso
+
+ );
u_areset_ddr_ref_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 40
- )
- port map(
- clk => CLK,
- in_rst => '0',
- out_rst => ddr_ref_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ port map(
+ clk => CLK,
+ in_rst => '0',
+ out_rst => ddr_ref_rst
+ );
u_node : entity work.node_unb1_ddr3_reorder
- generic map(
- g_sim => g_sim,
- g_use_MB_I => g_use_MB_I,
- g_tech_ddr => g_tech_ddr,
- g_nof_streams => c_nof_streams,
- g_in_dat_w => c_in_dat_w,
- g_ena_pre_transp => c_ena_pre_transp,
- g_frame_size_in => c_frame_size_in,
- g_frame_size_out => c_frame_size_out,
- g_reorder_seq => c_reorder_seq_conf
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ddr_ref_clk => CLK, -- Provide external 200 MHZ clk to DDR controller
- ddr_ref_rst => ddr_ref_rst,
-
- -- Clock outputs
- ddr_out_clk => dp_clk,
- ddr_out_rst => dp_rst, -- dp_clk is generated by DDR controller
-
- -- IO DDR register map
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Reorder transpose
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- -- BSN monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- -- Data Buffer Control
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- Data Buffer Data
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-
- -- Blockgenerator Control
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
-
- -- Blockgenerator Data
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
-
- -- TX Sequencer
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
-
- -- RX Sequencer
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
-
- -- SO-DIMM Memory Bank I = ddr3_I
- MB_I_in => MB_I_IN,
- MB_I_io => MB_I_IO,
- MB_I_ou => MB_I_OU
- );
+ generic map(
+ g_sim => g_sim,
+ g_use_MB_I => g_use_MB_I,
+ g_tech_ddr => g_tech_ddr,
+ g_nof_streams => c_nof_streams,
+ g_in_dat_w => c_in_dat_w,
+ g_ena_pre_transp => c_ena_pre_transp,
+ g_frame_size_in => c_frame_size_in,
+ g_frame_size_out => c_frame_size_out,
+ g_reorder_seq => c_reorder_seq_conf
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ddr_ref_clk => CLK, -- Provide external 200 MHZ clk to DDR controller
+ ddr_ref_rst => ddr_ref_rst,
+
+ -- Clock outputs
+ ddr_out_clk => dp_clk,
+ ddr_out_rst => dp_rst, -- dp_clk is generated by DDR controller
+
+ -- IO DDR register map
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Reorder transpose
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- BSN monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ -- Data Buffer Control
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- Data Buffer Data
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+
+ -- Blockgenerator Control
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+
+ -- Blockgenerator Data
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+
+ -- TX Sequencer
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ -- RX Sequencer
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ -- SO-DIMM Memory Bank I = ddr3_I
+ MB_I_in => MB_I_IN,
+ MB_I_io => MB_I_IO,
+ MB_I_ou => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
index 013700e866..56ec351ac9 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
@@ -27,29 +27,29 @@
library ip_stratixiv_ddr3_mem_model_lib;
library IEEE, common_lib, unb1_board_lib, i2c_lib, dp_lib, io_ddr_lib, eth_lib, technology_lib, tech_ddr_lib, diag_lib, reorder_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
-use eth_lib.eth_pkg.all;
-use diag_lib.diag_pkg.all;
-use reorder_lib.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use reorder_lib.reorder_pkg.all;
entity tb_unb1_ddr3_reorder is
- generic (
- g_design_name : string := "unb1_ddr3_reorder";
- g_design_note : string := "Reference Reorder";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7; -- Back node 3
- g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master
- );
+ generic (
+ g_design_name : string := "unb1_ddr3_reorder";
+ g_design_note : string := "Reference Reorder";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7; -- Back node 3
+ g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master
+ );
end tb_unb1_ddr3_reorder;
architecture tb of tb_unb1_ddr3_reorder is
@@ -123,7 +123,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
- ------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
-- 1GbE Loopback model
------------------------------------------------------------------------------
eth_rxp <= transport eth_txp after c_cable_delay;
@@ -171,50 +171,50 @@ begin
-- DDR3 memory model
------------------------------------------------------------------------------
u_tech_ddr_memory_model : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => g_tech_ddr
- )
- port map (
- mem3_in => phy_ou,
- mem3_io => phy_io,
- mem3_ou => phy_in
- );
+ generic map (
+ g_tech_ddr => g_tech_ddr
+ )
+ port map (
+ mem3_in => phy_ou,
+ mem3_io => phy_io,
+ mem3_ou => phy_in
+ );
------------------------------------------------------------------------------
-- UniBoard sensors
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
index 6687a715a0..e66462326b 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use common_lib.common_field_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity mmm_unb_ddr3_transpose is
generic (
@@ -135,51 +135,66 @@ begin
i_mm_clk <= not i_mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_clk_period * 5;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_ram_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_RE")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+ u_mm_file_ram_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_RE")
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
- u_mm_file_reg_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_RE")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+ u_mm_file_reg_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_RE")
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
- u_mm_file_ram_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_IM")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+ u_mm_file_ram_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_IM")
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
- u_mm_file_reg_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_IM")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+ u_mm_file_reg_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_IM")
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
- u_mm_file_ram_ss_ss_transp : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
+ u_mm_file_ram_ss_ss_transp : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ port map(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
- u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+ u_mm_file_reg_bsn_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+ port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
- u_mm_file_reg_io_ddr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
- port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+ u_mm_file_reg_io_ddr : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
+ port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -193,169 +208,169 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb_ddr3_transpose
- port map (
- clk_0 => xo_clk,
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk,
- tse_clk => eth1g_tse_clk,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb_common.
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg: entry for the register space of the block generator
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg: entry for the ram space of the block generator
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buf_im: register space for the imaginary databuffer
- coe_clk_export_from_the_reg_diag_data_buffer_im => OPEN,
- coe_reset_export_from_the_reg_diag_data_buffer_im => OPEN,
- coe_address_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.address(c_reg_diag_data_buf_im_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buf_im: ram space for the imaginary databuffer
- coe_clk_export_from_the_ram_diag_data_buffer_im => OPEN,
- coe_reset_export_from_the_ram_diag_data_buffer_im => OPEN,
- coe_address_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.address(c_ram_diag_data_buf_im_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buf_re: register space for the real databuffer
- coe_clk_export_from_the_reg_diag_data_buffer_re => OPEN,
- coe_reset_export_from_the_reg_diag_data_buffer_re => OPEN,
- coe_address_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.address(c_reg_diag_data_buf_re_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buf_re: ram space for the real databuffer
- coe_clk_export_from_the_ram_diag_data_buffer_re => OPEN,
- coe_reset_export_from_the_ram_diag_data_buffer_re => OPEN,
- coe_address_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.address(c_ram_diag_data_buf_re_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_ss_ss_transp: ram space for the subband select unit
- coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
- coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
- coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.rd,
- coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_transp_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wr,
- coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_io_ddr
- coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(1 downto 0),
- coe_clk_export_from_the_reg_io_ddr => OPEN,
- coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
- coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_io_ddr => OPEN,
- coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
- coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(1 + c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_bsn_monitor => OPEN,
- coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_bsn_monitor => OPEN,
- coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => eth1g_tse_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb_common.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg: entry for the register space of the block generator
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg: entry for the ram space of the block generator
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buf_im: register space for the imaginary databuffer
+ coe_clk_export_from_the_reg_diag_data_buffer_im => OPEN,
+ coe_reset_export_from_the_reg_diag_data_buffer_im => OPEN,
+ coe_address_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.address(c_reg_diag_data_buf_im_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buf_im: ram space for the imaginary databuffer
+ coe_clk_export_from_the_ram_diag_data_buffer_im => OPEN,
+ coe_reset_export_from_the_ram_diag_data_buffer_im => OPEN,
+ coe_address_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.address(c_ram_diag_data_buf_im_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buf_re: register space for the real databuffer
+ coe_clk_export_from_the_reg_diag_data_buffer_re => OPEN,
+ coe_reset_export_from_the_reg_diag_data_buffer_re => OPEN,
+ coe_address_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.address(c_reg_diag_data_buf_re_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buf_re: ram space for the real databuffer
+ coe_clk_export_from_the_ram_diag_data_buffer_re => OPEN,
+ coe_reset_export_from_the_ram_diag_data_buffer_re => OPEN,
+ coe_address_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.address(c_ram_diag_data_buf_re_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_ss_ss_transp: ram space for the subband select unit
+ coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.rd,
+ coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_transp_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wr,
+ coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_io_ddr
+ coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(1 downto 0),
+ coe_clk_export_from_the_reg_io_ddr => OPEN,
+ coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
+ coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_io_ddr => OPEN,
+ coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
+ coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(1 + c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_bsn_monitor => OPEN,
+ coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_bsn_monitor => OPEN,
+ coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
index 1f1463d40d..6501e3bee6 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
@@ -21,16 +21,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, eth_lib, diag_lib, dp_lib, ddr3_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use eth_lib.eth_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity unb1_ddr3_transpose is
generic (
@@ -88,12 +88,13 @@ architecture str of unb1_ddr3_transpose is
constant c_gapsize : natural := sel_a_b(g_sim, 0, 0); -- 0);
constant c_nof_blocks : positive := sel_a_b(g_sim, 4, 4); -- 16);
- constant c_ddr3_seq_conf : t_ddr3_seq := (c_wr_chunksize,
- c_wr_nof_chunks,
- c_rd_chunksize,
- c_rd_nof_chunks,
- c_gapsize,
- c_nof_blocks);
+ constant c_ddr3_seq_conf : t_ddr3_seq := (
+ c_wr_chunksize,
+ c_wr_nof_chunks,
+ c_rd_chunksize,
+ c_rd_nof_chunks,
+ c_gapsize,
+ c_nof_blocks);
constant c_blocksize : positive := c_wr_nof_chunks * c_wr_chunksize;
@@ -215,333 +216,333 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_dp_clk_use_pll => false,
- g_aux => c_unb1_board_aux
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => OPEN, -- dp_rst,
- dp_clk => OPEN, -- dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- -- . system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_dp_clk_use_pll => false,
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => OPEN, -- dp_rst,
+ dp_clk => OPEN, -- dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ -- . system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb_ddr3_transpose
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_frame_size_in => c_frame_size_in,
- g_nof_streams => c_nof_streams,
- g_ddr3_seq => c_ddr3_seq_conf
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- Blockgenerator
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
-
- -- DDR3 transpose
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- -- Databuffers
- ram_diag_data_buf_im_mosi => ram_diag_data_buf_im_mosi,
- ram_diag_data_buf_im_miso => ram_diag_data_buf_im_miso,
- reg_diag_data_buf_im_mosi => reg_diag_data_buf_im_mosi,
- reg_diag_data_buf_im_miso => reg_diag_data_buf_im_miso,
- ram_diag_data_buf_re_mosi => ram_diag_data_buf_re_mosi,
- ram_diag_data_buf_re_miso => ram_diag_data_buf_re_miso,
- reg_diag_data_buf_re_mosi => reg_diag_data_buf_re_mosi,
- reg_diag_data_buf_re_miso => reg_diag_data_buf_re_miso,
-
- -- BSN monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso
-
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_frame_size_in => c_frame_size_in,
+ g_nof_streams => c_nof_streams,
+ g_ddr3_seq => c_ddr3_seq_conf
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- Blockgenerator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+
+ -- DDR3 transpose
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- Databuffers
+ ram_diag_data_buf_im_mosi => ram_diag_data_buf_im_mosi,
+ ram_diag_data_buf_im_miso => ram_diag_data_buf_im_miso,
+ reg_diag_data_buf_im_mosi => reg_diag_data_buf_im_mosi,
+ reg_diag_data_buf_im_miso => reg_diag_data_buf_im_miso,
+ ram_diag_data_buf_re_mosi => ram_diag_data_buf_re_mosi,
+ ram_diag_data_buf_re_miso => ram_diag_data_buf_re_miso,
+ reg_diag_data_buf_re_mosi => reg_diag_data_buf_re_mosi,
+ reg_diag_data_buf_re_miso => reg_diag_data_buf_re_miso,
+
+ -- BSN monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso
+
+ );
-----------------------------------------------------------------------------
-- Node function
-----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => c_nof_streams,
- g_buf_dat_w => c_bg_buf_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w,
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_nof_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 2, -- Check one input and one output stream
- g_cross_clock_domain => true,
- g_bsn_w => c_dp_stream_bsn_w,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_log_first_bsn => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => (others => c_dp_siso_rdy),
- in_sosi_arr => bsn_sosi_arr
- );
+ generic map (
+ g_nof_streams => 2, -- Check one input and one output stream
+ g_cross_clock_domain => true,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_log_first_bsn => true
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => (others => c_dp_siso_rdy),
+ in_sosi_arr => bsn_sosi_arr
+ );
bsn_sosi_arr(0) <= bg_sosi_arr(0);
bsn_sosi_arr(1) <= out_sosi_arr(0);
u_areset_ddr_ref_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 40
- )
- port map(
- clk => CLK,
- in_rst => mm_rst,
- out_rst => ddr_ref_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ port map(
+ clk => CLK,
+ in_rst => mm_rst,
+ out_rst => ddr_ref_rst
+ );
u_ddr3_T: entity ddr3_lib.ddr3_transpose
- generic map(
- g_sim => g_sim,
- g_nof_streams => c_nof_streams,
- g_in_dat_w => c_bg_buf_dat_w / c_nof_complex,
- g_frame_size_in => c_frame_size_in,
- g_frame_size_out => c_frame_size_out,
- g_nof_blk_per_sync => c_nof_blk_per_sync,
- g_use_complex => true,
- g_ena_pre_transp => c_ena_pre_transpose,
- g_phy => c_phy,
- g_mts => c_mts,
- g_ddr3_seq => c_ddr3_seq_conf
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_ref_clk => CLK,
- dp_ref_rst => ddr_ref_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- dp_out_clk => dp_clk,
- dp_out_rst => dp_rst,
-
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- snk_out_arr => bg_siso_arr,
- snk_in_arr => bg_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr,
-
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- ser_term_ctrl_out => OPEN,
- par_term_ctrl_out => OPEN,
-
- ser_term_ctrl_in => OPEN,
- par_term_ctrl_in => OPEN,
-
- phy_in => MB_I_in,
- phy_io => MB_I_io,
- phy_ou => MB_I_ou
- );
+ generic map(
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams,
+ g_in_dat_w => c_bg_buf_dat_w / c_nof_complex,
+ g_frame_size_in => c_frame_size_in,
+ g_frame_size_out => c_frame_size_out,
+ g_nof_blk_per_sync => c_nof_blk_per_sync,
+ g_use_complex => true,
+ g_ena_pre_transp => c_ena_pre_transpose,
+ g_phy => c_phy,
+ g_mts => c_mts,
+ g_ddr3_seq => c_ddr3_seq_conf
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_ref_clk => CLK,
+ dp_ref_rst => ddr_ref_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ dp_out_clk => dp_clk,
+ dp_out_rst => dp_rst,
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ snk_out_arr => bg_siso_arr,
+ snk_in_arr => bg_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr,
+
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ ser_term_ctrl_out => OPEN,
+ par_term_ctrl_out => OPEN,
+
+ ser_term_ctrl_in => OPEN,
+ par_term_ctrl_in => OPEN,
+
+ phy_in => MB_I_in,
+ phy_io => MB_I_io,
+ phy_ou => MB_I_ou
+ );
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_type => c_db_data_type_re,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
- ram_data_buf_miso => ram_diag_data_buf_re_miso,
- reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
- reg_data_buf_miso => reg_diag_data_buf_re_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_type => c_db_data_type_im,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
- ram_data_buf_miso => ram_diag_data_buf_im_miso,
- reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
- reg_data_buf_miso => reg_diag_data_buf_im_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_type => c_db_data_type_im,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
index 3d8ecf213a..f6340f2f6f 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
@@ -25,13 +25,13 @@
-- that are used on hardware.
library IEEE, tech_ddr_lib, common_lib, unb1_board_lib, i2c_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity tb_unb1_ddr3_transpose is
end tb_unb1_ddr3_transpose;
@@ -73,7 +73,7 @@ architecture tb of tb_unb1_ddr3_transpose is
signal sens_scl : std_logic;
signal sens_sda : std_logic;
- -- Signals to interface with the DDR3 memory model.
+ -- Signals to interface with the DDR3 memory model.
signal phy_in : t_tech_ddr3_phy_in;
signal phy_io : t_tech_ddr3_phy_io;
signal phy_ou : t_tech_ddr3_phy_ou;
@@ -153,47 +153,47 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
-- DDR3 Model
u_tech_ddr_memory_model : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_tech_ddr
- )
- port map (
- -- DDR3 PHY interface
- mem3_in => phy_ou,
- mem3_io => phy_io
- );
+ generic map (
+ g_tech_ddr => c_tech_ddr
+ )
+ port map (
+ -- DDR3 PHY interface
+ mem3_in => phy_ou,
+ mem3_io => phy_io
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
index 02d12daee5..a9c2864955 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
@@ -20,21 +20,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity mmm_unb1_fn_terminal_db is
generic (
@@ -105,7 +105,7 @@ entity mmm_unb1_fn_terminal_db is
end mmm_unb1_fn_terminal_db;
architecture str of mmm_unb1_fn_terminal_db is
- -- Simulation
+ -- Simulation
constant c_mm_clk_period : time := 100 ps;
constant c_tse_clk_period : time := 8 ns;
@@ -148,38 +148,49 @@ begin
i_tse_clk <= not i_tse_clk after c_tse_clk_period / 2;
eth1g_mm_rst <= '1', '0' after c_tse_clk_period * 5;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_reg_tr_nonbonded : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
- port map(mm_rst, i_mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
+ u_mm_file_reg_tr_nonbonded : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
+ port map(mm_rst, i_mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
- u_mm_file_reg_diagnostics : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
- port map(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
+ u_mm_file_reg_diagnostics : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
+ port map(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
- u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+ u_mm_file_ram_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
- u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+ u_mm_file_reg_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
- u_mm_file_ram_diag_data_buf_mesh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_MESH")
- port map(mm_rst, i_mm_clk, ram_mesh_diag_data_buf_mosi, ram_mesh_diag_data_buf_miso);
+ u_mm_file_ram_diag_data_buf_mesh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_MESH")
+ port map(mm_rst, i_mm_clk, ram_mesh_diag_data_buf_mosi, ram_mesh_diag_data_buf_miso);
- u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+ u_mm_file_reg_bsn_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+ port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -204,10 +215,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_reg_mosi <= sim_eth1g_reg_mosi;
- else
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
- end if;
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ else
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -225,138 +236,138 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_fn_terminal_db
- port map (
- -- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
-
- -- the_altpll_0
- areset_to_the_altpll_0 => '0',
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_tr_nonbonded_mesh
- coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
- coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.rd,
- coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
- coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wr,
- coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diagnostics_mesh
- coe_address_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
- coe_read_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.rd,
- coe_readdata_export_to_the_reg_diagnostics_mesh => reg_diagnostics_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
- coe_write_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wr,
- coe_writedata_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buffer
- coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
- coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
- coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buffer
- coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
- coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
- coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buffer_mesh
- coe_address_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_data_buffer_mesh => OPEN,
- coe_read_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_data_buffer_mesh => OPEN,
- coe_write_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_bsn_monitor => OPEN,
- coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_bsn_monitor => OPEN,
- coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_pps
- in_port_to_the_pio_pps => pin_pps,
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ -- 1) global signals:
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+
+ -- the_altpll_0
+ areset_to_the_altpll_0 => '0',
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_tr_nonbonded_mesh
+ coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
+ coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
+ coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diagnostics_mesh
+ coe_address_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
+ coe_read_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.rd,
+ coe_readdata_export_to_the_reg_diagnostics_mesh => reg_diagnostics_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
+ coe_write_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wr,
+ coe_writedata_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buffer
+ coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buffer
+ coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buffer_mesh
+ coe_address_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_data_buffer_mesh => OPEN,
+ coe_read_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_data_buffer_mesh => OPEN,
+ coe_write_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_bsn_monitor => OPEN,
+ coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_bsn_monitor => OPEN,
+ coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ in_port_to_the_pio_pps => pin_pps,
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
-end;
+ end;
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
index f7ddc51006..64a33e34b0 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
@@ -123,13 +123,13 @@
-- advantage is that it
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity node_unb1_fn_terminal_db is
generic(
@@ -238,7 +238,7 @@ architecture str of node_unb1_fn_terminal_db is
signal rx_usr_siso_arr : t_dp_siso_arr(g_usr_nof_streams - 1 downto 0);
signal rx_usr_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Data buffer
-----------------------------------------------------------------------------
signal db_in_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
@@ -249,67 +249,67 @@ begin
-----------------------------------------------------------------------------
u_terminals_mesh : entity unb1_board_lib.unb1_board_terminals_mesh
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_node_type => e_fn,
- g_nof_bus => c_unb1_board_nof_bn, -- 4 to 4 nodes in mesh
- -- User
- g_usr_use_complex => true,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_block_len,
- g_usr_nof_streams => c_usr_nof_streams_per_bus,
- -- Phy
- g_phy_nof_serial => g_mesh_nof_serial,
- g_phy_gx_mbps => g_mesh_gx_mbps,
- g_phy_rx_fifo_size => c_phy_rx_fifo_size,
- g_phy_ena_reorder => g_mesh_ena_reorder,
- -- Tx
- g_use_tx => g_mesh_use_tx, -- optionally do support diag Tx
- g_tx_input_use_fifo => false, -- no user Tx
- -- Rx
- g_use_rx => true, -- user Rx must be TRUE for DB in FN,
- g_rx_output_use_fifo => true, -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_output_fifo_size => c_rx_output_fifo_size,
- g_rx_output_fifo_fill => c_rx_output_fifo_fill,
- g_rx_timeout_w => c_rx_timeout_w,
- -- Monitoring
- g_mon_select => g_mesh_mon_select,
- g_mon_nof_words => g_mesh_mon_nof_words,
- g_mon_use_sync => g_mesh_mon_use_sync
- )
- port map (
- chip_id => chip_id,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_sync => dp_pps,
- tr_clk => tr_mesh_clk,
- cal_clk => cal_clk,
-
- -- User interface (4 nodes)(4 input streams)
- rx_usr_siso_2arr => rx_usr_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- Rx (user Tx from FN to BN is unused)
-
- -- Mesh interface level (4 nodes)(4 lanes)
- -- . Serial (tr_nonbonded)
- tx_serial_2arr => tx_serial_2arr, -- Tx
- rx_serial_2arr => rx_serial_2arr, -- Rx
-
- -- MM Control
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
-
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_node_type => e_fn,
+ g_nof_bus => c_unb1_board_nof_bn, -- 4 to 4 nodes in mesh
+ -- User
+ g_usr_use_complex => true,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_block_len,
+ g_usr_nof_streams => c_usr_nof_streams_per_bus,
+ -- Phy
+ g_phy_nof_serial => g_mesh_nof_serial,
+ g_phy_gx_mbps => g_mesh_gx_mbps,
+ g_phy_rx_fifo_size => c_phy_rx_fifo_size,
+ g_phy_ena_reorder => g_mesh_ena_reorder,
+ -- Tx
+ g_use_tx => g_mesh_use_tx, -- optionally do support diag Tx
+ g_tx_input_use_fifo => false, -- no user Tx
+ -- Rx
+ g_use_rx => true, -- user Rx must be TRUE for DB in FN,
+ g_rx_output_use_fifo => true, -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_fifo_size => c_rx_output_fifo_size,
+ g_rx_output_fifo_fill => c_rx_output_fifo_fill,
+ g_rx_timeout_w => c_rx_timeout_w,
+ -- Monitoring
+ g_mon_select => g_mesh_mon_select,
+ g_mon_nof_words => g_mesh_mon_nof_words,
+ g_mon_use_sync => g_mesh_mon_use_sync
+ )
+ port map (
+ chip_id => chip_id,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_sync => dp_pps,
+ tr_clk => tr_mesh_clk,
+ cal_clk => cal_clk,
+
+ -- User interface (4 nodes)(4 input streams)
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- Rx (user Tx from FN to BN is unused)
+
+ -- Mesh interface level (4 nodes)(4 lanes)
+ -- . Serial (tr_nonbonded)
+ tx_serial_2arr => tx_serial_2arr, -- Tx
+ rx_serial_2arr => rx_serial_2arr, -- Rx
+
+ -- MM Control
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
+ );
---------------------------------------------------------------------------------------
-- Forward the received streams, rewire for single or multi UniBoard use
@@ -345,51 +345,51 @@ begin
gen_align : if g_use_bsn_align = true generate
u_bsn_align : entity dp_lib.dp_bsn_align
- generic map (
- g_block_size => g_usr_block_len,
- g_nof_input => g_usr_nof_streams,
- g_xoff_timeout => c_xoff_timeout,
- g_sop_timeout => c_sop_timeout,
- g_bsn_latency => c_burst_bsn_latency,
- g_bsn_request_pipeline => c_bsn_request_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sinks
- snk_out_arr => rx_usr_siso_arr,
- snk_in_arr => rx_usr_sosi_arr,
- -- ST source
- src_in_arr => dp_out_siso_arr,
- src_out_arr => db_in_sosi_arr,
- -- MM
- in_en_evt => '0', -- pulse '1' indicates that the in_en_arr user input enables have been updated
- in_en_arr => (others => '1') -- default all user inputs are enabled
- );
+ generic map (
+ g_block_size => g_usr_block_len,
+ g_nof_input => g_usr_nof_streams,
+ g_xoff_timeout => c_xoff_timeout,
+ g_sop_timeout => c_sop_timeout,
+ g_bsn_latency => c_burst_bsn_latency,
+ g_bsn_request_pipeline => c_bsn_request_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sinks
+ snk_out_arr => rx_usr_siso_arr,
+ snk_in_arr => rx_usr_sosi_arr,
+ -- ST source
+ src_in_arr => dp_out_siso_arr,
+ src_out_arr => db_in_sosi_arr,
+ -- MM
+ in_en_evt => '0', -- pulse '1' indicates that the in_en_arr user input enables have been updated
+ in_en_arr => (others => '1') -- default all user inputs are enabled
+ );
u_bsn_monitor_align : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- All streams are synchronous. Only monitor stream(0).
- g_cross_clock_domain => true,
- g_sync_timeout => g_mesh_sync_timeout,
- g_bsn_w => c_dp_stream_bsn_w,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_log_first_bsn => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => (others => c_dp_siso_rdy),
- in_sosi_arr => db_in_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- All streams are synchronous. Only monitor stream(0).
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_mesh_sync_timeout,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_log_first_bsn => true
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => (others => c_dp_siso_rdy),
+ in_sosi_arr => db_in_sosi_arr(0 downto 0)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -402,27 +402,27 @@ begin
gen_data_buf : if g_use_data_buf = true generate
u_data_buf : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => g_usr_nof_streams,
- g_data_w => g_usr_data_w,
- g_buf_nof_data => 1024,
- g_buf_use_sync => true
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- -- ST interface
- in_sync => db_in_sosi_arr(0).sync,
- in_sosi_arr => db_in_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_usr_nof_streams,
+ g_data_w => g_usr_data_w,
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => true
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => db_in_sosi_arr(0).sync,
+ in_sosi_arr => db_in_sosi_arr
+ );
end generate;
-----------------------------------------------------------------------------
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
index c3b0cd8997..6e268cd8b3 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
@@ -20,18 +20,18 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity unb1_fn_terminal_db is
generic (
@@ -47,7 +47,7 @@ entity unb1_fn_terminal_db is
g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
);
port (
- -- GENERAL
+ -- GENERAL
CLK : in std_logic; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
@@ -172,204 +172,204 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
- pin_pps => pin_pps,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+ pin_pps => pin_pps,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_fn_terminal_db
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
-
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- cal_clk => cal_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
- pin_pps => pin_pps,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
-
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- . diag_data_buffer_mesh
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
-
- -- . bsn_monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
- );
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ cal_clk => cal_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+ pin_pps => pin_pps,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- . diag_data_buffer_mesh
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+
+ -- . bsn_monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso
+
+ );
-----------------------------------------------------------------------------
-- Node functioon: Terminals and data buffer
-----------------------------------------------------------------------------
u_node_unb1_fn_terminal_db : entity unb1_board_lib.node_unb1_fn_terminal_db
- generic map(
- g_multi_unb => g_rev_multi_unb,
- -- Terminals interface
- g_use_mesh => c_use_mesh,
- g_mesh_mon_select => c_mesh_mon_select,
- g_mesh_mon_nof_words => c_mesh_mon_nof_words,
- g_mesh_mon_use_sync => c_mesh_mon_use_sync,
- -- Auxiliary Interface
- g_aux => c_unb1_board_aux
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => SB_CLK,
- cal_clk => cal_clk,
-
- chip_id => this_chip_id,
-
- -- MM interface
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
- -- . diag_data_buffer_mesh
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
- -- . bsn_monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- -- Mesh interface
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr
- );
+ generic map(
+ g_multi_unb => g_rev_multi_unb,
+ -- Terminals interface
+ g_use_mesh => c_use_mesh,
+ g_mesh_mon_select => c_mesh_mon_select,
+ g_mesh_mon_nof_words => c_mesh_mon_nof_words,
+ g_mesh_mon_use_sync => c_mesh_mon_use_sync,
+ -- Auxiliary Interface
+ g_aux => c_unb1_board_aux
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => SB_CLK,
+ cal_clk => cal_clk,
+
+ chip_id => this_chip_id,
+
+ -- MM interface
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+ -- . diag_data_buffer_mesh
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+ -- . bsn_monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ -- Mesh interface
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr
+ );
-----------------------------------------------------------------------------
-- Mesh I/O
@@ -380,23 +380,23 @@ begin
gen_tr_mesh : if c_use_phy.tr_mesh /= 0 generate
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_unb1_board_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr,
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_TX,
- FN_BN_0_RX => FN_BN_0_RX,
- FN_BN_1_TX => FN_BN_1_TX,
- FN_BN_1_RX => FN_BN_1_RX,
- FN_BN_2_TX => FN_BN_2_TX,
- FN_BN_2_RX => FN_BN_2_RX,
- FN_BN_3_TX => FN_BN_3_TX,
- FN_BN_3_RX => FN_BN_3_RX
- );
+ generic map (
+ g_bus_w => c_unb1_board_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr,
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX
+ );
end generate;
-end;
+ end;
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
index 25bd96f7d8..17e636434b 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
@@ -73,17 +73,17 @@
--
library IEEE, common_lib, unb_common_lib, bn_terminal_bg_lib, mm_lib, bf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use unb_common_lib.unb_common_pkg.all;
-use unb_common_lib.tb_unb_common_pkg.all;
-use bf_lib.bf_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use unb_common_lib.unb_common_pkg.all;
+ use unb_common_lib.tb_unb_common_pkg.all;
+ use bf_lib.bf_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
entity tb_mmf_node_fn_terminal_db is
generic (
@@ -96,7 +96,7 @@ architecture tb of tb_mmf_node_fn_terminal_db is
constant c_sim : boolean := true;
constant c_use_back : boolean := sel_a_b(g_unb_sys.nof_unb = 4, true, false); -- To interconnect multiple boards via the backplane when g_unb_sys.nof_unb=4 else when g_unb_sys.nof_unb=1
- -- this loops back each back node's BN_BI_TX to BN_BI_RX.
+ -- this loops back each back node's BN_BI_TX to BN_BI_RX.
constant c_ena_mesh_reorder : boolean := true;
constant c_mesh_use_bidir : boolean := false;
constant c_mesh_nof_serial : natural := 3; -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
@@ -227,11 +227,13 @@ begin
--u_mm_file_reg_diagnostics_back : mm_file GENERIC MAP(mmf_unb_file_prefix(UNB, BN, "BN") & "REG_DIAGNOSTICS_BACK")
-- PORT MAP(mm_rst, mm_clk, bn_reg_diagnostics_back_mosi_2arr(UNB)(BN), bn_reg_diagnostics_back_miso_2arr(UNB)(BN) );
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(UNB, BN, "BN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, bn_reg_diag_bg_mosi_2arr(UNB)(BN), bn_reg_diag_bg_miso_2arr(UNB)(BN) );
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(UNB, BN, "BN") & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, bn_reg_diag_bg_mosi_2arr(UNB)(BN), bn_reg_diag_bg_miso_2arr(UNB)(BN) );
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(UNB, BN, "BN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, bn_ram_diag_bg_mosi_2arr(UNB)(BN), bn_ram_diag_bg_miso_2arr(UNB)(BN) );
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(UNB, BN, "BN") & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, bn_ram_diag_bg_mosi_2arr(UNB)(BN), bn_ram_diag_bg_miso_2arr(UNB)(BN) );
--u_mm_file_reg_tr_nonbonded_mesh : mm_file GENERIC MAP(mmf_unb_file_prefix(UNB, BN, "BN") & "REG_TR_NONBONDED_MESH")
-- PORT MAP(mm_rst, mm_clk, bn_reg_tr_nonbonded_mesh_mosi_2arr(UNB)(BN), bn_reg_tr_nonbonded_mesh_miso_2arr(UNB)(BN) );
@@ -252,58 +254,58 @@ begin
-- bn_terminal_bg: Node function: block generator & terminals
----------------------------------------------------------------------------
u_node_bn_terminal_bg : entity bn_terminal_bg_lib.node_bn_terminal_bg
- generic map(
- g_sim => c_sim,
- g_sim_level => g_sim_level,
- g_use_back => c_use_back,
- g_mesh_nof_serial => c_mesh_nof_serial,
- g_mesh_use_rx => c_mesh_use_bidir,
- g_mesh_ena_reorder => c_ena_mesh_reorder
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => tr_CLK,
- tr_back_clk => tr_CLK,
- cal_clk => cal_rec_clk,
-
- chip_id => TO_UVEC(BN + 4, c_unb_nof_chip_w), -- BN chip ID 4,5,6,7
- bck_id => TO_UVEC(UNB, c_unb_nof_uniboard_w), -- Backplane ID 0,1,2,3
-
- -- MM interface
- -- . block generator
- reg_diag_bg_mosi => bn_reg_diag_bg_mosi_2arr(UNB)(BN),
- reg_diag_bg_miso => bn_reg_diag_bg_miso_2arr(UNB)(BN),
- ram_diag_bg_mosi => bn_ram_diag_bg_mosi_2arr(UNB)(BN),
- ram_diag_bg_miso => bn_ram_diag_bg_miso_2arr(UNB)(BN),
- -- . tr_nonbonded mesh
- reg_mesh_tr_nonbonded_mosi => bn_reg_tr_nonbonded_mesh_mosi_2arr(UNB)(BN),
- reg_mesh_tr_nonbonded_miso => bn_reg_tr_nonbonded_mesh_miso_2arr(UNB)(BN),
- reg_mesh_diagnostics_mosi => bn_reg_diagnostics_mesh_mosi_2arr(UNB)(BN),
- reg_mesh_diagnostics_miso => bn_reg_diagnostics_mesh_miso_2arr(UNB)(BN),
- -- . tr_nonbonded back
- reg_back_tr_nonbonded_mosi => bn_reg_tr_nonbonded_back_mosi_2arr(UNB)(BN),
- reg_back_tr_nonbonded_miso => bn_reg_tr_nonbonded_back_miso_2arr(UNB)(BN),
- reg_back_diagnostics_mosi => bn_reg_diagnostics_back_mosi_2arr(UNB)(BN),
- reg_back_diagnostics_miso => bn_reg_diagnostics_back_miso_2arr(UNB)(BN),
- -- . diag_data_buffer mesh
- ram_mesh_diag_data_buf_mosi => bn_ram_diag_data_buf_mesh_mosi_2arr(UNB)(BN),
- ram_mesh_diag_data_buf_miso => bn_ram_diag_data_buf_mesh_miso_2arr(UNB)(BN),
-
- -- Mesh interface level
- -- . Serial (tr_nonbonded)
- mesh_tx_serial_2arr => bn_out_mesh_serial_4arr(UNB)(BN),
- mesh_rx_serial_2arr => bn_in_mesh_serial_4arr(UNB)(BN),
-
- -- Back interface level
- -- . Serial (tr_nonbonded)
- back_tx_serial_2arr => bn_out_back_serial_4arr(UNB)(BN),
- back_rx_serial_2arr => bn_in_back_serial_4arr(UNB)(BN)
- );
+ generic map(
+ g_sim => c_sim,
+ g_sim_level => g_sim_level,
+ g_use_back => c_use_back,
+ g_mesh_nof_serial => c_mesh_nof_serial,
+ g_mesh_use_rx => c_mesh_use_bidir,
+ g_mesh_ena_reorder => c_ena_mesh_reorder
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => tr_CLK,
+ tr_back_clk => tr_CLK,
+ cal_clk => cal_rec_clk,
+
+ chip_id => TO_UVEC(BN + 4, c_unb_nof_chip_w), -- BN chip ID 4,5,6,7
+ bck_id => TO_UVEC(UNB, c_unb_nof_uniboard_w), -- Backplane ID 0,1,2,3
+
+ -- MM interface
+ -- . block generator
+ reg_diag_bg_mosi => bn_reg_diag_bg_mosi_2arr(UNB)(BN),
+ reg_diag_bg_miso => bn_reg_diag_bg_miso_2arr(UNB)(BN),
+ ram_diag_bg_mosi => bn_ram_diag_bg_mosi_2arr(UNB)(BN),
+ ram_diag_bg_miso => bn_ram_diag_bg_miso_2arr(UNB)(BN),
+ -- . tr_nonbonded mesh
+ reg_mesh_tr_nonbonded_mosi => bn_reg_tr_nonbonded_mesh_mosi_2arr(UNB)(BN),
+ reg_mesh_tr_nonbonded_miso => bn_reg_tr_nonbonded_mesh_miso_2arr(UNB)(BN),
+ reg_mesh_diagnostics_mosi => bn_reg_diagnostics_mesh_mosi_2arr(UNB)(BN),
+ reg_mesh_diagnostics_miso => bn_reg_diagnostics_mesh_miso_2arr(UNB)(BN),
+ -- . tr_nonbonded back
+ reg_back_tr_nonbonded_mosi => bn_reg_tr_nonbonded_back_mosi_2arr(UNB)(BN),
+ reg_back_tr_nonbonded_miso => bn_reg_tr_nonbonded_back_miso_2arr(UNB)(BN),
+ reg_back_diagnostics_mosi => bn_reg_diagnostics_back_mosi_2arr(UNB)(BN),
+ reg_back_diagnostics_miso => bn_reg_diagnostics_back_miso_2arr(UNB)(BN),
+ -- . diag_data_buffer mesh
+ ram_mesh_diag_data_buf_mosi => bn_ram_diag_data_buf_mesh_mosi_2arr(UNB)(BN),
+ ram_mesh_diag_data_buf_miso => bn_ram_diag_data_buf_mesh_miso_2arr(UNB)(BN),
+
+ -- Mesh interface level
+ -- . Serial (tr_nonbonded)
+ mesh_tx_serial_2arr => bn_out_mesh_serial_4arr(UNB)(BN),
+ mesh_rx_serial_2arr => bn_in_mesh_serial_4arr(UNB)(BN),
+
+ -- Back interface level
+ -- . Serial (tr_nonbonded)
+ back_tx_serial_2arr => bn_out_back_serial_4arr(UNB)(BN),
+ back_rx_serial_2arr => bn_in_back_serial_4arr(UNB)(BN)
+ );
end generate;
gen_fn: for FN in 0 to g_unb_sys.nof_fn - 1 generate
@@ -316,11 +318,13 @@ begin
--u_mm_file_reg_diagnostics : mm_file GENERIC MAP(mmf_unb_file_prefix(UNB, FN, "FN") & "REG_DIAGNOSTICS_MESH")
-- PORT MAP(mm_rst, mm_clk, fn_reg_diagnostics_mosi_2arr(UNB)(FN), fn_reg_diagnostics_miso_2arr(UNB)(FN) );
- u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(UNB, FN, "FN") & "RAM_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, fn_ram_diag_data_buf_mosi_2arr(UNB)(FN), fn_ram_diag_data_buf_miso_2arr(UNB)(FN) );
+ u_mm_file_ram_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(UNB, FN, "FN") & "RAM_DIAG_DATA_BUFFER")
+ port map(mm_rst, mm_clk, fn_ram_diag_data_buf_mosi_2arr(UNB)(FN), fn_ram_diag_data_buf_miso_2arr(UNB)(FN) );
- u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(UNB, FN, "FN") & "REG_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, fn_reg_diag_data_buf_mosi_2arr(UNB)(FN), fn_reg_diag_data_buf_miso_2arr(UNB)(FN) );
+ u_mm_file_reg_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(UNB, FN, "FN") & "REG_DIAG_DATA_BUFFER")
+ port map(mm_rst, mm_clk, fn_reg_diag_data_buf_mosi_2arr(UNB)(FN), fn_reg_diag_data_buf_miso_2arr(UNB)(FN) );
--u_mm_file_ram_diag_data_buf_mesh : mm_file GENERIC MAP(mmf_unb_file_prefix(UNB, FN, "FN") & "RAM_DIAG_DATA_BUFFER_MESH")
-- PORT MAP(mm_rst, mm_clk, fn_ram_mesh_diag_data_buf_mosi_2arr(UNB)(FN), fn_ram_mesh_diag_data_buf_miso_2arr(UNB)(FN) );
@@ -335,52 +339,52 @@ begin
-- Node function: Terminals and data buffer
-----------------------------------------------------------------------------
u_node_fn_terminal_db : entity work.node_unb1_fn_terminal_db
- generic map(
- g_sim => c_sim,
- g_sim_level => g_sim_level,
- g_use_bsn_align => true,
- g_use_data_buf => true,
- -- Terminals interface
- g_multi_unb => sel_a_b(g_unb_sys.nof_unb > 1, true, false),
- g_mesh_nof_serial => c_mesh_nof_serial,
- g_mesh_use_tx => c_mesh_use_bidir,
- g_mesh_ena_reorder => c_ena_mesh_reorder
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => tr_clk,
- cal_clk => cal_rec_clk,
-
- chip_id => TO_UVEC(FN, c_unb_nof_chip_w), -- FN chip ID 0,1,2,3
-
- -- MM interface
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => fn_reg_tr_nonbonded_mosi_2arr(UNB)(FN),
- reg_tr_nonbonded_miso => fn_reg_tr_nonbonded_miso_2arr(UNB)(FN),
- reg_diagnostics_mosi => fn_reg_diagnostics_mosi_2arr(UNB)(FN),
- reg_diagnostics_miso => fn_reg_diagnostics_miso_2arr(UNB)(FN),
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => fn_ram_diag_data_buf_mosi_2arr(UNB)(FN),
- ram_diag_data_buf_miso => fn_ram_diag_data_buf_miso_2arr(UNB)(FN),
- reg_diag_data_buf_mosi => fn_reg_diag_data_buf_mosi_2arr(UNB)(FN),
- reg_diag_data_buf_miso => fn_reg_diag_data_buf_miso_2arr(UNB)(FN),
- -- . diag_data_buffer_mesh
- ram_mesh_diag_data_buf_mosi => fn_ram_mesh_diag_data_buf_mosi_2arr(UNB)(FN),
- ram_mesh_diag_data_buf_miso => fn_ram_mesh_diag_data_buf_miso_2arr(UNB)(FN),
- -- . bsn_monitor
- reg_bsn_monitor_mosi => fn_reg_bsn_monitor_mosi_2arr(UNB)(FN),
- reg_bsn_monitor_miso => fn_reg_bsn_monitor_miso_2arr(UNB)(FN),
-
- -- Mesh interface level
- -- . Serial (tr_nonbonded)
- tx_serial_2arr => fn_out_mesh_serial_4arr(UNB)(FN), -- Tx support for diagnostics
- rx_serial_2arr => fn_in_mesh_serial_4arr(UNB)(FN) -- Rx
- );
+ generic map(
+ g_sim => c_sim,
+ g_sim_level => g_sim_level,
+ g_use_bsn_align => true,
+ g_use_data_buf => true,
+ -- Terminals interface
+ g_multi_unb => sel_a_b(g_unb_sys.nof_unb > 1, true, false),
+ g_mesh_nof_serial => c_mesh_nof_serial,
+ g_mesh_use_tx => c_mesh_use_bidir,
+ g_mesh_ena_reorder => c_ena_mesh_reorder
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => tr_clk,
+ cal_clk => cal_rec_clk,
+
+ chip_id => TO_UVEC(FN, c_unb_nof_chip_w), -- FN chip ID 0,1,2,3
+
+ -- MM interface
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => fn_reg_tr_nonbonded_mosi_2arr(UNB)(FN),
+ reg_tr_nonbonded_miso => fn_reg_tr_nonbonded_miso_2arr(UNB)(FN),
+ reg_diagnostics_mosi => fn_reg_diagnostics_mosi_2arr(UNB)(FN),
+ reg_diagnostics_miso => fn_reg_diagnostics_miso_2arr(UNB)(FN),
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => fn_ram_diag_data_buf_mosi_2arr(UNB)(FN),
+ ram_diag_data_buf_miso => fn_ram_diag_data_buf_miso_2arr(UNB)(FN),
+ reg_diag_data_buf_mosi => fn_reg_diag_data_buf_mosi_2arr(UNB)(FN),
+ reg_diag_data_buf_miso => fn_reg_diag_data_buf_miso_2arr(UNB)(FN),
+ -- . diag_data_buffer_mesh
+ ram_mesh_diag_data_buf_mosi => fn_ram_mesh_diag_data_buf_mosi_2arr(UNB)(FN),
+ ram_mesh_diag_data_buf_miso => fn_ram_mesh_diag_data_buf_miso_2arr(UNB)(FN),
+ -- . bsn_monitor
+ reg_bsn_monitor_mosi => fn_reg_bsn_monitor_mosi_2arr(UNB)(FN),
+ reg_bsn_monitor_miso => fn_reg_bsn_monitor_miso_2arr(UNB)(FN),
+
+ -- Mesh interface level
+ -- . Serial (tr_nonbonded)
+ tx_serial_2arr => fn_out_mesh_serial_4arr(UNB)(FN), -- Tx support for diagnostics
+ rx_serial_2arr => fn_in_mesh_serial_4arr(UNB)(FN) -- Rx
+ );
end generate;
------------------------------------------------------------------------------
@@ -399,36 +403,36 @@ begin
-- Mesh model
gen_mesh : if g_unb_sys.nof_bn > 1 or g_unb_sys.nof_fn > 1 generate
u_mesh_model_serial : entity unb_common_lib.unb_mesh_model_sl
- generic map(
- g_reorder => c_ena_mesh_reorder
- )
- port map (
- -- FN to BN
- fn_tx_sl_3arr => fn_out_mesh_serial_4arr(UNB),
- bn_rx_sl_3arr => bn_in_mesh_serial_4arr(UNB),
-
- -- BN to FN
- bn_tx_sl_3arr => bn_out_mesh_serial_4arr(UNB),
- fn_rx_sl_3arr => fn_in_mesh_serial_4arr(UNB)
- );
+ generic map(
+ g_reorder => c_ena_mesh_reorder
+ )
+ port map (
+ -- FN to BN
+ fn_tx_sl_3arr => fn_out_mesh_serial_4arr(UNB),
+ bn_rx_sl_3arr => bn_in_mesh_serial_4arr(UNB),
+
+ -- BN to FN
+ bn_tx_sl_3arr => bn_out_mesh_serial_4arr(UNB),
+ fn_rx_sl_3arr => fn_in_mesh_serial_4arr(UNB)
+ );
end generate;
end generate;
- ------------------------------------------------------------------------------
- -- Instantiate a backplane model that interconnects all UniBoards...
- ------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
+ -- Instantiate a backplane model that interconnects all UniBoards...
+ ------------------------------------------------------------------------------
gen_backplane : if c_use_back = true generate
gen_model : entity unb_common_lib.unb_back_model_sl
- port map (
- backplane_in_serial_4arr => bn_out_back_serial_4arr,
- backplane_out_serial_4arr => bn_in_back_serial_4arr
- );
+ port map (
+ backplane_in_serial_4arr => bn_out_back_serial_4arr,
+ backplane_out_serial_4arr => bn_in_back_serial_4arr
+ );
end generate;
- ------------------------------------------------------------------------------
- -- ...or loop back serial TX to RX in case of a single UniBoard.
- ------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
+ -- ...or loop back serial TX to RX in case of a single UniBoard.
+ ------------------------------------------------------------------------------
no_backplane: if c_use_back = false generate
bn_in_back_serial_4arr <= bn_out_back_serial_4arr;
end generate;
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
index 78bdc17f23..e81ae5e4e1 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb1_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb1_heater_pkg.all;
entity mmm_unb1_heater is
generic (
@@ -126,31 +126,40 @@ begin
eth1g_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_reg_heater : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
- port map(mm_rst, i_mm_clk, reg_heater_mosi, reg_heater_miso );
+ u_mm_file_reg_heater : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
+ port map(mm_rst, i_mm_clk, reg_heater_mosi, reg_heater_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
- port map(mm_rst, i_mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
- u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
- port map(mm_rst, i_mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+ u_mm_file_eth1g_reg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_eth1g_ram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
+ port map(mm_rst, i_mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+ u_mm_file_eth1g_tse : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
+ port map(mm_rst, i_mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -171,7 +180,7 @@ begin
tse_clk => eth1g_tse_clk,
epcs_clk => i_epcs_clk,
- -- the_altpll_0
+ -- the_altpll_0
locked_from_the_altpll_0 => mm_locked,
phasedone_from_the_altpll_0 => OPEN,
areset_to_the_altpll_0 => xo_rst,
@@ -307,7 +316,7 @@ begin
reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w - 1 downto 0),
reg_heater_write_export => reg_heater_mosi.wr,
reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
index 6ab5775f35..f34551f573 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
@@ -20,129 +20,129 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb1_heater_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_unb1_heater is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- mm_clk : out std_logic; -- clk
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- tse_clk : out std_logic; -- clk
- epcs_clk : out std_logic; -- clk
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- c3_from_the_altpll_0 : out std_logic; -- export
- coe_read_export_from_the_reg_remu : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(3 downto 0); -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_reset_export : out std_logic -- export
- );
- end component qsys_unb1_heater;
+ component qsys_unb1_heater is
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ mm_clk : out std_logic; -- clk
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ phasedone_from_the_altpll_0 : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ tse_clk : out std_logic; -- clk
+ epcs_clk : out std_logic; -- clk
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_remu : out std_logic; -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
+ areset_to_the_altpll_0 : in std_logic := 'X'; -- export
+ locked_from_the_altpll_0 : out std_logic; -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ c3_from_the_altpll_0 : out std_logic; -- export
+ coe_read_export_from_the_reg_remu : out std_logic; -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_reset_export : out std_logic -- export
+ );
+ end component qsys_unb1_heater;
end qsys_unb1_heater_pkg;
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
index 8187b73626..6852518ebd 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, util_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use util_lib.util_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use util_lib.util_heater_pkg.all;
entity unb1_heater is
generic (
@@ -148,201 +148,201 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_base_ip => c_base_ip,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- epcs_clk => epcs_clk,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_base_ip => c_base_ip,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ epcs_clk => epcs_clk,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_heater
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- epcs_clk => epcs_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- heater:
- reg_heater_mosi => reg_heater_mosi,
- reg_heater_miso => reg_heater_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ epcs_clk => epcs_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- heater:
+ reg_heater_mosi => reg_heater_mosi,
+ reg_heater_miso => reg_heater_miso
+ );
u_heater : entity util_lib.util_heater
- generic map (
- g_technology => g_technology,
- g_nof_mac4 => 315
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- sla_in => reg_heater_mosi,
- sla_out => reg_heater_miso
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_mac4 => 315
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ sla_in => reg_heater_mosi,
+ sla_out => reg_heater_miso
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
index 42cf774fa0..54df0f2df3 100644
--- a/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_heater is
- generic (
- g_design_name : string := "unb1_heater";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
- );
+ generic (
+ g_design_name : string := "unb1_heater";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7 -- Back node 3
+ );
end tb_unb1_heater;
architecture tb of tb_unb1_heater is
@@ -163,36 +163,36 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
index 158c2a2617..946b566c5f 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_minimal
library IEEE, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_minimal_mm_arbiter is
end tb_unb1_minimal_mm_arbiter;
@@ -32,8 +32,8 @@ end tb_unb1_minimal_mm_arbiter;
architecture tb of tb_unb1_minimal_mm_arbiter is
begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
- generic map (
- g_design_name => "unb1_minimal_mm_arbiter",
- g_sim_node_nr => 7 -- BN3
- );
+ generic map (
+ g_design_name => "unb1_minimal_mm_arbiter",
+ g_sim_node_nr => 7 -- BN3
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
index 94b8a71585..ead6369fbe 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, unb1_board_lib, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_mm_arbiter is
generic (
@@ -62,36 +62,36 @@ end unb1_minimal_mm_arbiter;
architecture str of unb1_minimal_mm_arbiter is
begin
u_revision : entity unb1_minimal_lib.unb1_minimal
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
index 86785da2a3..49536e63dc 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_minimal
library IEEE, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_minimal_qsys is
end tb_unb1_minimal_qsys;
@@ -32,8 +32,8 @@ end tb_unb1_minimal_qsys;
architecture tb of tb_unb1_minimal_qsys is
begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
- generic map (
- g_design_name => "unb1_minimal_qsys",
- g_sim_node_nr => 7 -- BN3
- );
+ generic map (
+ g_design_name => "unb1_minimal_qsys",
+ g_sim_node_nr => 7 -- BN3
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
index 0f6289c4b1..d00dcf4cfe 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, unb1_board_lib, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_qsys is
generic (
@@ -62,36 +62,36 @@ end unb1_minimal_qsys;
architecture str of unb1_minimal_qsys is
begin
u_revision : entity unb1_minimal_lib.unb1_minimal
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
index 2259919154..3140e03ca3 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
@@ -20,24 +20,24 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_wo_pll_unb1_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_wo_pll_unb1_minimal_pkg.all;
entity mmm_unb1_minimal_qsys_wo_pll is
generic (
@@ -121,28 +121,36 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
- port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
- u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
- port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+ u_mm_file_eth1g_reg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_eth1g_ram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
+ port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+ u_mm_file_eth1g_tse : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
+ port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -184,7 +192,7 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
signal mm_rst_n : std_logic;
- begin
+ begin
mm_rst_n <= not (mm_rst);
u_qsys : qsys_wo_pll_unb1_minimal
@@ -314,7 +322,7 @@ begin
coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
index 142125fe43..cb4fba0108 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
@@ -20,116 +20,116 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_wo_pll_unb1_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_wo_pll_unb1_minimal is
+ component qsys_wo_pll_unb1_minimal is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_remu : out std_logic -- export
- );
- end component qsys_wo_pll_unb1_minimal;
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- _vector(0 downto 0); -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic; -- _vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_remu : out std_logic; -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- _vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic; -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_remu : out std_logic -- export
+ );
+ end component qsys_wo_pll_unb1_minimal;
end qsys_wo_pll_unb1_minimal_pkg;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
index 0359b31911..8e11840aaa 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_minimal_qsys_wo_pll is
- generic (
- g_design_name : string := "unb1_minimal_qsys_wo_pll";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
- );
+ generic (
+ g_design_name : string := "unb1_minimal_qsys_wo_pll";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7 -- Back node 3
+ );
end tb_unb1_minimal_qsys_wo_pll;
architecture tb of tb_unb1_minimal_qsys_wo_pll is
@@ -163,36 +163,36 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
index 408c4bc506..4017e4ddd1 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_qsys_wo_pll is
generic (
@@ -141,186 +141,186 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_sim_flash_model => false,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_dp_clk_freq => c_unb1_board_ext_clk_freq_200M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_dp_clk_use_pll => true,
- g_xo_clk_use_pll => true
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk_out => mm_clk,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_locked => mm_locked,
- mm_locked_out => mm_locked,
-
- epcs_clk => epcs_clk,
- epcs_clk_out => epcs_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- cal_rec_clk => cal_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk_out => eth1g_tse_clk,
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_flash_model => false,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_dp_clk_freq => c_unb1_board_ext_clk_freq_200M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_dp_clk_use_pll => true,
+ g_xo_clk_use_pll => true
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ cal_rec_clk => cal_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_minimal_qsys_wo_pll
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso
+ );
-----------------------------------------------------------------------------
-- Node function
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
index 73b74d6314..38a87df6a6 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_minimal
library IEEE, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_minimal_sopc is
end tb_unb1_minimal_sopc;
@@ -32,8 +32,8 @@ end tb_unb1_minimal_sopc;
architecture tb of tb_unb1_minimal_sopc is
begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
- generic map (
- g_design_name => "unb1_minimal_sopc",
- g_sim_node_nr => 7 -- BN3
- );
+ generic map (
+ g_design_name => "unb1_minimal_sopc",
+ g_sim_node_nr => 7 -- BN3
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
index 31d891bafd..abe161a3e9 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, unb1_board_lib, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_sopc is
generic (
@@ -62,35 +62,35 @@ end unb1_minimal_sopc;
architecture str of unb1_minimal_sopc is
begin
u_revision : entity unb1_minimal_lib.unb1_minimal
- generic map (
- g_design_name => g_design_name,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
index d0dbf2fd6e..c76c9afe50 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb1_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb1_minimal_pkg.all;
entity mmm_unb1_minimal is
generic (
@@ -155,28 +155,36 @@ begin
eth1g_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
- port map(mm_rst, i_mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
- u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
- port map(mm_rst, i_mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+ u_mm_file_eth1g_reg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_eth1g_ram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
+ port map(mm_rst, i_mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+ u_mm_file_eth1g_tse : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
+ port map(mm_rst, i_mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -190,140 +198,140 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false and g_use_sopc = true generate
u_sopc : entity work.sopc_unb1_minimal
- port map (
- clk_0 => xo_clk,
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk,
- tse_clk => eth1g_tse_clk,
- epcs_clk => i_epcs_clk,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_dpmm_data
- coe_clk_export_from_the_reg_dpmm_data => OPEN,
- coe_reset_export_from_the_reg_dpmm_data => OPEN,
- coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
- coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dpmm_ctrl
- coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
- coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_mmdp_data
- coe_clk_export_from_the_reg_mmdp_data => OPEN,
- coe_reset_export_from_the_reg_mmdp_data => OPEN,
- coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
- coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_mmdp_ctrl
- coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
- coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_epcs
- coe_clk_export_from_the_reg_epcs => OPEN,
- coe_reset_export_from_the_reg_epcs => OPEN,
- coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
- coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
- coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_remu
- coe_clk_export_from_the_reg_remu => OPEN,
- coe_reset_export_from_the_reg_remu => OPEN,
- coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
- coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
- coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
+ port map (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => eth1g_tse_clk,
+ epcs_clk => i_epcs_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_dpmm_data
+ coe_clk_export_from_the_reg_dpmm_data => OPEN,
+ coe_reset_export_from_the_reg_dpmm_data => OPEN,
+ coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dpmm_ctrl
+ coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_mmdp_data
+ coe_clk_export_from_the_reg_mmdp_data => OPEN,
+ coe_reset_export_from_the_reg_mmdp_data => OPEN,
+ coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_mmdp_ctrl
+ coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_epcs
+ coe_clk_export_from_the_reg_epcs => OPEN,
+ coe_reset_export_from_the_reg_epcs => OPEN,
+ coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
+ coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
+ coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_remu
+ coe_clk_export_from_the_reg_remu => OPEN,
+ coe_reset_export_from_the_reg_remu => OPEN,
+ coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
+ coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
+ coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
);
end generate;
@@ -336,7 +344,7 @@ begin
tse_clk => eth1g_tse_clk,
epcs_clk => i_epcs_clk,
- -- the_altpll_0
+ -- the_altpll_0
locked_from_the_altpll_0 => mm_locked,
phasedone_from_the_altpll_0 => OPEN,
areset_to_the_altpll_0 => xo_rst,
@@ -463,7 +471,7 @@ begin
coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
-----------------------------------------------------------------------------
@@ -482,7 +490,7 @@ begin
tse_clk => eth1g_tse_clk,
epcs_clk => i_epcs_clk,
- -- the_altpll_0
+ -- the_altpll_0
locked_from_the_altpll_0 => mm_locked,
phasedone_from_the_altpll_0 => OPEN,
areset_to_the_altpll_0 => xo_rst,
@@ -531,21 +539,21 @@ begin
-- MM arbiter
-----------------------------------------------------------------------------
u_mm_arbiter : entity mm_lib.mm_arbiter
- generic map (
- g_nof_slaves => c_nof_slaves,
- g_slave_base_arr => c_slave_base_arr,
- g_slave_high_arr => c_slave_high_arr
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => mm_rst,
-
- master_mosi => master_mosi,
- master_miso => master_miso,
-
- slave_mosi_arr => slave_mosi_arr,
- slave_miso_arr => slave_miso_arr
- );
+ generic map (
+ g_nof_slaves => c_nof_slaves,
+ g_slave_base_arr => c_slave_base_arr,
+ g_slave_high_arr => c_slave_high_arr
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => mm_rst,
+
+ master_mosi => master_mosi,
+ master_miso => master_miso,
+
+ slave_mosi_arr => slave_mosi_arr,
+ slave_miso_arr => slave_miso_arr
+ );
-----------------------------------------------------------------------------
-- Connect slave array to individually names MM buses
@@ -557,7 +565,7 @@ begin
slave_miso_arr(1) <= rom_unb_system_info_miso;
-- pio_system_info; still needed within QSYS, so not connected here.
--- reg_unb_system_info_mosi <= slave_mosi_arr(2);
+ -- reg_unb_system_info_mosi <= slave_mosi_arr(2);
slave_miso_arr(2) <= c_mem_miso_rst;
reg_ppsh_mosi <= slave_mosi_arr(3);
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
index 63e5d9c4da..dbce0542f4 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
@@ -20,171 +20,171 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb1_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_unb1_minimal is
+ component qsys_unb1_minimal is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- mm_clk : out std_logic; -- clk
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- tse_clk : out std_logic; -- clk
- epcs_clk : out std_logic; -- clk
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- c3_from_the_altpll_0 : out std_logic; -- export
- coe_read_export_from_the_reg_remu : out std_logic -- export
- );
- end component qsys_unb1_minimal;
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ mm_clk : out std_logic; -- clk
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- _vector(0 downto 0); -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic; -- _vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ phasedone_from_the_altpll_0 : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ tse_clk : out std_logic; -- clk
+ epcs_clk : out std_logic; -- clk
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_remu : out std_logic; -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- _vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic; -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
+ areset_to_the_altpll_0 : in std_logic := 'X'; -- export
+ locked_from_the_altpll_0 : out std_logic; -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ c3_from_the_altpll_0 : out std_logic; -- export
+ coe_read_export_from_the_reg_remu : out std_logic -- export
+ );
+ end component qsys_unb1_minimal;
- component qsys_unb1_minimal_mm_arbiter is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- mm_clk : out std_logic; -- clk
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- tse_clk : out std_logic; -- clk
- epcs_clk : out std_logic; -- clk
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- c3_from_the_altpll_0 : out std_logic; -- export
- to_mm_arbiter_reset_export : out std_logic; -- export
- to_mm_arbiter_clk_export : out std_logic; -- export
- to_mm_arbiter_address_export : out std_logic_vector(10 downto 0); -- export
- to_mm_arbiter_write_export : out std_logic; -- export
- to_mm_arbiter_writedata_export : out std_logic_vector(31 downto 0); -- export
- to_mm_arbiter_read_export : out std_logic; -- export
- to_mm_arbiter_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_unb1_minimal_mm_arbiter;
+ component qsys_unb1_minimal_mm_arbiter is
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ mm_clk : out std_logic; -- clk
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ phasedone_from_the_altpll_0 : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ tse_clk : out std_logic; -- clk
+ epcs_clk : out std_logic; -- clk
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ areset_to_the_altpll_0 : in std_logic := 'X'; -- export
+ locked_from_the_altpll_0 : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ c3_from_the_altpll_0 : out std_logic; -- export
+ to_mm_arbiter_reset_export : out std_logic; -- export
+ to_mm_arbiter_clk_export : out std_logic; -- export
+ to_mm_arbiter_address_export : out std_logic_vector(10 downto 0); -- export
+ to_mm_arbiter_write_export : out std_logic; -- export
+ to_mm_arbiter_writedata_export : out std_logic_vector(31 downto 0); -- export
+ to_mm_arbiter_read_export : out std_logic; -- export
+ to_mm_arbiter_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_unb1_minimal_mm_arbiter;
end qsys_unb1_minimal_pkg;
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
index fbb7e941a4..4cb8602752 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal is
generic (
@@ -144,186 +144,186 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_base_ip => c_base_ip,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_epcs_protect_addr_range => true
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- epcs_clk => epcs_clk,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_base_ip => c_base_ip,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_epcs_protect_addr_range => true
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ epcs_clk => epcs_clk,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_use_qsys => c_use_qsys,
- g_use_sopc => c_use_sopc
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- epcs_clk => epcs_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_use_qsys => c_use_qsys,
+ g_use_sopc => c_use_sopc
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ epcs_clk => epcs_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso
+ );
-----------------------------------------------------------------------------
-- Node function
diff --git a/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
index 4ffbccca21..b0961594ee 100644
--- a/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_minimal is
- generic (
- g_design_name : string := "unb1_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
- );
+ generic (
+ g_design_name : string := "unb1_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7 -- Back node 3
+ );
end tb_unb1_minimal;
architecture tb of tb_unb1_minimal is
@@ -163,36 +163,36 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
index 4384501026..e98f264c78 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -66,23 +66,23 @@
-- );
--
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity mmm_unb1_terminal_bg_mesh_db is
generic (
@@ -267,38 +267,54 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_RAM")
- port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
- u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_TSE")
- port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
- u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso );
- u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso );
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
- u_mm_file_reg_diagnostics : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
- port map(mm_rst, mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
- u_mm_file_reg_tr_nonbonded : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
- port map(mm_rst, mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
- u_mm_file_ram_mesh_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_MESH_DIAG_DATA_BUF")
- port map(mm_rst, mm_clk, ram_mesh_diag_data_buf_mosi, ram_mesh_diag_data_buf_miso );
- u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_eth1g_ram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_RAM")
+ port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+ u_mm_file_eth1g_reg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_eth1g_tse : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_TSE")
+ port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+ u_mm_file_reg_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso );
+ u_mm_file_ram_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso );
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
+ u_mm_file_reg_diagnostics : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
+ port map(mm_rst, mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
+ u_mm_file_reg_tr_nonbonded : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
+ port map(mm_rst, mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
+ u_mm_file_ram_mesh_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_MESH_DIAG_DATA_BUF")
+ port map(mm_rst, mm_clk, ram_mesh_diag_data_buf_mosi, ram_mesh_diag_data_buf_miso );
+ u_mm_file_reg_bsn_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------
@@ -339,7 +355,7 @@ begin
mm_rst_n <= not(mm_rst);
u_qsys_unb1_terminal_bg_mesh_db : qsys_unb1_terminal_bg_mesh_db
- port map(
+ port map(
clk_in_clk => mm_clk,
eth1g_irq_export => eth1g_reg_interrupt,
eth1g_mm_clk_export => OPEN,
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
index f70200f9e0..fab3faab0b 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
@@ -29,13 +29,13 @@
-- Some more remarks:
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity node_unb1_terminal_bg_mesh_db is
generic(
@@ -72,12 +72,12 @@ entity node_unb1_terminal_bg_mesh_db is
g_rx_timeout_w : natural := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
-- Monitoring
g_mon_select : natural := 0; -- 0 = no SOSI data buffers monitor via MM
- -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
- -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
- -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
- -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute
- -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded
- -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder
+ -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
+ -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
+ -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
+ -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute
+ -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded
+ -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder
g_mon_nof_words : natural := 1024;
g_mon_use_sync : boolean := true;
-- UTH
@@ -207,40 +207,40 @@ begin
-- Block Generator
---------------------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- -- Generate configurations
- g_use_usr_input => c_use_usr_input,
- g_use_bg => g_use_bg,
- g_use_tx_seq => false,
- -- General
- g_nof_streams => c_bg_nof_streams,
- -- BG settings
- g_use_bg_buffer_ram => true,
- g_buf_dat_w => c_nof_complex * c_in_dat_w,
- g_buf_addr_w => c_bg_addr_w,
- g_file_name_prefix => c_file_name_prefix,
- -- User input multiplexer option
- g_usr_bypass_xonoff => false
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
-
- -- ST interface
- usr_siso_arr => bg_snk_out_arr,
- usr_sosi_arr => bg_snk_in_arr,
- out_siso_arr => bg_src_in_arr,
- out_sosi_arr => bg_src_out_arr
- );
+ generic map(
+ -- Generate configurations
+ g_use_usr_input => c_use_usr_input,
+ g_use_bg => g_use_bg,
+ g_use_tx_seq => false,
+ -- General
+ g_nof_streams => c_bg_nof_streams,
+ -- BG settings
+ g_use_bg_buffer_ram => true,
+ g_buf_dat_w => c_nof_complex * c_in_dat_w,
+ g_buf_addr_w => c_bg_addr_w,
+ g_file_name_prefix => c_file_name_prefix,
+ -- User input multiplexer option
+ g_usr_bypass_xonoff => false
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+
+ -- ST interface
+ usr_siso_arr => bg_snk_out_arr,
+ usr_sosi_arr => bg_snk_in_arr,
+ out_siso_arr => bg_src_in_arr,
+ out_sosi_arr => bg_src_out_arr
+ );
---------------------------------------------------------------------------------------
-- From 1d to 2d array. Output BG to input Mesh
@@ -253,75 +253,75 @@ begin
end generate;
u_mesh_terminal : entity unb1_board_lib.unb1_board_terminals_mesh
- generic map(
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_node_type => g_node_type,
- g_nof_bus => g_nof_bus,
- -- User
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- g_usr_nof_streams => g_usr_nof_streams,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- g_phy_gx_mbps => g_phy_gx_mbps,
- g_phy_rx_fifo_size => g_phy_rx_fifo_size,
- g_phy_ena_reorder => g_phy_ena_reorder,
- -- Tx
- g_use_tx => g_use_tx,
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- g_tx_input_fifo_size => g_tx_input_fifo_size,
- g_tx_input_fifo_fill => g_tx_input_fifo_fill,
- -- Rx
- g_use_rx => g_use_rx,
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_output_fifo_size => g_rx_output_fifo_size,
- g_rx_output_fifo_fill => g_rx_output_fifo_fill,
- g_rx_timeout_w => g_rx_timeout_w,
-
- -- Monitoring
- g_mon_select => g_mon_select,
- g_mon_nof_words => g_mon_nof_words,
- g_mon_use_sync => g_mon_use_sync,
-
- -- UTH
- g_uth_len_max => g_uth_len_max,
- g_uth_typ_ofs => g_uth_typ_ofs
- )
- port map (
- chip_id => chip_id,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_sync => dp_pps,
- tr_clk => tr_mesh_clk,
- cal_clk => cal_clk,
-
- -- User interface (4 nodes)(4 input streams)
- tx_usr_siso_2arr => bg_out_siso_2arr,
- tx_usr_sosi_2arr => bg_out_sosi_2arr, -- <== Data to the Mesh
- rx_usr_siso_2arr => rx_usr_i_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_i_sosi_2arr, -- ==> Data from the Mesh
-
- -- Serial (tr_nonbonded)
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr,
-
- -- MM Control
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
-
- -- . monitor data buffer
- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_node_type => g_node_type,
+ g_nof_bus => g_nof_bus,
+ -- User
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ g_usr_nof_streams => g_usr_nof_streams,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ g_phy_gx_mbps => g_phy_gx_mbps,
+ g_phy_rx_fifo_size => g_phy_rx_fifo_size,
+ g_phy_ena_reorder => g_phy_ena_reorder,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w,
+
+ -- Monitoring
+ g_mon_select => g_mon_select,
+ g_mon_nof_words => g_mon_nof_words,
+ g_mon_use_sync => g_mon_use_sync,
+
+ -- UTH
+ g_uth_len_max => g_uth_len_max,
+ g_uth_typ_ofs => g_uth_typ_ofs
+ )
+ port map (
+ chip_id => chip_id,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_sync => dp_pps,
+ tr_clk => tr_mesh_clk,
+ cal_clk => cal_clk,
+
+ -- User interface (4 nodes)(4 input streams)
+ tx_usr_siso_2arr => bg_out_siso_2arr,
+ tx_usr_sosi_2arr => bg_out_sosi_2arr, -- <== Data to the Mesh
+ rx_usr_siso_2arr => rx_usr_i_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_i_sosi_2arr, -- ==> Data from the Mesh
+
+ -- Serial (tr_nonbonded)
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr,
+
+ -- MM Control
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ -- . monitor data buffer
+ ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
+ );
---------------------------------------------------------------------------------------
-- From 2d to 1d array. Input port to input BG.
@@ -338,25 +338,25 @@ begin
-----------------------------------------------------------------------------
gen_bsn_align : if g_use_bsn_align generate
u_dp_bsn_align : entity dp_lib.dp_bsn_align
- generic map (
- g_block_size => c_block_size,
- g_block_period => c_block_period,
- g_nof_input => c_bsn_align_nof_streams,
- g_xoff_timeout => c_bsn_align_xoff_timeout,
- g_sop_timeout => c_bsn_align_sop_timeout,
- g_bsn_latency => c_bsn_align_latency,
- g_bsn_request_pipeline => 2
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => bsn_align_snk_out_arr,
- snk_in_arr => bsn_align_snk_in_arr,
-
- src_in_arr => bsn_align_src_in_arr,
- src_out_arr => bsn_align_src_out_arr
- );
+ generic map (
+ g_block_size => c_block_size,
+ g_block_period => c_block_period,
+ g_nof_input => c_bsn_align_nof_streams,
+ g_xoff_timeout => c_bsn_align_xoff_timeout,
+ g_sop_timeout => c_bsn_align_sop_timeout,
+ g_bsn_latency => c_bsn_align_latency,
+ g_bsn_request_pipeline => 2
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => bsn_align_snk_out_arr,
+ snk_in_arr => bsn_align_snk_in_arr,
+
+ src_in_arr => bsn_align_src_in_arr,
+ src_out_arr => bsn_align_src_out_arr
+ );
end generate;
gen_no_bsn_align : if not(g_use_bsn_align) generate
@@ -368,49 +368,49 @@ begin
-- BSN monitors at the output of the BSN aligner
-----------------------------------------------------------------------------
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => c_bsn_mon_nof_streams,
- g_sync_timeout => c_bsn_sync_time_out,
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => bsn_mon_snk_out_arr,
- in_sosi_arr => bsn_mon_snk_in_arr
- );
+ generic map (
+ g_nof_streams => c_bsn_mon_nof_streams,
+ g_sync_timeout => c_bsn_sync_time_out,
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => bsn_mon_snk_out_arr,
+ in_sosi_arr => bsn_mon_snk_in_arr
+ );
bsn_mon_snk_in_arr <= bsn_align_src_out_arr(c_bsn_mon_nof_streams - 1 downto 0);
bsn_mon_snk_out_arr <= bsn_align_src_in_arr(c_bsn_mon_nof_streams - 1 downto 0);
gen_data_buf : if g_use_data_buf generate
u_data_buf : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_w => g_usr_data_w,
- g_buf_nof_data => c_db_nof_data,
- g_buf_use_sync => true
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- -- ST interface
- in_sync => bsn_align_src_out_arr(0).sync,
- in_sosi_arr => bsn_align_src_out_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_w => g_usr_data_w,
+ g_buf_nof_data => c_db_nof_data,
+ g_buf_use_sync => true
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => bsn_align_src_out_arr(0).sync,
+ in_sosi_arr => bsn_align_src_out_arr
+ );
end generate;
---------------------------------------------------------------------------------------
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
index ec6f3afdfd..8f6eb1c57d 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
@@ -20,18 +20,18 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity unb1_terminal_bg_mesh_db is
generic (
@@ -47,7 +47,7 @@ entity unb1_terminal_bg_mesh_db is
g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
);
port (
- -- GENERAL
+ -- GENERAL
CLK : in std_logic; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
@@ -212,238 +212,238 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_sim_flash_model => not(g_sim),
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_dp_clk_use_pll => true,
- g_xo_clk_use_pll => true
- )
- port map (
- -- Clock and reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk_out => mm_clk,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_locked => mm_locked,
- mm_locked_out => mm_locked,
-
- epcs_clk => epcs_clk,
- epcs_clk_out => epcs_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- cal_rec_clk => cal_clk,
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk_out => eth1g_tse_clk,
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_sim_flash_model => not(g_sim),
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_dp_clk_use_pll => true,
+ g_xo_clk_use_pll => true
+ )
+ port map (
+ -- Clock and reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ cal_rec_clk => cal_clk,
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_inst_mmm_unb1_terminal_bg_mesh_db : entity work.mmm_unb1_terminal_bg_mesh_db
- generic map(
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- pout_wdi => pout_wdi,
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ pout_wdi => pout_wdi,
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso
+ );
-----------------------------------------------------------------------------
-- Node function: Terminals and data buffer
-----------------------------------------------------------------------------
u_terminal_mesh : entity work.node_unb1_terminal_bg_mesh_db
- generic map(
- g_sim => g_sim,
- g_sim_level => g_sim_level,
-
- -- BLOCK GENERATOR
- g_use_bg => c_use_bg,
-
- -- MESH TERMINAL
- -- System
- g_node_type => c_node_type,
- g_nof_bus => c_nof_bus,
- -- User
- g_usr_use_complex => c_usr_use_complex,
- g_usr_data_w => c_usr_data_w,
- g_usr_frame_len => c_usr_frame_len,
- g_usr_nof_streams => c_usr_nof_streams,
- -- Phy
- g_phy_nof_serial => c_phy_nof_serial,
- g_phy_gx_mbps => c_phy_gx_mbps,
- g_phy_rx_fifo_size => c_phy_rx_fifo_size,
- g_phy_ena_reorder => c_phy_ena_reorder,
- -- Tx
- g_use_tx => c_use_tx,
- g_tx_input_use_fifo => c_tx_input_use_fifo,
- g_tx_input_fifo_size => c_tx_input_fifo_size,
- g_tx_input_fifo_fill => c_tx_input_fifo_fill,
- -- Rx
- g_use_rx => c_use_rx,
- g_rx_output_use_fifo => c_rx_output_use_fifo,
- g_rx_output_fifo_size => c_rx_output_fifo_size,
- g_rx_output_fifo_fill => c_rx_output_fifo_fill,
- g_rx_timeout_w => c_rx_timeout_w,
- -- Monitoring
- g_mon_select => c_mon_select,
- g_mon_nof_words => c_mon_nof_words,
- g_mon_use_sync => c_mon_use_sync,
- -- UTH
- g_uth_len_max => c_uth_len_max,
- g_uth_typ_ofs => c_uth_typ_ofs,
-
- -- Auxiliary Interface
- g_aux => c_unb1_board_aux,
- -- BSN ALIGNER
- g_use_bsn_align => c_use_bsn_align,
- -- DATA BUFFER
- g_use_data_buf => c_use_data_buf
- )
- port map(
- -- System
- chip_id => this_chip_id,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => SB_CLK,
- cal_clk => cal_clk,
-
- -- MM interface
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- -- Datapath User interface (4 nodes)(4 input streams)
- tx_usr_siso_2arr => tx_usr_siso_2arr,
- tx_usr_sosi_2arr => tx_usr_sosi_2arr,
- rx_usr_siso_2arr => rx_usr_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr,
-
- -- Mesh serial interface (tr_nonbonded)
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+
+ -- BLOCK GENERATOR
+ g_use_bg => c_use_bg,
+
+ -- MESH TERMINAL
+ -- System
+ g_node_type => c_node_type,
+ g_nof_bus => c_nof_bus,
+ -- User
+ g_usr_use_complex => c_usr_use_complex,
+ g_usr_data_w => c_usr_data_w,
+ g_usr_frame_len => c_usr_frame_len,
+ g_usr_nof_streams => c_usr_nof_streams,
+ -- Phy
+ g_phy_nof_serial => c_phy_nof_serial,
+ g_phy_gx_mbps => c_phy_gx_mbps,
+ g_phy_rx_fifo_size => c_phy_rx_fifo_size,
+ g_phy_ena_reorder => c_phy_ena_reorder,
+ -- Tx
+ g_use_tx => c_use_tx,
+ g_tx_input_use_fifo => c_tx_input_use_fifo,
+ g_tx_input_fifo_size => c_tx_input_fifo_size,
+ g_tx_input_fifo_fill => c_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => c_use_rx,
+ g_rx_output_use_fifo => c_rx_output_use_fifo,
+ g_rx_output_fifo_size => c_rx_output_fifo_size,
+ g_rx_output_fifo_fill => c_rx_output_fifo_fill,
+ g_rx_timeout_w => c_rx_timeout_w,
+ -- Monitoring
+ g_mon_select => c_mon_select,
+ g_mon_nof_words => c_mon_nof_words,
+ g_mon_use_sync => c_mon_use_sync,
+ -- UTH
+ g_uth_len_max => c_uth_len_max,
+ g_uth_typ_ofs => c_uth_typ_ofs,
+
+ -- Auxiliary Interface
+ g_aux => c_unb1_board_aux,
+ -- BSN ALIGNER
+ g_use_bsn_align => c_use_bsn_align,
+ -- DATA BUFFER
+ g_use_data_buf => c_use_data_buf
+ )
+ port map(
+ -- System
+ chip_id => this_chip_id,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => SB_CLK,
+ cal_clk => cal_clk,
+
+ -- MM interface
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ -- Datapath User interface (4 nodes)(4 input streams)
+ tx_usr_siso_2arr => tx_usr_siso_2arr,
+ tx_usr_sosi_2arr => tx_usr_sosi_2arr,
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr,
+
+ -- Mesh serial interface (tr_nonbonded)
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr
+ );
-----------------------------------------------------------------------------
-- Mesh I/O
@@ -454,23 +454,23 @@ begin
gen_tr_mesh : if c_use_phy.tr_mesh /= 0 generate
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_unb1_board_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr,
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_TX,
- FN_BN_0_RX => FN_BN_0_RX,
- FN_BN_1_TX => FN_BN_1_TX,
- FN_BN_1_RX => FN_BN_1_RX,
- FN_BN_2_TX => FN_BN_2_TX,
- FN_BN_2_RX => FN_BN_2_RX,
- FN_BN_3_TX => FN_BN_3_TX,
- FN_BN_3_RX => FN_BN_3_RX
- );
+ generic map (
+ g_bus_w => c_unb1_board_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr,
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX
+ );
end generate;
-end;
+ end;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
index 4069b5616d..72017dce77 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
@@ -28,12 +28,12 @@
-- > run 10 us
library IEEE, common_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.tb_unb1_board_pkg.all;
entity tb_unb1_terminal_bg_mesh_db is
end tb_unb1_terminal_bg_mesh_db;
@@ -115,134 +115,134 @@ begin
------------------------------------------------------------------------------
gen_bn: for BN in 0 to c_nof_bn - 1 generate
u_bn : entity work.unb1_terminal_bg_mesh_db
- generic map (
- -- General
- g_sim => c_sim,
- g_sim_level => c_sim_level,
- g_sim_unb_nr => c_sim_unb_nr,
- g_sim_node_nr => (BN + 4)
- )
- port map (
- -- GENERAL
- WDI => WDI,
- CLK => ext_clk,
- PPS => ext_pps,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => TO_UVEC(BN + 4, c_unb1_board_aux.id_w), -- BN chip ID 4,5,6,7
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
- ETH_SGIN => eth_rxp(BN + c_nof_fn),
- ETH_SGOUT => eth_txp(BN + c_nof_fn),
-
- -- Transceiver clocks
- SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
-
- -- Mesh serial I/O
- FN_BN_0_TX => FN_BN_0_TX_arr(BN + c_nof_fn),
- FN_BN_0_RX => FN_BN_0_RX_arr(BN + c_nof_fn),
- FN_BN_1_TX => FN_BN_1_TX_arr(BN + c_nof_fn),
- FN_BN_1_RX => FN_BN_1_RX_arr(BN + c_nof_fn),
- FN_BN_2_TX => FN_BN_2_TX_arr(BN + c_nof_fn),
- FN_BN_2_RX => FN_BN_2_RX_arr(BN + c_nof_fn),
- FN_BN_3_TX => FN_BN_3_TX_arr(BN + c_nof_fn),
- FN_BN_3_RX => FN_BN_3_RX_arr(BN + c_nof_fn)
- );
+ generic map (
+ -- General
+ g_sim => c_sim,
+ g_sim_level => c_sim_level,
+ g_sim_unb_nr => c_sim_unb_nr,
+ g_sim_node_nr => (BN + 4)
+ )
+ port map (
+ -- GENERAL
+ WDI => WDI,
+ CLK => ext_clk,
+ PPS => ext_pps,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => TO_UVEC(BN + 4, c_unb1_board_aux.id_w), -- BN chip ID 4,5,6,7
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
+ ETH_SGIN => eth_rxp(BN + c_nof_fn),
+ ETH_SGOUT => eth_txp(BN + c_nof_fn),
+
+ -- Transceiver clocks
+ SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
+
+ -- Mesh serial I/O
+ FN_BN_0_TX => FN_BN_0_TX_arr(BN + c_nof_fn),
+ FN_BN_0_RX => FN_BN_0_RX_arr(BN + c_nof_fn),
+ FN_BN_1_TX => FN_BN_1_TX_arr(BN + c_nof_fn),
+ FN_BN_1_RX => FN_BN_1_RX_arr(BN + c_nof_fn),
+ FN_BN_2_TX => FN_BN_2_TX_arr(BN + c_nof_fn),
+ FN_BN_2_RX => FN_BN_2_RX_arr(BN + c_nof_fn),
+ FN_BN_3_TX => FN_BN_3_TX_arr(BN + c_nof_fn),
+ FN_BN_3_RX => FN_BN_3_RX_arr(BN + c_nof_fn)
+ );
-- Use mesh_io block to create 3arr format for the mesh model.
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_unb1_board_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => bn_in_mesh_serial_3arr(BN),
- rx_serial_2arr => bn_out_mesh_serial_3arr(BN),
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_RX_arr(BN + c_nof_fn),
- FN_BN_0_RX => FN_BN_0_TX_arr(BN + c_nof_fn),
- FN_BN_1_TX => FN_BN_1_RX_arr(BN + c_nof_fn),
- FN_BN_1_RX => FN_BN_1_TX_arr(BN + c_nof_fn),
- FN_BN_2_TX => FN_BN_2_RX_arr(BN + c_nof_fn),
- FN_BN_2_RX => FN_BN_2_TX_arr(BN + c_nof_fn),
- FN_BN_3_TX => FN_BN_3_RX_arr(BN + c_nof_fn),
- FN_BN_3_RX => FN_BN_3_TX_arr(BN + c_nof_fn)
- );
+ generic map (
+ g_bus_w => c_unb1_board_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => bn_in_mesh_serial_3arr(BN),
+ rx_serial_2arr => bn_out_mesh_serial_3arr(BN),
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_RX_arr(BN + c_nof_fn),
+ FN_BN_0_RX => FN_BN_0_TX_arr(BN + c_nof_fn),
+ FN_BN_1_TX => FN_BN_1_RX_arr(BN + c_nof_fn),
+ FN_BN_1_RX => FN_BN_1_TX_arr(BN + c_nof_fn),
+ FN_BN_2_TX => FN_BN_2_RX_arr(BN + c_nof_fn),
+ FN_BN_2_RX => FN_BN_2_TX_arr(BN + c_nof_fn),
+ FN_BN_3_TX => FN_BN_3_RX_arr(BN + c_nof_fn),
+ FN_BN_3_RX => FN_BN_3_TX_arr(BN + c_nof_fn)
+ );
end generate;
gen_fn: for FN in 0 to c_nof_fn - 1 generate
u_fn : entity work.unb1_terminal_bg_mesh_db
- generic map (
- -- General
- g_sim => c_sim,
- g_sim_level => c_sim_level,
- g_sim_unb_nr => c_sim_unb_nr,
- g_sim_node_nr => FN
- )
- port map (
- -- GENERAL
- WDI => WDI,
- CLK => ext_clk,
- PPS => ext_pps,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => TO_UVEC(FN, c_unb1_board_aux.id_w), -- FN chip ID 0,1,2,3,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
- ETH_SGIN => eth_rxp(FN),
- ETH_SGOUT => eth_txp(FN),
-
- -- Transceiver clocks
- SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
-
- -- Mesh serial I/O
- FN_BN_0_TX => FN_BN_0_TX_arr(FN),
- FN_BN_0_RX => FN_BN_0_RX_arr(FN),
- FN_BN_1_TX => FN_BN_1_TX_arr(FN),
- FN_BN_1_RX => FN_BN_1_RX_arr(FN),
- FN_BN_2_TX => FN_BN_2_TX_arr(FN),
- FN_BN_2_RX => FN_BN_2_RX_arr(FN),
- FN_BN_3_TX => FN_BN_3_TX_arr(FN),
- FN_BN_3_RX => FN_BN_3_RX_arr(FN)
- );
+ generic map (
+ -- General
+ g_sim => c_sim,
+ g_sim_level => c_sim_level,
+ g_sim_unb_nr => c_sim_unb_nr,
+ g_sim_node_nr => FN
+ )
+ port map (
+ -- GENERAL
+ WDI => WDI,
+ CLK => ext_clk,
+ PPS => ext_pps,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => TO_UVEC(FN, c_unb1_board_aux.id_w), -- FN chip ID 0,1,2,3,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
+ ETH_SGIN => eth_rxp(FN),
+ ETH_SGOUT => eth_txp(FN),
+
+ -- Transceiver clocks
+ SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
+
+ -- Mesh serial I/O
+ FN_BN_0_TX => FN_BN_0_TX_arr(FN),
+ FN_BN_0_RX => FN_BN_0_RX_arr(FN),
+ FN_BN_1_TX => FN_BN_1_TX_arr(FN),
+ FN_BN_1_RX => FN_BN_1_RX_arr(FN),
+ FN_BN_2_TX => FN_BN_2_TX_arr(FN),
+ FN_BN_2_RX => FN_BN_2_RX_arr(FN),
+ FN_BN_3_TX => FN_BN_3_TX_arr(FN),
+ FN_BN_3_RX => FN_BN_3_RX_arr(FN)
+ );
-- Use mesh_io block to create 3arr format for the mesh model.
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_unb1_board_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => fn_in_mesh_serial_3arr(FN),
- rx_serial_2arr => fn_out_mesh_serial_3arr(FN),
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_RX_arr(FN),
- FN_BN_0_RX => FN_BN_0_TX_arr(FN),
- FN_BN_1_TX => FN_BN_1_RX_arr(FN),
- FN_BN_1_RX => FN_BN_1_TX_arr(FN),
- FN_BN_2_TX => FN_BN_2_RX_arr(FN),
- FN_BN_2_RX => FN_BN_2_TX_arr(FN),
- FN_BN_3_TX => FN_BN_3_RX_arr(FN),
- FN_BN_3_RX => FN_BN_3_TX_arr(FN)
- );
+ generic map (
+ g_bus_w => c_unb1_board_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => fn_in_mesh_serial_3arr(FN),
+ rx_serial_2arr => fn_out_mesh_serial_3arr(FN),
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_RX_arr(FN),
+ FN_BN_0_RX => FN_BN_0_TX_arr(FN),
+ FN_BN_1_TX => FN_BN_1_RX_arr(FN),
+ FN_BN_1_RX => FN_BN_1_TX_arr(FN),
+ FN_BN_2_TX => FN_BN_2_RX_arr(FN),
+ FN_BN_2_RX => FN_BN_2_TX_arr(FN),
+ FN_BN_3_TX => FN_BN_3_RX_arr(FN),
+ FN_BN_3_RX => FN_BN_3_TX_arr(FN)
+ );
end generate;
-- Direct interconnect BN0<->FN0.
@@ -254,18 +254,18 @@ begin
-- Mesh model
gen_mesh : if c_nof_bn > 1 or c_nof_fn > 1 generate
u_mesh_model_serial : entity unb1_board_lib.unb1_board_mesh_model_sl
- generic map(
- g_reorder => c_ena_mesh_reorder
- )
- port map (
- -- FN to BN
- fn_tx_sl_3arr => fn_out_mesh_serial_3arr,
- bn_rx_sl_3arr => bn_in_mesh_serial_3arr,
-
- -- BN to FN
- bn_tx_sl_3arr => bn_out_mesh_serial_3arr,
- fn_rx_sl_3arr => fn_in_mesh_serial_3arr
- );
+ generic map(
+ g_reorder => c_ena_mesh_reorder
+ )
+ port map (
+ -- FN to BN
+ fn_tx_sl_3arr => fn_out_mesh_serial_3arr,
+ bn_rx_sl_3arr => bn_in_mesh_serial_3arr,
+
+ -- BN to FN
+ bn_tx_sl_3arr => bn_out_mesh_serial_3arr,
+ fn_rx_sl_3arr => fn_in_mesh_serial_3arr
+ );
end generate;
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
index e81056c6c6..86f421d10d 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_10GbE is
end tb_unb1_test_10GbE;
@@ -32,9 +32,9 @@ end tb_unb1_test_10GbE;
architecture tb of tb_unb1_test_10GbE is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_10GbE",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_10GbE",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
index b0979cb122..ba739c6a8c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity unb1_test_10GbE is
generic (
@@ -92,64 +92,64 @@ end unb1_test_10GbE;
architecture str of unb1_test_10GbE is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
- SI_FN_3_TX => SI_FN_3_TX,
- SI_FN_3_RX => SI_FN_3_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL,
- SI_FN_RSTN => SI_FN_RSTN,
-
- BN_BI_0_TX => BN_BI_0_TX,
- BN_BI_0_RX => BN_BI_0_RX,
- BN_BI_1_TX => BN_BI_1_TX,
- BN_BI_1_RX => BN_BI_1_RX,
- BN_BI_2_TX => BN_BI_2_TX,
- BN_BI_2_RX => BN_BI_2_RX,
- BN_BI_3_TX => BN_BI_3_TX,
- BN_BI_3_RX => BN_BI_3_RX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+ SI_FN_3_TX => SI_FN_3_TX,
+ SI_FN_3_RX => SI_FN_3_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL,
+ SI_FN_RSTN => SI_FN_RSTN,
+
+ BN_BI_0_TX => BN_BI_0_TX,
+ BN_BI_0_RX => BN_BI_0_RX,
+ BN_BI_1_TX => BN_BI_1_TX,
+ BN_BI_1_RX => BN_BI_1_RX,
+ BN_BI_2_TX => BN_BI_2_TX,
+ BN_BI_2_RX => BN_BI_2_RX,
+ BN_BI_3_TX => BN_BI_3_TX,
+ BN_BI_3_RX => BN_BI_3_RX
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
index d5bd19a9c3..6086164b66 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_10GbE_tx_only is
end tb_unb1_test_10GbE_tx_only;
@@ -32,9 +32,9 @@ end tb_unb1_test_10GbE_tx_only;
architecture tb of tb_unb1_test_10GbE_tx_only is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_10GbE_tx_only",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_10GbE_tx_only",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
index 3043972db6..7f08e40e55 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity unb1_test_10GbE_tx_only is
generic (
@@ -84,55 +84,55 @@ end unb1_test_10GbE_tx_only;
architecture str of unb1_test_10GbE_tx_only is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
- SI_FN_3_TX => SI_FN_3_TX,
- SI_FN_3_RX => SI_FN_3_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL,
- SI_FN_RSTN => SI_FN_RSTN
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+ SI_FN_3_TX => SI_FN_3_TX,
+ SI_FN_3_RX => SI_FN_3_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL,
+ SI_FN_RSTN => SI_FN_RSTN
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
index c56b4f415a..a7f611f4d0 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_1GbE is
end tb_unb1_test_1GbE;
@@ -32,9 +32,9 @@ end tb_unb1_test_1GbE;
architecture tb of tb_unb1_test_1GbE is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_1GbE",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_1GbE",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
index 4ce67372f9..34e5900286 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity unb1_test_1GbE is
generic (
@@ -64,36 +64,36 @@ end unb1_test_1GbE;
architecture str of unb1_test_1GbE is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
index c5dc616e08..96328fc53d 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_all is
end tb_unb1_test_all;
@@ -32,9 +32,9 @@ end tb_unb1_test_all;
architecture tb of tb_unb1_test_all is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_all",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_all",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
index d17bc71fa1..10748b84a6 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_all is
generic (
@@ -103,72 +103,72 @@ end unb1_test_all;
architecture str of unb1_test_all is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
- SI_FN_3_TX => SI_FN_3_TX,
- SI_FN_3_RX => SI_FN_3_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL,
- SI_FN_RSTN => SI_FN_RSTN,
-
- BN_BI_0_TX => BN_BI_0_TX,
- BN_BI_0_RX => BN_BI_0_RX,
- BN_BI_1_TX => BN_BI_1_TX,
- BN_BI_1_RX => BN_BI_1_RX,
- BN_BI_2_TX => BN_BI_2_TX,
- BN_BI_2_RX => BN_BI_2_RX,
- BN_BI_3_TX => BN_BI_3_TX,
- BN_BI_3_RX => BN_BI_3_RX,
-
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+ SI_FN_3_TX => SI_FN_3_TX,
+ SI_FN_3_RX => SI_FN_3_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL,
+ SI_FN_RSTN => SI_FN_RSTN,
+
+ BN_BI_0_TX => BN_BI_0_TX,
+ BN_BI_0_RX => BN_BI_0_RX,
+ BN_BI_1_TX => BN_BI_1_TX,
+ BN_BI_1_RX => BN_BI_1_RX,
+ BN_BI_2_TX => BN_BI_2_TX,
+ BN_BI_2_RX => BN_BI_2_RX,
+ BN_BI_3_TX => BN_BI_3_TX,
+ BN_BI_3_RX => BN_BI_3_RX,
+
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
index 969c0768bd..877558e130 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr is
end tb_unb1_test_ddr;
@@ -32,9 +32,9 @@ end tb_unb1_test_ddr;
architecture tb of tb_unb1_test_ddr is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
index df41e0d91a..c59916401d 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr is
generic (
@@ -70,44 +70,44 @@ end unb1_test_ddr;
architecture str of unb1_test_ddr is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
--- MB_II_IN => MB_II_IN,
--- MB_II_IO => MB_II_IO,
--- MB_II_OU => MB_II_OU
- );
+ -- MB_II_IN => MB_II_IN,
+ -- MB_II_IO => MB_II_IO,
+ -- MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
index 3dac8535f1..d506dbc63d 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_16g_MB_I is
end tb_unb1_test_ddr_16g_MB_I;
@@ -32,9 +32,9 @@ end tb_unb1_test_ddr_16g_MB_I;
architecture tb of tb_unb1_test_ddr_16g_MB_I is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_16g_MB_I",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_16g_MB_I",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
index 6f4ce8542b..9804c3b49c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_16g_MB_I is
generic (
@@ -70,41 +70,41 @@ end unb1_test_ddr_16g_MB_I;
architecture str of unb1_test_ddr_16g_MB_I is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
- );
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
index 51e1bc635b..3a0dda9a63 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_16g_MB_II is
end tb_unb1_test_ddr_16g_MB_II;
@@ -32,9 +32,9 @@ end tb_unb1_test_ddr_16g_MB_II;
architecture tb of tb_unb1_test_ddr_16g_MB_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_16g_MB_II",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_16g_MB_II",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
index af5925eda5..bb1795b5a7 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_16g_MB_II is
generic (
@@ -70,41 +70,41 @@ end unb1_test_ddr_16g_MB_II;
architecture str of unb1_test_ddr_16g_MB_II is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU
- );
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
index 29cb419b28..c4020b9b5c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_16g_MB_I_II is
end tb_unb1_test_ddr_16g_MB_I_II;
@@ -32,9 +32,9 @@ end tb_unb1_test_ddr_16g_MB_I_II;
architecture tb of tb_unb1_test_ddr_16g_MB_I_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_16g_MB_I_II",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_16g_MB_I_II",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
index 8b8d0ee03e..a1c054a46b 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_16g_MB_I_II is
generic (
@@ -75,46 +75,46 @@ end unb1_test_ddr_16g_MB_I_II;
architecture str of unb1_test_ddr_16g_MB_I_II is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU
- );
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
index 12ef191769..3fd67acfea 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_MB_I is
end tb_unb1_test_ddr_MB_I;
@@ -32,9 +32,9 @@ end tb_unb1_test_ddr_MB_I;
architecture tb of tb_unb1_test_ddr_MB_I is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_MB_I",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_MB_I",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
index dda6de3531..631e141bfe 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_MB_II is
end tb_unb1_test_ddr_MB_II;
@@ -32,9 +32,9 @@ end tb_unb1_test_ddr_MB_II;
architecture tb of tb_unb1_test_ddr_MB_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_MB_II",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_MB_II",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
index c1f597d928..c18c9608a3 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_MB_I_II is
end tb_unb1_test_ddr_MB_I_II;
@@ -32,9 +32,9 @@ end tb_unb1_test_ddr_MB_I_II;
architecture tb of tb_unb1_test_ddr_MB_I_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_MB_I_II",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 1 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_MB_I_II",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 1 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
index f5524185b2..9eead96dc4 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_MB_I_II is
generic (
@@ -75,46 +75,46 @@ end unb1_test_ddr_MB_I_II;
architecture str of unb1_test_ddr_MB_I_II is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU
- );
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 7e468fa82d..5a7b55b519 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb1_test_pkg.all;
-use work.unb1_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb1_test_pkg.all;
+ use work.unb1_test_pkg.all;
entity mmm_unb1_test is
generic (
@@ -258,103 +258,143 @@ begin
gen_mm_file_io : if g_sim = true generate
eth1g_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso);
-
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso);
-
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso);
-
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso);
-
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso);
-
- u_mm_file_reg_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
- u_mm_file_ram_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
- u_mm_file_reg_diag_tx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
-
- u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
- u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
- u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
-
- u_mm_file_reg_dp_offload_tx_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
- port map(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
- u_mm_file_reg_dp_offload_tx_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE")
- port map(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_mosi, reg_dp_offload_tx_10GbE_miso);
-
- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
- port map(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
- u_mm_file_reg_dp_offload_tx_10GbE_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE_HDR_DAT")
- port map(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_hdr_dat_mosi, reg_dp_offload_tx_10GbE_hdr_dat_miso);
-
- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
- port map(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
- u_mm_file_reg_dp_offload_rx_10GbE_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_10GBE_HDR_DAT")
- port map(mm_rst, mm_clk, reg_dp_offload_rx_10GbE_hdr_dat_mosi, reg_dp_offload_rx_10GbE_hdr_dat_miso);
-
- u_mm_file_reg_bsn_monitor_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
- u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
- u_mm_file_ram_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
- u_mm_file_reg_diag_rx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
- u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
- u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
-
- u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
-
- u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-
- u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
- port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
- u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
- port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
-
- u_mm_file_reg_tr_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE") -- , c_mm_clk_period, FALSE, 0)
- port map(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso);
-
- u_mm_file_reg_tr_xaui : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI") -- , c_mm_clk_period, FALSE, 0)
- port map(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso);
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso);
+
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso);
+
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso);
+
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso);
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso);
+
+ u_mm_file_reg_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+ u_mm_file_ram_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
+ u_mm_file_reg_diag_tx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
+
+ u_mm_file_reg_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+ u_mm_file_ram_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+ u_mm_file_reg_diag_tx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+
+ u_mm_file_reg_dp_offload_tx_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+ port map(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+ u_mm_file_reg_dp_offload_tx_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE")
+ port map(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_mosi, reg_dp_offload_tx_10GbE_miso);
+
+ u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
+ u_mm_file_reg_dp_offload_tx_10GbE_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_hdr_dat_mosi, reg_dp_offload_tx_10GbE_hdr_dat_miso);
+
+ u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
+ u_mm_file_reg_dp_offload_rx_10GbE_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_10GBE_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_dp_offload_rx_10GbE_hdr_dat_mosi, reg_dp_offload_rx_10GbE_hdr_dat_miso);
+
+ u_mm_file_reg_bsn_monitor_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
+ u_mm_file_reg_bsn_monitor_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
+ u_mm_file_ram_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
+ u_mm_file_reg_diag_rx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+ u_mm_file_ram_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+ u_mm_file_reg_diag_rx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+
+ u_mm_file_reg_io_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+ u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+ u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+ u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+ u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_reg_io_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+ u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+ u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+ u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+ u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+
+ u_mm_file_eth1g_reg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_eth1g_ram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
+ port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+ u_mm_file_eth1g_tse : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
+ port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+
+ u_mm_file_reg_tr_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE") -- , c_mm_clk_period, FALSE, 0)
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso);
+
+ u_mm_file_reg_tr_xaui : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI") -- , c_mm_clk_period, FALSE, 0)
+ port map(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -379,10 +419,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_reg_mosi <= sim_eth1g_reg_mosi;
- else
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
- end if;
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ else
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -796,7 +836,7 @@ begin
ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0)
- );
+ );
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
index 3c257fae3c..c712afa044 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
@@ -20,340 +20,340 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb1_test_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
- -----------------------------------------------------------------------------
- component qsys_unb1_test is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
- coe_waitrequest_export_to_the_reg_tr_10GbE : in std_logic := 'X'; -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_tr_xaui : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_tr_xaui : out std_logic_vector(10 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_waitrequest_export_to_the_reg_tr_xaui : in std_logic := 'X'; -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_reset_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
- coe_address_export_from_the_reg_tr_10GbE : out std_logic_vector(14 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_tr_xaui : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_tr_10GbE : out std_logic_vector(31 downto 0); -- export
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_clk_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_clk_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- coe_readdata_export_to_the_reg_tr_10GbE : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reset_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_remu : out std_logic; -- export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(11 downto 0); -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_10gbe_read_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_10gbe_write_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_offload_tx_10gbe_clk_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_offload_tx_1gbe_write_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_1gbe_read_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_1gbe_write_export : out std_logic; -- export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_1gbe_read_export : out std_logic; -- export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0); -- export
- ram_diag_bg_1gbe_write_export : out std_logic; -- export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_1gbe_read_export : out std_logic; -- export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_unb1_test;
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
+ -----------------------------------------------------------------------------
+ component qsys_unb1_test is
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
+ coe_waitrequest_export_to_the_reg_tr_10GbE : in std_logic := 'X'; -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_tr_xaui : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_tr_xaui : out std_logic_vector(10 downto 0); -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_waitrequest_export_to_the_reg_tr_xaui : in std_logic := 'X'; -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_reset_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_tr_10GbE : out std_logic_vector(14 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_tr_xaui : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_tr_10GbE : out std_logic_vector(31 downto 0); -- export
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_clk_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic; -- export
+ coe_write_export_from_the_reg_remu : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_clk_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
+ coe_readdata_export_to_the_reg_tr_10GbE : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reset_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_remu : out std_logic; -- export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_10gbe_read_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_10gbe_write_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_offload_tx_10gbe_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_offload_tx_1gbe_write_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_1gbe_read_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0); -- export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_unb1_test;
end qsys_unb1_test_pkg;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
index 2d696a1218..ddfc7aefd2 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
@@ -21,18 +21,18 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb1_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb1_test_pkg.all;
entity udp_stream is
generic (
@@ -100,14 +100,15 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable (disabled by default)
+ '0', -- enable_sync
+ TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "1001" & "111011111100" & "0001" & "101111111";
constant c_nof_crc_words : natural := 1;
@@ -149,124 +150,124 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl,
- g_use_tx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl,
+ g_use_tx_seq => true
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
--- reg_mosi => reg_dp_offload_tx_mosi,
--- reg_miso => reg_dp_offload_tx_miso,
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ -- reg_mosi => reg_dp_offload_tx_mosi,
+ -- reg_miso => reg_dp_offload_tx_miso,
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
@@ -287,50 +288,50 @@ begin
end generate;
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index 428faa733e..7f0c8c2e4c 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -21,21 +21,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, io_ddr_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb1_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb1_test_pkg.all;
entity unb1_test is
generic (
@@ -115,20 +115,21 @@ architecture str of unb1_test is
-- Firmware version x.y
constant c_fw_version : t_unb1_board_fw_version := (1, 2);
- -- Select the according revision record based on the design name.
+ -- Select the according revision record based on the design name.
constant c_revision_select : t_unb1_test_config := func_unb1_test_sel_revision_rec(g_design_name);
-- ddr
constant c_nof_MB : natural := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
- constant c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(c_revision_select.use_streaming_1GbE, 1, 0),
- c_revision_select.use_front, 0,
- c_revision_select.use_back,
- c_revision_select.use_ddr_MB_I,
- c_revision_select.use_ddr_MB_II,
- 0,
- 1);
+ constant c_use_phy : t_c_unb1_board_use_phy := (
+ sel_a_b(c_revision_select.use_streaming_1GbE, 1, 0),
+ c_revision_select.use_front, 0,
+ c_revision_select.use_back,
+ c_revision_select.use_ddr_MB_I,
+ c_revision_select.use_ddr_MB_II,
+ 0,
+ 1);
constant c_nof_streams_10GbE : natural := c_revision_select.use_nof_streams_10GbE;
constant c_nof_streams_1GbE : natural := c_revision_select.use_nof_streams_1GbE;
@@ -334,7 +335,7 @@ architecture str of unb1_test is
signal reg_io_ddr_MB_II_mosi : t_mem_mosi;
signal reg_io_ddr_MB_II_miso : t_mem_miso;
- -- DDR3 pass on termination control from master to slave controller
+ -- DDR3 pass on termination control from master to slave controller
signal term_ctrl_out : t_tech_ddr3_phy_terminationcontrol;
signal term_ctrl_in : t_tech_ddr3_phy_terminationcontrol;
@@ -344,412 +345,412 @@ architecture str of unb1_test is
signal MB_II_ctlr_rst : std_logic;
begin
u_areset_ddr_ref_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 40
- )
- port map(
- clk => CLK,
- in_rst => mm_rst,
- out_rst => ddr_ref_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ port map(
+ clk => CLK,
+ in_rst => mm_rst,
+ out_rst => ddr_ref_rst
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_udp_offload => c_revision_select.use_streaming_1GbE,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- g_dp_clk_use_pll => true,
- g_xo_clk_use_pll => true
- )
- port map (
- -- Clock and reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk_out => mm_clk,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_locked => mm_locked,
- mm_locked_out => mm_locked,
-
- epcs_clk => epcs_clk,
- epcs_clk_out => epcs_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- cal_rec_clk => cal_rec_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk_out => eth1g_tse_clk,
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => dp_offload_tx_1GbE_src_out_arr,
- udp_tx_siso_arr => dp_offload_tx_1GbE_src_in_arr,
- udp_rx_sosi_arr => dp_offload_rx_1GbE_snk_in_arr,
- udp_rx_siso_arr => dp_offload_rx_1GbE_snk_out_arr,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
--- END GENERATE;
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_udp_offload => c_revision_select.use_streaming_1GbE,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ g_dp_clk_use_pll => true,
+ g_xo_clk_use_pll => true
+ )
+ port map (
+ -- Clock and reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ cal_rec_clk => cal_rec_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => dp_offload_tx_1GbE_src_out_arr,
+ udp_tx_siso_arr => dp_offload_tx_1GbE_src_in_arr,
+ udp_rx_sosi_arr => dp_offload_rx_1GbE_snk_in_arr,
+ udp_rx_siso_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+ -- END GENERATE;
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_nof_streams_1GbE => c_nof_streams_1GbE,
- g_nof_streams_10GbE => 3, -- c_nof_streams_10GbE,
- g_nof_streams_ddr => 1, -- c_nof_streams_ddr,
- g_bg_block_size => c_bg_block_size
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- block gen
- ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
- reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
- reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
-
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
-
- reg_dp_offload_tx_10GbE_mosi => reg_dp_offload_tx_10GbE_mosi,
- reg_dp_offload_tx_10GbE_miso => reg_dp_offload_tx_10GbE_miso,
- reg_dp_offload_tx_10GbE_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
- reg_dp_offload_tx_10GbE_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
-
- -- dp_offload_rx
- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-
- reg_dp_offload_rx_10GbE_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
- reg_dp_offload_rx_10GbE_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
-
- -- bsn
- reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
-
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- tr_10GbE
- reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
- reg_tr_10GbE_miso => reg_tr_10GbE_miso,
- reg_tr_xaui_mosi => reg_tr_xaui_mosi,
- reg_tr_xaui_miso => reg_tr_xaui_miso,
-
- -- DDR3 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
-
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
-
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR3 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
-
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
-
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
- );
-
- gen_udp_stream_1GbE : if c_revision_select.use_streaming_1GbE = true generate
- u_udp_stream_1GbE : entity work.udp_stream
generic map (
- g_sim => g_sim,
- g_nof_streams => c_nof_streams_1GbE,
- g_data_w => c_data_w_32,
- g_bg_block_size => c_def_1GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_1GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_1GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => true
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_nof_streams_1GbE => c_nof_streams_1GbE,
+ g_nof_streams_10GbE => 3, -- c_nof_streams_10GbE,
+ g_nof_streams_ddr => 1, -- c_nof_streams_ddr,
+ g_bg_block_size => c_bg_block_size
)
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- block gen
+ ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
+
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-- dp_offload_tx
- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+ reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
+ reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
+ reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+
+ reg_dp_offload_tx_10GbE_mosi => reg_dp_offload_tx_10GbE_mosi,
+ reg_dp_offload_tx_10GbE_miso => reg_dp_offload_tx_10GbE_miso,
+ reg_dp_offload_tx_10GbE_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_10GbE_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
-- dp_offload_rx
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+ reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+
+ reg_dp_offload_rx_10GbE_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_10GbE_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
-- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
+
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- tr_10GbE
+ reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
+ reg_tr_10GbE_miso => reg_tr_10GbE_miso,
+ reg_tr_xaui_mosi => reg_tr_xaui_mosi,
+ reg_tr_xaui_miso => reg_tr_xaui_miso,
+
+ -- DDR3 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR3 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
+
+ gen_udp_stream_1GbE : if c_revision_select.use_streaming_1GbE = true generate
+ u_udp_stream_1GbE : entity work.udp_stream
+ generic map (
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams_1GbE,
+ g_data_w => c_data_w_32,
+ g_bg_block_size => c_def_1GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_1GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_1GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+
+ -- dp_offload_tx
+ reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
+ reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+
+ -- dp_offload_rx
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ );
end generate;
gen_udp_stream_10GbE : if c_revision_select.use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_nof_streams => c_nof_streams_10GbE,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_def_10GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen mm
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
- reg_dp_offload_tx_mosi => reg_dp_offload_tx_10GbE_mosi,
- reg_dp_offload_tx_miso => reg_dp_offload_tx_10GbE_miso,
- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
-
- -- dp_offload_rx
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- -- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams_10GbE,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_def_10GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen mm
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+ -- dp_offload_tx
+ reg_dp_offload_tx_mosi => reg_dp_offload_tx_10GbE_mosi,
+ reg_dp_offload_tx_miso => reg_dp_offload_tx_10GbE_miso,
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ -- dp_offload_rx
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
end generate;
-----------------------------------------------------------------------------
@@ -757,62 +758,62 @@ begin
-----------------------------------------------------------------------------
u_areset_sa_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map(
- clk => SA_CLK,
- in_rst => '0',
- out_rst => sa_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map(
+ clk => SA_CLK,
+ in_rst => '0',
+ out_rst => sa_rst
+ );
gen_tr_10GbE : if c_revision_select.use_10GbE = true generate
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_streams_10GbE,
- g_use_mdio => true,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk_156 => SA_CLK,
- tr_ref_rst_156 => sa_rst,
-
- cal_rec_clk => cal_rec_clk, -- mm_clk, --cal_clk, mm_clk required by XAUI phy
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mosi,
- reg_mac_miso => reg_tr_10GbE_miso,
-
- xaui_mosi => reg_tr_xaui_mosi,
- xaui_miso => reg_tr_xaui_miso,
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr,
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
-
- -- Serial XAUI IO
- xaui_tx_arr => i_xaui_tx_arr,
- xaui_rx_arr => i_xaui_rx_arr,
-
- -- MDIO External clock and serial data.
- mdio_rst => SI_FN_RSTN,
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_streams_10GbE,
+ g_use_mdio => true,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk_156 => SA_CLK,
+ tr_ref_rst_156 => sa_rst,
+
+ cal_rec_clk => cal_rec_clk, -- mm_clk, --cal_clk, mm_clk required by XAUI phy
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
+
+ xaui_mosi => reg_tr_xaui_mosi,
+ xaui_miso => reg_tr_xaui_miso,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr,
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
+
+ -- Serial XAUI IO
+ xaui_tx_arr => i_xaui_tx_arr,
+ xaui_rx_arr => i_xaui_rx_arr,
+
+ -- MDIO External clock and serial data.
+ mdio_rst => SI_FN_RSTN,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
+ );
-- Wire together different types
gen_wires: for i in 0 to c_nof_streams_10GbE-1 generate
@@ -821,158 +822,158 @@ begin
end generate;
gen_tr_front : if c_revision_select.use_front = 1 generate
- u_front_io : entity unb1_board_lib.unb1_board_front_io
- generic map (
- g_nof_xaui => c_nof_streams_10GbE
- )
- port map (
- xaui_tx_arr => xaui_tx_arr,
- xaui_rx_arr => xaui_rx_arr,
-
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL
- );
+ u_front_io : entity unb1_board_lib.unb1_board_front_io
+ generic map (
+ g_nof_xaui => c_nof_streams_10GbE
+ )
+ port map (
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
+
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL
+ );
end generate;
end generate;
-gen_mms_io_ddr_diag_MB_I : if c_revision_select.use_ddr_MB_I = 1 generate
- u_mms_io_ddr_diag_MB_I : entity io_ddr_lib.mms_io_ddr_diag
- generic map(
- -- System
- g_technology => g_technology,
- g_dp_data_w => c_data_w_64,
- g_dp_seq_dat_w => c_seq_dat_w,
- g_dp_wr_fifo_depth => c_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => c_revision_select.use_tech_ddr,
- -- DIAG data buffer
- g_db_use_db => c_use_db,
- g_db_buf_nof_data => c_buf_nof_data
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- DDR reference clock
- ctlr_ref_clk => CLK,
- ctlr_ref_rst => ddr_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => MB_I_ctlr_clk,
- ctlr_rst_out => MB_I_ctlr_rst,
-
- ctlr_clk_in => MB_I_ctlr_clk,
- ctlr_rst_in => MB_I_ctlr_rst,
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR3 pass on signals from master to slave controller
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
- -- DDR3 PHY external interface
- phy3_in => MB_I_IN,
- phy3_io => MB_I_IO,
- phy3_ou => MB_I_OU,
-
- -- DIAG Tx seq
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- -- DIAG rx seq with optional data buffer
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ gen_mms_io_ddr_diag_MB_I : if c_revision_select.use_ddr_MB_I = 1 generate
+ u_mms_io_ddr_diag_MB_I : entity io_ddr_lib.mms_io_ddr_diag
+ generic map(
+ -- System
+ g_technology => g_technology,
+ g_dp_data_w => c_data_w_64,
+ g_dp_seq_dat_w => c_seq_dat_w,
+ g_dp_wr_fifo_depth => c_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_rd_fifo_depth,
+ -- IO_DDR
+ g_io_tech_ddr => c_revision_select.use_tech_ddr,
+ -- DIAG data buffer
+ g_db_use_db => c_use_db,
+ g_db_buf_nof_data => c_buf_nof_data
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- DDR reference clock
+ ctlr_ref_clk => CLK,
+ ctlr_ref_rst => ddr_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => MB_I_ctlr_clk,
+ ctlr_rst_out => MB_I_ctlr_rst,
+
+ ctlr_clk_in => MB_I_ctlr_clk,
+ ctlr_rst_in => MB_I_ctlr_rst,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR3 pass on signals from master to slave controller
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ -- DDR3 PHY external interface
+ phy3_in => MB_I_IN,
+ phy3_io => MB_I_IO,
+ phy3_ou => MB_I_OU,
+
+ -- DIAG Tx seq
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ -- DIAG rx seq with optional data buffer
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
-gen_mms_io_ddr_diag_MB_II : if c_revision_select.use_ddr_MB_II = 1 generate
- u_mms_io_ddr_diag_MB_II : entity io_ddr_lib.mms_io_ddr_diag
- generic map(
- -- System
- g_technology => g_technology,
- g_dp_data_w => c_data_w_64,
- g_dp_seq_dat_w => c_seq_dat_w,
- g_dp_wr_fifo_depth => c_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => c_revision_select.use_tech_ddr,
- -- DIAG data buffer
- g_db_use_db => c_use_db,
- g_db_buf_nof_data => c_buf_nof_data
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- DDR reference clock
- ctlr_ref_clk => CLK,
- ctlr_ref_rst => ddr_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => MB_II_ctlr_clk,
- ctlr_rst_out => MB_II_ctlr_rst,
-
- ctlr_clk_in => MB_II_ctlr_clk,
- ctlr_rst_in => MB_II_ctlr_rst,
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR3 pass on signals from master to slave controller
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
- -- DDR3 PHY external interface
- phy3_in => MB_II_IN,
- phy3_io => MB_II_IO,
- phy3_ou => MB_II_OU,
-
- -- DIAG Tx seq
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- -- DIAG rx seq with optional data buffer
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ gen_mms_io_ddr_diag_MB_II : if c_revision_select.use_ddr_MB_II = 1 generate
+ u_mms_io_ddr_diag_MB_II : entity io_ddr_lib.mms_io_ddr_diag
+ generic map(
+ -- System
+ g_technology => g_technology,
+ g_dp_data_w => c_data_w_64,
+ g_dp_seq_dat_w => c_seq_dat_w,
+ g_dp_wr_fifo_depth => c_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_rd_fifo_depth,
+ -- IO_DDR
+ g_io_tech_ddr => c_revision_select.use_tech_ddr,
+ -- DIAG data buffer
+ g_db_use_db => c_use_db,
+ g_db_buf_nof_data => c_buf_nof_data
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- DDR reference clock
+ ctlr_ref_clk => CLK,
+ ctlr_ref_rst => ddr_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => MB_II_ctlr_clk,
+ ctlr_rst_out => MB_II_ctlr_rst,
+
+ ctlr_clk_in => MB_II_ctlr_clk,
+ ctlr_rst_in => MB_II_ctlr_rst,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR3 pass on signals from master to slave controller
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ -- DDR3 PHY external interface
+ phy3_in => MB_II_IN,
+ phy3_io => MB_II_IO,
+ phy3_ou => MB_II_OU,
+
+ -- DIAG Tx seq
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ -- DIAG rx seq with optional data buffer
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
index a1c4f5a385..cede083e66 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
@@ -20,11 +20,11 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
package unb1_test_pkg is
type t_unb1_test_config is record
@@ -42,35 +42,36 @@ package unb1_test_pkg is
-- dp_offload_tx
constant c_nof_hdr_fields : natural := 4 + 12 + 4 + 9; -- Total header bits = 512
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
- ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
- ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
- ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
- ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
- ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
- ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
- ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
- ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
+ constant c_hdr_field_arr : t_common_field_arr(
+ c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
+ ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
-- Function to select the revision configuration.
function func_unb1_test_sel_revision_rec(g_design_name : string) return t_unb1_test_config;
diff --git a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
index fd3eea1c89..0cd5280da3 100644
--- a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
@@ -45,21 +45,21 @@
library ip_stratixiv_ddr3_mem_model_lib;
library IEEE, common_lib, unb1_board_lib, i2c_lib, io_ddr_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
-use work.unb1_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
+ use work.unb1_test_pkg.all;
entity tb_unb1_test is
- generic (
- g_design_name : string := "unb1_test";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
- );
+ generic (
+ g_design_name : string := "unb1_test";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7 -- Back node 3
+ );
end tb_unb1_test;
architecture tb of tb_unb1_test is
@@ -218,14 +218,14 @@ begin
------------------------------------------------------------------------------
gen_tech_ddr_memory_model_MB_I : if c_revision_select.use_ddr_MB_I = 1 generate
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_revision_select.use_tech_ddr
- )
- port map (
- mem3_in => phy_MB_I_ou,
- mem3_io => phy_MB_I_io,
- mem3_ou => phy_MB_I_in
- );
+ generic map (
+ g_tech_ddr => c_revision_select.use_tech_ddr
+ )
+ port map (
+ mem3_in => phy_MB_I_ou,
+ mem3_io => phy_MB_I_io,
+ mem3_ou => phy_MB_I_in
+ );
end generate;
------------------------------------------------------------------------------
@@ -233,14 +233,14 @@ begin
------------------------------------------------------------------------------
gen_tech_ddr_memory_model_MB_II : if c_revision_select.use_ddr_MB_II = 1 generate
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_revision_select.use_tech_ddr
- )
- port map (
- mem3_in => phy_MB_II_ou,
- mem3_io => phy_MB_II_io,
- mem3_ou => phy_MB_II_in
- );
+ generic map (
+ g_tech_ddr => c_revision_select.use_tech_ddr
+ )
+ port map (
+ mem3_in => phy_MB_II_ou,
+ mem3_io => phy_MB_II_io,
+ mem3_ou => phy_MB_II_in
+ );
end generate;
------------------------------------------------------------------------------
@@ -248,36 +248,36 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd
index 2a79752d43..04dc9bee09 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd
@@ -20,23 +20,23 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity mmm_unb1_tr_10GbE is
generic (
@@ -252,7 +252,7 @@ begin
mm_rst_n <= not(mm_rst);
u_qsys_unb1_tr_10GbE : qsys_unb1_tr_10GbE
- port map(
+ port map(
clk_in_clk => mm_clk,
eth1g_irq_export => eth1g_reg_interrupt,
eth1g_mm_clk_export => OPEN,
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
index 289839f6e9..07a23898f7 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
@@ -21,22 +21,22 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, diag_lib, dp_lib, eth_lib, tech_tse_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-
--- Purpose:
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+
+ -- Purpose:
entity unb1_tr_10GbE is
generic (
@@ -86,7 +86,7 @@ entity unb1_tr_10GbE is
SI_FN_2_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_3_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_RSTN : out std_logic := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
- -- So we need to assign a '1' to it.
+ -- So we need to assign a '1' to it.
);
end unb1_tr_10GbE;
@@ -98,14 +98,15 @@ architecture str of unb1_tr_10GbE is
constant c_bg_block_size : natural := 176;
constant c_bg_gapsize : natural := 256 - 176;
constant c_bg_blocks_per_sync : natural := 100;
- constant c_bg_ctrl : t_diag_block_gen := (sel_a_b(g_sim, '1', '0'), -- enable: On by default in simulation; MM enable required on hardware.
- '0', -- enable_sync
- TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ sel_a_b(g_sim, '1', '0'), -- enable: On by default in simulation; MM enable required on hardware.
+ '0', -- enable_sync
+ TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
-- System
signal cs_sim : std_logic;
signal xo_clk : std_logic;
@@ -194,25 +195,25 @@ begin
-- TX: 3 Block generators
-----------------------------------------------------------------------------
u_mms_diag_block_gen : entity diag_lib.mms_diag_block_gen
- generic map (
- g_nof_streams => c_nof_10GbE_streams,
- g_buf_dat_w => 64,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_name_prefix => "hex/composite_signals",
- g_diag_block_gen_rst => c_bg_ctrl
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
-
- out_sosi_arr => mms_diag_block_gen_src_out_arr
- );
+ generic map (
+ g_nof_streams => c_nof_10GbE_streams,
+ g_buf_dat_w => 64,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_name_prefix => "hex/composite_signals",
+ g_diag_block_gen_rst => c_bg_ctrl
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+
+ out_sosi_arr => mms_diag_block_gen_src_out_arr
+ );
-----------------------------------------------------------------------------
-- 10GbE TX/RX
@@ -224,294 +225,294 @@ begin
end generate;
u_front_io : entity unb1_board_lib.unb1_board_front_io
- generic map (
- g_nof_xaui => c_nof_10GbE_streams
- )
- port map (
- xaui_tx_arr => unb_xaui_tx_arr,
- xaui_rx_arr => unb_xaui_rx_arr,
-
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL
- );
+ generic map (
+ g_nof_xaui => c_nof_10GbE_streams
+ )
+ port map (
+ xaui_tx_arr => unb_xaui_tx_arr,
+ xaui_rx_arr => unb_xaui_rx_arr,
+
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL
+ );
u_areset_sa_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map(
- clk => SA_CLK,
- in_rst => '0',
- out_rst => sa_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map(
+ clk => SA_CLK,
+ in_rst => '0',
+ out_rst => sa_rst
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map(
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_10GbE_streams,
- g_use_mdio => true
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_156 => SA_CLK,
- tr_ref_rst_156 => sa_rst,
-
- -- Calibration & reconfig clock
- cal_rec_clk => mm_clk,
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mosi,
- reg_mac_miso => reg_tr_10GbE_miso,
-
- xaui_mosi => reg_tr_xaui_mosi,
- xaui_miso => reg_tr_xaui_miso,
-
- mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_streams - 1 downto 0),
- mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_streams - 1 downto 0),
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_snk_in_arr,
- src_in_arr => dp_offload_rx_snk_out_arr,
-
- -- Serial XAUI IO
- xaui_tx_arr => xaui_tx_arr,
- xaui_rx_arr => xaui_rx_arr,
-
- -- MDIO interface
- mdio_rst => SI_FN_RSTN,
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_10GbE_streams,
+ g_use_mdio => true
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_156 => SA_CLK,
+ tr_ref_rst_156 => sa_rst,
+
+ -- Calibration & reconfig clock
+ cal_rec_clk => mm_clk,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
+
+ xaui_mosi => reg_tr_xaui_mosi,
+ xaui_miso => reg_tr_xaui_miso,
+
+ mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_streams - 1 downto 0),
+ mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_streams - 1 downto 0),
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_snk_in_arr,
+ src_in_arr => dp_offload_rx_snk_out_arr,
+
+ -- Serial XAUI IO
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
+
+ -- MDIO interface
+ mdio_rst => SI_FN_RSTN,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
--- u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
--- GENERIC MAP (
--- g_nof_streams => c_nof_10GbE_streams,
--- g_data_w => c_xgmii_data_w,
--- g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr,
--- g_remove_crc => FALSE,
--- g_crc_nof_words => 0
--- )
--- PORT MAP (
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
---
--- dp_rst => dp_rst,
--- dp_clk => dp_clk,
---
--- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
--- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
---
--- snk_in_arr => dp_offload_rx_snk_in_arr,
--- snk_out_arr => dp_offload_rx_snk_out_arr,
---
--- src_out_arr => dp_offload_rx_src_out_arr,
--- src_in_arr => (OTHERS=>c_dp_siso_rdy), --dp_offload_rx_src_in_arr,
---
--- hdr_fields_out_arr => hdr_fields_out_arr
--- );
---
--- gen_restore_bf_out_i : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
--- dp_offload_rx_restored_src_out_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_sync") DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_sync" )));
--- dp_offload_rx_restored_src_out_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" )), c_dp_stream_bsn_w);
---
--- dp_offload_rx_restored_src_out_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
--- dp_offload_rx_restored_src_out_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
--- dp_offload_rx_restored_src_out_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
--- dp_offload_rx_restored_src_out_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
--- dp_offload_rx_restored_src_out_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
--- END GENERATE;
+ -- u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
+ -- GENERIC MAP (
+ -- g_nof_streams => c_nof_10GbE_streams,
+ -- g_data_w => c_xgmii_data_w,
+ -- g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr,
+ -- g_remove_crc => FALSE,
+ -- g_crc_nof_words => 0
+ -- )
+ -- PORT MAP (
+ -- mm_rst => mm_rst,
+ -- mm_clk => mm_clk,
+ --
+ -- dp_rst => dp_rst,
+ -- dp_clk => dp_clk,
+ --
+ -- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ -- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ --
+ -- snk_in_arr => dp_offload_rx_snk_in_arr,
+ -- snk_out_arr => dp_offload_rx_snk_out_arr,
+ --
+ -- src_out_arr => dp_offload_rx_src_out_arr,
+ -- src_in_arr => (OTHERS=>c_dp_siso_rdy), --dp_offload_rx_src_in_arr,
+ --
+ -- hdr_fields_out_arr => hdr_fields_out_arr
+ -- );
+ --
+ -- gen_restore_bf_out_i : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ -- dp_offload_rx_restored_src_out_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_sync") DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_sync" )));
+ -- dp_offload_rx_restored_src_out_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" )), c_dp_stream_bsn_w);
+ --
+ -- dp_offload_rx_restored_src_out_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
+ -- dp_offload_rx_restored_src_out_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
+ -- dp_offload_rx_restored_src_out_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
+ -- dp_offload_rx_restored_src_out_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
+ -- dp_offload_rx_restored_src_out_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
+ -- END GENERATE;
-----------------------------------------------------------------------------
-- RX: BSN monitors at several stages in the stream
-----------------------------------------------------------------------------
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 5,
- g_sync_timeout => 200000000,
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => dp_bsn_monitor_in_siso_arr,
- in_sosi_arr => dp_bsn_monitor_in_sosi_arr
- );
+ generic map (
+ g_nof_streams => 5,
+ g_sync_timeout => 200000000,
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => dp_bsn_monitor_in_siso_arr,
+ in_sosi_arr => dp_bsn_monitor_in_sosi_arr
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_sim_flash_model => false,
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_dp_clk_use_pll => true,
- g_xo_clk_use_pll => true
- )
- port map (
- -- Clock and reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk_out => mm_clk,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_locked => mm_locked,
- mm_locked_out => mm_locked,
-
- epcs_clk => epcs_clk,
- epcs_clk_out => epcs_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- cal_rec_clk => cal_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk_out => eth1g_tse_clk,
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_flash_model => false,
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_dp_clk_use_pll => true,
+ g_xo_clk_use_pll => true
+ )
+ port map (
+ -- Clock and reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ cal_rec_clk => cal_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm_unb1_tr_10GbE : entity work.mmm_unb1_tr_10GbE
- generic map(
- g_sim => g_sim
- )
- port map(
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- pout_wdi => pout_wdi,
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- reg_mdio_0_mosi => reg_mdio_0_mosi,
- reg_mdio_0_miso => reg_mdio_0_miso,
- reg_mdio_1_mosi => reg_mdio_1_mosi,
- reg_mdio_1_miso => reg_mdio_1_miso,
- reg_mdio_2_mosi => reg_mdio_2_mosi,
- reg_mdio_2_miso => reg_mdio_2_miso,
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
- reg_tr_10gbe_mosi => reg_tr_10gbe_mosi,
- reg_tr_10gbe_miso => reg_tr_10gbe_miso,
- reg_tr_xaui_mosi => reg_tr_xaui_mosi,
- reg_tr_xaui_miso => reg_tr_xaui_miso,
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso
- );
+ generic map(
+ g_sim => g_sim
+ )
+ port map(
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ pout_wdi => pout_wdi,
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ reg_mdio_0_mosi => reg_mdio_0_mosi,
+ reg_mdio_0_miso => reg_mdio_0_miso,
+ reg_mdio_1_mosi => reg_mdio_1_mosi,
+ reg_mdio_1_miso => reg_mdio_1_miso,
+ reg_mdio_2_mosi => reg_mdio_2_mosi,
+ reg_mdio_2_miso => reg_mdio_2_miso,
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+ reg_tr_10gbe_mosi => reg_tr_10gbe_mosi,
+ reg_tr_10gbe_miso => reg_tr_10gbe_miso,
+ reg_tr_xaui_mosi => reg_tr_xaui_mosi,
+ reg_tr_xaui_miso => reg_tr_xaui_miso,
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso
+ );
reg_mdio_mosi_arr(0) <= reg_mdio_0_mosi;
reg_mdio_mosi_arr(1) <= reg_mdio_1_mosi;
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
index 3c298d5e15..7290ead563 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
@@ -25,11 +25,11 @@
-- Usage:
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_tr_10GbE is
end tb_unb1_tr_10GbE;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
index a26175ea38..42a02ac88a 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
@@ -26,17 +26,17 @@
-- . node_<design_name>.vhd with the actual functionality of <design_name>
library IEEE, common_lib, mm_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb1_board is
generic (
@@ -364,31 +364,31 @@ begin
gen_pll: if g_dp_clk_use_pll = true generate
u_unb1_board_clk200_pll : entity work.unb1_board_clk200_pll
- generic map (
- g_technology => g_technology,
- g_sel => c_dp_clk_pll_sel,
- g_clk200_phase_shift => g_dp_clk_phase,
- g_clk_vec_w => g_dp_phs_clk_vec_w,
- g_clk1_phase_shift => c_dp_clk1_phase, -- dp_phs_clk_vec(0)
- g_clk2_phase_shift => c_dp_clk2_phase, -- dp_phs_clk_vec(1)
- g_clk3_phase_shift => c_dp_clk3_phase, -- dp_phs_clk_vec(2)
- g_clk4_phase_shift => c_dp_clk4_phase, -- dp_phs_clk_vec(3)
- g_clk5_phase_shift => c_dp_clk5_phase, -- dp_phs_clk_vec(4)
- g_clk6_phase_shift => c_dp_clk6_phase, -- dp_phs_clk_vec(5)
- g_clk1_divide_by => g_dp_phs_clk_divide_by,
- g_clk2_divide_by => g_dp_phs_clk_divide_by,
- g_clk3_divide_by => g_dp_phs_clk_divide_by,
- g_clk4_divide_by => g_dp_phs_clk_divide_by,
- g_clk5_divide_by => g_dp_phs_clk_divide_by,
- g_clk6_divide_by => g_dp_phs_clk_divide_by
- )
- port map (
- arst => dp_dis,
- clk200 => ext_clk,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => dp_rst,
- st_clk_vec => dp_phs_clk_vec -- PLL c6-c1
- );
+ generic map (
+ g_technology => g_technology,
+ g_sel => c_dp_clk_pll_sel,
+ g_clk200_phase_shift => g_dp_clk_phase,
+ g_clk_vec_w => g_dp_phs_clk_vec_w,
+ g_clk1_phase_shift => c_dp_clk1_phase, -- dp_phs_clk_vec(0)
+ g_clk2_phase_shift => c_dp_clk2_phase, -- dp_phs_clk_vec(1)
+ g_clk3_phase_shift => c_dp_clk3_phase, -- dp_phs_clk_vec(2)
+ g_clk4_phase_shift => c_dp_clk4_phase, -- dp_phs_clk_vec(3)
+ g_clk5_phase_shift => c_dp_clk5_phase, -- dp_phs_clk_vec(4)
+ g_clk6_phase_shift => c_dp_clk6_phase, -- dp_phs_clk_vec(5)
+ g_clk1_divide_by => g_dp_phs_clk_divide_by,
+ g_clk2_divide_by => g_dp_phs_clk_divide_by,
+ g_clk3_divide_by => g_dp_phs_clk_divide_by,
+ g_clk4_divide_by => g_dp_phs_clk_divide_by,
+ g_clk5_divide_by => g_dp_phs_clk_divide_by,
+ g_clk6_divide_by => g_dp_phs_clk_divide_by
+ )
+ port map (
+ arst => dp_dis,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => dp_rst,
+ st_clk_vec => dp_phs_clk_vec -- PLL c6-c1
+ );
end generate;
no_pll: if g_dp_clk_use_pll = false and g_dp_clk_use_xo_pll = false generate
@@ -418,74 +418,74 @@ begin
end generate;
u_unb1_board_clk25_pll : entity work.unb1_board_clk25_pll
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk25 => i_xo_clk,
+ c0_clk20 => clk20M,
+ c1_clk40 => clk40M,
+ c2_clk50 => clk50M,
+ c3_clk125 => clk125M,
+ c4_clk200 => clk200M,
+ pll_locked => mm_locked_out
+ );
+ end generate;
+
+ u_unb1_board_node_ctrl : entity work.unb1_board_node_ctrl
generic map (
- g_technology => g_technology
+ g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk25 => i_xo_clk,
- c0_clk20 => clk20M,
- c1_clk40 => clk40M,
- c2_clk50 => clk50M,
- c3_clk125 => clk125M,
- c4_clk200 => clk200M,
- pll_locked => mm_locked_out
+ xo_clk => i_xo_clk,
+ xo_rst_n => i_xo_rst_n,
+ sys_clk => mm_clk,
+ sys_locked => mm_locked,
+ sys_rst => i_mm_rst,
+ cal_clk => '0',
+ cal_rst => OPEN,
+ st_clk => node_ctrl_dp_clk_in,
+ st_rst => node_ctrl_dp_rst_out,
+ wdi_in => pout_wdi,
+ wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ pulse_us => OPEN,
+ pulse_ms => mm_pulse_ms,
+ pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb1_board_node_ctrl : entity work.unb1_board_node_ctrl
- generic map (
- g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- xo_clk => i_xo_clk,
- xo_rst_n => i_xo_rst_n,
- sys_clk => mm_clk,
- sys_locked => mm_locked,
- sys_rst => i_mm_rst,
- cal_clk => '0',
- cal_rst => OPEN,
- st_clk => node_ctrl_dp_clk_in,
- st_rst => node_ctrl_dp_rst_out,
- wdi_in => pout_wdi,
- wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- pulse_us => OPEN,
- pulse_ms => mm_pulse_ms,
- pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-- System info
cs_sim <= is_true(g_sim);
u_mms_unb1_board_system_info : entity work.mms_unb1_board_system_info
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_use_phy => g_use_phy,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version,
- g_technology => g_technology
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_use_phy => g_use_phy,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
-- Red LED control
@@ -520,12 +520,12 @@ begin
led_toggle_green <= sel_a_b(g_design_name(1 to 8) /= "unb1_min", led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
-- WDI override
@@ -536,15 +536,15 @@ begin
WDI <= sel_a_b(g_use_phy.wdi, mm_wdi or temp_alarm or wdi_override, 'Z');
u_unb1_board_wdi_reg : entity work.unb1_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
-- Remote upgrade
@@ -554,15 +554,15 @@ begin
-- and reconfigure from that address.
gen_mms_remu : if c_use_flash = true generate -- enable on HW, disable to save simulation time when not used in tb
u_mms_remu : entity remu_lib.mms_remu
- port map (
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
end generate;
no_remu_in_sim : if c_use_flash = false generate
@@ -574,31 +574,31 @@ begin
-----------------------------------------------------------------------------
gen_mms_epcs : if c_use_flash = true generate -- enable on HW, disable to save simulation time when not used in tb
u_mms_epcs : entity epcs_lib.mms_epcs
- generic map (
- g_sim_flash_model => g_sim_flash_model,
- g_protect_addr_range => g_epcs_protect_addr_range
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_sim_flash_model => g_sim_flash_model,
+ g_protect_addr_range => g_epcs_protect_addr_range
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
end generate;
no_epcs_in_sim : if c_use_flash = false generate
@@ -612,45 +612,45 @@ begin
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => mms_ppsh_pps_sys
- );
+ generic map (
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => mms_ppsh_pps_sys
+ );
------------------------------------------------------------------------------
-- PPS delay
------------------------------------------------------------------------------
gen_mms_common_pulse_delay : if g_pps_delay_max > 0 generate
u_mms_common_pulse_delay : entity common_lib.mms_common_pulse_delay
- generic map (
- g_pulse_delay_max => g_pps_delay_max,
- g_register_out => true
- )
- port map (
- pulse_clk => dp_clk_in,
- pulse_rst => dp_rst_in,
- pulse_in => mms_ppsh_pps_sys,
- pulse_out => dp_pps,
-
- mm_clk => mm_clk,
- mm_rst => i_mm_rst,
- reg_mosi => reg_common_pulse_delay_mosi,
- reg_miso => reg_common_pulse_delay_miso
- );
+ generic map (
+ g_pulse_delay_max => g_pps_delay_max,
+ g_register_out => true
+ )
+ port map (
+ pulse_clk => dp_clk_in,
+ pulse_rst => dp_rst_in,
+ pulse_in => mms_ppsh_pps_sys,
+ pulse_out => dp_pps,
+
+ mm_clk => mm_clk,
+ mm_rst => i_mm_rst,
+ reg_mosi => reg_common_pulse_delay_mosi,
+ reg_miso => reg_common_pulse_delay_miso
+ );
end generate;
no_mms_common_pulse_delay : if g_pps_delay_max = 0 generate
@@ -664,28 +664,28 @@ begin
mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_ms; -- speed up in simulation
u_mms_unb1_board_sens : entity work.mms_unb1_board_sens
- generic map (
- g_sim => g_sim,
- g_clk_freq => g_mm_clk_freq,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_sens_mosi,
- reg_miso => reg_unb_sens_miso,
-
- -- i2c bus
- scl => sens_sc,
- sda => sens_sd,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_clk_freq => g_mm_clk_freq,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_sens_mosi,
+ reg_miso => reg_unb_sens_miso,
+
+ -- i2c bus
+ scl => sens_sc,
+ sda => sens_sd,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
-- Ethernet 1GbE
@@ -713,44 +713,44 @@ begin
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
u_mac : entity eth_lib.eth
- generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_sim => g_sim,
- g_sim_level => g_sim_level
- )
- port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => mm_clk, -- use mm_clk direct
- eth_clk => eth1g_tse_clk, -- use the dedicated 125 MHz tse_clock, independent of the mm_clk
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT,
- eth_rxp => ETH_SGIN,
-
- -- LED interface
- tse_led => eth1g_led
- );
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => mm_clk, -- use mm_clk direct
+ eth_clk => eth1g_tse_clk, -- use the dedicated 125 MHz tse_clock, independent of the mm_clk
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT,
+ eth_rxp => ETH_SGIN,
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
end generate;
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
index b6754497a9..a4d9f84fa3 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
@@ -23,10 +23,10 @@
-- Description: See unb1_board_sens.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_unb1_board_sens is
generic (
@@ -63,46 +63,46 @@ architecture str of mms_unb1_board_sens is
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
begin
u_unb1_board_sens_reg : entity work.unb1_board_sens_reg
- generic map (
- g_sens_nof_result => c_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_sens_nof_result => c_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers
- sens_err => sens_err, -- using same protocol list for both BN3 and all nodes implies that sens_err is only valid for BN3.
- sens_data => sens_data,
+ -- MM registers
+ sens_err => sens_err, -- using same protocol list for both BN3 and all nodes implies that sens_err is only valid for BN3.
+ sens_data => sens_data,
- -- Max temp threshold
- temp_high => temp_high
- );
+ -- Max temp threshold
+ temp_high => temp_high
+ );
u_unb1_board_sens : entity work.unb1_board_sens
- generic map (
- g_sim => g_sim,
- g_clk_freq => g_clk_freq,
- g_temp_high => g_temp_high,
- g_sens_nof_result => c_sens_nof_result
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
- start => mm_start,
- -- i2c bus
- scl => scl,
- sda => sda,
- -- read results
- sens_evt => OPEN,
- sens_err => sens_err,
- sens_data => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_clk_freq => g_clk_freq,
+ g_temp_high => g_temp_high,
+ g_sens_nof_result => c_sens_nof_result
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+ start => mm_start,
+ -- i2c bus
+ scl => scl,
+ sda => sda,
+ -- read results
+ sens_evt => OPEN,
+ sens_err => sens_err,
+ sens_data => sens_data
+ );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
index 3501660869..7be50357bb 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb1_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb1_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb1_board_system_info is
generic (
@@ -59,7 +59,7 @@ entity mms_unb1_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb1_board_system_info;
architecture str of mms_unb1_board_system_info is
@@ -69,68 +69,69 @@ architecture str of mms_unb1_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/";
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb1_board_system_info: entity work.unb1_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb1_board_system_info_reg: entity work.unb1_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_use_phy => g_use_phy,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_use_phy => g_use_phy,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
index f7ddc51006..64a33e34b0 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
@@ -123,13 +123,13 @@
-- advantage is that it
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity node_unb1_fn_terminal_db is
generic(
@@ -238,7 +238,7 @@ architecture str of node_unb1_fn_terminal_db is
signal rx_usr_siso_arr : t_dp_siso_arr(g_usr_nof_streams - 1 downto 0);
signal rx_usr_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Data buffer
-----------------------------------------------------------------------------
signal db_in_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
@@ -249,67 +249,67 @@ begin
-----------------------------------------------------------------------------
u_terminals_mesh : entity unb1_board_lib.unb1_board_terminals_mesh
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_node_type => e_fn,
- g_nof_bus => c_unb1_board_nof_bn, -- 4 to 4 nodes in mesh
- -- User
- g_usr_use_complex => true,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_block_len,
- g_usr_nof_streams => c_usr_nof_streams_per_bus,
- -- Phy
- g_phy_nof_serial => g_mesh_nof_serial,
- g_phy_gx_mbps => g_mesh_gx_mbps,
- g_phy_rx_fifo_size => c_phy_rx_fifo_size,
- g_phy_ena_reorder => g_mesh_ena_reorder,
- -- Tx
- g_use_tx => g_mesh_use_tx, -- optionally do support diag Tx
- g_tx_input_use_fifo => false, -- no user Tx
- -- Rx
- g_use_rx => true, -- user Rx must be TRUE for DB in FN,
- g_rx_output_use_fifo => true, -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_output_fifo_size => c_rx_output_fifo_size,
- g_rx_output_fifo_fill => c_rx_output_fifo_fill,
- g_rx_timeout_w => c_rx_timeout_w,
- -- Monitoring
- g_mon_select => g_mesh_mon_select,
- g_mon_nof_words => g_mesh_mon_nof_words,
- g_mon_use_sync => g_mesh_mon_use_sync
- )
- port map (
- chip_id => chip_id,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_sync => dp_pps,
- tr_clk => tr_mesh_clk,
- cal_clk => cal_clk,
-
- -- User interface (4 nodes)(4 input streams)
- rx_usr_siso_2arr => rx_usr_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- Rx (user Tx from FN to BN is unused)
-
- -- Mesh interface level (4 nodes)(4 lanes)
- -- . Serial (tr_nonbonded)
- tx_serial_2arr => tx_serial_2arr, -- Tx
- rx_serial_2arr => rx_serial_2arr, -- Rx
-
- -- MM Control
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
-
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_node_type => e_fn,
+ g_nof_bus => c_unb1_board_nof_bn, -- 4 to 4 nodes in mesh
+ -- User
+ g_usr_use_complex => true,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_block_len,
+ g_usr_nof_streams => c_usr_nof_streams_per_bus,
+ -- Phy
+ g_phy_nof_serial => g_mesh_nof_serial,
+ g_phy_gx_mbps => g_mesh_gx_mbps,
+ g_phy_rx_fifo_size => c_phy_rx_fifo_size,
+ g_phy_ena_reorder => g_mesh_ena_reorder,
+ -- Tx
+ g_use_tx => g_mesh_use_tx, -- optionally do support diag Tx
+ g_tx_input_use_fifo => false, -- no user Tx
+ -- Rx
+ g_use_rx => true, -- user Rx must be TRUE for DB in FN,
+ g_rx_output_use_fifo => true, -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_fifo_size => c_rx_output_fifo_size,
+ g_rx_output_fifo_fill => c_rx_output_fifo_fill,
+ g_rx_timeout_w => c_rx_timeout_w,
+ -- Monitoring
+ g_mon_select => g_mesh_mon_select,
+ g_mon_nof_words => g_mesh_mon_nof_words,
+ g_mon_use_sync => g_mesh_mon_use_sync
+ )
+ port map (
+ chip_id => chip_id,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_sync => dp_pps,
+ tr_clk => tr_mesh_clk,
+ cal_clk => cal_clk,
+
+ -- User interface (4 nodes)(4 input streams)
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- Rx (user Tx from FN to BN is unused)
+
+ -- Mesh interface level (4 nodes)(4 lanes)
+ -- . Serial (tr_nonbonded)
+ tx_serial_2arr => tx_serial_2arr, -- Tx
+ rx_serial_2arr => rx_serial_2arr, -- Rx
+
+ -- MM Control
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
+ );
---------------------------------------------------------------------------------------
-- Forward the received streams, rewire for single or multi UniBoard use
@@ -345,51 +345,51 @@ begin
gen_align : if g_use_bsn_align = true generate
u_bsn_align : entity dp_lib.dp_bsn_align
- generic map (
- g_block_size => g_usr_block_len,
- g_nof_input => g_usr_nof_streams,
- g_xoff_timeout => c_xoff_timeout,
- g_sop_timeout => c_sop_timeout,
- g_bsn_latency => c_burst_bsn_latency,
- g_bsn_request_pipeline => c_bsn_request_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sinks
- snk_out_arr => rx_usr_siso_arr,
- snk_in_arr => rx_usr_sosi_arr,
- -- ST source
- src_in_arr => dp_out_siso_arr,
- src_out_arr => db_in_sosi_arr,
- -- MM
- in_en_evt => '0', -- pulse '1' indicates that the in_en_arr user input enables have been updated
- in_en_arr => (others => '1') -- default all user inputs are enabled
- );
+ generic map (
+ g_block_size => g_usr_block_len,
+ g_nof_input => g_usr_nof_streams,
+ g_xoff_timeout => c_xoff_timeout,
+ g_sop_timeout => c_sop_timeout,
+ g_bsn_latency => c_burst_bsn_latency,
+ g_bsn_request_pipeline => c_bsn_request_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sinks
+ snk_out_arr => rx_usr_siso_arr,
+ snk_in_arr => rx_usr_sosi_arr,
+ -- ST source
+ src_in_arr => dp_out_siso_arr,
+ src_out_arr => db_in_sosi_arr,
+ -- MM
+ in_en_evt => '0', -- pulse '1' indicates that the in_en_arr user input enables have been updated
+ in_en_arr => (others => '1') -- default all user inputs are enabled
+ );
u_bsn_monitor_align : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- All streams are synchronous. Only monitor stream(0).
- g_cross_clock_domain => true,
- g_sync_timeout => g_mesh_sync_timeout,
- g_bsn_w => c_dp_stream_bsn_w,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_log_first_bsn => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => (others => c_dp_siso_rdy),
- in_sosi_arr => db_in_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- All streams are synchronous. Only monitor stream(0).
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_mesh_sync_timeout,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_log_first_bsn => true
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => (others => c_dp_siso_rdy),
+ in_sosi_arr => db_in_sosi_arr(0 downto 0)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -402,27 +402,27 @@ begin
gen_data_buf : if g_use_data_buf = true generate
u_data_buf : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => g_usr_nof_streams,
- g_data_w => g_usr_data_w,
- g_buf_nof_data => 1024,
- g_buf_use_sync => true
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- -- ST interface
- in_sync => db_in_sosi_arr(0).sync,
- in_sosi_arr => db_in_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_usr_nof_streams,
+ g_data_w => g_usr_data_w,
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => true
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => db_in_sosi_arr(0).sync,
+ in_sosi_arr => db_in_sosi_arr
+ );
end generate;
-----------------------------------------------------------------------------
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
index b3e7726427..49ccda5ea0 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_back_io is
generic (
@@ -60,4 +60,4 @@ begin
rx_serial_2arr(3)(I) <= BN_BI_3_RX(I);
end generate;
-end;
+ end;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
index 8f32540b83..8624fee3d2 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
@@ -53,11 +53,11 @@
-- . See unb1_board_back_model_sl.vhd for the Apertif backplane model
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_back_reorder is
port (
@@ -96,69 +96,69 @@ begin
-- Map the usr busses for the other UniBoards to the phy busses 2:0
case TO_UINT(bck_id) is
when 0 =>
- -- UniBoard 0 connects to UniBoards 3,2,1 via phy busses 0,2,1
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
- tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
- rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
-
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
- tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
- rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
-
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
- tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
- rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
+ -- UniBoard 0 connects to UniBoards 3,2,1 via phy busses 0,2,1
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
+
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
+
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
when 1 =>
- -- UniBoard 1 connects to UniBoards 3,2,0 via phy busses 0,1,2
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
- tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
- rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
-
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(2); -- to unb 2
- tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1); -- from unb 2
- rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(2);
-
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
- tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
- rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
+ -- UniBoard 1 connects to UniBoards 3,2,0 via phy busses 0,1,2
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
+
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(2); -- to unb 2
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1); -- from unb 2
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(2);
+
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
when 2 =>
- -- UniBoard 2 connects to UniBoards 3,1,0 via phy busses 1,0,2
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
- tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
- rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
-
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(1); -- to unb 1
- tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(0); -- from unb 1
- rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(1);
-
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(3); -- to unb 3
- tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(1); -- from unb 3
- rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(3);
+ -- UniBoard 2 connects to UniBoards 3,1,0 via phy busses 1,0,2
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
+
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(1); -- to unb 1
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(0); -- from unb 1
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(1);
+
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(3); -- to unb 3
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(1); -- from unb 3
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(3);
when 3 =>
- -- UniBoard 3 connects to UniBoards 2,1,0 via phy busses 2,1,0
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(0); -- to unb 0
- tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(0); -- from unb 0
- rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(0);
-
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
- tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
- rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
-
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
- tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
- rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
+ -- UniBoard 3 connects to UniBoards 2,1,0 via phy busses 2,1,0
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(0); -- to unb 0
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(0); -- from unb 0
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(0);
+
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
+
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
when others => null;
end case;
end process;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
index 6aaadd11ea..f0c0dccc40 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
@@ -36,11 +36,11 @@
-- are ignored.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_back_select is
port (
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
index 1ee7f13647..9f7184e2ea 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
@@ -26,13 +26,13 @@
-- except for the SOSI entity I/O types and the monitor outputs.
library IEEE, common_lib, dp_lib, uth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_packet_pkg.all;
-use work.unb1_board_pkg.all;
-use uth_lib.uth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_packet_pkg.all;
+ use work.unb1_board_pkg.all;
+ use uth_lib.uth_pkg.all;
entity unb1_board_back_uth_terminals_bidir is
generic (
@@ -83,51 +83,51 @@ architecture str of unb1_board_back_uth_terminals_bidir is
begin
gen_bus : for I in 0 to c_unb1_board_tr_back.nof_bus - 1 generate
u_uth_terminal_bidir : entity uth_lib.uth_terminal_bidir
- generic map (
- -- User
- g_usr_nof_streams => g_usr_nof_streams,
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- -- DP/UTH packet
- g_packet_data_w => g_packet_data_w,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- -- Tx
- g_use_tx => g_use_tx,
- g_tx_mux_mode => c_tx_mux_mode,
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- g_tx_input_fifo_size => g_tx_input_fifo_size,
- g_tx_input_fifo_fill => g_tx_input_fifo_fill,
- -- Rx
- g_use_rx => g_use_rx,
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_output_fifo_size => g_rx_output_fifo_size,
- g_rx_output_fifo_fill => g_rx_output_fifo_fill,
- g_rx_timeout_w => g_rx_timeout_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => g_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_mux_mode => c_tx_mux_mode,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- usr side interface
- tx_dp_sosi_arr => tx_dp_sosi_2arr(I),
- tx_dp_siso_arr => tx_dp_siso_2arr(I),
+ -- usr side interface
+ tx_dp_sosi_arr => tx_dp_sosi_2arr(I),
+ tx_dp_siso_arr => tx_dp_siso_2arr(I),
- rx_dp_sosi_arr => rx_dp_sosi_2arr(I),
- rx_dp_siso_arr => rx_dp_siso_2arr(I),
+ rx_dp_sosi_arr => rx_dp_sosi_2arr(I),
+ rx_dp_siso_arr => rx_dp_siso_2arr(I),
- -- phy side interface
- tx_uth_sosi_arr => tx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- tx_uth_siso_arr => tx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ -- phy side interface
+ tx_uth_sosi_arr => tx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ tx_uth_siso_arr => tx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
- rx_uth_sosi_arr => rx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- rx_uth_siso_arr => rx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ rx_uth_sosi_arr => rx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ rx_uth_siso_arr => rx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
- -- monitoring interface
- rx_mon_pkt_sosi_arr => OPEN,
- rx_mon_dist_sosi_arr => open
- );
+ -- monitoring interface
+ rx_mon_pkt_sosi_arr => OPEN,
+ rx_mon_dist_sosi_arr => open
+ );
end generate;
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
index 54d62c3a5d..aa03eb398c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
@@ -21,74 +21,74 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Purpose: PLL for UniBoard node CLK input @ 200 MHz
--- Description:
--- . The PLL runs in normal mode using c0 to compensate for the internal clock
--- network delay, so that c0 = st_clk200 is aligned to the input clk200.
--- . The assumption is that default the streaming DSP will run on the 200 MHz
--- clock from the CLK input via c1 = st_clk200p.
--- . The PLL normal mode operation compensates for internal clock network
--- delays of c0. This compensations aligns c0 to inclk0. With
--- tb_unb1_board_clk200_pll.vhd it appears that the phase setting for c0 does
--- not influence the compensation. Therefore it is llso possible to use
--- g_clk200_phase_shift /= 0 and touse c0 as processing clock instead of c1.
--- . The phase offset of c0 and c1 in the clk200_pll MegaWizard component
--- can be set in steps of 11.25 degrees (and even finer):
--- g_clk200_phase_shift (for c0)
--- phase [degrees] g_clk200p_phase_shift (for c1)
--- 0 "0"
--- 11.25 "156"
--- 22.5 "313"
--- 33.75 "469"
--- 45 "625"
--- 56.25 "781"
--- 67.5 "938"
--- 78.75 "1094"
--- 90 "1250"
--- 101.25 "1406" = 1250+ 156
--- 112.5 "1563" = 1250+ 313
--- 123.75 "1719" = 1250+ 469
--- 135 "1875" = 1250+ 625
--- 146.25 "2031" = 1250+ 781
--- 157.5 "2188" = 1250+ 938
--- 168.75 "2344" = 1250+1094
--- 180 "2500" = 1250+1250
--- 191.25 "2656" = 2500+ 156
--- 202.5 "2813" = 2500+ 313
--- 213.75 "2969" = 2500+ 469
--- 225 "3125" = 2500+ 625
--- 236.25 "3281" = 2500+ 781
--- 247.5 "3438" = 2500+ 938
--- 258.75 "3594" = 2500+1094
--- 270 "3750" = 2500+1250
--- 281.25 "3906" = 3750+ 156
--- 292.5 "4063" = 3750+ 313
--- 303.75 "4219" = 3750+ 469
--- 315 "4375" = 3750+ 625
--- 326.25 "4531" = 3750+ 781
--- 337.5 "4688" = 3750+ 938
--- 348.75 "4844" = 3750+1094
--- 360 "5000" = 3750+1250
--- . With a phase offset of 22.5 degrees the c1 = clk200p is offset by a 1/16
--- period of 200 MHz, so 1/8 period of the 400 MHz DCLK from ADU and 1/4
--- period of the 800 MHz sample SCLK of ADU. This phase offset can be used
--- to achieve stable timing between the DCLK and the clk200p domain.
--- . Some DSP may also be possible at 400 MHz via st_clk400. Note that this
--- 400 MHz can also be used at places where only a little more than 200 MHz
--- would be needed, e.g. to create packets at full data rate.
--- Therefore it is not necessary to create yet another st clock frequency.
--- This to also avoid the EMI or RFI that a non integer factor of 200 MHz
--- like e.g. 250 MHz would cause.
--- . At 400 MHz ADC samples can be clocked in at 800 MSps using DDIO. At 800
--- MSps the sample period is 1250 ns. Input timing can be tuned via fixed
--- pad input delays and/or by using another phase of the PLL output clock.
--- Remarks:
--- . If necessary more 400 M clock phase could be made available, via g_sel.
---
+ -- Purpose: PLL for UniBoard node CLK input @ 200 MHz
+ -- Description:
+ -- . The PLL runs in normal mode using c0 to compensate for the internal clock
+ -- network delay, so that c0 = st_clk200 is aligned to the input clk200.
+ -- . The assumption is that default the streaming DSP will run on the 200 MHz
+ -- clock from the CLK input via c1 = st_clk200p.
+ -- . The PLL normal mode operation compensates for internal clock network
+ -- delays of c0. This compensations aligns c0 to inclk0. With
+ -- tb_unb1_board_clk200_pll.vhd it appears that the phase setting for c0 does
+ -- not influence the compensation. Therefore it is llso possible to use
+ -- g_clk200_phase_shift /= 0 and touse c0 as processing clock instead of c1.
+ -- . The phase offset of c0 and c1 in the clk200_pll MegaWizard component
+ -- can be set in steps of 11.25 degrees (and even finer):
+ -- g_clk200_phase_shift (for c0)
+ -- phase [degrees] g_clk200p_phase_shift (for c1)
+ -- 0 "0"
+ -- 11.25 "156"
+ -- 22.5 "313"
+ -- 33.75 "469"
+ -- 45 "625"
+ -- 56.25 "781"
+ -- 67.5 "938"
+ -- 78.75 "1094"
+ -- 90 "1250"
+ -- 101.25 "1406" = 1250+ 156
+ -- 112.5 "1563" = 1250+ 313
+ -- 123.75 "1719" = 1250+ 469
+ -- 135 "1875" = 1250+ 625
+ -- 146.25 "2031" = 1250+ 781
+ -- 157.5 "2188" = 1250+ 938
+ -- 168.75 "2344" = 1250+1094
+ -- 180 "2500" = 1250+1250
+ -- 191.25 "2656" = 2500+ 156
+ -- 202.5 "2813" = 2500+ 313
+ -- 213.75 "2969" = 2500+ 469
+ -- 225 "3125" = 2500+ 625
+ -- 236.25 "3281" = 2500+ 781
+ -- 247.5 "3438" = 2500+ 938
+ -- 258.75 "3594" = 2500+1094
+ -- 270 "3750" = 2500+1250
+ -- 281.25 "3906" = 3750+ 156
+ -- 292.5 "4063" = 3750+ 313
+ -- 303.75 "4219" = 3750+ 469
+ -- 315 "4375" = 3750+ 625
+ -- 326.25 "4531" = 3750+ 781
+ -- 337.5 "4688" = 3750+ 938
+ -- 348.75 "4844" = 3750+1094
+ -- 360 "5000" = 3750+1250
+ -- . With a phase offset of 22.5 degrees the c1 = clk200p is offset by a 1/16
+ -- period of 200 MHz, so 1/8 period of the 400 MHz DCLK from ADU and 1/4
+ -- period of the 800 MHz sample SCLK of ADU. This phase offset can be used
+ -- to achieve stable timing between the DCLK and the clk200p domain.
+ -- . Some DSP may also be possible at 400 MHz via st_clk400. Note that this
+ -- 400 MHz can also be used at places where only a little more than 200 MHz
+ -- would be needed, e.g. to create packets at full data rate.
+ -- Therefore it is not necessary to create yet another st clock frequency.
+ -- This to also avoid the EMI or RFI that a non integer factor of 200 MHz
+ -- like e.g. 250 MHz would cause.
+ -- . At 400 MHz ADC samples can be clocked in at 800 MSps using DDIO. At 800
+ -- MSps the sample period is 1250 ns. Input timing can be tuned via fixed
+ -- pad input delays and/or by using another phase of the PLL output clock.
+ -- Remarks:
+ -- . If necessary more 400 M clock phase could be made available, via g_sel.
+ --
entity unb1_board_clk200_pll is
generic (
@@ -108,9 +108,9 @@ entity unb1_board_clk200_pll is
g_clk3_phase_shift : string := "313"; -- = 022.5 = st_clk_vec[3]
g_clk4_phase_shift : string := "469"; -- = 033.75 = st_clk_vec[4]
g_clk5_phase_shift : string := "625"; -- = 045 = st_clk_vec[5]
- -- "781"; -- = 056.25
+ -- "781"; -- = 056.25
g_clk6_phase_shift : string := "938"; -- = 067.5 = st_clk_vec[6]
- -- "1094"; -- = 078.75
+ -- "1094"; -- = 078.75
g_clk1_divide_by : natural := 32; -- = clk 200/32 MHz
g_clk2_divide_by : natural := 32; -- = clk 200/32 MHz
g_clk3_divide_by : natural := 32; -- = clk 200/32 MHz
@@ -163,96 +163,96 @@ begin
gen_0 : if g_sel = 0 generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_1 : if g_sel = 1 generate
i_st_clk200p <= i_st_clk_vec(0);
u_st_pll_p6 : entity tech_pll_lib.tech_pll_clk200_p6
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk0_phase_shift,
- g_clk1_used => c_clk1_used,
- g_clk2_used => c_clk2_used,
- g_clk3_used => c_clk3_used,
- g_clk4_used => c_clk4_used,
- g_clk5_used => c_clk5_used,
- g_clk6_used => c_clk6_used,
- g_clk1_divide_by => g_clk1_divide_by,
- g_clk2_divide_by => g_clk2_divide_by,
- g_clk3_divide_by => g_clk3_divide_by,
- g_clk4_divide_by => g_clk4_divide_by,
- g_clk5_divide_by => g_clk5_divide_by,
- g_clk6_divide_by => g_clk6_divide_by,
- g_clk1_phase_shift => g_clk1_phase_shift,
- g_clk2_phase_shift => g_clk2_phase_shift,
- g_clk3_phase_shift => g_clk3_phase_shift,
- g_clk4_phase_shift => g_clk4_phase_shift,
- g_clk5_phase_shift => g_clk5_phase_shift,
- g_clk6_phase_shift => g_clk6_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200,
- c0 => i_st_clk200,
- c1 => i_st_clk_vec(0),
- c2 => i_st_clk_vec(1),
- c3 => i_st_clk_vec(2),
- c4 => i_st_clk_vec(3),
- c5 => i_st_clk_vec(4),
- c6 => i_st_clk_vec(5),
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk0_phase_shift,
+ g_clk1_used => c_clk1_used,
+ g_clk2_used => c_clk2_used,
+ g_clk3_used => c_clk3_used,
+ g_clk4_used => c_clk4_used,
+ g_clk5_used => c_clk5_used,
+ g_clk6_used => c_clk6_used,
+ g_clk1_divide_by => g_clk1_divide_by,
+ g_clk2_divide_by => g_clk2_divide_by,
+ g_clk3_divide_by => g_clk3_divide_by,
+ g_clk4_divide_by => g_clk4_divide_by,
+ g_clk5_divide_by => g_clk5_divide_by,
+ g_clk6_divide_by => g_clk6_divide_by,
+ g_clk1_phase_shift => g_clk1_phase_shift,
+ g_clk2_phase_shift => g_clk2_phase_shift,
+ g_clk3_phase_shift => g_clk3_phase_shift,
+ g_clk4_phase_shift => g_clk4_phase_shift,
+ g_clk5_phase_shift => g_clk5_phase_shift,
+ g_clk6_phase_shift => g_clk6_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200,
+ c0 => i_st_clk200,
+ c1 => i_st_clk_vec(0),
+ c2 => i_st_clk_vec(1),
+ c3 => i_st_clk_vec(2),
+ c4 => i_st_clk_vec(3),
+ c5 => i_st_clk_vec(4),
+ c6 => i_st_clk_vec(5),
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end stratix4;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
index f5684a4c5c..e575366f10 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
@@ -21,17 +21,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Purpose: PLL for UniBoard node CLK input @ 25 MHz
--- Description:
--- c0 = 20 MHz
--- c1 = 40 MHz
--- c2 = 50 MHz
--- c3 = 125 MHz
---
+ -- Purpose: PLL for UniBoard node CLK input @ 25 MHz
+ -- Description:
+ -- c0 = 20 MHz
+ -- c1 = 40 MHz
+ -- c2 = 50 MHz
+ -- c3 = 125 MHz
+ --
entity unb1_board_clk25_pll is
generic (
@@ -53,17 +53,17 @@ end unb1_board_clk25_pll;
architecture stratixiv of unb1_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk40,
- c2 => c2_clk50,
- c3 => c3_clk125,
- c4 => c4_clk200,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk40,
+ c2 => c2_clk50,
+ c3 => c3_clk125,
+ c4 => c4_clk200,
+ locked => pll_locked
+ );
end stratixiv;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
index 4498f945ae..b6424aad1b 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose:
--- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
--- reset_n).
--- 2) sys_rst released when the sys_clk PLL from the SOPC system has locked,
--- can be used as a system reset for the sys_clk domain.
+ -- Purpose:
+ -- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
+ -- reset_n).
+ -- 2) sys_rst released when the sys_clk PLL from the SOPC system has locked,
+ -- can be used as a system reset for the sys_clk domain.
entity unb1_board_clk_rst is
port (
@@ -55,27 +55,27 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
index ce43144b74..463c237a0c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_front_io is
generic (
@@ -78,50 +78,50 @@ begin
-- MDIO buffers
gen_iobuf_0 : if g_nof_xaui > 0 generate
u_iobuf_0 : entity common_lib.common_inout
- port map (
- dat_inout => SI_FN_0_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
- dat_in_from_line => mdio_mdat_in_arr(0),
- dat_out_to_line => '0',
- dat_out_en => mdio_mdat_oen_arr(0)
- );
+ port map (
+ dat_inout => SI_FN_0_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(0),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(0)
+ );
SI_FN_0_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(0);
end generate;
gen_iobuf_1 : if g_nof_xaui > 1 generate
u_iobuf_1 : entity common_lib.common_inout
- port map (
- dat_inout => SI_FN_1_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
- dat_in_from_line => mdio_mdat_in_arr(1),
- dat_out_to_line => '0',
- dat_out_en => mdio_mdat_oen_arr(1)
- );
+ port map (
+ dat_inout => SI_FN_1_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(1),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(1)
+ );
SI_FN_1_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(1);
end generate;
gen_iobuf_2 : if g_nof_xaui > 2 generate
u_iobuf_2 : entity common_lib.common_inout
- port map (
- dat_inout => SI_FN_2_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
- dat_in_from_line => mdio_mdat_in_arr(2),
- dat_out_to_line => '0',
- dat_out_en => mdio_mdat_oen_arr(2)
- );
+ port map (
+ dat_inout => SI_FN_2_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(2),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(2)
+ );
SI_FN_2_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(2);
end generate;
gen_iobuf_3 : if g_nof_xaui > 3 generate
u_iobuf_3 : entity common_lib.common_inout
- port map (
- dat_inout => SI_FN_3_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
- dat_in_from_line => mdio_mdat_in_arr(3),
- dat_out_to_line => '0',
- dat_out_en => mdio_mdat_oen_arr(3)
- );
+ port map (
+ dat_inout => SI_FN_3_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(3),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(3)
+ );
SI_FN_3_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(3);
end generate;
-end;
+ end;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
index f16b3b3714..ecf3e1a2f7 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_io is
generic (
@@ -58,4 +58,4 @@ begin
rx_serial_2arr(3)(I) <= FN_BN_3_RX(I);
end generate;
-end;
+ end;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
index 28c28e6f37..f8beb5a23c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
@@ -133,11 +133,11 @@
-- unb1_board_mesh_model_sl.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_reorder_bidir is
generic (
@@ -166,30 +166,30 @@ end unb1_board_mesh_reorder_bidir;
architecture str of unb1_board_mesh_reorder_bidir is
begin
u_tx : entity work.unb1_board_mesh_reorder_tx
- generic map (
- g_node_type => g_node_type,
- g_reorder => g_reorder
- )
- port map (
- chip_id => chip_id,
- clk => tx_clk,
- tx_usr_sosi_2arr => tx_usr_sosi_2arr,
- rx_usr_siso_2arr => rx_usr_siso_2arr,
- tx_phy_sosi_2arr => tx_phy_sosi_2arr,
- rx_phy_siso_2arr => rx_phy_siso_2arr
- );
+ generic map (
+ g_node_type => g_node_type,
+ g_reorder => g_reorder
+ )
+ port map (
+ chip_id => chip_id,
+ clk => tx_clk,
+ tx_usr_sosi_2arr => tx_usr_sosi_2arr,
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
+ tx_phy_sosi_2arr => tx_phy_sosi_2arr,
+ rx_phy_siso_2arr => rx_phy_siso_2arr
+ );
u_rx : entity work.unb1_board_mesh_reorder_rx
- generic map (
- g_node_type => g_node_type,
- g_reorder => g_reorder
- )
- port map (
- chip_id => chip_id,
- clk => rx_clk,
- rx_phy_sosi_2arr => rx_phy_sosi_2arr,
- tx_phy_siso_2arr => tx_phy_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr,
- tx_usr_siso_2arr => tx_usr_siso_2arr
- );
+ generic map (
+ g_node_type => g_node_type,
+ g_reorder => g_reorder
+ )
+ port map (
+ chip_id => chip_id,
+ clk => rx_clk,
+ rx_phy_sosi_2arr => rx_phy_sosi_2arr,
+ tx_phy_siso_2arr => tx_phy_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr,
+ tx_usr_siso_2arr => tx_usr_siso_2arr
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
index 71b2ca8114..4dd350e609 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
@@ -31,11 +31,11 @@
-- . Indexing for *_2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_reorder_rx is
generic (
@@ -91,8 +91,8 @@ begin
tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(0);
tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(1);
when 4 |
- 5 => -- this is BN0
- -- or BN1, connect phy bus 0,1,2,3 to usr bus 3,2,1,0
+ 5 => -- this is BN0
+ -- or BN1, connect phy bus 0,1,2,3 to usr bus 3,2,1,0
-- sosi
rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0);
rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
index 7fe1309d41..ba44d1f768 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
@@ -31,11 +31,11 @@
-- . Indexing for *_2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_reorder_tx is
generic (
@@ -59,19 +59,19 @@ begin
-- Register the chip_id from FPGA pins to ease timing closure.
-- . Alternatively these registers may better be removed and pin input chip_id[] set as false path for timing closure
u_chip_id : entity common_lib.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => c_meta_delay_len,
- g_reset_value => 0,
- g_in_dat_w => chip_id'LENGTH,
- g_out_dat_w => chip_id'length
- )
- port map (
- rst => '0',
- clk => clk,
- in_dat => chip_id,
- out_dat => chip_id_reg
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => c_meta_delay_len,
+ g_reset_value => 0,
+ g_in_dat_w => chip_id'LENGTH,
+ g_out_dat_w => chip_id'length
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ in_dat => chip_id,
+ out_dat => chip_id_reg
+ );
-- force chip_id(2) to '0' or '1' to reduce the case options in p_comb if the design will run only on a FN or only on a BN
chip_id_i <= func_unb1_board_chip_id(chip_id_reg, g_node_type);
@@ -109,8 +109,8 @@ begin
rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(0);
rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(1);
when 4 |
- 5 => -- this is BN0
- -- or BN1, connect usr bus 0,1,2,3 to phy bus 3,2,1,0
+ 5 => -- this is BN0
+ -- or BN1, connect usr bus 0,1,2,3 to phy bus 3,2,1,0
-- sosi
tx_phy_sosi_2arr(3) <= tx_usr_sosi_2arr(0);
tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(1);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
index a4259a7ade..b96d31d374 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
@@ -26,13 +26,13 @@
-- except for the SOSI entity I/O types and the monitor outputs.
library IEEE, common_lib, dp_lib, uth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_packet_pkg.all;
-use work.unb1_board_pkg.all;
-use uth_lib.uth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_packet_pkg.all;
+ use work.unb1_board_pkg.all;
+ use uth_lib.uth_pkg.all;
entity unb1_board_mesh_uth_terminals_bidir is
generic (
@@ -90,54 +90,54 @@ architecture str of unb1_board_mesh_uth_terminals_bidir is
begin
gen_uth_terminal_bidir : for I in 0 to c_unb1_board_tr_mesh.nof_bus - 1 generate
u_uth_terminal_bidir : entity uth_lib.uth_terminal_bidir
- generic map (
- -- User
- g_usr_nof_streams => g_usr_nof_streams,
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- -- DP/UTH packet
- g_packet_data_w => g_packet_data_w,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- -- Tx
- g_use_tx => g_use_tx,
- g_tx_mux_mode => c_tx_mux_mode,
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- g_tx_input_fifo_size => g_tx_input_fifo_size,
- g_tx_input_fifo_fill => g_tx_input_fifo_fill,
- -- Rx
- g_use_rx => g_use_rx,
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_output_fifo_size => g_rx_output_fifo_size,
- g_rx_output_fifo_fill => g_rx_output_fifo_fill,
- g_rx_timeout_w => g_rx_timeout_w,
- -- UTH
- g_uth_len_max => g_uth_len_max,
- g_uth_typ_ofs => g_uth_typ_ofs
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => g_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_mux_mode => c_tx_mux_mode,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w,
+ -- UTH
+ g_uth_len_max => g_uth_len_max,
+ g_uth_typ_ofs => g_uth_typ_ofs
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- usr side interface
- tx_dp_sosi_arr => tx_dp_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0),
- tx_dp_siso_arr => tx_dp_siso_2arr(I)(g_usr_nof_streams - 1 downto 0),
+ -- usr side interface
+ tx_dp_sosi_arr => tx_dp_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0),
+ tx_dp_siso_arr => tx_dp_siso_2arr(I)(g_usr_nof_streams - 1 downto 0),
- rx_dp_sosi_arr => rx_dp_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0),
- rx_dp_siso_arr => rx_dp_siso_2arr(I)(g_usr_nof_streams - 1 downto 0),
+ rx_dp_sosi_arr => rx_dp_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0),
+ rx_dp_siso_arr => rx_dp_siso_2arr(I)(g_usr_nof_streams - 1 downto 0),
- -- phy side interface
- tx_uth_sosi_arr => tx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- tx_uth_siso_arr => tx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ -- phy side interface
+ tx_uth_sosi_arr => tx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ tx_uth_siso_arr => tx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
- rx_uth_sosi_arr => rx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- rx_uth_siso_arr => rx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ rx_uth_sosi_arr => rx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ rx_uth_siso_arr => rx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
- -- monitoring interface
- rx_mon_pkt_sosi_arr => rx_mon_pkt_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- rx_mon_dist_sosi_arr => rx_mon_dist_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0)
- );
+ -- monitoring interface
+ rx_mon_pkt_sosi_arr => rx_mon_pkt_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ rx_mon_dist_sosi_arr => rx_mon_dist_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
index d5644e7de8..bd045a83a9 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose:
--- Provide the basic node control along with an SOPC Builder system:
--- . sys_rst for sys_clk
--- . pulse every 1 us, 1 ms and 1 s
--- . extend WDI to avoid watchdog reset during SW reload
+ -- Purpose:
+ -- Provide the basic node control along with an SOPC Builder system:
+ -- . sys_rst for sys_clk
+ -- . pulse every 1 us, 1 ms and 1 s
+ -- . extend WDI to avoid watchdog reset during SW reload
entity unb1_board_node_ctrl is
generic (
@@ -66,59 +66,59 @@ begin
pulse_ms <= i_pulse_ms;
u_unb1_board_clk_rst : entity work.unb1_board_clk_rst
- port map (
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- sys_clk => sys_clk,
- sys_locked => sys_locked,
- sys_rst => i_sys_rst -- release reset some clock cycles after sys_locked went high
- );
+ port map (
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ sys_clk => sys_clk,
+ sys_locked => sys_locked,
+ sys_rst => i_sys_rst -- release reset some clock cycles after sys_locked went high
+ );
u_common_areset_cal : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
- clk => cal_clk,
- out_rst => cal_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
+ clk => cal_clk,
+ out_rst => cal_rst
+ );
u_common_areset_st : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
- clk => st_clk,
- out_rst => st_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
+ clk => st_clk,
+ out_rst => st_rst
+ );
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_sys_rst,
- clk => sys_clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_sys_rst,
+ clk => sys_clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => pulse_s
+ );
u_unb1_board_wdi_extend : entity work.unb1_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_sys_rst,
- clk => sys_clk,
- pulse_ms => i_pulse_ms,
- wdi_in => wdi_in,
- wdi_out => wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_sys_rst,
+ clk => sys_clk,
+ pulse_ms => i_pulse_ms,
+ wdi_in => wdi_in,
+ wdi_out => wdi_out
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
index d524e5a623..a8a469be7c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb1_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
@@ -74,10 +74,10 @@ package unb1_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
index 180b535b22..f23468a6e5 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb1_board_pkg is
-- UniBoard
@@ -196,7 +196,7 @@ package unb1_board_pkg is
use_lvds_clk_rst : boolean; -- = FALSE; -- When TRUE then support reset pulse to ADU to align the lvds_clk to the dp_clk, else no support
lvds_clk_phase : natural; -- = 0; -- Use PLL phase 0 for center aligned. Only for no DPA
nof_clocks : natural; -- = 2; -- 1 --> Use ADC BI clock D or dp_clk and 32 bit port ABCD
- -- 2 --> Use ADC BI clock A, D and 16 bit ports AB, CD
+ -- 2 --> Use ADC BI clock A, D and 16 bit ports AB, CD
lvds_deser_factor : natural; -- = 2; -- The ADC sampled data comes in with a DDR lvds_clk, so lvds_data_rate / 2
dp_deser_factor : natural; -- = 4; -- The Data Path clock dp_clk frequency is 200 MHz, so lvds_data_rate / 4
end record;
@@ -257,7 +257,7 @@ package unb1_board_pkg is
type t_c_unb1_board_system_info is record
version : natural; -- UniBoard board HW version (2 bit value)
id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
+ -- Derived ID info:
bck_id : natural; -- = id[7:3], ID part from back plane
chip_id : natural; -- = id[2:0], ID part from UniBoard
is_bn : natural; -- = id[2], 0 for Front Node, 1 for Back Node
@@ -265,11 +265,13 @@ package unb1_board_pkg is
is_bn3 : natural; -- 1 for Back Node 3, else 0.
end record;
- function func_unb1_board_system_info(VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0)) return t_c_unb1_board_system_info;
+ function func_unb1_board_system_info(
+ VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0)) return t_c_unb1_board_system_info;
- function func_unb1_board_chip_id(chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
- node_type : in t_e_unb1_board_node) return std_logic_vector;
+ function func_unb1_board_chip_id(
+ chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
+ node_type : in t_e_unb1_board_node) return std_logic_vector;
-- Connect: out_2arr = in_2arr of different types
function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr;
@@ -290,8 +292,9 @@ package unb1_board_pkg is
end unb1_board_pkg;
package body unb1_board_pkg is
- function func_unb1_board_system_info(VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0)) return t_c_unb1_board_system_info is
+ function func_unb1_board_system_info(
+ VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0)) return t_c_unb1_board_system_info is
variable v_system_info : t_c_unb1_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
@@ -304,8 +307,9 @@ package body unb1_board_pkg is
return v_system_info;
end;
- function func_unb1_board_chip_id(chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
- node_type : in t_e_unb1_board_node) return std_logic_vector is
+ function func_unb1_board_chip_id(
+ chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
+ node_type : in t_e_unb1_board_node) return std_logic_vector is
variable v_chip_id : std_logic_vector(chip_id'range); -- [2:0]
begin
v_chip_id := chip_id; -- default for design that can run on either FN or BN
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
index ac56d4d4b2..002297fbc2 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use i2c_lib.i2c_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use i2c_lib.i2c_pkg.all;
entity unb1_board_sens is
generic (
@@ -49,7 +49,7 @@ architecture str of unb1_board_sens is
-- I2C clock rate settings
constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
constant c_sens_comma_w : natural := 0; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
- -- 0 = no comma time
+ -- 0 = no comma time
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
@@ -62,43 +62,43 @@ architecture str of unb1_board_sens is
signal smbus_out_end : std_logic;
begin
u_unb1_board_sens_ctrl : entity work.unb1_board_sens_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
u_i2c_smbus : entity i2c_lib.i2c_smbus
- generic map (
- g_i2c_phy => c_sens_phy
- )
- port map (
- gs_sim => g_sim,
- clk => clk,
- rst => rst,
- in_dat => smbus_in_dat,
- in_req => smbus_in_val,
- out_dat => smbus_out_dat,
- out_val => smbus_out_val,
- out_err => smbus_out_err,
- out_ack => smbus_out_ack,
- st_end => smbus_out_end,
- scl => scl,
- sda => sda
- );
-end architecture;
+ generic map (
+ g_i2c_phy => c_sens_phy
+ )
+ port map (
+ gs_sim => g_sim,
+ clk => clk,
+ rst => rst,
+ in_dat => smbus_in_dat,
+ in_req => smbus_in_val,
+ out_dat => smbus_out_dat,
+ out_val => smbus_out_val,
+ out_err => smbus_out_err,
+ out_ack => smbus_out_ack,
+ st_end => smbus_out_end,
+ scl => scl,
+ sda => sda
+ );
+ end architecture;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
index a9747754f1..595dfb9b17 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use common_lib.common_pkg.all;
entity unb1_board_sens_ctrl is
generic (
@@ -69,7 +69,7 @@ architecture rtl of unb1_board_sens_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
+ ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
constant c_seq_len : natural := c_SEQ'length - 1; -- upto SMBUS_C_END, the SMBUS_C_NOP is dummy to allow sufficient seq_cnt range
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
index 43e27b565f..221d02c39f 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
@@ -60,10 +60,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb1_board_sens_reg is
generic (
@@ -92,13 +92,14 @@ end unb1_board_sens_reg;
architecture rtl of unb1_board_sens_reg is
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
- -- +1 to fit sens_err in the last address
+ -- +1 to fit sens_err in the last address
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_mm_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_mm_nof_dat),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_mm_nof_dat,
+ init_sl => '0');
signal i_temp_high : std_logic_vector(6 downto 0);
begin
@@ -130,14 +131,14 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
if vA = g_sens_nof_result + 1 then
- -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
- -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
- if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
- i_temp_high <= sla_in.wrdata(6 downto 0);
- end if;
+ -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
+ -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
+ if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
+ i_temp_high <= sla_in.wrdata(6 downto 0);
+ end if;
end if;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
index 06b60254c0..8b21b3da69 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
@@ -21,14 +21,14 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb1_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb1_board_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Keep the UniBoard system info knowledge in this HDL entity and in the
--- corresponding software functions in unb_common.c,h. This avoids having to
--- define named constants for indexing the fields in the info word.
+ -- Keep the UniBoard system info knowledge in this HDL entity and in the
+ -- corresponding software functions in unb_common.c,h. This avoids having to
+ -- define named constants for indexing the fields in the info word.
entity unb1_board_system_info is
generic (
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
index 594354d35e..d43b3f59ce 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_system_info_reg is
generic (
@@ -69,7 +69,7 @@ entity unb1_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb1_board_system_info_reg;
architecture rtl of unb1_board_system_info_reg is
@@ -80,21 +80,23 @@ architecture rtl of unb1_board_system_info_reg is
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0');
constant c_use_phy_w : natural := 8;
- constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := TO_UVEC(g_use_phy.eth1g, 1) &
- TO_UVEC(g_use_phy.tr_front,1) &
- TO_UVEC(g_use_phy.tr_mesh, 1) &
- TO_UVEC(g_use_phy.tr_back, 1) &
- TO_UVEC(g_use_phy.ddr3_I, 1) &
- TO_UVEC(g_use_phy.ddr3_II, 1) &
- TO_UVEC(g_use_phy.adc, 1) &
- TO_UVEC(g_use_phy.wdi, 1);
+ constant c_use_phy : std_logic_vector(
+ c_use_phy_w - 1 downto 0) := TO_UVEC(g_use_phy.eth1g, 1) &
+ TO_UVEC(g_use_phy.tr_front,1) &
+ TO_UVEC(g_use_phy.tr_mesh, 1) &
+ TO_UVEC(g_use_phy.tr_back, 1) &
+ TO_UVEC(g_use_phy.ddr3_I, 1) &
+ TO_UVEC(g_use_phy.ddr3_II, 1) &
+ TO_UVEC(g_use_phy.adc, 1) &
+ TO_UVEC(g_use_phy.wdi, 1);
constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
index d0e464d77e..47a00ee9b7 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
@@ -34,14 +34,14 @@
-- g_use_tx and g_use_rx because they are both TRUE.
library IEEE, common_lib, dp_lib, uth_lib, tr_nonbonded_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_packet_pkg.all;
-use uth_lib.uth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_packet_pkg.all;
+ use uth_lib.uth_pkg.all;
entity unb1_board_terminals_back is
generic (
@@ -136,80 +136,80 @@ architecture str of unb1_board_terminals_back is
signal rx_serial_arr : std_logic_vector(c_nof_gx - 1 downto 0);
begin
u_unb1_board_back_select: entity work.unb1_board_back_select
- port map (
- bck_id => bck_id,
- clk => dp_clk,
+ port map (
+ bck_id => bck_id,
+ clk => dp_clk,
- -- User side
- tx_usr_sosi_2arr => tx_usr_sosi_2arr,
- tx_usr_siso_2arr => tx_usr_siso_2arr,
+ -- User side
+ tx_usr_sosi_2arr => tx_usr_sosi_2arr,
+ tx_usr_siso_2arr => tx_usr_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr,
- rx_usr_siso_2arr => rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr,
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
- -- Phy side
- tx_phy_sosi_2arr => tx_sel_sosi_2arr,
- tx_phy_siso_2arr => tx_sel_siso_2arr,
+ -- Phy side
+ tx_phy_sosi_2arr => tx_sel_sosi_2arr,
+ tx_phy_siso_2arr => tx_sel_siso_2arr,
- rx_phy_sosi_2arr => rx_sel_sosi_2arr,
- rx_phy_siso_2arr => rx_sel_siso_2arr
- );
+ rx_phy_sosi_2arr => rx_sel_sosi_2arr,
+ rx_phy_siso_2arr => rx_sel_siso_2arr
+ );
u_unb1_board_back_reorder : entity work.unb1_board_back_reorder
- port map (
- bck_id => bck_id,
- clk => dp_clk,
+ port map (
+ bck_id => bck_id,
+ clk => dp_clk,
- -- User side
- tx_usr_sosi_2arr => tx_sel_sosi_2arr,
- tx_usr_siso_2arr => tx_sel_siso_2arr,
+ -- User side
+ tx_usr_sosi_2arr => tx_sel_sosi_2arr,
+ tx_usr_siso_2arr => tx_sel_siso_2arr,
- rx_usr_sosi_2arr => rx_sel_sosi_2arr,
- rx_usr_siso_2arr => rx_sel_siso_2arr,
+ rx_usr_sosi_2arr => rx_sel_sosi_2arr,
+ rx_usr_siso_2arr => rx_sel_siso_2arr,
- -- Phy side
- tx_phy_sosi_2arr => tx_term_sosi_2arr,
- tx_phy_siso_2arr => tx_term_siso_2arr,
+ -- Phy side
+ tx_phy_sosi_2arr => tx_term_sosi_2arr,
+ tx_phy_siso_2arr => tx_term_siso_2arr,
- rx_phy_sosi_2arr => rx_term_sosi_2arr,
- rx_phy_siso_2arr => rx_term_siso_2arr
- );
+ rx_phy_sosi_2arr => rx_term_sosi_2arr,
+ rx_phy_siso_2arr => rx_term_siso_2arr
+ );
u_unb1_board_back_uth_terminals_bidir : entity work.unb1_board_back_uth_terminals_bidir
- generic map (
- -- User
- g_usr_nof_streams => g_usr_nof_streams,
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- -- DP/UTH packet
- g_packet_data_w => c_packet_data_w,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- -- Tx
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- -- Rx
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_timeout_w => g_rx_timeout_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- User
- tx_dp_sosi_2arr => tx_term_sosi_2arr,
- tx_dp_siso_2arr => tx_term_siso_2arr,
-
- rx_dp_sosi_2arr => rx_term_sosi_2arr,
- rx_dp_siso_2arr => rx_term_siso_2arr,
-
- -- Phy
- tx_uth_sosi_2arr => tx_phy_sosi_2arr,
- tx_uth_siso_2arr => tx_phy_siso_2arr,
-
- rx_uth_sosi_2arr => rx_phy_sosi_2arr,
- rx_uth_siso_2arr => rx_phy_siso_2arr
- );
+ generic map (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => c_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ -- Rx
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_timeout_w => g_rx_timeout_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- User
+ tx_dp_sosi_2arr => tx_term_sosi_2arr,
+ tx_dp_siso_2arr => tx_term_siso_2arr,
+
+ rx_dp_sosi_2arr => rx_term_sosi_2arr,
+ rx_dp_siso_2arr => rx_term_siso_2arr,
+
+ -- Phy
+ tx_uth_sosi_2arr => tx_phy_sosi_2arr,
+ tx_uth_siso_2arr => tx_phy_siso_2arr,
+
+ rx_uth_sosi_2arr => rx_phy_sosi_2arr,
+ rx_uth_siso_2arr => rx_phy_siso_2arr
+ );
------------------------------------------------------------------------------
-- GX serial interface level (g_sim_level)
@@ -218,54 +218,54 @@ begin
-- Map 1-dim array on 2-dim array
gen_bus : for i in c_nof_bus_serial - 1 downto 0 generate
gen_lane : for j in g_phy_nof_serial - 1 downto 0 generate
- -- SOSI
- tx_phy_sosi_arr(i * g_phy_nof_serial + j) <= tx_phy_sosi_2arr(i)(j);
- tx_phy_siso_2arr(i)(j) <= tx_phy_siso_arr(i * g_phy_nof_serial + j);
+ -- SOSI
+ tx_phy_sosi_arr(i * g_phy_nof_serial + j) <= tx_phy_sosi_2arr(i)(j);
+ tx_phy_siso_2arr(i)(j) <= tx_phy_siso_arr(i * g_phy_nof_serial + j);
- rx_phy_sosi_2arr(i)(j) <= rx_phy_sosi_arr(i * g_phy_nof_serial + j);
- rx_phy_siso_arr(i * g_phy_nof_serial + j) <= rx_phy_siso_2arr(i)(j);
+ rx_phy_sosi_2arr(i)(j) <= rx_phy_sosi_arr(i * g_phy_nof_serial + j);
+ rx_phy_siso_arr(i * g_phy_nof_serial + j) <= rx_phy_siso_2arr(i)(j);
- -- Serial
- tx_serial_2arr(i)(j) <= tx_serial_arr(i * g_phy_nof_serial + j);
- rx_serial_arr(i * g_phy_nof_serial + j) <= rx_serial_2arr(i)(j);
+ -- Serial
+ tx_serial_2arr(i)(j) <= tx_serial_arr(i * g_phy_nof_serial + j);
+ rx_serial_arr(i * g_phy_nof_serial + j) <= rx_serial_2arr(i)(j);
end generate;
end generate;
u_tr_nonbonded : entity tr_nonbonded_lib.mms_tr_nonbonded
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_nof_gx => c_nof_gx,
- g_mbps => g_phy_gx_mbps,
- g_tx => true,
- g_rx => true,
- g_rx_fifo_depth => g_phy_rx_fifo_size
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- tr_clk => tr_clk,
- cal_rec_clk => cal_clk,
-
- --Serial data I/O
- tx_dataout => tx_serial_arr,
- rx_datain => rx_serial_arr,
-
- --Streaming I/O
- snk_out_arr => tx_phy_siso_arr,
- snk_in_arr => tx_phy_sosi_arr,
-
- src_in_arr => rx_phy_siso_arr,
- src_out_arr => rx_phy_sosi_arr,
-
- tr_nonbonded_mm_mosi => reg_tr_nonbonded_mosi,
- tr_nonbonded_mm_miso => reg_tr_nonbonded_miso,
-
- diagnostics_mm_mosi => reg_diagnostics_mosi,
- diagnostics_mm_miso => reg_diagnostics_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_gx => c_nof_gx,
+ g_mbps => g_phy_gx_mbps,
+ g_tx => true,
+ g_rx => true,
+ g_rx_fifo_depth => g_phy_rx_fifo_size
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ tr_clk => tr_clk,
+ cal_rec_clk => cal_clk,
+
+ --Serial data I/O
+ tx_dataout => tx_serial_arr,
+ rx_datain => rx_serial_arr,
+
+ --Streaming I/O
+ snk_out_arr => tx_phy_siso_arr,
+ snk_in_arr => tx_phy_sosi_arr,
+
+ src_in_arr => rx_phy_siso_arr,
+ src_out_arr => rx_phy_sosi_arr,
+
+ tr_nonbonded_mm_mosi => reg_tr_nonbonded_mosi,
+ tr_nonbonded_mm_miso => reg_tr_nonbonded_miso,
+
+ diagnostics_mm_mosi => reg_diagnostics_mosi,
+ diagnostics_mm_miso => reg_diagnostics_miso
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
index b65dc635d7..c36473442c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
@@ -49,14 +49,14 @@
-- hardware use the default g_phy_ena_reorder = TRUE.
library IEEE, common_lib, dp_lib, uth_lib, tr_nonbonded_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_packet_pkg.all;
-use uth_lib.uth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_packet_pkg.all;
+ use uth_lib.uth_pkg.all;
entity unb1_board_terminals_mesh is
generic (
@@ -88,12 +88,12 @@ entity unb1_board_terminals_mesh is
g_rx_timeout_w : natural := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
-- Monitoring
g_mon_select : natural := 0; -- 0 = no SOSI data buffers monitor via MM
- -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
- -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
- -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
- -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute
- -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded
- -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder
+ -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
+ -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
+ -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
+ -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute
+ -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded
+ -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder
g_mon_nof_words : natural := 1024;
g_mon_use_sync : boolean := true;
-- UTH
@@ -144,20 +144,22 @@ architecture str of unb1_board_terminals_mesh is
-- g_mon_select
constant c_usr_nof_streams : natural := g_nof_bus * g_usr_nof_streams;
- constant c_mon_nof_streams : natural := sel_n(g_mon_select, c_phy_nof_gx,
- c_phy_nof_gx,
- c_phy_nof_gx,
- c_phy_nof_gx,
- c_usr_nof_streams,
- c_phy_nof_gx,
- c_phy_nof_gx);
- constant c_mon_data_w : natural := sel_n(g_mon_select, c_packet_data_w,
- c_packet_data_w,
- c_packet_data_w,
- c_packet_data_w,
- g_usr_data_w,
- c_packet_data_w,
- c_packet_data_w);
+ constant c_mon_nof_streams : natural := sel_n(
+ g_mon_select, c_phy_nof_gx,
+ c_phy_nof_gx,
+ c_phy_nof_gx,
+ c_phy_nof_gx,
+ c_usr_nof_streams,
+ c_phy_nof_gx,
+ c_phy_nof_gx);
+ constant c_mon_data_w : natural := sel_n(
+ g_mon_select, c_packet_data_w,
+ c_packet_data_w,
+ c_packet_data_w,
+ c_packet_data_w,
+ g_usr_data_w,
+ c_packet_data_w,
+ c_packet_data_w);
-- uth terminals
signal tx_term_siso_2arr : t_unb1_board_mesh_siso_2arr;
@@ -243,25 +245,25 @@ begin
gen_monitor : if g_mon_select >= 1 generate
u_data_buf : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_mon_nof_streams,
- g_data_w => c_mon_data_w, -- stream data width must be <= c_word_w = 32b, the MM word width
- g_buf_nof_data => g_mon_nof_words, -- nof words per data buffer
- g_buf_use_sync => g_mon_use_sync -- when TRUE start filling the buffer after the in_sync, else after the last word was read
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- -- ST interface
- in_sync => dp_sync, -- input sync pulse in ST dp_clk domain that starts data buffer when g_use_in_sync = TRUE
- in_sosi_arr => mon_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_mon_nof_streams,
+ g_data_w => c_mon_data_w, -- stream data width must be <= c_word_w = 32b, the MM word width
+ g_buf_nof_data => g_mon_nof_words, -- nof words per data buffer
+ g_buf_use_sync => g_mon_use_sync -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ -- ST interface
+ in_sync => dp_sync, -- input sync pulse in ST dp_clk domain that starts data buffer when g_use_in_sync = TRUE
+ in_sosi_arr => mon_sosi_arr
+ );
end generate;
------------------------------------------------------------------------------
@@ -269,85 +271,85 @@ begin
------------------------------------------------------------------------------
u_unb1_board_mesh_uth_terminals_bidir : entity work.unb1_board_mesh_uth_terminals_bidir
- generic map (
- -- User
- g_usr_nof_streams => g_usr_nof_streams,
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- -- DP/UTH packet
- g_packet_data_w => c_packet_data_w,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- -- Tx
- g_use_tx => g_use_tx,
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- g_tx_input_fifo_size => g_tx_input_fifo_size,
- g_tx_input_fifo_fill => g_tx_input_fifo_fill,
- -- Rx
- g_use_rx => g_use_rx,
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_output_fifo_size => g_rx_output_fifo_size,
- g_rx_output_fifo_fill => g_rx_output_fifo_fill,
- g_rx_timeout_w => g_rx_timeout_w,
- -- UTH
- g_uth_len_max => g_uth_len_max,
- g_uth_typ_ofs => g_uth_typ_ofs
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => c_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w,
+ -- UTH
+ g_uth_len_max => g_uth_len_max,
+ g_uth_typ_ofs => g_uth_typ_ofs
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- User
- tx_dp_sosi_2arr => tx_usr_sosi_2arr,
- tx_dp_siso_2arr => tx_usr_siso_2arr,
+ -- User
+ tx_dp_sosi_2arr => tx_usr_sosi_2arr,
+ tx_dp_siso_2arr => tx_usr_siso_2arr,
- rx_dp_sosi_2arr => rx_usr_sosi_2arr,
- rx_dp_siso_2arr => rx_usr_siso_2arr,
+ rx_dp_sosi_2arr => rx_usr_sosi_2arr,
+ rx_dp_siso_2arr => rx_usr_siso_2arr,
- -- Phy
- tx_uth_sosi_2arr => tx_term_sosi_2arr,
- tx_uth_siso_2arr => tx_term_siso_2arr,
+ -- Phy
+ tx_uth_sosi_2arr => tx_term_sosi_2arr,
+ tx_uth_siso_2arr => tx_term_siso_2arr,
- rx_uth_sosi_2arr => rx_term_sosi_2arr,
- rx_uth_siso_2arr => rx_term_siso_2arr,
+ rx_uth_sosi_2arr => rx_term_sosi_2arr,
+ rx_uth_siso_2arr => rx_term_siso_2arr,
- -- Monitoring
- rx_mon_pkt_sosi_2arr => mon_rx_term_pkt_sosi_2arr,
- rx_mon_dist_sosi_2arr => mon_rx_term_dist_sosi_2arr
- );
+ -- Monitoring
+ rx_mon_pkt_sosi_2arr => mon_rx_term_pkt_sosi_2arr,
+ rx_mon_dist_sosi_2arr => mon_rx_term_dist_sosi_2arr
+ );
------------------------------------------------------------------------------
-- Compensate for mesh reorder (g_phy_ena_reorder)
------------------------------------------------------------------------------
u_tx : entity work.unb1_board_mesh_reorder_tx
- generic map (
- g_node_type => g_node_type,
- g_reorder => g_phy_ena_reorder
- )
- port map (
- chip_id => chip_id,
- clk => dp_clk,
- tx_usr_sosi_2arr => tx_term_sosi_2arr, -- g_use_tx
- rx_usr_siso_2arr => rx_term_siso_2arr, -- g_use_rx
- tx_phy_sosi_2arr => tx_phy_sosi_2arr,
- rx_phy_siso_2arr => rx_phy_siso_2arr
- );
+ generic map (
+ g_node_type => g_node_type,
+ g_reorder => g_phy_ena_reorder
+ )
+ port map (
+ chip_id => chip_id,
+ clk => dp_clk,
+ tx_usr_sosi_2arr => tx_term_sosi_2arr, -- g_use_tx
+ rx_usr_siso_2arr => rx_term_siso_2arr, -- g_use_rx
+ tx_phy_sosi_2arr => tx_phy_sosi_2arr,
+ rx_phy_siso_2arr => rx_phy_siso_2arr
+ );
u_rx : entity work.unb1_board_mesh_reorder_rx
- generic map (
- g_node_type => g_node_type,
- g_reorder => g_phy_ena_reorder
- )
- port map (
- chip_id => chip_id,
- clk => dp_clk,
- rx_phy_sosi_2arr => rx_phy_sosi_2arr,
- tx_phy_siso_2arr => tx_phy_siso_2arr,
- rx_usr_sosi_2arr => rx_term_sosi_2arr, -- g_use_rx
- tx_usr_siso_2arr => tx_term_siso_2arr -- g_use_tx
- );
+ generic map (
+ g_node_type => g_node_type,
+ g_reorder => g_phy_ena_reorder
+ )
+ port map (
+ chip_id => chip_id,
+ clk => dp_clk,
+ rx_phy_sosi_2arr => rx_phy_sosi_2arr,
+ tx_phy_siso_2arr => tx_phy_siso_2arr,
+ rx_usr_sosi_2arr => rx_term_sosi_2arr, -- g_use_rx
+ tx_usr_siso_2arr => tx_term_siso_2arr -- g_use_tx
+ );
------------------------------------------------------------------------------
-- GX serial interface level (g_sim_level)
@@ -356,55 +358,55 @@ begin
-- Map 1-dim array on 2-dim array
gen_bus : for I in g_nof_bus - 1 downto 0 generate
gen_lane : for J in g_phy_nof_serial - 1 downto 0 generate
- -- SOSI
- tx_phy_sosi_arr(I * g_phy_nof_serial + J) <= tx_phy_sosi_2arr(I)(J);
- tx_phy_siso_2arr(I)(J) <= tx_phy_siso_arr(I * g_phy_nof_serial + J);
+ -- SOSI
+ tx_phy_sosi_arr(I * g_phy_nof_serial + J) <= tx_phy_sosi_2arr(I)(J);
+ tx_phy_siso_2arr(I)(J) <= tx_phy_siso_arr(I * g_phy_nof_serial + J);
- rx_phy_sosi_2arr(I)(J) <= rx_phy_sosi_arr(I * g_phy_nof_serial + J);
- rx_phy_siso_arr(I * g_phy_nof_serial + J) <= rx_phy_siso_2arr(I)(J);
+ rx_phy_sosi_2arr(I)(J) <= rx_phy_sosi_arr(I * g_phy_nof_serial + J);
+ rx_phy_siso_arr(I * g_phy_nof_serial + J) <= rx_phy_siso_2arr(I)(J);
- -- Serial
- tx_serial_2arr(I)(J) <= tx_serial_arr(I * g_phy_nof_serial + J);
- rx_serial_arr(I * g_phy_nof_serial + J) <= rx_serial_2arr(I)(J);
+ -- Serial
+ tx_serial_2arr(I)(J) <= tx_serial_arr(I * g_phy_nof_serial + J);
+ rx_serial_arr(I * g_phy_nof_serial + J) <= rx_serial_2arr(I)(J);
end generate;
end generate;
u_tr_nonbonded : entity tr_nonbonded_lib.mms_tr_nonbonded
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_data_w => c_phy_data_w,
- g_nof_gx => c_phy_nof_gx,
- g_mbps => g_phy_gx_mbps,
- g_tx => g_use_tx,
- g_rx => g_use_rx,
- g_rx_fifo_depth => g_phy_rx_fifo_size
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- tr_clk => tr_clk,
- cal_rec_clk => cal_clk,
-
- --Serial data I/O
- tx_dataout => tx_serial_arr,
- rx_datain => rx_serial_arr,
-
- --Streaming I/O
- snk_out_arr => tx_phy_siso_arr,
- snk_in_arr => tx_phy_sosi_arr,
-
- src_in_arr => rx_phy_siso_arr,
- src_out_arr => rx_phy_sosi_arr,
-
- tr_nonbonded_mm_mosi => reg_tr_nonbonded_mosi,
- tr_nonbonded_mm_miso => reg_tr_nonbonded_miso,
-
- diagnostics_mm_mosi => reg_diagnostics_mosi,
- diagnostics_mm_miso => reg_diagnostics_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_data_w => c_phy_data_w,
+ g_nof_gx => c_phy_nof_gx,
+ g_mbps => g_phy_gx_mbps,
+ g_tx => g_use_tx,
+ g_rx => g_use_rx,
+ g_rx_fifo_depth => g_phy_rx_fifo_size
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ tr_clk => tr_clk,
+ cal_rec_clk => cal_clk,
+
+ --Serial data I/O
+ tx_dataout => tx_serial_arr,
+ rx_datain => rx_serial_arr,
+
+ --Streaming I/O
+ snk_out_arr => tx_phy_siso_arr,
+ snk_in_arr => tx_phy_sosi_arr,
+
+ src_in_arr => rx_phy_siso_arr,
+ src_out_arr => rx_phy_sosi_arr,
+
+ tr_nonbonded_mm_mosi => reg_tr_nonbonded_mosi,
+ tr_nonbonded_mm_miso => reg_tr_nonbonded_miso,
+
+ diagnostics_mm_mosi => reg_diagnostics_mosi,
+ diagnostics_mm_miso => reg_diagnostics_miso
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
index 5bc2d1698e..51ea2bc690 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose:
--- Extend the input WDI that is controlled in SW (as it should be) to avoid
--- that the watchdog reset will occur when new SW is loaded, while keeping
--- the HDL image. This component extends the last input WDI by toggling the
--- output WDI for about 2**(g_extend_w-1) ms more.
+ -- Purpose:
+ -- Extend the input WDI that is controlled in SW (as it should be) to avoid
+ -- that the watchdog reset will occur when new SW is loaded, while keeping
+ -- the HDL image. This component extends the last input WDI by toggling the
+ -- output WDI for about 2**(g_extend_w-1) ms more.
entity unb1_board_wdi_extend is
generic (
@@ -68,26 +68,26 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
index 8645f86e8f..5f52f5ddb3 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb1_board_wdi_reg is
port (
@@ -40,16 +40,17 @@ entity unb1_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb1_board_wdi_reg;
architecture rtl of unb1_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
@@ -60,7 +61,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
index ca4d940d7b..3871332af4 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
@@ -32,11 +32,11 @@ entity tb_mms_unb1_board_sens is
end tb_mms_unb1_board_sens;
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
architecture tb of tb_mms_unb1_board_sens is
constant c_sim : boolean := true; -- FALSE;
@@ -147,58 +147,58 @@ begin
-- I2C sensors master
u_mms_unb1_board_sens : entity work.mms_unb1_board_sens
- generic map (
- g_sim => c_sim,
- g_clk_freq => c_clk_freq,
- g_temp_high => c_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- mm_start => start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- i2c bus
- scl => scl,
- sda => sda
- );
+ generic map (
+ g_sim => c_sim,
+ g_clk_freq => c_clk_freq,
+ g_temp_high => c_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ mm_start => start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- i2c bus
+ scl => scl,
+ sda => sda
+ );
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => scl,
- sda => sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd
index f489d4b5d4..608063dc99 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd
@@ -27,7 +27,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_tb_unb1_board_regression is
end tb_tb_tb_unb1_board_regression;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
index c30e88c962..5edd44e3a2 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb1_board_clk200_pll is
end tb_unb1_board_clk200_pll;
@@ -68,68 +68,68 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb1_board_clk200_pll
- generic map (
- g_sel => 0, -- g_sel=0 for clk200_pll.vhd
- -- g_sel=0 for clk200_pll.vhd
- g_clk200_phase_shift => "0",
- g_clk200p_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_sel => 0, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=0 for clk200_pll.vhd
+ g_clk200_phase_shift => "0",
+ g_clk200p_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb1_board_clk200_pll
- generic map (
- g_sel => 0, -- g_sel=0 for clk200_pll.vhd
- -- g_sel=0 for clk200_pll.vhd
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_sel => 0, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=0 for clk200_pll.vhd
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb1_board_clk200_pll
- generic map (
- g_sel => 1, -- g_sel=0 for clk200_pll.vhd
- -- g_sel=1 for clk200_pll_p6.vhd
- g_clk200_phase_shift => "0",
- -- g_sel=1 for clk200_pll_p6.vhd
- g_clk0_phase_shift => "0",
- g_clk_vec_w => c_clk_vec_w,
- g_clk1_phase_shift => "0",
- g_clk2_phase_shift => "156",
- g_clk3_phase_shift => "313",
- g_clk4_phase_shift => "469",
- g_clk5_phase_shift => "625",
- g_clk6_phase_shift => "938",
- g_clk1_divide_by => c_clk_div,
- g_clk2_divide_by => c_clk_div,
- g_clk3_divide_by => c_clk_div,
- g_clk4_divide_by => c_clk_div,
- g_clk5_divide_by => c_clk_div,
- g_clk6_divide_by => c_clk_div
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200,
- -- . g_sel=1
- st_clk_vec => st_clk_vec
- );
+ generic map (
+ g_sel => 1, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=1 for clk200_pll_p6.vhd
+ g_clk200_phase_shift => "0",
+ -- g_sel=1 for clk200_pll_p6.vhd
+ g_clk0_phase_shift => "0",
+ g_clk_vec_w => c_clk_vec_w,
+ g_clk1_phase_shift => "0",
+ g_clk2_phase_shift => "156",
+ g_clk3_phase_shift => "313",
+ g_clk4_phase_shift => "469",
+ g_clk5_phase_shift => "625",
+ g_clk6_phase_shift => "938",
+ g_clk1_divide_by => c_clk_div,
+ g_clk2_divide_by => c_clk_div,
+ g_clk3_divide_by => c_clk_div,
+ g_clk4_divide_by => c_clk_div,
+ g_clk5_divide_by => c_clk_div,
+ g_clk6_divide_by => c_clk_div
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200,
+ -- . g_sel=1
+ st_clk_vec => st_clk_vec
+ );
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
index 1eaa6aa807..4526c62d8e 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
@@ -40,12 +40,12 @@
-- transceiver bus reorderings on UniBoard PCB.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
-use work.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
+ use work.tb_unb1_board_pkg.all;
entity tb_unb1_board_mesh_reorder_bidir is
end tb_unb1_board_mesh_reorder_bidir;
@@ -220,27 +220,27 @@ begin
gen_fn : for I in 0 to c_nof_node-1 generate
u_order : entity work.unb1_board_mesh_reorder_bidir
- generic map (
- g_node_type => e_fn,
- g_reorder => c_reorder
- )
- port map (
- chip_id => TO_UVEC(I, c_chip_id_w), -- chip id 0, 1, 2, 3
-
- -- Transmit clock domain
- tx_clk => clk,
- tx_usr_sosi_2arr => fn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from FN user
- tx_usr_siso_2arr => fn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to FN user
- tx_phy_sosi_2arr => fn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
- tx_phy_siso_2arr => fn_tx_phy_siso_3arr(I), -- phy siso from mesh
-
- -- Receive clock domain
- rx_clk => clk,
- rx_phy_sosi_2arr => fn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
- rx_phy_siso_2arr => fn_rx_phy_siso_3arr(I), -- phy siso to mesh
- rx_usr_sosi_2arr => fn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to FN user
- rx_usr_siso_2arr => fn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from FN user
- );
+ generic map (
+ g_node_type => e_fn,
+ g_reorder => c_reorder
+ )
+ port map (
+ chip_id => TO_UVEC(I, c_chip_id_w), -- chip id 0, 1, 2, 3
+
+ -- Transmit clock domain
+ tx_clk => clk,
+ tx_usr_sosi_2arr => fn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from FN user
+ tx_usr_siso_2arr => fn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to FN user
+ tx_phy_sosi_2arr => fn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
+ tx_phy_siso_2arr => fn_tx_phy_siso_3arr(I), -- phy siso from mesh
+
+ -- Receive clock domain
+ rx_clk => clk,
+ rx_phy_sosi_2arr => fn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
+ rx_phy_siso_2arr => fn_rx_phy_siso_3arr(I), -- phy siso to mesh
+ rx_usr_sosi_2arr => fn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to FN user
+ rx_usr_siso_2arr => fn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from FN user
+ );
end generate;
------------------------------------------------------------------------------
@@ -260,18 +260,18 @@ begin
end generate;
u_pcb_mesh_serial : entity work.unb1_board_mesh_model_sl
- generic map (
- g_reorder => c_reorder
- )
- port map (
- -- FN to BN
- fn_tx_sl_3arr => fn_tx_phy_sl_3arr,
- bn_rx_sl_3arr => bn_rx_phy_sl_3arr,
-
- -- BN to FN
- bn_tx_sl_3arr => bn_tx_phy_sl_3arr,
- fn_rx_sl_3arr => fn_rx_phy_sl_3arr
- );
+ generic map (
+ g_reorder => c_reorder
+ )
+ port map (
+ -- FN to BN
+ fn_tx_sl_3arr => fn_tx_phy_sl_3arr,
+ bn_rx_sl_3arr => bn_rx_phy_sl_3arr,
+
+ -- BN to FN
+ bn_tx_sl_3arr => bn_tx_phy_sl_3arr,
+ fn_rx_sl_3arr => fn_rx_phy_sl_3arr
+ );
-- Use rx_phy SOSI.valid as reference output to verify output of unb1_board_mesh_model_sl
mon_rx_serial : for I in 0 to c_nof_node-1 generate
@@ -298,62 +298,62 @@ begin
-- >>> unb1_board_mesh_model_sosi
u_pcb_mesh_sosi : entity work.unb1_board_mesh_model_sosi
- generic map (
- g_reorder => c_reorder
- )
- port map (
- -- FN to BN
- fn0_tx_sosi_2arr => fn_tx_phy_sosi_3arr(0),
- fn1_tx_sosi_2arr => fn_tx_phy_sosi_3arr(1),
- fn2_tx_sosi_2arr => fn_tx_phy_sosi_3arr(2),
- fn3_tx_sosi_2arr => fn_tx_phy_sosi_3arr(3),
-
- bn0_rx_sosi_2arr => bn_rx_phy_sosi_3arr(0),
- bn1_rx_sosi_2arr => bn_rx_phy_sosi_3arr(1),
- bn2_rx_sosi_2arr => bn_rx_phy_sosi_3arr(2),
- bn3_rx_sosi_2arr => bn_rx_phy_sosi_3arr(3),
-
- -- BN to FN
- bn0_tx_sosi_2arr => bn_tx_phy_sosi_3arr(0),
- bn1_tx_sosi_2arr => bn_tx_phy_sosi_3arr(1),
- bn2_tx_sosi_2arr => bn_tx_phy_sosi_3arr(2),
- bn3_tx_sosi_2arr => bn_tx_phy_sosi_3arr(3),
-
- fn0_rx_sosi_2arr => fn_rx_phy_sosi_3arr(0),
- fn1_rx_sosi_2arr => fn_rx_phy_sosi_3arr(1),
- fn2_rx_sosi_2arr => fn_rx_phy_sosi_3arr(2),
- fn3_rx_sosi_2arr => fn_rx_phy_sosi_3arr(3)
- );
+ generic map (
+ g_reorder => c_reorder
+ )
+ port map (
+ -- FN to BN
+ fn0_tx_sosi_2arr => fn_tx_phy_sosi_3arr(0),
+ fn1_tx_sosi_2arr => fn_tx_phy_sosi_3arr(1),
+ fn2_tx_sosi_2arr => fn_tx_phy_sosi_3arr(2),
+ fn3_tx_sosi_2arr => fn_tx_phy_sosi_3arr(3),
+
+ bn0_rx_sosi_2arr => bn_rx_phy_sosi_3arr(0),
+ bn1_rx_sosi_2arr => bn_rx_phy_sosi_3arr(1),
+ bn2_rx_sosi_2arr => bn_rx_phy_sosi_3arr(2),
+ bn3_rx_sosi_2arr => bn_rx_phy_sosi_3arr(3),
+
+ -- BN to FN
+ bn0_tx_sosi_2arr => bn_tx_phy_sosi_3arr(0),
+ bn1_tx_sosi_2arr => bn_tx_phy_sosi_3arr(1),
+ bn2_tx_sosi_2arr => bn_tx_phy_sosi_3arr(2),
+ bn3_tx_sosi_2arr => bn_tx_phy_sosi_3arr(3),
+
+ fn0_rx_sosi_2arr => fn_rx_phy_sosi_3arr(0),
+ fn1_rx_sosi_2arr => fn_rx_phy_sosi_3arr(1),
+ fn2_rx_sosi_2arr => fn_rx_phy_sosi_3arr(2),
+ fn3_rx_sosi_2arr => fn_rx_phy_sosi_3arr(3)
+ );
-- >>> unb1_board_mesh_model_siso
u_pcb_mesh_siso : entity work.unb1_board_mesh_model_siso
- generic map (
- g_reorder => c_reorder
- )
- port map (
- -- FN to BN
- fn0_rx_siso_2arr => fn_rx_phy_siso_3arr(0),
- fn1_rx_siso_2arr => fn_rx_phy_siso_3arr(1),
- fn2_rx_siso_2arr => fn_rx_phy_siso_3arr(2),
- fn3_rx_siso_2arr => fn_rx_phy_siso_3arr(3),
-
- bn0_tx_siso_2arr => bn_tx_phy_siso_3arr(0),
- bn1_tx_siso_2arr => bn_tx_phy_siso_3arr(1),
- bn2_tx_siso_2arr => bn_tx_phy_siso_3arr(2),
- bn3_tx_siso_2arr => bn_tx_phy_siso_3arr(3),
-
- -- BN to FN
- bn0_rx_siso_2arr => bn_rx_phy_siso_3arr(0),
- bn1_rx_siso_2arr => bn_rx_phy_siso_3arr(1),
- bn2_rx_siso_2arr => bn_rx_phy_siso_3arr(2),
- bn3_rx_siso_2arr => bn_rx_phy_siso_3arr(3),
-
- fn0_tx_siso_2arr => fn_tx_phy_siso_3arr(0),
- fn1_tx_siso_2arr => fn_tx_phy_siso_3arr(1),
- fn2_tx_siso_2arr => fn_tx_phy_siso_3arr(2),
- fn3_tx_siso_2arr => fn_tx_phy_siso_3arr(3)
- );
+ generic map (
+ g_reorder => c_reorder
+ )
+ port map (
+ -- FN to BN
+ fn0_rx_siso_2arr => fn_rx_phy_siso_3arr(0),
+ fn1_rx_siso_2arr => fn_rx_phy_siso_3arr(1),
+ fn2_rx_siso_2arr => fn_rx_phy_siso_3arr(2),
+ fn3_rx_siso_2arr => fn_rx_phy_siso_3arr(3),
+
+ bn0_tx_siso_2arr => bn_tx_phy_siso_3arr(0),
+ bn1_tx_siso_2arr => bn_tx_phy_siso_3arr(1),
+ bn2_tx_siso_2arr => bn_tx_phy_siso_3arr(2),
+ bn3_tx_siso_2arr => bn_tx_phy_siso_3arr(3),
+
+ -- BN to FN
+ bn0_rx_siso_2arr => bn_rx_phy_siso_3arr(0),
+ bn1_rx_siso_2arr => bn_rx_phy_siso_3arr(1),
+ bn2_rx_siso_2arr => bn_rx_phy_siso_3arr(2),
+ bn3_rx_siso_2arr => bn_rx_phy_siso_3arr(3),
+
+ fn0_tx_siso_2arr => fn_tx_phy_siso_3arr(0),
+ fn1_tx_siso_2arr => fn_tx_phy_siso_3arr(1),
+ fn2_tx_siso_2arr => fn_tx_phy_siso_3arr(2),
+ fn3_tx_siso_2arr => fn_tx_phy_siso_3arr(3)
+ );
------------------------------------------------------------------------------
-- UniBoard BN0,1,2,3
@@ -361,27 +361,27 @@ begin
gen_bn : for I in 0 to c_nof_node-1 generate
u_order : entity work.unb1_board_mesh_reorder_bidir
- generic map (
- g_node_type => e_bn,
- g_reorder => c_reorder
- )
- port map (
- chip_id => TO_UVEC(c_nof_node + I, c_chip_id_w), -- chip id 4, 5, 6, 7
-
- -- Transmit clock domain
- tx_clk => clk,
- tx_usr_sosi_2arr => bn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from BN user
- tx_usr_siso_2arr => bn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to BN user
- tx_phy_sosi_2arr => bn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
- tx_phy_siso_2arr => bn_tx_phy_siso_3arr(I), -- phy siso from mesh
-
- -- Receive clock domain
- rx_clk => clk,
- rx_phy_sosi_2arr => bn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
- rx_phy_siso_2arr => bn_rx_phy_siso_3arr(I), -- phy siso to mesh
- rx_usr_sosi_2arr => bn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to BN user
- rx_usr_siso_2arr => bn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from BN user
- );
+ generic map (
+ g_node_type => e_bn,
+ g_reorder => c_reorder
+ )
+ port map (
+ chip_id => TO_UVEC(c_nof_node + I, c_chip_id_w), -- chip id 4, 5, 6, 7
+
+ -- Transmit clock domain
+ tx_clk => clk,
+ tx_usr_sosi_2arr => bn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from BN user
+ tx_usr_siso_2arr => bn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to BN user
+ tx_phy_sosi_2arr => bn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
+ tx_phy_siso_2arr => bn_tx_phy_siso_3arr(I), -- phy siso from mesh
+
+ -- Receive clock domain
+ rx_clk => clk,
+ rx_phy_sosi_2arr => bn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
+ rx_phy_siso_2arr => bn_rx_phy_siso_3arr(I), -- phy siso to mesh
+ rx_usr_sosi_2arr => bn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to BN user
+ rx_usr_siso_2arr => bn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from BN user
+ );
end generate;
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
index de88c78405..bb724d59f8 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb1_board_node_ctrl is
end tb_unb1_board_node_ctrl;
@@ -76,22 +76,22 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb1_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- sys_clk => sys_clk,
- sys_locked => sys_locked,
- sys_rst => sys_rst,
- wdi_in => wdi_in,
- wdi_out => wdi_out,
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ sys_clk => sys_clk,
+ sys_locked => sys_locked,
+ sys_rst => sys_rst,
+ wdi_in => wdi_in,
+ wdi_out => wdi_out,
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
index f404f0a478..09df5093c4 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
package tb_unb1_board_pkg is
-- Aggregate types to contain all TR for all nodes on one side of the mesh or backplane interface
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
index 59579fcd40..aad1c3a9ec 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
@@ -35,11 +35,11 @@
-- . Phy bus 3 is not used and left not connected on the backplane.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use work.unb1_board_pkg.all;
-use work.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use work.unb1_board_pkg.all;
+ use work.tb_unb1_board_pkg.all;
entity unb1_board_back_model_sl is
port (
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
index 6262f52ab7..34ee7c1332 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
@@ -25,11 +25,11 @@
-- Model the backplane at sosi level. See unb1_board_back_model_sl for more details.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use work.unb1_board_pkg.all;
-use work.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use work.unb1_board_pkg.all;
+ use work.tb_unb1_board_pkg.all;
entity unb1_board_back_model_sosi is
port (
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
index c186f45bb4..1c4f27aee4 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
@@ -24,11 +24,11 @@
-- Description: See unb1_board_mesh_reorder_bidir.vhd
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_model_siso is
generic (
@@ -108,7 +108,7 @@ begin
-- Actual UniBoard PCB mesh connect for transpose
gen_reorder : if g_reorder = true generate
- -- BN, phy <= FN, phy
+ -- BN, phy <= FN, phy
bn0_tx_siso_2arr(0) <= fn3_rx_siso_2arr(1); -- 0,0 <= 3,1
bn0_tx_siso_2arr(1) <= fn2_rx_siso_2arr(0); -- 0,1 <= 2,0
bn0_tx_siso_2arr(2) <= fn1_rx_siso_2arr(0); -- 0,2 <= 1,0
@@ -129,7 +129,7 @@ begin
bn3_tx_siso_2arr(2) <= fn2_rx_siso_2arr(3); -- 3,2 <= 2,3
bn3_tx_siso_2arr(3) <= fn1_rx_siso_2arr(2); -- 3,3 <= 1,2
- -- FN, phy <= BN, phy
+ -- FN, phy <= BN, phy
fn0_tx_siso_2arr(0) <= bn0_rx_siso_2arr(3); -- 0,0 <= 0,3
fn0_tx_siso_2arr(1) <= bn3_rx_siso_2arr(1); -- 0,1 <= 3,1
fn0_tx_siso_2arr(2) <= bn2_rx_siso_2arr(2); -- 0,2 <= 2,2
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
index 11019e63c4..322ef4cc15 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
@@ -25,12 +25,12 @@
-- Description: See unb1_board_mesh_reorder_bidir.vhd
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
-use work.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
+ use work.tb_unb1_board_pkg.all;
entity unb1_board_mesh_model_sl is
generic (
@@ -63,7 +63,7 @@ begin
-- Actual UniBoard PCB mesh connect for transpose
gen_reorder : if g_reorder = true generate
- -- BN, phy <= FN, phy
+ -- BN, phy <= FN, phy
bn_rx_sl_3arr(0)(0) <= fn_tx_sl_3arr(3)(1); -- 0,0 <= 3,1
bn_rx_sl_3arr(0)(1) <= fn_tx_sl_3arr(2)(0); -- 0,1 <= 2,0
bn_rx_sl_3arr(0)(2) <= fn_tx_sl_3arr(1)(0); -- 0,2 <= 1,0
@@ -84,7 +84,7 @@ begin
bn_rx_sl_3arr(3)(2) <= fn_tx_sl_3arr(2)(3); -- 3,2 <= 2,3
bn_rx_sl_3arr(3)(3) <= fn_tx_sl_3arr(1)(2); -- 3,3 <= 1,2
- -- FN, phy <= BN, phy
+ -- FN, phy <= BN, phy
fn_rx_sl_3arr(0)(0) <= bn_tx_sl_3arr(0)(3); -- 0,0 <= 0,3
fn_rx_sl_3arr(0)(1) <= bn_tx_sl_3arr(3)(1); -- 0,1 <= 3,1
fn_rx_sl_3arr(0)(2) <= bn_tx_sl_3arr(2)(2); -- 0,2 <= 2,2
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
index 17a37b3c88..6b1064c11f 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
@@ -24,11 +24,11 @@
-- Description: See unb1_board_mesh_reorder_bidir.vhd
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_model_sosi is
generic (
@@ -108,7 +108,7 @@ begin
-- Actual UniBoard PCB mesh connect for transpose
gen_reorder : if g_reorder = true generate
- -- BN, phy <= FN, phy
+ -- BN, phy <= FN, phy
bn0_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(1); -- 0,0 <= 3,1
bn0_rx_sosi_2arr(1) <= fn2_tx_sosi_2arr(0); -- 0,1 <= 2,0
bn0_rx_sosi_2arr(2) <= fn1_tx_sosi_2arr(0); -- 0,2 <= 1,0
@@ -129,7 +129,7 @@ begin
bn3_rx_sosi_2arr(2) <= fn2_tx_sosi_2arr(3); -- 3,2 <= 2,3
bn3_rx_sosi_2arr(3) <= fn1_tx_sosi_2arr(2); -- 3,3 <= 1,2
- -- FN, phy <= BN, phy
+ -- FN, phy <= BN, phy
fn0_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(3); -- 0,0 <= 0,3
fn0_rx_sosi_2arr(1) <= bn3_tx_sosi_2arr(1); -- 0,1 <= 3,1
fn0_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(2); -- 0,2 <= 2,2
diff --git a/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd b/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
index ebe9c5d3e7..54eb78e005 100644
--- a/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
+++ b/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
entity unb2_led is
generic (
@@ -99,15 +99,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
-- mm_clk
@@ -118,40 +118,40 @@ begin
i_mm_clk <= clk50;
gen_mm_clk_sim: if g_sim = true generate
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- mm_locked <= '0', '1' after 70 ns;
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2_board_clk125_pll : entity unb2_board_lib.unb2_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c1_clk50 => clk50,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2_board_node_ctrl : entity unb2_board_lib.unb2_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c1_clk50 => clk50,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => mm_pulse_s,
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2_board_node_ctrl : entity unb2_board_lib.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => mm_pulse_s,
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
------------------------------------------------------------------------------
-- Toggle red LED when unb2_minimal is running, green LED for other designs.
@@ -177,17 +177,17 @@ begin
TESTIO(c_unb2_board_testio_led_green) <= led_flash_green;
u_common_pulser_10Hz : entity common_lib.common_pulser
- generic map (
- g_pulse_period => 100,
- g_pulse_phase => 100 - 1
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- clken => '1',
- pulse_en => mm_pulse_ms,
- pulse_out => pulse_10Hz
- );
+ generic map (
+ g_pulse_period => 100,
+ g_pulse_phase => 100 - 1
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ clken => '1',
+ pulse_en => mm_pulse_ms,
+ pulse_out => pulse_10Hz
+ );
u_extend_10Hz : common_lib.common_pulse_extend
generic map (
@@ -201,12 +201,12 @@ begin
);
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
QSFP_LED(2) <= pulse_10Hz_extended;
QSFP_LED(6) <= led_toggle;
diff --git a/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd b/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
index 71ff33a36b..257ecaa763 100644
--- a/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
+++ b/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
@@ -39,18 +39,18 @@
--
library IEEE, common_lib, unb2_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2_led is
- generic (
- g_design_name : string := "unb2_led";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2_led";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2_led;
architecture tb of tb_unb2_led is
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
index 2bd1ab97d5..0d6efaada5 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use unb2_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use unb2_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2_minimal_pkg.all;
entity mmm_unb2_minimal is
generic (
@@ -110,33 +110,42 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -291,7 +300,7 @@ begin
reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
end str;
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
index 305c225eae..7ba69f92f0 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
@@ -20,136 +20,136 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v14 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_unb2_minimal is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(4 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
- );
- end component qsys_unb2_minimal;
+ component qsys_unb2_minimal is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2_minimal;
end qsys_unb2_minimal_pkg;
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
index c0ae33a4c2..9aa1b2df9b 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
entity unb2_minimal is
generic (
@@ -156,219 +156,219 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ QSFP_LED => QSFP_LED
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
- );
-
--- u_front_led : ENTITY unb2_board_lib.unb2_board_qsfp_leds
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_factory_image => g_factory_image,
--- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
--- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
--- )
--- PORT MAP (
--- rst => mm_rst,
--- clk => mm_clk,
--- green_led_arr => qsfp_green_led_arr,
--- red_led_arr => qsfp_red_led_arr
--- );
---
--- u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
--- GENERIC MAP (
--- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
--- )
--- PORT MAP (
--- green_led_arr => qsfp_green_led_arr,
--- red_led_arr => qsfp_red_led_arr,
--- QSFP_LED => QSFP_LED
--- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso
+ );
+
+ -- u_front_led : ENTITY unb2_board_lib.unb2_board_qsfp_leds
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_factory_image => g_factory_image,
+ -- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ -- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- )
+ -- PORT MAP (
+ -- rst => mm_rst,
+ -- clk => mm_clk,
+ -- green_led_arr => qsfp_green_led_arr,
+ -- red_led_arr => qsfp_red_led_arr
+ -- );
+ --
+ -- u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
+ -- GENERIC MAP (
+ -- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ -- )
+ -- PORT MAP (
+ -- green_led_arr => qsfp_green_led_arr,
+ -- red_led_arr => qsfp_red_led_arr,
+ -- QSFP_LED => QSFP_LED
+ -- );
end str;
diff --git a/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
index 5f1ebd006c..41cdac2354 100644
--- a/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb2_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2_minimal is
- generic (
- g_design_name : string := "unb2_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2_minimal;
architecture tb of tb_unb2_minimal is
@@ -181,36 +181,36 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
index 24a8174ff6..6b2562529f 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
+++ b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, unb_common_lib;
-use unb_common_lib.unb_common_pkg.all;
-use IEEE.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use unb_common_lib.unb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity unb2_pinning is
port (
@@ -131,8 +131,8 @@ entity unb2_pinning is
-- I2C Interface to Sensors
SENS_SC : inout std_logic;
SENS_SD : inout std_logic;
- -- Others
--- CFG_DATA : inout std_logic_vector (3 downto 0);
+ -- Others
+ -- CFG_DATA : inout std_logic_vector (3 downto 0);
VERSION : in std_logic_vector(1 downto 0);
ID : in std_logic_vector(7 downto 0);
TESTIO : inout std_logic_vector(5 downto 0);
@@ -141,184 +141,184 @@ entity unb2_pinning is
end unb2_pinning;
architecture str of unb2_pinning is
- component ddr4 is
- port (
- global_reset_n : in std_logic := 'X'; -- reset_n
- pll_ref_clk : in std_logic := 'X'; -- clk
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_alert_n : in std_logic_vector(0 downto 0); -- mem_alert_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par ** new in 14.0 **
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic; -- local_cal_fail
- emif_usr_reset_n : out std_logic; -- reset_n
- emif_usr_clk : out std_logic; -- clk
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address ** chg from 23 bits in 14.0 **
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount ** chg from 8 bits in 14.0 **
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic -- readdatavalid
- );
- end component ddr4;
-
- component transceiver_phy is
- port (
- tx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_analogreset
- tx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_digitalreset
- rx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_analogreset
- rx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_digitalreset
- tx_cal_busy : out std_logic_vector(47 downto 0); -- tx_cal_busy
- rx_cal_busy : out std_logic_vector(47 downto 0); -- rx_cal_busy
- rx_is_lockedtodata : out std_logic_vector(47 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
- rx_cdr_refclk0 : in std_logic := 'X'; -- clk
- tx_serial_data : out std_logic_vector(47 downto 0); -- tx_serial_data
- rx_serial_data : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_serial_data
- tx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
- rx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
- tx_clkout : out std_logic_vector(47 downto 0); -- clk
- rx_clkout : out std_logic_vector(47 downto 0); -- clk
- tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_enh_data_valid
- rx_enh_data_valid : out std_logic_vector(47 downto 0); -- rx_enh_data_valid
- rx_enh_blk_lock : out std_logic_vector(47 downto 0); -- rx_enh_blk_lock
- tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X'); -- tx_parallel_data
- tx_control : in std_logic_vector(383 downto 0) := (others => 'X'); -- tx_control
- tx_err_ins : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_err_ins
- unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X'); -- unused_tx_parallel_data
- unused_tx_control : in std_logic_vector(431 downto 0) := (others => 'X'); -- unused_tx_control
- rx_parallel_data : out std_logic_vector(3071 downto 0); -- rx_parallel_data
- rx_control : out std_logic_vector(383 downto 0); -- rx_control
- unused_rx_parallel_data : out std_logic_vector(3071 downto 0); -- unused_rx_parallel_data
- unused_rx_control : out std_logic_vector(575 downto 0) -- unused_rx_control
- );
- end component transceiver_phy;
-
- component transceiver_phy_24channel is
- port (
- tx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_analogreset
- tx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_digitalreset
- rx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_analogreset
- rx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_digitalreset
- tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy
- rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy
- rx_is_lockedtodata : out std_logic_vector(23 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
- rx_cdr_refclk0 : in std_logic := 'X'; -- clk
- tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data
- rx_serial_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_serial_data
- tx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
- rx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
- tx_clkout : out std_logic_vector(23 downto 0); -- clk
- rx_clkout : out std_logic_vector(23 downto 0); -- clk
- tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_enh_data_valid
- rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid
- rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock
- tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X'); -- tx_parallel_data
- tx_control : in std_logic_vector(191 downto 0) := (others => 'X'); -- tx_control
- tx_err_ins : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_err_ins
- unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X'); -- unused_tx_parallel_data
- unused_tx_control : in std_logic_vector(215 downto 0) := (others => 'X'); -- unused_tx_control
- rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data
- rx_control : out std_logic_vector(191 downto 0); -- rx_control
- unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data
- unused_rx_control : out std_logic_vector(287 downto 0) -- unused_rx_control
- );
- end component transceiver_phy_24channel;
-
- component transceiver_reset_controller is
- port (
- clock : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- tx_analogreset : out std_logic_vector(47 downto 0); -- tx_analogreset
- tx_digitalreset : out std_logic_vector(47 downto 0); -- tx_digitalreset
- tx_ready : out std_logic_vector(47 downto 0); -- tx_ready
- pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
- pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
- tx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_cal_busy
- rx_analogreset : out std_logic_vector(47 downto 0); -- rx_analogreset
- rx_digitalreset : out std_logic_vector(47 downto 0); -- rx_digitalreset
- rx_ready : out std_logic_vector(47 downto 0); -- rx_ready
- rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X') -- rx_cal_busy
- );
- end component transceiver_reset_controller;
-
- component transceiver_reset_controller_24 is
- port (
- clock : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset
- tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset
- tx_ready : out std_logic_vector(23 downto 0); -- tx_ready
- pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
- pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
- tx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_cal_busy
- rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset
- rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset
- rx_ready : out std_logic_vector(23 downto 0); -- rx_ready
- rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X') -- rx_cal_busy
- );
- end component transceiver_reset_controller_24;
-
- component transceiver_pll is
- port (
- pll_powerdown : in std_logic := 'X'; -- pll_powerdown
- pll_refclk0 : in std_logic := 'X'; -- clk
- pll_locked : out std_logic; -- pll_locked
- pll_cal_busy : out std_logic; -- pll_cal_busy
- mcgb_rst : in std_logic := 'X'; -- mcgb_rst
- mcgb_serial_clk : out std_logic -- clk
- );
- end component transceiver_pll;
-
- component sys_clkctrl is
- port (
- inclk : in std_logic := 'X'; -- inclk
- outclk : out std_logic -- outclk
- );
- end component sys_clkctrl;
-
- component system_pll is
- port (
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X';
- locked : out std_logic;
- outclk_0 : out std_logic; -- outclk0
- outclk_1 : out std_logic; -- outclk1
- outclk_2 : out std_logic -- outclk2
- );
+ component ddr4 is
+ port (
+ global_reset_n : in std_logic := 'X'; -- reset_n
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ mem_alert_n : in std_logic_vector(0 downto 0); -- mem_alert_n
+ mem_par : out std_logic_vector(0 downto 0); -- mem_par ** new in 14.0 **
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
+ local_cal_success : out std_logic; -- local_cal_success
+ local_cal_fail : out std_logic; -- local_cal_fail
+ emif_usr_reset_n : out std_logic; -- reset_n
+ emif_usr_clk : out std_logic; -- clk
+ amm_ready_0 : out std_logic; -- waitrequest_n
+ amm_read_0 : in std_logic := 'X'; -- read
+ amm_write_0 : in std_logic := 'X'; -- write
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address ** chg from 23 bits in 14.0 **
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount ** chg from 8 bits in 14.0 **
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
+ amm_readdatavalid_0 : out std_logic -- readdatavalid
+ );
+ end component ddr4;
+
+ component transceiver_phy is
+ port (
+ tx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_digitalreset
+ rx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_digitalreset
+ tx_cal_busy : out std_logic_vector(47 downto 0); -- tx_cal_busy
+ rx_cal_busy : out std_logic_vector(47 downto 0); -- rx_cal_busy
+ rx_is_lockedtodata : out std_logic_vector(47 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
+ rx_cdr_refclk0 : in std_logic := 'X'; -- clk
+ tx_serial_data : out std_logic_vector(47 downto 0); -- tx_serial_data
+ rx_serial_data : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_serial_data
+ tx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
+ rx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
+ tx_clkout : out std_logic_vector(47 downto 0); -- clk
+ rx_clkout : out std_logic_vector(47 downto 0); -- clk
+ tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(47 downto 0); -- rx_enh_data_valid
+ rx_enh_blk_lock : out std_logic_vector(47 downto 0); -- rx_enh_blk_lock
+ tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X'); -- tx_parallel_data
+ tx_control : in std_logic_vector(383 downto 0) := (others => 'X'); -- tx_control
+ tx_err_ins : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_err_ins
+ unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X'); -- unused_tx_parallel_data
+ unused_tx_control : in std_logic_vector(431 downto 0) := (others => 'X'); -- unused_tx_control
+ rx_parallel_data : out std_logic_vector(3071 downto 0); -- rx_parallel_data
+ rx_control : out std_logic_vector(383 downto 0); -- rx_control
+ unused_rx_parallel_data : out std_logic_vector(3071 downto 0); -- unused_rx_parallel_data
+ unused_rx_control : out std_logic_vector(575 downto 0) -- unused_rx_control
+ );
+ end component transceiver_phy;
+
+ component transceiver_phy_24channel is
+ port (
+ tx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_digitalreset
+ rx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_digitalreset
+ tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy
+ rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy
+ rx_is_lockedtodata : out std_logic_vector(23 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
+ rx_cdr_refclk0 : in std_logic := 'X'; -- clk
+ tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data
+ rx_serial_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_serial_data
+ tx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
+ rx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
+ tx_clkout : out std_logic_vector(23 downto 0); -- clk
+ rx_clkout : out std_logic_vector(23 downto 0); -- clk
+ tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid
+ rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock
+ tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X'); -- tx_parallel_data
+ tx_control : in std_logic_vector(191 downto 0) := (others => 'X'); -- tx_control
+ tx_err_ins : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_err_ins
+ unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X'); -- unused_tx_parallel_data
+ unused_tx_control : in std_logic_vector(215 downto 0) := (others => 'X'); -- unused_tx_control
+ rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data
+ rx_control : out std_logic_vector(191 downto 0); -- rx_control
+ unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data
+ unused_rx_control : out std_logic_vector(287 downto 0) -- unused_rx_control
+ );
+ end component transceiver_phy_24channel;
+
+ component transceiver_reset_controller is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ tx_analogreset : out std_logic_vector(47 downto 0); -- tx_analogreset
+ tx_digitalreset : out std_logic_vector(47 downto 0); -- tx_digitalreset
+ tx_ready : out std_logic_vector(47 downto 0); -- tx_ready
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
+ tx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_cal_busy
+ rx_analogreset : out std_logic_vector(47 downto 0); -- rx_analogreset
+ rx_digitalreset : out std_logic_vector(47 downto 0); -- rx_digitalreset
+ rx_ready : out std_logic_vector(47 downto 0); -- rx_ready
+ rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X') -- rx_cal_busy
+ );
+ end component transceiver_reset_controller;
+
+ component transceiver_reset_controller_24 is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset
+ tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset
+ tx_ready : out std_logic_vector(23 downto 0); -- tx_ready
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
+ tx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_cal_busy
+ rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset
+ rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset
+ rx_ready : out std_logic_vector(23 downto 0); -- rx_ready
+ rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X') -- rx_cal_busy
+ );
+ end component transceiver_reset_controller_24;
+
+ component transceiver_pll is
+ port (
+ pll_powerdown : in std_logic := 'X'; -- pll_powerdown
+ pll_refclk0 : in std_logic := 'X'; -- clk
+ pll_locked : out std_logic; -- pll_locked
+ pll_cal_busy : out std_logic; -- pll_cal_busy
+ mcgb_rst : in std_logic := 'X'; -- mcgb_rst
+ mcgb_serial_clk : out std_logic -- clk
+ );
+ end component transceiver_pll;
+
+ component sys_clkctrl is
+ port (
+ inclk : in std_logic := 'X'; -- inclk
+ outclk : out std_logic -- outclk
+ );
+ end component sys_clkctrl;
+
+ component system_pll is
+ port (
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X';
+ locked : out std_logic;
+ outclk_0 : out std_logic; -- outclk0
+ outclk_1 : out std_logic; -- outclk1
+ outclk_2 : out std_logic -- outclk2
+ );
end component system_pll;
- component system_fpll is
- port (
- pll_refclk0 : in std_logic := 'X'; -- clk
- pll_powerdown : in std_logic := 'X';
- pll_locked : out std_logic;
- pll_cal_busy : out std_logic;
- outclk0 : out std_logic; -- outclk0
- outclk1 : out std_logic; -- outclk1
- outclk2 : out std_logic -- outclk2
- );
+ component system_fpll is
+ port (
+ pll_refclk0 : in std_logic := 'X'; -- clk
+ pll_powerdown : in std_logic := 'X';
+ pll_locked : out std_logic;
+ pll_cal_busy : out std_logic;
+ outclk0 : out std_logic; -- outclk0
+ outclk1 : out std_logic; -- outclk1
+ outclk2 : out std_logic -- outclk2
+ );
end component system_fpll;
component unb2_pinning_qsys is
@@ -381,608 +381,608 @@ architecture str of unb2_pinning is
eth_tse_1_serial_connection_txp_0 : out std_logic; -- txp
pio_0_external_connection_export : in std_logic_vector(11 downto 0) := (others => 'X') -- export
- );
+ );
end component unb2_pinning_qsys;
- -- constants
- constant cs_sim : std_logic := '0';
- constant cs_sync : std_logic := '1';
-
- -- general reset and clock signals
- signal reset_n : std_logic;
- signal reset_p : std_logic;
- signal pout_wdi : std_logic := '0';
- signal sys_clk : std_logic := '0';
- signal sys_locked : std_logic := '0';
- signal mm_clk : std_logic := '0';
- signal clk_125 : std_logic := '0';
- signal CLK_buffered : std_logic := '0';
-
- -- signals for the ddr4 controllers
- signal local_i_cal_success : std_logic;
- signal local_i_cal_fail : std_logic;
- signal local_i_reset_n : std_logic;
- signal local_i_clk : std_logic;
- signal local_i_ready : std_logic;
- signal local_i_read : std_logic;
- signal local_i_write : std_logic;
- signal local_i_address : std_logic_vector(26 downto 0);
- signal local_i_readdata : std_logic_vector(575 downto 0);
- signal local_i_writedata : std_logic_vector(575 downto 0);
- signal local_i_burstcount : std_logic_vector(6 downto 0);
- signal local_i_be : std_logic_vector(71 downto 0);
- signal local_i_read_data_valid : std_logic;
- signal mb_i_a_internal : std_logic_vector(16 downto 0);
- signal local_ii_cal_success : std_logic;
- signal local_ii_cal_fail : std_logic;
- signal local_ii_reset_n : std_logic;
- signal local_ii_clk : std_logic;
- signal local_ii_ready : std_logic;
- signal local_ii_read : std_logic;
- signal local_ii_write : std_logic;
- signal local_ii_address : std_logic_vector(26 downto 0);
- signal local_ii_readdata : std_logic_vector(575 downto 0);
- signal local_ii_writedata : std_logic_vector(575 downto 0);
- signal local_ii_burstcount : std_logic_vector(6 downto 0);
- signal local_ii_be : std_logic_vector(71 downto 0);
- signal local_ii_read_data_valid: std_logic;
- signal mb_ii_a_internal : std_logic_vector(16 downto 0);
-
- -- signals for the transceivers
- signal tx_serial_data_front : std_logic_vector(47 downto 0);
- signal rx_serial_data_front : std_logic_vector(47 downto 0);
- signal dataloopback_front : std_logic_vector(3071 downto 0);
- signal controlloopback_front : std_logic_vector(383 downto 0);
- signal tx_serdesclk_front : std_logic_vector(47 downto 0);
- signal validloopback_front : std_logic_vector(47 downto 0);
- signal tx_analogreset_front : std_logic_vector(47 downto 0);
- signal tx_digitalreset_front : std_logic_vector(47 downto 0);
- signal rx_analogreset_front : std_logic_vector(47 downto 0);
- signal rx_digitalreset_front : std_logic_vector(47 downto 0);
- signal tx_cal_busy_front : std_logic_vector(47 downto 0);
- signal rx_cal_busy_front : std_logic_vector(47 downto 0);
- signal txpll_cal_busy_front : std_logic_vector(47 downto 0);
- signal pll_cal_busy_front : std_logic;
- signal rx_is_lockedtodata_front: std_logic_vector(47 downto 0);
- signal pll_powerdown_front : std_logic_vector(0 downto 0);
- signal pll_locked_front : std_logic_vector(0 downto 0);
- signal tx_serial_clk_front : std_logic_vector(47 downto 0);
- signal mcgb_serial_clk_front : std_logic;
-
- signal tx_serial_data_back : std_logic_vector(47 downto 0);
- signal rx_serial_data_back : std_logic_vector(47 downto 0);
- signal dataloopback_back : std_logic_vector(3071 downto 0);
- signal controlloopback_back : std_logic_vector(383 downto 0);
- signal dataloopback_test : std_logic_vector(1535 downto 0);
- signal controlloopback_test : std_logic_vector(191 downto 0);
- signal tx_serdesclk_back : std_logic_vector(47 downto 0);
- signal validloopback_back : std_logic_vector(47 downto 0);
- signal tx_analogreset_back : std_logic_vector(47 downto 0);
- signal tx_digitalreset_back : std_logic_vector(47 downto 0);
- signal rx_analogreset_back : std_logic_vector(47 downto 0);
- signal rx_digitalreset_back : std_logic_vector(47 downto 0);
- signal tx_cal_busy_back : std_logic_vector(47 downto 0);
- signal rx_cal_busy_back : std_logic_vector(47 downto 0);
- signal txpll_cal_busy_back : std_logic_vector(47 downto 0);
- signal pll_cal_busy_back_upper : std_logic;
- signal pll_cal_busy_back_lower : std_logic;
- signal rx_is_lockedtodata_back: std_logic_vector(47 downto 0);
- signal pll_powerdown_back_upper : std_logic_vector(0 downto 0);
- signal pll_powerdown_back_lower : std_logic_vector(0 downto 0);
- signal pll_locked_back_upper : std_logic_vector(0 downto 0);
- signal pll_locked_back_lower : std_logic_vector(0 downto 0);
- signal tx_serial_clk_back : std_logic_vector(47 downto 0);
- signal mcgb_serial_clk_back_upper : std_logic;
- signal mcgb_serial_clk_back_lower : std_logic;
-
- -- signals for the bidirectional and misc ios
- signal inta_in : std_logic;
- signal intb_in : std_logic;
- signal testio_in : std_logic_vector(5 downto 0);
- signal qsfp_led_in : std_logic_vector(11 downto 0);
- signal bck_err_in : std_logic_vector(2 downto 0);
- signal inta_out : std_logic;
- signal intb_out : std_logic;
- signal testio_out : std_logic_vector(5 downto 0);
- signal qsfp_led_out : std_logic_vector(11 downto 0);
- signal bck_err_out : std_logic_vector(2 downto 0);
- signal ver_id_pmbusalert : std_logic_vector(11 downto 0);
+ -- constants
+ constant cs_sim : std_logic := '0';
+ constant cs_sync : std_logic := '1';
+
+ -- general reset and clock signals
+ signal reset_n : std_logic;
+ signal reset_p : std_logic;
+ signal pout_wdi : std_logic := '0';
+ signal sys_clk : std_logic := '0';
+ signal sys_locked : std_logic := '0';
+ signal mm_clk : std_logic := '0';
+ signal clk_125 : std_logic := '0';
+ signal CLK_buffered : std_logic := '0';
+
+ -- signals for the ddr4 controllers
+ signal local_i_cal_success : std_logic;
+ signal local_i_cal_fail : std_logic;
+ signal local_i_reset_n : std_logic;
+ signal local_i_clk : std_logic;
+ signal local_i_ready : std_logic;
+ signal local_i_read : std_logic;
+ signal local_i_write : std_logic;
+ signal local_i_address : std_logic_vector(26 downto 0);
+ signal local_i_readdata : std_logic_vector(575 downto 0);
+ signal local_i_writedata : std_logic_vector(575 downto 0);
+ signal local_i_burstcount : std_logic_vector(6 downto 0);
+ signal local_i_be : std_logic_vector(71 downto 0);
+ signal local_i_read_data_valid : std_logic;
+ signal mb_i_a_internal : std_logic_vector(16 downto 0);
+ signal local_ii_cal_success : std_logic;
+ signal local_ii_cal_fail : std_logic;
+ signal local_ii_reset_n : std_logic;
+ signal local_ii_clk : std_logic;
+ signal local_ii_ready : std_logic;
+ signal local_ii_read : std_logic;
+ signal local_ii_write : std_logic;
+ signal local_ii_address : std_logic_vector(26 downto 0);
+ signal local_ii_readdata : std_logic_vector(575 downto 0);
+ signal local_ii_writedata : std_logic_vector(575 downto 0);
+ signal local_ii_burstcount : std_logic_vector(6 downto 0);
+ signal local_ii_be : std_logic_vector(71 downto 0);
+ signal local_ii_read_data_valid: std_logic;
+ signal mb_ii_a_internal : std_logic_vector(16 downto 0);
+
+ -- signals for the transceivers
+ signal tx_serial_data_front : std_logic_vector(47 downto 0);
+ signal rx_serial_data_front : std_logic_vector(47 downto 0);
+ signal dataloopback_front : std_logic_vector(3071 downto 0);
+ signal controlloopback_front : std_logic_vector(383 downto 0);
+ signal tx_serdesclk_front : std_logic_vector(47 downto 0);
+ signal validloopback_front : std_logic_vector(47 downto 0);
+ signal tx_analogreset_front : std_logic_vector(47 downto 0);
+ signal tx_digitalreset_front : std_logic_vector(47 downto 0);
+ signal rx_analogreset_front : std_logic_vector(47 downto 0);
+ signal rx_digitalreset_front : std_logic_vector(47 downto 0);
+ signal tx_cal_busy_front : std_logic_vector(47 downto 0);
+ signal rx_cal_busy_front : std_logic_vector(47 downto 0);
+ signal txpll_cal_busy_front : std_logic_vector(47 downto 0);
+ signal pll_cal_busy_front : std_logic;
+ signal rx_is_lockedtodata_front: std_logic_vector(47 downto 0);
+ signal pll_powerdown_front : std_logic_vector(0 downto 0);
+ signal pll_locked_front : std_logic_vector(0 downto 0);
+ signal tx_serial_clk_front : std_logic_vector(47 downto 0);
+ signal mcgb_serial_clk_front : std_logic;
+
+ signal tx_serial_data_back : std_logic_vector(47 downto 0);
+ signal rx_serial_data_back : std_logic_vector(47 downto 0);
+ signal dataloopback_back : std_logic_vector(3071 downto 0);
+ signal controlloopback_back : std_logic_vector(383 downto 0);
+ signal dataloopback_test : std_logic_vector(1535 downto 0);
+ signal controlloopback_test : std_logic_vector(191 downto 0);
+ signal tx_serdesclk_back : std_logic_vector(47 downto 0);
+ signal validloopback_back : std_logic_vector(47 downto 0);
+ signal tx_analogreset_back : std_logic_vector(47 downto 0);
+ signal tx_digitalreset_back : std_logic_vector(47 downto 0);
+ signal rx_analogreset_back : std_logic_vector(47 downto 0);
+ signal rx_digitalreset_back : std_logic_vector(47 downto 0);
+ signal tx_cal_busy_back : std_logic_vector(47 downto 0);
+ signal rx_cal_busy_back : std_logic_vector(47 downto 0);
+ signal txpll_cal_busy_back : std_logic_vector(47 downto 0);
+ signal pll_cal_busy_back_upper : std_logic;
+ signal pll_cal_busy_back_lower : std_logic;
+ signal rx_is_lockedtodata_back: std_logic_vector(47 downto 0);
+ signal pll_powerdown_back_upper : std_logic_vector(0 downto 0);
+ signal pll_powerdown_back_lower : std_logic_vector(0 downto 0);
+ signal pll_locked_back_upper : std_logic_vector(0 downto 0);
+ signal pll_locked_back_lower : std_logic_vector(0 downto 0);
+ signal tx_serial_clk_back : std_logic_vector(47 downto 0);
+ signal mcgb_serial_clk_back_upper : std_logic;
+ signal mcgb_serial_clk_back_lower : std_logic;
+
+ -- signals for the bidirectional and misc ios
+ signal inta_in : std_logic;
+ signal intb_in : std_logic;
+ signal testio_in : std_logic_vector(5 downto 0);
+ signal qsfp_led_in : std_logic_vector(11 downto 0);
+ signal bck_err_in : std_logic_vector(2 downto 0);
+ signal inta_out : std_logic;
+ signal intb_out : std_logic;
+ signal testio_out : std_logic_vector(5 downto 0);
+ signal qsfp_led_out : std_logic_vector(11 downto 0);
+ signal bck_err_out : std_logic_vector(2 downto 0);
+ signal ver_id_pmbusalert : std_logic_vector(11 downto 0);
begin
- WDI <= 'Z';
-
- -- ****** DDR4 memory controllers ******
-
- mb_i_a <= mb_i_a_internal(13 downto 0);
- mb_i_we_a14 <= mb_i_a_internal(14);
- mb_i_cas_a15 <= mb_i_a_internal(15);
- mb_i_ras_a16 <= mb_i_a_internal(16);
-
- local_i_proc : process(local_i_clk, local_i_reset_n)
- begin
- if local_i_reset_n = '0' then
- local_i_read <= '0';
- local_i_write <= '0';
- local_i_address <= (others => '0');
- local_i_writedata <= (others => '0');
- local_i_burstcount <= (others => '0');
- local_i_be <= (others => '0');
- else
- if local_i_clk'event and local_i_clk = '1' then
- local_i_be <= (others => '1');
- if local_i_ready = '1' then
- local_i_read <= not local_i_read;
- local_i_write <= local_i_read_data_valid;
- local_i_address <= local_i_address + 1;
- if local_i_read_data_valid = '1' then
- local_i_writedata <= not local_i_readdata;
- else
- local_i_writedata <= (others => '1');
- end if;
+ WDI <= 'Z';
+
+ -- ****** DDR4 memory controllers ******
+
+ mb_i_a <= mb_i_a_internal(13 downto 0);
+ mb_i_we_a14 <= mb_i_a_internal(14);
+ mb_i_cas_a15 <= mb_i_a_internal(15);
+ mb_i_ras_a16 <= mb_i_a_internal(16);
+
+ local_i_proc : process(local_i_clk, local_i_reset_n)
+ begin
+ if local_i_reset_n = '0' then
+ local_i_read <= '0';
+ local_i_write <= '0';
+ local_i_address <= (others => '0');
+ local_i_writedata <= (others => '0');
+ local_i_burstcount <= (others => '0');
+ local_i_be <= (others => '0');
+ else
+ if local_i_clk'event and local_i_clk = '1' then
+ local_i_be <= (others => '1');
+ if local_i_ready = '1' then
+ local_i_read <= not local_i_read;
+ local_i_write <= local_i_read_data_valid;
+ local_i_address <= local_i_address + 1;
+ if local_i_read_data_valid = '1' then
+ local_i_writedata <= not local_i_readdata;
+ else
+ local_i_writedata <= (others => '1');
end if;
- end if;
+ end if;
end if;
- end process;
-
- u_ddr4_i : ddr4
- port map (
- global_reset_n => reset_n,
- pll_ref_clk => MB_I_REF_CLK,
- oct_rzqin => MB_I_RZQ,
- mem_ck => mb_i_ck,
- mem_ck_n => mb_i_ck_n,
- mem_a => mb_i_a_internal,
- mem_act_n => mb_i_act_n,
- mem_ba => mb_i_ba,
- mem_bg => mb_i_bg,
- mem_cke => mb_i_cke,
- mem_cs_n => mb_i_cs,
- mem_odt => mb_i_odt,
- mem_reset_n => mb_i_reset_n,
- mem_alert_n => mb_i_alert_n,
- mem_par => mb_i_parity,
- mem_dqs => mb_i_dqs,
- mem_dqs_n => mb_i_dqs_n,
- mem_dq(63 downto 0) => mb_i_dq,
- mem_dq(71 downto 64) => mb_i_cb,
- mem_dbi_n => mb_i_dm,
- local_cal_success => local_i_cal_success,
- local_cal_fail => local_i_cal_fail,
- emif_usr_reset_n => local_i_reset_n,
- emif_usr_clk => local_i_clk,
- amm_ready_0 => local_i_ready,
- amm_read_0 => local_i_read,
- amm_write_0 => local_i_write,
- amm_address_0 => local_i_address,
- amm_readdata_0 => local_i_readdata,
- amm_writedata_0 => local_i_writedata,
- amm_burstcount_0 => local_i_burstcount,
- amm_byteenable_0 => local_i_be,
- amm_readdatavalid_0 => local_i_read_data_valid
- );
-
- mb_ii_a <= mb_ii_a_internal(13 downto 0);
- mb_ii_we_a14 <= mb_ii_a_internal(14);
- mb_ii_cas_a15 <= mb_ii_a_internal(15);
- mb_ii_ras_a16 <= mb_ii_a_internal(16);
-
- local_ii_proc : process(local_ii_clk, local_ii_reset_n)
- begin
- if local_ii_reset_n = '0' then
- local_ii_read <= '0';
- local_ii_write <= '0';
- local_ii_address <= (others => '0');
- local_ii_writedata <= (others => '0');
- local_ii_burstcount <= (others => '0');
- local_ii_be <= (others => '0');
- else
- if local_ii_clk'event and local_ii_clk = '1' then
- local_ii_be <= (others => '1');
- if local_ii_ready = '1' then
- local_ii_read <= not local_ii_read;
- local_ii_write <= local_ii_read_data_valid;
- local_ii_address <= local_ii_address + 1;
- if local_ii_read_data_valid = '1' then
- local_ii_writedata <= not local_ii_readdata;
- else
- local_ii_writedata <= (others => '1');
- end if;
+ end if;
+ end process;
+
+ u_ddr4_i : ddr4
+ port map (
+ global_reset_n => reset_n,
+ pll_ref_clk => MB_I_REF_CLK,
+ oct_rzqin => MB_I_RZQ,
+ mem_ck => mb_i_ck,
+ mem_ck_n => mb_i_ck_n,
+ mem_a => mb_i_a_internal,
+ mem_act_n => mb_i_act_n,
+ mem_ba => mb_i_ba,
+ mem_bg => mb_i_bg,
+ mem_cke => mb_i_cke,
+ mem_cs_n => mb_i_cs,
+ mem_odt => mb_i_odt,
+ mem_reset_n => mb_i_reset_n,
+ mem_alert_n => mb_i_alert_n,
+ mem_par => mb_i_parity,
+ mem_dqs => mb_i_dqs,
+ mem_dqs_n => mb_i_dqs_n,
+ mem_dq(63 downto 0) => mb_i_dq,
+ mem_dq(71 downto 64) => mb_i_cb,
+ mem_dbi_n => mb_i_dm,
+ local_cal_success => local_i_cal_success,
+ local_cal_fail => local_i_cal_fail,
+ emif_usr_reset_n => local_i_reset_n,
+ emif_usr_clk => local_i_clk,
+ amm_ready_0 => local_i_ready,
+ amm_read_0 => local_i_read,
+ amm_write_0 => local_i_write,
+ amm_address_0 => local_i_address,
+ amm_readdata_0 => local_i_readdata,
+ amm_writedata_0 => local_i_writedata,
+ amm_burstcount_0 => local_i_burstcount,
+ amm_byteenable_0 => local_i_be,
+ amm_readdatavalid_0 => local_i_read_data_valid
+ );
+
+ mb_ii_a <= mb_ii_a_internal(13 downto 0);
+ mb_ii_we_a14 <= mb_ii_a_internal(14);
+ mb_ii_cas_a15 <= mb_ii_a_internal(15);
+ mb_ii_ras_a16 <= mb_ii_a_internal(16);
+
+ local_ii_proc : process(local_ii_clk, local_ii_reset_n)
+ begin
+ if local_ii_reset_n = '0' then
+ local_ii_read <= '0';
+ local_ii_write <= '0';
+ local_ii_address <= (others => '0');
+ local_ii_writedata <= (others => '0');
+ local_ii_burstcount <= (others => '0');
+ local_ii_be <= (others => '0');
+ else
+ if local_ii_clk'event and local_ii_clk = '1' then
+ local_ii_be <= (others => '1');
+ if local_ii_ready = '1' then
+ local_ii_read <= not local_ii_read;
+ local_ii_write <= local_ii_read_data_valid;
+ local_ii_address <= local_ii_address + 1;
+ if local_ii_read_data_valid = '1' then
+ local_ii_writedata <= not local_ii_readdata;
+ else
+ local_ii_writedata <= (others => '1');
end if;
- end if;
+ end if;
end if;
- end process;
-
- u_ddr4_ii : ddr4
- port map (
- global_reset_n => reset_n,
- pll_ref_clk => MB_II_REF_CLK,
- oct_rzqin => MB_II_RZQ,
- mem_ck => mb_ii_ck,
- mem_ck_n => mb_ii_ck_n,
- mem_a => mb_ii_a_internal,
- mem_act_n => mb_ii_act_n,
- mem_ba => mb_ii_ba,
- mem_bg => mb_ii_bg,
- mem_cke => mb_ii_cke,
- mem_cs_n => mb_ii_cs,
- mem_odt => mb_ii_odt,
- mem_reset_n => mb_ii_reset_n,
- mem_alert_n => mb_ii_alert_n,
- mem_par => mb_ii_parity,
- mem_dqs => mb_ii_dqs,
- mem_dqs_n => mb_ii_dqs_n,
- mem_dq(63 downto 0) => mb_ii_dq,
- mem_dq(71 downto 64) => mb_ii_cb,
- mem_dbi_n => mb_ii_dm,
- local_cal_success => local_ii_cal_success,
- local_cal_fail => local_ii_cal_fail,
- emif_usr_reset_n => local_ii_reset_n,
- emif_usr_clk => local_ii_clk,
- amm_ready_0 => local_ii_ready,
- amm_read_0 => local_ii_read,
- amm_write_0 => local_ii_write,
- amm_address_0 => local_ii_address,
- amm_readdata_0 => local_ii_readdata,
- amm_writedata_0 => local_ii_writedata,
- amm_burstcount_0 => local_ii_burstcount,
- amm_byteenable_0 => local_ii_be,
- amm_readdatavalid_0 => local_ii_read_data_valid
- );
-
--- -- ****** Front side transceivers ******
---
- RING_0_TX <= tx_serial_data_front(47 downto 36);
- QSFP_0_TX <= tx_serial_data_front(35 downto 32);
- QSFP_1_TX <= tx_serial_data_front(31 downto 28);
- QSFP_2_TX <= tx_serial_data_front(27 downto 24);
- QSFP_3_TX <= tx_serial_data_front(23 downto 20);
- QSFP_4_TX <= tx_serial_data_front(19 downto 16);
- QSFP_5_TX <= tx_serial_data_front(15 downto 12);
- RING_1_TX <= tx_serial_data_front(11 downto 0);
-
- rx_serial_data_front <= RING_0_RX
+ end if;
+ end process;
+
+ u_ddr4_ii : ddr4
+ port map (
+ global_reset_n => reset_n,
+ pll_ref_clk => MB_II_REF_CLK,
+ oct_rzqin => MB_II_RZQ,
+ mem_ck => mb_ii_ck,
+ mem_ck_n => mb_ii_ck_n,
+ mem_a => mb_ii_a_internal,
+ mem_act_n => mb_ii_act_n,
+ mem_ba => mb_ii_ba,
+ mem_bg => mb_ii_bg,
+ mem_cke => mb_ii_cke,
+ mem_cs_n => mb_ii_cs,
+ mem_odt => mb_ii_odt,
+ mem_reset_n => mb_ii_reset_n,
+ mem_alert_n => mb_ii_alert_n,
+ mem_par => mb_ii_parity,
+ mem_dqs => mb_ii_dqs,
+ mem_dqs_n => mb_ii_dqs_n,
+ mem_dq(63 downto 0) => mb_ii_dq,
+ mem_dq(71 downto 64) => mb_ii_cb,
+ mem_dbi_n => mb_ii_dm,
+ local_cal_success => local_ii_cal_success,
+ local_cal_fail => local_ii_cal_fail,
+ emif_usr_reset_n => local_ii_reset_n,
+ emif_usr_clk => local_ii_clk,
+ amm_ready_0 => local_ii_ready,
+ amm_read_0 => local_ii_read,
+ amm_write_0 => local_ii_write,
+ amm_address_0 => local_ii_address,
+ amm_readdata_0 => local_ii_readdata,
+ amm_writedata_0 => local_ii_writedata,
+ amm_burstcount_0 => local_ii_burstcount,
+ amm_byteenable_0 => local_ii_be,
+ amm_readdatavalid_0 => local_ii_read_data_valid
+ );
+
+ -- -- ****** Front side transceivers ******
+ --
+ RING_0_TX <= tx_serial_data_front(47 downto 36);
+ QSFP_0_TX <= tx_serial_data_front(35 downto 32);
+ QSFP_1_TX <= tx_serial_data_front(31 downto 28);
+ QSFP_2_TX <= tx_serial_data_front(27 downto 24);
+ QSFP_3_TX <= tx_serial_data_front(23 downto 20);
+ QSFP_4_TX <= tx_serial_data_front(19 downto 16);
+ QSFP_5_TX <= tx_serial_data_front(15 downto 12);
+ RING_1_TX <= tx_serial_data_front(11 downto 0);
+
+ rx_serial_data_front <= RING_0_RX
& QSFP_0_RX & QSFP_1_RX & QSFP_2_RX & QSFP_3_RX & QSFP_4_RX & QSFP_5_RX
& RING_1_RX;
- transceiver_phy_front : transceiver_phy
- port map (
- tx_analogreset => tx_analogreset_front,
- tx_digitalreset => tx_digitalreset_front,
- rx_analogreset => rx_analogreset_front,
- rx_digitalreset => rx_digitalreset_front,
- tx_cal_busy => tx_cal_busy_front,
- rx_cal_busy => rx_cal_busy_front,
- rx_is_lockedtodata => rx_is_lockedtodata_front,
- tx_serial_clk0 => tx_serial_clk_front,
- rx_cdr_refclk0 => sa_clk,
- tx_serial_data => tx_serial_data_front,
- rx_serial_data => rx_serial_data_front,
- tx_coreclkin => tx_serdesclk_front, -- write side clock for tx fifo
- rx_coreclkin => tx_serdesclk_front,
- tx_clkout => tx_serdesclk_front,
- rx_clkout => open,
- tx_enh_data_valid => validloopback_front,
- rx_enh_data_valid => validloopback_front,
- rx_enh_blk_lock => open,
- tx_parallel_data => dataloopback_front,
- tx_control => controlloopback_front,
- tx_err_ins => (others => '0'), -- use to insert sync errors
- unused_tx_parallel_data => (others => '0'),
- unused_tx_control => (others => '0'),
- rx_parallel_data => dataloopback_front,
- rx_control => controlloopback_front,
- unused_rx_parallel_data => open,
- unused_rx_control => open
- );
-
- transceiver_reset_front : transceiver_reset_controller
- port map (
- clock => clk,
- reset => reset_p,
- pll_powerdown => pll_powerdown_front,
- tx_analogreset => tx_analogreset_front,
- tx_digitalreset => tx_digitalreset_front,
- tx_ready => open,
- pll_locked => pll_locked_front,
- pll_select => "0",
- tx_cal_busy => txpll_cal_busy_front,
- rx_analogreset => rx_analogreset_front,
- rx_digitalreset => rx_digitalreset_front,
- rx_ready => open,
- rx_is_lockedtodata => rx_is_lockedtodata_front,
- rx_cal_busy => rx_cal_busy_front
- );
-
- transceiver_pll_front : transceiver_pll
- port map (
- pll_powerdown => pll_powerdown_front(0),
- pll_refclk0 => sa_clk,
- pll_locked => pll_locked_front(0),
- pll_cal_busy => pll_cal_busy_front,
- mcgb_rst => pll_powerdown_front(0),
- mcgb_serial_clk => mcgb_serial_clk_front
- );
-
- tx_serial_clk_front <= (others => mcgb_serial_clk_front);
- txpll_cal_busy_front <= tx_cal_busy_front when pll_cal_busy_front = '0' else (others => '1');
-
- -- ****** Back side transceivers ******
- -- upper 24 transceivers use sb_clk
- -- Nov 4 - temporarily disconnect BCK_TX/RX(47) to see what gets synthesised away
-
- BCK_TX(47 downto 0) <= tx_serial_data_back(47 downto 0);
--- BCK_TX(47) <= '0';
-
- rx_serial_data_back(47 downto 0) <= BCK_RX(47 downto 0);
--- dataloopback_test <= X"0000000000000000" & dataloopback_back(3007 downto 1536);
--- controlloopback_test <= X"00" & controlloopback_back(375 downto 192);
-
- transceiver_phy_back_upper : transceiver_phy_24channel
- port map (
- tx_analogreset => tx_analogreset_back(47 downto 24),
- tx_digitalreset => tx_digitalreset_back(47 downto 24),
- rx_analogreset => rx_analogreset_back(47 downto 24),
- rx_digitalreset => rx_digitalreset_back(47 downto 24),
- tx_cal_busy => tx_cal_busy_back(47 downto 24),
- rx_cal_busy => rx_cal_busy_back(47 downto 24),
- rx_is_lockedtodata => rx_is_lockedtodata_back(47 downto 24),
- tx_serial_clk0 => tx_serial_clk_back(47 downto 24),
- rx_cdr_refclk0 => sb_clk,
- tx_serial_data => tx_serial_data_back(47 downto 24),
- rx_serial_data => rx_serial_data_back(47 downto 24),
- tx_coreclkin => tx_serdesclk_back(47 downto 24), -- write side clock for tx fifo
- rx_coreclkin => tx_serdesclk_back(47 downto 24),
- tx_clkout => tx_serdesclk_back(47 downto 24),
- rx_clkout => open,
- tx_enh_data_valid => validloopback_back(47 downto 24),
- rx_enh_data_valid => validloopback_back(47 downto 24),
- rx_enh_blk_lock => open,
- tx_parallel_data => dataloopback_back(3071 downto 1536),
- tx_control => controlloopback_back(383 downto 192),
- tx_err_ins => (others => '0'), -- use to insert sync errors
- unused_tx_parallel_data => (others => '0'),
- unused_tx_control => (others => '0'),
- rx_parallel_data => dataloopback_back(3071 downto 1536),
- rx_control => controlloopback_back(383 downto 192),
- unused_rx_parallel_data => open,
- unused_rx_control => open
- );
-
- transceiver_reset_back_upper : transceiver_reset_controller_24
- port map (
- clock => clk,
- reset => reset_p,
- pll_powerdown => pll_powerdown_back_upper,
- tx_analogreset => tx_analogreset_back(47 downto 24),
- tx_digitalreset => tx_digitalreset_back(47 downto 24),
- tx_ready => open,
- pll_locked => pll_locked_back_upper,
- pll_select => "0",
- tx_cal_busy => txpll_cal_busy_back(47 downto 24),
- rx_analogreset => rx_analogreset_back(47 downto 24),
- rx_digitalreset => rx_digitalreset_back(47 downto 24),
- rx_ready => open,
- rx_is_lockedtodata => rx_is_lockedtodata_back(47 downto 24),
- rx_cal_busy => rx_cal_busy_back(47 downto 24)
- );
-
- transceiver_pll_back_upper : transceiver_pll
- port map (
- pll_powerdown => pll_powerdown_back_upper(0),
- pll_refclk0 => sb_clk,
- pll_locked => pll_locked_back_upper(0),
- pll_cal_busy => pll_cal_busy_back_upper,
- mcgb_rst => pll_powerdown_back_upper(0),
- mcgb_serial_clk => mcgb_serial_clk_back_upper
- );
-
- tx_serial_clk_back(47 downto 24) <= (others => mcgb_serial_clk_back_upper);
- txpll_cal_busy_back(47 downto 24) <= tx_cal_busy_back(47 downto 24) when pll_cal_busy_back_upper = '0' else (others => '1');
-
- -- lower 24 transceivers use sb_clk
-
- transceiver_phy_back_lower : transceiver_phy_24channel
- port map (
- tx_analogreset => tx_analogreset_back(23 downto 0),
- tx_digitalreset => tx_digitalreset_back(23 downto 0),
- rx_analogreset => rx_analogreset_back(23 downto 0),
- rx_digitalreset => rx_digitalreset_back(23 downto 0),
- tx_cal_busy => tx_cal_busy_back(23 downto 0),
- rx_cal_busy => rx_cal_busy_back(23 downto 0),
- rx_is_lockedtodata => rx_is_lockedtodata_back(23 downto 0),
- tx_serial_clk0 => tx_serial_clk_back(23 downto 0),
- rx_cdr_refclk0 => bck_ref_clk,
- tx_serial_data => tx_serial_data_back(23 downto 0),
- rx_serial_data => rx_serial_data_back(23 downto 0),
- tx_coreclkin => tx_serdesclk_back(23 downto 0), -- write side clock for tx fifo
- rx_coreclkin => tx_serdesclk_back(23 downto 0),
- tx_clkout => tx_serdesclk_back(23 downto 0),
- rx_clkout => open,
- tx_enh_data_valid => validloopback_back(23 downto 0),
- rx_enh_data_valid => validloopback_back(23 downto 0),
- rx_enh_blk_lock => open,
- tx_parallel_data => dataloopback_back(1535 downto 0),
- tx_control => controlloopback_back(191 downto 0),
- tx_err_ins => (others => '0'), -- use to insert sync errors
- unused_tx_parallel_data => (others => '0'),
- unused_tx_control => (others => '0'),
- rx_parallel_data => dataloopback_back(1535 downto 0),
- rx_control => controlloopback_back(191 downto 0),
- unused_rx_parallel_data => open,
- unused_rx_control => open
- );
-
- transceiver_reset_back_lower : transceiver_reset_controller_24
- port map (
- clock => clk,
- reset => reset_p,
- pll_powerdown => pll_powerdown_back_lower,
- tx_analogreset => tx_analogreset_back(23 downto 0),
- tx_digitalreset => tx_digitalreset_back(23 downto 0),
- tx_ready => open,
- pll_locked => pll_locked_back_lower,
- pll_select => "0",
- tx_cal_busy => txpll_cal_busy_back(23 downto 0),
- rx_analogreset => rx_analogreset_back(23 downto 0),
- rx_digitalreset => rx_digitalreset_back(23 downto 0),
- rx_ready => open,
- rx_is_lockedtodata => rx_is_lockedtodata_back(23 downto 0),
- rx_cal_busy => rx_cal_busy_back(23 downto 0)
- );
-
- transceiver_pll_back_lower : transceiver_pll
- port map (
- pll_powerdown => pll_powerdown_back_lower(0),
- pll_refclk0 => bck_ref_clk,
- pll_locked => pll_locked_back_lower(0),
- pll_cal_busy => pll_cal_busy_back_lower,
- mcgb_rst => pll_powerdown_back_lower(0),
- mcgb_serial_clk => mcgb_serial_clk_back_lower
- );
-
- tx_serial_clk_back(23 downto 0) <= (others => mcgb_serial_clk_back_lower);
- txpll_cal_busy_back(23 downto 0) <= tx_cal_busy_back(23 downto 0) when pll_cal_busy_back_lower = '0' else (others => '1');
-
- -- ****** node control for resets and wdi
-
- u_node_ctrl : entity unb_common_lib.unb_node_ctrl
- generic map (
- g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- xo_clk => ETH_clk,
- xo_rst_n => reset_n,
- sys_clk => sys_clk,
- sys_locked => sys_locked,
- sys_rst => open,
- st_clk => clk,
- st_rst => open,
- wdi_in => pout_wdi,
- wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
- pulse_us => open,
- pulse_ms => open,
- pulse_s => open -- could be used to toggle a LED
- );
-
- reset_p <= not reset_n;
-
- u0 : component sys_clkctrl
- port map (
- inclk => CLK, -- altclkctrl_input.inclk
- outclk => CLK_buffered -- altclkctrl_output.outclk
+ transceiver_phy_front : transceiver_phy
+ port map (
+ tx_analogreset => tx_analogreset_front,
+ tx_digitalreset => tx_digitalreset_front,
+ rx_analogreset => rx_analogreset_front,
+ rx_digitalreset => rx_digitalreset_front,
+ tx_cal_busy => tx_cal_busy_front,
+ rx_cal_busy => rx_cal_busy_front,
+ rx_is_lockedtodata => rx_is_lockedtodata_front,
+ tx_serial_clk0 => tx_serial_clk_front,
+ rx_cdr_refclk0 => sa_clk,
+ tx_serial_data => tx_serial_data_front,
+ rx_serial_data => rx_serial_data_front,
+ tx_coreclkin => tx_serdesclk_front, -- write side clock for tx fifo
+ rx_coreclkin => tx_serdesclk_front,
+ tx_clkout => tx_serdesclk_front,
+ rx_clkout => open,
+ tx_enh_data_valid => validloopback_front,
+ rx_enh_data_valid => validloopback_front,
+ rx_enh_blk_lock => open,
+ tx_parallel_data => dataloopback_front,
+ tx_control => controlloopback_front,
+ tx_err_ins => (others => '0'), -- use to insert sync errors
+ unused_tx_parallel_data => (others => '0'),
+ unused_tx_control => (others => '0'),
+ rx_parallel_data => dataloopback_front,
+ rx_control => controlloopback_front,
+ unused_rx_parallel_data => open,
+ unused_rx_control => open
+ );
+
+ transceiver_reset_front : transceiver_reset_controller
+ port map (
+ clock => clk,
+ reset => reset_p,
+ pll_powerdown => pll_powerdown_front,
+ tx_analogreset => tx_analogreset_front,
+ tx_digitalreset => tx_digitalreset_front,
+ tx_ready => open,
+ pll_locked => pll_locked_front,
+ pll_select => "0",
+ tx_cal_busy => txpll_cal_busy_front,
+ rx_analogreset => rx_analogreset_front,
+ rx_digitalreset => rx_digitalreset_front,
+ rx_ready => open,
+ rx_is_lockedtodata => rx_is_lockedtodata_front,
+ rx_cal_busy => rx_cal_busy_front
+ );
+
+ transceiver_pll_front : transceiver_pll
+ port map (
+ pll_powerdown => pll_powerdown_front(0),
+ pll_refclk0 => sa_clk,
+ pll_locked => pll_locked_front(0),
+ pll_cal_busy => pll_cal_busy_front,
+ mcgb_rst => pll_powerdown_front(0),
+ mcgb_serial_clk => mcgb_serial_clk_front
+ );
+
+ tx_serial_clk_front <= (others => mcgb_serial_clk_front);
+ txpll_cal_busy_front <= tx_cal_busy_front when pll_cal_busy_front = '0' else (others => '1');
+
+ -- ****** Back side transceivers ******
+ -- upper 24 transceivers use sb_clk
+ -- Nov 4 - temporarily disconnect BCK_TX/RX(47) to see what gets synthesised away
+
+ BCK_TX(47 downto 0) <= tx_serial_data_back(47 downto 0);
+ -- BCK_TX(47) <= '0';
+
+ rx_serial_data_back(47 downto 0) <= BCK_RX(47 downto 0);
+ -- dataloopback_test <= X"0000000000000000" & dataloopback_back(3007 downto 1536);
+ -- controlloopback_test <= X"00" & controlloopback_back(375 downto 192);
+
+ transceiver_phy_back_upper : transceiver_phy_24channel
+ port map (
+ tx_analogreset => tx_analogreset_back(47 downto 24),
+ tx_digitalreset => tx_digitalreset_back(47 downto 24),
+ rx_analogreset => rx_analogreset_back(47 downto 24),
+ rx_digitalreset => rx_digitalreset_back(47 downto 24),
+ tx_cal_busy => tx_cal_busy_back(47 downto 24),
+ rx_cal_busy => rx_cal_busy_back(47 downto 24),
+ rx_is_lockedtodata => rx_is_lockedtodata_back(47 downto 24),
+ tx_serial_clk0 => tx_serial_clk_back(47 downto 24),
+ rx_cdr_refclk0 => sb_clk,
+ tx_serial_data => tx_serial_data_back(47 downto 24),
+ rx_serial_data => rx_serial_data_back(47 downto 24),
+ tx_coreclkin => tx_serdesclk_back(47 downto 24), -- write side clock for tx fifo
+ rx_coreclkin => tx_serdesclk_back(47 downto 24),
+ tx_clkout => tx_serdesclk_back(47 downto 24),
+ rx_clkout => open,
+ tx_enh_data_valid => validloopback_back(47 downto 24),
+ rx_enh_data_valid => validloopback_back(47 downto 24),
+ rx_enh_blk_lock => open,
+ tx_parallel_data => dataloopback_back(3071 downto 1536),
+ tx_control => controlloopback_back(383 downto 192),
+ tx_err_ins => (others => '0'), -- use to insert sync errors
+ unused_tx_parallel_data => (others => '0'),
+ unused_tx_control => (others => '0'),
+ rx_parallel_data => dataloopback_back(3071 downto 1536),
+ rx_control => controlloopback_back(383 downto 192),
+ unused_rx_parallel_data => open,
+ unused_rx_control => open
+ );
+
+ transceiver_reset_back_upper : transceiver_reset_controller_24
+ port map (
+ clock => clk,
+ reset => reset_p,
+ pll_powerdown => pll_powerdown_back_upper,
+ tx_analogreset => tx_analogreset_back(47 downto 24),
+ tx_digitalreset => tx_digitalreset_back(47 downto 24),
+ tx_ready => open,
+ pll_locked => pll_locked_back_upper,
+ pll_select => "0",
+ tx_cal_busy => txpll_cal_busy_back(47 downto 24),
+ rx_analogreset => rx_analogreset_back(47 downto 24),
+ rx_digitalreset => rx_digitalreset_back(47 downto 24),
+ rx_ready => open,
+ rx_is_lockedtodata => rx_is_lockedtodata_back(47 downto 24),
+ rx_cal_busy => rx_cal_busy_back(47 downto 24)
+ );
+
+ transceiver_pll_back_upper : transceiver_pll
+ port map (
+ pll_powerdown => pll_powerdown_back_upper(0),
+ pll_refclk0 => sb_clk,
+ pll_locked => pll_locked_back_upper(0),
+ pll_cal_busy => pll_cal_busy_back_upper,
+ mcgb_rst => pll_powerdown_back_upper(0),
+ mcgb_serial_clk => mcgb_serial_clk_back_upper
+ );
+
+ tx_serial_clk_back(47 downto 24) <= (others => mcgb_serial_clk_back_upper);
+ txpll_cal_busy_back(47 downto 24) <= tx_cal_busy_back(47 downto 24) when pll_cal_busy_back_upper = '0' else (others => '1');
+
+ -- lower 24 transceivers use sb_clk
+
+ transceiver_phy_back_lower : transceiver_phy_24channel
+ port map (
+ tx_analogreset => tx_analogreset_back(23 downto 0),
+ tx_digitalreset => tx_digitalreset_back(23 downto 0),
+ rx_analogreset => rx_analogreset_back(23 downto 0),
+ rx_digitalreset => rx_digitalreset_back(23 downto 0),
+ tx_cal_busy => tx_cal_busy_back(23 downto 0),
+ rx_cal_busy => rx_cal_busy_back(23 downto 0),
+ rx_is_lockedtodata => rx_is_lockedtodata_back(23 downto 0),
+ tx_serial_clk0 => tx_serial_clk_back(23 downto 0),
+ rx_cdr_refclk0 => bck_ref_clk,
+ tx_serial_data => tx_serial_data_back(23 downto 0),
+ rx_serial_data => rx_serial_data_back(23 downto 0),
+ tx_coreclkin => tx_serdesclk_back(23 downto 0), -- write side clock for tx fifo
+ rx_coreclkin => tx_serdesclk_back(23 downto 0),
+ tx_clkout => tx_serdesclk_back(23 downto 0),
+ rx_clkout => open,
+ tx_enh_data_valid => validloopback_back(23 downto 0),
+ rx_enh_data_valid => validloopback_back(23 downto 0),
+ rx_enh_blk_lock => open,
+ tx_parallel_data => dataloopback_back(1535 downto 0),
+ tx_control => controlloopback_back(191 downto 0),
+ tx_err_ins => (others => '0'), -- use to insert sync errors
+ unused_tx_parallel_data => (others => '0'),
+ unused_tx_control => (others => '0'),
+ rx_parallel_data => dataloopback_back(1535 downto 0),
+ rx_control => controlloopback_back(191 downto 0),
+ unused_rx_parallel_data => open,
+ unused_rx_control => open
+ );
+
+ transceiver_reset_back_lower : transceiver_reset_controller_24
+ port map (
+ clock => clk,
+ reset => reset_p,
+ pll_powerdown => pll_powerdown_back_lower,
+ tx_analogreset => tx_analogreset_back(23 downto 0),
+ tx_digitalreset => tx_digitalreset_back(23 downto 0),
+ tx_ready => open,
+ pll_locked => pll_locked_back_lower,
+ pll_select => "0",
+ tx_cal_busy => txpll_cal_busy_back(23 downto 0),
+ rx_analogreset => rx_analogreset_back(23 downto 0),
+ rx_digitalreset => rx_digitalreset_back(23 downto 0),
+ rx_ready => open,
+ rx_is_lockedtodata => rx_is_lockedtodata_back(23 downto 0),
+ rx_cal_busy => rx_cal_busy_back(23 downto 0)
+ );
+
+ transceiver_pll_back_lower : transceiver_pll
+ port map (
+ pll_powerdown => pll_powerdown_back_lower(0),
+ pll_refclk0 => bck_ref_clk,
+ pll_locked => pll_locked_back_lower(0),
+ pll_cal_busy => pll_cal_busy_back_lower,
+ mcgb_rst => pll_powerdown_back_lower(0),
+ mcgb_serial_clk => mcgb_serial_clk_back_lower
+ );
+
+ tx_serial_clk_back(23 downto 0) <= (others => mcgb_serial_clk_back_lower);
+ txpll_cal_busy_back(23 downto 0) <= tx_cal_busy_back(23 downto 0) when pll_cal_busy_back_lower = '0' else (others => '1');
+
+ -- ****** node control for resets and wdi
+
+ u_node_ctrl : entity unb_common_lib.unb_node_ctrl
+ generic map (
+ g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ )
+ port map (
+ xo_clk => ETH_clk,
+ xo_rst_n => reset_n,
+ sys_clk => sys_clk,
+ sys_locked => sys_locked,
+ sys_rst => open,
+ st_clk => clk,
+ st_rst => open,
+ wdi_in => pout_wdi,
+ wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
+ pulse_us => open,
+ pulse_ms => open,
+ pulse_s => open -- could be used to toggle a LED
);
- u_system_pll : system_pll
- port map(
--- refclk => ETH_CLK,
- refclk => CLK_buffered,
--- refclk => INTB,
- rst => reset_p,
- locked => sys_locked,
- outclk_0 => mm_clk, -- 100MHz
- outclk_1 => sys_clk, -- 300MHz
- outclk_2 => clk_125 -- 125MHz for 1ge
- );
-
--- u_system_pll : system_fpll
--- port map(
--- pll_refclk0 => INTB,
--- pll_powerdown => reset_p,
--- pll_locked => sys_locked,
--- pll_cal_busy => open,
--- outclk0 => mm_clk, -- 100MHz
--- outclk1 => sys_clk, -- 300MHz
--- outclk2 => clk_125 -- 125MHz for 1ge
--- );
-
- -- ****** i2c interfaces ******
-
- u_qsys : unb2_pinning_qsys
- port map (
- clk_clk => mm_clk,
- reset_reset_n => reset_n,
- avs_i2c_master_0_gs_sim_export => cs_sim,
- avs_i2c_master_0_sync_export => cs_sync,
- avs_i2c_master_0_i2c_scl_export => sens_sc,
- avs_i2c_master_0_i2c_sda_export => sens_sd,
- avs_i2c_master_1_gs_sim_export => cs_sim,
- avs_i2c_master_1_sync_export => cs_sync,
- avs_i2c_master_1_i2c_scl_export => pmbus_sc,
- avs_i2c_master_1_i2c_sda_export => pmbus_sd,
- avs_i2c_master_2_gs_sim_export => cs_sim,
- avs_i2c_master_2_sync_export => cs_sync,
- avs_i2c_master_2_i2c_scl_export => bck_scl(0),
- avs_i2c_master_2_i2c_sda_export => bck_sda(0),
- avs_i2c_master_3_gs_sim_export => cs_sim,
- avs_i2c_master_3_sync_export => cs_sync,
- avs_i2c_master_3_i2c_scl_export => bck_scl(1),
- avs_i2c_master_3_i2c_sda_export => bck_sda(1),
- avs_i2c_master_4_sync_export => cs_sync,
- avs_i2c_master_4_gs_sim_export => cs_sim,
- avs_i2c_master_4_i2c_scl_export => bck_scl(2),
- avs_i2c_master_4_i2c_sda_export => bck_sda(2),
- avs_i2c_master_5_sync_export => cs_sync,
- avs_i2c_master_5_gs_sim_export => cs_sim,
- avs_i2c_master_5_i2c_sda_export => qsfp_sda(0),
- avs_i2c_master_5_i2c_scl_export => qsfp_scl(0),
- avs_i2c_master_6_sync_export => cs_sync,
- avs_i2c_master_6_gs_sim_export => cs_sim,
- avs_i2c_master_6_i2c_sda_export => qsfp_sda(1),
- avs_i2c_master_6_i2c_scl_export => qsfp_scl(1),
- avs_i2c_master_7_sync_export => cs_sync,
- avs_i2c_master_7_gs_sim_export => cs_sim,
- avs_i2c_master_7_i2c_sda_export => qsfp_sda(2),
- avs_i2c_master_7_i2c_scl_export => qsfp_scl(2),
- avs_i2c_master_8_sync_export => cs_sync,
- avs_i2c_master_8_gs_sim_export => cs_sim,
- avs_i2c_master_8_i2c_sda_export => qsfp_sda(3),
- avs_i2c_master_8_i2c_scl_export => qsfp_scl(3),
- avs_i2c_master_9_sync_export => cs_sync,
- avs_i2c_master_9_gs_sim_export => cs_sim,
- avs_i2c_master_9_i2c_sda_export => qsfp_sda(4),
- avs_i2c_master_9_i2c_scl_export => qsfp_scl(4),
- avs_i2c_master_10_sync_export => cs_sync,
- avs_i2c_master_10_gs_sim_export => cs_sim,
- avs_i2c_master_10_i2c_sda_export => qsfp_sda(5),
- avs_i2c_master_10_i2c_scl_export => qsfp_scl(5),
- avs_i2c_master_11_sync_export => cs_sync,
- avs_i2c_master_11_gs_sim_export => cs_sim,
- avs_i2c_master_11_i2c_sda_export => mb_sda,
- avs_i2c_master_11_i2c_scl_export => mb_scl,
- eth_tse_0_serial_connection_rxp_0 => ETH_SGIN(0),
- eth_tse_0_serial_connection_txp_0 => ETH_SGOUT(0),
- --eth_tse_0_pcs_ref_clk_clock_connection_clk => clk_125,
- eth_tse_0_pcs_ref_clk_clock_connection_clk => ETH_CLK,
- --eth_tse_1_pcs_ref_clk_clock_connection_clk => clk_125,
- eth_tse_1_pcs_ref_clk_clock_connection_clk => ETH_CLK,
- eth_tse_1_serial_connection_rxp_0 => ETH_SGIN(1),
- eth_tse_1_serial_connection_txp_0 => ETH_SGOUT(1),
- pio_0_external_connection_export => ver_id_pmbusalert
- );
-
--- bidirectional and misc
--- use PPS as output enable
-
- INTA <= inta_out when PPS = '1' else 'Z';
- INTB <= intb_out when PPS = '1' else 'Z';
- TESTIO(5 downto 0) <= testio_out(5 downto 0) when PPS = '1' else "ZZZZZZ";
- QSFP_LED <= qsfp_led_out when PPS = '1' else "ZZZZZZZZZZZZ";
- BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
-
- inta_in <= INTA;
- intb_in <= INTB;
- testio_in(5 downto 0) <= TESTIO(5 downto 0);
- qsfp_led_in <= QSFP_LED;
- bck_err_in <= BCK_ERR;
-
- inta_out <= intb_in;
- intb_out <= inta_in;
- testio_out(5 downto 3) <= testio_in(2 downto 0);
- testio_out(2 downto 0) <= testio_in(5 downto 3);
- qsfp_led_out(11 downto 6) <= qsfp_led_in(5 downto 0);
- qsfp_led_out(5 downto 0) <= qsfp_led_in(11 downto 6);
- bck_err_out(2) <= bck_err_in(1);
- bck_err_out(1) <= bck_err_in(0);
- bck_err_out(0) <= bck_err_in(2);
-
- ver_id_pmbusalert <= version & id & pmbus_alert & mb_event;
+ reset_p <= not reset_n;
+
+ u0 : component sys_clkctrl
+ port map (
+ inclk => CLK, -- altclkctrl_input.inclk
+ outclk => CLK_buffered -- altclkctrl_output.outclk
+ );
+
+ u_system_pll : system_pll
+ port map(
+ -- refclk => ETH_CLK,
+ refclk => CLK_buffered,
+ -- refclk => INTB,
+ rst => reset_p,
+ locked => sys_locked,
+ outclk_0 => mm_clk, -- 100MHz
+ outclk_1 => sys_clk, -- 300MHz
+ outclk_2 => clk_125 -- 125MHz for 1ge
+ );
+
+ -- u_system_pll : system_fpll
+ -- port map(
+ -- pll_refclk0 => INTB,
+ -- pll_powerdown => reset_p,
+ -- pll_locked => sys_locked,
+ -- pll_cal_busy => open,
+ -- outclk0 => mm_clk, -- 100MHz
+ -- outclk1 => sys_clk, -- 300MHz
+ -- outclk2 => clk_125 -- 125MHz for 1ge
+ -- );
+
+ -- ****** i2c interfaces ******
+
+ u_qsys : unb2_pinning_qsys
+ port map (
+ clk_clk => mm_clk,
+ reset_reset_n => reset_n,
+ avs_i2c_master_0_gs_sim_export => cs_sim,
+ avs_i2c_master_0_sync_export => cs_sync,
+ avs_i2c_master_0_i2c_scl_export => sens_sc,
+ avs_i2c_master_0_i2c_sda_export => sens_sd,
+ avs_i2c_master_1_gs_sim_export => cs_sim,
+ avs_i2c_master_1_sync_export => cs_sync,
+ avs_i2c_master_1_i2c_scl_export => pmbus_sc,
+ avs_i2c_master_1_i2c_sda_export => pmbus_sd,
+ avs_i2c_master_2_gs_sim_export => cs_sim,
+ avs_i2c_master_2_sync_export => cs_sync,
+ avs_i2c_master_2_i2c_scl_export => bck_scl(0),
+ avs_i2c_master_2_i2c_sda_export => bck_sda(0),
+ avs_i2c_master_3_gs_sim_export => cs_sim,
+ avs_i2c_master_3_sync_export => cs_sync,
+ avs_i2c_master_3_i2c_scl_export => bck_scl(1),
+ avs_i2c_master_3_i2c_sda_export => bck_sda(1),
+ avs_i2c_master_4_sync_export => cs_sync,
+ avs_i2c_master_4_gs_sim_export => cs_sim,
+ avs_i2c_master_4_i2c_scl_export => bck_scl(2),
+ avs_i2c_master_4_i2c_sda_export => bck_sda(2),
+ avs_i2c_master_5_sync_export => cs_sync,
+ avs_i2c_master_5_gs_sim_export => cs_sim,
+ avs_i2c_master_5_i2c_sda_export => qsfp_sda(0),
+ avs_i2c_master_5_i2c_scl_export => qsfp_scl(0),
+ avs_i2c_master_6_sync_export => cs_sync,
+ avs_i2c_master_6_gs_sim_export => cs_sim,
+ avs_i2c_master_6_i2c_sda_export => qsfp_sda(1),
+ avs_i2c_master_6_i2c_scl_export => qsfp_scl(1),
+ avs_i2c_master_7_sync_export => cs_sync,
+ avs_i2c_master_7_gs_sim_export => cs_sim,
+ avs_i2c_master_7_i2c_sda_export => qsfp_sda(2),
+ avs_i2c_master_7_i2c_scl_export => qsfp_scl(2),
+ avs_i2c_master_8_sync_export => cs_sync,
+ avs_i2c_master_8_gs_sim_export => cs_sim,
+ avs_i2c_master_8_i2c_sda_export => qsfp_sda(3),
+ avs_i2c_master_8_i2c_scl_export => qsfp_scl(3),
+ avs_i2c_master_9_sync_export => cs_sync,
+ avs_i2c_master_9_gs_sim_export => cs_sim,
+ avs_i2c_master_9_i2c_sda_export => qsfp_sda(4),
+ avs_i2c_master_9_i2c_scl_export => qsfp_scl(4),
+ avs_i2c_master_10_sync_export => cs_sync,
+ avs_i2c_master_10_gs_sim_export => cs_sim,
+ avs_i2c_master_10_i2c_sda_export => qsfp_sda(5),
+ avs_i2c_master_10_i2c_scl_export => qsfp_scl(5),
+ avs_i2c_master_11_sync_export => cs_sync,
+ avs_i2c_master_11_gs_sim_export => cs_sim,
+ avs_i2c_master_11_i2c_sda_export => mb_sda,
+ avs_i2c_master_11_i2c_scl_export => mb_scl,
+ eth_tse_0_serial_connection_rxp_0 => ETH_SGIN(0),
+ eth_tse_0_serial_connection_txp_0 => ETH_SGOUT(0),
+ --eth_tse_0_pcs_ref_clk_clock_connection_clk => clk_125,
+ eth_tse_0_pcs_ref_clk_clock_connection_clk => ETH_CLK,
+ --eth_tse_1_pcs_ref_clk_clock_connection_clk => clk_125,
+ eth_tse_1_pcs_ref_clk_clock_connection_clk => ETH_CLK,
+ eth_tse_1_serial_connection_rxp_0 => ETH_SGIN(1),
+ eth_tse_1_serial_connection_txp_0 => ETH_SGOUT(1),
+ pio_0_external_connection_export => ver_id_pmbusalert
+ );
+
+ -- bidirectional and misc
+ -- use PPS as output enable
+
+ INTA <= inta_out when PPS = '1' else 'Z';
+ INTB <= intb_out when PPS = '1' else 'Z';
+ TESTIO(5 downto 0) <= testio_out(5 downto 0) when PPS = '1' else "ZZZZZZ";
+ QSFP_LED <= qsfp_led_out when PPS = '1' else "ZZZZZZZZZZZZ";
+ BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
+
+ inta_in <= INTA;
+ intb_in <= INTB;
+ testio_in(5 downto 0) <= TESTIO(5 downto 0);
+ qsfp_led_in <= QSFP_LED;
+ bck_err_in <= BCK_ERR;
+
+ inta_out <= intb_in;
+ intb_out <= inta_in;
+ testio_out(5 downto 3) <= testio_in(2 downto 0);
+ testio_out(2 downto 0) <= testio_in(5 downto 3);
+ qsfp_led_out(11 downto 6) <= qsfp_led_in(5 downto 0);
+ qsfp_led_out(5 downto 0) <= qsfp_led_in(11 downto 6);
+ bck_err_out(2) <= bck_err_in(1);
+ bck_err_out(1) <= bck_err_in(0);
+ bck_err_out(0) <= bck_err_in(2);
+
+ ver_id_pmbusalert <= version & id & pmbus_alert & mb_event;
end str;
diff --git a/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd b/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
index 8f346a6f27..f99c071326 100644
--- a/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
+++ b/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, unb_common_lib;
-use unb_common_lib.unb_common_pkg.all;
-use IEEE.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use unb_common_lib.unb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity unb2_singlemac is
port (
@@ -47,54 +47,54 @@ entity unb2_singlemac is
BCK_REF_CLK : in std_logic; -- SerDes reference clock back
-- SO-DIMM DDR4 Memory Bank i2c (common)
--- MB_SCL : inout std_logic;
--- MB_SDA : inout std_logic;
+ -- MB_SCL : inout std_logic;
+ -- MB_SDA : inout std_logic;
-- SO-DIMM DDR4 Memory Bank I
--- MB_I_RZQ : in STD_LOGIC;
--- MB_I_REF_CLK : in STD_LOGIC; -- External reference clock
--- MB_I_A : out std_logic_vector (13 downto 0);
--- MB_I_ACT_N : out std_logic_vector(0 downto 0);
--- MB_I_BA : out std_logic_vector (1 downto 0);
--- MB_I_BG : out std_logic_vector (1 downto 0);
--- MB_I_CAS_A15 : out std_logic;
--- MB_I_CB : inout std_logic_vector (7 downto 0);
--- MB_I_CK : out std_logic_vector (1 downto 0);
--- MB_I_CK_n : out std_logic_vector (1 downto 0);
--- MB_I_CKE : out std_logic_vector (1 downto 0);
--- MB_I_CS : out std_logic_vector (1 downto 0);
--- MB_I_DM : inout std_logic_vector (8 downto 0);
--- MB_I_DQ : inout std_logic_vector (63 downto 0);
--- MB_I_DQS : inout std_logic_vector (8 downto 0);
--- MB_I_DQS_n : inout std_logic_vector (8 downto 0);
--- MB_I_ODT : out std_logic_vector (1 downto 0);
--- MB_I_PARITY : out std_logic_vector(0 downto 0);
--- MB_I_RAS_A16 : out std_logic;
--- MB_I_WE_A14 : out std_logic;
--- MB_I_RESET_N : out std_logic_vector(0 downto 0);
--- MB_I_ALERT_N : in std_logic_vector(0 downto 0);
+ -- MB_I_RZQ : in STD_LOGIC;
+ -- MB_I_REF_CLK : in STD_LOGIC; -- External reference clock
+ -- MB_I_A : out std_logic_vector (13 downto 0);
+ -- MB_I_ACT_N : out std_logic_vector(0 downto 0);
+ -- MB_I_BA : out std_logic_vector (1 downto 0);
+ -- MB_I_BG : out std_logic_vector (1 downto 0);
+ -- MB_I_CAS_A15 : out std_logic;
+ -- MB_I_CB : inout std_logic_vector (7 downto 0);
+ -- MB_I_CK : out std_logic_vector (1 downto 0);
+ -- MB_I_CK_n : out std_logic_vector (1 downto 0);
+ -- MB_I_CKE : out std_logic_vector (1 downto 0);
+ -- MB_I_CS : out std_logic_vector (1 downto 0);
+ -- MB_I_DM : inout std_logic_vector (8 downto 0);
+ -- MB_I_DQ : inout std_logic_vector (63 downto 0);
+ -- MB_I_DQS : inout std_logic_vector (8 downto 0);
+ -- MB_I_DQS_n : inout std_logic_vector (8 downto 0);
+ -- MB_I_ODT : out std_logic_vector (1 downto 0);
+ -- MB_I_PARITY : out std_logic_vector(0 downto 0);
+ -- MB_I_RAS_A16 : out std_logic;
+ -- MB_I_WE_A14 : out std_logic;
+ -- MB_I_RESET_N : out std_logic_vector(0 downto 0);
+ -- MB_I_ALERT_N : in std_logic_vector(0 downto 0);
-- SO-DIMM DDR4 Memory Bank II
--- MB_II_RZQ : in STD_LOGIC;
--- MB_II_REF_CLK : in STD_LOGIC; -- External reference clock
--- MB_II_A : out std_logic_vector (13 downto 0);
--- MB_II_ACT_N : out std_logic_vector(0 downto 0);
--- MB_II_BA : out std_logic_vector (1 downto 0);
--- MB_II_BG : out std_logic_vector (1 downto 0);
--- MB_II_CAS_A15 : out std_logic;
--- MB_II_CB : inout std_logic_vector (7 downto 0);
--- MB_II_CK : out std_logic_vector (1 downto 0);
--- MB_II_CK_n : out std_logic_vector (1 downto 0);
--- MB_II_CKE : out std_logic_vector (1 downto 0);
--- MB_II_CS : out std_logic_vector (1 downto 0);
--- MB_II_DM : inout std_logic_vector (8 downto 0);
--- MB_II_DQ : inout std_logic_vector (63 downto 0);
--- MB_II_DQS : inout std_logic_vector (8 downto 0);
--- MB_II_DQS_n : inout std_logic_vector (8 downto 0);
--- MB_II_ODT : out std_logic_vector (1 downto 0);
--- MB_II_PARITY : out std_logic_vector(0 downto 0);
--- MB_II_RAS_A16 : out std_logic;
--- MB_II_WE_A14 : out std_logic;
--- MB_II_RESET_N : out std_logic_vector(0 downto 0);
--- MB_II_ALERT_N : in std_logic_vector(0 downto 0);
+ -- MB_II_RZQ : in STD_LOGIC;
+ -- MB_II_REF_CLK : in STD_LOGIC; -- External reference clock
+ -- MB_II_A : out std_logic_vector (13 downto 0);
+ -- MB_II_ACT_N : out std_logic_vector(0 downto 0);
+ -- MB_II_BA : out std_logic_vector (1 downto 0);
+ -- MB_II_BG : out std_logic_vector (1 downto 0);
+ -- MB_II_CAS_A15 : out std_logic;
+ -- MB_II_CB : inout std_logic_vector (7 downto 0);
+ -- MB_II_CK : out std_logic_vector (1 downto 0);
+ -- MB_II_CK_n : out std_logic_vector (1 downto 0);
+ -- MB_II_CKE : out std_logic_vector (1 downto 0);
+ -- MB_II_CS : out std_logic_vector (1 downto 0);
+ -- MB_II_DM : inout std_logic_vector (8 downto 0);
+ -- MB_II_DQ : inout std_logic_vector (63 downto 0);
+ -- MB_II_DQS : inout std_logic_vector (8 downto 0);
+ -- MB_II_DQS_n : inout std_logic_vector (8 downto 0);
+ -- MB_II_ODT : out std_logic_vector (1 downto 0);
+ -- MB_II_PARITY : out std_logic_vector(0 downto 0);
+ -- MB_II_RAS_A16 : out std_logic;
+ -- MB_II_WE_A14 : out std_logic;
+ -- MB_II_RESET_N : out std_logic_vector(0 downto 0);
+ -- MB_II_ALERT_N : in std_logic_vector(0 downto 0);
-- back transceivers
BCK_SDA : inout std_logic_vector(2 downto 0);
@@ -113,8 +113,8 @@ entity unb2_singlemac is
-- I2C Interface to Sensors
SENS_SC : inout std_logic;
SENS_SD : inout std_logic;
- -- Others
--- CFG_DATA : inout std_logic_vector (3 downto 0);
+ -- Others
+ -- CFG_DATA : inout std_logic_vector (3 downto 0);
VERSION : in std_logic_vector(1 downto 0);
ID : in std_logic_vector(7 downto 0);
TESTIO : inout std_logic_vector(5 downto 0);
@@ -123,15 +123,15 @@ entity unb2_singlemac is
end unb2_singlemac;
architecture str of unb2_singlemac is
- component system_iopll is
- port (
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X';
- locked : out std_logic;
- outclk_0 : out std_logic; -- outclk0
- outclk_1 : out std_logic; -- outclk1
- outclk_2 : out std_logic -- outclk2
- );
+ component system_iopll is
+ port (
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X';
+ locked : out std_logic;
+ outclk_0 : out std_logic; -- outclk0
+ outclk_1 : out std_logic; -- outclk1
+ outclk_2 : out std_logic -- outclk2
+ );
end component system_iopll;
component tech_transceiver_arria10_1 is
@@ -196,85 +196,85 @@ architecture str of unb2_singlemac is
);
end component ip_arria10_mac_10g;
- -- constants
- constant cs_sim : std_logic := '0';
- constant cs_sync : std_logic := '1';
- --CONSTANT c_block_len : NATURAL := 180; -- = 1440 user bytes. Including packetizing: 1508 bytes.
- constant c_block_len : natural := 1118; -- = 8944 user bytes. Including packetizing: 9012 bytes.
+ -- constants
+ constant cs_sim : std_logic := '0';
+ constant cs_sync : std_logic := '1';
+ --CONSTANT c_block_len : NATURAL := 180; -- = 1440 user bytes. Including packetizing: 1508 bytes.
+ constant c_block_len : natural := 1118; -- = 8944 user bytes. Including packetizing: 9012 bytes.
- -- general reset and clock signals
- signal reset_n : std_logic := '0';
- signal reset_p : std_logic := '0';
- signal pout_wdi : std_logic := '0';
- signal sys_clk : std_logic := '0';
- signal sys_locked : std_logic := '0';
- signal mm_clk : std_logic := '0';
- signal clk_125 : std_logic := '0';
+ -- general reset and clock signals
+ signal reset_n : std_logic := '0';
+ signal reset_p : std_logic := '0';
+ signal pout_wdi : std_logic := '0';
+ signal sys_clk : std_logic := '0';
+ signal sys_locked : std_logic := '0';
+ signal mm_clk : std_logic := '0';
+ signal clk_125 : std_logic := '0';
- -- signals for the transceivers
- signal tx_serial_data_front : std_logic_vector(0 downto 0);
- signal rx_serial_data_front : std_logic_vector(0 downto 0);
- signal xgmii_tx : std_logic_vector(71 downto 0);
- signal xgmii_rx : std_logic_vector(71 downto 0);
- signal clk_156 : std_logic_vector(0 downto 0);
- signal clk_312 : std_logic_vector(0 downto 0);
+ -- signals for the transceivers
+ signal tx_serial_data_front : std_logic_vector(0 downto 0);
+ signal rx_serial_data_front : std_logic_vector(0 downto 0);
+ signal xgmii_tx : std_logic_vector(71 downto 0);
+ signal xgmii_rx : std_logic_vector(71 downto 0);
+ signal clk_156 : std_logic_vector(0 downto 0);
+ signal clk_312 : std_logic_vector(0 downto 0);
- -- signals for the MAC
- signal mac_10g_loopback_sop : std_logic;
- signal mac_10g_loopback_eop : std_logic;
- signal mac_10g_loopback_valid : std_logic;
- signal mac_10g_loopback_ready : std_logic;
- signal mac_10g_loopback_data : std_logic_vector(63 downto 0);
- signal mac_10g_loopback_empty : std_logic_vector(2 downto 0);
- signal mac_10g_loopback_err : std_logic_vector(5 downto 0);
+ -- signals for the MAC
+ signal mac_10g_loopback_sop : std_logic;
+ signal mac_10g_loopback_eop : std_logic;
+ signal mac_10g_loopback_valid : std_logic;
+ signal mac_10g_loopback_ready : std_logic;
+ signal mac_10g_loopback_data : std_logic_vector(63 downto 0);
+ signal mac_10g_loopback_empty : std_logic_vector(2 downto 0);
+ signal mac_10g_loopback_err : std_logic_vector(5 downto 0);
- signal reg_mac_rd : std_logic;
- signal reg_mac_wr : std_logic;
- signal reg_mac_waitrequest : std_logic;
- signal reg_mac_rddata : std_logic_vector(31 downto 0);
- signal reg_mac_wrdata : std_logic_vector(31 downto 0);
- signal reg_mac_address : std_logic_vector(12 downto 0);
+ signal reg_mac_rd : std_logic;
+ signal reg_mac_wr : std_logic;
+ signal reg_mac_waitrequest : std_logic;
+ signal reg_mac_rddata : std_logic_vector(31 downto 0);
+ signal reg_mac_wrdata : std_logic_vector(31 downto 0);
+ signal reg_mac_address : std_logic_vector(12 downto 0);
- -- signals for the bidirectional and misc ios
- signal inta_in : std_logic;
- signal intb_in : std_logic;
- signal testio_in : std_logic_vector(5 downto 0);
- signal qsfp_led_in : std_logic_vector(11 downto 0);
- signal bck_err_in : std_logic_vector(2 downto 0);
- signal inta_out : std_logic;
- signal intb_out : std_logic;
- signal testio_out : std_logic_vector(5 downto 0);
- signal qsfp_led_out : std_logic_vector(11 downto 0);
- signal bck_err_out : std_logic_vector(2 downto 0);
- signal ver_id_pmbusalert : std_logic_vector(10 downto 0);
- signal toggle_count : std_logic_vector(31 downto 0);
- signal toggle_count1 : std_logic_vector(31 downto 0);
- signal led_state : std_logic;
+ -- signals for the bidirectional and misc ios
+ signal inta_in : std_logic;
+ signal intb_in : std_logic;
+ signal testio_in : std_logic_vector(5 downto 0);
+ signal qsfp_led_in : std_logic_vector(11 downto 0);
+ signal bck_err_in : std_logic_vector(2 downto 0);
+ signal inta_out : std_logic;
+ signal intb_out : std_logic;
+ signal testio_out : std_logic_vector(5 downto 0);
+ signal qsfp_led_out : std_logic_vector(11 downto 0);
+ signal bck_err_out : std_logic_vector(2 downto 0);
+ signal ver_id_pmbusalert : std_logic_vector(10 downto 0);
+ signal toggle_count : std_logic_vector(31 downto 0);
+ signal toggle_count1 : std_logic_vector(31 downto 0);
+ signal led_state : std_logic;
begin
- WDI <= 'Z';
+ WDI <= 'Z';
--- -- ****** Front side transceivers and MAC ******
---
- QSFP_0_TX <= tx_serial_data_front;
- rx_serial_data_front <= QSFP_0_RX;
+ -- -- ****** Front side transceivers and MAC ******
+ --
+ QSFP_0_TX <= tx_serial_data_front;
+ rx_serial_data_front <= QSFP_0_RX;
- u_transceiver: tech_transceiver_arria10_1
- generic map (
- g_nof_channels => 1
- )
- port map(
- clk => mm_clk,
- reset_p => reset_p,
- refclk => SA_CLK,
- clk_156_arr => clk_156,
- clk_312_arr => clk_312,
- tx_serial_data => tx_serial_data_front,
- rx_serial_data => rx_serial_data_front,
- tx_parallel_data => xgmii_tx(63 downto 0),
- rx_parallel_data => xgmii_rx(63 downto 0),
- tx_control => xgmii_tx(71 downto 64),
- rx_control => xgmii_rx(71 downto 64)
- );
+ u_transceiver: tech_transceiver_arria10_1
+ generic map (
+ g_nof_channels => 1
+ )
+ port map(
+ clk => mm_clk,
+ reset_p => reset_p,
+ refclk => SA_CLK,
+ clk_156_arr => clk_156,
+ clk_312_arr => clk_312,
+ tx_serial_data => tx_serial_data_front,
+ rx_serial_data => rx_serial_data_front,
+ tx_parallel_data => xgmii_tx(63 downto 0),
+ rx_parallel_data => xgmii_rx(63 downto 0),
+ tx_control => xgmii_tx(71 downto 64),
+ rx_control => xgmii_rx(71 downto 64)
+ );
u0 : ip_arria10_mac_10g
port map (
@@ -318,96 +318,96 @@ begin
avalon_st_rxstatus_error => open
);
- -- ****** node control for resets and wdi
+ -- ****** node control for resets and wdi
- u_node_ctrl : entity unb_common_lib.unb_node_ctrl
- generic map (
- g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- xo_clk => ETH_clk,
- xo_rst_n => reset_n,
- sys_clk => sys_clk,
- sys_locked => sys_locked,
- sys_rst => open,
- st_clk => clk,
- st_rst => open,
- wdi_in => pout_wdi,
- wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
- pulse_us => open,
- pulse_ms => open,
- pulse_s => open -- could be used to toggle a LED
- );
+ u_node_ctrl : entity unb_common_lib.unb_node_ctrl
+ generic map (
+ g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ )
+ port map (
+ xo_clk => ETH_clk,
+ xo_rst_n => reset_n,
+ sys_clk => sys_clk,
+ sys_locked => sys_locked,
+ sys_rst => open,
+ st_clk => clk,
+ st_rst => open,
+ wdi_in => pout_wdi,
+ wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
+ pulse_us => open,
+ pulse_ms => open,
+ pulse_s => open -- could be used to toggle a LED
+ );
- reset_p <= not reset_n;
+ reset_p <= not reset_n;
- u_system_pll : system_iopll
- port map(
- refclk => ETH_CLK,
- rst => reset_p,
- locked => sys_locked,
- outclk_0 => mm_clk, -- 100MHz
- outclk_1 => sys_clk, -- 300MHz
- outclk_2 => clk_125 -- 125MHz for 1ge
- );
+ u_system_pll : system_iopll
+ port map(
+ refclk => ETH_CLK,
+ rst => reset_p,
+ locked => sys_locked,
+ outclk_0 => mm_clk, -- 100MHz
+ outclk_1 => sys_clk, -- 300MHz
+ outclk_2 => clk_125 -- 125MHz for 1ge
+ );
--- bidirectional and misc
--- use PPS as output enable
+ -- bidirectional and misc
+ -- use PPS as output enable
- INTA <= inta_out when PPS = '1' else 'Z';
- INTB <= intb_out when PPS = '1' else 'Z';
- TESTIO <= testio_out;
- QSFP_LED <= qsfp_led_out;
- BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
+ INTA <= inta_out when PPS = '1' else 'Z';
+ INTB <= intb_out when PPS = '1' else 'Z';
+ TESTIO <= testio_out;
+ QSFP_LED <= qsfp_led_out;
+ BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
- inta_in <= INTA;
- intb_in <= INTB;
- testio_in <= TESTIO;
- qsfp_led_in <= QSFP_LED;
- bck_err_in <= BCK_ERR;
+ inta_in <= INTA;
+ intb_in <= INTB;
+ testio_in <= TESTIO;
+ qsfp_led_in <= QSFP_LED;
+ bck_err_in <= BCK_ERR;
- inta_out <= intb_in;
- intb_out <= inta_in;
- testio_out(5 downto 3) <= (others => '0');
- testio_out(0) <= CLK;
- testio_out(1) <= mm_clk;
--- qsfp_led_out(11 downto 6) <= qsfp_led_in(5 downto 0);
--- qsfp_led_out(5 downto 0) <= qsfp_led_in(11 downto 6);
- qsfp_led_out(11 downto 6) <= (others => led_state);
- qsfp_led_out(5 downto 0) <= (others => not led_state);
- bck_err_out(2) <= bck_err_in(1);
- bck_err_out(1) <= bck_err_in(0);
- bck_err_out(0) <= bck_err_in(2);
+ inta_out <= intb_in;
+ intb_out <= inta_in;
+ testio_out(5 downto 3) <= (others => '0');
+ testio_out(0) <= CLK;
+ testio_out(1) <= mm_clk;
+ -- qsfp_led_out(11 downto 6) <= qsfp_led_in(5 downto 0);
+ -- qsfp_led_out(5 downto 0) <= qsfp_led_in(11 downto 6);
+ qsfp_led_out(11 downto 6) <= (others => led_state);
+ qsfp_led_out(5 downto 0) <= (others => not led_state);
+ bck_err_out(2) <= bck_err_in(1);
+ bck_err_out(1) <= bck_err_in(0);
+ bck_err_out(0) <= bck_err_in(2);
- ver_id_pmbusalert <= version & id & pmbus_alert;
+ ver_id_pmbusalert <= version & id & pmbus_alert;
- toggle_led_proc: process(mm_clk, reset_p)
- begin
- if reset_p = '1' then
- toggle_count <= (others => '0');
- led_state <= '0';
- else
- if mm_clk'event and mm_clk = '1' then
- if (toggle_count < 100000000) then
- toggle_count <= toggle_count + 1;
- else
- toggle_count <= (others => '0');
- led_state <= not led_state;
- end if;
+ toggle_led_proc: process(mm_clk, reset_p)
+ begin
+ if reset_p = '1' then
+ toggle_count <= (others => '0');
+ led_state <= '0';
+ else
+ if mm_clk'event and mm_clk = '1' then
+ if (toggle_count < 100000000) then
+ toggle_count <= toggle_count + 1;
+ else
+ toggle_count <= (others => '0');
+ led_state <= not led_state;
end if;
end if;
- end process;
+ end if;
+ end process;
- toggle_led_proc1: process(clk)
- begin
- if clk'event and clk = '1' then
- if (toggle_count1 < 100000000) then
- toggle_count1 <= toggle_count1 + 1;
- else
- toggle_count1 <= (others => '0');
- testio_out(2) <= not testio_out(2);
- pout_wdi <= not pout_wdi;
- end if;
+ toggle_led_proc1: process(clk)
+ begin
+ if clk'event and clk = '1' then
+ if (toggle_count1 < 100000000) then
+ toggle_count1 <= toggle_count1 + 1;
+ else
+ toggle_count1 <= (others => '0');
+ testio_out(2) <= not testio_out(2);
+ pout_wdi <= not pout_wdi;
end if;
- end process;
+ end if;
+ end process;
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
index aa7c4a89fa..8df414c185 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_10GbE is
end tb_unb2_test_10GbE;
@@ -29,7 +29,7 @@ end tb_unb2_test_10GbE;
architecture tb of tb_unb2_test_10GbE is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_10GbE"
- );
+ generic map (
+ g_design_name => "unb2_test_10GbE"
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
index 3fbb7d4604..329ae0ed68 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_test_10GbE is
generic (
@@ -66,20 +66,20 @@ entity unb2_test_10GbE is
BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
--- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
+ -- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
- -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -109,78 +109,78 @@ end unb2_test_10GbE;
architecture str of unb2_test_10GbE is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
-
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
index 3d56ebd96f..2f4a8c358d 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_1GbE is
end tb_unb2_test_1GbE;
@@ -29,7 +29,7 @@ end tb_unb2_test_1GbE;
architecture tb of tb_unb2_test_1GbE is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_1GbE"
- );
+ generic map (
+ g_design_name => "unb2_test_1GbE"
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
index d80b47e0e2..80bdf307c8 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_test_1GbE is
generic (
@@ -71,42 +71,42 @@ end unb2_test_1GbE;
architecture str of unb2_test_1GbE is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
index d1b4f650ee..719d918f42 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_all is
end tb_unb2_test_all;
@@ -29,8 +29,8 @@ end tb_unb2_test_all;
architecture tb of tb_unb2_test_all is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_all",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2_test_all",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
index 2eaf164405..f79c418ebc 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2_test_all is
generic (
@@ -71,17 +71,17 @@ entity unb2_test_all is
MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
--- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -120,91 +120,91 @@ end unb2_test_all;
architecture str of unb2_test_all is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
index 2c4a69008f..5b72bdddbf 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_ddr_MB_I is
end tb_unb2_test_ddr_MB_I;
@@ -29,8 +29,8 @@ end tb_unb2_test_ddr_MB_I;
architecture tb of tb_unb2_test_ddr_MB_I is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_ddr_MB_I",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2_test_ddr_MB_I",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
index 2443e9f95a..d952390c8e 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2_test_ddr_MB_I is
generic (
@@ -80,50 +80,50 @@ end unb2_test_ddr_MB_I;
architecture str of unb2_test_ddr_MB_I is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
index 35969d021c..f3cefb9401 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_ddr_MB_II is
end tb_unb2_test_ddr_MB_II;
@@ -29,8 +29,8 @@ end tb_unb2_test_ddr_MB_II;
architecture tb of tb_unb2_test_ddr_MB_II is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_ddr_MB_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2_test_ddr_MB_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
index 13039a84e0..6b05fda99d 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2_test_ddr_MB_II is
generic (
@@ -80,50 +80,50 @@ end unb2_test_ddr_MB_II;
architecture str of unb2_test_ddr_MB_II is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
index f7b56945a1..024fe1a14d 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_ddr_MB_I_II is
end tb_unb2_test_ddr_MB_I_II;
@@ -29,8 +29,8 @@ end tb_unb2_test_ddr_MB_I_II;
architecture tb of tb_unb2_test_ddr_MB_I_II is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_ddr_MB_I_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2_test_ddr_MB_I_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
index 9680fc8e5d..7360169310 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2_test_ddr_MB_I_II is
generic (
@@ -86,56 +86,56 @@ end unb2_test_ddr_MB_I_II;
architecture str of unb2_test_ddr_MB_I_II is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index 0e6ff5436b..2217df8e52 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use unb2_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb2_test_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
-use work.unb2_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use unb2_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb2_test_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use work.unb2_test_pkg.all;
entity mmm_unb2_test is
generic (
@@ -234,16 +234,16 @@ architecture str of mmm_unb2_test is
constant c_ram_diag_databuffer_ddr_addr_w : natural := ceil_log2(2 * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
--- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
--- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
---
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
---
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
+ -- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
-- tr_10GbE
constant c_reg_tr_10GbE_adr_w : natural := func_tech_mac_10g_csr_addr_w(g_technology);
@@ -284,110 +284,149 @@ begin
eth1g_eth0_mm_rst <= mm_rst;
eth1g_eth1_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
-
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
-
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
-
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
-
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
-
- u_mm_file_reg_fpga_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_SENS")
- port map(mm_rst, mm_clk, reg_fpga_sens_mosi, reg_fpga_sens_miso );
-
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-
- u_mm_file_reg_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
- u_mm_file_ram_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
- u_mm_file_reg_diag_tx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
-
- u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
- u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
- u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
-
--- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
---
--- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
---
--- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
-
- u_mm_file_reg_bsn_monitor_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
- u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
- u_mm_file_ram_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
- u_mm_file_reg_diag_rx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
- u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
- u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
-
- u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
-
- u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+
+ u_mm_file_reg_fpga_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_sens_mosi, reg_fpga_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ u_mm_file_reg_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+ u_mm_file_ram_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
+ u_mm_file_reg_diag_tx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
+
+ u_mm_file_reg_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+ u_mm_file_ram_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+ u_mm_file_reg_diag_tx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+
+ -- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+ --
+ -- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
+ --
+ -- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
+
+ u_mm_file_reg_bsn_monitor_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
+ u_mm_file_reg_bsn_monitor_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
+ u_mm_file_ram_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
+ u_mm_file_reg_diag_rx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+ u_mm_file_ram_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+ u_mm_file_reg_diag_rx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+
+ u_mm_file_reg_io_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+ u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+ u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+ u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+ u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_reg_io_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+ u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+ u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+ u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+ u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
- u_mm_file_reg_eth1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
-
- u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
- port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
- u_mm_file_reg_tr_10GbE_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
- u_mm_file_reg_tr_10GbE_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
-
- u_mm_file_reg_eth10g_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
- port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
- u_mm_file_reg_eth10g_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
- port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
- u_mm_file_reg_eth10g_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
- port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
+ u_mm_file_reg_eth0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
+ u_mm_file_reg_eth1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
+ port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
+
+ u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
+ u_mm_file_reg_tr_10GbE_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
+ u_mm_file_reg_tr_10GbE_back1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
+
+ u_mm_file_reg_eth10g_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
+ u_mm_file_reg_eth10g_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
+ port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
+ u_mm_file_reg_eth10g_back1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
+ port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -412,10 +451,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_eth0_reg_mosi, i_eth1g_eth0_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
- else
- eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
- end if;
+ eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
+ else
+ eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -635,32 +674,32 @@ begin
reg_eth10g_back1_read_export => reg_eth10g_back1_mosi.rd,
reg_eth10g_back1_readdata_export => reg_eth10g_back1_miso.rddata(c_word_w - 1 downto 0),
--- -- the_reg_dp_offload_tx_1GbE
--- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
--- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
--- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_tx_1GbE_hdr_dat
--- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_rx_1GbE_hdr_dat
--- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- -- the_reg_dp_offload_tx_1GbE
+ -- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_tx_1GbE_hdr_dat
+ -- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_rx_1GbE_hdr_dat
+ -- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_1gbe_reset_export => OPEN,
reg_bsn_monitor_1gbe_clk_export => OPEN,
@@ -758,21 +797,21 @@ begin
reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 3db6393627..b5445c60a4 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2_test_pkg is
-----------------------------------------------------------------------------
@@ -28,354 +28,354 @@ package qsys_unb2_test_pkg is
-- $HDL_WORK/build/unb2/quartus/unb2_test_ddr/qsys_unb2_test/sim/qsys_unb2_test.vhd
-----------------------------------------------------------------------------
- component qsys_unb2_test is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_clk_export : out std_logic; -- export
- avs_eth_1_irq_export : in std_logic := 'X'; -- export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_ram_read_export : out std_logic; -- export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_ram_write_export : out std_logic; -- export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_1_reg_read_export : out std_logic; -- export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_reg_write_export : out std_logic; -- export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_reset_export : out std_logic; -- export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_tse_read_export : out std_logic; -- export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_1_tse_write_export : out std_logic; -- export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- export
- ram_diag_bg_1gbe_read_export : out std_logic; -- export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- export
- ram_diag_bg_1gbe_write_export : out std_logic; -- export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- export
- reg_diag_bg_1gbe_read_export : out std_logic; -- export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- export
- reg_diag_bg_1gbe_write_export : out std_logic; -- export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back0_clk_export : out std_logic; -- export
- reg_eth10g_back0_read_export : out std_logic; -- export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back0_reset_export : out std_logic; -- export
- reg_eth10g_back0_write_export : out std_logic; -- export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back1_clk_export : out std_logic; -- export
- reg_eth10g_back1_read_export : out std_logic; -- export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back1_reset_export : out std_logic; -- export
- reg_eth10g_back1_write_export : out std_logic; -- export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_sens_clk_export : out std_logic; -- export
- reg_fpga_sens_read_export : out std_logic; -- export
- reg_fpga_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_sens_reset_export : out std_logic; -- export
- reg_fpga_sens_write_export : out std_logic; -- export
- reg_fpga_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- export
- reg_tr_10gbe_back0_read_export : out std_logic; -- export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back0_write_export : out std_logic; -- export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- export
- reg_tr_10gbe_back1_read_export : out std_logic; -- export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back1_write_export : out std_logic; -- export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(2 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
- );
- end component qsys_unb2_test;
+ component qsys_unb2_test is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_clk_export : out std_logic; -- export
+ avs_eth_1_irq_export : in std_logic := 'X'; -- export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_ram_read_export : out std_logic; -- export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_ram_write_export : out std_logic; -- export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_1_reg_read_export : out std_logic; -- export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_reg_write_export : out std_logic; -- export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reset_export : out std_logic; -- export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_tse_read_export : out std_logic; -- export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_1_tse_write_export : out std_logic; -- export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back0_clk_export : out std_logic; -- export
+ reg_eth10g_back0_read_export : out std_logic; -- export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back0_reset_export : out std_logic; -- export
+ reg_eth10g_back0_write_export : out std_logic; -- export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back1_clk_export : out std_logic; -- export
+ reg_eth10g_back1_read_export : out std_logic; -- export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back1_reset_export : out std_logic; -- export
+ reg_eth10g_back1_write_export : out std_logic; -- export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_sens_clk_export : out std_logic; -- export
+ reg_fpga_sens_read_export : out std_logic; -- export
+ reg_fpga_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_sens_reset_export : out std_logic; -- export
+ reg_fpga_sens_write_export : out std_logic; -- export
+ reg_fpga_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2_test;
end qsys_unb2_test_pkg;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
index b025b45615..2397132b5d 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, unb2_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb2_test_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb2_test_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity udp_stream is
generic (
@@ -102,14 +102,15 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable (disabled by default)
+ '0', -- enable_sync
+ TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
constant c_nof_crc_words : natural := 1;
constant c_max_nof_words_per_block : natural := g_bg_block_size;
@@ -150,127 +151,127 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl,
- g_use_tx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl,
+ g_use_tx_seq => true
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
- --reg_mosi => reg_dp_offload_tx_mosi,
- --reg_miso => reg_dp_offload_tx_miso,
- --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ --reg_mosi => reg_dp_offload_tx_mosi,
+ --reg_miso => reg_dp_offload_tx_miso,
+ --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
@@ -291,51 +292,51 @@ begin
end generate;
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index a4e2c262f8..4ef22fb0e7 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb2_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb2_test_pkg.all;
entity unb2_test is
generic (
@@ -315,10 +315,10 @@ architecture str of unb2_test is
signal i_QSFP_TX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
signal i_QSFP_RX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
- -- SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
signal serial_10G_tx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0) := (others => '0');
signal serial_10G_rx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0);
@@ -351,13 +351,13 @@ architecture str of unb2_test is
signal reg_diag_tx_seq_10GbE_mosi : t_mem_mosi;
signal reg_diag_tx_seq_10GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
---
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
+ --
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
signal reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
signal reg_bsn_monitor_1GbE_miso : t_mem_miso;
@@ -433,382 +433,382 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_udp_offload => c_use_1GbE,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- --g_tse_clk_buf => TRUE,
- g_dp_clk_use_pll => true,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
-
- ext_clk200 => ext_clk200,
- ext_rst200 => ext_rst200,
-
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_mm_rst => eth1g_eth0_mm_rst,
- eth1g_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_tse_miso => eth1g_eth0_tse_miso,
- eth1g_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_reg_miso => eth1g_eth0_reg_miso,
- eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_udp_offload => c_use_1GbE,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ --g_tse_clk_buf => TRUE,
+ g_dp_clk_use_pll => true,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+
+ ext_clk200 => ext_clk200,
+ ext_rst200 => ext_rst200,
+
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_technology => g_technology,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr,
- g_nof_streams_1GbE => c_unb2_board_nof_eth,
- g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
- g_nof_streams_ring => 24, -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
- g_nof_streams_back0 => 24, -- c_unb2_board_tr_back.bus_w,
- g_nof_streams_back1 => 24 -- c_unb2_board_tr_back.bus_w
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_sens_miso => reg_fpga_temp_sens_miso, -- FIXME:
- --reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- --reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- --reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- --reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
- eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
- eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
- eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g ch1
- eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
- eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
- eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
- eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
- eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
- eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
- eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
- eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- block gen
- ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
- reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
- reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
-
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
--- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
---
--- -- dp_offload_rx
--- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-
- -- bsn
- reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
-
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- 10GbE
- reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
-
- reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
- reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
-
- reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
- reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
-
- -- eth10g status
- reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
-
- reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_back0_miso => reg_eth10g_back0_miso,
-
- reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
- reg_eth10g_back1_miso => reg_eth10g_back1_miso,
-
- -- DDR4 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR4 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
- );
-
- gen_udp_stream_1GbE : if c_use_1GbE = true generate
- u_udp_stream_1GbE : entity work.udp_stream
generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_1GbE,
- g_data_w => c_data_w_32,
- g_bg_block_size => c_def_1GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_1GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_1GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => true
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_technology => g_technology,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_nof_streams_1GbE => c_unb2_board_nof_eth,
+ g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
+ g_nof_streams_ring => 24, -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
+ g_nof_streams_back0 => 24, -- c_unb2_board_tr_back.bus_w,
+ g_nof_streams_back1 => 24 -- c_unb2_board_tr_back.bus_w
)
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_sens_miso => reg_fpga_temp_sens_miso, -- FIXME:
+ --reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ --reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ --reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ --reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g ch1
+ eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
+ eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
+ eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
+ eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
+ eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
+ eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
+ eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
+ eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- block gen
+ ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
+
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-- dp_offload_tx
--- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
-
- -- dp_offload_rx
--- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+ -- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ --
+ -- -- dp_offload_rx
+ -- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
+
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- 10GbE
+ reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
+
+ reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
+ reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
+
+ reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
+ reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
+
+ -- eth10g status
+ reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
+
+ reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_back0_miso => reg_eth10g_back0_miso,
+
+ reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
+ reg_eth10g_back1_miso => reg_eth10g_back1_miso,
+
+ -- DDR4 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR4 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
+
+ gen_udp_stream_1GbE : if c_use_1GbE = true generate
+ u_udp_stream_1GbE : entity work.udp_stream
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_1GbE,
+ g_data_w => c_data_w_32,
+ g_bg_block_size => c_def_1GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_1GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_1GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+
+ -- dp_offload_tx
+ -- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+
+ -- dp_offload_rx
+ -- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ );
end generate;
-----------------------------------------------------------------------------
@@ -825,80 +825,80 @@ begin
gen_udp_stream_10GbE : if c_use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_bg_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ID => ID,
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
-
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ID => ID,
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
u_tr_10GbE_qsfp_and_ring: entity unb2_board_10gbe_lib.unb2_board_10gbe -- QSFP and Ring lines
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk => SA_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
- reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
-
- serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
- serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SA_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+ reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+
+ serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
+ serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
+ );
gen_qsfp_wires: for i in 0 to c_nof_streams_qsfp - 1 generate
- serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
+ serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
@@ -917,163 +917,163 @@ begin
QSFP_5_TX <= i_QSFP_TX(5);
u_front_io : entity unb2_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_qsfp_arr,
- serial_rx_arr => serial_10G_rx_qsfp_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
-
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
-
- --QSFP_SDA => QSFP_SDA,
- --QSFP_SCL => QSFP_SCL,
- --QSFP_RST => QSFP_RST,
-
- QSFP_LED => QSFP_LED
- );
-
--- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
--- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
--- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
--- END GENERATE;
---
--- i_RING_RX(0) <= RING_0_RX;
--- i_RING_RX(1) <= RING_1_RX;
--- RING_0_TX <= i_RING_TX(0);
--- RING_1_TX <= i_RING_TX(1);
---
--- u_ring_io : ENTITY unb2_board_lib.unb2_board_ring_io
--- GENERIC MAP (
--- g_nof_ring_bus => 2--c_nof_ring_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_ring_arr,
--- serial_rx_arr => serial_10G_rx_ring_arr,
--- RING_RX => i_RING_RX,
--- RING_TX => i_RING_TX
--- );
-
--- u_tr_10GbE_back: ENTITY unb2_board_10gbe_lib.unb2_board_10gbe -- BACK lines
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_sim_level => 1,
--- g_technology => g_technology,
--- g_nof_macs => c_nof_streams_back0,
--- g_tx_fifo_fill => c_def_10GbE_block_size,
--- g_tx_fifo_size => c_def_10GbE_block_size*2
--- )
--- PORT MAP (
--- tr_ref_clk => SB_CLK,
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
--- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
--- reg_mac_miso => reg_tr_10GbE_back0_miso,
--- reg_eth10g_mosi => reg_eth10g_back0_mosi,
--- reg_eth10g_miso => reg_eth10g_back0_miso,
--- dp_rst => dp_rst,
--- dp_clk => dp_clk,
---
--- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
----- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
---
--- serial_tx_arr => i_serial_10G_tx_back0_arr,
--- serial_rx_arr => i_serial_10G_rx_back0_arr
--- );
---
--- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
--- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
--- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
--- END GENERATE;
--- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
--- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
--- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
--- --END GENERATE;
---
--- u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
--- GENERIC MAP (
--- g_nof_back_bus => c_nof_back_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_back_arr,
--- serial_rx_arr => serial_10G_rx_back_arr,
---
--- -- Serial I/O
--- -- back transceivers
--- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
--- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
--- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
--- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
---
--- BCK_SDA => BCK_SDA,
--- BCK_SCL => BCK_SCL,
--- BCK_ERR => BCK_ERR
--- );
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_qsfp_arr,
+ serial_rx_arr => serial_10G_rx_qsfp_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
+
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
+
+ --QSFP_SDA => QSFP_SDA,
+ --QSFP_SCL => QSFP_SCL,
+ --QSFP_RST => QSFP_RST,
+
+ QSFP_LED => QSFP_LED
+ );
+
+ -- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
+ -- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
+ -- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
+ -- END GENERATE;
+ --
+ -- i_RING_RX(0) <= RING_0_RX;
+ -- i_RING_RX(1) <= RING_1_RX;
+ -- RING_0_TX <= i_RING_TX(0);
+ -- RING_1_TX <= i_RING_TX(1);
+ --
+ -- u_ring_io : ENTITY unb2_board_lib.unb2_board_ring_io
+ -- GENERIC MAP (
+ -- g_nof_ring_bus => 2--c_nof_ring_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_ring_arr,
+ -- serial_rx_arr => serial_10G_rx_ring_arr,
+ -- RING_RX => i_RING_RX,
+ -- RING_TX => i_RING_TX
+ -- );
+
+ -- u_tr_10GbE_back: ENTITY unb2_board_10gbe_lib.unb2_board_10gbe -- BACK lines
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_sim_level => 1,
+ -- g_technology => g_technology,
+ -- g_nof_macs => c_nof_streams_back0,
+ -- g_tx_fifo_fill => c_def_10GbE_block_size,
+ -- g_tx_fifo_size => c_def_10GbE_block_size*2
+ -- )
+ -- PORT MAP (
+ -- tr_ref_clk => SB_CLK,
+ -- mm_rst => mm_rst,
+ -- mm_clk => mm_clk,
+ -- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
+ -- reg_mac_miso => reg_tr_10GbE_back0_miso,
+ -- reg_eth10g_mosi => reg_eth10g_back0_mosi,
+ -- reg_eth10g_miso => reg_eth10g_back0_miso,
+ -- dp_rst => dp_rst,
+ -- dp_clk => dp_clk,
+ --
+ -- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ ---- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ --
+ -- serial_tx_arr => i_serial_10G_tx_back0_arr,
+ -- serial_rx_arr => i_serial_10G_rx_back0_arr
+ -- );
+ --
+ -- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
+ -- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
+ -- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
+ -- END GENERATE;
+ -- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
+ -- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
+ -- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
+ -- --END GENERATE;
+ --
+ -- u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
+ -- GENERIC MAP (
+ -- g_nof_back_bus => c_nof_back_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_back_arr,
+ -- serial_rx_arr => serial_10G_rx_back_arr,
+ --
+ -- -- Serial I/O
+ -- -- back transceivers
+ -- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
+ -- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
+ -- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ -- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ --
+ -- BCK_SDA => BCK_SDA,
+ -- BCK_SCL => BCK_SCL,
+ -- BCK_ERR => BCK_ERR
+ -- );
u_front_led : entity unb2_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
-
- tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
- tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
- rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
- --green_led_arr => qsfp_green_led_arr(2-1 DOWNTO 0),
- --red_led_arr => qsfp_red_led_arr(2-1 DOWNTO 0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+
+ tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
+ rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ --green_led_arr => qsfp_green_led_arr(2-1 DOWNTO 0),
+ --red_led_arr => qsfp_red_led_arr(2-1 DOWNTO 0)
+ );
end generate;
gen_no_udp_stream_10GbE : if c_use_10GbE = false generate
u_front_io : entity unb2_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_front_led : entity unb2_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
end generate;
-----------------------------------------------------------------------------
@@ -1084,156 +1084,156 @@ begin
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_I,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_I_clk200,
- ctlr_rst_out => ddr_I_rst200,
-
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_I,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_I_clk200,
+ ctlr_rst_out => ddr_I_rst200,
+
+ ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
gen_stream_MB_II : if c_use_MB_II = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_II,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_II_REF_CLK,
- ctlr_ref_rst => mb_II_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_II_clk200,
- ctlr_rst_out => ddr_II_rst200,
-
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_II_IN,
- phy4_io => MB_II_IO,
- phy4_ou => MB_II_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_II,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_II_REF_CLK,
+ ctlr_ref_rst => mb_II_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_II_clk200,
+ ctlr_rst_out => ddr_II_rst200,
+
+ ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_II_IN,
+ phy4_io => MB_II_IO,
+ phy4_ou => MB_II_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
end str;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
index da3fbc3dc0..8f4cbd0d56 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
@@ -20,37 +20,38 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
package unb2_test_pkg is
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
+ constant c_hdr_field_arr : t_common_field_arr(
+ c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
diff --git a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
index 3fca57d0e8..f4c6b21171 100644
--- a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
@@ -43,14 +43,14 @@
--
library IEEE, common_lib, unb2_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb2_test is
generic (
@@ -182,142 +182,142 @@ begin
-- DUT
------------------------------------------------------------------------------
u_unb2_test : entity work.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_sim_model_ddr => g_sim_model_ddr,
- g_ddr_MB_I => c_ddr_MB_I,
- g_ddr_MB_II => c_ddr_MB_II
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => sa_clk,
- SB_CLK => sb_clk,
- BCK_REF_CLK => bck_ref_clk,
-
- -- DDR reference clocks
- MB_I_REF_CLK => mb_I_ref_clk,
- MB_II_REF_CLK => mb_II_ref_clk,
-
- PMBUS_ALERT => '0',
-
- -- Serial I/O
- QSFP_0_TX => si_lpbk_0,
- QSFP_0_RX => si_lpbk_0,
- QSFP_1_TX => si_lpbk_1,
- QSFP_1_RX => si_lpbk_1,
- QSFP_2_TX => si_lpbk_2,
- QSFP_2_RX => si_lpbk_2,
- QSFP_3_TX => si_lpbk_3,
- QSFP_3_RX => si_lpbk_3,
- QSFP_4_TX => si_lpbk_4,
- QSFP_4_RX => si_lpbk_4,
- QSFP_5_TX => si_lpbk_5,
- QSFP_5_RX => si_lpbk_5,
---
--- RING_0_TX => si_lpbk_6,
--- RING_0_RX => si_lpbk_6,
--- RING_1_TX => si_lpbk_7,
--- RING_1_RX => si_lpbk_7,
---
--- BCK_TX => si_lpbk_8,
--- BCK_RX => si_lpbk_8,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- -- Leds
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_ddr_MB_I => c_ddr_MB_I,
+ g_ddr_MB_II => c_ddr_MB_II
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+ SB_CLK => sb_clk,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => mb_I_ref_clk,
+ MB_II_REF_CLK => mb_II_ref_clk,
+
+ PMBUS_ALERT => '0',
+
+ -- Serial I/O
+ QSFP_0_TX => si_lpbk_0,
+ QSFP_0_RX => si_lpbk_0,
+ QSFP_1_TX => si_lpbk_1,
+ QSFP_1_RX => si_lpbk_1,
+ QSFP_2_TX => si_lpbk_2,
+ QSFP_2_RX => si_lpbk_2,
+ QSFP_3_TX => si_lpbk_3,
+ QSFP_3_RX => si_lpbk_3,
+ QSFP_4_TX => si_lpbk_4,
+ QSFP_4_RX => si_lpbk_4,
+ QSFP_5_TX => si_lpbk_5,
+ QSFP_5_RX => si_lpbk_5,
+ --
+ -- RING_0_TX => si_lpbk_6,
+ -- RING_0_RX => si_lpbk_6,
+ -- RING_1_TX => si_lpbk_7,
+ -- RING_1_RX => si_lpbk_7,
+ --
+ -- BCK_TX => si_lpbk_8,
+ -- BCK_RX => si_lpbk_8,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ -- Leds
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- UniBoard sensors
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
------------------------------------------------------------------------------
-- UniBoard DDR4
------------------------------------------------------------------------------
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_I
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_I_OU,
- mem4_io => MB_I_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_I
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_I_OU,
+ mem4_io => MB_I_IO
+ );
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_II
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_II_OU,
- mem4_io => MB_II_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_II
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_II_OU,
+ mem4_io => MB_II_IO
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index 8a4c6bd89a..fedd73215a 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -25,16 +25,16 @@
-- . ctrl_unb2_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
library IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb2_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb2_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb2_board is
generic (
@@ -315,15 +315,15 @@ begin
i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
u_common_areset_ext : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_ext_clk200,
- out_rst => ext_rst200
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_ext_clk200,
+ out_rst => ext_rst200
+ );
-----------------------------------------------------------------------------
-- xo_ethclk = ETH_CLK
@@ -332,15 +332,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
-- MB_I_REF_CLK --> mb_I_ref_rst
@@ -348,26 +348,26 @@ begin
-----------------------------------------------------------------------------
u_common_areset_mb_I : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_I_REF_CLK,
- out_rst => mb_I_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_I_REF_CLK,
+ out_rst => mb_I_ref_rst
+ );
u_common_areset_mb_II : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_II_REF_CLK,
- out_rst => mb_II_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_II_REF_CLK,
+ out_rst => mb_II_ref_rst
+ );
-----------------------------------------------------------------------------
-- dp_clk
@@ -378,46 +378,46 @@ begin
dp_clk <= i_ext_clk200;
u_common_areset_st : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
+ );
end generate;
gen_dp_clk_hardware: if g_sim = false generate
gen_pll: if g_dp_clk_use_pll = true generate
u_unb2_board_clk200_pll : entity work.unb2_board_clk200_pll
- generic map (
- g_technology => g_technology,
- g_use_fpll => true,
- g_clk200_phase_shift => g_dp_clk_phase
- )
- port map (
- arst => i_mm_rst,
- clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => dp_rst
- );
+ generic map (
+ g_technology => g_technology,
+ g_use_fpll => true,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ port map (
+ arst => i_mm_rst,
+ clk200 => i_ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => dp_rst
+ );
end generate;
no_pll: if g_dp_clk_use_pll = false generate
dp_clk <= i_ext_clk200;
u_common_areset_st : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
+ );
end generate;
end generate;
@@ -434,48 +434,48 @@ begin
clk50; -- default
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
- mm_sim_clk <= not mm_sim_clk after 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
- mm_locked <= '0', '1' after 70 ns;
+ epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
+ clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
+ mm_sim_clk <= not mm_sim_clk after 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2_board_clk125_pll : entity work.unb2_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => epcs_clk,
+ c1_clk50 => clk50,
+ c2_clk100 => clk100,
+ c3_clk125 => clk125,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2_board_node_ctrl : entity work.unb2_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c0_clk20 => epcs_clk,
- c1_clk50 => clk50,
- c2_clk100 => clk100,
- c3_clk125 => clk125,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2_board_node_ctrl : entity work.unb2_board_node_ctrl
- generic map (
- g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-----------------------------------------------------------------------------
-- System info
@@ -483,33 +483,33 @@ begin
cs_sim <= is_true(g_sim);
u_mms_unb2_board_system_info : entity work.mms_unb2_board_system_info
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
-- Red LED control
@@ -544,12 +544,12 @@ begin
led_toggle_green <= sel_a_b(g_factory_image = false, led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
-- WDI override
@@ -560,15 +560,15 @@ begin
WDI <= mm_wdi or temp_alarm or wdi_override;
u_unb2_board_wdi_reg : entity work.unb2_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
-- Remote upgrade
@@ -577,73 +577,73 @@ begin
-- So there is full control over the memory mapped registers to set start address of the flash
-- and reconfigure from that address.
u_mms_remu: entity remu_lib.mms_remu
- generic map (
- g_technology => g_technology
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
-------------------------------------------------------------------------------
---- EPCS
-------------------------------------------------------------------------------
u_mms_epcs: entity epcs_lib.mms_epcs
- generic map (
- g_technology => g_technology,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
------------------------------------------------------------------------------
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_technology => g_technology,
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => dp_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => dp_pps
+ );
------------------------------------------------------------------------------
-- I2C control for UniBoard sensors
@@ -652,69 +652,69 @@ begin
mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_ms; -- speed up in simulation
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_clk_freq => g_mm_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_sens_mosi,
- reg_miso => reg_unb_sens_miso,
-
- -- i2c bus
- scl => SENS_SC,
- sda => SENS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_clk_freq => g_mm_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_sens_mosi,
+ reg_miso => reg_unb_sens_miso,
+
+ -- i2c bus
+ scl => SENS_SC,
+ sda => SENS_SD
+ );
u_mms_unb2_board_pmbus : entity work.mms_unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_pmbus => true,
- g_clk_freq => 8 * 10**6 -- I2C bus run at ~300kHz @ mm_clk=50MHz
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_pmbus_mosi,
- reg_miso => reg_unb_pmbus_miso,
-
- -- i2c bus
- scl => PMBUS_SC,
- sda => PMBUS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_pmbus => true,
+ g_clk_freq => 8 * 10**6 -- I2C bus run at ~300kHz @ mm_clk=50MHz
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_pmbus_mosi,
+ reg_miso => reg_unb_pmbus_miso,
+
+ -- i2c bus
+ scl => PMBUS_SC,
+ sda => PMBUS_SD
+ );
u_mms_unb2_fpga_sens : entity work.mms_unb2_fpga_sens
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
- mm_start => '1', -- this works
-
- -- Memory-mapped clock domain
- reg_temp_mosi => reg_fpga_temp_sens_mosi,
- reg_temp_miso => reg_fpga_temp_sens_miso,
- reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
- reg_voltage_miso => reg_fpga_voltage_sens_miso,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
+ mm_start => '1', -- this works
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
-- Ethernet 1GbE
@@ -723,18 +723,18 @@ begin
gen_tse_clk_buf: if g_tse_clk_buf = true generate
-- Separate clkbuf for the 1GbE tse_clk:
u_tse_clk_buf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => i_xo_ethclk,
- outclk => i_tse_clk
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => i_xo_ethclk,
+ outclk => i_tse_clk
+ );
end generate;
gen_tse_no_clk_buf: if g_tse_clk_buf = false generate
- i_tse_clk <= i_xo_ethclk;
+ i_tse_clk <= i_xo_ethclk;
end generate;
wire_udp_offload: for i in 0 to g_udp_offload_nof_streams - 1 generate
@@ -759,43 +759,43 @@ begin
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
u_eth : entity eth_lib.eth
- generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_frm_discard_en => true
- )
- port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT(0),
- eth_rxp => ETH_SGIN(0),
-
- -- LED interface
- tse_led => eth1g_led
- );
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_frm_discard_en => true
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => i_mm_clk, -- use mm_clk direct
+ eth_clk => i_tse_clk, -- 125 MHz clock
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT(0),
+ eth_rxp => ETH_SGIN(0),
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
end generate;
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
index f8a10253cf..17f15224b6 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
@@ -23,10 +23,10 @@
-- Description: See unb2_board_sens.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_unb2_board_sens is
generic (
@@ -64,47 +64,47 @@ architecture str of mms_unb2_board_sens is
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
begin
u_unb2_board_sens_reg : entity work.unb2_board_sens_reg
- generic map (
- g_sens_nof_result => c_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_sens_nof_result => c_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers
- sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- sens_data => sens_data,
+ -- MM registers
+ sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ sens_data => sens_data,
- -- Max temp threshold
- temp_high => temp_high
- );
+ -- Max temp threshold
+ temp_high => temp_high
+ );
u_unb2_board_sens : entity work.unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_pmbus => g_pmbus,
- g_clk_freq => g_clk_freq,
- g_temp_high => g_temp_high,
- g_sens_nof_result => c_sens_nof_result
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
- start => mm_start,
- -- i2c bus
- scl => scl,
- sda => sda,
- -- read results
- sens_evt => OPEN,
- sens_err => sens_err,
- sens_data => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_pmbus => g_pmbus,
+ g_clk_freq => g_clk_freq,
+ g_temp_high => g_temp_high,
+ g_sens_nof_result => c_sens_nof_result
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+ start => mm_start,
+ -- i2c bus
+ scl => scl,
+ sda => sda,
+ -- read results
+ sens_evt => OPEN,
+ sens_err => sens_err,
+ sens_data => sens_data
+ );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
index 8116249508..05d923ed82 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2_board_system_info is
generic (
@@ -58,7 +58,7 @@ entity mms_unb2_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb2_board_system_info;
architecture str of mms_unb2_board_system_info is
@@ -68,68 +68,69 @@ architecture str of mms_unb2_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/";
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb2_board_system_info: entity work.unb2_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb2_board_system_info_reg: entity work.unb2_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_technology => g_technology,
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
index 9697e2b7f1..a9515f45db 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -23,11 +23,11 @@
-- Description: See unb2_fpga_sens.vhd
library IEEE, technology_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2_fpga_sens is
generic (
@@ -62,51 +62,51 @@ architecture str of mms_unb2_fpga_sens is
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
begin
u_unb2_fpga_sens_reg : entity work.unb2_fpga_sens_reg
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_sens_nof_result => c_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- start => mm_start,
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_sens_nof_result => c_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ start => mm_start,
- -- Memory Mapped Slave in mm_clk domain
- sla_temp_in => reg_temp_mosi,
- sla_temp_out => reg_temp_miso,
- sla_voltage_in => reg_voltage_mosi,
- sla_voltage_out => reg_voltage_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_temp_in => reg_temp_mosi,
+ sla_temp_out => reg_temp_miso,
+ sla_voltage_in => reg_voltage_mosi,
+ sla_voltage_out => reg_voltage_miso,
- -- MM registers
- --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- --sens_data => sens_data,
+ -- MM registers
+ --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ --sens_data => sens_data,
- -- Max temp threshold
- temp_high => temp_high
- );
+ -- Max temp threshold
+ temp_high => temp_high
+ );
--- u_unb2_board_sens : ENTITY work.unb2_board_sens
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_clk_freq => g_clk_freq,
--- g_temp_high => g_temp_high,
--- g_sens_nof_result => c_sens_nof_result
--- )
--- PORT MAP (
--- clk => mm_clk,
--- rst => mm_rst,
--- start => mm_start,
--- -- i2c bus
--- scl => scl,
--- sda => sda,
--- -- read results
--- sens_evt => OPEN,
--- sens_err => sens_err,
--- sens_data => sens_data
--- );
+ -- u_unb2_board_sens : ENTITY work.unb2_board_sens
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_clk_freq => g_clk_freq,
+ -- g_temp_high => g_temp_high,
+ -- g_sens_nof_result => c_sens_nof_result
+ -- )
+ -- PORT MAP (
+ -- clk => mm_clk,
+ -- rst => mm_rst,
+ -- start => mm_start,
+ -- -- i2c bus
+ -- scl => scl,
+ -- sda => sda,
+ -- -- read results
+ -- sens_evt => OPEN,
+ -- sens_err => sens_err,
+ -- sens_data => sens_data
+ -- );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
index 9210abec47..2a38884034 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_back_io is
generic (
@@ -57,4 +57,4 @@ begin
serial_rx_arr(i * c_unb2_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
-end;
+ end;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
index 48fad46da5..26484a4d0b 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
@@ -21,17 +21,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Purpose: PLL for UniBoard node CLK input @ 125 MHz
--- Description:
--- c0 = 20 MHz
--- c1 = 50 MHz
--- c2 = 100 MHz
--- c3 = 125 MHz
---
+ -- Purpose: PLL for UniBoard node CLK input @ 125 MHz
+ -- Description:
+ -- c0 = 20 MHz
+ -- c1 = 50 MHz
+ -- c2 = 100 MHz
+ -- c3 = 125 MHz
+ --
entity unb2_board_clk125_pll is
generic (
@@ -60,46 +60,46 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk125,
- outclk => clk125buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk125,
+ outclk => clk125buf
+ );
end generate;
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
gen_fractional_pll : if g_use_fpll = true generate
u_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
end arria10;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
index 9ca4ebe75e..1b5a3d7c4a 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
@@ -21,74 +21,74 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Purpose: PLL for UniBoard node CLK input @ 200 MHz
--- Description:
--- . The PLL runs in normal mode using c0 to compensate for the internal clock
--- network delay, so that c0 = st_clk200 is aligned to the input clk200.
--- . The assumption is that default the streaming DSP will run on the 200 MHz
--- clock from the CLK input via c1 = st_clk200p.
--- . The PLL normal mode operation compensates for internal clock network
--- delays of c0. This compensations aligns c0 to inclk0. With
--- tb_unb2_board_clk200_pll.vhd it appears that the phase setting for c0 does
--- not influence the compensation. Therefore it is llso possible to use
--- g_clk200_phase_shift /= 0 and touse c0 as processing clock instead of c1.
--- . The phase offset of c0 and c1 in the clk200_pll MegaWizard component
--- can be set in steps of 11.25 degrees (and even finer):
--- g_clk200_phase_shift (for c0)
--- phase [degrees] g_clk200p_phase_shift (for c1)
--- 0 "0"
--- 11.25 "156"
--- 22.5 "313"
--- 33.75 "469"
--- 45 "625"
--- 56.25 "781"
--- 67.5 "938"
--- 78.75 "1094"
--- 90 "1250"
--- 101.25 "1406" = 1250+ 156
--- 112.5 "1563" = 1250+ 313
--- 123.75 "1719" = 1250+ 469
--- 135 "1875" = 1250+ 625
--- 146.25 "2031" = 1250+ 781
--- 157.5 "2188" = 1250+ 938
--- 168.75 "2344" = 1250+1094
--- 180 "2500" = 1250+1250
--- 191.25 "2656" = 2500+ 156
--- 202.5 "2813" = 2500+ 313
--- 213.75 "2969" = 2500+ 469
--- 225 "3125" = 2500+ 625
--- 236.25 "3281" = 2500+ 781
--- 247.5 "3438" = 2500+ 938
--- 258.75 "3594" = 2500+1094
--- 270 "3750" = 2500+1250
--- 281.25 "3906" = 3750+ 156
--- 292.5 "4063" = 3750+ 313
--- 303.75 "4219" = 3750+ 469
--- 315 "4375" = 3750+ 625
--- 326.25 "4531" = 3750+ 781
--- 337.5 "4688" = 3750+ 938
--- 348.75 "4844" = 3750+1094
--- 360 "5000" = 3750+1250
--- . With a phase offset of 22.5 degrees the c1 = clk200p is offset by a 1/16
--- period of 200 MHz, so 1/8 period of the 400 MHz DCLK from ADU and 1/4
--- period of the 800 MHz sample SCLK of ADU. This phase offset can be used
--- to achieve stable timing between the DCLK and the clk200p domain.
--- . Some DSP may also be possible at 400 MHz via st_clk400. Note that this
--- 400 MHz can also be used at places where only a little more than 200 MHz
--- would be needed, e.g. to create packets at full data rate.
--- Therefore it is not necessary to create yet another st clock frequency.
--- This to also avoid the EMI or RFI that a non integer factor of 200 MHz
--- like e.g. 250 MHz would cause.
--- . At 400 MHz ADC samples can be clocked in at 800 MSps using DDIO. At 800
--- MSps the sample period is 1250 ns. Input timing can be tuned via fixed
--- pad input delays and/or by using another phase of the PLL output clock.
--- Remarks:
--- . If necessary more 400 M clock phase could be made available, via g_sel.
---
+ -- Purpose: PLL for UniBoard node CLK input @ 200 MHz
+ -- Description:
+ -- . The PLL runs in normal mode using c0 to compensate for the internal clock
+ -- network delay, so that c0 = st_clk200 is aligned to the input clk200.
+ -- . The assumption is that default the streaming DSP will run on the 200 MHz
+ -- clock from the CLK input via c1 = st_clk200p.
+ -- . The PLL normal mode operation compensates for internal clock network
+ -- delays of c0. This compensations aligns c0 to inclk0. With
+ -- tb_unb2_board_clk200_pll.vhd it appears that the phase setting for c0 does
+ -- not influence the compensation. Therefore it is llso possible to use
+ -- g_clk200_phase_shift /= 0 and touse c0 as processing clock instead of c1.
+ -- . The phase offset of c0 and c1 in the clk200_pll MegaWizard component
+ -- can be set in steps of 11.25 degrees (and even finer):
+ -- g_clk200_phase_shift (for c0)
+ -- phase [degrees] g_clk200p_phase_shift (for c1)
+ -- 0 "0"
+ -- 11.25 "156"
+ -- 22.5 "313"
+ -- 33.75 "469"
+ -- 45 "625"
+ -- 56.25 "781"
+ -- 67.5 "938"
+ -- 78.75 "1094"
+ -- 90 "1250"
+ -- 101.25 "1406" = 1250+ 156
+ -- 112.5 "1563" = 1250+ 313
+ -- 123.75 "1719" = 1250+ 469
+ -- 135 "1875" = 1250+ 625
+ -- 146.25 "2031" = 1250+ 781
+ -- 157.5 "2188" = 1250+ 938
+ -- 168.75 "2344" = 1250+1094
+ -- 180 "2500" = 1250+1250
+ -- 191.25 "2656" = 2500+ 156
+ -- 202.5 "2813" = 2500+ 313
+ -- 213.75 "2969" = 2500+ 469
+ -- 225 "3125" = 2500+ 625
+ -- 236.25 "3281" = 2500+ 781
+ -- 247.5 "3438" = 2500+ 938
+ -- 258.75 "3594" = 2500+1094
+ -- 270 "3750" = 2500+1250
+ -- 281.25 "3906" = 3750+ 156
+ -- 292.5 "4063" = 3750+ 313
+ -- 303.75 "4219" = 3750+ 469
+ -- 315 "4375" = 3750+ 625
+ -- 326.25 "4531" = 3750+ 781
+ -- 337.5 "4688" = 3750+ 938
+ -- 348.75 "4844" = 3750+1094
+ -- 360 "5000" = 3750+1250
+ -- . With a phase offset of 22.5 degrees the c1 = clk200p is offset by a 1/16
+ -- period of 200 MHz, so 1/8 period of the 400 MHz DCLK from ADU and 1/4
+ -- period of the 800 MHz sample SCLK of ADU. This phase offset can be used
+ -- to achieve stable timing between the DCLK and the clk200p domain.
+ -- . Some DSP may also be possible at 400 MHz via st_clk400. Note that this
+ -- 400 MHz can also be used at places where only a little more than 200 MHz
+ -- would be needed, e.g. to create packets at full data rate.
+ -- Therefore it is not necessary to create yet another st clock frequency.
+ -- This to also avoid the EMI or RFI that a non integer factor of 200 MHz
+ -- like e.g. 250 MHz would cause.
+ -- . At 400 MHz ADC samples can be clocked in at 800 MSps using DDIO. At 800
+ -- MSps the sample period is 1250 ns. Input timing can be tuned via fixed
+ -- pad input delays and/or by using another phase of the PLL output clock.
+ -- Remarks:
+ -- . If necessary more 400 M clock phase could be made available, via g_sel.
+ --
entity unb2_board_clk200_pll is
generic (
@@ -136,82 +136,82 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk200,
- outclk => clk200buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk200,
+ outclk => clk200buf
+ );
end generate;
gen_st_pll : if g_use_fpll = false generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200buf,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_st_fractional_pll : if g_use_fpll = true generate
u_st_fractional_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk200
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf, -- 200 MHz
+ c0 => i_st_clk200, -- 200 MHz
+ c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
+ c2 => i_st_clk400, -- 400 MHz
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end arria10;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
index 70d83befad..ac1110c652 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
@@ -21,17 +21,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Purpose: PLL for UniBoard node CLK input @ 25 MHz
--- Description:
--- c0 = 20 MHz
--- c1 = 50 MHz
--- c2 = 100 MHz
--- c3 = 125 MHz
---
+ -- Purpose: PLL for UniBoard node CLK input @ 25 MHz
+ -- Description:
+ -- c0 = 20 MHz
+ -- c1 = 50 MHz
+ -- c2 = 100 MHz
+ -- c3 = 125 MHz
+ --
entity unb2_board_clk25_pll is
generic (
@@ -52,16 +52,16 @@ end unb2_board_clk25_pll;
architecture arria10 of unb2_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end arria10;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
index 4bacebe5af..a0ef1a7cae 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose:
--- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
--- reset_n).
--- 2) sys_rst released when the sys_clk PLL from the SOPC system has locked,
--- can be used as a system reset for the sys_clk domain.
+ -- Purpose:
+ -- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
+ -- reset_n).
+ -- 2) sys_rst released when the sys_clk PLL from the SOPC system has locked,
+ -- can be used as a system reset for the sys_clk domain.
entity unb2_board_clk_rst is
port (
@@ -55,27 +55,27 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
index 1e8e9a974c..79d90d91e0 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_front_io is
generic (
@@ -62,8 +62,8 @@ begin
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2_board_tr_qsfp.bus_w - 1 generate
- si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
- serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
-end;
+ end;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
index b37cfbaf8f..dcdcee8770 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose: Provide the basic node clock control (resets, pulses, WDI)
--- Description:
--- . Create mm_rst for mm_clk:
--- . Extend WDI to avoid watchdog reset during software reload
--- . Pulse every 1 us, 1 ms and 1 s
+ -- Purpose: Provide the basic node clock control (resets, pulses, WDI)
+ -- Description:
+ -- . Create mm_rst for mm_clk:
+ -- . Extend WDI to avoid watchdog reset during software reload
+ -- . Pulse every 1 us, 1 ms and 1 s
entity unb2_board_node_ctrl is
generic (
@@ -67,43 +67,43 @@ begin
mm_locked_n <= not mm_locked;
u_common_areset_mm : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => mm_clk,
- out_rst => i_mm_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => mm_clk,
+ out_rst => i_mm_rst
+ );
-- Create 1 pulse per us, per ms and per s
mm_pulse_ms <= i_mm_pulse_ms;
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_us => mm_pulse_us,
- pulse_ms => i_mm_pulse_ms,
- pulse_s => mm_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_us => mm_pulse_us,
+ pulse_ms => i_mm_pulse_ms,
+ pulse_s => mm_pulse_s
+ );
-- Toggle the WDI every 1 ms
u_unb2_board_wdi_extend : entity work.unb2_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_ms => i_mm_pulse_ms,
- wdi_in => mm_wdi_in,
- wdi_out => mm_wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_ms => i_mm_pulse_ms,
+ wdi_in => mm_wdi_in,
+ wdi_out => mm_wdi_out
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
index aa42e0627d..6770d02645 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb2_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
@@ -74,10 +74,10 @@ package unb2_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
index 20f6933225..eb8ccddb9b 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb2_board_pkg is
-- UniBoard
@@ -135,21 +135,23 @@ package unb2_board_pkg is
type t_c_unb2_board_system_info is record
version : natural; -- UniBoard board HW version (2 bit value)
id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
+ -- Derived ID info:
bck_id : natural; -- = id[7:2], ID part from back plane
chip_id : natural; -- = id[1:0], ID part from UniBoard
node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
is_node2 : natural; -- 1 for Node 2, else 0.
end record;
- function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info;
+ function func_unb2_board_system_info(
+ VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info;
-end unb2_board_pkg;
+ end unb2_board_pkg;
package body unb2_board_pkg is
- function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info is
+ function func_unb2_board_system_info(
+ VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info is
variable v_system_info : t_c_unb2_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
@@ -161,4 +163,4 @@ package body unb2_board_pkg is
return v_system_info;
end;
-end unb2_board_pkg;
+ end unb2_board_pkg;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
index 45987424f3..ee2859bcc2 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_pmbus_ctrl is
generic (
@@ -71,16 +71,16 @@ architecture rtl of unb2_board_pmbus_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
--- SMBUS_READ_BYTE , LOC_POWER_CORE, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_CORE, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_CORE, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_CORE, LP_TEMP,
+ -- SMBUS_READ_BYTE , LOC_POWER_CORE, LP_VOUT_MODE,
+ -- SMBUS_READ_WORD , LOC_POWER_CORE, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_CORE, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_CORE, LP_TEMP,
--SMBUS_READ_BYTE , LOC_POWER_ERAM, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_TEMP,
---
+ -- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_TEMP,
+ --
SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_VOUT_MODE,
SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_VOUT_MODE,
SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_VOUT_MODE,
@@ -88,26 +88,26 @@ architecture rtl of unb2_board_pmbus_ctrl is
--SMBUS_READ_WORD , LOC_POWER_TR_R, LP_VOUT,
--SMBUS_READ_WORD , LOC_POWER_TR_R, LP_IOUT,
--SMBUS_READ_WORD , LOC_POWER_TR_R, LP_TEMP,
---
--- --SMBUS_READ_BYTE , LOC_POWER_TR_T, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_TEMP,
---
--- --SMBUS_READ_BYTE , LOC_POWER_BAT, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_BAT, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_BAT, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_BAT, LP_TEMP,
---
--- --SMBUS_READ_BYTE , LOC_POWER_IO, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_IO, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_IO, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_IO, LP_TEMP,
+ --
+ -- --SMBUS_READ_BYTE , LOC_POWER_TR_T, LP_VOUT_MODE,
+ -- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_TEMP,
+ --
+ -- --SMBUS_READ_BYTE , LOC_POWER_BAT, LP_VOUT_MODE,
+ -- SMBUS_READ_WORD , LOC_POWER_BAT, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_BAT, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_BAT, LP_TEMP,
+ --
+ -- --SMBUS_READ_BYTE , LOC_POWER_IO, LP_VOUT_MODE,
+ -- SMBUS_READ_WORD , LOC_POWER_IO, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_IO, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_IO, LP_TEMP,
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
+ ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
constant c_seq_len : natural := c_SEQ'length - 1; -- upto SMBUS_C_END, the SMBUS_C_NOP is dummy to allow sufficient seq_cnt range
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
index db1d2a0252..ce6011fa73 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
@@ -21,48 +21,48 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
--- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
--- Description:
--- The testio LED on UniBoard2 is not visible via the front panel. The
--- front panel does have a dual colour LED for each QSFP lane. Therefore
--- these QSFP LEDs are used to signal some application information and lane
--- status/activity information.
---
--- LED lights:
---
--- 1) Default behaviour for all QSFP leds:
--- . off = no FPGA image is running
---
--- 2) For factory image:
--- . green off
--- . red toggling every 1 s = factory image is running (g_factory_image=TRUE)
---
--- 3) For a user image without Gbps lane functionality:
--- . red off
--- . green toggling every 1 s = user image is running (g_factory_image=FALSE and green_on_arr(I)='0' default)
---
--- 4) For a user image with Gbps lane functionality:
--- . red off
--- . green toggling every 1 s when the lane status is not OK (green_on_arr(I)=xon='0')
--- . green on continously when the lane status is OK (green_on_arr(I)=xon='1')
--- . green led goes off briefly off when there is an Tx or Rx packet (green_evt_arr(I).sop='1')
---
--- The combined colour amber (= red + green) is not used. The factory image
--- only uses the red led and the user image only uses the green led.
---
--- Each QSFP carries c_quad = 4 lanes, therefore the green led LED can only
--- signal a combined status of the lanes. The combined status eg. be:
---
--- 'and-status' = combined status is on when all lanes are on
--- 'or-status' = combined status is on when at least 1 lane is on
---
--- Choose using 'or-status', because then the LED can give lane status
--- information when less than all 4 lane are connected.
---
+ -- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
+ -- Description:
+ -- The testio LED on UniBoard2 is not visible via the front panel. The
+ -- front panel does have a dual colour LED for each QSFP lane. Therefore
+ -- these QSFP LEDs are used to signal some application information and lane
+ -- status/activity information.
+ --
+ -- LED lights:
+ --
+ -- 1) Default behaviour for all QSFP leds:
+ -- . off = no FPGA image is running
+ --
+ -- 2) For factory image:
+ -- . green off
+ -- . red toggling every 1 s = factory image is running (g_factory_image=TRUE)
+ --
+ -- 3) For a user image without Gbps lane functionality:
+ -- . red off
+ -- . green toggling every 1 s = user image is running (g_factory_image=FALSE and green_on_arr(I)='0' default)
+ --
+ -- 4) For a user image with Gbps lane functionality:
+ -- . red off
+ -- . green toggling every 1 s when the lane status is not OK (green_on_arr(I)=xon='0')
+ -- . green on continously when the lane status is OK (green_on_arr(I)=xon='1')
+ -- . green led goes off briefly off when there is an Tx or Rx packet (green_evt_arr(I).sop='1')
+ --
+ -- The combined colour amber (= red + green) is not used. The factory image
+ -- only uses the red led and the user image only uses the green led.
+ --
+ -- Each QSFP carries c_quad = 4 lanes, therefore the green led LED can only
+ -- signal a combined status of the lanes. The combined status eg. be:
+ --
+ -- 'and-status' = combined status is on when all lanes are on
+ -- 'or-status' = combined status is on when at least 1 lane is on
+ --
+ -- Choose using 'or-status', because then the LED can give lane status
+ -- information when less than all 4 lane are connected.
+ --
entity unb2_board_qsfp_leds is
generic (
@@ -107,43 +107,43 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => i_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => i_pulse_s
+ );
u_common_toggle_s : entity common_lib.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => i_pulse_s,
- out_dat => toggle_s
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => i_pulse_s,
+ out_dat => toggle_s
+ );
gen_factory_image : if g_factory_image = true generate
green_led_arr <= (others => '0');
gen_red_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
u_red_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- -- led control
- ctrl_input => toggle_s,
- -- led output
- led => red_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- led control
+ ctrl_input => toggle_s,
+ -- led output
+ led => red_led_arr(I)
+ );
end generate;
end generate;
@@ -160,20 +160,20 @@ begin
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
u_green_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => i_pulse_ms,
- -- led control
- ctrl_on => qsfp_on_arr(I),
- ctrl_evt => qsfp_evt_arr(I),
- ctrl_input => toggle_s,
- -- led output
- led => green_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => i_pulse_ms,
+ -- led control
+ ctrl_on => qsfp_on_arr(I),
+ ctrl_evt => qsfp_evt_arr(I),
+ ctrl_input => toggle_s,
+ -- led output
+ led => green_led_arr(I)
+ );
end generate;
end generate;
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
index b83c069659..00fde0bd2f 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_ring_io is
generic (
@@ -52,4 +52,4 @@ begin
serial_rx_arr(i * c_unb2_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
-end;
+ end;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
index 18a16b5aab..795b69fae2 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use i2c_lib.i2c_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use i2c_lib.i2c_pkg.all;
entity unb2_board_sens is
generic (
@@ -50,7 +50,7 @@ architecture str of unb2_board_sens is
-- I2C clock rate settings
constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
constant c_sens_comma_w : natural := 0; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
- -- 0 = no comma time
+ -- 0 = no comma time
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
@@ -64,68 +64,68 @@ architecture str of unb2_board_sens is
begin
gen_unb2_board_sens_ctrl : if g_pmbus = false generate
u_unb2_board_sens_ctrl : entity work.unb2_board_sens_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2_board_pmbus_ctrl : if g_pmbus = true generate
u_unb2_board_pmbus_ctrl : entity work.unb2_board_pmbus_ctrl
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
+ end generate;
+
+ u_i2c_smbus : entity i2c_lib.i2c_smbus
generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
+ g_i2c_phy => c_sens_phy
)
port map (
+ gs_sim => g_sim,
clk => clk,
rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
+ in_dat => smbus_in_dat,
+ in_req => smbus_in_val,
+ out_dat => smbus_out_dat,
+ out_val => smbus_out_val,
+ out_err => smbus_out_err,
+ out_ack => smbus_out_ack,
+ st_end => smbus_out_end,
+ scl => scl,
+ sda => sda
);
- end generate;
-
- u_i2c_smbus : entity i2c_lib.i2c_smbus
- generic map (
- g_i2c_phy => c_sens_phy
- )
- port map (
- gs_sim => g_sim,
- clk => clk,
- rst => rst,
- in_dat => smbus_in_dat,
- in_req => smbus_in_val,
- out_dat => smbus_out_dat,
- out_val => smbus_out_val,
- out_err => smbus_out_err,
- out_ack => smbus_out_ack,
- st_end => smbus_out_end,
- scl => scl,
- sda => sda
- );
-end architecture;
+ end architecture;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
index da90d846f8..3462492067 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_sens_ctrl is
generic (
@@ -69,7 +69,7 @@ architecture rtl of unb2_board_sens_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
+ ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
constant c_seq_len : natural := c_SEQ'length - 1; -- upto SMBUS_C_END, the SMBUS_C_NOP is dummy to allow sufficient seq_cnt range
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
index 9790dc3ea0..d641807ddc 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
@@ -60,10 +60,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2_board_sens_reg is
generic (
@@ -92,13 +92,14 @@ end unb2_board_sens_reg;
architecture rtl of unb2_board_sens_reg is
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
- -- +1 to fit sens_err in the last address
+ -- +1 to fit sens_err in the last address
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_mm_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_mm_nof_dat),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_mm_nof_dat,
+ init_sl => '0');
signal i_temp_high : std_logic_vector(6 downto 0);
begin
@@ -130,14 +131,14 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
if vA = g_sens_nof_result + 1 then
- -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
- -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
- if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
- i_temp_high <= sla_in.wrdata(6 downto 0);
- end if;
+ -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
+ -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
+ if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
+ i_temp_high <= sla_in.wrdata(6 downto 0);
+ end if;
end if;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
index c3958aa407..d6cddd260d 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
@@ -21,14 +21,14 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Keep the UniBoard system info knowledge in this HDL entity and in the
--- corresponding software functions in unb_common.c,h. This avoids having to
--- define named constants for indexing the fields in the info word.
+ -- Keep the UniBoard system info knowledge in this HDL entity and in the
+ -- corresponding software functions in unb_common.c,h. This avoids having to
+ -- define named constants for indexing the fields in the info word.
entity unb2_board_system_info is
generic (
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
index 2b7a13332c..b40384049a 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_system_info_reg is
generic (
@@ -68,7 +68,7 @@ entity unb2_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb2_board_system_info_reg;
architecture rtl of unb2_board_system_info_reg is
@@ -79,11 +79,12 @@ architecture rtl of unb2_board_system_info_reg is
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0');
constant c_use_phy_w : natural := 8;
constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
index e09adb5ff9..c308456393 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose:
--- Extend the input WDI that is controlled in SW (as it should be) to avoid
--- that the watchdog reset will occur when new SW is loaded, while keeping
--- the HDL image. This component extends the last input WDI by toggling the
--- output WDI for about 2**(g_extend_w-1) ms more.
+ -- Purpose:
+ -- Extend the input WDI that is controlled in SW (as it should be) to avoid
+ -- that the watchdog reset will occur when new SW is loaded, while keeping
+ -- the HDL image. This component extends the last input WDI by toggling the
+ -- output WDI for about 2**(g_extend_w-1) ms more.
entity unb2_board_wdi_extend is
generic (
@@ -68,26 +68,26 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
index fa05af1d4f..b6565635d1 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2_board_wdi_reg is
port (
@@ -40,16 +40,17 @@ entity unb2_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb2_board_wdi_reg;
architecture rtl of unb2_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
@@ -60,7 +61,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
index 049c7da72e..22f84d19e8 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
@@ -23,11 +23,11 @@
--
library IEEE, common_lib, technology_lib, fpga_sense_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_fpga_sens_reg is
generic (
@@ -64,20 +64,20 @@ begin
temp_high <= (others => '0'); -- i_temp_high;
u_fpga_sense: entity fpga_sense_lib.fpga_sense
- generic map (
- g_technology => g_technology,
- g_sim => g_sim
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_technology => g_technology,
+ g_sim => g_sim
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- start_sense => start,
+ start_sense => start,
- reg_temp_mosi => sla_temp_in,
- reg_temp_miso => sla_temp_out,
+ reg_temp_mosi => sla_temp_in,
+ reg_temp_miso => sla_temp_out,
- reg_voltage_store_mosi => sla_voltage_in,
- reg_voltage_store_miso => sla_voltage_out
- );
+ reg_voltage_store_mosi => sla_voltage_in,
+ reg_voltage_store_miso => sla_voltage_out
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index 3449629f92..46e3f1824c 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -32,11 +32,11 @@ entity tb_mms_unb2_board_sens is
end tb_mms_unb2_board_sens;
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
architecture tb of tb_mms_unb2_board_sens is
constant c_sim : boolean := true; -- FALSE;
@@ -147,58 +147,58 @@ begin
-- I2C sensors master
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
- generic map (
- g_sim => c_sim,
- g_clk_freq => c_clk_freq,
- g_temp_high => c_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- mm_start => start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- i2c bus
- scl => scl,
- sda => sda
- );
+ generic map (
+ g_sim => c_sim,
+ g_clk_freq => c_clk_freq,
+ g_temp_high => c_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ mm_start => start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- i2c bus
+ scl => scl,
+ sda => sda
+ );
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => scl,
- sda => sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
index bd1504ec13..35eb1a3016 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk125_pll is
end tb_unb2_board_clk125_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk125_pll
- port map (
- arst => ext_rst,
- clk125 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk125 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
index ae4e087f1e..6dbde563b3 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk200_pll is
end tb_unb2_board_clk200_pll;
@@ -66,44 +66,44 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
index b8ea88958d..cbb9a1d472 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk25_pll is
end tb_unb2_board_clk25_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk25_pll
- port map (
- arst => ext_rst,
- clk25 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk25 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
index 1d6125db58..ed4bda1034 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_node_ctrl is
end tb_unb2_board_node_ctrl;
@@ -71,23 +71,23 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- -- MM clock domain reset
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => wdi_in,
- mm_wdi_out => wdi_out,
- -- Pulses
- mm_pulse_us => pulse_us,
- mm_pulse_ms => pulse_ms,
- mm_pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => wdi_in,
+ mm_wdi_out => wdi_out,
+ -- Pulses
+ mm_pulse_us => pulse_us,
+ mm_pulse_ms => pulse_ms,
+ mm_pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
index 2a4f41e547..d7e287a9a2 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
@@ -37,10 +37,10 @@
-- > run -a
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_unb2_board_qsfp_leds is
end tb_unb2_board_qsfp_leds;
@@ -139,48 +139,48 @@ begin
end process;
u_unb2_factory_qsfp_leds : entity work.unb2_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => factory_green_led_arr,
- red_led_arr => factory_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => true, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => factory_green_led_arr,
+ red_led_arr => factory_red_led_arr
+ );
u_unb2_user_qsfp_leds : entity work.unb2_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => user_green_led_arr,
- red_led_arr => user_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => false, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => user_green_led_arr,
+ red_led_arr => user_red_led_arr
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
index 24d2ecc45e..8924b23776 100644
--- a/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
+++ b/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_10gbe is
generic (
@@ -74,17 +74,17 @@ architecture str of unb2_board_10gbe is
signal tr_ref_rst_156 : std_logic;
begin
u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => g_technology
- )
- port map (
- refclk_644 => tr_ref_clk,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ refclk_644 => tr_ref_clk,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
index f2b16a7154..c21c545a25 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
@@ -1,90 +1,90 @@
- component ddr4_micron46_mbIIskew is
- port (
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic; -- readdatavalid
- mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
- mmr_slave_read_0 : in std_logic := 'X'; -- read
- mmr_slave_write_0 : in std_logic := 'X'; -- write
- mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
- mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
- mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
- mmr_slave_readdatavalid_0 : out std_logic; -- readdatavalid
- emif_usr_clk : out std_logic; -- clk
- emif_usr_reset_n : out std_logic; -- reset_n
- global_reset_n : in std_logic := 'X'; -- reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- pll_ref_clk : in std_logic := 'X'; -- clk
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic -- local_cal_fail
- );
- end component ddr4_micron46_mbIIskew;
+component ddr4_micron46_mbIIskew is
+ port (
+ amm_ready_0 : out std_logic; -- waitrequest_n
+ amm_read_0 : in std_logic := 'X'; -- read
+ amm_write_0 : in std_logic := 'X'; -- write
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
+ amm_readdatavalid_0 : out std_logic; -- readdatavalid
+ mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
+ mmr_slave_read_0 : in std_logic := 'X'; -- read
+ mmr_slave_write_0 : in std_logic := 'X'; -- write
+ mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
+ mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
+ mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
+ mmr_slave_readdatavalid_0 : out std_logic; -- readdatavalid
+ emif_usr_clk : out std_logic; -- clk
+ emif_usr_reset_n : out std_logic; -- reset_n
+ global_reset_n : in std_logic := 'X'; -- reset_n
+ mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ mem_par : out std_logic_vector(0 downto 0); -- mem_par
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
+ oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ local_cal_success : out std_logic; -- local_cal_success
+ local_cal_fail : out std_logic -- local_cal_fail
+ );
+end component ddr4_micron46_mbIIskew;
- u0 : component ddr4_micron46_mbIIskew
- port map (
- amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
- amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
- amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
- amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
- amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
- amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
- amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
- mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
- mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
- mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
- mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
- mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
- mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
- mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
- mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
- mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0, -- .readdatavalid
- emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
- emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
- global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
- mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
- mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
- mem_a => CONNECTED_TO_mem_a, -- .mem_a
- mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
- mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
- mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
- mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
- mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
- mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
- mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
- mem_par => CONNECTED_TO_mem_par, -- .mem_par
- mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
- mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
- mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
- mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
- mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
- oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
- local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
- );
+u0 : component ddr4_micron46_mbIIskew
+ port map (
+ amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
+ amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
+ amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
+ amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
+ amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
+ amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
+ amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
+ amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
+ amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
+ mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
+ mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
+ mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
+ mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
+ mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
+ mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
+ mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
+ mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
+ mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0, -- .readdatavalid
+ emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
+ emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
+ global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
+ mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
+ mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
+ mem_a => CONNECTED_TO_mem_a, -- .mem_a
+ mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
+ mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
+ mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
+ mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
+ mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
+ mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
+ mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
+ mem_par => CONNECTED_TO_mem_par, -- .mem_par
+ mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
+ mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
+ mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
+ mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
+ mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
+ oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
+ local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
+ );
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
index c028fced70..fe371a18ec 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
@@ -1,90 +1,90 @@
- component ddr4_micron46_mbIskew is
- port (
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic; -- readdatavalid
- mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
- mmr_slave_read_0 : in std_logic := 'X'; -- read
- mmr_slave_write_0 : in std_logic := 'X'; -- write
- mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
- mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
- mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
- mmr_slave_readdatavalid_0 : out std_logic; -- readdatavalid
- emif_usr_clk : out std_logic; -- clk
- emif_usr_reset_n : out std_logic; -- reset_n
- global_reset_n : in std_logic := 'X'; -- reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- pll_ref_clk : in std_logic := 'X'; -- clk
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic -- local_cal_fail
- );
- end component ddr4_micron46_mbIskew;
+component ddr4_micron46_mbIskew is
+ port (
+ amm_ready_0 : out std_logic; -- waitrequest_n
+ amm_read_0 : in std_logic := 'X'; -- read
+ amm_write_0 : in std_logic := 'X'; -- write
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
+ amm_readdatavalid_0 : out std_logic; -- readdatavalid
+ mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
+ mmr_slave_read_0 : in std_logic := 'X'; -- read
+ mmr_slave_write_0 : in std_logic := 'X'; -- write
+ mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
+ mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
+ mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
+ mmr_slave_readdatavalid_0 : out std_logic; -- readdatavalid
+ emif_usr_clk : out std_logic; -- clk
+ emif_usr_reset_n : out std_logic; -- reset_n
+ global_reset_n : in std_logic := 'X'; -- reset_n
+ mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ mem_par : out std_logic_vector(0 downto 0); -- mem_par
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
+ oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ local_cal_success : out std_logic; -- local_cal_success
+ local_cal_fail : out std_logic -- local_cal_fail
+ );
+end component ddr4_micron46_mbIskew;
- u0 : component ddr4_micron46_mbIskew
- port map (
- amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
- amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
- amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
- amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
- amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
- amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
- amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
- mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
- mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
- mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
- mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
- mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
- mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
- mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
- mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
- mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0, -- .readdatavalid
- emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
- emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
- global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
- mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
- mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
- mem_a => CONNECTED_TO_mem_a, -- .mem_a
- mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
- mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
- mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
- mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
- mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
- mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
- mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
- mem_par => CONNECTED_TO_mem_par, -- .mem_par
- mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
- mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
- mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
- mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
- mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
- oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
- local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
- );
+u0 : component ddr4_micron46_mbIskew
+ port map (
+ amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
+ amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
+ amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
+ amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
+ amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
+ amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
+ amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
+ amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
+ amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
+ mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
+ mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
+ mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
+ mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
+ mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
+ mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
+ mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
+ mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
+ mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0, -- .readdatavalid
+ emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
+ emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
+ global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
+ mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
+ mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
+ mem_a => CONNECTED_TO_mem_a, -- .mem_a
+ mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
+ mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
+ mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
+ mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
+ mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
+ mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
+ mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
+ mem_par => CONNECTED_TO_mem_par, -- .mem_par
+ mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
+ mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
+ mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
+ mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
+ mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
+ oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
+ local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
+ );
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
index f1ce0394dc..16b03f8b6f 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use unb2a_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2a_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use unb2a_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2a_heater_pkg.all;
entity mmm_unb2a_heater is
generic (
@@ -114,36 +114,46 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_reg_heater : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
- port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
+ u_mm_file_reg_heater : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
+ port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -306,7 +316,7 @@ begin
reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w - 1 downto 0),
reg_heater_write_export => reg_heater_mosi.wr,
reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
end str;
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
index b60792517e..0a6bb7c469 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
@@ -20,143 +20,143 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2a_heater_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v15.1 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v15.1 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_unb2a_heater is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_reset_export : out std_logic -- export
- );
- end component qsys_unb2a_heater;
+ component qsys_unb2a_heater is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2a_heater;
end qsys_unb2a_heater_pkg;
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
index 5c298a90dc..15f9bfcf2c 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, technology_lib, util_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use util_lib.util_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use util_lib.util_heater_pkg.all;
entity unb2a_heater is
generic (
@@ -161,240 +161,240 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2a_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_tse_clk_buf => false, -- TRUE,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_tse_clk_buf => false, -- TRUE,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2a_heater
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- heater:
- reg_heater_mosi => reg_heater_mosi,
- reg_heater_miso => reg_heater_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- heater:
+ reg_heater_mosi => reg_heater_mosi,
+ reg_heater_miso => reg_heater_miso
+ );
u_front_led : entity unb2a_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2a_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_heater : entity util_lib.util_heater
- generic map (
- g_technology => g_technology,
- --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
- --g_nof_mac4 => 630 --
- g_nof_mac4 => 736 -- 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- sla_in => reg_heater_mosi,
- sla_out => reg_heater_miso
- );
+ generic map (
+ g_technology => g_technology,
+ --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
+ --g_nof_mac4 => 630 --
+ g_nof_mac4 => 736 -- 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ sla_in => reg_heater_mosi,
+ sla_out => reg_heater_miso
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
index 16c91fe754..cf108a644a 100644
--- a/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb2a_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2a_heater is
- generic (
- g_design_name : string := "unb2a_heater";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2a_heater";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2a_heater;
architecture tb of tb_unb2a_heater is
@@ -181,36 +181,36 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd b/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
index 4290c6d733..7c04262c09 100644
--- a/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
+++ b/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
entity unb2a_led is
generic (
@@ -99,15 +99,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
-- mm_clk
@@ -118,40 +118,40 @@ begin
i_mm_clk <= clk50;
gen_mm_clk_sim: if g_sim = true generate
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- mm_locked <= '0', '1' after 70 ns;
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2a_board_clk125_pll : entity unb2a_board_lib.unb2_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c1_clk50 => clk50,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2a_board_node_ctrl : entity unb2a_board_lib.unb2_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c1_clk50 => clk50,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => mm_pulse_s,
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2a_board_node_ctrl : entity unb2a_board_lib.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => mm_pulse_s,
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
------------------------------------------------------------------------------
-- Toggle red LED when unb2a_minimal is running, green LED for other designs.
@@ -160,15 +160,15 @@ begin
led_flash_green <= sel_a_b(g_factory_image = false, led_flash, '0');
u_extend : entity common_lib.common_pulse_extend
- generic map (
- g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- p_in => mm_pulse_s,
- ep_out => led_flash
- );
+ generic map (
+ g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ p_in => mm_pulse_s,
+ ep_out => led_flash
+ );
-- Red LED control
TESTIO(c_unb2_board_testio_led_red) <= led_flash_red;
@@ -177,36 +177,36 @@ begin
TESTIO(c_unb2_board_testio_led_green) <= led_flash_green;
u_common_pulser_10Hz : entity common_lib.common_pulser
- generic map (
- g_pulse_period => 100,
- g_pulse_phase => 100 - 1
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- clken => '1',
- pulse_en => mm_pulse_ms,
- pulse_out => pulse_10Hz
- );
+ generic map (
+ g_pulse_period => 100,
+ g_pulse_phase => 100 - 1
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ clken => '1',
+ pulse_en => mm_pulse_ms,
+ pulse_out => pulse_10Hz
+ );
u_extend_10Hz : entity common_lib.common_pulse_extend
- generic map (
- g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- p_in => pulse_10Hz,
- ep_out => pulse_10Hz_extended
- );
+ generic map (
+ g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ p_in => pulse_10Hz,
+ ep_out => pulse_10Hz_extended
+ );
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
QSFP_LED(2) <= pulse_10Hz_extended;
QSFP_LED(6) <= led_toggle;
diff --git a/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd b/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
index 4e604241be..9eeed8ebd9 100644
--- a/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
+++ b/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
@@ -39,18 +39,18 @@
--
library IEEE, common_lib, unb2a_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2a_led is
- generic (
- g_design_name : string := "unb2a_led";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2a_led";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2a_led;
architecture tb of tb_unb2a_led is
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
index 2a634cb563..a1c09d7630 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use unb2a_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2a_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use unb2a_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2a_minimal_pkg.all;
entity mmm_unb2a_minimal is
generic (
@@ -110,33 +110,42 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -291,7 +300,7 @@ begin
reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
end str;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
index 6897ea10bf..873f0224a3 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
@@ -20,136 +20,136 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2a_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v14 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_unb2a_minimal is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
- );
- end component qsys_unb2a_minimal;
+ component qsys_unb2a_minimal is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2a_minimal;
end qsys_unb2a_minimal_pkg;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
index ea1f2090f8..4ceac5de57 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
entity unb2a_minimal is
generic (
@@ -156,217 +156,217 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2a_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2a_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso
+ );
u_front_led : entity unb2a_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2a_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
index 6f8ae35cfe..ca172e78c9 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
@@ -43,20 +43,20 @@
--
library IEEE, common_lib, unb2a_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
entity tb_unb2a_minimal is
- generic (
- g_design_name : string := "unb2a_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2a_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2a_minimal;
architecture tb of tb_unb2a_minimal is
@@ -185,51 +185,51 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
u_pmbus_tcvr0 : entity i2c_lib.dev_pmbus
- generic map (
- g_address => c_pmbus_tcvr0_address
- )
- port map (
- scl => PMBUS_SC,
- sda => PMBUS_SD,
- vout_mode => 13,
- vin => 92,
- vout => 18,
- iout => 12,
- vcap => 0,
- temp => 36
- );
+ generic map (
+ g_address => c_pmbus_tcvr0_address
+ )
+ port map (
+ scl => PMBUS_SC,
+ sda => PMBUS_SD,
+ vout_mode => 13,
+ vin => 92,
+ vout => 18,
+ iout => 12,
+ vcap => 0,
+ temp => 36
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
index 61f50f2ce0..ff638f6c22 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_10GbE is
end tb_unb2a_test_10GbE;
@@ -29,7 +29,7 @@ end tb_unb2a_test_10GbE;
architecture tb of tb_unb2a_test_10GbE is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_10GbE"
- );
+ generic map (
+ g_design_name => "unb2a_test_10GbE"
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
index bbcc7c1c0f..49fcc6023c 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2a_test_10GbE is
generic (
@@ -66,20 +66,20 @@ entity unb2a_test_10GbE is
BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
--- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
+ -- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
- -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -109,78 +109,78 @@ end unb2a_test_10GbE;
architecture str of unb2a_test_10GbE is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
-
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
index bbf7b8271e..d5f2442823 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_1GbE is
end tb_unb2a_test_1GbE;
@@ -29,7 +29,7 @@ end tb_unb2a_test_1GbE;
architecture tb of tb_unb2a_test_1GbE is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_1GbE"
- );
+ generic map (
+ g_design_name => "unb2a_test_1GbE"
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
index d326502fef..657aa4d913 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2a_test_1GbE is
generic (
@@ -71,42 +71,42 @@ end unb2a_test_1GbE;
architecture str of unb2a_test_1GbE is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
index f0a08f448d..947345317f 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_all is
end tb_unb2a_test_all;
@@ -29,8 +29,8 @@ end tb_unb2a_test_all;
architecture tb of tb_unb2a_test_all is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_all",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2a_test_all",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
index 3f78a1a941..c02b5bb9f6 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2a_test_all is
generic (
@@ -71,17 +71,17 @@ entity unb2a_test_all is
MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
--- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -120,91 +120,91 @@ end unb2a_test_all;
architecture str of unb2a_test_all is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
index e09dc3465b..c7308b5171 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_ddr_MB_I is
end tb_unb2a_test_ddr_MB_I;
@@ -29,8 +29,8 @@ end tb_unb2a_test_ddr_MB_I;
architecture tb of tb_unb2a_test_ddr_MB_I is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_ddr_MB_I",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2a_test_ddr_MB_I",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
index 7f6bcc8d64..a2563c0b6f 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2a_test_ddr_MB_I is
generic (
@@ -80,50 +80,50 @@ end unb2a_test_ddr_MB_I;
architecture str of unb2a_test_ddr_MB_I is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
index 0c5b8a474e..26fc2a7247 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_ddr_MB_II is
end tb_unb2a_test_ddr_MB_II;
@@ -29,8 +29,8 @@ end tb_unb2a_test_ddr_MB_II;
architecture tb of tb_unb2a_test_ddr_MB_II is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_ddr_MB_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2a_test_ddr_MB_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
index 45225efbb7..62c7df0f8b 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2a_test_ddr_MB_II is
generic (
@@ -80,50 +80,50 @@ end unb2a_test_ddr_MB_II;
architecture str of unb2a_test_ddr_MB_II is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
index 4e43f4e2f6..1850e8ff7e 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_ddr_MB_I_II is
end tb_unb2a_test_ddr_MB_I_II;
@@ -29,8 +29,8 @@ end tb_unb2a_test_ddr_MB_I_II;
architecture tb of tb_unb2a_test_ddr_MB_I_II is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_ddr_MB_I_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2a_test_ddr_MB_I_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
index a6f576bdf9..6d3ddbd47b 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2a_test_ddr_MB_I_II is
generic (
@@ -86,56 +86,56 @@ end unb2a_test_ddr_MB_I_II;
architecture str of unb2a_test_ddr_MB_I_II is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
index 262091355a..32fa582888 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use unb2a_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb2a_test_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
-use work.unb2a_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use unb2a_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb2a_test_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use work.unb2a_test_pkg.all;
entity mmm_unb2a_test is
generic (
@@ -237,16 +237,16 @@ architecture str of mmm_unb2a_test is
constant c_ram_diag_databuffer_ddr_addr_w : natural := ceil_log2(2 * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
--- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
--- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
---
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
---
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
+ -- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
-- tr_10GbE
constant c_reg_tr_10GbE_adr_w : natural := func_tech_mac_10g_csr_addr_w(g_technology);
@@ -287,116 +287,157 @@ begin
eth1g_eth0_mm_rst <= mm_rst;
eth1g_eth1_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
-
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
-
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
-
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
-
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
-
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
-
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
-
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-
- u_mm_file_reg_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
- u_mm_file_ram_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
- u_mm_file_reg_diag_tx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
-
- u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
- u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
- u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
-
--- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
---
--- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
---
--- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
-
- u_mm_file_reg_bsn_monitor_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
- u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
- u_mm_file_ram_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
- u_mm_file_reg_diag_rx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
- u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
- u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
-
- u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
-
- u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ u_mm_file_reg_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+ u_mm_file_ram_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
+ u_mm_file_reg_diag_tx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
+
+ u_mm_file_reg_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+ u_mm_file_ram_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+ u_mm_file_reg_diag_tx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+
+ -- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+ --
+ -- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
+ --
+ -- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
+
+ u_mm_file_reg_bsn_monitor_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
+ u_mm_file_reg_bsn_monitor_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
+ u_mm_file_ram_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
+ u_mm_file_reg_diag_rx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+ u_mm_file_ram_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+ u_mm_file_reg_diag_rx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+
+ u_mm_file_reg_io_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+ u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+ u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+ u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+ u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_reg_io_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+ u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+ u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+ u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+ u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
- u_mm_file_reg_eth1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
-
- u_mm_file_reg_10gbase_r_24 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_10GBASE_R_24")
- port map(mm_rst, mm_clk, reg_10gbase_r_24_mosi, reg_10gbase_r_24_miso);
-
- u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
- port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
- u_mm_file_reg_tr_10GbE_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
- u_mm_file_reg_tr_10GbE_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
-
- u_mm_file_reg_eth10g_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
- port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
- u_mm_file_reg_eth10g_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
- port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
- u_mm_file_reg_eth10g_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
- port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
+ u_mm_file_reg_eth0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
+ u_mm_file_reg_eth1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
+ port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
+
+ u_mm_file_reg_10gbase_r_24 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_10GBASE_R_24")
+ port map(mm_rst, mm_clk, reg_10gbase_r_24_mosi, reg_10gbase_r_24_miso);
+
+ u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
+ u_mm_file_reg_tr_10GbE_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
+ u_mm_file_reg_tr_10GbE_back1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
+
+ u_mm_file_reg_eth10g_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
+ u_mm_file_reg_eth10g_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
+ port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
+ u_mm_file_reg_eth10g_back1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
+ port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -421,10 +462,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_eth0_reg_mosi, i_eth1g_eth0_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
- else
- eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
- end if;
+ eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
+ else
+ eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -661,32 +702,32 @@ begin
reg_eth10g_back1_read_export => reg_eth10g_back1_mosi.rd,
reg_eth10g_back1_readdata_export => reg_eth10g_back1_miso.rddata(c_word_w - 1 downto 0),
--- -- the_reg_dp_offload_tx_1GbE
--- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
--- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
--- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_tx_1GbE_hdr_dat
--- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_rx_1GbE_hdr_dat
--- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- -- the_reg_dp_offload_tx_1GbE
+ -- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_tx_1GbE_hdr_dat
+ -- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_rx_1GbE_hdr_dat
+ -- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_1gbe_reset_export => OPEN,
reg_bsn_monitor_1gbe_clk_export => OPEN,
@@ -784,21 +825,21 @@ begin
reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
index 1a5006c92d..10b3fe0777 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2a_test_pkg is
-----------------------------------------------------------------------------
@@ -28,369 +28,369 @@ package qsys_unb2a_test_pkg is
-- $HDL_WORK/build/unb2a/quartus/unb2a_test_ddr/qsys_unb2a_test/sim/qsys_unb2a_test.vhd
-----------------------------------------------------------------------------
- component qsys_unb2a_test is
- port (
- avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
- avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
- avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
- avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
- avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
- avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
- avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
- avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
- avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
- avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
- avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
- avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
- avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
- avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
- avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
- avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
- avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
- avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
- avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
- avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
- clk_clk : in std_logic := '0'; -- clk.clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
- pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
- pio_pps_read_export : out std_logic; -- pio_pps_read.export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
- pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
- pio_pps_write_export : out std_logic; -- pio_pps_write.export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
- pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
- pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
- pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
- pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
- pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
- ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
- ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
- ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
- ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
- reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
- reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
- reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
- reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- reg_diag_data_buffer_10gbe_address.export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
- reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
- reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
- reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
- reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
- reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
- reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
- reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
- reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
- reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
- reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
- reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
- reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back0_address.export
- reg_eth10g_back0_clk_export : out std_logic; -- reg_eth10g_back0_clk.export
- reg_eth10g_back0_read_export : out std_logic; -- reg_eth10g_back0_read.export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back0_readdata.export
- reg_eth10g_back0_reset_export : out std_logic; -- reg_eth10g_back0_reset.export
- reg_eth10g_back0_write_export : out std_logic; -- reg_eth10g_back0_write.export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back0_writedata.export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back1_address.export
- reg_eth10g_back1_clk_export : out std_logic; -- reg_eth10g_back1_clk.export
- reg_eth10g_back1_read_export : out std_logic; -- reg_eth10g_back1_read.export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back1_readdata.export
- reg_eth10g_back1_reset_export : out std_logic; -- reg_eth10g_back1_reset.export
- reg_eth10g_back1_write_export : out std_logic; -- reg_eth10g_back1_write.export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back1_writedata.export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- reg_eth10g_qsfp_ring_address.export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- reg_eth10g_qsfp_ring_clk.export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- reg_eth10g_qsfp_ring_read.export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_qsfp_ring_readdata.export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- reg_eth10g_qsfp_ring_reset.export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- reg_eth10g_qsfp_ring_write.export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_qsfp_ring_writedata.export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- reg_fpga_temp_sens_address.export
- reg_fpga_temp_sens_clk_export : out std_logic; -- reg_fpga_temp_sens_clk.export
- reg_fpga_temp_sens_read_export : out std_logic; -- reg_fpga_temp_sens_read.export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_temp_sens_readdata.export
- reg_fpga_temp_sens_reset_export : out std_logic; -- reg_fpga_temp_sens_reset.export
- reg_fpga_temp_sens_write_export : out std_logic; -- reg_fpga_temp_sens_write.export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_temp_sens_writedata.export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- reg_fpga_voltage_sens_address.export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- reg_fpga_voltage_sens_clk.export
- reg_fpga_voltage_sens_read_export : out std_logic; -- reg_fpga_voltage_sens_read.export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_voltage_sens_readdata.export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- reg_fpga_voltage_sens_reset.export
- reg_fpga_voltage_sens_write_export : out std_logic; -- reg_fpga_voltage_sens_write.export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_voltage_sens_writedata.export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
- reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
- reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
- reg_10gbase_r_24_address_export : out std_logic_vector(14 downto 0); -- reg_10gbase_r_24_address.export
- reg_10gbase_r_24_clk_export : out std_logic; -- reg_10gbase_r_24_clk.export
- reg_10gbase_r_24_read_export : out std_logic; -- reg_10gbase_r_24_read.export
- reg_10gbase_r_24_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_10gbase_r_24_readdata.export
- reg_10gbase_r_24_reset_export : out std_logic; -- reg_10gbase_r_24_reset.export
- reg_10gbase_r_24_waitrequest_export : in std_logic := '0'; -- reg_10gbase_r_24_waitrequest.export
- reg_10gbase_r_24_write_export : out std_logic; -- reg_10gbase_r_24_write.export
- reg_10gbase_r_24_writedata_export : out std_logic_vector(31 downto 0); -- reg_10gbase_r_24_writedata.export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
- reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
- reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
- reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
- reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
- reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
- reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
- reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
- reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
- reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
- reg_remu_read_export : out std_logic; -- reg_remu_read.export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
- reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
- reg_remu_write_export : out std_logic; -- reg_remu_write.export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
- reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
- reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
- reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
- reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- reg_unb_pmbus_address.export
- reg_unb_pmbus_clk_export : out std_logic; -- reg_unb_pmbus_clk.export
- reg_unb_pmbus_read_export : out std_logic; -- reg_unb_pmbus_read.export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_pmbus_readdata.export
- reg_unb_pmbus_reset_export : out std_logic; -- reg_unb_pmbus_reset.export
- reg_unb_pmbus_write_export : out std_logic; -- reg_unb_pmbus_write.export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_pmbus_writedata.export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- reg_unb_sens_address.export
- reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
- reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
- reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
- reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
- reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
- reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
- reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
- reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
- reset_reset_n : in std_logic := '0'; -- reset.reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
- rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
- rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
- rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
- rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
- );
- end component qsys_unb2a_test;
+ component qsys_unb2a_test is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
+ avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
+ avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
+ avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
+ avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
+ avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
+ avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
+ avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
+ avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
+ avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
+ avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
+ avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
+ avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
+ avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
+ avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
+ avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
+ avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
+ avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
+ avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
+ avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
+ clk_clk : in std_logic := '0'; -- clk.clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
+ pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
+ pio_pps_read_export : out std_logic; -- pio_pps_read.export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
+ pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
+ pio_pps_write_export : out std_logic; -- pio_pps_write.export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
+ pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
+ pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
+ pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
+ pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
+ pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- reg_diag_data_buffer_10gbe_address.export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
+ reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
+ reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
+ reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
+ reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
+ reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
+ reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
+ reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
+ reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
+ reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
+ reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back0_address.export
+ reg_eth10g_back0_clk_export : out std_logic; -- reg_eth10g_back0_clk.export
+ reg_eth10g_back0_read_export : out std_logic; -- reg_eth10g_back0_read.export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back0_readdata.export
+ reg_eth10g_back0_reset_export : out std_logic; -- reg_eth10g_back0_reset.export
+ reg_eth10g_back0_write_export : out std_logic; -- reg_eth10g_back0_write.export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back0_writedata.export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back1_address.export
+ reg_eth10g_back1_clk_export : out std_logic; -- reg_eth10g_back1_clk.export
+ reg_eth10g_back1_read_export : out std_logic; -- reg_eth10g_back1_read.export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back1_readdata.export
+ reg_eth10g_back1_reset_export : out std_logic; -- reg_eth10g_back1_reset.export
+ reg_eth10g_back1_write_export : out std_logic; -- reg_eth10g_back1_write.export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back1_writedata.export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- reg_eth10g_qsfp_ring_address.export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- reg_eth10g_qsfp_ring_clk.export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- reg_eth10g_qsfp_ring_read.export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_qsfp_ring_readdata.export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- reg_eth10g_qsfp_ring_reset.export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- reg_eth10g_qsfp_ring_write.export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_qsfp_ring_writedata.export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- reg_fpga_temp_sens_address.export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- reg_fpga_temp_sens_clk.export
+ reg_fpga_temp_sens_read_export : out std_logic; -- reg_fpga_temp_sens_read.export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_temp_sens_readdata.export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- reg_fpga_temp_sens_reset.export
+ reg_fpga_temp_sens_write_export : out std_logic; -- reg_fpga_temp_sens_write.export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_temp_sens_writedata.export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- reg_fpga_voltage_sens_address.export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- reg_fpga_voltage_sens_clk.export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- reg_fpga_voltage_sens_read.export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_voltage_sens_readdata.export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- reg_fpga_voltage_sens_reset.export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- reg_fpga_voltage_sens_write.export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_voltage_sens_writedata.export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
+ reg_10gbase_r_24_address_export : out std_logic_vector(14 downto 0); -- reg_10gbase_r_24_address.export
+ reg_10gbase_r_24_clk_export : out std_logic; -- reg_10gbase_r_24_clk.export
+ reg_10gbase_r_24_read_export : out std_logic; -- reg_10gbase_r_24_read.export
+ reg_10gbase_r_24_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_10gbase_r_24_readdata.export
+ reg_10gbase_r_24_reset_export : out std_logic; -- reg_10gbase_r_24_reset.export
+ reg_10gbase_r_24_waitrequest_export : in std_logic := '0'; -- reg_10gbase_r_24_waitrequest.export
+ reg_10gbase_r_24_write_export : out std_logic; -- reg_10gbase_r_24_write.export
+ reg_10gbase_r_24_writedata_export : out std_logic_vector(31 downto 0); -- reg_10gbase_r_24_writedata.export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
+ reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
+ reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
+ reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
+ reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
+ reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
+ reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
+ reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
+ reg_remu_read_export : out std_logic; -- reg_remu_read.export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
+ reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
+ reg_remu_write_export : out std_logic; -- reg_remu_write.export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- reg_unb_pmbus_address.export
+ reg_unb_pmbus_clk_export : out std_logic; -- reg_unb_pmbus_clk.export
+ reg_unb_pmbus_read_export : out std_logic; -- reg_unb_pmbus_read.export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_pmbus_readdata.export
+ reg_unb_pmbus_reset_export : out std_logic; -- reg_unb_pmbus_reset.export
+ reg_unb_pmbus_write_export : out std_logic; -- reg_unb_pmbus_write.export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_pmbus_writedata.export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- reg_unb_sens_address.export
+ reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
+ reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
+ reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
+ reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
+ reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
+ reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
+ reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
+ reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
+ reset_reset_n : in std_logic := '0'; -- reset.reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
+ rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
+ rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
+ rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
+ rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
+ );
+ end component qsys_unb2a_test;
end qsys_unb2a_test_pkg;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
index 1784bbb118..93e11e3778 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, unb2a_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb2a_test_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb2a_test_pkg.all;
+ use technology_lib.technology_pkg.all;
entity udp_stream is
generic (
@@ -102,14 +102,15 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable (disabled by default)
+ '0', -- enable_sync
+ TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
constant c_nof_crc_words : natural := 1;
constant c_max_nof_words_per_block : natural := g_bg_block_size;
@@ -150,127 +151,127 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl
--- g_use_tx_seq => TRUE
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ -- g_use_tx_seq => TRUE
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
- --reg_mosi => reg_dp_offload_tx_mosi,
- --reg_miso => reg_dp_offload_tx_miso,
- --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ --reg_mosi => reg_dp_offload_tx_mosi,
+ --reg_miso => reg_dp_offload_tx_miso,
+ --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
@@ -291,52 +292,52 @@ begin
end generate;
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
index 73f726f8a9..719362d21a 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb2a_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb2a_test_pkg.all;
entity unb2a_test is
generic (
@@ -315,10 +315,10 @@ architecture str of unb2a_test is
signal i_QSFP_TX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
signal i_QSFP_RX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
- -- SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
signal serial_10G_tx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0) := (others => '0');
signal serial_10G_rx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0);
@@ -354,13 +354,13 @@ architecture str of unb2a_test is
signal reg_diag_tx_seq_10GbE_mosi : t_mem_mosi;
signal reg_diag_tx_seq_10GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
---
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
+ --
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
signal reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
signal reg_bsn_monitor_1GbE_miso : t_mem_miso;
@@ -437,383 +437,383 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2a_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_udp_offload => c_use_1GbE,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- g_dp_clk_use_pll => true,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
-
- ext_clk200 => ext_clk200,
- ext_rst200 => ext_rst200,
-
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_mm_rst => eth1g_eth0_mm_rst,
- eth1g_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_tse_miso => eth1g_eth0_tse_miso,
- eth1g_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_reg_miso => eth1g_eth0_reg_miso,
- eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_udp_offload => c_use_1GbE,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ g_dp_clk_use_pll => true,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+
+ ext_clk200 => ext_clk200,
+ ext_rst200 => ext_rst200,
+
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2a_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_technology => g_technology,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr,
- g_nof_streams_1GbE => c_unb2_board_nof_eth,
- g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
- g_nof_streams_ring => 24, -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
- g_nof_streams_back0 => 24, -- c_unb2_board_tr_back.bus_w,
- g_nof_streams_back1 => 24 -- c_unb2_board_tr_back.bus_w
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
- eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
- eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
- eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g ch1
- eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
- eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
- eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
- eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
- eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
- eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
- eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
- eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- block gen
- ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
- reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
- reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
-
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
--- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
---
--- -- dp_offload_rx
--- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-
- -- bsn
- reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
-
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- 10GbE
-
- reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
-
- reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
-
- reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
- reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
-
- reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
- reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
-
- -- eth10g status
- reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
-
- reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_back0_miso => reg_eth10g_back0_miso,
-
- reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
- reg_eth10g_back1_miso => reg_eth10g_back1_miso,
-
- -- DDR4 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR4 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
- );
-
- gen_udp_stream_1GbE : if c_use_1GbE = true generate
- u_udp_stream_1GbE : entity work.udp_stream
generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_1GbE,
- g_data_w => c_data_w_32,
- g_bg_block_size => c_def_1GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_1GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_1GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => true
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_technology => g_technology,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_nof_streams_1GbE => c_unb2_board_nof_eth,
+ g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
+ g_nof_streams_ring => 24, -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
+ g_nof_streams_back0 => 24, -- c_unb2_board_tr_back.bus_w,
+ g_nof_streams_back1 => 24 -- c_unb2_board_tr_back.bus_w
)
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g ch1
+ eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
+ eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
+ eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
+ eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
+ eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
+ eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
+ eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
+ eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- block gen
+ ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
+
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-- dp_offload_tx
--- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
-
- -- dp_offload_rx
--- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+ -- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ --
+ -- -- dp_offload_rx
+ -- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
+
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- 10GbE
+
+ reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+
+ reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
+
+ reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
+ reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
+
+ reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
+ reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
+
+ -- eth10g status
+ reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
+
+ reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_back0_miso => reg_eth10g_back0_miso,
+
+ reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
+ reg_eth10g_back1_miso => reg_eth10g_back1_miso,
+
+ -- DDR4 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR4 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
+
+ gen_udp_stream_1GbE : if c_use_1GbE = true generate
+ u_udp_stream_1GbE : entity work.udp_stream
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_1GbE,
+ g_data_w => c_data_w_32,
+ g_bg_block_size => c_def_1GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_1GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_1GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+
+ -- dp_offload_tx
+ -- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+
+ -- dp_offload_rx
+ -- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ );
end generate;
-----------------------------------------------------------------------------
@@ -830,89 +830,89 @@ begin
gen_udp_stream_10GbE : if c_use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_bg_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ID => ID,
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- loopback:
- --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
- --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
-
- -- connect to dp_offload:
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ID => ID,
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+ -- loopback:
+ --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
+ --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ -- connect to dp_offload:
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
u_tr_10GbE_qsfp_and_ring: entity unb2a_board_10gbe_lib.unb2_board_10gbe -- QSFP and Ring lines
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk => SA_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
- reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
- reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
-
- serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
- serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SA_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+ reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
+ reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+
+ serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
+ serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
+ );
gen_qsfp_wires: for i in 0 to c_nof_streams_qsfp - 1 generate
- serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
+ serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
@@ -931,161 +931,161 @@ begin
QSFP_5_TX <= i_QSFP_TX(5);
u_front_io : entity unb2a_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_qsfp_arr,
- serial_rx_arr => serial_10G_rx_qsfp_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
-
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
-
- --QSFP_SDA => QSFP_SDA,
- --QSFP_SCL => QSFP_SCL,
- --QSFP_RST => QSFP_RST,
-
- QSFP_LED => QSFP_LED
- );
-
--- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
--- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
--- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
--- END GENERATE;
---
--- i_RING_RX(0) <= RING_0_RX;
--- i_RING_RX(1) <= RING_1_RX;
--- RING_0_TX <= i_RING_TX(0);
--- RING_1_TX <= i_RING_TX(1);
---
--- u_ring_io : ENTITY unb2a_board_lib.unb2_board_ring_io
--- GENERIC MAP (
--- g_nof_ring_bus => 2--c_nof_ring_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_ring_arr,
--- serial_rx_arr => serial_10G_rx_ring_arr,
--- RING_RX => i_RING_RX,
--- RING_TX => i_RING_TX
--- );
-
--- u_tr_10GbE_back: ENTITY unb2a_board_10gbe_lib.unb2_board_10gbe -- BACK lines
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_sim_level => 1,
--- g_technology => g_technology,
--- g_nof_macs => c_nof_streams_back0,
--- g_tx_fifo_fill => c_def_10GbE_block_size,
--- g_tx_fifo_size => c_def_10GbE_block_size*2
--- )
--- PORT MAP (
--- tr_ref_clk => SB_CLK,
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
--- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
--- reg_mac_miso => reg_tr_10GbE_back0_miso,
--- reg_eth10g_mosi => reg_eth10g_back0_mosi,
--- reg_eth10g_miso => reg_eth10g_back0_miso,
--- dp_rst => dp_rst,
--- dp_clk => dp_clk,
---
--- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
----- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
---
--- serial_tx_arr => i_serial_10G_tx_back0_arr,
--- serial_rx_arr => i_serial_10G_rx_back0_arr
--- );
---
--- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
--- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
--- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
--- END GENERATE;
--- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
--- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
--- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
--- --END GENERATE;
---
--- u_back_io : ENTITY unb2a_board_lib.unb2_board_back_io
--- GENERIC MAP (
--- g_nof_back_bus => c_nof_back_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_back_arr,
--- serial_rx_arr => serial_10G_rx_back_arr,
---
--- -- Serial I/O
--- -- back transceivers
--- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
--- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
--- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
--- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
---
--- BCK_SDA => BCK_SDA,
--- BCK_SCL => BCK_SCL,
--- BCK_ERR => BCK_ERR
--- );
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_qsfp_arr,
+ serial_rx_arr => serial_10G_rx_qsfp_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
+
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
+
+ --QSFP_SDA => QSFP_SDA,
+ --QSFP_SCL => QSFP_SCL,
+ --QSFP_RST => QSFP_RST,
+
+ QSFP_LED => QSFP_LED
+ );
+
+ -- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
+ -- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
+ -- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
+ -- END GENERATE;
+ --
+ -- i_RING_RX(0) <= RING_0_RX;
+ -- i_RING_RX(1) <= RING_1_RX;
+ -- RING_0_TX <= i_RING_TX(0);
+ -- RING_1_TX <= i_RING_TX(1);
+ --
+ -- u_ring_io : ENTITY unb2a_board_lib.unb2_board_ring_io
+ -- GENERIC MAP (
+ -- g_nof_ring_bus => 2--c_nof_ring_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_ring_arr,
+ -- serial_rx_arr => serial_10G_rx_ring_arr,
+ -- RING_RX => i_RING_RX,
+ -- RING_TX => i_RING_TX
+ -- );
+
+ -- u_tr_10GbE_back: ENTITY unb2a_board_10gbe_lib.unb2_board_10gbe -- BACK lines
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_sim_level => 1,
+ -- g_technology => g_technology,
+ -- g_nof_macs => c_nof_streams_back0,
+ -- g_tx_fifo_fill => c_def_10GbE_block_size,
+ -- g_tx_fifo_size => c_def_10GbE_block_size*2
+ -- )
+ -- PORT MAP (
+ -- tr_ref_clk => SB_CLK,
+ -- mm_rst => mm_rst,
+ -- mm_clk => mm_clk,
+ -- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
+ -- reg_mac_miso => reg_tr_10GbE_back0_miso,
+ -- reg_eth10g_mosi => reg_eth10g_back0_mosi,
+ -- reg_eth10g_miso => reg_eth10g_back0_miso,
+ -- dp_rst => dp_rst,
+ -- dp_clk => dp_clk,
+ --
+ -- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ ---- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ --
+ -- serial_tx_arr => i_serial_10G_tx_back0_arr,
+ -- serial_rx_arr => i_serial_10G_rx_back0_arr
+ -- );
+ --
+ -- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
+ -- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
+ -- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
+ -- END GENERATE;
+ -- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
+ -- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
+ -- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
+ -- --END GENERATE;
+ --
+ -- u_back_io : ENTITY unb2a_board_lib.unb2_board_back_io
+ -- GENERIC MAP (
+ -- g_nof_back_bus => c_nof_back_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_back_arr,
+ -- serial_rx_arr => serial_10G_rx_back_arr,
+ --
+ -- -- Serial I/O
+ -- -- back transceivers
+ -- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
+ -- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
+ -- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ -- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ --
+ -- BCK_SDA => BCK_SDA,
+ -- BCK_SCL => BCK_SCL,
+ -- BCK_ERR => BCK_ERR
+ -- );
u_front_led : entity unb2a_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
-
- tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
- tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
- rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+
+ tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
+ rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ );
end generate;
gen_no_udp_stream_10GbE : if c_use_10GbE = false generate
u_front_io : entity unb2a_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_front_led : entity unb2a_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
end generate;
-----------------------------------------------------------------------------
@@ -1096,156 +1096,156 @@ begin
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_I,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_I_clk200,
- ctlr_rst_out => ddr_I_rst200,
-
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_I,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_I_clk200,
+ ctlr_rst_out => ddr_I_rst200,
+
+ ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
gen_stream_MB_II : if c_use_MB_II = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_II,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_II_REF_CLK,
- ctlr_ref_rst => mb_II_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_II_clk200,
- ctlr_rst_out => ddr_II_rst200,
-
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_II_IN,
- phy4_io => MB_II_IO,
- phy4_ou => MB_II_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_II,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_II_REF_CLK,
+ ctlr_ref_rst => mb_II_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_II_clk200,
+ ctlr_rst_out => ddr_II_rst200,
+
+ ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_II_IN,
+ phy4_io => MB_II_IO,
+ phy4_ou => MB_II_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
index b3bb5004d9..3a2c980274 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
@@ -20,37 +20,38 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
package unb2a_test_pkg is
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
+ constant c_hdr_field_arr : t_common_field_arr(
+ c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
diff --git a/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
index 819942904d..18b084dd0e 100644
--- a/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
@@ -43,14 +43,14 @@
--
library IEEE, common_lib, unb2a_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb2a_test is
generic (
@@ -182,142 +182,142 @@ begin
-- DUT
------------------------------------------------------------------------------
u_unb2a_test : entity work.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_sim_model_ddr => g_sim_model_ddr,
- g_ddr_MB_I => c_ddr_MB_I,
- g_ddr_MB_II => c_ddr_MB_II
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => sa_clk,
- SB_CLK => sb_clk,
- BCK_REF_CLK => bck_ref_clk,
-
- -- DDR reference clocks
- MB_I_REF_CLK => mb_I_ref_clk,
- MB_II_REF_CLK => mb_II_ref_clk,
-
- PMBUS_ALERT => '0',
-
- -- Serial I/O
- -- QSFP_0_TX => si_lpbk_0,
- -- QSFP_0_RX => si_lpbk_0,
--- QSFP_1_TX => si_lpbk_1,
--- QSFP_1_RX => si_lpbk_1,
--- QSFP_2_TX => si_lpbk_2,
--- QSFP_2_RX => si_lpbk_2,
--- QSFP_3_TX => si_lpbk_3,
--- QSFP_3_RX => si_lpbk_3,
--- QSFP_4_TX => si_lpbk_4,
--- QSFP_4_RX => si_lpbk_4,
--- QSFP_5_TX => si_lpbk_5,
--- QSFP_5_RX => si_lpbk_5,
---
--- RING_0_TX => si_lpbk_6,
--- RING_0_RX => si_lpbk_6,
--- RING_1_TX => si_lpbk_7,
--- RING_1_RX => si_lpbk_7,
---
--- BCK_TX => si_lpbk_8,
--- BCK_RX => si_lpbk_8,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- -- Leds
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_ddr_MB_I => c_ddr_MB_I,
+ g_ddr_MB_II => c_ddr_MB_II
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+ SB_CLK => sb_clk,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => mb_I_ref_clk,
+ MB_II_REF_CLK => mb_II_ref_clk,
+
+ PMBUS_ALERT => '0',
+
+ -- Serial I/O
+ -- QSFP_0_TX => si_lpbk_0,
+ -- QSFP_0_RX => si_lpbk_0,
+ -- QSFP_1_TX => si_lpbk_1,
+ -- QSFP_1_RX => si_lpbk_1,
+ -- QSFP_2_TX => si_lpbk_2,
+ -- QSFP_2_RX => si_lpbk_2,
+ -- QSFP_3_TX => si_lpbk_3,
+ -- QSFP_3_RX => si_lpbk_3,
+ -- QSFP_4_TX => si_lpbk_4,
+ -- QSFP_4_RX => si_lpbk_4,
+ -- QSFP_5_TX => si_lpbk_5,
+ -- QSFP_5_RX => si_lpbk_5,
+ --
+ -- RING_0_TX => si_lpbk_6,
+ -- RING_0_RX => si_lpbk_6,
+ -- RING_1_TX => si_lpbk_7,
+ -- RING_1_RX => si_lpbk_7,
+ --
+ -- BCK_TX => si_lpbk_8,
+ -- BCK_RX => si_lpbk_8,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ -- Leds
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- UniBoard sensors
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
------------------------------------------------------------------------------
-- UniBoard DDR4
------------------------------------------------------------------------------
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_I
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_I_OU,
- mem4_io => MB_I_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_I
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_I_OU,
+ mem4_io => MB_I_IO
+ );
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_II
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_II_OU,
- mem4_io => MB_II_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_II
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_II_OU,
+ mem4_io => MB_II_IO
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
index 2f62140372..712fe64b99 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
@@ -25,16 +25,16 @@
-- . ctrl_unb2_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
library IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb2_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb2_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb2_board is
generic (
@@ -327,15 +327,15 @@ begin
i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
u_common_areset_ext : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_ext_clk200,
- out_rst => ext_rst200
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_ext_clk200,
+ out_rst => ext_rst200
+ );
-----------------------------------------------------------------------------
-- xo_ethclk = ETH_CLK
@@ -344,15 +344,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
-- MB_I_REF_CLK --> mb_I_ref_rst
@@ -360,26 +360,26 @@ begin
-----------------------------------------------------------------------------
u_common_areset_mb_I : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_I_REF_CLK,
- out_rst => mb_I_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_I_REF_CLK,
+ out_rst => mb_I_ref_rst
+ );
u_common_areset_mb_II : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_II_REF_CLK,
- out_rst => mb_II_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_II_REF_CLK,
+ out_rst => mb_II_ref_rst
+ );
-----------------------------------------------------------------------------
-- dp_clk + dp_rst generation
@@ -393,29 +393,29 @@ begin
gen_pll: if g_sim = false and g_dp_clk_use_pll = true generate
u_unb2_board_clk200_pll : entity work.unb2_board_clk200_pll
+ generic map (
+ g_technology => g_technology,
+ g_use_fpll => true,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ port map (
+ arst => i_mm_rst,
+ clk200 => i_ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => common_areset_in_rst
+ );
+ end generate;
+
+ u_common_areset_dp_rst : entity common_lib.common_areset
generic map (
- g_technology => g_technology,
- g_use_fpll => true,
- g_clk200_phase_shift => g_dp_clk_phase
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
)
port map (
- arst => i_mm_rst,
- clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => common_areset_in_rst
+ in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
);
- end generate;
-
- u_common_areset_dp_rst : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
-----------------------------------------------------------------------------
-- mm_clk
@@ -430,48 +430,48 @@ begin
clk50; -- default
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
- mm_sim_clk <= not mm_sim_clk after 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
- mm_locked <= '0', '1' after 70 ns;
+ epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
+ clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
+ mm_sim_clk <= not mm_sim_clk after 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2_board_clk125_pll : entity work.unb2_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => epcs_clk,
+ c1_clk50 => clk50,
+ c2_clk100 => clk100,
+ c3_clk125 => clk125,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2_board_node_ctrl : entity work.unb2_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c0_clk20 => epcs_clk,
- c1_clk50 => clk50,
- c2_clk100 => clk100,
- c3_clk125 => clk125,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2_board_node_ctrl : entity work.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-----------------------------------------------------------------------------
-- System info
@@ -479,33 +479,33 @@ begin
cs_sim <= is_true(g_sim);
u_mms_unb2_board_system_info : entity work.mms_unb2_board_system_info
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
-- Red LED control
@@ -540,12 +540,12 @@ begin
led_toggle_green <= sel_a_b(g_factory_image = false, led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
-- WDI override
@@ -556,15 +556,15 @@ begin
WDI <= mm_wdi or temp_alarm or wdi_override;
u_unb2_board_wdi_reg : entity work.unb2_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
-- Remote upgrade
@@ -573,75 +573,75 @@ begin
-- So there is full control over the memory mapped registers to set start address of the flash
-- and reconfigure from that address.
u_mms_remu: entity remu_lib.mms_remu
- generic map (
- g_technology => g_technology
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
-------------------------------------------------------------------------------
---- EPCS
-------------------------------------------------------------------------------
u_mms_epcs: entity epcs_lib.mms_epcs
- generic map (
- g_technology => g_technology,
- g_protect_addr_range => g_protect_addr_range,
- g_protected_addr_lo => g_protected_addr_lo,
- g_protected_addr_hi => g_protected_addr_hi
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology,
+ g_protect_addr_range => g_protect_addr_range,
+ g_protected_addr_lo => g_protected_addr_lo,
+ g_protected_addr_hi => g_protected_addr_hi
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
------------------------------------------------------------------------------
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_technology => g_technology,
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => dp_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => dp_pps
+ );
------------------------------------------------------------------------------
-- I2C control for UniBoard sensors
@@ -650,74 +650,74 @@ begin
mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_s; -- mm_pulse_ms; ms pulse comes before the end of the I2C frame, this results in an overflow in simulation -- speed up in simulation
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => c_i2c_peripheral_sens,
- g_sens_nof_result => 40,
- g_clk_freq => g_mm_clk_freq,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_sens_mosi,
- reg_miso => reg_unb_sens_miso,
-
- -- i2c bus
- scl => SENS_SC,
- sda => SENS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => c_i2c_peripheral_sens,
+ g_sens_nof_result => 40,
+ g_clk_freq => g_mm_clk_freq,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_sens_mosi,
+ reg_miso => reg_unb_sens_miso,
+
+ -- i2c bus
+ scl => SENS_SC,
+ sda => SENS_SD
+ );
u_mms_unb2_board_pmbus : entity work.mms_unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => c_i2c_peripheral_pmbus,
- g_sens_nof_result => 42,
- g_clk_freq => g_mm_clk_freq,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_pmbus_mosi,
- reg_miso => reg_unb_pmbus_miso,
-
- -- i2c bus
- scl => PMBUS_SC,
- sda => PMBUS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => c_i2c_peripheral_pmbus,
+ g_sens_nof_result => 42,
+ g_clk_freq => g_mm_clk_freq,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_pmbus_mosi,
+ reg_miso => reg_unb_pmbus_miso,
+
+ -- i2c bus
+ scl => PMBUS_SC,
+ sda => PMBUS_SD
+ );
u_mms_unb2_fpga_sens : entity work.mms_unb2_fpga_sens
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
- mm_start => '1', -- this works
-
- -- Memory-mapped clock domain
- reg_temp_mosi => reg_fpga_temp_sens_mosi,
- reg_temp_miso => reg_fpga_temp_sens_miso,
- reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
- reg_voltage_miso => reg_fpga_voltage_sens_miso,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
+ mm_start => '1', -- this works
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
-- Ethernet 1GbE
@@ -726,18 +726,18 @@ begin
gen_tse_clk_buf: if g_tse_clk_buf = true generate
-- Separate clkbuf for the 1GbE tse_clk:
u_tse_clk_buf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => i_xo_ethclk,
- outclk => i_tse_clk
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => i_xo_ethclk,
+ outclk => i_tse_clk
+ );
end generate;
gen_tse_no_clk_buf: if g_tse_clk_buf = false generate
- i_tse_clk <= i_xo_ethclk;
+ i_tse_clk <= i_xo_ethclk;
end generate;
wire_udp_offload: for i in 0 to g_udp_offload_nof_streams - 1 generate
@@ -762,43 +762,43 @@ begin
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
u_eth : entity eth_lib.eth
- generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_frm_discard_en => true
- )
- port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT(0),
- eth_rxp => ETH_SGIN(0),
-
- -- LED interface
- tse_led => eth1g_led
- );
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_frm_discard_en => true
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => i_mm_clk, -- use mm_clk direct
+ eth_clk => i_tse_clk, -- 125 MHz clock
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT(0),
+ eth_rxp => ETH_SGIN(0),
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
end generate;
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
index f3276e7196..446b6865c4 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
@@ -23,10 +23,10 @@
-- Description: See unb2_board_sens.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_unb2_board_sens is
generic (
@@ -65,48 +65,48 @@ architecture str of mms_unb2_board_sens is
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
begin
u_unb2_board_sens_reg : entity work.unb2_board_sens_reg
- generic map (
- g_sens_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_sens_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers
- sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- sens_data => sens_data,
+ -- MM registers
+ sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ sens_data => sens_data,
- -- Max temp threshold
- temp_high => temp_high
- );
+ -- Max temp threshold
+ temp_high => temp_high
+ );
u_unb2_board_sens : entity work.unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => g_i2c_peripheral,
- g_clk_freq => g_clk_freq,
- g_temp_high => g_temp_high,
- g_sens_nof_result => g_sens_nof_result,
- g_comma_w => g_comma_w
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
- start => mm_start,
- -- i2c bus
- scl => scl,
- sda => sda,
- -- read results
- sens_evt => OPEN,
- sens_err => sens_err,
- sens_data => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => g_i2c_peripheral,
+ g_clk_freq => g_clk_freq,
+ g_temp_high => g_temp_high,
+ g_sens_nof_result => g_sens_nof_result,
+ g_comma_w => g_comma_w
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+ start => mm_start,
+ -- i2c bus
+ scl => scl,
+ sda => sda,
+ -- read results
+ sens_evt => OPEN,
+ sens_err => sens_err,
+ sens_data => sens_data
+ );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
index 8116249508..05d923ed82 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2_board_system_info is
generic (
@@ -58,7 +58,7 @@ entity mms_unb2_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb2_board_system_info;
architecture str of mms_unb2_board_system_info is
@@ -68,68 +68,69 @@ architecture str of mms_unb2_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/";
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb2_board_system_info: entity work.unb2_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb2_board_system_info_reg: entity work.unb2_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_technology => g_technology,
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
index 9697e2b7f1..a9515f45db 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -23,11 +23,11 @@
-- Description: See unb2_fpga_sens.vhd
library IEEE, technology_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2_fpga_sens is
generic (
@@ -62,51 +62,51 @@ architecture str of mms_unb2_fpga_sens is
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
begin
u_unb2_fpga_sens_reg : entity work.unb2_fpga_sens_reg
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_sens_nof_result => c_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- start => mm_start,
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_sens_nof_result => c_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ start => mm_start,
- -- Memory Mapped Slave in mm_clk domain
- sla_temp_in => reg_temp_mosi,
- sla_temp_out => reg_temp_miso,
- sla_voltage_in => reg_voltage_mosi,
- sla_voltage_out => reg_voltage_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_temp_in => reg_temp_mosi,
+ sla_temp_out => reg_temp_miso,
+ sla_voltage_in => reg_voltage_mosi,
+ sla_voltage_out => reg_voltage_miso,
- -- MM registers
- --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- --sens_data => sens_data,
+ -- MM registers
+ --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ --sens_data => sens_data,
- -- Max temp threshold
- temp_high => temp_high
- );
+ -- Max temp threshold
+ temp_high => temp_high
+ );
--- u_unb2_board_sens : ENTITY work.unb2_board_sens
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_clk_freq => g_clk_freq,
--- g_temp_high => g_temp_high,
--- g_sens_nof_result => c_sens_nof_result
--- )
--- PORT MAP (
--- clk => mm_clk,
--- rst => mm_rst,
--- start => mm_start,
--- -- i2c bus
--- scl => scl,
--- sda => sda,
--- -- read results
--- sens_evt => OPEN,
--- sens_err => sens_err,
--- sens_data => sens_data
--- );
+ -- u_unb2_board_sens : ENTITY work.unb2_board_sens
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_clk_freq => g_clk_freq,
+ -- g_temp_high => g_temp_high,
+ -- g_sens_nof_result => c_sens_nof_result
+ -- )
+ -- PORT MAP (
+ -- clk => mm_clk,
+ -- rst => mm_rst,
+ -- start => mm_start,
+ -- -- i2c bus
+ -- scl => scl,
+ -- sda => sda,
+ -- -- read results
+ -- sens_evt => OPEN,
+ -- sens_err => sens_err,
+ -- sens_data => sens_data
+ -- );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
index 9210abec47..2a38884034 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_back_io is
generic (
@@ -57,4 +57,4 @@ begin
serial_rx_arr(i * c_unb2_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
-end;
+ end;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
index 48fad46da5..26484a4d0b 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
@@ -21,17 +21,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Purpose: PLL for UniBoard node CLK input @ 125 MHz
--- Description:
--- c0 = 20 MHz
--- c1 = 50 MHz
--- c2 = 100 MHz
--- c3 = 125 MHz
---
+ -- Purpose: PLL for UniBoard node CLK input @ 125 MHz
+ -- Description:
+ -- c0 = 20 MHz
+ -- c1 = 50 MHz
+ -- c2 = 100 MHz
+ -- c3 = 125 MHz
+ --
entity unb2_board_clk125_pll is
generic (
@@ -60,46 +60,46 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk125,
- outclk => clk125buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk125,
+ outclk => clk125buf
+ );
end generate;
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
gen_fractional_pll : if g_use_fpll = true generate
u_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
end arria10;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
index 9ca4ebe75e..1b5a3d7c4a 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
@@ -21,74 +21,74 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Purpose: PLL for UniBoard node CLK input @ 200 MHz
--- Description:
--- . The PLL runs in normal mode using c0 to compensate for the internal clock
--- network delay, so that c0 = st_clk200 is aligned to the input clk200.
--- . The assumption is that default the streaming DSP will run on the 200 MHz
--- clock from the CLK input via c1 = st_clk200p.
--- . The PLL normal mode operation compensates for internal clock network
--- delays of c0. This compensations aligns c0 to inclk0. With
--- tb_unb2_board_clk200_pll.vhd it appears that the phase setting for c0 does
--- not influence the compensation. Therefore it is llso possible to use
--- g_clk200_phase_shift /= 0 and touse c0 as processing clock instead of c1.
--- . The phase offset of c0 and c1 in the clk200_pll MegaWizard component
--- can be set in steps of 11.25 degrees (and even finer):
--- g_clk200_phase_shift (for c0)
--- phase [degrees] g_clk200p_phase_shift (for c1)
--- 0 "0"
--- 11.25 "156"
--- 22.5 "313"
--- 33.75 "469"
--- 45 "625"
--- 56.25 "781"
--- 67.5 "938"
--- 78.75 "1094"
--- 90 "1250"
--- 101.25 "1406" = 1250+ 156
--- 112.5 "1563" = 1250+ 313
--- 123.75 "1719" = 1250+ 469
--- 135 "1875" = 1250+ 625
--- 146.25 "2031" = 1250+ 781
--- 157.5 "2188" = 1250+ 938
--- 168.75 "2344" = 1250+1094
--- 180 "2500" = 1250+1250
--- 191.25 "2656" = 2500+ 156
--- 202.5 "2813" = 2500+ 313
--- 213.75 "2969" = 2500+ 469
--- 225 "3125" = 2500+ 625
--- 236.25 "3281" = 2500+ 781
--- 247.5 "3438" = 2500+ 938
--- 258.75 "3594" = 2500+1094
--- 270 "3750" = 2500+1250
--- 281.25 "3906" = 3750+ 156
--- 292.5 "4063" = 3750+ 313
--- 303.75 "4219" = 3750+ 469
--- 315 "4375" = 3750+ 625
--- 326.25 "4531" = 3750+ 781
--- 337.5 "4688" = 3750+ 938
--- 348.75 "4844" = 3750+1094
--- 360 "5000" = 3750+1250
--- . With a phase offset of 22.5 degrees the c1 = clk200p is offset by a 1/16
--- period of 200 MHz, so 1/8 period of the 400 MHz DCLK from ADU and 1/4
--- period of the 800 MHz sample SCLK of ADU. This phase offset can be used
--- to achieve stable timing between the DCLK and the clk200p domain.
--- . Some DSP may also be possible at 400 MHz via st_clk400. Note that this
--- 400 MHz can also be used at places where only a little more than 200 MHz
--- would be needed, e.g. to create packets at full data rate.
--- Therefore it is not necessary to create yet another st clock frequency.
--- This to also avoid the EMI or RFI that a non integer factor of 200 MHz
--- like e.g. 250 MHz would cause.
--- . At 400 MHz ADC samples can be clocked in at 800 MSps using DDIO. At 800
--- MSps the sample period is 1250 ns. Input timing can be tuned via fixed
--- pad input delays and/or by using another phase of the PLL output clock.
--- Remarks:
--- . If necessary more 400 M clock phase could be made available, via g_sel.
---
+ -- Purpose: PLL for UniBoard node CLK input @ 200 MHz
+ -- Description:
+ -- . The PLL runs in normal mode using c0 to compensate for the internal clock
+ -- network delay, so that c0 = st_clk200 is aligned to the input clk200.
+ -- . The assumption is that default the streaming DSP will run on the 200 MHz
+ -- clock from the CLK input via c1 = st_clk200p.
+ -- . The PLL normal mode operation compensates for internal clock network
+ -- delays of c0. This compensations aligns c0 to inclk0. With
+ -- tb_unb2_board_clk200_pll.vhd it appears that the phase setting for c0 does
+ -- not influence the compensation. Therefore it is llso possible to use
+ -- g_clk200_phase_shift /= 0 and touse c0 as processing clock instead of c1.
+ -- . The phase offset of c0 and c1 in the clk200_pll MegaWizard component
+ -- can be set in steps of 11.25 degrees (and even finer):
+ -- g_clk200_phase_shift (for c0)
+ -- phase [degrees] g_clk200p_phase_shift (for c1)
+ -- 0 "0"
+ -- 11.25 "156"
+ -- 22.5 "313"
+ -- 33.75 "469"
+ -- 45 "625"
+ -- 56.25 "781"
+ -- 67.5 "938"
+ -- 78.75 "1094"
+ -- 90 "1250"
+ -- 101.25 "1406" = 1250+ 156
+ -- 112.5 "1563" = 1250+ 313
+ -- 123.75 "1719" = 1250+ 469
+ -- 135 "1875" = 1250+ 625
+ -- 146.25 "2031" = 1250+ 781
+ -- 157.5 "2188" = 1250+ 938
+ -- 168.75 "2344" = 1250+1094
+ -- 180 "2500" = 1250+1250
+ -- 191.25 "2656" = 2500+ 156
+ -- 202.5 "2813" = 2500+ 313
+ -- 213.75 "2969" = 2500+ 469
+ -- 225 "3125" = 2500+ 625
+ -- 236.25 "3281" = 2500+ 781
+ -- 247.5 "3438" = 2500+ 938
+ -- 258.75 "3594" = 2500+1094
+ -- 270 "3750" = 2500+1250
+ -- 281.25 "3906" = 3750+ 156
+ -- 292.5 "4063" = 3750+ 313
+ -- 303.75 "4219" = 3750+ 469
+ -- 315 "4375" = 3750+ 625
+ -- 326.25 "4531" = 3750+ 781
+ -- 337.5 "4688" = 3750+ 938
+ -- 348.75 "4844" = 3750+1094
+ -- 360 "5000" = 3750+1250
+ -- . With a phase offset of 22.5 degrees the c1 = clk200p is offset by a 1/16
+ -- period of 200 MHz, so 1/8 period of the 400 MHz DCLK from ADU and 1/4
+ -- period of the 800 MHz sample SCLK of ADU. This phase offset can be used
+ -- to achieve stable timing between the DCLK and the clk200p domain.
+ -- . Some DSP may also be possible at 400 MHz via st_clk400. Note that this
+ -- 400 MHz can also be used at places where only a little more than 200 MHz
+ -- would be needed, e.g. to create packets at full data rate.
+ -- Therefore it is not necessary to create yet another st clock frequency.
+ -- This to also avoid the EMI or RFI that a non integer factor of 200 MHz
+ -- like e.g. 250 MHz would cause.
+ -- . At 400 MHz ADC samples can be clocked in at 800 MSps using DDIO. At 800
+ -- MSps the sample period is 1250 ns. Input timing can be tuned via fixed
+ -- pad input delays and/or by using another phase of the PLL output clock.
+ -- Remarks:
+ -- . If necessary more 400 M clock phase could be made available, via g_sel.
+ --
entity unb2_board_clk200_pll is
generic (
@@ -136,82 +136,82 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk200,
- outclk => clk200buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk200,
+ outclk => clk200buf
+ );
end generate;
gen_st_pll : if g_use_fpll = false generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200buf,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_st_fractional_pll : if g_use_fpll = true generate
u_st_fractional_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk200
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf, -- 200 MHz
+ c0 => i_st_clk200, -- 200 MHz
+ c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
+ c2 => i_st_clk400, -- 400 MHz
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end arria10;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
index 70d83befad..ac1110c652 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
@@ -21,17 +21,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Purpose: PLL for UniBoard node CLK input @ 25 MHz
--- Description:
--- c0 = 20 MHz
--- c1 = 50 MHz
--- c2 = 100 MHz
--- c3 = 125 MHz
---
+ -- Purpose: PLL for UniBoard node CLK input @ 25 MHz
+ -- Description:
+ -- c0 = 20 MHz
+ -- c1 = 50 MHz
+ -- c2 = 100 MHz
+ -- c3 = 125 MHz
+ --
entity unb2_board_clk25_pll is
generic (
@@ -52,16 +52,16 @@ end unb2_board_clk25_pll;
architecture arria10 of unb2_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end arria10;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
index 4bacebe5af..a0ef1a7cae 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose:
--- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
--- reset_n).
--- 2) sys_rst released when the sys_clk PLL from the SOPC system has locked,
--- can be used as a system reset for the sys_clk domain.
+ -- Purpose:
+ -- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
+ -- reset_n).
+ -- 2) sys_rst released when the sys_clk PLL from the SOPC system has locked,
+ -- can be used as a system reset for the sys_clk domain.
entity unb2_board_clk_rst is
port (
@@ -55,27 +55,27 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
index 1e8e9a974c..79d90d91e0 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_front_io is
generic (
@@ -62,8 +62,8 @@ begin
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2_board_tr_qsfp.bus_w - 1 generate
- si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
- serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
-end;
+ end;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
index 226d6091e3..1ff6b5d52c 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_hmc_ctrl is
generic (
@@ -89,7 +89,7 @@ architecture rtl of unb2_board_hmc_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- );
+ );
constant c_seq_len : natural := c_SEQ'length - 1;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
index b37cfbaf8f..dcdcee8770 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose: Provide the basic node clock control (resets, pulses, WDI)
--- Description:
--- . Create mm_rst for mm_clk:
--- . Extend WDI to avoid watchdog reset during software reload
--- . Pulse every 1 us, 1 ms and 1 s
+ -- Purpose: Provide the basic node clock control (resets, pulses, WDI)
+ -- Description:
+ -- . Create mm_rst for mm_clk:
+ -- . Extend WDI to avoid watchdog reset during software reload
+ -- . Pulse every 1 us, 1 ms and 1 s
entity unb2_board_node_ctrl is
generic (
@@ -67,43 +67,43 @@ begin
mm_locked_n <= not mm_locked;
u_common_areset_mm : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => mm_clk,
- out_rst => i_mm_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => mm_clk,
+ out_rst => i_mm_rst
+ );
-- Create 1 pulse per us, per ms and per s
mm_pulse_ms <= i_mm_pulse_ms;
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_us => mm_pulse_us,
- pulse_ms => i_mm_pulse_ms,
- pulse_s => mm_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_us => mm_pulse_us,
+ pulse_ms => i_mm_pulse_ms,
+ pulse_s => mm_pulse_s
+ );
-- Toggle the WDI every 1 ms
u_unb2_board_wdi_extend : entity work.unb2_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_ms => i_mm_pulse_ms,
- wdi_in => mm_wdi_in,
- wdi_out => mm_wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_ms => i_mm_pulse_ms,
+ wdi_in => mm_wdi_in,
+ wdi_out => mm_wdi_out
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
index a936b7c0e6..e441946a14 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb2_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
@@ -74,10 +74,10 @@ package unb2_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
index 081135d117..6b22ec690c 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb2_board_pkg is
-- UniBoard
@@ -140,21 +140,23 @@ package unb2_board_pkg is
type t_c_unb2_board_system_info is record
version : natural; -- UniBoard board HW version (2 bit value)
id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
+ -- Derived ID info:
bck_id : natural; -- = id[7:2], ID part from back plane
chip_id : natural; -- = id[1:0], ID part from UniBoard
node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
is_node2 : natural; -- 1 for Node 2, else 0.
end record;
- function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info;
+ function func_unb2_board_system_info(
+ VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info;
-end unb2_board_pkg;
+ end unb2_board_pkg;
package body unb2_board_pkg is
- function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info is
+ function func_unb2_board_system_info(
+ VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info is
variable v_system_info : t_c_unb2_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
@@ -166,4 +168,4 @@ package body unb2_board_pkg is
return v_system_info;
end;
-end unb2_board_pkg;
+ end unb2_board_pkg;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
index efe7114174..770eac1e6d 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_pmbus_ctrl is
generic (
@@ -89,7 +89,7 @@ architecture rtl of unb2_board_pmbus_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- );
+ );
constant c_seq_len : natural := c_SEQ'length - 1;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
index db1d2a0252..ce6011fa73 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
@@ -21,48 +21,48 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
--- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
--- Description:
--- The testio LED on UniBoard2 is not visible via the front panel. The
--- front panel does have a dual colour LED for each QSFP lane. Therefore
--- these QSFP LEDs are used to signal some application information and lane
--- status/activity information.
---
--- LED lights:
---
--- 1) Default behaviour for all QSFP leds:
--- . off = no FPGA image is running
---
--- 2) For factory image:
--- . green off
--- . red toggling every 1 s = factory image is running (g_factory_image=TRUE)
---
--- 3) For a user image without Gbps lane functionality:
--- . red off
--- . green toggling every 1 s = user image is running (g_factory_image=FALSE and green_on_arr(I)='0' default)
---
--- 4) For a user image with Gbps lane functionality:
--- . red off
--- . green toggling every 1 s when the lane status is not OK (green_on_arr(I)=xon='0')
--- . green on continously when the lane status is OK (green_on_arr(I)=xon='1')
--- . green led goes off briefly off when there is an Tx or Rx packet (green_evt_arr(I).sop='1')
---
--- The combined colour amber (= red + green) is not used. The factory image
--- only uses the red led and the user image only uses the green led.
---
--- Each QSFP carries c_quad = 4 lanes, therefore the green led LED can only
--- signal a combined status of the lanes. The combined status eg. be:
---
--- 'and-status' = combined status is on when all lanes are on
--- 'or-status' = combined status is on when at least 1 lane is on
---
--- Choose using 'or-status', because then the LED can give lane status
--- information when less than all 4 lane are connected.
---
+ -- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
+ -- Description:
+ -- The testio LED on UniBoard2 is not visible via the front panel. The
+ -- front panel does have a dual colour LED for each QSFP lane. Therefore
+ -- these QSFP LEDs are used to signal some application information and lane
+ -- status/activity information.
+ --
+ -- LED lights:
+ --
+ -- 1) Default behaviour for all QSFP leds:
+ -- . off = no FPGA image is running
+ --
+ -- 2) For factory image:
+ -- . green off
+ -- . red toggling every 1 s = factory image is running (g_factory_image=TRUE)
+ --
+ -- 3) For a user image without Gbps lane functionality:
+ -- . red off
+ -- . green toggling every 1 s = user image is running (g_factory_image=FALSE and green_on_arr(I)='0' default)
+ --
+ -- 4) For a user image with Gbps lane functionality:
+ -- . red off
+ -- . green toggling every 1 s when the lane status is not OK (green_on_arr(I)=xon='0')
+ -- . green on continously when the lane status is OK (green_on_arr(I)=xon='1')
+ -- . green led goes off briefly off when there is an Tx or Rx packet (green_evt_arr(I).sop='1')
+ --
+ -- The combined colour amber (= red + green) is not used. The factory image
+ -- only uses the red led and the user image only uses the green led.
+ --
+ -- Each QSFP carries c_quad = 4 lanes, therefore the green led LED can only
+ -- signal a combined status of the lanes. The combined status eg. be:
+ --
+ -- 'and-status' = combined status is on when all lanes are on
+ -- 'or-status' = combined status is on when at least 1 lane is on
+ --
+ -- Choose using 'or-status', because then the LED can give lane status
+ -- information when less than all 4 lane are connected.
+ --
entity unb2_board_qsfp_leds is
generic (
@@ -107,43 +107,43 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => i_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => i_pulse_s
+ );
u_common_toggle_s : entity common_lib.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => i_pulse_s,
- out_dat => toggle_s
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => i_pulse_s,
+ out_dat => toggle_s
+ );
gen_factory_image : if g_factory_image = true generate
green_led_arr <= (others => '0');
gen_red_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
u_red_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- -- led control
- ctrl_input => toggle_s,
- -- led output
- led => red_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- led control
+ ctrl_input => toggle_s,
+ -- led output
+ led => red_led_arr(I)
+ );
end generate;
end generate;
@@ -160,20 +160,20 @@ begin
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
u_green_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => i_pulse_ms,
- -- led control
- ctrl_on => qsfp_on_arr(I),
- ctrl_evt => qsfp_evt_arr(I),
- ctrl_input => toggle_s,
- -- led output
- led => green_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => i_pulse_ms,
+ -- led control
+ ctrl_on => qsfp_on_arr(I),
+ ctrl_evt => qsfp_evt_arr(I),
+ ctrl_input => toggle_s,
+ -- led output
+ led => green_led_arr(I)
+ );
end generate;
end generate;
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
index b83c069659..00fde0bd2f 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_ring_io is
generic (
@@ -52,4 +52,4 @@ begin
serial_rx_arr(i * c_unb2_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
-end;
+ end;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
index 877028aa9c..4cf675c478 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_sens is
generic (
@@ -52,18 +52,18 @@ architecture str of unb2_board_sens is
-- I2C clock rate settings
constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
--CONSTANT c_sens_comma_w : NATURAL := 13; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
- -- 0 = no comma time
+ -- 0 = no comma time
--- octave:4> t=1/50e6
--- t = 2.0000e-08
--- octave:5> delay=2^13 * t
--- delay = 1.6384e-04
--- octave:6> delay/t
--- ans = 8192
--- octave:7> log2(ans)
--- ans = 13
--- octave:8> log2(delay/t)
--- ans = 13
+ -- octave:4> t=1/50e6
+ -- t = 2.0000e-08
+ -- octave:5> delay=2^13 * t
+ -- delay = 1.6384e-04
+ -- octave:6> delay/t
+ -- ans = 8192
+ -- octave:7> log2(ans)
+ -- ans = 13
+ -- octave:8> log2(delay/t)
+ -- ans = 13
--CONSTANT c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, g_comma_w);
@@ -78,93 +78,93 @@ architecture str of unb2_board_sens is
begin
gen_unb2_board_sens_ctrl : if g_i2c_peripheral = c_i2c_peripheral_sens generate
u_unb2_board_sens_ctrl : entity work.unb2_board_sens_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2_board_pmbus_ctrl : if g_i2c_peripheral = c_i2c_peripheral_pmbus generate
u_unb2_board_pmbus_ctrl : entity work.unb2_board_pmbus_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2_board_hmc_ctrl : if g_i2c_peripheral = c_i2c_peripheral_hmc generate
u_unb2_board_hmc_ctrl : entity work.unb2_board_hmc_ctrl
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
+ end generate;
+
+ u_i2c_smbus : entity i2c_lib.i2c_smbus
generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
+ g_i2c_phy => c_sens_phy,
+ g_clock_stretch_sense_scl => true
)
port map (
+ gs_sim => g_sim,
clk => clk,
rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
+ in_dat => smbus_in_dat,
+ in_req => smbus_in_val,
+ out_dat => smbus_out_dat,
+ out_val => smbus_out_val,
+ out_err => smbus_out_err,
+ out_ack => smbus_out_ack,
+ st_end => smbus_out_end,
+ scl => scl,
+ sda => sda
);
- end generate;
-
- u_i2c_smbus : entity i2c_lib.i2c_smbus
- generic map (
- g_i2c_phy => c_sens_phy,
- g_clock_stretch_sense_scl => true
- )
- port map (
- gs_sim => g_sim,
- clk => clk,
- rst => rst,
- in_dat => smbus_in_dat,
- in_req => smbus_in_val,
- out_dat => smbus_out_dat,
- out_val => smbus_out_val,
- out_err => smbus_out_err,
- out_ack => smbus_out_ack,
- st_end => smbus_out_end,
- scl => scl,
- sda => sda
- );
-end architecture;
+ end architecture;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
index 9da0c246c1..33716a06a3 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_sens_ctrl is
generic (
@@ -105,7 +105,7 @@ architecture rtl of unb2_board_sens_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- );
+ );
constant c_seq_len : natural := c_SEQ'length - 1;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
index 9790dc3ea0..d641807ddc 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
@@ -60,10 +60,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2_board_sens_reg is
generic (
@@ -92,13 +92,14 @@ end unb2_board_sens_reg;
architecture rtl of unb2_board_sens_reg is
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
- -- +1 to fit sens_err in the last address
+ -- +1 to fit sens_err in the last address
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_mm_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_mm_nof_dat),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_mm_nof_dat,
+ init_sl => '0');
signal i_temp_high : std_logic_vector(6 downto 0);
begin
@@ -130,14 +131,14 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
if vA = g_sens_nof_result + 1 then
- -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
- -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
- if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
- i_temp_high <= sla_in.wrdata(6 downto 0);
- end if;
+ -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
+ -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
+ if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
+ i_temp_high <= sla_in.wrdata(6 downto 0);
+ end if;
end if;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
index c3958aa407..d6cddd260d 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
@@ -21,14 +21,14 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Keep the UniBoard system info knowledge in this HDL entity and in the
--- corresponding software functions in unb_common.c,h. This avoids having to
--- define named constants for indexing the fields in the info word.
+ -- Keep the UniBoard system info knowledge in this HDL entity and in the
+ -- corresponding software functions in unb_common.c,h. This avoids having to
+ -- define named constants for indexing the fields in the info word.
entity unb2_board_system_info is
generic (
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
index 2b7a13332c..b40384049a 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_system_info_reg is
generic (
@@ -68,7 +68,7 @@ entity unb2_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb2_board_system_info_reg;
architecture rtl of unb2_board_system_info_reg is
@@ -79,11 +79,12 @@ architecture rtl of unb2_board_system_info_reg is
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0');
constant c_use_phy_w : natural := 8;
constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
index e09adb5ff9..c308456393 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose:
--- Extend the input WDI that is controlled in SW (as it should be) to avoid
--- that the watchdog reset will occur when new SW is loaded, while keeping
--- the HDL image. This component extends the last input WDI by toggling the
--- output WDI for about 2**(g_extend_w-1) ms more.
+ -- Purpose:
+ -- Extend the input WDI that is controlled in SW (as it should be) to avoid
+ -- that the watchdog reset will occur when new SW is loaded, while keeping
+ -- the HDL image. This component extends the last input WDI by toggling the
+ -- output WDI for about 2**(g_extend_w-1) ms more.
entity unb2_board_wdi_extend is
generic (
@@ -68,26 +68,26 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
index fa05af1d4f..b6565635d1 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2_board_wdi_reg is
port (
@@ -40,16 +40,17 @@ entity unb2_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb2_board_wdi_reg;
architecture rtl of unb2_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
@@ -60,7 +61,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
index 049c7da72e..22f84d19e8 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
@@ -23,11 +23,11 @@
--
library IEEE, common_lib, technology_lib, fpga_sense_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_fpga_sens_reg is
generic (
@@ -64,20 +64,20 @@ begin
temp_high <= (others => '0'); -- i_temp_high;
u_fpga_sense: entity fpga_sense_lib.fpga_sense
- generic map (
- g_technology => g_technology,
- g_sim => g_sim
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_technology => g_technology,
+ g_sim => g_sim
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- start_sense => start,
+ start_sense => start,
- reg_temp_mosi => sla_temp_in,
- reg_temp_miso => sla_temp_out,
+ reg_temp_mosi => sla_temp_in,
+ reg_temp_miso => sla_temp_out,
- reg_voltage_store_mosi => sla_voltage_in,
- reg_voltage_store_miso => sla_voltage_out
- );
+ reg_voltage_store_mosi => sla_voltage_in,
+ reg_voltage_store_miso => sla_voltage_out
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index a91ab0e90c..6e6b469c07 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -32,12 +32,12 @@ entity tb_mms_unb2_board_sens is
end tb_mms_unb2_board_sens;
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
architecture tb of tb_mms_unb2_board_sens is
constant c_sim : boolean := true; -- FALSE;
@@ -148,61 +148,61 @@ begin
-- I2C sensors master
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
- generic map (
- g_sim => c_sim,
- g_i2c_peripheral => c_i2c_peripheral_sens,
- g_sens_nof_result => 40,
- g_clk_freq => c_clk_freq,
- g_temp_high => c_temp_high,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- mm_start => start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- i2c bus
- scl => scl,
- sda => sda
- );
+ generic map (
+ g_sim => c_sim,
+ g_i2c_peripheral => c_i2c_peripheral_sens,
+ g_sens_nof_result => 40,
+ g_clk_freq => c_clk_freq,
+ g_temp_high => c_temp_high,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ mm_start => start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- i2c bus
+ scl => scl,
+ sda => sda
+ );
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => scl,
- sda => sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
index bd1504ec13..35eb1a3016 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk125_pll is
end tb_unb2_board_clk125_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk125_pll
- port map (
- arst => ext_rst,
- clk125 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk125 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
index ae4e087f1e..6dbde563b3 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk200_pll is
end tb_unb2_board_clk200_pll;
@@ -66,44 +66,44 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
index b8ea88958d..cbb9a1d472 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk25_pll is
end tb_unb2_board_clk25_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk25_pll
- port map (
- arst => ext_rst,
- clk25 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk25 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
index 1d6125db58..ed4bda1034 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_node_ctrl is
end tb_unb2_board_node_ctrl;
@@ -71,23 +71,23 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- -- MM clock domain reset
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => wdi_in,
- mm_wdi_out => wdi_out,
- -- Pulses
- mm_pulse_us => pulse_us,
- mm_pulse_ms => pulse_ms,
- mm_pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => wdi_in,
+ mm_wdi_out => wdi_out,
+ -- Pulses
+ mm_pulse_us => pulse_us,
+ mm_pulse_ms => pulse_ms,
+ mm_pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
index 2a4f41e547..d7e287a9a2 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
@@ -37,10 +37,10 @@
-- > run -a
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_unb2_board_qsfp_leds is
end tb_unb2_board_qsfp_leds;
@@ -139,48 +139,48 @@ begin
end process;
u_unb2_factory_qsfp_leds : entity work.unb2_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => factory_green_led_arr,
- red_led_arr => factory_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => true, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => factory_green_led_arr,
+ red_led_arr => factory_red_led_arr
+ );
u_unb2_user_qsfp_leds : entity work.unb2_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => user_green_led_arr,
- red_led_arr => user_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => false, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => user_green_led_arr,
+ red_led_arr => user_red_led_arr
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
index 1abc9ae0a3..f62222669d 100644
--- a/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_board_10gbe is
generic (
@@ -76,17 +76,17 @@ architecture str of unb2_board_10gbe is
signal tr_ref_rst_156 : std_logic;
begin
u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => g_technology
- )
- port map (
- refclk_644 => tr_ref_clk,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ refclk_644 => tr_ref_clk,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
index 4b7405306f..1f7787737d 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
@@ -27,16 +27,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, eth_lib, eth1g_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb2b_arp_ping is
generic (
@@ -187,130 +187,130 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_technology => g_technology,
- g_base_ip => c_base_ip,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_udp_offload => g_sim, -- use g_udp_offload to enable ETH instance in simulation
- g_udp_offload_nof_streams => 3, -- use g_udp_offload, but no UDP offload streams
- g_protect_addr_range => g_protect_addr_range,
- g_app_led_red => true,
- g_app_led_green => true
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- app_led_red => app_led_red,
- app_led_green => app_led_green,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_technology => g_technology,
+ g_base_ip => c_base_ip,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_udp_offload => g_sim, -- use g_udp_offload to enable ETH instance in simulation
+ g_udp_offload_nof_streams => 3, -- use g_udp_offload, but no UDP offload streams
+ g_protect_addr_range => g_protect_addr_range,
+ g_app_led_red => true,
+ g_app_led_green => true
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ app_led_red => app_led_red,
+ app_led_green => app_led_green,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-- normaly done by unb_os
p_wdi : process(mm_clk)
@@ -338,46 +338,46 @@ begin
--u_eth1g_master : ENTITY eth1g_lib.eth1g_master(beh)
u_eth1g_master : entity eth1g_lib.eth1g_master(rtl)
- generic map (
- g_sim => g_sim
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- tse_mosi => eth1g_tse_mosi,
- tse_miso => eth1g_tse_miso,
- reg_interrupt => eth1g_reg_interrupt,
- reg_mosi => eth1g_reg_mosi,
- reg_miso => eth1g_reg_miso,
- ram_mosi => eth1g_ram_mosi,
- ram_miso => eth1g_ram_miso,
-
- src_mac => src_mac,
- src_ip => src_ip
- );
+ generic map (
+ g_sim => g_sim
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ tse_mosi => eth1g_tse_mosi,
+ tse_miso => eth1g_tse_miso,
+ reg_interrupt => eth1g_reg_interrupt,
+ reg_mosi => eth1g_reg_mosi,
+ reg_miso => eth1g_reg_miso,
+ ram_mosi => eth1g_ram_mosi,
+ ram_miso => eth1g_ram_miso,
+
+ src_mac => src_mac,
+ src_ip => src_ip
+ );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
index e506669594..149793ffd2 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
@@ -40,19 +40,19 @@
-- > run -all
library IEEE, common_lib, dp_lib, technology_lib, eth_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity tb_eth1g is
-- Test bench control parameters
@@ -90,7 +90,7 @@ architecture tb of tb_eth1g is
-- Payload user data
constant c_tb_nof_data : natural := 0; -- nof UDP user data, nof ping padding data
constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data; -- nof IP data,
- -- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
+ -- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
constant c_tb_reply_payload : boolean := true; -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
-- Packet headers
@@ -103,15 +103,18 @@ architecture tb of tb_eth1g is
-- symbols counter ARP=0x806 IP=0x800 IP=0x800
constant c_dut_ethertype : natural := sel_n(g_data_type, 16#07F0#, 16#07F1#, c_network_eth_type_arp, c_network_eth_type_ip, c_network_eth_type_ip);
- constant c_tx_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
- src_mac => c_lcu_src_mac,
- eth_type => TO_UVEC(c_dut_ethertype, c_network_eth_type_w));
- constant c_discard_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
- src_mac => c_lcu_src_mac,
- eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w));
- constant c_exp_eth_header : t_network_eth_header := (dst_mac => c_tx_eth_header.src_mac, -- \/
- src_mac => c_tx_eth_header.dst_mac, -- /\
- eth_type => c_tx_eth_header.eth_type); -- =
+ constant c_tx_eth_header : t_network_eth_header := (
+ dst_mac => c_dut_src_mac,
+ src_mac => c_lcu_src_mac,
+ eth_type => TO_UVEC(c_dut_ethertype, c_network_eth_type_w));
+ constant c_discard_eth_header : t_network_eth_header := (
+ dst_mac => c_dut_src_mac,
+ src_mac => c_lcu_src_mac,
+ eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w));
+ constant c_exp_eth_header : t_network_eth_header := (
+ dst_mac => c_tx_eth_header.src_mac, -- \/
+ src_mac => c_tx_eth_header.dst_mac, -- /\
+ eth_type => c_tx_eth_header.eth_type); -- =
-- . IP header
constant c_lcu_ip_addr : natural := 16#05060708#; -- = 05:06:07:08
@@ -122,64 +125,70 @@ architecture tb of tb_eth1g is
-- symbols counter ARP ping=1 UDP=17
constant c_tb_ip_protocol : natural := sel_n(g_data_type, 13, 14, 15, c_network_ip_protocol_icmp, c_network_ip_protocol_udp);
- constant c_tx_ip_header : t_network_ip_header := (version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
- header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
- services => TO_UVEC(c_network_ip_services, c_network_ip_services_w),
- total_length => TO_UVEC(c_tb_ip_total_length, c_network_ip_total_length_w),
- identification => TO_UVEC(c_network_ip_identification, c_network_ip_identification_w),
- flags => TO_UVEC(c_network_ip_flags, c_network_ip_flags_w),
- fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
- time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
- protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
- header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
- src_ip_addr => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
- dst_ip_addr => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w));
-
- constant c_exp_ip_header : t_network_ip_header := (version => c_tx_ip_header.version, -- =
- header_length => c_tx_ip_header.header_length, -- =
- services => c_tx_ip_header.services, -- =
- total_length => c_tx_ip_header.total_length, -- =
- identification => c_tx_ip_header.identification, -- =
- flags => c_tx_ip_header.flags, -- =
- fragment_offset => c_tx_ip_header.fragment_offset, -- =
- time_to_live => c_tx_ip_header.time_to_live, -- =
- protocol => c_tx_ip_header.protocol, -- =
- header_checksum => c_tx_ip_header.header_checksum, -- init value
- src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
- dst_ip_addr => c_tx_ip_header.src_ip_addr); -- /\
+ constant c_tx_ip_header : t_network_ip_header := (
+ version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
+ header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
+ services => TO_UVEC(c_network_ip_services, c_network_ip_services_w),
+ total_length => TO_UVEC(c_tb_ip_total_length, c_network_ip_total_length_w),
+ identification => TO_UVEC(c_network_ip_identification, c_network_ip_identification_w),
+ flags => TO_UVEC(c_network_ip_flags, c_network_ip_flags_w),
+ fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
+ time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
+ protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
+ header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
+ src_ip_addr => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
+ dst_ip_addr => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w));
+
+ constant c_exp_ip_header : t_network_ip_header := (
+ version => c_tx_ip_header.version, -- =
+ header_length => c_tx_ip_header.header_length, -- =
+ services => c_tx_ip_header.services, -- =
+ total_length => c_tx_ip_header.total_length, -- =
+ identification => c_tx_ip_header.identification, -- =
+ flags => c_tx_ip_header.flags, -- =
+ fragment_offset => c_tx_ip_header.fragment_offset, -- =
+ time_to_live => c_tx_ip_header.time_to_live, -- =
+ protocol => c_tx_ip_header.protocol, -- =
+ header_checksum => c_tx_ip_header.header_checksum, -- init value
+ src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
+ dst_ip_addr => c_tx_ip_header.src_ip_addr); -- /\
-- . ARP packet
- constant c_tx_arp_packet : t_network_arp_packet := (htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
- ptype => TO_UVEC(c_network_arp_ptype, c_network_arp_ptype_w),
- hlen => TO_UVEC(c_network_arp_hlen, c_network_arp_hlen_w),
- plen => TO_UVEC(c_network_arp_plen, c_network_arp_plen_w),
- oper => TO_UVEC(c_network_arp_oper_request, c_network_arp_oper_w),
- sha => c_lcu_src_mac,
- spa => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
- tha => c_dut_src_mac,
- tpa => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w));
-
- constant c_exp_arp_packet : t_network_arp_packet := (htype => c_tx_arp_packet.htype,
- ptype => c_tx_arp_packet.ptype,
- hlen => c_tx_arp_packet.hlen,
- plen => c_tx_arp_packet.plen,
- oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
- sha => c_tx_arp_packet.tha, -- \/
- spa => c_tx_arp_packet.tpa, -- /\ \/
- tha => c_tx_arp_packet.sha, -- / \ /\
- tpa => c_tx_arp_packet.spa); -- / \
+ constant c_tx_arp_packet : t_network_arp_packet := (
+ htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
+ ptype => TO_UVEC(c_network_arp_ptype, c_network_arp_ptype_w),
+ hlen => TO_UVEC(c_network_arp_hlen, c_network_arp_hlen_w),
+ plen => TO_UVEC(c_network_arp_plen, c_network_arp_plen_w),
+ oper => TO_UVEC(c_network_arp_oper_request, c_network_arp_oper_w),
+ sha => c_lcu_src_mac,
+ spa => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
+ tha => c_dut_src_mac,
+ tpa => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w));
+
+ constant c_exp_arp_packet : t_network_arp_packet := (
+ htype => c_tx_arp_packet.htype,
+ ptype => c_tx_arp_packet.ptype,
+ hlen => c_tx_arp_packet.hlen,
+ plen => c_tx_arp_packet.plen,
+ oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
+ sha => c_tx_arp_packet.tha, -- \/
+ spa => c_tx_arp_packet.tpa, -- /\ \/
+ tha => c_tx_arp_packet.sha, -- / \ /\
+ tpa => c_tx_arp_packet.spa); -- / \
-- . ICMP header
- constant c_tx_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w), -- ping request
- code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
- checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
- id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
- sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
- constant c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
- code => c_tx_icmp_header.code,
- checksum => c_tx_icmp_header.checksum, -- init value
- id => c_tx_icmp_header.id,
- sequence => c_tx_icmp_header.sequence);
+ constant c_tx_icmp_header : t_network_icmp_header := (
+ msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w), -- ping request
+ code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
+ checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
+ id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
+ sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
+ constant c_exp_icmp_header : t_network_icmp_header := (
+ msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
+ code => c_tx_icmp_header.code,
+ checksum => c_tx_icmp_header.checksum, -- init value
+ id => c_tx_icmp_header.id,
+ sequence => c_tx_icmp_header.sequence);
-- . UDP header
constant c_dut_udp_port_ctrl : natural := 11; -- ETH demux UDP for control
@@ -190,15 +199,17 @@ architecture tb of tb_eth1g is
constant c_lcu_udp_port : natural := 10; -- UDP port used for src_port
constant c_dut_udp_port_st : natural := c_dut_udp_port_st0; -- UDP port used for dst_port
constant c_tb_udp_total_length : natural := c_network_udp_total_length + c_tb_nof_data;
- constant c_tx_udp_header : t_network_udp_header := (src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
- dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
- total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
- checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
-
- constant c_exp_udp_header : t_network_udp_header := (src_port => c_tx_udp_header.dst_port, -- \/
- dst_port => c_tx_udp_header.src_port, -- /\
- total_length => c_tx_udp_header.total_length, -- =
- checksum => c_tx_udp_header.checksum); -- init value
+ constant c_tx_udp_header : t_network_udp_header := (
+ src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
+ dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
+ total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
+ checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
+
+ constant c_exp_udp_header : t_network_udp_header := (
+ src_port => c_tx_udp_header.dst_port, -- \/
+ dst_port => c_tx_udp_header.src_port, -- /\
+ total_length => c_tx_udp_header.total_length, -- =
+ checksum => c_tx_udp_header.checksum); -- init value
signal tx_total_header : t_network_total_header; -- transmitted packet header
signal discard_total_header: t_network_total_header; -- transmitted packet header for to be discarded packet
@@ -320,10 +331,11 @@ begin
-- Wait for ETH init
while dut_eth_init = '1' loop wait until rising_edge(mm_clk); end loop;
-- Setup the TSE MAC
- proc_tech_tse_setup(g_technology_dut,
- c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
- c_dut_src_mac, eth_psc_access,
- mm_clk, eth_tse_miso, eth_tse_mosi);
+ proc_tech_tse_setup(
+ g_technology_dut,
+ c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
+ c_dut_src_mac, eth_psc_access,
+ mm_clk, eth_tse_miso, eth_tse_mosi);
dut_tse_init <= '0';
wait;
end process;
@@ -396,7 +408,7 @@ begin
proc_mem_mm_bus_rd_latency(c_mem_ram_rd_latency, mm_clk);
proc_mem_mm_bus_wr(c_eth_ram_tx_offset + I, TO_SINT(eth_ram_miso.rddata(c_word_w - 1 downto 0)), mm_clk, eth_ram_miso, eth_ram_mosi);
end loop;
- --ELSE
+ --ELSE
-- . only reply header
end if;
v_eth_control_word := func_eth_mm_reg_control(eth_mm_reg_control);
@@ -421,10 +433,11 @@ begin
-- Wait for reset release
while mm_rst = '1' loop wait until rising_edge(mm_clk); end loop;
-- Setup the LCU TSE MAC
- proc_tech_tse_setup(g_technology_lcu,
- c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
- c_lcu_src_mac, lcu_psc_access,
- mm_clk, lcu_tse_miso, lcu_tse_mosi);
+ proc_tech_tse_setup(
+ g_technology_lcu,
+ c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
+ c_lcu_src_mac, lcu_psc_access,
+ mm_clk, lcu_tse_miso, lcu_tse_mosi);
-- Wait for DUT init done
while dut_tse_init /= '0' loop wait until rising_edge(mm_clk); end loop;
lcu_init <= '0';
@@ -478,17 +491,17 @@ begin
proc_tech_tse_tx_packet(tx_total_header, 2, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
end if;
--- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1472, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1472, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
tx_end <= '1';
wait;
@@ -523,77 +536,77 @@ begin
end generate;
dut : entity eth_lib.eth
- generic map (
- g_technology => g_technology_dut,
- g_cross_clock_domain => c_cross_clock_domain,
- g_frm_discard_en => g_frm_discard_en
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- eth_clk => eth_clk,
- st_rst => st_rst,
- st_clk => st_clk,
- -- UDP transmit interfaceg_frm_discard_en
- -- . ST sink
- udp_tx_snk_in_arr => udp_tx_sosi_arr,
- udp_tx_snk_out_arr => udp_tx_siso_arr,
- -- UDP receive interface
- -- . ST source
- udp_rx_src_in_arr => udp_rx_siso_arr,
- udp_rx_src_out_arr => udp_rx_sosi_arr,
- -- Control Memory Mapped Slaves
- tse_sla_in => eth_tse_mosi,
- tse_sla_out => eth_tse_miso,
- reg_sla_in => eth_reg_mosi,
- reg_sla_out => eth_reg_miso,
- reg_sla_interrupt => eth_reg_interrupt,
- ram_sla_in => eth_ram_mosi,
- ram_sla_out => eth_ram_miso,
- -- Monitoring
- rx_flushed_frm_cnt => rx_pkt_flushed_cnt,
- -- PHY interface
- eth_txp => eth_txp,
- eth_rxp => eth_rxp,
- -- LED interface
- tse_led => eth_led
- );
+ generic map (
+ g_technology => g_technology_dut,
+ g_cross_clock_domain => c_cross_clock_domain,
+ g_frm_discard_en => g_frm_discard_en
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ eth_clk => eth_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+ -- UDP transmit interfaceg_frm_discard_en
+ -- . ST sink
+ udp_tx_snk_in_arr => udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => udp_tx_siso_arr,
+ -- UDP receive interface
+ -- . ST source
+ udp_rx_src_in_arr => udp_rx_siso_arr,
+ udp_rx_src_out_arr => udp_rx_sosi_arr,
+ -- Control Memory Mapped Slaves
+ tse_sla_in => eth_tse_mosi,
+ tse_sla_out => eth_tse_miso,
+ reg_sla_in => eth_reg_mosi,
+ reg_sla_out => eth_reg_miso,
+ reg_sla_interrupt => eth_reg_interrupt,
+ ram_sla_in => eth_ram_mosi,
+ ram_sla_out => eth_ram_miso,
+ -- Monitoring
+ rx_flushed_frm_cnt => rx_pkt_flushed_cnt,
+ -- PHY interface
+ eth_txp => eth_txp,
+ eth_rxp => eth_rxp,
+ -- LED interface
+ tse_led => eth_led
+ );
lcu : entity tech_tse_lib.tech_tse
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- eth_clk => eth_clk,
- tx_snk_clk => st_clk,
- rx_src_clk => st_clk,
-
- -- Memory Mapped Slave
- mm_sla_in => lcu_tse_mosi,
- mm_sla_out => lcu_tse_miso,
-
- -- MAC transmit interface
- -- . ST sink
- tx_snk_in => lcu_tx_sosi,
- tx_snk_out => lcu_tx_siso,
- -- . MAC specific
- tx_mac_in => lcu_tx_mac_in,
- tx_mac_out => lcu_tx_mac_out,
-
- -- MAC receive interface
- -- . ST Source
- rx_src_in => lcu_rx_siso,
- rx_src_out => lcu_rx_sosi,
- -- . MAC specific
- rx_mac_out => lcu_rx_mac_out,
-
- -- PHY interface
- eth_txp => lcu_txp,
- eth_rxp => lcu_rxp,
-
- tse_led => lcu_led
- );
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ eth_clk => eth_clk,
+ tx_snk_clk => st_clk,
+ rx_src_clk => st_clk,
+
+ -- Memory Mapped Slave
+ mm_sla_in => lcu_tse_mosi,
+ mm_sla_out => lcu_tse_miso,
+
+ -- MAC transmit interface
+ -- . ST sink
+ tx_snk_in => lcu_tx_sosi,
+ tx_snk_out => lcu_tx_siso,
+ -- . MAC specific
+ tx_mac_in => lcu_tx_mac_in,
+ tx_mac_out => lcu_tx_mac_out,
+
+ -- MAC receive interface
+ -- . ST Source
+ rx_src_in => lcu_rx_siso,
+ rx_src_out => lcu_rx_sosi,
+ -- . MAC specific
+ rx_mac_out => lcu_rx_mac_out,
+
+ -- PHY interface
+ eth_txp => lcu_txp,
+ eth_rxp => lcu_rxp,
+
+ tse_led => lcu_led
+ );
-- Verification
tx_pkt_cnt <= tx_pkt_cnt + 1 when lcu_tx_sosi.sop = '1' and rising_edge(st_clk);
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
index ce140222f1..5be58566e8 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
@@ -28,10 +28,10 @@
-- > run -all
library IEEE, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity tb_tb_eth1g is
generic (
@@ -46,24 +46,24 @@ architecture tb of tb_tb_eth1g is
signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
signal tb_end : std_logic := '0';
begin
--- g_technology_dut : NATURAL := c_tech_select_default;
--- g_technology_lcu : NATURAL := c_tech_select_default;
--- g_frm_discard_en : BOOLEAN := TRUE; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
--- g_flush_test_en : BOOLEAN := FALSE; -- when TRUE send many large frames to enforce flush in eth_buffer
--- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
--- -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
--- -- g_data_type = c_tb_tech_tse_data_type_counter = 1
--- -- g_data_type = c_tb_tech_tse_data_type_arp = 2
--- -- g_data_type = c_tb_tech_tse_data_type_ping = 3
--- -- g_data_type = c_tb_tech_tse_data_type_udp = 4
--- g_data_type : NATURAL := c_tb_tech_tse_data_type_udp
+ -- g_technology_dut : NATURAL := c_tech_select_default;
+ -- g_technology_lcu : NATURAL := c_tech_select_default;
+ -- g_frm_discard_en : BOOLEAN := TRUE; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+ -- g_flush_test_en : BOOLEAN := FALSE; -- when TRUE send many large frames to enforce flush in eth_buffer
+ -- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ -- -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
+ -- -- g_data_type = c_tb_tech_tse_data_type_counter = 1
+ -- -- g_data_type = c_tb_tech_tse_data_type_arp = 2
+ -- -- g_data_type = c_tb_tech_tse_data_type_ping = 3
+ -- -- g_data_type = c_tb_tech_tse_data_type_udp = 4
+ -- g_data_type : NATURAL := c_tb_tech_tse_data_type_udp
--- u_use_symbols : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_symbols) PORT MAP (tb_end_vec(0));
--- u_use_counter : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_counter) PORT MAP (tb_end_vec(1));
--- u_use_arp : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_arp ) PORT MAP (tb_end_vec(2));
+ -- u_use_symbols : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_symbols) PORT MAP (tb_end_vec(0));
+ -- u_use_counter : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_counter) PORT MAP (tb_end_vec(1));
+ -- u_use_arp : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_arp ) PORT MAP (tb_end_vec(2));
u_use_ping : entity work.tb_eth1g generic map (g_technology_dut, c_technology_lcu, true, false, false, c_tb_tech_tse_data_type_ping ) port map (tb_end_vec(3));
--- u_use_udp : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(4));
--- u_use_udp_flush : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, TRUE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(5));
+ -- u_use_udp : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(4));
+ -- u_use_udp_flush : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, TRUE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(5));
tb_end <= '1' when tb_end_vec = c_tb_end_vec else '0';
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
index 7acf42ed8e..e66babc795 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
@@ -43,31 +43,31 @@
--
library IEEE, common_lib, technology_lib, unb2b_board_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.tb_common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_unb2b_arp_ping is
- generic (
- g_frm_discard_en : boolean := false; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
- g_flush_test_en : boolean := false; -- when TRUE send many large frames to enforce flush in eth_buffer
- -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
- -- g_data_type = c_tb_tech_tse_data_type_counter = 1
- -- g_data_type = c_tb_tech_tse_data_type_arp = 2
- -- g_data_type = c_tb_tech_tse_data_type_ping = 3
- -- g_data_type = c_tb_tech_tse_data_type_udp = 4
- g_data_type : natural := c_tb_tech_tse_data_type_ping;
- g_tb_end : boolean := true -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
- );
+ generic (
+ g_frm_discard_en : boolean := false; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+ g_flush_test_en : boolean := false; -- when TRUE send many large frames to enforce flush in eth_buffer
+ -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
+ -- g_data_type = c_tb_tech_tse_data_type_counter = 1
+ -- g_data_type = c_tb_tech_tse_data_type_arp = 2
+ -- g_data_type = c_tb_tech_tse_data_type_ping = 3
+ -- g_data_type = c_tb_tech_tse_data_type_udp = 4
+ g_data_type : natural := c_tb_tech_tse_data_type_ping;
+ g_tb_end : boolean := true -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ );
port (
tb_end : out std_logic
);
@@ -187,7 +187,7 @@ architecture tb of tb_unb2b_arp_ping is
-- Payload user data
constant c_tb_nof_data : natural := 0; -- nof UDP user data, nof ping padding data
constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data; -- nof IP data,
- -- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
+ -- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
constant c_tb_reply_payload : boolean := true; -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
-- Packet headers
@@ -195,15 +195,18 @@ architecture tb of tb_unb2b_arp_ping is
-- symbols counter ARP=0x806 IP=0x800 IP=0x800
constant c_dut_ethertype : natural := sel_n(g_data_type, 16#07F0#, 16#07F1#, c_network_eth_type_arp, c_network_eth_type_ip, c_network_eth_type_ip);
- constant c_tx_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
- src_mac => c_lcu_src_mac,
- eth_type => TO_UVEC(c_dut_ethertype, c_network_eth_type_w));
- constant c_discard_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
- src_mac => c_lcu_src_mac,
- eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w));
- constant c_exp_eth_header : t_network_eth_header := (dst_mac => c_tx_eth_header.src_mac, -- \/
- src_mac => c_tx_eth_header.dst_mac, -- /\
- eth_type => c_tx_eth_header.eth_type); -- =
+ constant c_tx_eth_header : t_network_eth_header := (
+ dst_mac => c_dut_src_mac,
+ src_mac => c_lcu_src_mac,
+ eth_type => TO_UVEC(c_dut_ethertype, c_network_eth_type_w));
+ constant c_discard_eth_header : t_network_eth_header := (
+ dst_mac => c_dut_src_mac,
+ src_mac => c_lcu_src_mac,
+ eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w));
+ constant c_exp_eth_header : t_network_eth_header := (
+ dst_mac => c_tx_eth_header.src_mac, -- \/
+ src_mac => c_tx_eth_header.dst_mac, -- /\
+ eth_type => c_tx_eth_header.eth_type); -- =
-- . IP header
constant c_tb_ip_total_length : natural := c_network_ip_total_length + c_tb_ip_nof_data;
@@ -212,64 +215,70 @@ architecture tb of tb_unb2b_arp_ping is
-- symbols counter ARP ping=1 UDP=17
constant c_tb_ip_protocol : natural := sel_n(g_data_type, 13, 14, 15, c_network_ip_protocol_icmp, c_network_ip_protocol_udp);
- constant c_tx_ip_header : t_network_ip_header := (version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
- header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
- services => TO_UVEC(c_network_ip_services, c_network_ip_services_w),
- total_length => TO_UVEC(c_tb_ip_total_length, c_network_ip_total_length_w),
- identification => TO_UVEC(c_network_ip_identification, c_network_ip_identification_w),
- flags => TO_UVEC(c_network_ip_flags, c_network_ip_flags_w),
- fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
- time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
- protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
- header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
- src_ip_addr => c_lcu_src_ip,
- dst_ip_addr => c_dut_src_ip);
-
- constant c_exp_ip_header : t_network_ip_header := (version => c_tx_ip_header.version, -- =
- header_length => c_tx_ip_header.header_length, -- =
- services => c_tx_ip_header.services, -- =
- total_length => c_tx_ip_header.total_length, -- =
- identification => c_tx_ip_header.identification, -- =
- flags => c_tx_ip_header.flags, -- =
- fragment_offset => c_tx_ip_header.fragment_offset, -- =
- time_to_live => c_tx_ip_header.time_to_live, -- =
- protocol => c_tx_ip_header.protocol, -- =
- header_checksum => c_tx_ip_header.header_checksum, -- init value
- src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
- dst_ip_addr => c_tx_ip_header.src_ip_addr); -- /\
+ constant c_tx_ip_header : t_network_ip_header := (
+ version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
+ header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
+ services => TO_UVEC(c_network_ip_services, c_network_ip_services_w),
+ total_length => TO_UVEC(c_tb_ip_total_length, c_network_ip_total_length_w),
+ identification => TO_UVEC(c_network_ip_identification, c_network_ip_identification_w),
+ flags => TO_UVEC(c_network_ip_flags, c_network_ip_flags_w),
+ fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
+ time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
+ protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
+ header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
+ src_ip_addr => c_lcu_src_ip,
+ dst_ip_addr => c_dut_src_ip);
+
+ constant c_exp_ip_header : t_network_ip_header := (
+ version => c_tx_ip_header.version, -- =
+ header_length => c_tx_ip_header.header_length, -- =
+ services => c_tx_ip_header.services, -- =
+ total_length => c_tx_ip_header.total_length, -- =
+ identification => c_tx_ip_header.identification, -- =
+ flags => c_tx_ip_header.flags, -- =
+ fragment_offset => c_tx_ip_header.fragment_offset, -- =
+ time_to_live => c_tx_ip_header.time_to_live, -- =
+ protocol => c_tx_ip_header.protocol, -- =
+ header_checksum => c_tx_ip_header.header_checksum, -- init value
+ src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
+ dst_ip_addr => c_tx_ip_header.src_ip_addr); -- /\
-- . ARP packet
- constant c_tx_arp_packet : t_network_arp_packet := (htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
- ptype => TO_UVEC(c_network_arp_ptype, c_network_arp_ptype_w),
- hlen => TO_UVEC(c_network_arp_hlen, c_network_arp_hlen_w),
- plen => TO_UVEC(c_network_arp_plen, c_network_arp_plen_w),
- oper => TO_UVEC(c_network_arp_oper_request, c_network_arp_oper_w),
- sha => c_lcu_src_mac,
- spa => c_lcu_src_ip,
- tha => c_dut_src_mac,
- tpa => c_dut_src_ip);
-
- constant c_exp_arp_packet : t_network_arp_packet := (htype => c_tx_arp_packet.htype,
- ptype => c_tx_arp_packet.ptype,
- hlen => c_tx_arp_packet.hlen,
- plen => c_tx_arp_packet.plen,
- oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
- sha => c_tx_arp_packet.tha, -- \/
- spa => c_tx_arp_packet.tpa, -- /\ \/
- tha => c_tx_arp_packet.sha, -- / \ /\
- tpa => c_tx_arp_packet.spa); -- / \
+ constant c_tx_arp_packet : t_network_arp_packet := (
+ htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
+ ptype => TO_UVEC(c_network_arp_ptype, c_network_arp_ptype_w),
+ hlen => TO_UVEC(c_network_arp_hlen, c_network_arp_hlen_w),
+ plen => TO_UVEC(c_network_arp_plen, c_network_arp_plen_w),
+ oper => TO_UVEC(c_network_arp_oper_request, c_network_arp_oper_w),
+ sha => c_lcu_src_mac,
+ spa => c_lcu_src_ip,
+ tha => c_dut_src_mac,
+ tpa => c_dut_src_ip);
+
+ constant c_exp_arp_packet : t_network_arp_packet := (
+ htype => c_tx_arp_packet.htype,
+ ptype => c_tx_arp_packet.ptype,
+ hlen => c_tx_arp_packet.hlen,
+ plen => c_tx_arp_packet.plen,
+ oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
+ sha => c_tx_arp_packet.tha, -- \/
+ spa => c_tx_arp_packet.tpa, -- /\ \/
+ tha => c_tx_arp_packet.sha, -- / \ /\
+ tpa => c_tx_arp_packet.spa); -- / \
-- . ICMP header
- constant c_tx_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w), -- ping request
- code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
- checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
- id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
- sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
- constant c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
- code => c_tx_icmp_header.code,
- checksum => c_tx_icmp_header.checksum, -- init value
- id => c_tx_icmp_header.id,
- sequence => c_tx_icmp_header.sequence);
+ constant c_tx_icmp_header : t_network_icmp_header := (
+ msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w), -- ping request
+ code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
+ checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
+ id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
+ sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
+ constant c_exp_icmp_header : t_network_icmp_header := (
+ msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
+ code => c_tx_icmp_header.code,
+ checksum => c_tx_icmp_header.checksum, -- init value
+ id => c_tx_icmp_header.id,
+ sequence => c_tx_icmp_header.sequence);
-- . UDP header
constant c_dut_udp_port_ctrl : natural := 11; -- ETH demux UDP for control
@@ -277,15 +286,17 @@ architecture tb of tb_unb2b_arp_ping is
constant c_tb_udp_total_length : natural := c_network_udp_total_length + c_tb_nof_data;
- constant c_tx_udp_header : t_network_udp_header := (src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
- dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
- total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
- checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
+ constant c_tx_udp_header : t_network_udp_header := (
+ src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
+ dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
+ total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
+ checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
- constant c_exp_udp_header : t_network_udp_header := (src_port => c_tx_udp_header.dst_port, -- \/
- dst_port => c_tx_udp_header.src_port, -- /\
- total_length => c_tx_udp_header.total_length, -- =
- checksum => c_tx_udp_header.checksum); -- init value
+ constant c_exp_udp_header : t_network_udp_header := (
+ src_port => c_tx_udp_header.dst_port, -- \/
+ dst_port => c_tx_udp_header.src_port, -- /\
+ total_length => c_tx_udp_header.total_length, -- =
+ checksum => c_tx_udp_header.checksum); -- init value
signal tx_total_header : t_network_total_header; -- transmitted packet header
signal discard_total_header: t_network_total_header; -- transmitted packet header for to be discarded packet
@@ -311,37 +322,37 @@ begin
PMBUS_SD <= 'H'; -- pull up
u_dut : entity work.unb2b_arp_ping
- generic map (
- g_sim => c_sim,
- g_sim_level => c_sim_level
- )
- port map (
- -- GENERAL
- CLK => sys_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk,
- ETH_SGIN => eth_rxp_arr,
- ETH_SGOUT => eth_txp_arr,
-
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_level => c_sim_level
+ )
+ port map (
+ -- GENERAL
+ CLK => sys_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp_arr,
+ ETH_SGOUT => eth_txp_arr,
+
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- Ethernet cable between LCU and DUT
@@ -370,52 +381,53 @@ begin
while mm_rst = '1' loop wait until rising_edge(mm_clk); end loop;
-- Setup the LCU TSE MAC
- proc_tech_tse_setup(c_tech_select_default,
- c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
- c_lcu_src_mac, lcu_psc_access,
- mm_clk, lcu_tse_miso, lcu_tse_mosi);
+ proc_tech_tse_setup(
+ c_tech_select_default,
+ c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
+ c_lcu_src_mac, lcu_psc_access,
+ mm_clk, lcu_tse_miso, lcu_tse_mosi);
lcu_init <= '0';
wait;
end process;
u_lcu : entity tech_tse_lib.tech_tse
- generic map (
- g_sim => c_sim,
- g_sim_level => c_sim_level
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- eth_clk => tse_clk,
- tx_snk_clk => st_clk,
- rx_src_clk => st_clk,
-
- -- Memory Mapped Slave
- mm_sla_in => lcu_tse_mosi,
- mm_sla_out => lcu_tse_miso,
-
- -- MAC transmit interface
- -- . ST sink
- tx_snk_in => lcu_tx_sosi,
- tx_snk_out => lcu_tx_siso,
- -- . MAC specific
- tx_mac_in => lcu_tx_mac_in,
- tx_mac_out => lcu_tx_mac_out,
-
- -- MAC receive interface
- -- . ST Source
- rx_src_in => lcu_rx_siso,
- rx_src_out => lcu_rx_sosi,
- -- . MAC specific
- rx_mac_out => lcu_rx_mac_out,
-
- -- PHY interface
- eth_txp => lcu_txp,
- eth_rxp => lcu_rxp,
-
- tse_led => lcu_led
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_level => c_sim_level
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ eth_clk => tse_clk,
+ tx_snk_clk => st_clk,
+ rx_src_clk => st_clk,
+
+ -- Memory Mapped Slave
+ mm_sla_in => lcu_tse_mosi,
+ mm_sla_out => lcu_tse_miso,
+
+ -- MAC transmit interface
+ -- . ST sink
+ tx_snk_in => lcu_tx_sosi,
+ tx_snk_out => lcu_tx_siso,
+ -- . MAC specific
+ tx_mac_in => lcu_tx_mac_in,
+ tx_mac_out => lcu_tx_mac_out,
+
+ -- MAC receive interface
+ -- . ST Source
+ rx_src_in => lcu_rx_siso,
+ rx_src_out => lcu_rx_sosi,
+ -- . MAC specific
+ rx_mac_out => lcu_rx_mac_out,
+
+ -- PHY interface
+ eth_txp => lcu_txp,
+ eth_rxp => lcu_rxp,
+
+ tse_led => lcu_led
+ );
------------------------------------------------------------------------------
-- LCU transmit and receive packets
@@ -484,17 +496,17 @@ begin
proc_tech_tse_tx_packet(tx_total_header, 2, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
end if;
--- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1472, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1472, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
tx_end <= '1';
wait;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
index ccfa91c513..1706521896 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2b_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2b_heater_pkg.all;
entity mmm_unb2b_heater is
generic (
@@ -114,36 +114,46 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_reg_heater : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
- port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
+ u_mm_file_reg_heater : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
+ port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -222,7 +232,7 @@ begin
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
---c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ --c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -239,7 +249,7 @@ begin
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
---c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ --c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
@@ -308,7 +318,7 @@ begin
reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w - 1 downto 0),
reg_heater_write_export => reg_heater_mosi.wr,
reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
end str;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
index b36fb7ceda..8f29c722e4 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
@@ -20,142 +20,142 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2b_heater_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v17 QSYS builder
- -----------------------------------------------------------------------------
- component qsys_unb2b_heater is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_reset_export : out std_logic; -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_unb2b_heater;
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v17 QSYS builder
+ -----------------------------------------------------------------------------
+ component qsys_unb2b_heater is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_reset_export : out std_logic; -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_unb2b_heater;
end qsys_unb2b_heater_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
index be12b6758a..09e5a4d38a 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, util_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use util_lib.util_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use util_lib.util_heater_pkg.all;
entity unb2b_heater is
generic (
@@ -56,12 +56,12 @@ entity unb2b_heater is
TESTIO : inout std_logic_vector(c_unb2b_board_aux.testio_w - 1 downto 0);
-- I2C Interface to Sensors
--- SENS_SC : INOUT STD_LOGIC;
--- SENS_SD : INOUT STD_LOGIC;
---
--- PMBUS_SC : INOUT STD_LOGIC;
--- PMBUS_SD : INOUT STD_LOGIC;
--- PMBUS_ALERT : IN STD_LOGIC := '0';
+ -- SENS_SC : INOUT STD_LOGIC;
+ -- SENS_SD : INOUT STD_LOGIC;
+ --
+ -- PMBUS_SC : INOUT STD_LOGIC;
+ -- PMBUS_SD : INOUT STD_LOGIC;
+ -- PMBUS_ALERT : IN STD_LOGIC := '0';
-- 1GbE Control Interface
ETH_CLK : in std_logic;
@@ -161,244 +161,244 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_dp_clk_use_pll => true,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_tse_clk_buf => false, -- TRUE,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
--- SENS_SC => 'Z', --SENS_SC,
--- SENS_SD => 'Z', --SENS_SD,
--- -- PM bus
--- PMBUS_SC => 'Z', --PMBUS_SC,
--- PMBUS_SD => 'Z', --PMBUS_SD,
--- PMBUS_ALERT => 'Z', --PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_dp_clk_use_pll => true,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_tse_clk_buf => false, -- TRUE,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ -- SENS_SC => 'Z', --SENS_SC,
+ -- SENS_SD => 'Z', --SENS_SD,
+ -- -- PM bus
+ -- PMBUS_SC => 'Z', --PMBUS_SC,
+ -- PMBUS_SD => 'Z', --PMBUS_SD,
+ -- PMBUS_ALERT => 'Z', --PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2b_heater
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- heater:
- reg_heater_mosi => reg_heater_mosi,
- reg_heater_miso => reg_heater_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- heater:
+ reg_heater_mosi => reg_heater_mosi,
+ reg_heater_miso => reg_heater_miso
+ );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_heater : entity util_lib.util_heater
- generic map (
- g_technology => g_technology,
- --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
- --g_nof_mac4 => 630 --
- g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
- g_pipeline => 72, -- max 72
- g_nof_ram => 4, -- max 4
- g_nof_logic => 24 -- max 24
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- sla_in => reg_heater_mosi,
- sla_out => reg_heater_miso
- );
+ generic map (
+ g_technology => g_technology,
+ --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
+ --g_nof_mac4 => 630 --
+ g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
+ g_pipeline => 72, -- max 72
+ g_nof_ram => 4, -- max 4
+ g_nof_logic => 24 -- max 24
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ sla_in => reg_heater_mosi,
+ sla_out => reg_heater_miso
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
index aec05451ad..fd134966d5 100644
--- a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2b_heater is
- generic (
- g_design_name : string := "unb2b_heater";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2b_heater";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2b_heater;
architecture tb of tb_unb2b_heater is
@@ -181,36 +181,36 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
index 1188b1f4a3..1c2fecffe6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
@@ -1,18 +1,18 @@
- component altjesd_ss_RX_corepll is
- port (
- locked : out std_logic; -- export
- outclk_0 : out std_logic; -- clk
- outclk_1 : out std_logic; -- clk
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X' -- reset
- );
- end component altjesd_ss_RX_corepll;
+component altjesd_ss_RX_corepll is
+ port (
+ locked : out std_logic; -- export
+ outclk_0 : out std_logic; -- clk
+ outclk_1 : out std_logic; -- clk
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X' -- reset
+ );
+end component altjesd_ss_RX_corepll;
- u0 : component altjesd_ss_RX_corepll
- port map (
- locked => CONNECTED_TO_locked, -- locked.export
- outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk
- outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
- refclk => CONNECTED_TO_refclk, -- refclk.clk
- rst => CONNECTED_TO_rst -- reset.reset
- );
+u0 : component altjesd_ss_RX_corepll
+ port map (
+ locked => CONNECTED_TO_locked, -- locked.export
+ outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk
+ outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
+ refclk => CONNECTED_TO_refclk, -- refclk.clk
+ rst => CONNECTED_TO_rst -- reset.reset
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
index 4d125d7d6b..c9239eba0d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
@@ -1,14 +1,14 @@
- component altjesd_ss_RX_frame_reset is
- port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
- );
- end component altjesd_ss_RX_frame_reset;
+component altjesd_ss_RX_frame_reset is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in_reset_n : in std_logic := 'X'; -- reset_n
+ out_reset_n : out std_logic -- reset_n
+ );
+end component altjesd_ss_RX_frame_reset;
- u0 : component altjesd_ss_RX_frame_reset
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+u0 : component altjesd_ss_RX_frame_reset
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
index 2fdfadb51a..9ff4466cf1 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
@@ -1,14 +1,14 @@
- component altjesd_ss_RX_link_reset is
- port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
- );
- end component altjesd_ss_RX_link_reset;
+component altjesd_ss_RX_link_reset is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in_reset_n : in std_logic := 'X'; -- reset_n
+ out_reset_n : out std_logic -- reset_n
+ );
+end component altjesd_ss_RX_link_reset;
- u0 : component altjesd_ss_RX_link_reset
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+u0 : component altjesd_ss_RX_link_reset
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
index f5e2ba1f77..556545d436 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
@@ -1,162 +1,162 @@
- component altjesd_ss_RX_reset_seq is
- generic (
- NUM_OUTPUTS : integer := 3;
- ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
- ENABLE_ASSERTION_SEQUENCE : integer := 0;
- ENABLE_DEASSERTION_SEQUENCE : integer := 0;
- MIN_ASRT_TIME : integer := 0;
- ASRT_DELAY0 : integer := 0;
- DSRT_DELAY0 : integer := 0;
- ASRT_REMAP0 : integer := 0;
- DSRT_REMAP0 : integer := 0;
- DSRT_QUALCNT_0 : integer := 0;
- ASRT_DELAY1 : integer := 0;
- DSRT_DELAY1 : integer := 0;
- ASRT_REMAP1 : integer := 1;
- DSRT_REMAP1 : integer := 1;
- DSRT_QUALCNT_1 : integer := 0;
- ASRT_DELAY2 : integer := 0;
- DSRT_DELAY2 : integer := 0;
- ASRT_REMAP2 : integer := 2;
- DSRT_REMAP2 : integer := 2;
- DSRT_QUALCNT_2 : integer := 0;
- ASRT_DELAY3 : integer := 0;
- DSRT_DELAY3 : integer := 0;
- ASRT_REMAP3 : integer := 3;
- DSRT_REMAP3 : integer := 3;
- DSRT_QUALCNT_3 : integer := 0;
- ASRT_DELAY4 : integer := 0;
- DSRT_DELAY4 : integer := 0;
- ASRT_REMAP4 : integer := 4;
- DSRT_REMAP4 : integer := 4;
- DSRT_QUALCNT_4 : integer := 0;
- ASRT_DELAY5 : integer := 0;
- DSRT_DELAY5 : integer := 0;
- ASRT_REMAP5 : integer := 5;
- DSRT_REMAP5 : integer := 5;
- DSRT_QUALCNT_5 : integer := 0;
- ASRT_DELAY6 : integer := 0;
- DSRT_DELAY6 : integer := 0;
- ASRT_REMAP6 : integer := 6;
- DSRT_REMAP6 : integer := 6;
- DSRT_QUALCNT_6 : integer := 0;
- ASRT_DELAY7 : integer := 0;
- DSRT_DELAY7 : integer := 0;
- ASRT_REMAP7 : integer := 7;
- DSRT_REMAP7 : integer := 7;
- DSRT_QUALCNT_7 : integer := 0;
- ASRT_DELAY8 : integer := 0;
- DSRT_DELAY8 : integer := 0;
- ASRT_REMAP8 : integer := 8;
- DSRT_REMAP8 : integer := 8;
- DSRT_QUALCNT_8 : integer := 0;
- ASRT_DELAY9 : integer := 0;
- DSRT_DELAY9 : integer := 0;
- ASRT_REMAP9 : integer := 9;
- DSRT_REMAP9 : integer := 9;
- DSRT_QUALCNT_9 : integer := 0
- );
- port (
- av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_read : in std_logic := 'X'; -- read
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_write : in std_logic := 'X'; -- write
- irq : out std_logic; -- irq
- clk : in std_logic := 'X'; -- clk
- csr_reset : in std_logic := 'X'; -- reset
- reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
- reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
- reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
- reset_in0 : in std_logic := 'X'; -- reset
- reset_out0 : out std_logic; -- reset
- reset_out1 : out std_logic; -- reset
- reset_out2 : out std_logic; -- reset
- reset_out3 : out std_logic; -- reset
- reset_out4 : out std_logic; -- reset
- reset_out5 : out std_logic; -- reset
- reset_out6 : out std_logic; -- reset
- reset_out7 : out std_logic -- reset
- );
- end component altjesd_ss_RX_reset_seq;
+component altjesd_ss_RX_reset_seq is
+ generic (
+ NUM_OUTPUTS : integer := 3;
+ ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
+ ENABLE_ASSERTION_SEQUENCE : integer := 0;
+ ENABLE_DEASSERTION_SEQUENCE : integer := 0;
+ MIN_ASRT_TIME : integer := 0;
+ ASRT_DELAY0 : integer := 0;
+ DSRT_DELAY0 : integer := 0;
+ ASRT_REMAP0 : integer := 0;
+ DSRT_REMAP0 : integer := 0;
+ DSRT_QUALCNT_0 : integer := 0;
+ ASRT_DELAY1 : integer := 0;
+ DSRT_DELAY1 : integer := 0;
+ ASRT_REMAP1 : integer := 1;
+ DSRT_REMAP1 : integer := 1;
+ DSRT_QUALCNT_1 : integer := 0;
+ ASRT_DELAY2 : integer := 0;
+ DSRT_DELAY2 : integer := 0;
+ ASRT_REMAP2 : integer := 2;
+ DSRT_REMAP2 : integer := 2;
+ DSRT_QUALCNT_2 : integer := 0;
+ ASRT_DELAY3 : integer := 0;
+ DSRT_DELAY3 : integer := 0;
+ ASRT_REMAP3 : integer := 3;
+ DSRT_REMAP3 : integer := 3;
+ DSRT_QUALCNT_3 : integer := 0;
+ ASRT_DELAY4 : integer := 0;
+ DSRT_DELAY4 : integer := 0;
+ ASRT_REMAP4 : integer := 4;
+ DSRT_REMAP4 : integer := 4;
+ DSRT_QUALCNT_4 : integer := 0;
+ ASRT_DELAY5 : integer := 0;
+ DSRT_DELAY5 : integer := 0;
+ ASRT_REMAP5 : integer := 5;
+ DSRT_REMAP5 : integer := 5;
+ DSRT_QUALCNT_5 : integer := 0;
+ ASRT_DELAY6 : integer := 0;
+ DSRT_DELAY6 : integer := 0;
+ ASRT_REMAP6 : integer := 6;
+ DSRT_REMAP6 : integer := 6;
+ DSRT_QUALCNT_6 : integer := 0;
+ ASRT_DELAY7 : integer := 0;
+ DSRT_DELAY7 : integer := 0;
+ ASRT_REMAP7 : integer := 7;
+ DSRT_REMAP7 : integer := 7;
+ DSRT_QUALCNT_7 : integer := 0;
+ ASRT_DELAY8 : integer := 0;
+ DSRT_DELAY8 : integer := 0;
+ ASRT_REMAP8 : integer := 8;
+ DSRT_REMAP8 : integer := 8;
+ DSRT_QUALCNT_8 : integer := 0;
+ ASRT_DELAY9 : integer := 0;
+ DSRT_DELAY9 : integer := 0;
+ ASRT_REMAP9 : integer := 9;
+ DSRT_REMAP9 : integer := 9;
+ DSRT_QUALCNT_9 : integer := 0
+ );
+ port (
+ av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_read : in std_logic := 'X'; -- read
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_write : in std_logic := 'X'; -- write
+ irq : out std_logic; -- irq
+ clk : in std_logic := 'X'; -- clk
+ csr_reset : in std_logic := 'X'; -- reset
+ reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
+ reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
+ reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
+ reset_in0 : in std_logic := 'X'; -- reset
+ reset_out0 : out std_logic; -- reset
+ reset_out1 : out std_logic; -- reset
+ reset_out2 : out std_logic; -- reset
+ reset_out3 : out std_logic; -- reset
+ reset_out4 : out std_logic; -- reset
+ reset_out5 : out std_logic; -- reset
+ reset_out6 : out std_logic; -- reset
+ reset_out7 : out std_logic -- reset
+ );
+end component altjesd_ss_RX_reset_seq;
- u0 : component altjesd_ss_RX_reset_seq
- generic map (
- NUM_OUTPUTS => INTEGER_VALUE_FOR_NUM_OUTPUTS,
- ENABLE_DEASSERTION_INPUT_QUAL => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_INPUT_QUAL,
- ENABLE_ASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_ASSERTION_SEQUENCE,
- ENABLE_DEASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_SEQUENCE,
- MIN_ASRT_TIME => INTEGER_VALUE_FOR_MIN_ASRT_TIME,
- ASRT_DELAY0 => INTEGER_VALUE_FOR_ASRT_DELAY0,
- DSRT_DELAY0 => INTEGER_VALUE_FOR_DSRT_DELAY0,
- ASRT_REMAP0 => INTEGER_VALUE_FOR_ASRT_REMAP0,
- DSRT_REMAP0 => INTEGER_VALUE_FOR_DSRT_REMAP0,
- DSRT_QUALCNT_0 => INTEGER_VALUE_FOR_DSRT_QUALCNT_0,
- ASRT_DELAY1 => INTEGER_VALUE_FOR_ASRT_DELAY1,
- DSRT_DELAY1 => INTEGER_VALUE_FOR_DSRT_DELAY1,
- ASRT_REMAP1 => INTEGER_VALUE_FOR_ASRT_REMAP1,
- DSRT_REMAP1 => INTEGER_VALUE_FOR_DSRT_REMAP1,
- DSRT_QUALCNT_1 => INTEGER_VALUE_FOR_DSRT_QUALCNT_1,
- ASRT_DELAY2 => INTEGER_VALUE_FOR_ASRT_DELAY2,
- DSRT_DELAY2 => INTEGER_VALUE_FOR_DSRT_DELAY2,
- ASRT_REMAP2 => INTEGER_VALUE_FOR_ASRT_REMAP2,
- DSRT_REMAP2 => INTEGER_VALUE_FOR_DSRT_REMAP2,
- DSRT_QUALCNT_2 => INTEGER_VALUE_FOR_DSRT_QUALCNT_2,
- ASRT_DELAY3 => INTEGER_VALUE_FOR_ASRT_DELAY3,
- DSRT_DELAY3 => INTEGER_VALUE_FOR_DSRT_DELAY3,
- ASRT_REMAP3 => INTEGER_VALUE_FOR_ASRT_REMAP3,
- DSRT_REMAP3 => INTEGER_VALUE_FOR_DSRT_REMAP3,
- DSRT_QUALCNT_3 => INTEGER_VALUE_FOR_DSRT_QUALCNT_3,
- ASRT_DELAY4 => INTEGER_VALUE_FOR_ASRT_DELAY4,
- DSRT_DELAY4 => INTEGER_VALUE_FOR_DSRT_DELAY4,
- ASRT_REMAP4 => INTEGER_VALUE_FOR_ASRT_REMAP4,
- DSRT_REMAP4 => INTEGER_VALUE_FOR_DSRT_REMAP4,
- DSRT_QUALCNT_4 => INTEGER_VALUE_FOR_DSRT_QUALCNT_4,
- ASRT_DELAY5 => INTEGER_VALUE_FOR_ASRT_DELAY5,
- DSRT_DELAY5 => INTEGER_VALUE_FOR_DSRT_DELAY5,
- ASRT_REMAP5 => INTEGER_VALUE_FOR_ASRT_REMAP5,
- DSRT_REMAP5 => INTEGER_VALUE_FOR_DSRT_REMAP5,
- DSRT_QUALCNT_5 => INTEGER_VALUE_FOR_DSRT_QUALCNT_5,
- ASRT_DELAY6 => INTEGER_VALUE_FOR_ASRT_DELAY6,
- DSRT_DELAY6 => INTEGER_VALUE_FOR_DSRT_DELAY6,
- ASRT_REMAP6 => INTEGER_VALUE_FOR_ASRT_REMAP6,
- DSRT_REMAP6 => INTEGER_VALUE_FOR_DSRT_REMAP6,
- DSRT_QUALCNT_6 => INTEGER_VALUE_FOR_DSRT_QUALCNT_6,
- ASRT_DELAY7 => INTEGER_VALUE_FOR_ASRT_DELAY7,
- DSRT_DELAY7 => INTEGER_VALUE_FOR_DSRT_DELAY7,
- ASRT_REMAP7 => INTEGER_VALUE_FOR_ASRT_REMAP7,
- DSRT_REMAP7 => INTEGER_VALUE_FOR_DSRT_REMAP7,
- DSRT_QUALCNT_7 => INTEGER_VALUE_FOR_DSRT_QUALCNT_7,
- ASRT_DELAY8 => INTEGER_VALUE_FOR_ASRT_DELAY8,
- DSRT_DELAY8 => INTEGER_VALUE_FOR_DSRT_DELAY8,
- ASRT_REMAP8 => INTEGER_VALUE_FOR_ASRT_REMAP8,
- DSRT_REMAP8 => INTEGER_VALUE_FOR_DSRT_REMAP8,
- DSRT_QUALCNT_8 => INTEGER_VALUE_FOR_DSRT_QUALCNT_8,
- ASRT_DELAY9 => INTEGER_VALUE_FOR_ASRT_DELAY9,
- DSRT_DELAY9 => INTEGER_VALUE_FOR_DSRT_DELAY9,
- ASRT_REMAP9 => INTEGER_VALUE_FOR_ASRT_REMAP9,
- DSRT_REMAP9 => INTEGER_VALUE_FOR_DSRT_REMAP9,
- DSRT_QUALCNT_9 => INTEGER_VALUE_FOR_DSRT_QUALCNT_9
- )
- port map (
- av_address => CONNECTED_TO_av_address, -- av_csr.address
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_read => CONNECTED_TO_av_read, -- .read
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_write => CONNECTED_TO_av_write, -- .write
- irq => CONNECTED_TO_irq, -- av_csr_irq.irq
- clk => CONNECTED_TO_clk, -- clk.clk
- csr_reset => CONNECTED_TO_csr_reset, -- csr_reset.reset
- reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual, -- reset1_dsrt_qual.reset1_dsrt_qual
- reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual, -- reset2_dsrt_qual.reset2_dsrt_qual
- reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual, -- reset5_dsrt_qual.reset5_dsrt_qual
- reset_in0 => CONNECTED_TO_reset_in0, -- reset_in0.reset
- reset_out0 => CONNECTED_TO_reset_out0, -- reset_out0.reset
- reset_out1 => CONNECTED_TO_reset_out1, -- reset_out1.reset
- reset_out2 => CONNECTED_TO_reset_out2, -- reset_out2.reset
- reset_out3 => CONNECTED_TO_reset_out3, -- reset_out3.reset
- reset_out4 => CONNECTED_TO_reset_out4, -- reset_out4.reset
- reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
- reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
- reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
- );
+u0 : component altjesd_ss_RX_reset_seq
+ generic map (
+ NUM_OUTPUTS => INTEGER_VALUE_FOR_NUM_OUTPUTS,
+ ENABLE_DEASSERTION_INPUT_QUAL => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_INPUT_QUAL,
+ ENABLE_ASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_ASSERTION_SEQUENCE,
+ ENABLE_DEASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_SEQUENCE,
+ MIN_ASRT_TIME => INTEGER_VALUE_FOR_MIN_ASRT_TIME,
+ ASRT_DELAY0 => INTEGER_VALUE_FOR_ASRT_DELAY0,
+ DSRT_DELAY0 => INTEGER_VALUE_FOR_DSRT_DELAY0,
+ ASRT_REMAP0 => INTEGER_VALUE_FOR_ASRT_REMAP0,
+ DSRT_REMAP0 => INTEGER_VALUE_FOR_DSRT_REMAP0,
+ DSRT_QUALCNT_0 => INTEGER_VALUE_FOR_DSRT_QUALCNT_0,
+ ASRT_DELAY1 => INTEGER_VALUE_FOR_ASRT_DELAY1,
+ DSRT_DELAY1 => INTEGER_VALUE_FOR_DSRT_DELAY1,
+ ASRT_REMAP1 => INTEGER_VALUE_FOR_ASRT_REMAP1,
+ DSRT_REMAP1 => INTEGER_VALUE_FOR_DSRT_REMAP1,
+ DSRT_QUALCNT_1 => INTEGER_VALUE_FOR_DSRT_QUALCNT_1,
+ ASRT_DELAY2 => INTEGER_VALUE_FOR_ASRT_DELAY2,
+ DSRT_DELAY2 => INTEGER_VALUE_FOR_DSRT_DELAY2,
+ ASRT_REMAP2 => INTEGER_VALUE_FOR_ASRT_REMAP2,
+ DSRT_REMAP2 => INTEGER_VALUE_FOR_DSRT_REMAP2,
+ DSRT_QUALCNT_2 => INTEGER_VALUE_FOR_DSRT_QUALCNT_2,
+ ASRT_DELAY3 => INTEGER_VALUE_FOR_ASRT_DELAY3,
+ DSRT_DELAY3 => INTEGER_VALUE_FOR_DSRT_DELAY3,
+ ASRT_REMAP3 => INTEGER_VALUE_FOR_ASRT_REMAP3,
+ DSRT_REMAP3 => INTEGER_VALUE_FOR_DSRT_REMAP3,
+ DSRT_QUALCNT_3 => INTEGER_VALUE_FOR_DSRT_QUALCNT_3,
+ ASRT_DELAY4 => INTEGER_VALUE_FOR_ASRT_DELAY4,
+ DSRT_DELAY4 => INTEGER_VALUE_FOR_DSRT_DELAY4,
+ ASRT_REMAP4 => INTEGER_VALUE_FOR_ASRT_REMAP4,
+ DSRT_REMAP4 => INTEGER_VALUE_FOR_DSRT_REMAP4,
+ DSRT_QUALCNT_4 => INTEGER_VALUE_FOR_DSRT_QUALCNT_4,
+ ASRT_DELAY5 => INTEGER_VALUE_FOR_ASRT_DELAY5,
+ DSRT_DELAY5 => INTEGER_VALUE_FOR_DSRT_DELAY5,
+ ASRT_REMAP5 => INTEGER_VALUE_FOR_ASRT_REMAP5,
+ DSRT_REMAP5 => INTEGER_VALUE_FOR_DSRT_REMAP5,
+ DSRT_QUALCNT_5 => INTEGER_VALUE_FOR_DSRT_QUALCNT_5,
+ ASRT_DELAY6 => INTEGER_VALUE_FOR_ASRT_DELAY6,
+ DSRT_DELAY6 => INTEGER_VALUE_FOR_DSRT_DELAY6,
+ ASRT_REMAP6 => INTEGER_VALUE_FOR_ASRT_REMAP6,
+ DSRT_REMAP6 => INTEGER_VALUE_FOR_DSRT_REMAP6,
+ DSRT_QUALCNT_6 => INTEGER_VALUE_FOR_DSRT_QUALCNT_6,
+ ASRT_DELAY7 => INTEGER_VALUE_FOR_ASRT_DELAY7,
+ DSRT_DELAY7 => INTEGER_VALUE_FOR_DSRT_DELAY7,
+ ASRT_REMAP7 => INTEGER_VALUE_FOR_ASRT_REMAP7,
+ DSRT_REMAP7 => INTEGER_VALUE_FOR_DSRT_REMAP7,
+ DSRT_QUALCNT_7 => INTEGER_VALUE_FOR_DSRT_QUALCNT_7,
+ ASRT_DELAY8 => INTEGER_VALUE_FOR_ASRT_DELAY8,
+ DSRT_DELAY8 => INTEGER_VALUE_FOR_DSRT_DELAY8,
+ ASRT_REMAP8 => INTEGER_VALUE_FOR_ASRT_REMAP8,
+ DSRT_REMAP8 => INTEGER_VALUE_FOR_DSRT_REMAP8,
+ DSRT_QUALCNT_8 => INTEGER_VALUE_FOR_DSRT_QUALCNT_8,
+ ASRT_DELAY9 => INTEGER_VALUE_FOR_ASRT_DELAY9,
+ DSRT_DELAY9 => INTEGER_VALUE_FOR_DSRT_DELAY9,
+ ASRT_REMAP9 => INTEGER_VALUE_FOR_ASRT_REMAP9,
+ DSRT_REMAP9 => INTEGER_VALUE_FOR_DSRT_REMAP9,
+ DSRT_QUALCNT_9 => INTEGER_VALUE_FOR_DSRT_QUALCNT_9
+ )
+ port map (
+ av_address => CONNECTED_TO_av_address, -- av_csr.address
+ av_readdata => CONNECTED_TO_av_readdata, -- .readdata
+ av_read => CONNECTED_TO_av_read, -- .read
+ av_writedata => CONNECTED_TO_av_writedata, -- .writedata
+ av_write => CONNECTED_TO_av_write, -- .write
+ irq => CONNECTED_TO_irq, -- av_csr_irq.irq
+ clk => CONNECTED_TO_clk, -- clk.clk
+ csr_reset => CONNECTED_TO_csr_reset, -- csr_reset.reset
+ reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual, -- reset1_dsrt_qual.reset1_dsrt_qual
+ reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual, -- reset2_dsrt_qual.reset2_dsrt_qual
+ reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual, -- reset5_dsrt_qual.reset5_dsrt_qual
+ reset_in0 => CONNECTED_TO_reset_in0, -- reset_in0.reset
+ reset_out0 => CONNECTED_TO_reset_out0, -- reset_out0.reset
+ reset_out1 => CONNECTED_TO_reset_out1, -- reset_out1.reset
+ reset_out2 => CONNECTED_TO_reset_out2, -- reset_out2.reset
+ reset_out3 => CONNECTED_TO_reset_out3, -- reset_out3.reset
+ reset_out4 => CONNECTED_TO_reset_out4, -- reset_out4.reset
+ reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
+ reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
+ reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
index e49f93a337..bbdcb4db80 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
@@ -1,24 +1,24 @@
- component altjesd_ss_RX_xcvr_reset_control is
- port (
- clock : in std_logic := 'X'; -- clk
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- reset : in std_logic := 'X'; -- reset
- rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_cal_busy
- rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_ready : out std_logic_vector(0 downto 0) -- rx_ready
- );
- end component altjesd_ss_RX_xcvr_reset_control;
+component altjesd_ss_RX_xcvr_reset_control is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ reset : in std_logic := 'X'; -- reset
+ rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_cal_busy
+ rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_ready : out std_logic_vector(0 downto 0) -- rx_ready
+ );
+end component altjesd_ss_RX_xcvr_reset_control;
- u0 : component altjesd_ss_RX_xcvr_reset_control
- port map (
- clock => CONNECTED_TO_clock, -- clock.clk
- pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
- reset => CONNECTED_TO_reset, -- reset.reset
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
- );
+u0 : component altjesd_ss_RX_xcvr_reset_control
+ port map (
+ clock => CONNECTED_TO_clock, -- clock.clk
+ pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
+ reset => CONNECTED_TO_reset, -- reset.reset
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
index af64e25109..fa71f3dded 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
@@ -1,16 +1,16 @@
- component device_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component device_clk;
+component device_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component device_clk;
- u0 : component device_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component device_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
index 26992b63a4..59df25d1b2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
@@ -1,16 +1,16 @@
- component frame_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component frame_clk;
+component frame_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component frame_clk;
- u0 : component frame_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component frame_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
index 745dc1937c..a7de702cec 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
@@ -1,100 +1,100 @@
- component jesd is
- port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
- );
- end component jesd;
+component jesd is
+ port (
+ alldev_lane_aligned : in std_logic := 'X'; -- export
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ dev_lane_aligned : out std_logic; -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_rx_avs_read : in std_logic := 'X'; -- read
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_rx_avs_write : in std_logic := 'X'; -- write
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_frame_error : in std_logic := 'X'; -- export
+ jesd204_rx_int : out std_logic; -- irq
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ jesd204_rx_link_valid : out std_logic; -- valid
+ jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ rxlink_clk : in std_logic := 'X'; -- clk
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxphy_clk : out std_logic_vector(0 downto 0); -- export
+ sof : out std_logic_vector(3 downto 0); -- export
+ somf : out std_logic_vector(3 downto 0); -- export
+ sysref : in std_logic := 'X' -- export
+ );
+end component jesd;
- u0 : component jesd
- port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
- );
+u0 : component jesd
+ port map (
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
+ csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
+ csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
+ csr_f => CONNECTED_TO_csr_f, -- csr_f.export
+ csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
+ csr_k => CONNECTED_TO_csr_k, -- csr_k.export
+ csr_l => CONNECTED_TO_csr_l, -- csr_l.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
+ csr_m => CONNECTED_TO_csr_m, -- csr_m.export
+ csr_n => CONNECTED_TO_csr_n, -- csr_n.export
+ csr_np => CONNECTED_TO_csr_np, -- csr_np.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
+ csr_s => CONNECTED_TO_csr_s, -- csr_s.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
+ rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
+ rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
+ rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
+ sof => CONNECTED_TO_sof, -- sof.export
+ somf => CONNECTED_TO_somf, -- somf.export
+ sysref => CONNECTED_TO_sysref -- sysref.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
index acbc33a2d1..c5f8f7bcb0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
@@ -1,16 +1,16 @@
- component link_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component link_clk;
+component link_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component link_clk;
- u0 : component link_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component link_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
index 42aae3ddf0..2d82124533 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_avs_common_mm_0 is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_common_mm_0;
+component qsys_unb2b_minimal_avs_common_mm_0 is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_avs_common_mm_0;
- u0 : component qsys_unb2b_minimal_avs_common_mm_0
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_avs_common_mm_0
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
index 4ddaf7fa7d..a838049964 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_avs_common_mm_1 is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_common_mm_1;
+component qsys_unb2b_minimal_avs_common_mm_1 is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_avs_common_mm_1;
- u0 : component qsys_unb2b_minimal_avs_common_mm_1
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_avs_common_mm_1
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
index d648f26fb1..97ced47767 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
@@ -26,10 +26,10 @@
-- . The avs2_eth_coe_hw.tcl determines the read latency per port
library IEEE, common_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use work.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use work.eth_pkg.all;
entity avs2_eth_coe is
port (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
index e879f1b9ed..7f2c37e56a 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
@@ -23,9 +23,9 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_network_layers_pkg is
-- All *_len constants are in nof octets = nof bytes = c_8 bits
@@ -85,9 +85,10 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001");
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -134,221 +135,225 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
- constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
- c_network_ip_identification_len + c_network_ip_flags_fragment_len +
- c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
- c_network_ip_addr_len +
- c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
- -- default field values
- constant c_network_ip_version : natural := 4; -- 4 = IPv4,
- constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
- constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
- constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
- constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
- constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
- constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
- constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
- constant c_network_ip_header_checksum : natural := 0; -- init value
-
- -- useful field values
- constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
- constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
- constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
-
- constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
-
- type t_network_ip_header is record
- version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
- header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
- services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
- total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
- identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
- flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
- fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
- time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
- protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
- header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
- src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- end record;
-
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
-
- ------------------------------------------------------------------------------
- -- ARP Packet
- --
- -- 0 7 8 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Hardware Type | Protocol Type | 4
- -- |----------------------------------------------------------------------|
- -- | HW Addr Len | Prot Addr Len | Operation | 5
- -- |----------------------------------------------------------------------|
- -- | Sender Hardware Address | 6
- -- | ------------------------------------|
- -- | | | 7
- -- |---------------------------------/ /----------------------------------|
- -- | Sender Protocol Address | | 8
- -- |----------------------------------- |
- -- | Target Hardware Address | 9
- -- |----------------------------------------------------------------------|
- -- | Target Protocol Address | 10
- -- |----------------------------------------------------------------------|
- --
- -- Note that ARP header = ARP packet, because ARP has no payload
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_arp_htype_len : natural := 2;
- constant c_network_arp_htype_w : natural := c_network_arp_htype_len * c_8;
- constant c_network_arp_ptype_len : natural := 2;
- constant c_network_arp_ptype_w : natural := c_network_arp_ptype_len * c_8;
- constant c_network_arp_hlen_len : natural := 1;
- constant c_network_arp_hlen_w : natural := c_network_arp_hlen_len * c_8;
- constant c_network_arp_plen_len : natural := 1;
- constant c_network_arp_plen_w : natural := c_network_arp_plen_len * c_8;
- constant c_network_arp_oper_len : natural := 2;
- constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
-
- -- [0:15] [16:31]
- constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
- c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-
- -- default field values
- constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
- constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
- constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
- constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
- constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
- constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
-
- -- useful field values
- constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
- constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
-
- type t_network_arp_packet is record
- htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
- ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
- hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
- plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
- oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
- sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
- spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
- tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
- tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
- end record;
-
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
-
- ------------------------------------------------------------------------------
- -- ICMP (for ping)
- --
- -- 0 7 8 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Type | Code | Checksum | 9
- -- |----------------------------------------------------------------------|
- -- | ID | Sequence | 10
- -- |----------------------------------------------------------------------|
- -- | |
- -- | ICMP Payload (padding data) |
- -- | |
- -- |------------------------------------------------------------ // ------|
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_icmp_msg_type_len : natural := 1;
- constant c_network_icmp_msg_type_w : natural := c_network_icmp_msg_type_len * c_8;
- constant c_network_icmp_code_len : natural := 1;
- constant c_network_icmp_code_w : natural := c_network_icmp_code_len * c_8;
- constant c_network_icmp_checksum_len : natural := 2;
- constant c_network_icmp_checksum_w : natural := c_network_icmp_checksum_len * c_8;
- constant c_network_icmp_id_len : natural := 2;
- constant c_network_icmp_id_w : natural := c_network_icmp_id_len * c_8;
- constant c_network_icmp_sequence_len : natural := 2;
- constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
- constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
- c_network_icmp_id_len + c_network_icmp_sequence_len;
-
- -- default field values
- constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
- constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
- constant c_network_icmp_checksum : natural := 0; -- init value
-
- -- useful field values
- constant c_network_icmp_code : natural := 0; -- default
- constant c_network_icmp_id : natural := 3; -- arbitrary value
- constant c_network_icmp_sequence : natural := 4; -- arbitrary value
-
- type t_network_icmp_header is record
- msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
- code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
- checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
- id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
- sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
- end record;
-
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
-
- ------------------------------------------------------------------------------
- -- UDP Packet
- --
- -- 0 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Source Port | Destination Port | 9
- -- |----------------------------------------------------------------------|
- -- | Total Length | Checksum | 10
- -- |----------------------------------------------------------------------|
- -- | |
- -- | UDP Payload |
- -- | |
- -- |----------------------------------------------------------- // -------|
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_udp_port_len : natural := 2;
- constant c_network_udp_port_w : natural := c_network_udp_port_len * c_8;
- constant c_network_udp_total_length_len : natural := 2;
- constant c_network_udp_total_length_w : natural := c_network_udp_total_length_len * c_8;
- constant c_network_udp_checksum_len : natural := 2;
- constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
-
- -- [0:15] [16:31]
- constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
-
- -- default field values
- constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
- constant c_network_udp_checksum : natural := 0; -- init value
-
- -- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
-
- constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
- constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
- constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
-
- type t_network_udp_header is record
- src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
- checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
- end record;
-
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ -- [0:7] [8:15] [16:31]
+ constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
+ c_network_ip_identification_len + c_network_ip_flags_fragment_len +
+ c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
+ c_network_ip_addr_len +
+ c_network_ip_addr_len;
+ -- = c_network_ip_header_length * c_word_sz = 20
+ -- default field values
+ constant c_network_ip_version : natural := 4; -- 4 = IPv4,
+ constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
+ constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
+ constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
+ constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
+ constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
+ constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
+ constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
+ constant c_network_ip_header_checksum : natural := 0; -- init value
+
+ -- useful field values
+ constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
+ constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
+ constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
+
+ constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
+
+ type t_network_ip_header is record
+ version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
+ header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
+ services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
+ total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
+ identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
+ flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
+ fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
+ time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
+ protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
+ header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
+ src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ end record;
+
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001", "0001", "00000001", "0000000000000001",
+ "0000000000000001", "001", "0000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- ARP Packet
+ --
+ -- 0 7 8 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Hardware Type | Protocol Type | 4
+ -- |----------------------------------------------------------------------|
+ -- | HW Addr Len | Prot Addr Len | Operation | 5
+ -- |----------------------------------------------------------------------|
+ -- | Sender Hardware Address | 6
+ -- | ------------------------------------|
+ -- | | | 7
+ -- |---------------------------------/ /----------------------------------|
+ -- | Sender Protocol Address | | 8
+ -- |----------------------------------- |
+ -- | Target Hardware Address | 9
+ -- |----------------------------------------------------------------------|
+ -- | Target Protocol Address | 10
+ -- |----------------------------------------------------------------------|
+ --
+ -- Note that ARP header = ARP packet, because ARP has no payload
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_arp_htype_len : natural := 2;
+ constant c_network_arp_htype_w : natural := c_network_arp_htype_len * c_8;
+ constant c_network_arp_ptype_len : natural := 2;
+ constant c_network_arp_ptype_w : natural := c_network_arp_ptype_len * c_8;
+ constant c_network_arp_hlen_len : natural := 1;
+ constant c_network_arp_hlen_w : natural := c_network_arp_hlen_len * c_8;
+ constant c_network_arp_plen_len : natural := 1;
+ constant c_network_arp_plen_w : natural := c_network_arp_plen_len * c_8;
+ constant c_network_arp_oper_len : natural := 2;
+ constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
+
+ -- [0:15] [16:31]
+ constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
+ c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len;
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+
+ -- default field values
+ constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
+ constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
+ constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
+ constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
+ constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
+ constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
+
+ -- useful field values
+ constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
+ constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
+
+ type t_network_arp_packet is record
+ htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
+ ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
+ hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
+ plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
+ oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
+ sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
+ spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
+ tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
+ tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
+ end record;
+
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001", "0000000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- ICMP (for ping)
+ --
+ -- 0 7 8 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Type | Code | Checksum | 9
+ -- |----------------------------------------------------------------------|
+ -- | ID | Sequence | 10
+ -- |----------------------------------------------------------------------|
+ -- | |
+ -- | ICMP Payload (padding data) |
+ -- | |
+ -- |------------------------------------------------------------ // ------|
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_icmp_msg_type_len : natural := 1;
+ constant c_network_icmp_msg_type_w : natural := c_network_icmp_msg_type_len * c_8;
+ constant c_network_icmp_code_len : natural := 1;
+ constant c_network_icmp_code_w : natural := c_network_icmp_code_len * c_8;
+ constant c_network_icmp_checksum_len : natural := 2;
+ constant c_network_icmp_checksum_w : natural := c_network_icmp_checksum_len * c_8;
+ constant c_network_icmp_id_len : natural := 2;
+ constant c_network_icmp_id_w : natural := c_network_icmp_id_len * c_8;
+ constant c_network_icmp_sequence_len : natural := 2;
+ constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
+ constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
+ c_network_icmp_id_len + c_network_icmp_sequence_len;
+
+ -- default field values
+ constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
+ constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
+ constant c_network_icmp_checksum : natural := 0; -- init value
+
+ -- useful field values
+ constant c_network_icmp_code : natural := 0; -- default
+ constant c_network_icmp_id : natural := 3; -- arbitrary value
+ constant c_network_icmp_sequence : natural := 4; -- arbitrary value
+
+ type t_network_icmp_header is record
+ msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
+ code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
+ checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
+ id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
+ sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
+ end record;
+
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001", "00000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- UDP Packet
+ --
+ -- 0 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Source Port | Destination Port | 9
+ -- |----------------------------------------------------------------------|
+ -- | Total Length | Checksum | 10
+ -- |----------------------------------------------------------------------|
+ -- | |
+ -- | UDP Payload |
+ -- | |
+ -- |----------------------------------------------------------- // -------|
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_udp_port_len : natural := 2;
+ constant c_network_udp_port_w : natural := c_network_udp_port_len * c_8;
+ constant c_network_udp_total_length_len : natural := 2;
+ constant c_network_udp_total_length_w : natural := c_network_udp_total_length_len * c_8;
+ constant c_network_udp_checksum_len : natural := 2;
+ constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
+
+ -- [0:15] [16:31]
+ constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
+ c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+
+ -- default field values
+ constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
+ constant c_network_udp_checksum : natural := 0; -- init value
+
+ -- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
+
+ constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
+ constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
+ constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
+
+ type t_network_udp_header is record
+ src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
+ dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
+ total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
+ checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
+ end record;
+
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
end common_network_layers_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index 4bd7e15cc8..d6ca1b9008 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -30,9 +30,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
-- CONSTANT DECLARATIONS ----------------------------------------------------
@@ -332,7 +332,7 @@ package common_pkg is
function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
--- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
+ -- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
-- appropriate approach is to ignore the MSbit sign and just keep the LS part. For too large values this
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
@@ -353,7 +353,7 @@ package common_pkg is
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
+ -- Used in common_add_sub.vhd
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
@@ -429,20 +429,22 @@ package common_pkg is
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
function func_common_reorder2_is_there(I, J : natural) return boolean;
@@ -452,9 +454,10 @@ package common_pkg is
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
@@ -465,38 +468,38 @@ package body common_pkg is
end;
function ceil_pow2(n : integer) return natural is
- -- Also allows negative exponents and rounds up before returning the value
+ -- Also allows negative exponents and rounds up before returning the value
begin
return natural(integer(ceil(2**real(n))));
end;
function true_log2(n : natural) return natural is
- -- Purpose: For calculating extra vector width of existing vector
- -- Description: Return mathematical ceil(log2(n))
- -- n log2()
- -- 0 -> -oo --> FAILURE
- -- 1 -> 0
- -- 2 -> 1
- -- 3 -> 2
- -- 4 -> 2
- -- 5 -> 3
- -- 6 -> 3
- -- 7 -> 3
- -- 8 -> 3
- -- 9 -> 4
- -- etc, up to n = NATURAL'HIGH = 2**31-1
+ -- Purpose: For calculating extra vector width of existing vector
+ -- Description: Return mathematical ceil(log2(n))
+ -- n log2()
+ -- 0 -> -oo --> FAILURE
+ -- 1 -> 0
+ -- 2 -> 1
+ -- 3 -> 2
+ -- 4 -> 2
+ -- 5 -> 3
+ -- 6 -> 3
+ -- 7 -> 3
+ -- 8 -> 3
+ -- 9 -> 4
+ -- etc, up to n = NATURAL'HIGH = 2**31-1
begin
return natural(integer(ceil(log2(real(n)))));
end;
function ceil_log2(n : natural) return natural is
- -- Purpose: For calculating vector width of new vector
- -- Description:
- -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
- -- the vector width width for 1 address, to avoid NULL array for single
- -- word register address.
- -- If n = 0, return 0 so we get a NULL array when using
- -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
+ -- Purpose: For calculating vector width of new vector
+ -- Description:
+ -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
+ -- the vector width width for 1 address, to avoid NULL array for single
+ -- word register address.
+ -- If n = 0, return 0 so we get a NULL array when using
+ -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
return 0; -- Get NULL array
@@ -773,7 +776,7 @@ package body common_pkg is
function smallest(n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
@@ -1738,8 +1741,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
@@ -1748,8 +1751,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
@@ -2143,16 +2146,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2172,8 +2176,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -2276,8 +2281,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -2316,9 +2321,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index 7b6d1a2da0..696b4c8f66 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
------------------------------------------------------------------------------
@@ -120,15 +120,16 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(1, c_dp_stream_bsn_w),
+ to_unsigned(1, c_dp_stream_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ '1', '1', '1',
+ to_unsigned(1, c_dp_stream_empty_w),
+ to_unsigned(1, c_dp_stream_channel_w),
+ to_unsigned(1, c_dp_stream_error_w));
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -207,30 +208,34 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
-- . Use these functions to assign sosi data TO a record field
@@ -353,11 +358,11 @@ package dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
@@ -396,11 +401,12 @@ end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -415,20 +421,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -446,10 +454,11 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
@@ -1231,16 +1240,16 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
@@ -1264,7 +1273,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
@@ -1416,11 +1425,11 @@ package body dp_stream_pkg is
if data_order_im_re = true then
-- data = im&re
v_out_data := RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w) &
- RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
+ RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
else
-- data = re&im
v_out_data := RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w) &
- RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
+ RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
end if;
end if;
end if;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
index 1036675757..98bb5545f7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
@@ -44,12 +44,12 @@ package eth_pkg is
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
- -- yield simulation warning: Address pointed at port A is out of bound!
+ -- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
- -- when the module is used in an Nios II SOPC system
- -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
+ -- when the module is used in an Nios II SOPC system
+ -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
@@ -71,9 +71,10 @@ package eth_pkg is
is_dhcp : std_logic;
end record;
- constant c_eth_hdr_status_rst : t_eth_hdr_status := ('0', '0', '0', '0',
- (others => '0'), '0', '0',
- (others => '0'), '0');
+ constant c_eth_hdr_status_rst : t_eth_hdr_status := (
+ '0', '0', '0', '0',
+ (others => '0'), '0', '0',
+ (others => '0'), '0');
------------------------------------------------------------------------------
-- Definitions for eth demux udp
@@ -197,22 +198,22 @@ package eth_pkg is
-- Definitions for eth_mm_registers
------------------------------------------------------------------------------
- constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
- c_eth_reg_config_nof_words +
- c_eth_reg_control_nof_words +
- c_eth_reg_frame_nof_words +
- c_eth_reg_status_nof_words;
- constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
-
- ------------------------------------------------------------------------------
- -- Definitions for ETH Rx packet buffer and Tx packet buffer
- ------------------------------------------------------------------------------
-
- -- Use MM bus data width = c_word_w = 32
- constant c_eth_ram_rx_offset : natural := 0;
- constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
- constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
- constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
+ constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
+ c_eth_reg_config_nof_words +
+ c_eth_reg_control_nof_words +
+ c_eth_reg_frame_nof_words +
+ c_eth_reg_status_nof_words;
+ constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
+
+ ------------------------------------------------------------------------------
+ -- Definitions for ETH Rx packet buffer and Tx packet buffer
+ ------------------------------------------------------------------------------
+
+ -- Use MM bus data width = c_word_w = 32
+ constant c_eth_ram_rx_offset : natural := 0;
+ constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
+ constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
+ constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
end eth_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
index 177eb750c7..fd301389d3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package tech_tse_pkg is
constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
index d648f26fb1..97ced47767 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
@@ -26,10 +26,10 @@
-- . The avs2_eth_coe_hw.tcl determines the read latency per port
library IEEE, common_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use work.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use work.eth_pkg.all;
entity avs2_eth_coe is
port (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
index e879f1b9ed..7f2c37e56a 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
@@ -23,9 +23,9 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_network_layers_pkg is
-- All *_len constants are in nof octets = nof bytes = c_8 bits
@@ -85,9 +85,10 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001");
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -134,221 +135,225 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
- constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
- c_network_ip_identification_len + c_network_ip_flags_fragment_len +
- c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
- c_network_ip_addr_len +
- c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
- -- default field values
- constant c_network_ip_version : natural := 4; -- 4 = IPv4,
- constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
- constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
- constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
- constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
- constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
- constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
- constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
- constant c_network_ip_header_checksum : natural := 0; -- init value
-
- -- useful field values
- constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
- constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
- constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
-
- constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
-
- type t_network_ip_header is record
- version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
- header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
- services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
- total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
- identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
- flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
- fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
- time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
- protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
- header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
- src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- end record;
-
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
-
- ------------------------------------------------------------------------------
- -- ARP Packet
- --
- -- 0 7 8 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Hardware Type | Protocol Type | 4
- -- |----------------------------------------------------------------------|
- -- | HW Addr Len | Prot Addr Len | Operation | 5
- -- |----------------------------------------------------------------------|
- -- | Sender Hardware Address | 6
- -- | ------------------------------------|
- -- | | | 7
- -- |---------------------------------/ /----------------------------------|
- -- | Sender Protocol Address | | 8
- -- |----------------------------------- |
- -- | Target Hardware Address | 9
- -- |----------------------------------------------------------------------|
- -- | Target Protocol Address | 10
- -- |----------------------------------------------------------------------|
- --
- -- Note that ARP header = ARP packet, because ARP has no payload
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_arp_htype_len : natural := 2;
- constant c_network_arp_htype_w : natural := c_network_arp_htype_len * c_8;
- constant c_network_arp_ptype_len : natural := 2;
- constant c_network_arp_ptype_w : natural := c_network_arp_ptype_len * c_8;
- constant c_network_arp_hlen_len : natural := 1;
- constant c_network_arp_hlen_w : natural := c_network_arp_hlen_len * c_8;
- constant c_network_arp_plen_len : natural := 1;
- constant c_network_arp_plen_w : natural := c_network_arp_plen_len * c_8;
- constant c_network_arp_oper_len : natural := 2;
- constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
-
- -- [0:15] [16:31]
- constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
- c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-
- -- default field values
- constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
- constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
- constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
- constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
- constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
- constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
-
- -- useful field values
- constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
- constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
-
- type t_network_arp_packet is record
- htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
- ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
- hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
- plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
- oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
- sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
- spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
- tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
- tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
- end record;
-
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
-
- ------------------------------------------------------------------------------
- -- ICMP (for ping)
- --
- -- 0 7 8 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Type | Code | Checksum | 9
- -- |----------------------------------------------------------------------|
- -- | ID | Sequence | 10
- -- |----------------------------------------------------------------------|
- -- | |
- -- | ICMP Payload (padding data) |
- -- | |
- -- |------------------------------------------------------------ // ------|
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_icmp_msg_type_len : natural := 1;
- constant c_network_icmp_msg_type_w : natural := c_network_icmp_msg_type_len * c_8;
- constant c_network_icmp_code_len : natural := 1;
- constant c_network_icmp_code_w : natural := c_network_icmp_code_len * c_8;
- constant c_network_icmp_checksum_len : natural := 2;
- constant c_network_icmp_checksum_w : natural := c_network_icmp_checksum_len * c_8;
- constant c_network_icmp_id_len : natural := 2;
- constant c_network_icmp_id_w : natural := c_network_icmp_id_len * c_8;
- constant c_network_icmp_sequence_len : natural := 2;
- constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
- constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
- c_network_icmp_id_len + c_network_icmp_sequence_len;
-
- -- default field values
- constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
- constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
- constant c_network_icmp_checksum : natural := 0; -- init value
-
- -- useful field values
- constant c_network_icmp_code : natural := 0; -- default
- constant c_network_icmp_id : natural := 3; -- arbitrary value
- constant c_network_icmp_sequence : natural := 4; -- arbitrary value
-
- type t_network_icmp_header is record
- msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
- code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
- checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
- id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
- sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
- end record;
-
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
-
- ------------------------------------------------------------------------------
- -- UDP Packet
- --
- -- 0 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Source Port | Destination Port | 9
- -- |----------------------------------------------------------------------|
- -- | Total Length | Checksum | 10
- -- |----------------------------------------------------------------------|
- -- | |
- -- | UDP Payload |
- -- | |
- -- |----------------------------------------------------------- // -------|
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_udp_port_len : natural := 2;
- constant c_network_udp_port_w : natural := c_network_udp_port_len * c_8;
- constant c_network_udp_total_length_len : natural := 2;
- constant c_network_udp_total_length_w : natural := c_network_udp_total_length_len * c_8;
- constant c_network_udp_checksum_len : natural := 2;
- constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
-
- -- [0:15] [16:31]
- constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
-
- -- default field values
- constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
- constant c_network_udp_checksum : natural := 0; -- init value
-
- -- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
-
- constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
- constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
- constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
-
- type t_network_udp_header is record
- src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
- checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
- end record;
-
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ -- [0:7] [8:15] [16:31]
+ constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
+ c_network_ip_identification_len + c_network_ip_flags_fragment_len +
+ c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
+ c_network_ip_addr_len +
+ c_network_ip_addr_len;
+ -- = c_network_ip_header_length * c_word_sz = 20
+ -- default field values
+ constant c_network_ip_version : natural := 4; -- 4 = IPv4,
+ constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
+ constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
+ constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
+ constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
+ constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
+ constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
+ constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
+ constant c_network_ip_header_checksum : natural := 0; -- init value
+
+ -- useful field values
+ constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
+ constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
+ constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
+
+ constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
+
+ type t_network_ip_header is record
+ version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
+ header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
+ services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
+ total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
+ identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
+ flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
+ fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
+ time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
+ protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
+ header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
+ src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ end record;
+
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001", "0001", "00000001", "0000000000000001",
+ "0000000000000001", "001", "0000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- ARP Packet
+ --
+ -- 0 7 8 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Hardware Type | Protocol Type | 4
+ -- |----------------------------------------------------------------------|
+ -- | HW Addr Len | Prot Addr Len | Operation | 5
+ -- |----------------------------------------------------------------------|
+ -- | Sender Hardware Address | 6
+ -- | ------------------------------------|
+ -- | | | 7
+ -- |---------------------------------/ /----------------------------------|
+ -- | Sender Protocol Address | | 8
+ -- |----------------------------------- |
+ -- | Target Hardware Address | 9
+ -- |----------------------------------------------------------------------|
+ -- | Target Protocol Address | 10
+ -- |----------------------------------------------------------------------|
+ --
+ -- Note that ARP header = ARP packet, because ARP has no payload
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_arp_htype_len : natural := 2;
+ constant c_network_arp_htype_w : natural := c_network_arp_htype_len * c_8;
+ constant c_network_arp_ptype_len : natural := 2;
+ constant c_network_arp_ptype_w : natural := c_network_arp_ptype_len * c_8;
+ constant c_network_arp_hlen_len : natural := 1;
+ constant c_network_arp_hlen_w : natural := c_network_arp_hlen_len * c_8;
+ constant c_network_arp_plen_len : natural := 1;
+ constant c_network_arp_plen_w : natural := c_network_arp_plen_len * c_8;
+ constant c_network_arp_oper_len : natural := 2;
+ constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
+
+ -- [0:15] [16:31]
+ constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
+ c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len;
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+
+ -- default field values
+ constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
+ constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
+ constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
+ constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
+ constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
+ constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
+
+ -- useful field values
+ constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
+ constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
+
+ type t_network_arp_packet is record
+ htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
+ ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
+ hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
+ plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
+ oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
+ sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
+ spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
+ tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
+ tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
+ end record;
+
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001", "0000000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- ICMP (for ping)
+ --
+ -- 0 7 8 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Type | Code | Checksum | 9
+ -- |----------------------------------------------------------------------|
+ -- | ID | Sequence | 10
+ -- |----------------------------------------------------------------------|
+ -- | |
+ -- | ICMP Payload (padding data) |
+ -- | |
+ -- |------------------------------------------------------------ // ------|
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_icmp_msg_type_len : natural := 1;
+ constant c_network_icmp_msg_type_w : natural := c_network_icmp_msg_type_len * c_8;
+ constant c_network_icmp_code_len : natural := 1;
+ constant c_network_icmp_code_w : natural := c_network_icmp_code_len * c_8;
+ constant c_network_icmp_checksum_len : natural := 2;
+ constant c_network_icmp_checksum_w : natural := c_network_icmp_checksum_len * c_8;
+ constant c_network_icmp_id_len : natural := 2;
+ constant c_network_icmp_id_w : natural := c_network_icmp_id_len * c_8;
+ constant c_network_icmp_sequence_len : natural := 2;
+ constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
+ constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
+ c_network_icmp_id_len + c_network_icmp_sequence_len;
+
+ -- default field values
+ constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
+ constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
+ constant c_network_icmp_checksum : natural := 0; -- init value
+
+ -- useful field values
+ constant c_network_icmp_code : natural := 0; -- default
+ constant c_network_icmp_id : natural := 3; -- arbitrary value
+ constant c_network_icmp_sequence : natural := 4; -- arbitrary value
+
+ type t_network_icmp_header is record
+ msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
+ code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
+ checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
+ id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
+ sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
+ end record;
+
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001", "00000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- UDP Packet
+ --
+ -- 0 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Source Port | Destination Port | 9
+ -- |----------------------------------------------------------------------|
+ -- | Total Length | Checksum | 10
+ -- |----------------------------------------------------------------------|
+ -- | |
+ -- | UDP Payload |
+ -- | |
+ -- |----------------------------------------------------------- // -------|
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_udp_port_len : natural := 2;
+ constant c_network_udp_port_w : natural := c_network_udp_port_len * c_8;
+ constant c_network_udp_total_length_len : natural := 2;
+ constant c_network_udp_total_length_w : natural := c_network_udp_total_length_len * c_8;
+ constant c_network_udp_checksum_len : natural := 2;
+ constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
+
+ -- [0:15] [16:31]
+ constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
+ c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+
+ -- default field values
+ constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
+ constant c_network_udp_checksum : natural := 0; -- init value
+
+ -- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
+
+ constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
+ constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
+ constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
+
+ type t_network_udp_header is record
+ src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
+ dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
+ total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
+ checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
+ end record;
+
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
end common_network_layers_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index 4bd7e15cc8..d6ca1b9008 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -30,9 +30,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
-- CONSTANT DECLARATIONS ----------------------------------------------------
@@ -332,7 +332,7 @@ package common_pkg is
function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
--- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
+ -- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
-- appropriate approach is to ignore the MSbit sign and just keep the LS part. For too large values this
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
@@ -353,7 +353,7 @@ package common_pkg is
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
+ -- Used in common_add_sub.vhd
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
@@ -429,20 +429,22 @@ package common_pkg is
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
function func_common_reorder2_is_there(I, J : natural) return boolean;
@@ -452,9 +454,10 @@ package common_pkg is
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
@@ -465,38 +468,38 @@ package body common_pkg is
end;
function ceil_pow2(n : integer) return natural is
- -- Also allows negative exponents and rounds up before returning the value
+ -- Also allows negative exponents and rounds up before returning the value
begin
return natural(integer(ceil(2**real(n))));
end;
function true_log2(n : natural) return natural is
- -- Purpose: For calculating extra vector width of existing vector
- -- Description: Return mathematical ceil(log2(n))
- -- n log2()
- -- 0 -> -oo --> FAILURE
- -- 1 -> 0
- -- 2 -> 1
- -- 3 -> 2
- -- 4 -> 2
- -- 5 -> 3
- -- 6 -> 3
- -- 7 -> 3
- -- 8 -> 3
- -- 9 -> 4
- -- etc, up to n = NATURAL'HIGH = 2**31-1
+ -- Purpose: For calculating extra vector width of existing vector
+ -- Description: Return mathematical ceil(log2(n))
+ -- n log2()
+ -- 0 -> -oo --> FAILURE
+ -- 1 -> 0
+ -- 2 -> 1
+ -- 3 -> 2
+ -- 4 -> 2
+ -- 5 -> 3
+ -- 6 -> 3
+ -- 7 -> 3
+ -- 8 -> 3
+ -- 9 -> 4
+ -- etc, up to n = NATURAL'HIGH = 2**31-1
begin
return natural(integer(ceil(log2(real(n)))));
end;
function ceil_log2(n : natural) return natural is
- -- Purpose: For calculating vector width of new vector
- -- Description:
- -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
- -- the vector width width for 1 address, to avoid NULL array for single
- -- word register address.
- -- If n = 0, return 0 so we get a NULL array when using
- -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
+ -- Purpose: For calculating vector width of new vector
+ -- Description:
+ -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
+ -- the vector width width for 1 address, to avoid NULL array for single
+ -- word register address.
+ -- If n = 0, return 0 so we get a NULL array when using
+ -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
return 0; -- Get NULL array
@@ -773,7 +776,7 @@ package body common_pkg is
function smallest(n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
@@ -1738,8 +1741,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
@@ -1748,8 +1751,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
@@ -2143,16 +2146,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2172,8 +2176,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -2276,8 +2281,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -2316,9 +2321,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index 7b6d1a2da0..696b4c8f66 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
------------------------------------------------------------------------------
@@ -120,15 +120,16 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(1, c_dp_stream_bsn_w),
+ to_unsigned(1, c_dp_stream_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ '1', '1', '1',
+ to_unsigned(1, c_dp_stream_empty_w),
+ to_unsigned(1, c_dp_stream_channel_w),
+ to_unsigned(1, c_dp_stream_error_w));
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -207,30 +208,34 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
-- . Use these functions to assign sosi data TO a record field
@@ -353,11 +358,11 @@ package dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
@@ -396,11 +401,12 @@ end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -415,20 +421,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -446,10 +454,11 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
@@ -1231,16 +1240,16 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
@@ -1264,7 +1273,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
@@ -1416,11 +1425,11 @@ package body dp_stream_pkg is
if data_order_im_re = true then
-- data = im&re
v_out_data := RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w) &
- RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
+ RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
else
-- data = re&im
v_out_data := RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w) &
- RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
+ RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
end if;
end if;
end if;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
index 1036675757..98bb5545f7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
@@ -44,12 +44,12 @@ package eth_pkg is
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
- -- yield simulation warning: Address pointed at port A is out of bound!
+ -- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
- -- when the module is used in an Nios II SOPC system
- -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
+ -- when the module is used in an Nios II SOPC system
+ -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
@@ -71,9 +71,10 @@ package eth_pkg is
is_dhcp : std_logic;
end record;
- constant c_eth_hdr_status_rst : t_eth_hdr_status := ('0', '0', '0', '0',
- (others => '0'), '0', '0',
- (others => '0'), '0');
+ constant c_eth_hdr_status_rst : t_eth_hdr_status := (
+ '0', '0', '0', '0',
+ (others => '0'), '0', '0',
+ (others => '0'), '0');
------------------------------------------------------------------------------
-- Definitions for eth demux udp
@@ -197,22 +198,22 @@ package eth_pkg is
-- Definitions for eth_mm_registers
------------------------------------------------------------------------------
- constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
- c_eth_reg_config_nof_words +
- c_eth_reg_control_nof_words +
- c_eth_reg_frame_nof_words +
- c_eth_reg_status_nof_words;
- constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
-
- ------------------------------------------------------------------------------
- -- Definitions for ETH Rx packet buffer and Tx packet buffer
- ------------------------------------------------------------------------------
-
- -- Use MM bus data width = c_word_w = 32
- constant c_eth_ram_rx_offset : natural := 0;
- constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
- constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
- constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
+ constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
+ c_eth_reg_config_nof_words +
+ c_eth_reg_control_nof_words +
+ c_eth_reg_frame_nof_words +
+ c_eth_reg_status_nof_words;
+ constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
+
+ ------------------------------------------------------------------------------
+ -- Definitions for ETH Rx packet buffer and Tx packet buffer
+ ------------------------------------------------------------------------------
+
+ -- Use MM bus data width = c_word_w = 32
+ constant c_eth_ram_rx_offset : natural := 0;
+ constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
+ constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
+ constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
end eth_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
index 177eb750c7..fd301389d3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package tech_tse_pkg is
constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
index 06df7d37f4..1db149d4b3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
@@ -1,84 +1,84 @@
- component qsys_unb2b_minimal_avs_eth_0 is
- port (
- coe_clk_export : out std_logic; -- export
- ins_interrupt_irq : out std_logic; -- irq
- coe_irq_export : in std_logic := 'X'; -- export
- csi_mm_clk : in std_logic := 'X'; -- clk
- csi_mm_reset : in std_logic := 'X'; -- reset
- mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_ram_write : in std_logic := 'X'; -- write
- mms_ram_read : in std_logic := 'X'; -- read
- mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_ram_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
- mms_reg_write : in std_logic := 'X'; -- write
- mms_reg_read : in std_logic := 'X'; -- read
- mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_reg_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_tse_write : in std_logic := 'X'; -- write
- mms_tse_read : in std_logic := 'X'; -- read
- mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_tse_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_waitrequest : out std_logic; -- waitrequest
- coe_ram_address_export : out std_logic_vector(9 downto 0); -- export
- coe_ram_read_export : out std_logic; -- export
- coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_write_export : out std_logic; -- export
- coe_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reg_address_export : out std_logic_vector(3 downto 0); -- export
- coe_reg_read_export : out std_logic; -- export
- coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reg_write_export : out std_logic; -- export
- coe_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reset_export : out std_logic; -- export
- coe_tse_address_export : out std_logic_vector(9 downto 0); -- export
- coe_tse_read_export : out std_logic; -- export
- coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_tse_waitrequest_export : in std_logic := 'X'; -- export
- coe_tse_write_export : out std_logic; -- export
- coe_tse_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_eth_0;
+component qsys_unb2b_minimal_avs_eth_0 is
+ port (
+ coe_clk_export : out std_logic; -- export
+ ins_interrupt_irq : out std_logic; -- irq
+ coe_irq_export : in std_logic := 'X'; -- export
+ csi_mm_clk : in std_logic := 'X'; -- clk
+ csi_mm_reset : in std_logic := 'X'; -- reset
+ mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mms_ram_write : in std_logic := 'X'; -- write
+ mms_ram_read : in std_logic := 'X'; -- read
+ mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_ram_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
+ mms_reg_write : in std_logic := 'X'; -- write
+ mms_reg_read : in std_logic := 'X'; -- read
+ mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_reg_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mms_tse_write : in std_logic := 'X'; -- write
+ mms_tse_read : in std_logic := 'X'; -- read
+ mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_tse_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_tse_waitrequest : out std_logic; -- waitrequest
+ coe_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ coe_ram_read_export : out std_logic; -- export
+ coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_write_export : out std_logic; -- export
+ coe_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ coe_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ coe_reg_read_export : out std_logic; -- export
+ coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reg_write_export : out std_logic; -- export
+ coe_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export : out std_logic; -- export
+ coe_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ coe_tse_read_export : out std_logic; -- export
+ coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_tse_waitrequest_export : in std_logic := 'X'; -- export
+ coe_tse_write_export : out std_logic; -- export
+ coe_tse_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_avs_eth_0;
- u0 : component qsys_unb2b_minimal_avs_eth_0
- port map (
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq, -- interrupt.irq
- coe_irq_export => CONNECTED_TO_coe_irq_export, -- irq.export
- csi_mm_clk => CONNECTED_TO_csi_mm_clk, -- mm.clk
- csi_mm_reset => CONNECTED_TO_csi_mm_reset, -- mm_reset.reset
- mms_ram_address => CONNECTED_TO_mms_ram_address, -- mms_ram.address
- mms_ram_write => CONNECTED_TO_mms_ram_write, -- .write
- mms_ram_read => CONNECTED_TO_mms_ram_read, -- .read
- mms_ram_writedata => CONNECTED_TO_mms_ram_writedata, -- .writedata
- mms_ram_readdata => CONNECTED_TO_mms_ram_readdata, -- .readdata
- mms_reg_address => CONNECTED_TO_mms_reg_address, -- mms_reg.address
- mms_reg_write => CONNECTED_TO_mms_reg_write, -- .write
- mms_reg_read => CONNECTED_TO_mms_reg_read, -- .read
- mms_reg_writedata => CONNECTED_TO_mms_reg_writedata, -- .writedata
- mms_reg_readdata => CONNECTED_TO_mms_reg_readdata, -- .readdata
- mms_tse_address => CONNECTED_TO_mms_tse_address, -- mms_tse.address
- mms_tse_write => CONNECTED_TO_mms_tse_write, -- .write
- mms_tse_read => CONNECTED_TO_mms_tse_read, -- .read
- mms_tse_writedata => CONNECTED_TO_mms_tse_writedata, -- .writedata
- mms_tse_readdata => CONNECTED_TO_mms_tse_readdata, -- .readdata
- mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest, -- .waitrequest
- coe_ram_address_export => CONNECTED_TO_coe_ram_address_export, -- ram_address.export
- coe_ram_read_export => CONNECTED_TO_coe_ram_read_export, -- ram_read.export
- coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export, -- ram_readdata.export
- coe_ram_write_export => CONNECTED_TO_coe_ram_write_export, -- ram_write.export
- coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export, -- ram_writedata.export
- coe_reg_address_export => CONNECTED_TO_coe_reg_address_export, -- reg_address.export
- coe_reg_read_export => CONNECTED_TO_coe_reg_read_export, -- reg_read.export
- coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export, -- reg_readdata.export
- coe_reg_write_export => CONNECTED_TO_coe_reg_write_export, -- reg_write.export
- coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export, -- reg_writedata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- coe_tse_address_export => CONNECTED_TO_coe_tse_address_export, -- tse_address.export
- coe_tse_read_export => CONNECTED_TO_coe_tse_read_export, -- tse_read.export
- coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export, -- tse_readdata.export
- coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
- coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
- coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
- );
+u0 : component qsys_unb2b_minimal_avs_eth_0
+ port map (
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq, -- interrupt.irq
+ coe_irq_export => CONNECTED_TO_coe_irq_export, -- irq.export
+ csi_mm_clk => CONNECTED_TO_csi_mm_clk, -- mm.clk
+ csi_mm_reset => CONNECTED_TO_csi_mm_reset, -- mm_reset.reset
+ mms_ram_address => CONNECTED_TO_mms_ram_address, -- mms_ram.address
+ mms_ram_write => CONNECTED_TO_mms_ram_write, -- .write
+ mms_ram_read => CONNECTED_TO_mms_ram_read, -- .read
+ mms_ram_writedata => CONNECTED_TO_mms_ram_writedata, -- .writedata
+ mms_ram_readdata => CONNECTED_TO_mms_ram_readdata, -- .readdata
+ mms_reg_address => CONNECTED_TO_mms_reg_address, -- mms_reg.address
+ mms_reg_write => CONNECTED_TO_mms_reg_write, -- .write
+ mms_reg_read => CONNECTED_TO_mms_reg_read, -- .read
+ mms_reg_writedata => CONNECTED_TO_mms_reg_writedata, -- .writedata
+ mms_reg_readdata => CONNECTED_TO_mms_reg_readdata, -- .readdata
+ mms_tse_address => CONNECTED_TO_mms_tse_address, -- mms_tse.address
+ mms_tse_write => CONNECTED_TO_mms_tse_write, -- .write
+ mms_tse_read => CONNECTED_TO_mms_tse_read, -- .read
+ mms_tse_writedata => CONNECTED_TO_mms_tse_writedata, -- .writedata
+ mms_tse_readdata => CONNECTED_TO_mms_tse_readdata, -- .readdata
+ mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest, -- .waitrequest
+ coe_ram_address_export => CONNECTED_TO_coe_ram_address_export, -- ram_address.export
+ coe_ram_read_export => CONNECTED_TO_coe_ram_read_export, -- ram_read.export
+ coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export, -- ram_readdata.export
+ coe_ram_write_export => CONNECTED_TO_coe_ram_write_export, -- ram_write.export
+ coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export, -- ram_writedata.export
+ coe_reg_address_export => CONNECTED_TO_coe_reg_address_export, -- reg_address.export
+ coe_reg_read_export => CONNECTED_TO_coe_reg_read_export, -- reg_read.export
+ coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export, -- reg_readdata.export
+ coe_reg_write_export => CONNECTED_TO_coe_reg_write_export, -- reg_write.export
+ coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export, -- reg_writedata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ coe_tse_address_export => CONNECTED_TO_coe_tse_address_export, -- tse_address.export
+ coe_tse_read_export => CONNECTED_TO_coe_tse_read_export, -- tse_read.export
+ coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export, -- tse_readdata.export
+ coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
+ coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
+ coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
index fafd41bbfa..f5b3868395 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
@@ -1,16 +1,16 @@
- component qsys_unb2b_minimal_clk_0 is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component qsys_unb2b_minimal_clk_0;
+component qsys_unb2b_minimal_clk_0 is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component qsys_unb2b_minimal_clk_0;
- u0 : component qsys_unb2b_minimal_clk_0
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component qsys_unb2b_minimal_clk_0
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
index 38fce9676f..530ffe2274 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
@@ -1,60 +1,60 @@
- component qsys_unb2b_minimal_cpu_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- dummy_ci_port : out std_logic; -- readra
- d_address : out std_logic_vector(19 downto 0); -- address
- d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
- d_read : out std_logic; -- read
- d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- d_waitrequest : in std_logic := 'X'; -- waitrequest
- d_write : out std_logic; -- write
- d_writedata : out std_logic_vector(31 downto 0); -- writedata
- debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
- debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
- debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
- debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
- debug_mem_slave_read : in std_logic := 'X'; -- read
- debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
- debug_mem_slave_waitrequest : out std_logic; -- waitrequest
- debug_mem_slave_write : in std_logic := 'X'; -- write
- debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- debug_reset_request : out std_logic; -- reset
- i_address : out std_logic_vector(17 downto 0); -- address
- i_read : out std_logic; -- read
- i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- i_waitrequest : in std_logic := 'X'; -- waitrequest
- irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- reset_req : in std_logic := 'X' -- reset_req
- );
- end component qsys_unb2b_minimal_cpu_0;
+component qsys_unb2b_minimal_cpu_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ dummy_ci_port : out std_logic; -- readra
+ d_address : out std_logic_vector(19 downto 0); -- address
+ d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ d_read : out std_logic; -- read
+ d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ d_waitrequest : in std_logic := 'X'; -- waitrequest
+ d_write : out std_logic; -- write
+ d_writedata : out std_logic_vector(31 downto 0); -- writedata
+ debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
+ debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
+ debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
+ debug_mem_slave_read : in std_logic := 'X'; -- read
+ debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
+ debug_mem_slave_waitrequest : out std_logic; -- waitrequest
+ debug_mem_slave_write : in std_logic := 'X'; -- write
+ debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ debug_reset_request : out std_logic; -- reset
+ i_address : out std_logic_vector(17 downto 0); -- address
+ i_read : out std_logic; -- read
+ i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ i_waitrequest : in std_logic := 'X'; -- waitrequest
+ irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_req : in std_logic := 'X' -- reset_req
+ );
+end component qsys_unb2b_minimal_cpu_0;
- u0 : component qsys_unb2b_minimal_cpu_0
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
- d_address => CONNECTED_TO_d_address, -- data_master.address
- d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
- d_read => CONNECTED_TO_d_read, -- .read
- d_readdata => CONNECTED_TO_d_readdata, -- .readdata
- d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
- d_write => CONNECTED_TO_d_write, -- .write
- d_writedata => CONNECTED_TO_d_writedata, -- .writedata
- debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
- debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
- debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
- debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
- debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
- debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
- debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
- debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
- debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
- debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
- i_address => CONNECTED_TO_i_address, -- instruction_master.address
- i_read => CONNECTED_TO_i_read, -- .read
- i_readdata => CONNECTED_TO_i_readdata, -- .readdata
- i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- reset_req => CONNECTED_TO_reset_req -- .reset_req
- );
+u0 : component qsys_unb2b_minimal_cpu_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
+ d_address => CONNECTED_TO_d_address, -- data_master.address
+ d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
+ d_read => CONNECTED_TO_d_read, -- .read
+ d_readdata => CONNECTED_TO_d_readdata, -- .readdata
+ d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
+ d_write => CONNECTED_TO_d_write, -- .write
+ d_writedata => CONNECTED_TO_d_writedata, -- .writedata
+ debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
+ debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
+ debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
+ debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
+ debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
+ debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
+ debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
+ debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
+ debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
+ debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
+ i_address => CONNECTED_TO_i_address, -- instruction_master.address
+ i_read => CONNECTED_TO_i_read, -- .read
+ i_readdata => CONNECTED_TO_i_readdata, -- .readdata
+ i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
+ irq => CONNECTED_TO_irq, -- irq.irq
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ reset_req => CONNECTED_TO_reset_req -- .reset_req
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
index c76f427acb..e1d0e8ddbe 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
@@ -1,100 +1,100 @@
- component qsys_unb2b_minimal_jesd204 is
- port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
- );
- end component qsys_unb2b_minimal_jesd204;
+component qsys_unb2b_minimal_jesd204 is
+ port (
+ alldev_lane_aligned : in std_logic := 'X'; -- export
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ dev_lane_aligned : out std_logic; -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_rx_avs_read : in std_logic := 'X'; -- read
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_rx_avs_write : in std_logic := 'X'; -- write
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_frame_error : in std_logic := 'X'; -- export
+ jesd204_rx_int : out std_logic; -- irq
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ jesd204_rx_link_valid : out std_logic; -- valid
+ jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ rxlink_clk : in std_logic := 'X'; -- clk
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxphy_clk : out std_logic_vector(0 downto 0); -- export
+ sof : out std_logic_vector(3 downto 0); -- export
+ somf : out std_logic_vector(3 downto 0); -- export
+ sysref : in std_logic := 'X' -- export
+ );
+end component qsys_unb2b_minimal_jesd204;
- u0 : component qsys_unb2b_minimal_jesd204
- port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
- );
+u0 : component qsys_unb2b_minimal_jesd204
+ port map (
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
+ csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
+ csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
+ csr_f => CONNECTED_TO_csr_f, -- csr_f.export
+ csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
+ csr_k => CONNECTED_TO_csr_k, -- csr_k.export
+ csr_l => CONNECTED_TO_csr_l, -- csr_l.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
+ csr_m => CONNECTED_TO_csr_m, -- csr_m.export
+ csr_n => CONNECTED_TO_csr_n, -- csr_n.export
+ csr_np => CONNECTED_TO_csr_np, -- csr_np.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
+ csr_s => CONNECTED_TO_csr_s, -- csr_s.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
+ rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
+ rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
+ rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
+ sof => CONNECTED_TO_sof, -- sof.export
+ somf => CONNECTED_TO_somf, -- somf.export
+ sysref => CONNECTED_TO_sysref -- sysref.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
index f745d32d0b..0d4b6170c8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
@@ -15,55 +15,56 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library std;
-use std.textio.all;
+ use std.textio.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
begin
---synthesis translate_off
- process (clk)
+ --synthesis translate_off
+ process (clk)
variable write_line : line;
- begin
- if clk'event and clk = '1' then
- if std_logic'(fifo_wr) = '1' then
- write(write_line, character'val(CONV_INTEGER(fifo_wdata)));
- write(write_line, string'(""));
- write(output, write_line.all);
- deallocate (write_line);
- end if;
+ begin
+ if clk'event and clk = '1' then
+ if std_logic'(fifo_wr) = '1' then
+ write(write_line, character'val(CONV_INTEGER(fifo_wdata)));
+ write(write_line, string'(""));
+ write(output, write_line.all);
+ deallocate (write_line);
end if;
- end process;
+ end if;
+ end process;
- wfifo_used <= A_REP(std_logic'('0'), 6);
- r_dat <= A_REP(std_logic'('0'), 8);
- fifo_FF <= std_logic'('0');
- wfifo_empty <= std_logic'('1');
---synthesis translate_on
+ wfifo_used <= A_REP(std_logic'('0'), 6);
+ r_dat <= A_REP(std_logic'('0'), 8);
+ fifo_FF <= std_logic'('0');
+ wfifo_empty <= std_logic'('1');
+ --synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
@@ -71,96 +72,98 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
- signal rd_wfifo : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+ signal rd_wfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
---synthesis translate_off
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- component scfifo is
---GENERIC (
--- lpm_hint : STRING;
--- lpm_numwords : NATURAL;
--- lpm_showahead : STRING;
--- lpm_type : STRING;
--- lpm_width : NATURAL;
--- lpm_widthu : NATURAL;
--- overflow_checking : STRING;
--- underflow_checking : STRING;
--- use_eab : STRING
--- );
--- PORT (
--- signal full : OUT STD_LOGIC;
--- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
--- signal empty : OUT STD_LOGIC;
--- signal rdreq : IN STD_LOGIC;
--- signal aclr : IN STD_LOGIC;
--- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal clock : IN STD_LOGIC;
--- signal wrreq : IN STD_LOGIC
--- );
--- end component scfifo;
---synthesis read_comments_as_HDL off
- signal internal_fifo_FF : std_logic;
- signal internal_r_dat : std_logic_vector(7 downto 0);
- signal internal_wfifo_empty : std_logic;
- signal internal_wfifo_used : std_logic_vector(5 downto 0);
-begin
- --vhdl renameroo for output signals
- fifo_FF <= internal_fifo_FF;
- --vhdl renameroo for output signals
- r_dat <= internal_r_dat;
- --vhdl renameroo for output signals
- wfifo_empty <= internal_wfifo_empty;
- --vhdl renameroo for output signals
- wfifo_used <= internal_wfifo_used;
---synthesis translate_off
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w
+ --synthesis translate_off
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- component scfifo is
+ --GENERIC (
+ -- lpm_hint : STRING;
+ -- lpm_numwords : NATURAL;
+ -- lpm_showahead : STRING;
+ -- lpm_type : STRING;
+ -- lpm_width : NATURAL;
+ -- lpm_widthu : NATURAL;
+ -- overflow_checking : STRING;
+ -- underflow_checking : STRING;
+ -- use_eab : STRING
+ -- );
+ -- PORT (
+ -- signal full : OUT STD_LOGIC;
+ -- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+ -- signal empty : OUT STD_LOGIC;
+ -- signal rdreq : IN STD_LOGIC;
+ -- signal aclr : IN STD_LOGIC;
+ -- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal clock : IN STD_LOGIC;
+ -- signal wrreq : IN STD_LOGIC
+ -- );
+ -- end component scfifo;
+ --synthesis read_comments_as_HDL off
+ signal internal_fifo_FF : std_logic;
+ signal internal_r_dat : std_logic_vector(7 downto 0);
+ signal internal_wfifo_empty : std_logic;
+ signal internal_wfifo_used : std_logic_vector(5 downto 0);
+ begin
+ --vhdl renameroo for output signals
+ fifo_FF <= internal_fifo_FF;
+ --vhdl renameroo for output signals
+ r_dat <= internal_r_dat;
+ --vhdl renameroo for output signals
+ wfifo_empty <= internal_wfifo_empty;
+ --vhdl renameroo for output signals
+ wfifo_used <= internal_wfifo_used;
+ --synthesis translate_off
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w
port map(
fifo_FF => internal_fifo_FF,
r_dat => internal_r_dat,
@@ -171,103 +174,104 @@ begin
fifo_wr => fifo_wr
);
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- wfifo : scfifo
--- generic map(
--- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
--- lpm_numwords => 64,
--- lpm_showahead => "OFF",
--- lpm_type => "scfifo",
--- lpm_width => 8,
--- lpm_widthu => 6,
--- overflow_checking => "OFF",
--- underflow_checking => "OFF",
--- use_eab => "ON"
--- )
--- port map(
--- aclr => fifo_clear,
--- clock => clk,
--- data => fifo_wdata,
--- empty => internal_wfifo_empty,
--- full => internal_fifo_FF,
--- q => internal_r_dat,
--- rdreq => rd_wfifo,
--- usedw => internal_wfifo_used,
--- wrreq => fifo_wr
--- );
---
---synthesis read_comments_as_HDL off
-end europa;
-
--- turn off superfluous VHDL processor warnings
--- altera message_level Level1
--- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- wfifo : scfifo
+ -- generic map(
+ -- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
+ -- lpm_numwords => 64,
+ -- lpm_showahead => "OFF",
+ -- lpm_type => "scfifo",
+ -- lpm_width => 8,
+ -- lpm_widthu => 6,
+ -- overflow_checking => "OFF",
+ -- underflow_checking => "OFF",
+ -- use_eab => "ON"
+ -- )
+ -- port map(
+ -- aclr => fifo_clear,
+ -- clock => clk,
+ -- data => fifo_wdata,
+ -- empty => internal_wfifo_empty,
+ -- full => internal_fifo_FF,
+ -- q => internal_r_dat,
+ -- rdreq => rd_wfifo,
+ -- usedw => internal_wfifo_used,
+ -- wrreq => fifo_wr
+ -- );
+ --
+ --synthesis read_comments_as_HDL off
+ end europa;
+
+ -- turn off superfluous VHDL processor warnings
+ -- altera message_level Level1
+ -- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- signal bytes_left : std_logic_vector(31 downto 0);
- signal fifo_rd_d : std_logic;
- signal internal_rfifo_full1 : std_logic;
- signal new_rom : std_logic;
- signal num_bytes : std_logic_vector(31 downto 0);
- signal rfifo_entries : std_logic_vector(6 downto 0);
+ signal bytes_left : std_logic_vector(31 downto 0);
+ signal fifo_rd_d : std_logic;
+ signal internal_rfifo_full1 : std_logic;
+ signal new_rom : std_logic;
+ signal num_bytes : std_logic_vector(31 downto 0);
+ signal rfifo_entries : std_logic_vector(6 downto 0);
begin
--vhdl renameroo for output signals
rfifo_full <= internal_rfifo_full1;
---synthesis translate_off
- -- Generate rfifo_entries for simulation
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- bytes_left <= std_logic_vector'("00000000000000000000000000000000");
- fifo_rd_d <= std_logic'('0');
- elsif clk'event and clk = '1' then
- fifo_rd_d <= fifo_rd;
- -- decrement on read
- if std_logic'(fifo_rd_d) = '1' then
- bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32);
- end if;
- -- catch new contents
- if std_logic'(new_rom) = '1' then
- bytes_left <= num_bytes;
- end if;
+ --synthesis translate_off
+ -- Generate rfifo_entries for simulation
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ bytes_left <= std_logic_vector'("00000000000000000000000000000000");
+ fifo_rd_d <= std_logic'('0');
+ elsif clk'event and clk = '1' then
+ fifo_rd_d <= fifo_rd;
+ -- decrement on read
+ if std_logic'(fifo_rd_d) = '1' then
+ bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32);
end if;
- end process;
-
- fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
- internal_rfifo_full1 <= to_std_logic((bytes_left > std_logic_vector'("00000000000000000000000001000000")));
- rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7);
- rfifo_used <= rfifo_entries(5 downto 0);
- new_rom <= std_logic'('0');
- num_bytes <= std_logic_vector'("00000000000000000000000000000000");
- fifo_rdata <= std_logic_vector'("00000000");
---synthesis translate_on
+ -- catch new contents
+ if std_logic'(new_rom) = '1' then
+ bytes_left <= num_bytes;
+ end if;
+ end if;
+ end process;
+
+ fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
+ internal_rfifo_full1 <= to_std_logic((bytes_left > std_logic_vector'("00000000000000000000000001000000")));
+ rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7);
+ rfifo_used <= rfifo_entries(5 downto 0);
+ new_rom <= std_logic'('0');
+ num_bytes <= std_logic_vector'("00000000000000000000000000000000");
+ fifo_rdata <= std_logic_vector'("00000000");
+ --synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
@@ -275,97 +279,99 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
- signal t_dat : in std_logic_vector(7 downto 0);
- signal wr_rfifo : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+ signal t_dat : in std_logic_vector(7 downto 0);
+ signal wr_rfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
---synthesis translate_off
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- component scfifo is
---GENERIC (
--- lpm_hint : STRING;
--- lpm_numwords : NATURAL;
--- lpm_showahead : STRING;
--- lpm_type : STRING;
--- lpm_width : NATURAL;
--- lpm_widthu : NATURAL;
--- overflow_checking : STRING;
--- underflow_checking : STRING;
--- use_eab : STRING
--- );
--- PORT (
--- signal full : OUT STD_LOGIC;
--- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
--- signal empty : OUT STD_LOGIC;
--- signal rdreq : IN STD_LOGIC;
--- signal aclr : IN STD_LOGIC;
--- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal clock : IN STD_LOGIC;
--- signal wrreq : IN STD_LOGIC
--- );
--- end component scfifo;
---synthesis read_comments_as_HDL off
- signal internal_fifo_EF : std_logic;
- signal internal_fifo_rdata : std_logic_vector(7 downto 0);
- signal internal_rfifo_full : std_logic;
- signal internal_rfifo_used : std_logic_vector(5 downto 0);
-begin
- --vhdl renameroo for output signals
- fifo_EF <= internal_fifo_EF;
- --vhdl renameroo for output signals
- fifo_rdata <= internal_fifo_rdata;
- --vhdl renameroo for output signals
- rfifo_full <= internal_rfifo_full;
- --vhdl renameroo for output signals
- rfifo_used <= internal_rfifo_used;
---synthesis translate_off
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r
+ --synthesis translate_off
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- component scfifo is
+ --GENERIC (
+ -- lpm_hint : STRING;
+ -- lpm_numwords : NATURAL;
+ -- lpm_showahead : STRING;
+ -- lpm_type : STRING;
+ -- lpm_width : NATURAL;
+ -- lpm_widthu : NATURAL;
+ -- overflow_checking : STRING;
+ -- underflow_checking : STRING;
+ -- use_eab : STRING
+ -- );
+ -- PORT (
+ -- signal full : OUT STD_LOGIC;
+ -- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+ -- signal empty : OUT STD_LOGIC;
+ -- signal rdreq : IN STD_LOGIC;
+ -- signal aclr : IN STD_LOGIC;
+ -- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal clock : IN STD_LOGIC;
+ -- signal wrreq : IN STD_LOGIC
+ -- );
+ -- end component scfifo;
+ --synthesis read_comments_as_HDL off
+ signal internal_fifo_EF : std_logic;
+ signal internal_fifo_rdata : std_logic_vector(7 downto 0);
+ signal internal_rfifo_full : std_logic;
+ signal internal_rfifo_used : std_logic_vector(5 downto 0);
+ begin
+ --vhdl renameroo for output signals
+ fifo_EF <= internal_fifo_EF;
+ --vhdl renameroo for output signals
+ fifo_rdata <= internal_fifo_rdata;
+ --vhdl renameroo for output signals
+ rfifo_full <= internal_rfifo_full;
+ --vhdl renameroo for output signals
+ rfifo_used <= internal_rfifo_used;
+ --synthesis translate_off
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r
port map(
fifo_EF => internal_fifo_EF,
fifo_rdata => internal_fifo_rdata,
@@ -376,344 +382,346 @@ begin
rst_n => rst_n
);
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- rfifo : scfifo
--- generic map(
--- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
--- lpm_numwords => 64,
--- lpm_showahead => "OFF",
--- lpm_type => "scfifo",
--- lpm_width => 8,
--- lpm_widthu => 6,
--- overflow_checking => "OFF",
--- underflow_checking => "OFF",
--- use_eab => "ON"
--- )
--- port map(
--- aclr => fifo_clear,
--- clock => clk,
--- data => t_dat,
--- empty => internal_fifo_EF,
--- full => internal_rfifo_full,
--- q => internal_fifo_rdata,
--- rdreq => fifo_rd,
--- usedw => internal_rfifo_used,
--- wrreq => wr_rfifo
--- );
---
---synthesis read_comments_as_HDL off
-end europa;
-
--- turn off superfluous VHDL processor warnings
--- altera message_level Level1
--- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- rfifo : scfifo
+ -- generic map(
+ -- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
+ -- lpm_numwords => 64,
+ -- lpm_showahead => "OFF",
+ -- lpm_type => "scfifo",
+ -- lpm_width => 8,
+ -- lpm_widthu => 6,
+ -- overflow_checking => "OFF",
+ -- underflow_checking => "OFF",
+ -- use_eab => "ON"
+ -- )
+ -- port map(
+ -- aclr => fifo_clear,
+ -- clock => clk,
+ -- data => t_dat,
+ -- empty => internal_fifo_EF,
+ -- full => internal_rfifo_full,
+ -- q => internal_fifo_rdata,
+ -- rdreq => fifo_rd,
+ -- usedw => internal_rfifo_used,
+ -- wrreq => wr_rfifo
+ -- );
+ --
+ --synthesis read_comments_as_HDL off
+ end europa;
+
+ -- turn off superfluous VHDL processor warnings
+ -- altera message_level Level1
+ -- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
- port (
- -- inputs:
- signal av_address : in std_logic;
- signal av_chipselect : in std_logic;
- signal av_read_n : in std_logic;
- signal av_write_n : in std_logic;
- signal av_writedata : in std_logic_vector(31 downto 0);
- signal clk : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal av_irq : out std_logic;
- signal av_readdata : out std_logic_vector(31 downto 0);
- signal av_waitrequest : out std_logic;
- signal dataavailable : out std_logic;
- signal readyfordata : out std_logic
- );
-attribute ALTERA_ATTRIBUTE : string;
-attribute ALTERA_ATTRIBUTE of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi : entity is "SUPPRESS_DA_RULE_INTERNAL=" "R101,C106,D101,D103" "";
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi;
+ port (
+ -- inputs:
+ signal av_address : in std_logic;
+ signal av_chipselect : in std_logic;
+ signal av_read_n : in std_logic;
+ signal av_write_n : in std_logic;
+ signal av_writedata : in std_logic_vector(31 downto 0);
+ signal clk : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal av_irq : out std_logic;
+ signal av_readdata : out std_logic_vector(31 downto 0);
+ signal av_waitrequest : out std_logic;
+ signal dataavailable : out std_logic;
+ signal readyfordata : out std_logic
+ );
+ attribute ALTERA_ATTRIBUTE : string;
+ attribute ALTERA_ATTRIBUTE of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi : entity is "SUPPRESS_DA_RULE_INTERNAL=" "R101,C106,D101,D103" "";
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
- signal rd_wfifo : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
-
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
- signal t_dat : in std_logic_vector(7 downto 0);
- signal wr_rfifo : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
-
---synthesis read_comments_as_HDL on
--- component alt_jtag_atlantic is
---GENERIC (
--- INSTANCE_ID : NATURAL;
--- LOG2_RXFIFO_DEPTH : NATURAL;
--- LOG2_TXFIFO_DEPTH : NATURAL;
--- SLD_AUTO_INSTANCE_INDEX : STRING
--- );
--- PORT (
--- signal t_pause : OUT STD_LOGIC;
--- signal r_ena : OUT STD_LOGIC;
--- signal t_ena : OUT STD_LOGIC;
--- signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal t_dav : IN STD_LOGIC;
--- signal rst_n : IN STD_LOGIC;
--- signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal r_val : IN STD_LOGIC;
--- signal clk : IN STD_LOGIC
--- );
--- end component alt_jtag_atlantic;
---synthesis read_comments_as_HDL off
- signal ac : std_logic;
- signal activity : std_logic;
- signal fifo_AE : std_logic;
- signal fifo_AF : std_logic;
- signal fifo_EF : std_logic;
- signal fifo_FF : std_logic;
- signal fifo_clear : std_logic;
- signal fifo_rd : std_logic;
- signal fifo_rdata : std_logic_vector(7 downto 0);
- signal fifo_wdata : std_logic_vector(7 downto 0);
- signal fifo_wr : std_logic;
- signal ien_AE : std_logic;
- signal ien_AF : std_logic;
- signal internal_av_waitrequest : std_logic;
- signal ipen_AE : std_logic;
- signal ipen_AF : std_logic;
- signal pause_irq : std_logic;
- signal r_dat : std_logic_vector(7 downto 0);
- signal r_ena : std_logic;
- signal r_val : std_logic;
- signal rd_wfifo : std_logic;
- signal read_0 : std_logic;
- signal rfifo_full : std_logic;
- signal rfifo_used : std_logic_vector(5 downto 0);
- signal rvalid : std_logic;
- signal sim_r_ena : std_logic;
- signal sim_t_dat : std_logic;
- signal sim_t_ena : std_logic;
- signal sim_t_pause : std_logic;
- signal t_dat : std_logic_vector(7 downto 0);
- signal t_dav : std_logic;
- signal t_ena : std_logic;
- signal t_pause : std_logic;
- signal wfifo_empty : std_logic;
- signal wfifo_used : std_logic_vector(5 downto 0);
- signal woverflow : std_logic;
- signal wr_rfifo : std_logic;
-begin
- --avalon_jtag_slave, which is an e_avalon_slave
- rd_wfifo <= r_ena and not wfifo_empty;
- wr_rfifo <= t_ena and not rfifo_full;
- fifo_clear <= not rst_n;
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w
- port map(
- fifo_FF => fifo_FF,
- r_dat => r_dat,
- wfifo_empty => wfifo_empty,
- wfifo_used => wfifo_used,
- clk => clk,
- fifo_clear => fifo_clear,
- fifo_wdata => fifo_wdata,
- fifo_wr => fifo_wr,
- rd_wfifo => rd_wfifo
- );
-
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r
- port map(
- fifo_EF => fifo_EF,
- fifo_rdata => fifo_rdata,
- rfifo_full => rfifo_full,
- rfifo_used => rfifo_used,
- clk => clk,
- fifo_clear => fifo_clear,
- fifo_rd => fifo_rd,
- rst_n => rst_n,
- t_dat => t_dat,
- wr_rfifo => wr_rfifo
- );
-
- ipen_AE <= ien_AE and fifo_AE;
- ipen_AF <= ien_AF and ((pause_irq or fifo_AF));
- av_irq <= ipen_AE or ipen_AF;
- activity <= t_pause or t_ena;
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- pause_irq <= std_logic'('0');
- elsif clk'event and clk = '1' then
- -- only if fifo is not empty...
- if std_logic'((t_pause and not fifo_EF)) = '1' then
- pause_irq <= std_logic'('1');
- elsif std_logic'(read_0) = '1' then
- pause_irq <= std_logic'('0');
- end if;
- end if;
- end process;
-
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- r_val <= std_logic'('0');
- t_dav <= std_logic'('1');
- elsif clk'event and clk = '1' then
- r_val <= r_ena and not wfifo_empty;
- t_dav <= not rfifo_full;
- end if;
- end process;
-
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- fifo_AE <= std_logic'('0');
- fifo_AF <= std_logic'('0');
- fifo_wr <= std_logic'('0');
- rvalid <= std_logic'('0');
- read_0 <= std_logic'('0');
- ien_AE <= std_logic'('0');
- ien_AF <= std_logic'('0');
- ac <= std_logic'('0');
- woverflow <= std_logic'('0');
- internal_av_waitrequest <= std_logic'('1');
- elsif clk'event and clk = '1' then
- fifo_AE <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))) <= std_logic_vector'("00000000000000000000000000001000")));
- fifo_AF <= to_std_logic(((std_logic_vector'("000000000000000000000000") & (((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(rfifo_full) & rfifo_used))))))) <= std_logic_vector'("00000000000000000000000000001000")));
- fifo_wr <= std_logic'('0');
- read_0 <= std_logic'('0');
- internal_av_waitrequest <= not (((av_chipselect and ((not av_write_n or not av_read_n))) and internal_av_waitrequest));
- if std_logic'(activity) = '1' then
- ac <= std_logic'('1');
- end if;
- -- write
- if std_logic'(((av_chipselect and not av_write_n) and internal_av_waitrequest)) = '1' then
- -- addr 1 is control; addr 0 is data
- if std_logic'(av_address) = '1' then
- ien_AF <= av_writedata(0);
- ien_AE <= av_writedata(1);
- if std_logic'((av_writedata(10) and not activity)) = '1' then
- ac <= std_logic'('0');
- end if;
- else
- fifo_wr <= not fifo_FF;
- woverflow <= fifo_FF;
- end if;
- end if;
- -- read
- if std_logic'(((av_chipselect and not av_read_n) and internal_av_waitrequest)) = '1' then
- -- addr 1 is interrupt; addr 0 is data
- if std_logic'(not av_address) = '1' then
- rvalid <= not fifo_EF;
- end if;
- read_0 <= not av_address;
- end if;
- end if;
- end process;
-
- fifo_wdata <= av_writedata(7 downto 0);
- fifo_rd <= A_WE_StdLogic((std_logic'(((((av_chipselect and not av_read_n) and internal_av_waitrequest) and not av_address))) = '1'), not fifo_EF, std_logic'('0'));
- av_readdata <= A_EXT (A_WE_StdLogicVector((std_logic'(read_0) = '1'), (std_logic_vector'("0") & ((A_REP(std_logic'('0'), 9) & A_ToStdLogicVector(rfifo_full) & rfifo_used & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & fifo_rdata))), (A_REP(std_logic'('0'), 9) & ((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))))) & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & A_REP(std_logic'('0'), 6) & A_ToStdLogicVector(ien_AE) & A_ToStdLogicVector(ien_AF))), 32);
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- readyfordata <= std_logic'('0');
- elsif clk'event and clk = '1' then
- readyfordata <= not fifo_FF;
- end if;
- end process;
-
- --vhdl renameroo for output signals
- av_waitrequest <= internal_av_waitrequest;
---synthesis translate_off
- -- Tie off Atlantic Interface signals not used for simulation
- process (clk)
- begin
- if clk'event and clk = '1' then
- sim_t_pause <= std_logic'('0');
- sim_t_ena <= std_logic'('0');
- sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
- sim_r_ena <= std_logic'('0');
- end if;
- end process;
-
- r_ena <= sim_r_ena;
- t_ena <= sim_t_ena;
- t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat));
- t_pause <= sim_t_pause;
- process (fifo_EF)
- begin
- dataavailable <= not fifo_EF;
- end process;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_alt_jtag_atlantic : alt_jtag_atlantic
--- generic map(
--- INSTANCE_ID => 0,
--- LOG2_RXFIFO_DEPTH => 6,
--- LOG2_TXFIFO_DEPTH => 6,
--- SLD_AUTO_INSTANCE_INDEX => "YES"
--- )
--- port map(
--- clk => clk,
--- r_dat => r_dat,
--- r_ena => r_ena,
--- r_val => r_val,
--- rst_n => rst_n,
--- t_dat => t_dat,
--- t_dav => t_dav,
--- t_ena => t_ena,
--- t_pause => t_pause
--- );
---
--- process (clk, rst_n)
--- begin
--- if rst_n = '0' then
--- dataavailable <= std_logic'('0');
--- elsif clk'event and clk = '1' then
--- dataavailable <= NOT fifo_EF;
--- end if;
---
--- end process;
---
---synthesis read_comments_as_HDL off
-end europa;
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+ signal rd_wfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
+
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+ signal t_dat : in std_logic_vector(7 downto 0);
+ signal wr_rfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
+
+ --synthesis read_comments_as_HDL on
+ -- component alt_jtag_atlantic is
+ --GENERIC (
+ -- INSTANCE_ID : NATURAL;
+ -- LOG2_RXFIFO_DEPTH : NATURAL;
+ -- LOG2_TXFIFO_DEPTH : NATURAL;
+ -- SLD_AUTO_INSTANCE_INDEX : STRING
+ -- );
+ -- PORT (
+ -- signal t_pause : OUT STD_LOGIC;
+ -- signal r_ena : OUT STD_LOGIC;
+ -- signal t_ena : OUT STD_LOGIC;
+ -- signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal t_dav : IN STD_LOGIC;
+ -- signal rst_n : IN STD_LOGIC;
+ -- signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal r_val : IN STD_LOGIC;
+ -- signal clk : IN STD_LOGIC
+ -- );
+ -- end component alt_jtag_atlantic;
+ --synthesis read_comments_as_HDL off
+ signal ac : std_logic;
+ signal activity : std_logic;
+ signal fifo_AE : std_logic;
+ signal fifo_AF : std_logic;
+ signal fifo_EF : std_logic;
+ signal fifo_FF : std_logic;
+ signal fifo_clear : std_logic;
+ signal fifo_rd : std_logic;
+ signal fifo_rdata : std_logic_vector(7 downto 0);
+ signal fifo_wdata : std_logic_vector(7 downto 0);
+ signal fifo_wr : std_logic;
+ signal ien_AE : std_logic;
+ signal ien_AF : std_logic;
+ signal internal_av_waitrequest : std_logic;
+ signal ipen_AE : std_logic;
+ signal ipen_AF : std_logic;
+ signal pause_irq : std_logic;
+ signal r_dat : std_logic_vector(7 downto 0);
+ signal r_ena : std_logic;
+ signal r_val : std_logic;
+ signal rd_wfifo : std_logic;
+ signal read_0 : std_logic;
+ signal rfifo_full : std_logic;
+ signal rfifo_used : std_logic_vector(5 downto 0);
+ signal rvalid : std_logic;
+ signal sim_r_ena : std_logic;
+ signal sim_t_dat : std_logic;
+ signal sim_t_ena : std_logic;
+ signal sim_t_pause : std_logic;
+ signal t_dat : std_logic_vector(7 downto 0);
+ signal t_dav : std_logic;
+ signal t_ena : std_logic;
+ signal t_pause : std_logic;
+ signal wfifo_empty : std_logic;
+ signal wfifo_used : std_logic_vector(5 downto 0);
+ signal woverflow : std_logic;
+ signal wr_rfifo : std_logic;
+ begin
+ --avalon_jtag_slave, which is an e_avalon_slave
+ rd_wfifo <= r_ena and not wfifo_empty;
+ wr_rfifo <= t_ena and not rfifo_full;
+ fifo_clear <= not rst_n;
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w
+ port map(
+ fifo_FF => fifo_FF,
+ r_dat => r_dat,
+ wfifo_empty => wfifo_empty,
+ wfifo_used => wfifo_used,
+ clk => clk,
+ fifo_clear => fifo_clear,
+ fifo_wdata => fifo_wdata,
+ fifo_wr => fifo_wr,
+ rd_wfifo => rd_wfifo
+ );
+
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r
+ port map(
+ fifo_EF => fifo_EF,
+ fifo_rdata => fifo_rdata,
+ rfifo_full => rfifo_full,
+ rfifo_used => rfifo_used,
+ clk => clk,
+ fifo_clear => fifo_clear,
+ fifo_rd => fifo_rd,
+ rst_n => rst_n,
+ t_dat => t_dat,
+ wr_rfifo => wr_rfifo
+ );
+
+ ipen_AE <= ien_AE and fifo_AE;
+ ipen_AF <= ien_AF and ((pause_irq or fifo_AF));
+ av_irq <= ipen_AE or ipen_AF;
+ activity <= t_pause or t_ena;
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ pause_irq <= std_logic'('0');
+ elsif clk'event and clk = '1' then
+ -- only if fifo is not empty...
+ if std_logic'((t_pause and not fifo_EF)) = '1' then
+ pause_irq <= std_logic'('1');
+ elsif std_logic'(read_0) = '1' then
+ pause_irq <= std_logic'('0');
+ end if;
+ end if;
+ end process;
+
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ r_val <= std_logic'('0');
+ t_dav <= std_logic'('1');
+ elsif clk'event and clk = '1' then
+ r_val <= r_ena and not wfifo_empty;
+ t_dav <= not rfifo_full;
+ end if;
+ end process;
+
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ fifo_AE <= std_logic'('0');
+ fifo_AF <= std_logic'('0');
+ fifo_wr <= std_logic'('0');
+ rvalid <= std_logic'('0');
+ read_0 <= std_logic'('0');
+ ien_AE <= std_logic'('0');
+ ien_AF <= std_logic'('0');
+ ac <= std_logic'('0');
+ woverflow <= std_logic'('0');
+ internal_av_waitrequest <= std_logic'('1');
+ elsif clk'event and clk = '1' then
+ fifo_AE <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))) <= std_logic_vector'("00000000000000000000000000001000")));
+ fifo_AF <= to_std_logic(((std_logic_vector'("000000000000000000000000") & (((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(rfifo_full) & rfifo_used))))))) <= std_logic_vector'("00000000000000000000000000001000")));
+ fifo_wr <= std_logic'('0');
+ read_0 <= std_logic'('0');
+ internal_av_waitrequest <= not (((av_chipselect and ((not av_write_n or not av_read_n))) and internal_av_waitrequest));
+ if std_logic'(activity) = '1' then
+ ac <= std_logic'('1');
+ end if;
+ -- write
+ if std_logic'(((av_chipselect and not av_write_n) and internal_av_waitrequest)) = '1' then
+ -- addr 1 is control; addr 0 is data
+ if std_logic'(av_address) = '1' then
+ ien_AF <= av_writedata(0);
+ ien_AE <= av_writedata(1);
+ if std_logic'((av_writedata(10) and not activity)) = '1' then
+ ac <= std_logic'('0');
+ end if;
+ else
+ fifo_wr <= not fifo_FF;
+ woverflow <= fifo_FF;
+ end if;
+ end if;
+ -- read
+ if std_logic'(((av_chipselect and not av_read_n) and internal_av_waitrequest)) = '1' then
+ -- addr 1 is interrupt; addr 0 is data
+ if std_logic'(not av_address) = '1' then
+ rvalid <= not fifo_EF;
+ end if;
+ read_0 <= not av_address;
+ end if;
+ end if;
+ end process;
+
+ fifo_wdata <= av_writedata(7 downto 0);
+ fifo_rd <= A_WE_StdLogic((std_logic'(((((av_chipselect and not av_read_n) and internal_av_waitrequest) and not av_address))) = '1'), not fifo_EF, std_logic'('0'));
+ av_readdata <= A_EXT (A_WE_StdLogicVector((std_logic'(read_0) = '1'), (std_logic_vector'("0") & ((A_REP(std_logic'('0'), 9) & A_ToStdLogicVector(rfifo_full) & rfifo_used & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & fifo_rdata))), (A_REP(std_logic'('0'), 9) & ((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))))) & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & A_REP(std_logic'('0'), 6) & A_ToStdLogicVector(ien_AE) & A_ToStdLogicVector(ien_AF))), 32);
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ readyfordata <= std_logic'('0');
+ elsif clk'event and clk = '1' then
+ readyfordata <= not fifo_FF;
+ end if;
+ end process;
+
+ --vhdl renameroo for output signals
+ av_waitrequest <= internal_av_waitrequest;
+ --synthesis translate_off
+ -- Tie off Atlantic Interface signals not used for simulation
+ process (clk)
+ begin
+ if clk'event and clk = '1' then
+ sim_t_pause <= std_logic'('0');
+ sim_t_ena <= std_logic'('0');
+ sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
+ sim_r_ena <= std_logic'('0');
+ end if;
+ end process;
+
+ r_ena <= sim_r_ena;
+ t_ena <= sim_t_ena;
+ t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat));
+ t_pause <= sim_t_pause;
+ process (fifo_EF)
+ begin
+ dataavailable <= not fifo_EF;
+ end process;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_alt_jtag_atlantic : alt_jtag_atlantic
+ -- generic map(
+ -- INSTANCE_ID => 0,
+ -- LOG2_RXFIFO_DEPTH => 6,
+ -- LOG2_TXFIFO_DEPTH => 6,
+ -- SLD_AUTO_INSTANCE_INDEX => "YES"
+ -- )
+ -- port map(
+ -- clk => clk,
+ -- r_dat => r_dat,
+ -- r_ena => r_ena,
+ -- r_val => r_val,
+ -- rst_n => rst_n,
+ -- t_dat => t_dat,
+ -- t_dav => t_dav,
+ -- t_ena => t_ena,
+ -- t_pause => t_pause
+ -- );
+ --
+ -- process (clk, rst_n)
+ -- begin
+ -- if rst_n = '0' then
+ -- dataavailable <= std_logic'('0');
+ -- elsif clk'event and clk = '1' then
+ -- dataavailable <= NOT fifo_EF;
+ -- end if;
+ --
+ -- end process;
+ --
+ --synthesis read_comments_as_HDL off
+ end europa;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
index bc11c57e41..68a1b9756e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
@@ -1,28 +1,28 @@
- component qsys_unb2b_minimal_jtag_uart_0 is
- port (
- av_chipselect : in std_logic := 'X'; -- chipselect
- av_address : in std_logic := 'X'; -- address
- av_read_n : in std_logic := 'X'; -- read_n
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_write_n : in std_logic := 'X'; -- write_n
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_waitrequest : out std_logic; -- waitrequest
- clk : in std_logic := 'X'; -- clk
- av_irq : out std_logic; -- irq
- rst_n : in std_logic := 'X' -- reset_n
- );
- end component qsys_unb2b_minimal_jtag_uart_0;
+component qsys_unb2b_minimal_jtag_uart_0 is
+ port (
+ av_chipselect : in std_logic := 'X'; -- chipselect
+ av_address : in std_logic := 'X'; -- address
+ av_read_n : in std_logic := 'X'; -- read_n
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_write_n : in std_logic := 'X'; -- write_n
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_waitrequest : out std_logic; -- waitrequest
+ clk : in std_logic := 'X'; -- clk
+ av_irq : out std_logic; -- irq
+ rst_n : in std_logic := 'X' -- reset_n
+ );
+end component qsys_unb2b_minimal_jtag_uart_0;
- u0 : component qsys_unb2b_minimal_jtag_uart_0
- port map (
- av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
- av_address => CONNECTED_TO_av_address, -- .address
- av_read_n => CONNECTED_TO_av_read_n, -- .read_n
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_write_n => CONNECTED_TO_av_write_n, -- .write_n
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
- clk => CONNECTED_TO_clk, -- clk.clk
- av_irq => CONNECTED_TO_av_irq, -- irq.irq
- rst_n => CONNECTED_TO_rst_n -- reset.reset_n
- );
+u0 : component qsys_unb2b_minimal_jtag_uart_0
+ port map (
+ av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
+ av_address => CONNECTED_TO_av_address, -- .address
+ av_read_n => CONNECTED_TO_av_read_n, -- .read_n
+ av_readdata => CONNECTED_TO_av_readdata, -- .readdata
+ av_write_n => CONNECTED_TO_av_write_n, -- .write_n
+ av_writedata => CONNECTED_TO_av_writedata, -- .writedata
+ av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
+ clk => CONNECTED_TO_clk, -- clk.clk
+ av_irq => CONNECTED_TO_av_irq, -- irq.irq
+ rst_n => CONNECTED_TO_rst_n -- reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
index 64222401d7..d7a5f0bc08 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
@@ -15,99 +15,101 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y is
- generic (
- INIT_FILE : string := "onchip_memory2_0.hex"
- );
- port (
- -- inputs:
- signal address : in std_logic_vector(14 downto 0);
- signal byteenable : in std_logic_vector(3 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal clken : in std_logic;
- signal freeze : in std_logic;
- signal reset : in std_logic;
- signal reset_req : in std_logic;
- signal write : in std_logic;
- signal writedata : in std_logic_vector(31 downto 0);
+ generic (
+ INIT_FILE : string := "onchip_memory2_0.hex"
+ );
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(14 downto 0);
+ signal byteenable : in std_logic_vector(3 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal clken : in std_logic;
+ signal freeze : in std_logic;
+ signal reset : in std_logic;
+ signal reset_req : in std_logic;
+ signal write : in std_logic;
+ signal writedata : in std_logic_vector(31 downto 0);
- -- outputs:
- signal readdata : out std_logic_vector(31 downto 0)
- );
-end entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y;
+ -- outputs:
+ signal readdata : out std_logic_vector(
+ 31 downto 0)
+ );
+ end entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y;
architecture europa of qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y is
component altsyncram is
-generic (
+ generic (
byte_size : natural;
- init_file : string;
- lpm_type : string;
- maximum_depth : natural;
- numwords_a : natural;
- operation_mode : string;
- outdata_reg_a : string;
- ram_block_type : string;
- read_during_write_mode_mixed_ports : string;
- read_during_write_mode_port_a : string;
- width_a : natural;
- width_byteena_a : natural;
- widthad_a : natural
- );
+ init_file : string;
+ lpm_type : string;
+ maximum_depth : natural;
+ numwords_a : natural;
+ operation_mode : string;
+ outdata_reg_a : string;
+ ram_block_type : string;
+ read_during_write_mode_mixed_ports : string;
+ read_during_write_mode_port_a : string;
+ width_a : natural;
+ width_byteena_a : natural;
+ widthad_a : natural
+ );
port (
- signal q_a : out std_logic_vector(31 downto 0);
- signal wren_a : in std_logic;
- signal byteena_a : in std_logic_vector(3 downto 0);
- signal clock0 : in std_logic;
- signal address_a : in std_logic_vector(14 downto 0);
- signal clocken0 : in std_logic;
- signal data_a : in std_logic_vector(31 downto 0)
+ signal q_a : out std_logic_vector(31 downto 0);
+ signal wren_a : in std_logic;
+ signal byteena_a : in std_logic_vector(3 downto 0);
+ signal clock0 : in std_logic;
+ signal address_a : in std_logic_vector(14 downto 0);
+ signal clocken0 : in std_logic;
+ signal data_a : in std_logic_vector(
+ 31 downto 0)
+ );
+ end component altsyncram;
+ signal clocken0 : std_logic;
+ signal internal_readdata : std_logic_vector(31 downto 0);
+ signal wren : std_logic;
+ begin
+ wren <= chipselect and write;
+ clocken0 <= clken and not reset_req;
+ the_altsyncram : altsyncram
+ generic map(
+ byte_size => 8,
+ init_file => INIT_FILE,
+ lpm_type => "altsyncram",
+ maximum_depth => 32768,
+ numwords_a => 32768,
+ operation_mode => "SINGLE_PORT",
+ outdata_reg_a => "UNREGISTERED",
+ ram_block_type => "AUTO",
+ read_during_write_mode_mixed_ports => "DONT_CARE",
+ read_during_write_mode_port_a => "DONT_CARE",
+ width_a => 32,
+ width_byteena_a => 4,
+ widthad_a => 15
+ )
+ port map(
+ address_a => address,
+ byteena_a => byteenable,
+ clock0 => clk,
+ clocken0 => clocken0,
+ data_a => writedata,
+ q_a => internal_readdata,
+ wren_a => wren
);
- end component altsyncram;
- signal clocken0 : std_logic;
- signal internal_readdata : std_logic_vector(31 downto 0);
- signal wren : std_logic;
-begin
- wren <= chipselect and write;
- clocken0 <= clken and not reset_req;
- the_altsyncram : altsyncram
- generic map(
- byte_size => 8,
- init_file => INIT_FILE,
- lpm_type => "altsyncram",
- maximum_depth => 32768,
- numwords_a => 32768,
- operation_mode => "SINGLE_PORT",
- outdata_reg_a => "UNREGISTERED",
- ram_block_type => "AUTO",
- read_during_write_mode_mixed_ports => "DONT_CARE",
- read_during_write_mode_port_a => "DONT_CARE",
- width_a => 32,
- width_byteena_a => 4,
- widthad_a => 15
- )
- port map(
- address_a => address,
- byteena_a => byteenable,
- clock0 => clk,
- clocken0 => clocken0,
- data_a => writedata,
- q_a => internal_readdata,
- wren_a => wren
- );
- --s1, which is an e_avalon_slave
- --s2, which is an e_avalon_slave
- --vhdl renameroo for output signals
- readdata <= internal_readdata;
-end europa;
+ --s1, which is an e_avalon_slave
+ --s2, which is an e_avalon_slave
+ --vhdl renameroo for output signals
+ readdata <= internal_readdata;
+ end europa;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
index f453120efc..500649d8da 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
@@ -1,28 +1,28 @@
- component qsys_unb2b_minimal_onchip_memory2_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- reset_req : in std_logic := 'X'; -- reset_req
- address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
- clken : in std_logic := 'X'; -- clken
- chipselect : in std_logic := 'X'; -- chipselect
- write : in std_logic := 'X'; -- write
- readdata : out std_logic_vector(31 downto 0); -- readdata
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
- );
- end component qsys_unb2b_minimal_onchip_memory2_0;
+component qsys_unb2b_minimal_onchip_memory2_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ reset_req : in std_logic := 'X'; -- reset_req
+ address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
+ clken : in std_logic := 'X'; -- clken
+ chipselect : in std_logic := 'X'; -- chipselect
+ write : in std_logic := 'X'; -- write
+ readdata : out std_logic_vector(31 downto 0); -- readdata
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
+ );
+end component qsys_unb2b_minimal_onchip_memory2_0;
- u0 : component qsys_unb2b_minimal_onchip_memory2_0
- port map (
- clk => CONNECTED_TO_clk, -- clk1.clk
- reset => CONNECTED_TO_reset, -- reset1.reset
- reset_req => CONNECTED_TO_reset_req, -- .reset_req
- address => CONNECTED_TO_address, -- s1.address
- clken => CONNECTED_TO_clken, -- .clken
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write => CONNECTED_TO_write, -- .write
- readdata => CONNECTED_TO_readdata, -- .readdata
- writedata => CONNECTED_TO_writedata, -- .writedata
- byteenable => CONNECTED_TO_byteenable -- .byteenable
- );
+u0 : component qsys_unb2b_minimal_onchip_memory2_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk1.clk
+ reset => CONNECTED_TO_reset, -- reset1.reset
+ reset_req => CONNECTED_TO_reset_req, -- .reset_req
+ address => CONNECTED_TO_address, -- s1.address
+ clken => CONNECTED_TO_clken, -- .clken
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ write => CONNECTED_TO_write, -- .write
+ readdata => CONNECTED_TO_readdata, -- .readdata
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ byteenable => CONNECTED_TO_byteenable -- .byteenable
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
index 580187433d..faef008bb8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_pio_pps is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_pio_pps;
+component qsys_unb2b_minimal_pio_pps is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_pio_pps;
- u0 : component qsys_unb2b_minimal_pio_pps
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_pio_pps
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
index b05a01d444..031eaa0af9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_pio_system_info is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_pio_system_info;
+component qsys_unb2b_minimal_pio_system_info is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_pio_system_info;
- u0 : component qsys_unb2b_minimal_pio_system_info
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_pio_system_info
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
index 0cc60e970e..d01f9d0090 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
@@ -15,36 +15,37 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
- port (
- -- inputs:
- signal address : in std_logic_vector(1 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal reset_n : in std_logic;
- signal write_n : in std_logic;
- signal writedata : in std_logic_vector(31 downto 0);
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(1 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal reset_n : in std_logic;
+ signal write_n : in std_logic;
+ signal writedata : in std_logic_vector(31 downto 0);
- -- outputs:
- signal out_port : out std_logic;
- signal readdata : out std_logic_vector(31 downto 0)
- );
-end entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq;
+ -- outputs:
+ signal out_port : out std_logic;
+ signal readdata : out std_logic_vector(
+ 31 downto 0)
+ );
+ end entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq;
architecture europa of qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
- signal clk_en : std_logic;
- signal data_out : std_logic;
- signal read_mux_out : std_logic;
+ signal clk_en : std_logic;
+ signal data_out : std_logic;
+ signal read_mux_out : std_logic;
begin
clk_en <= std_logic'('1');
--s1, which is an e_avalon_slave
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
index 4639e141f5..0b7dcff402 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
@@ -1,24 +1,24 @@
- component qsys_unb2b_minimal_pio_wdi is
- port (
- clk : in std_logic := 'X'; -- clk
- out_port : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
- write_n : in std_logic := 'X'; -- write_n
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- chipselect : in std_logic := 'X'; -- chipselect
- readdata : out std_logic_vector(31 downto 0) -- readdata
- );
- end component qsys_unb2b_minimal_pio_wdi;
+component qsys_unb2b_minimal_pio_wdi is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ out_port : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
+ write_n : in std_logic := 'X'; -- write_n
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ chipselect : in std_logic := 'X'; -- chipselect
+ readdata : out std_logic_vector(31 downto 0) -- readdata
+ );
+end component qsys_unb2b_minimal_pio_wdi;
- u0 : component qsys_unb2b_minimal_pio_wdi
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- out_port => CONNECTED_TO_out_port, -- external_connection.export
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- write_n => CONNECTED_TO_write_n, -- .write_n
- writedata => CONNECTED_TO_writedata, -- .writedata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- readdata => CONNECTED_TO_readdata -- .readdata
- );
+u0 : component qsys_unb2b_minimal_pio_wdi
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ out_port => CONNECTED_TO_out_port, -- external_connection.export
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ address => CONNECTED_TO_address, -- s1.address
+ write_n => CONNECTED_TO_write_n, -- .write_n
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ readdata => CONNECTED_TO_readdata -- .readdata
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
index ec32464391..b7feaef425 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_dpmm_ctrl is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_dpmm_ctrl;
+component qsys_unb2b_minimal_reg_dpmm_ctrl is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_dpmm_ctrl;
- u0 : component qsys_unb2b_minimal_reg_dpmm_ctrl
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_dpmm_ctrl
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
index 902a48132b..c3c65aee84 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_dpmm_data is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_dpmm_data;
+component qsys_unb2b_minimal_reg_dpmm_data is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_dpmm_data;
- u0 : component qsys_unb2b_minimal_reg_dpmm_data
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_dpmm_data
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
index b7e771b662..7cae834a56 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_epcs is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_epcs;
+component qsys_unb2b_minimal_reg_epcs is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_epcs;
- u0 : component qsys_unb2b_minimal_reg_epcs
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_epcs
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
index 170f85ed58..7a32df88c6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_fpga_temp_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_fpga_temp_sens;
+component qsys_unb2b_minimal_reg_fpga_temp_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_fpga_temp_sens;
- u0 : component qsys_unb2b_minimal_reg_fpga_temp_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_fpga_temp_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
index 495dae0b21..cfde8e9176 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_fpga_voltage_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_fpga_voltage_sens;
+component qsys_unb2b_minimal_reg_fpga_voltage_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_fpga_voltage_sens;
- u0 : component qsys_unb2b_minimal_reg_fpga_voltage_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_fpga_voltage_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
index e099a81cd1..73c8f9c0cf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_mmdp_ctrl is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_mmdp_ctrl;
+component qsys_unb2b_minimal_reg_mmdp_ctrl is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_mmdp_ctrl;
- u0 : component qsys_unb2b_minimal_reg_mmdp_ctrl
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_mmdp_ctrl
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
index d25eb92a9c..c9c4463043 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_mmdp_data is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_mmdp_data;
+component qsys_unb2b_minimal_reg_mmdp_data is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_mmdp_data;
- u0 : component qsys_unb2b_minimal_reg_mmdp_data
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_mmdp_data
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
index 837cb45819..e54b9651be 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_remu is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_remu;
+component qsys_unb2b_minimal_reg_remu is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_remu;
- u0 : component qsys_unb2b_minimal_reg_remu
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_remu
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
index b97ef222ec..c9fdcffd9c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_unb_pmbus is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_unb_pmbus;
+component qsys_unb2b_minimal_reg_unb_pmbus is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_unb_pmbus;
- u0 : component qsys_unb2b_minimal_reg_unb_pmbus
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_unb_pmbus
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
index 1871be2f74..c80cce2d60 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_unb_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_unb_sens;
+component qsys_unb2b_minimal_reg_unb_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_unb_sens;
- u0 : component qsys_unb2b_minimal_reg_unb_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_unb_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
index 229a2d315e..f956b5a4e7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_wdi is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_wdi;
+component qsys_unb2b_minimal_reg_wdi is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_wdi;
- u0 : component qsys_unb2b_minimal_reg_wdi
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_wdi
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
index ae35f2bd19..ed9ccedfa9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_rom_system_info is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_rom_system_info;
+component qsys_unb2b_minimal_rom_system_info is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_rom_system_info;
- u0 : component qsys_unb2b_minimal_rom_system_info
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_rom_system_info
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
index a954c70405..70d139b638 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
@@ -15,51 +15,52 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
- port (
- -- inputs:
- signal address : in std_logic_vector(2 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal reset_n : in std_logic;
- signal write_n : in std_logic;
- signal writedata : in std_logic_vector(15 downto 0);
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(2 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal reset_n : in std_logic;
+ signal write_n : in std_logic;
+ signal writedata : in std_logic_vector(15 downto 0);
- -- outputs:
- signal irq : out std_logic;
- signal readdata : out std_logic_vector(15 downto 0)
- );
-end entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby;
+ -- outputs:
+ signal irq : out std_logic;
+ signal readdata : out std_logic_vector(
+ 15 downto 0)
+ );
+ end entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby;
architecture europa of qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
- signal clk_en : std_logic;
- signal control_interrupt_enable : std_logic;
- signal control_register : std_logic;
- signal control_wr_strobe : std_logic;
- signal counter_is_running : std_logic;
- signal counter_is_zero : std_logic;
- signal counter_load_value : std_logic_vector(16 downto 0);
- signal delayed_unxcounter_is_zeroxx0 : std_logic;
- signal do_start_counter : std_logic;
- signal do_stop_counter : std_logic;
- signal force_reload : std_logic;
- signal internal_counter : std_logic_vector(16 downto 0);
- signal period_h_wr_strobe : std_logic;
- signal period_l_wr_strobe : std_logic;
- signal read_mux_out : std_logic_vector(15 downto 0);
- signal status_wr_strobe : std_logic;
- signal timeout_event : std_logic;
- signal timeout_occurred : std_logic;
+ signal clk_en : std_logic;
+ signal control_interrupt_enable : std_logic;
+ signal control_register : std_logic;
+ signal control_wr_strobe : std_logic;
+ signal counter_is_running : std_logic;
+ signal counter_is_zero : std_logic;
+ signal counter_load_value : std_logic_vector(16 downto 0);
+ signal delayed_unxcounter_is_zeroxx0 : std_logic;
+ signal do_start_counter : std_logic;
+ signal do_stop_counter : std_logic;
+ signal force_reload : std_logic;
+ signal internal_counter : std_logic_vector(16 downto 0);
+ signal period_h_wr_strobe : std_logic;
+ signal period_l_wr_strobe : std_logic;
+ signal read_mux_out : std_logic_vector(15 downto 0);
+ signal status_wr_strobe : std_logic;
+ signal timeout_event : std_logic;
+ signal timeout_occurred : std_logic;
begin
clk_en <= std_logic'('1');
process (clk, reset_n)
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
index ff04a90d2b..e6864d98a9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
@@ -1,24 +1,24 @@
- component qsys_unb2b_minimal_timer_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- irq : out std_logic; -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
- writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
- readdata : out std_logic_vector(15 downto 0); -- readdata
- chipselect : in std_logic := 'X'; -- chipselect
- write_n : in std_logic := 'X' -- write_n
- );
- end component qsys_unb2b_minimal_timer_0;
+component qsys_unb2b_minimal_timer_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ irq : out std_logic; -- irq
+ reset_n : in std_logic := 'X'; -- reset_n
+ address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
+ writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
+ readdata : out std_logic_vector(15 downto 0); -- readdata
+ chipselect : in std_logic := 'X'; -- chipselect
+ write_n : in std_logic := 'X' -- write_n
+ );
+end component qsys_unb2b_minimal_timer_0;
- u0 : component qsys_unb2b_minimal_timer_0
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- writedata => CONNECTED_TO_writedata, -- .writedata
- readdata => CONNECTED_TO_readdata, -- .readdata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write_n => CONNECTED_TO_write_n -- .write_n
- );
+u0 : component qsys_unb2b_minimal_timer_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ irq => CONNECTED_TO_irq, -- irq.irq
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ address => CONNECTED_TO_address, -- s1.address
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ readdata => CONNECTED_TO_readdata, -- .readdata
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ write_n => CONNECTED_TO_write_n -- .write_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
index 5e0e90fde0..0d89cb41bb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, unb2b_jesd_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb2b_jesd_node0 is
generic (
@@ -45,7 +45,7 @@ entity unb2b_jesd_node0 is
);
port (
-- GENERAL
--- CLK : IN STD_LOGIC; -- System Clock
+ -- CLK : IN STD_LOGIC; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
INTA : inout std_logic; -- FPGA interconnect line
@@ -82,49 +82,49 @@ end unb2b_jesd_node0;
architecture str of unb2b_jesd_node0 is
begin
u_revision : entity unb2b_jesd_lib.unb2b_jesd
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_technology => g_technology,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- GENERAL
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- GENERAL
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
- -- 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED,
+ QSFP_LED => QSFP_LED,
- -- JESD signals
- jesd204_rx_serial_data => jesd204_rx_serial_data,
- jesd204_sync_n_out => jesd204_sync_n_out,
- jesd204_rx_sysref => jesd204_rx_sysref,
- jesd204_device_clk => jesd204_device_clk
- );
+ -- JESD signals
+ jesd204_rx_serial_data => jesd204_rx_serial_data,
+ jesd204_sync_n_out => jesd204_sync_n_out,
+ jesd204_rx_sysref => jesd204_rx_sysref,
+ jesd204_device_clk => jesd204_device_clk
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
index 1188b1f4a3..1c2fecffe6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
@@ -1,18 +1,18 @@
- component altjesd_ss_RX_corepll is
- port (
- locked : out std_logic; -- export
- outclk_0 : out std_logic; -- clk
- outclk_1 : out std_logic; -- clk
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X' -- reset
- );
- end component altjesd_ss_RX_corepll;
+component altjesd_ss_RX_corepll is
+ port (
+ locked : out std_logic; -- export
+ outclk_0 : out std_logic; -- clk
+ outclk_1 : out std_logic; -- clk
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X' -- reset
+ );
+end component altjesd_ss_RX_corepll;
- u0 : component altjesd_ss_RX_corepll
- port map (
- locked => CONNECTED_TO_locked, -- locked.export
- outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk
- outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
- refclk => CONNECTED_TO_refclk, -- refclk.clk
- rst => CONNECTED_TO_rst -- reset.reset
- );
+u0 : component altjesd_ss_RX_corepll
+ port map (
+ locked => CONNECTED_TO_locked, -- locked.export
+ outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk
+ outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
+ refclk => CONNECTED_TO_refclk, -- refclk.clk
+ rst => CONNECTED_TO_rst -- reset.reset
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
index 4d125d7d6b..c9239eba0d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
@@ -1,14 +1,14 @@
- component altjesd_ss_RX_frame_reset is
- port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
- );
- end component altjesd_ss_RX_frame_reset;
+component altjesd_ss_RX_frame_reset is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in_reset_n : in std_logic := 'X'; -- reset_n
+ out_reset_n : out std_logic -- reset_n
+ );
+end component altjesd_ss_RX_frame_reset;
- u0 : component altjesd_ss_RX_frame_reset
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+u0 : component altjesd_ss_RX_frame_reset
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
index 2fdfadb51a..9ff4466cf1 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
@@ -1,14 +1,14 @@
- component altjesd_ss_RX_link_reset is
- port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
- );
- end component altjesd_ss_RX_link_reset;
+component altjesd_ss_RX_link_reset is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in_reset_n : in std_logic := 'X'; -- reset_n
+ out_reset_n : out std_logic -- reset_n
+ );
+end component altjesd_ss_RX_link_reset;
- u0 : component altjesd_ss_RX_link_reset
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+u0 : component altjesd_ss_RX_link_reset
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
index f5e2ba1f77..556545d436 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
@@ -1,162 +1,162 @@
- component altjesd_ss_RX_reset_seq is
- generic (
- NUM_OUTPUTS : integer := 3;
- ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
- ENABLE_ASSERTION_SEQUENCE : integer := 0;
- ENABLE_DEASSERTION_SEQUENCE : integer := 0;
- MIN_ASRT_TIME : integer := 0;
- ASRT_DELAY0 : integer := 0;
- DSRT_DELAY0 : integer := 0;
- ASRT_REMAP0 : integer := 0;
- DSRT_REMAP0 : integer := 0;
- DSRT_QUALCNT_0 : integer := 0;
- ASRT_DELAY1 : integer := 0;
- DSRT_DELAY1 : integer := 0;
- ASRT_REMAP1 : integer := 1;
- DSRT_REMAP1 : integer := 1;
- DSRT_QUALCNT_1 : integer := 0;
- ASRT_DELAY2 : integer := 0;
- DSRT_DELAY2 : integer := 0;
- ASRT_REMAP2 : integer := 2;
- DSRT_REMAP2 : integer := 2;
- DSRT_QUALCNT_2 : integer := 0;
- ASRT_DELAY3 : integer := 0;
- DSRT_DELAY3 : integer := 0;
- ASRT_REMAP3 : integer := 3;
- DSRT_REMAP3 : integer := 3;
- DSRT_QUALCNT_3 : integer := 0;
- ASRT_DELAY4 : integer := 0;
- DSRT_DELAY4 : integer := 0;
- ASRT_REMAP4 : integer := 4;
- DSRT_REMAP4 : integer := 4;
- DSRT_QUALCNT_4 : integer := 0;
- ASRT_DELAY5 : integer := 0;
- DSRT_DELAY5 : integer := 0;
- ASRT_REMAP5 : integer := 5;
- DSRT_REMAP5 : integer := 5;
- DSRT_QUALCNT_5 : integer := 0;
- ASRT_DELAY6 : integer := 0;
- DSRT_DELAY6 : integer := 0;
- ASRT_REMAP6 : integer := 6;
- DSRT_REMAP6 : integer := 6;
- DSRT_QUALCNT_6 : integer := 0;
- ASRT_DELAY7 : integer := 0;
- DSRT_DELAY7 : integer := 0;
- ASRT_REMAP7 : integer := 7;
- DSRT_REMAP7 : integer := 7;
- DSRT_QUALCNT_7 : integer := 0;
- ASRT_DELAY8 : integer := 0;
- DSRT_DELAY8 : integer := 0;
- ASRT_REMAP8 : integer := 8;
- DSRT_REMAP8 : integer := 8;
- DSRT_QUALCNT_8 : integer := 0;
- ASRT_DELAY9 : integer := 0;
- DSRT_DELAY9 : integer := 0;
- ASRT_REMAP9 : integer := 9;
- DSRT_REMAP9 : integer := 9;
- DSRT_QUALCNT_9 : integer := 0
- );
- port (
- av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_read : in std_logic := 'X'; -- read
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_write : in std_logic := 'X'; -- write
- irq : out std_logic; -- irq
- clk : in std_logic := 'X'; -- clk
- csr_reset : in std_logic := 'X'; -- reset
- reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
- reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
- reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
- reset_in0 : in std_logic := 'X'; -- reset
- reset_out0 : out std_logic; -- reset
- reset_out1 : out std_logic; -- reset
- reset_out2 : out std_logic; -- reset
- reset_out3 : out std_logic; -- reset
- reset_out4 : out std_logic; -- reset
- reset_out5 : out std_logic; -- reset
- reset_out6 : out std_logic; -- reset
- reset_out7 : out std_logic -- reset
- );
- end component altjesd_ss_RX_reset_seq;
+component altjesd_ss_RX_reset_seq is
+ generic (
+ NUM_OUTPUTS : integer := 3;
+ ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
+ ENABLE_ASSERTION_SEQUENCE : integer := 0;
+ ENABLE_DEASSERTION_SEQUENCE : integer := 0;
+ MIN_ASRT_TIME : integer := 0;
+ ASRT_DELAY0 : integer := 0;
+ DSRT_DELAY0 : integer := 0;
+ ASRT_REMAP0 : integer := 0;
+ DSRT_REMAP0 : integer := 0;
+ DSRT_QUALCNT_0 : integer := 0;
+ ASRT_DELAY1 : integer := 0;
+ DSRT_DELAY1 : integer := 0;
+ ASRT_REMAP1 : integer := 1;
+ DSRT_REMAP1 : integer := 1;
+ DSRT_QUALCNT_1 : integer := 0;
+ ASRT_DELAY2 : integer := 0;
+ DSRT_DELAY2 : integer := 0;
+ ASRT_REMAP2 : integer := 2;
+ DSRT_REMAP2 : integer := 2;
+ DSRT_QUALCNT_2 : integer := 0;
+ ASRT_DELAY3 : integer := 0;
+ DSRT_DELAY3 : integer := 0;
+ ASRT_REMAP3 : integer := 3;
+ DSRT_REMAP3 : integer := 3;
+ DSRT_QUALCNT_3 : integer := 0;
+ ASRT_DELAY4 : integer := 0;
+ DSRT_DELAY4 : integer := 0;
+ ASRT_REMAP4 : integer := 4;
+ DSRT_REMAP4 : integer := 4;
+ DSRT_QUALCNT_4 : integer := 0;
+ ASRT_DELAY5 : integer := 0;
+ DSRT_DELAY5 : integer := 0;
+ ASRT_REMAP5 : integer := 5;
+ DSRT_REMAP5 : integer := 5;
+ DSRT_QUALCNT_5 : integer := 0;
+ ASRT_DELAY6 : integer := 0;
+ DSRT_DELAY6 : integer := 0;
+ ASRT_REMAP6 : integer := 6;
+ DSRT_REMAP6 : integer := 6;
+ DSRT_QUALCNT_6 : integer := 0;
+ ASRT_DELAY7 : integer := 0;
+ DSRT_DELAY7 : integer := 0;
+ ASRT_REMAP7 : integer := 7;
+ DSRT_REMAP7 : integer := 7;
+ DSRT_QUALCNT_7 : integer := 0;
+ ASRT_DELAY8 : integer := 0;
+ DSRT_DELAY8 : integer := 0;
+ ASRT_REMAP8 : integer := 8;
+ DSRT_REMAP8 : integer := 8;
+ DSRT_QUALCNT_8 : integer := 0;
+ ASRT_DELAY9 : integer := 0;
+ DSRT_DELAY9 : integer := 0;
+ ASRT_REMAP9 : integer := 9;
+ DSRT_REMAP9 : integer := 9;
+ DSRT_QUALCNT_9 : integer := 0
+ );
+ port (
+ av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_read : in std_logic := 'X'; -- read
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_write : in std_logic := 'X'; -- write
+ irq : out std_logic; -- irq
+ clk : in std_logic := 'X'; -- clk
+ csr_reset : in std_logic := 'X'; -- reset
+ reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
+ reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
+ reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
+ reset_in0 : in std_logic := 'X'; -- reset
+ reset_out0 : out std_logic; -- reset
+ reset_out1 : out std_logic; -- reset
+ reset_out2 : out std_logic; -- reset
+ reset_out3 : out std_logic; -- reset
+ reset_out4 : out std_logic; -- reset
+ reset_out5 : out std_logic; -- reset
+ reset_out6 : out std_logic; -- reset
+ reset_out7 : out std_logic -- reset
+ );
+end component altjesd_ss_RX_reset_seq;
- u0 : component altjesd_ss_RX_reset_seq
- generic map (
- NUM_OUTPUTS => INTEGER_VALUE_FOR_NUM_OUTPUTS,
- ENABLE_DEASSERTION_INPUT_QUAL => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_INPUT_QUAL,
- ENABLE_ASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_ASSERTION_SEQUENCE,
- ENABLE_DEASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_SEQUENCE,
- MIN_ASRT_TIME => INTEGER_VALUE_FOR_MIN_ASRT_TIME,
- ASRT_DELAY0 => INTEGER_VALUE_FOR_ASRT_DELAY0,
- DSRT_DELAY0 => INTEGER_VALUE_FOR_DSRT_DELAY0,
- ASRT_REMAP0 => INTEGER_VALUE_FOR_ASRT_REMAP0,
- DSRT_REMAP0 => INTEGER_VALUE_FOR_DSRT_REMAP0,
- DSRT_QUALCNT_0 => INTEGER_VALUE_FOR_DSRT_QUALCNT_0,
- ASRT_DELAY1 => INTEGER_VALUE_FOR_ASRT_DELAY1,
- DSRT_DELAY1 => INTEGER_VALUE_FOR_DSRT_DELAY1,
- ASRT_REMAP1 => INTEGER_VALUE_FOR_ASRT_REMAP1,
- DSRT_REMAP1 => INTEGER_VALUE_FOR_DSRT_REMAP1,
- DSRT_QUALCNT_1 => INTEGER_VALUE_FOR_DSRT_QUALCNT_1,
- ASRT_DELAY2 => INTEGER_VALUE_FOR_ASRT_DELAY2,
- DSRT_DELAY2 => INTEGER_VALUE_FOR_DSRT_DELAY2,
- ASRT_REMAP2 => INTEGER_VALUE_FOR_ASRT_REMAP2,
- DSRT_REMAP2 => INTEGER_VALUE_FOR_DSRT_REMAP2,
- DSRT_QUALCNT_2 => INTEGER_VALUE_FOR_DSRT_QUALCNT_2,
- ASRT_DELAY3 => INTEGER_VALUE_FOR_ASRT_DELAY3,
- DSRT_DELAY3 => INTEGER_VALUE_FOR_DSRT_DELAY3,
- ASRT_REMAP3 => INTEGER_VALUE_FOR_ASRT_REMAP3,
- DSRT_REMAP3 => INTEGER_VALUE_FOR_DSRT_REMAP3,
- DSRT_QUALCNT_3 => INTEGER_VALUE_FOR_DSRT_QUALCNT_3,
- ASRT_DELAY4 => INTEGER_VALUE_FOR_ASRT_DELAY4,
- DSRT_DELAY4 => INTEGER_VALUE_FOR_DSRT_DELAY4,
- ASRT_REMAP4 => INTEGER_VALUE_FOR_ASRT_REMAP4,
- DSRT_REMAP4 => INTEGER_VALUE_FOR_DSRT_REMAP4,
- DSRT_QUALCNT_4 => INTEGER_VALUE_FOR_DSRT_QUALCNT_4,
- ASRT_DELAY5 => INTEGER_VALUE_FOR_ASRT_DELAY5,
- DSRT_DELAY5 => INTEGER_VALUE_FOR_DSRT_DELAY5,
- ASRT_REMAP5 => INTEGER_VALUE_FOR_ASRT_REMAP5,
- DSRT_REMAP5 => INTEGER_VALUE_FOR_DSRT_REMAP5,
- DSRT_QUALCNT_5 => INTEGER_VALUE_FOR_DSRT_QUALCNT_5,
- ASRT_DELAY6 => INTEGER_VALUE_FOR_ASRT_DELAY6,
- DSRT_DELAY6 => INTEGER_VALUE_FOR_DSRT_DELAY6,
- ASRT_REMAP6 => INTEGER_VALUE_FOR_ASRT_REMAP6,
- DSRT_REMAP6 => INTEGER_VALUE_FOR_DSRT_REMAP6,
- DSRT_QUALCNT_6 => INTEGER_VALUE_FOR_DSRT_QUALCNT_6,
- ASRT_DELAY7 => INTEGER_VALUE_FOR_ASRT_DELAY7,
- DSRT_DELAY7 => INTEGER_VALUE_FOR_DSRT_DELAY7,
- ASRT_REMAP7 => INTEGER_VALUE_FOR_ASRT_REMAP7,
- DSRT_REMAP7 => INTEGER_VALUE_FOR_DSRT_REMAP7,
- DSRT_QUALCNT_7 => INTEGER_VALUE_FOR_DSRT_QUALCNT_7,
- ASRT_DELAY8 => INTEGER_VALUE_FOR_ASRT_DELAY8,
- DSRT_DELAY8 => INTEGER_VALUE_FOR_DSRT_DELAY8,
- ASRT_REMAP8 => INTEGER_VALUE_FOR_ASRT_REMAP8,
- DSRT_REMAP8 => INTEGER_VALUE_FOR_DSRT_REMAP8,
- DSRT_QUALCNT_8 => INTEGER_VALUE_FOR_DSRT_QUALCNT_8,
- ASRT_DELAY9 => INTEGER_VALUE_FOR_ASRT_DELAY9,
- DSRT_DELAY9 => INTEGER_VALUE_FOR_DSRT_DELAY9,
- ASRT_REMAP9 => INTEGER_VALUE_FOR_ASRT_REMAP9,
- DSRT_REMAP9 => INTEGER_VALUE_FOR_DSRT_REMAP9,
- DSRT_QUALCNT_9 => INTEGER_VALUE_FOR_DSRT_QUALCNT_9
- )
- port map (
- av_address => CONNECTED_TO_av_address, -- av_csr.address
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_read => CONNECTED_TO_av_read, -- .read
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_write => CONNECTED_TO_av_write, -- .write
- irq => CONNECTED_TO_irq, -- av_csr_irq.irq
- clk => CONNECTED_TO_clk, -- clk.clk
- csr_reset => CONNECTED_TO_csr_reset, -- csr_reset.reset
- reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual, -- reset1_dsrt_qual.reset1_dsrt_qual
- reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual, -- reset2_dsrt_qual.reset2_dsrt_qual
- reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual, -- reset5_dsrt_qual.reset5_dsrt_qual
- reset_in0 => CONNECTED_TO_reset_in0, -- reset_in0.reset
- reset_out0 => CONNECTED_TO_reset_out0, -- reset_out0.reset
- reset_out1 => CONNECTED_TO_reset_out1, -- reset_out1.reset
- reset_out2 => CONNECTED_TO_reset_out2, -- reset_out2.reset
- reset_out3 => CONNECTED_TO_reset_out3, -- reset_out3.reset
- reset_out4 => CONNECTED_TO_reset_out4, -- reset_out4.reset
- reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
- reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
- reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
- );
+u0 : component altjesd_ss_RX_reset_seq
+ generic map (
+ NUM_OUTPUTS => INTEGER_VALUE_FOR_NUM_OUTPUTS,
+ ENABLE_DEASSERTION_INPUT_QUAL => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_INPUT_QUAL,
+ ENABLE_ASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_ASSERTION_SEQUENCE,
+ ENABLE_DEASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_SEQUENCE,
+ MIN_ASRT_TIME => INTEGER_VALUE_FOR_MIN_ASRT_TIME,
+ ASRT_DELAY0 => INTEGER_VALUE_FOR_ASRT_DELAY0,
+ DSRT_DELAY0 => INTEGER_VALUE_FOR_DSRT_DELAY0,
+ ASRT_REMAP0 => INTEGER_VALUE_FOR_ASRT_REMAP0,
+ DSRT_REMAP0 => INTEGER_VALUE_FOR_DSRT_REMAP0,
+ DSRT_QUALCNT_0 => INTEGER_VALUE_FOR_DSRT_QUALCNT_0,
+ ASRT_DELAY1 => INTEGER_VALUE_FOR_ASRT_DELAY1,
+ DSRT_DELAY1 => INTEGER_VALUE_FOR_DSRT_DELAY1,
+ ASRT_REMAP1 => INTEGER_VALUE_FOR_ASRT_REMAP1,
+ DSRT_REMAP1 => INTEGER_VALUE_FOR_DSRT_REMAP1,
+ DSRT_QUALCNT_1 => INTEGER_VALUE_FOR_DSRT_QUALCNT_1,
+ ASRT_DELAY2 => INTEGER_VALUE_FOR_ASRT_DELAY2,
+ DSRT_DELAY2 => INTEGER_VALUE_FOR_DSRT_DELAY2,
+ ASRT_REMAP2 => INTEGER_VALUE_FOR_ASRT_REMAP2,
+ DSRT_REMAP2 => INTEGER_VALUE_FOR_DSRT_REMAP2,
+ DSRT_QUALCNT_2 => INTEGER_VALUE_FOR_DSRT_QUALCNT_2,
+ ASRT_DELAY3 => INTEGER_VALUE_FOR_ASRT_DELAY3,
+ DSRT_DELAY3 => INTEGER_VALUE_FOR_DSRT_DELAY3,
+ ASRT_REMAP3 => INTEGER_VALUE_FOR_ASRT_REMAP3,
+ DSRT_REMAP3 => INTEGER_VALUE_FOR_DSRT_REMAP3,
+ DSRT_QUALCNT_3 => INTEGER_VALUE_FOR_DSRT_QUALCNT_3,
+ ASRT_DELAY4 => INTEGER_VALUE_FOR_ASRT_DELAY4,
+ DSRT_DELAY4 => INTEGER_VALUE_FOR_DSRT_DELAY4,
+ ASRT_REMAP4 => INTEGER_VALUE_FOR_ASRT_REMAP4,
+ DSRT_REMAP4 => INTEGER_VALUE_FOR_DSRT_REMAP4,
+ DSRT_QUALCNT_4 => INTEGER_VALUE_FOR_DSRT_QUALCNT_4,
+ ASRT_DELAY5 => INTEGER_VALUE_FOR_ASRT_DELAY5,
+ DSRT_DELAY5 => INTEGER_VALUE_FOR_DSRT_DELAY5,
+ ASRT_REMAP5 => INTEGER_VALUE_FOR_ASRT_REMAP5,
+ DSRT_REMAP5 => INTEGER_VALUE_FOR_DSRT_REMAP5,
+ DSRT_QUALCNT_5 => INTEGER_VALUE_FOR_DSRT_QUALCNT_5,
+ ASRT_DELAY6 => INTEGER_VALUE_FOR_ASRT_DELAY6,
+ DSRT_DELAY6 => INTEGER_VALUE_FOR_DSRT_DELAY6,
+ ASRT_REMAP6 => INTEGER_VALUE_FOR_ASRT_REMAP6,
+ DSRT_REMAP6 => INTEGER_VALUE_FOR_DSRT_REMAP6,
+ DSRT_QUALCNT_6 => INTEGER_VALUE_FOR_DSRT_QUALCNT_6,
+ ASRT_DELAY7 => INTEGER_VALUE_FOR_ASRT_DELAY7,
+ DSRT_DELAY7 => INTEGER_VALUE_FOR_DSRT_DELAY7,
+ ASRT_REMAP7 => INTEGER_VALUE_FOR_ASRT_REMAP7,
+ DSRT_REMAP7 => INTEGER_VALUE_FOR_DSRT_REMAP7,
+ DSRT_QUALCNT_7 => INTEGER_VALUE_FOR_DSRT_QUALCNT_7,
+ ASRT_DELAY8 => INTEGER_VALUE_FOR_ASRT_DELAY8,
+ DSRT_DELAY8 => INTEGER_VALUE_FOR_DSRT_DELAY8,
+ ASRT_REMAP8 => INTEGER_VALUE_FOR_ASRT_REMAP8,
+ DSRT_REMAP8 => INTEGER_VALUE_FOR_DSRT_REMAP8,
+ DSRT_QUALCNT_8 => INTEGER_VALUE_FOR_DSRT_QUALCNT_8,
+ ASRT_DELAY9 => INTEGER_VALUE_FOR_ASRT_DELAY9,
+ DSRT_DELAY9 => INTEGER_VALUE_FOR_DSRT_DELAY9,
+ ASRT_REMAP9 => INTEGER_VALUE_FOR_ASRT_REMAP9,
+ DSRT_REMAP9 => INTEGER_VALUE_FOR_DSRT_REMAP9,
+ DSRT_QUALCNT_9 => INTEGER_VALUE_FOR_DSRT_QUALCNT_9
+ )
+ port map (
+ av_address => CONNECTED_TO_av_address, -- av_csr.address
+ av_readdata => CONNECTED_TO_av_readdata, -- .readdata
+ av_read => CONNECTED_TO_av_read, -- .read
+ av_writedata => CONNECTED_TO_av_writedata, -- .writedata
+ av_write => CONNECTED_TO_av_write, -- .write
+ irq => CONNECTED_TO_irq, -- av_csr_irq.irq
+ clk => CONNECTED_TO_clk, -- clk.clk
+ csr_reset => CONNECTED_TO_csr_reset, -- csr_reset.reset
+ reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual, -- reset1_dsrt_qual.reset1_dsrt_qual
+ reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual, -- reset2_dsrt_qual.reset2_dsrt_qual
+ reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual, -- reset5_dsrt_qual.reset5_dsrt_qual
+ reset_in0 => CONNECTED_TO_reset_in0, -- reset_in0.reset
+ reset_out0 => CONNECTED_TO_reset_out0, -- reset_out0.reset
+ reset_out1 => CONNECTED_TO_reset_out1, -- reset_out1.reset
+ reset_out2 => CONNECTED_TO_reset_out2, -- reset_out2.reset
+ reset_out3 => CONNECTED_TO_reset_out3, -- reset_out3.reset
+ reset_out4 => CONNECTED_TO_reset_out4, -- reset_out4.reset
+ reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
+ reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
+ reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
index e49f93a337..bbdcb4db80 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
@@ -1,24 +1,24 @@
- component altjesd_ss_RX_xcvr_reset_control is
- port (
- clock : in std_logic := 'X'; -- clk
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- reset : in std_logic := 'X'; -- reset
- rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_cal_busy
- rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_ready : out std_logic_vector(0 downto 0) -- rx_ready
- );
- end component altjesd_ss_RX_xcvr_reset_control;
+component altjesd_ss_RX_xcvr_reset_control is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ reset : in std_logic := 'X'; -- reset
+ rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_cal_busy
+ rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_ready : out std_logic_vector(0 downto 0) -- rx_ready
+ );
+end component altjesd_ss_RX_xcvr_reset_control;
- u0 : component altjesd_ss_RX_xcvr_reset_control
- port map (
- clock => CONNECTED_TO_clock, -- clock.clk
- pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
- reset => CONNECTED_TO_reset, -- reset.reset
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
- );
+u0 : component altjesd_ss_RX_xcvr_reset_control
+ port map (
+ clock => CONNECTED_TO_clock, -- clock.clk
+ pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
+ reset => CONNECTED_TO_reset, -- reset.reset
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
index af64e25109..fa71f3dded 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
@@ -1,16 +1,16 @@
- component device_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component device_clk;
+component device_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component device_clk;
- u0 : component device_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component device_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
index 26992b63a4..59df25d1b2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
@@ -1,16 +1,16 @@
- component frame_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component frame_clk;
+component frame_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component frame_clk;
- u0 : component frame_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component frame_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
index 745dc1937c..a7de702cec 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
@@ -1,100 +1,100 @@
- component jesd is
- port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
- );
- end component jesd;
+component jesd is
+ port (
+ alldev_lane_aligned : in std_logic := 'X'; -- export
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ dev_lane_aligned : out std_logic; -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_rx_avs_read : in std_logic := 'X'; -- read
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_rx_avs_write : in std_logic := 'X'; -- write
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_frame_error : in std_logic := 'X'; -- export
+ jesd204_rx_int : out std_logic; -- irq
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ jesd204_rx_link_valid : out std_logic; -- valid
+ jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ rxlink_clk : in std_logic := 'X'; -- clk
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxphy_clk : out std_logic_vector(0 downto 0); -- export
+ sof : out std_logic_vector(3 downto 0); -- export
+ somf : out std_logic_vector(3 downto 0); -- export
+ sysref : in std_logic := 'X' -- export
+ );
+end component jesd;
- u0 : component jesd
- port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
- );
+u0 : component jesd
+ port map (
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
+ csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
+ csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
+ csr_f => CONNECTED_TO_csr_f, -- csr_f.export
+ csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
+ csr_k => CONNECTED_TO_csr_k, -- csr_k.export
+ csr_l => CONNECTED_TO_csr_l, -- csr_l.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
+ csr_m => CONNECTED_TO_csr_m, -- csr_m.export
+ csr_n => CONNECTED_TO_csr_n, -- csr_n.export
+ csr_np => CONNECTED_TO_csr_np, -- csr_np.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
+ csr_s => CONNECTED_TO_csr_s, -- csr_s.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
+ rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
+ rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
+ rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
+ sof => CONNECTED_TO_sof, -- sof.export
+ somf => CONNECTED_TO_somf, -- somf.export
+ sysref => CONNECTED_TO_sysref -- sysref.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
index acbc33a2d1..c5f8f7bcb0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
@@ -1,16 +1,16 @@
- component link_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component link_clk;
+component link_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component link_clk;
- u0 : component link_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component link_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
index 42aae3ddf0..2d82124533 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_avs_common_mm_0 is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_common_mm_0;
+component qsys_unb2b_minimal_avs_common_mm_0 is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_avs_common_mm_0;
- u0 : component qsys_unb2b_minimal_avs_common_mm_0
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_avs_common_mm_0
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
index 4ddaf7fa7d..a838049964 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_avs_common_mm_1 is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_common_mm_1;
+component qsys_unb2b_minimal_avs_common_mm_1 is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_avs_common_mm_1;
- u0 : component qsys_unb2b_minimal_avs_common_mm_1
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_avs_common_mm_1
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
index d648f26fb1..97ced47767 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
@@ -26,10 +26,10 @@
-- . The avs2_eth_coe_hw.tcl determines the read latency per port
library IEEE, common_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use work.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use work.eth_pkg.all;
entity avs2_eth_coe is
port (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
index e879f1b9ed..7f2c37e56a 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
@@ -23,9 +23,9 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_network_layers_pkg is
-- All *_len constants are in nof octets = nof bytes = c_8 bits
@@ -85,9 +85,10 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001");
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -134,221 +135,225 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
- constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
- c_network_ip_identification_len + c_network_ip_flags_fragment_len +
- c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
- c_network_ip_addr_len +
- c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
- -- default field values
- constant c_network_ip_version : natural := 4; -- 4 = IPv4,
- constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
- constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
- constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
- constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
- constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
- constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
- constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
- constant c_network_ip_header_checksum : natural := 0; -- init value
-
- -- useful field values
- constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
- constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
- constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
-
- constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
-
- type t_network_ip_header is record
- version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
- header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
- services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
- total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
- identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
- flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
- fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
- time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
- protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
- header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
- src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- end record;
-
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
-
- ------------------------------------------------------------------------------
- -- ARP Packet
- --
- -- 0 7 8 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Hardware Type | Protocol Type | 4
- -- |----------------------------------------------------------------------|
- -- | HW Addr Len | Prot Addr Len | Operation | 5
- -- |----------------------------------------------------------------------|
- -- | Sender Hardware Address | 6
- -- | ------------------------------------|
- -- | | | 7
- -- |---------------------------------/ /----------------------------------|
- -- | Sender Protocol Address | | 8
- -- |----------------------------------- |
- -- | Target Hardware Address | 9
- -- |----------------------------------------------------------------------|
- -- | Target Protocol Address | 10
- -- |----------------------------------------------------------------------|
- --
- -- Note that ARP header = ARP packet, because ARP has no payload
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_arp_htype_len : natural := 2;
- constant c_network_arp_htype_w : natural := c_network_arp_htype_len * c_8;
- constant c_network_arp_ptype_len : natural := 2;
- constant c_network_arp_ptype_w : natural := c_network_arp_ptype_len * c_8;
- constant c_network_arp_hlen_len : natural := 1;
- constant c_network_arp_hlen_w : natural := c_network_arp_hlen_len * c_8;
- constant c_network_arp_plen_len : natural := 1;
- constant c_network_arp_plen_w : natural := c_network_arp_plen_len * c_8;
- constant c_network_arp_oper_len : natural := 2;
- constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
-
- -- [0:15] [16:31]
- constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
- c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-
- -- default field values
- constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
- constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
- constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
- constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
- constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
- constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
-
- -- useful field values
- constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
- constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
-
- type t_network_arp_packet is record
- htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
- ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
- hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
- plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
- oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
- sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
- spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
- tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
- tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
- end record;
-
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
-
- ------------------------------------------------------------------------------
- -- ICMP (for ping)
- --
- -- 0 7 8 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Type | Code | Checksum | 9
- -- |----------------------------------------------------------------------|
- -- | ID | Sequence | 10
- -- |----------------------------------------------------------------------|
- -- | |
- -- | ICMP Payload (padding data) |
- -- | |
- -- |------------------------------------------------------------ // ------|
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_icmp_msg_type_len : natural := 1;
- constant c_network_icmp_msg_type_w : natural := c_network_icmp_msg_type_len * c_8;
- constant c_network_icmp_code_len : natural := 1;
- constant c_network_icmp_code_w : natural := c_network_icmp_code_len * c_8;
- constant c_network_icmp_checksum_len : natural := 2;
- constant c_network_icmp_checksum_w : natural := c_network_icmp_checksum_len * c_8;
- constant c_network_icmp_id_len : natural := 2;
- constant c_network_icmp_id_w : natural := c_network_icmp_id_len * c_8;
- constant c_network_icmp_sequence_len : natural := 2;
- constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
- constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
- c_network_icmp_id_len + c_network_icmp_sequence_len;
-
- -- default field values
- constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
- constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
- constant c_network_icmp_checksum : natural := 0; -- init value
-
- -- useful field values
- constant c_network_icmp_code : natural := 0; -- default
- constant c_network_icmp_id : natural := 3; -- arbitrary value
- constant c_network_icmp_sequence : natural := 4; -- arbitrary value
-
- type t_network_icmp_header is record
- msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
- code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
- checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
- id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
- sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
- end record;
-
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
-
- ------------------------------------------------------------------------------
- -- UDP Packet
- --
- -- 0 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Source Port | Destination Port | 9
- -- |----------------------------------------------------------------------|
- -- | Total Length | Checksum | 10
- -- |----------------------------------------------------------------------|
- -- | |
- -- | UDP Payload |
- -- | |
- -- |----------------------------------------------------------- // -------|
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_udp_port_len : natural := 2;
- constant c_network_udp_port_w : natural := c_network_udp_port_len * c_8;
- constant c_network_udp_total_length_len : natural := 2;
- constant c_network_udp_total_length_w : natural := c_network_udp_total_length_len * c_8;
- constant c_network_udp_checksum_len : natural := 2;
- constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
-
- -- [0:15] [16:31]
- constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
-
- -- default field values
- constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
- constant c_network_udp_checksum : natural := 0; -- init value
-
- -- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
-
- constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
- constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
- constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
-
- type t_network_udp_header is record
- src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
- checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
- end record;
-
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ -- [0:7] [8:15] [16:31]
+ constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
+ c_network_ip_identification_len + c_network_ip_flags_fragment_len +
+ c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
+ c_network_ip_addr_len +
+ c_network_ip_addr_len;
+ -- = c_network_ip_header_length * c_word_sz = 20
+ -- default field values
+ constant c_network_ip_version : natural := 4; -- 4 = IPv4,
+ constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
+ constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
+ constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
+ constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
+ constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
+ constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
+ constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
+ constant c_network_ip_header_checksum : natural := 0; -- init value
+
+ -- useful field values
+ constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
+ constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
+ constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
+
+ constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
+
+ type t_network_ip_header is record
+ version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
+ header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
+ services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
+ total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
+ identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
+ flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
+ fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
+ time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
+ protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
+ header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
+ src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ end record;
+
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001", "0001", "00000001", "0000000000000001",
+ "0000000000000001", "001", "0000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- ARP Packet
+ --
+ -- 0 7 8 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Hardware Type | Protocol Type | 4
+ -- |----------------------------------------------------------------------|
+ -- | HW Addr Len | Prot Addr Len | Operation | 5
+ -- |----------------------------------------------------------------------|
+ -- | Sender Hardware Address | 6
+ -- | ------------------------------------|
+ -- | | | 7
+ -- |---------------------------------/ /----------------------------------|
+ -- | Sender Protocol Address | | 8
+ -- |----------------------------------- |
+ -- | Target Hardware Address | 9
+ -- |----------------------------------------------------------------------|
+ -- | Target Protocol Address | 10
+ -- |----------------------------------------------------------------------|
+ --
+ -- Note that ARP header = ARP packet, because ARP has no payload
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_arp_htype_len : natural := 2;
+ constant c_network_arp_htype_w : natural := c_network_arp_htype_len * c_8;
+ constant c_network_arp_ptype_len : natural := 2;
+ constant c_network_arp_ptype_w : natural := c_network_arp_ptype_len * c_8;
+ constant c_network_arp_hlen_len : natural := 1;
+ constant c_network_arp_hlen_w : natural := c_network_arp_hlen_len * c_8;
+ constant c_network_arp_plen_len : natural := 1;
+ constant c_network_arp_plen_w : natural := c_network_arp_plen_len * c_8;
+ constant c_network_arp_oper_len : natural := 2;
+ constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
+
+ -- [0:15] [16:31]
+ constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
+ c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len;
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+
+ -- default field values
+ constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
+ constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
+ constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
+ constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
+ constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
+ constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
+
+ -- useful field values
+ constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
+ constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
+
+ type t_network_arp_packet is record
+ htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
+ ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
+ hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
+ plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
+ oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
+ sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
+ spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
+ tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
+ tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
+ end record;
+
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001", "0000000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- ICMP (for ping)
+ --
+ -- 0 7 8 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Type | Code | Checksum | 9
+ -- |----------------------------------------------------------------------|
+ -- | ID | Sequence | 10
+ -- |----------------------------------------------------------------------|
+ -- | |
+ -- | ICMP Payload (padding data) |
+ -- | |
+ -- |------------------------------------------------------------ // ------|
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_icmp_msg_type_len : natural := 1;
+ constant c_network_icmp_msg_type_w : natural := c_network_icmp_msg_type_len * c_8;
+ constant c_network_icmp_code_len : natural := 1;
+ constant c_network_icmp_code_w : natural := c_network_icmp_code_len * c_8;
+ constant c_network_icmp_checksum_len : natural := 2;
+ constant c_network_icmp_checksum_w : natural := c_network_icmp_checksum_len * c_8;
+ constant c_network_icmp_id_len : natural := 2;
+ constant c_network_icmp_id_w : natural := c_network_icmp_id_len * c_8;
+ constant c_network_icmp_sequence_len : natural := 2;
+ constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
+ constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
+ c_network_icmp_id_len + c_network_icmp_sequence_len;
+
+ -- default field values
+ constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
+ constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
+ constant c_network_icmp_checksum : natural := 0; -- init value
+
+ -- useful field values
+ constant c_network_icmp_code : natural := 0; -- default
+ constant c_network_icmp_id : natural := 3; -- arbitrary value
+ constant c_network_icmp_sequence : natural := 4; -- arbitrary value
+
+ type t_network_icmp_header is record
+ msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
+ code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
+ checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
+ id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
+ sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
+ end record;
+
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001", "00000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- UDP Packet
+ --
+ -- 0 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Source Port | Destination Port | 9
+ -- |----------------------------------------------------------------------|
+ -- | Total Length | Checksum | 10
+ -- |----------------------------------------------------------------------|
+ -- | |
+ -- | UDP Payload |
+ -- | |
+ -- |----------------------------------------------------------- // -------|
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_udp_port_len : natural := 2;
+ constant c_network_udp_port_w : natural := c_network_udp_port_len * c_8;
+ constant c_network_udp_total_length_len : natural := 2;
+ constant c_network_udp_total_length_w : natural := c_network_udp_total_length_len * c_8;
+ constant c_network_udp_checksum_len : natural := 2;
+ constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
+
+ -- [0:15] [16:31]
+ constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
+ c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+
+ -- default field values
+ constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
+ constant c_network_udp_checksum : natural := 0; -- init value
+
+ -- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
+
+ constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
+ constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
+ constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
+
+ type t_network_udp_header is record
+ src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
+ dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
+ total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
+ checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
+ end record;
+
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
end common_network_layers_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index 4bd7e15cc8..d6ca1b9008 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -30,9 +30,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
-- CONSTANT DECLARATIONS ----------------------------------------------------
@@ -332,7 +332,7 @@ package common_pkg is
function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
--- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
+ -- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
-- appropriate approach is to ignore the MSbit sign and just keep the LS part. For too large values this
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
@@ -353,7 +353,7 @@ package common_pkg is
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
+ -- Used in common_add_sub.vhd
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
@@ -429,20 +429,22 @@ package common_pkg is
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
function func_common_reorder2_is_there(I, J : natural) return boolean;
@@ -452,9 +454,10 @@ package common_pkg is
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
@@ -465,38 +468,38 @@ package body common_pkg is
end;
function ceil_pow2(n : integer) return natural is
- -- Also allows negative exponents and rounds up before returning the value
+ -- Also allows negative exponents and rounds up before returning the value
begin
return natural(integer(ceil(2**real(n))));
end;
function true_log2(n : natural) return natural is
- -- Purpose: For calculating extra vector width of existing vector
- -- Description: Return mathematical ceil(log2(n))
- -- n log2()
- -- 0 -> -oo --> FAILURE
- -- 1 -> 0
- -- 2 -> 1
- -- 3 -> 2
- -- 4 -> 2
- -- 5 -> 3
- -- 6 -> 3
- -- 7 -> 3
- -- 8 -> 3
- -- 9 -> 4
- -- etc, up to n = NATURAL'HIGH = 2**31-1
+ -- Purpose: For calculating extra vector width of existing vector
+ -- Description: Return mathematical ceil(log2(n))
+ -- n log2()
+ -- 0 -> -oo --> FAILURE
+ -- 1 -> 0
+ -- 2 -> 1
+ -- 3 -> 2
+ -- 4 -> 2
+ -- 5 -> 3
+ -- 6 -> 3
+ -- 7 -> 3
+ -- 8 -> 3
+ -- 9 -> 4
+ -- etc, up to n = NATURAL'HIGH = 2**31-1
begin
return natural(integer(ceil(log2(real(n)))));
end;
function ceil_log2(n : natural) return natural is
- -- Purpose: For calculating vector width of new vector
- -- Description:
- -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
- -- the vector width width for 1 address, to avoid NULL array for single
- -- word register address.
- -- If n = 0, return 0 so we get a NULL array when using
- -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
+ -- Purpose: For calculating vector width of new vector
+ -- Description:
+ -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
+ -- the vector width width for 1 address, to avoid NULL array for single
+ -- word register address.
+ -- If n = 0, return 0 so we get a NULL array when using
+ -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
return 0; -- Get NULL array
@@ -773,7 +776,7 @@ package body common_pkg is
function smallest(n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
@@ -1738,8 +1741,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
@@ -1748,8 +1751,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
@@ -2143,16 +2146,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2172,8 +2176,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -2276,8 +2281,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -2316,9 +2321,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index 7b6d1a2da0..696b4c8f66 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
------------------------------------------------------------------------------
@@ -120,15 +120,16 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(1, c_dp_stream_bsn_w),
+ to_unsigned(1, c_dp_stream_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ '1', '1', '1',
+ to_unsigned(1, c_dp_stream_empty_w),
+ to_unsigned(1, c_dp_stream_channel_w),
+ to_unsigned(1, c_dp_stream_error_w));
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -207,30 +208,34 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
-- . Use these functions to assign sosi data TO a record field
@@ -353,11 +358,11 @@ package dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
@@ -396,11 +401,12 @@ end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -415,20 +421,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -446,10 +454,11 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
@@ -1231,16 +1240,16 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
@@ -1264,7 +1273,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
@@ -1416,11 +1425,11 @@ package body dp_stream_pkg is
if data_order_im_re = true then
-- data = im&re
v_out_data := RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w) &
- RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
+ RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
else
-- data = re&im
v_out_data := RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w) &
- RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
+ RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
end if;
end if;
end if;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
index 1036675757..98bb5545f7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
@@ -44,12 +44,12 @@ package eth_pkg is
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
- -- yield simulation warning: Address pointed at port A is out of bound!
+ -- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
- -- when the module is used in an Nios II SOPC system
- -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
+ -- when the module is used in an Nios II SOPC system
+ -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
@@ -71,9 +71,10 @@ package eth_pkg is
is_dhcp : std_logic;
end record;
- constant c_eth_hdr_status_rst : t_eth_hdr_status := ('0', '0', '0', '0',
- (others => '0'), '0', '0',
- (others => '0'), '0');
+ constant c_eth_hdr_status_rst : t_eth_hdr_status := (
+ '0', '0', '0', '0',
+ (others => '0'), '0', '0',
+ (others => '0'), '0');
------------------------------------------------------------------------------
-- Definitions for eth demux udp
@@ -197,22 +198,22 @@ package eth_pkg is
-- Definitions for eth_mm_registers
------------------------------------------------------------------------------
- constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
- c_eth_reg_config_nof_words +
- c_eth_reg_control_nof_words +
- c_eth_reg_frame_nof_words +
- c_eth_reg_status_nof_words;
- constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
-
- ------------------------------------------------------------------------------
- -- Definitions for ETH Rx packet buffer and Tx packet buffer
- ------------------------------------------------------------------------------
-
- -- Use MM bus data width = c_word_w = 32
- constant c_eth_ram_rx_offset : natural := 0;
- constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
- constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
- constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
+ constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
+ c_eth_reg_config_nof_words +
+ c_eth_reg_control_nof_words +
+ c_eth_reg_frame_nof_words +
+ c_eth_reg_status_nof_words;
+ constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
+
+ ------------------------------------------------------------------------------
+ -- Definitions for ETH Rx packet buffer and Tx packet buffer
+ ------------------------------------------------------------------------------
+
+ -- Use MM bus data width = c_word_w = 32
+ constant c_eth_ram_rx_offset : natural := 0;
+ constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
+ constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
+ constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
end eth_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
index 177eb750c7..fd301389d3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package tech_tse_pkg is
constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
index d648f26fb1..97ced47767 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
@@ -26,10 +26,10 @@
-- . The avs2_eth_coe_hw.tcl determines the read latency per port
library IEEE, common_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use work.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use work.eth_pkg.all;
entity avs2_eth_coe is
port (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
index e879f1b9ed..7f2c37e56a 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
@@ -23,9 +23,9 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_network_layers_pkg is
-- All *_len constants are in nof octets = nof bytes = c_8 bits
@@ -85,9 +85,10 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001");
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -134,221 +135,225 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
- constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
- c_network_ip_identification_len + c_network_ip_flags_fragment_len +
- c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
- c_network_ip_addr_len +
- c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
- -- default field values
- constant c_network_ip_version : natural := 4; -- 4 = IPv4,
- constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
- constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
- constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
- constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
- constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
- constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
- constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
- constant c_network_ip_header_checksum : natural := 0; -- init value
-
- -- useful field values
- constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
- constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
- constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
-
- constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
-
- type t_network_ip_header is record
- version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
- header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
- services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
- total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
- identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
- flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
- fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
- time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
- protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
- header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
- src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- end record;
-
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
-
- ------------------------------------------------------------------------------
- -- ARP Packet
- --
- -- 0 7 8 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Hardware Type | Protocol Type | 4
- -- |----------------------------------------------------------------------|
- -- | HW Addr Len | Prot Addr Len | Operation | 5
- -- |----------------------------------------------------------------------|
- -- | Sender Hardware Address | 6
- -- | ------------------------------------|
- -- | | | 7
- -- |---------------------------------/ /----------------------------------|
- -- | Sender Protocol Address | | 8
- -- |----------------------------------- |
- -- | Target Hardware Address | 9
- -- |----------------------------------------------------------------------|
- -- | Target Protocol Address | 10
- -- |----------------------------------------------------------------------|
- --
- -- Note that ARP header = ARP packet, because ARP has no payload
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_arp_htype_len : natural := 2;
- constant c_network_arp_htype_w : natural := c_network_arp_htype_len * c_8;
- constant c_network_arp_ptype_len : natural := 2;
- constant c_network_arp_ptype_w : natural := c_network_arp_ptype_len * c_8;
- constant c_network_arp_hlen_len : natural := 1;
- constant c_network_arp_hlen_w : natural := c_network_arp_hlen_len * c_8;
- constant c_network_arp_plen_len : natural := 1;
- constant c_network_arp_plen_w : natural := c_network_arp_plen_len * c_8;
- constant c_network_arp_oper_len : natural := 2;
- constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
-
- -- [0:15] [16:31]
- constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
- c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-
- -- default field values
- constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
- constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
- constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
- constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
- constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
- constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
-
- -- useful field values
- constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
- constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
-
- type t_network_arp_packet is record
- htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
- ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
- hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
- plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
- oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
- sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
- spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
- tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
- tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
- end record;
-
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
-
- ------------------------------------------------------------------------------
- -- ICMP (for ping)
- --
- -- 0 7 8 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Type | Code | Checksum | 9
- -- |----------------------------------------------------------------------|
- -- | ID | Sequence | 10
- -- |----------------------------------------------------------------------|
- -- | |
- -- | ICMP Payload (padding data) |
- -- | |
- -- |------------------------------------------------------------ // ------|
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_icmp_msg_type_len : natural := 1;
- constant c_network_icmp_msg_type_w : natural := c_network_icmp_msg_type_len * c_8;
- constant c_network_icmp_code_len : natural := 1;
- constant c_network_icmp_code_w : natural := c_network_icmp_code_len * c_8;
- constant c_network_icmp_checksum_len : natural := 2;
- constant c_network_icmp_checksum_w : natural := c_network_icmp_checksum_len * c_8;
- constant c_network_icmp_id_len : natural := 2;
- constant c_network_icmp_id_w : natural := c_network_icmp_id_len * c_8;
- constant c_network_icmp_sequence_len : natural := 2;
- constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
- constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
- c_network_icmp_id_len + c_network_icmp_sequence_len;
-
- -- default field values
- constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
- constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
- constant c_network_icmp_checksum : natural := 0; -- init value
-
- -- useful field values
- constant c_network_icmp_code : natural := 0; -- default
- constant c_network_icmp_id : natural := 3; -- arbitrary value
- constant c_network_icmp_sequence : natural := 4; -- arbitrary value
-
- type t_network_icmp_header is record
- msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
- code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
- checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
- id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
- sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
- end record;
-
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
-
- ------------------------------------------------------------------------------
- -- UDP Packet
- --
- -- 0 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Source Port | Destination Port | 9
- -- |----------------------------------------------------------------------|
- -- | Total Length | Checksum | 10
- -- |----------------------------------------------------------------------|
- -- | |
- -- | UDP Payload |
- -- | |
- -- |----------------------------------------------------------- // -------|
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_udp_port_len : natural := 2;
- constant c_network_udp_port_w : natural := c_network_udp_port_len * c_8;
- constant c_network_udp_total_length_len : natural := 2;
- constant c_network_udp_total_length_w : natural := c_network_udp_total_length_len * c_8;
- constant c_network_udp_checksum_len : natural := 2;
- constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
-
- -- [0:15] [16:31]
- constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
-
- -- default field values
- constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
- constant c_network_udp_checksum : natural := 0; -- init value
-
- -- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
-
- constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
- constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
- constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
-
- type t_network_udp_header is record
- src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
- checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
- end record;
-
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ -- [0:7] [8:15] [16:31]
+ constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
+ c_network_ip_identification_len + c_network_ip_flags_fragment_len +
+ c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
+ c_network_ip_addr_len +
+ c_network_ip_addr_len;
+ -- = c_network_ip_header_length * c_word_sz = 20
+ -- default field values
+ constant c_network_ip_version : natural := 4; -- 4 = IPv4,
+ constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
+ constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
+ constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
+ constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
+ constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
+ constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
+ constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
+ constant c_network_ip_header_checksum : natural := 0; -- init value
+
+ -- useful field values
+ constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
+ constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
+ constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
+
+ constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
+
+ type t_network_ip_header is record
+ version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
+ header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
+ services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
+ total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
+ identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
+ flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
+ fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
+ time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
+ protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
+ header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
+ src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ end record;
+
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001", "0001", "00000001", "0000000000000001",
+ "0000000000000001", "001", "0000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- ARP Packet
+ --
+ -- 0 7 8 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Hardware Type | Protocol Type | 4
+ -- |----------------------------------------------------------------------|
+ -- | HW Addr Len | Prot Addr Len | Operation | 5
+ -- |----------------------------------------------------------------------|
+ -- | Sender Hardware Address | 6
+ -- | ------------------------------------|
+ -- | | | 7
+ -- |---------------------------------/ /----------------------------------|
+ -- | Sender Protocol Address | | 8
+ -- |----------------------------------- |
+ -- | Target Hardware Address | 9
+ -- |----------------------------------------------------------------------|
+ -- | Target Protocol Address | 10
+ -- |----------------------------------------------------------------------|
+ --
+ -- Note that ARP header = ARP packet, because ARP has no payload
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_arp_htype_len : natural := 2;
+ constant c_network_arp_htype_w : natural := c_network_arp_htype_len * c_8;
+ constant c_network_arp_ptype_len : natural := 2;
+ constant c_network_arp_ptype_w : natural := c_network_arp_ptype_len * c_8;
+ constant c_network_arp_hlen_len : natural := 1;
+ constant c_network_arp_hlen_w : natural := c_network_arp_hlen_len * c_8;
+ constant c_network_arp_plen_len : natural := 1;
+ constant c_network_arp_plen_w : natural := c_network_arp_plen_len * c_8;
+ constant c_network_arp_oper_len : natural := 2;
+ constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
+
+ -- [0:15] [16:31]
+ constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
+ c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len;
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+
+ -- default field values
+ constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
+ constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
+ constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
+ constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
+ constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
+ constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
+
+ -- useful field values
+ constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
+ constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
+
+ type t_network_arp_packet is record
+ htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
+ ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
+ hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
+ plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
+ oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
+ sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
+ spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
+ tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
+ tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
+ end record;
+
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001", "0000000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- ICMP (for ping)
+ --
+ -- 0 7 8 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Type | Code | Checksum | 9
+ -- |----------------------------------------------------------------------|
+ -- | ID | Sequence | 10
+ -- |----------------------------------------------------------------------|
+ -- | |
+ -- | ICMP Payload (padding data) |
+ -- | |
+ -- |------------------------------------------------------------ // ------|
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_icmp_msg_type_len : natural := 1;
+ constant c_network_icmp_msg_type_w : natural := c_network_icmp_msg_type_len * c_8;
+ constant c_network_icmp_code_len : natural := 1;
+ constant c_network_icmp_code_w : natural := c_network_icmp_code_len * c_8;
+ constant c_network_icmp_checksum_len : natural := 2;
+ constant c_network_icmp_checksum_w : natural := c_network_icmp_checksum_len * c_8;
+ constant c_network_icmp_id_len : natural := 2;
+ constant c_network_icmp_id_w : natural := c_network_icmp_id_len * c_8;
+ constant c_network_icmp_sequence_len : natural := 2;
+ constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
+ constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
+ c_network_icmp_id_len + c_network_icmp_sequence_len;
+
+ -- default field values
+ constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
+ constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
+ constant c_network_icmp_checksum : natural := 0; -- init value
+
+ -- useful field values
+ constant c_network_icmp_code : natural := 0; -- default
+ constant c_network_icmp_id : natural := 3; -- arbitrary value
+ constant c_network_icmp_sequence : natural := 4; -- arbitrary value
+
+ type t_network_icmp_header is record
+ msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
+ code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
+ checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
+ id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
+ sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
+ end record;
+
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001", "00000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- UDP Packet
+ --
+ -- 0 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Source Port | Destination Port | 9
+ -- |----------------------------------------------------------------------|
+ -- | Total Length | Checksum | 10
+ -- |----------------------------------------------------------------------|
+ -- | |
+ -- | UDP Payload |
+ -- | |
+ -- |----------------------------------------------------------- // -------|
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_udp_port_len : natural := 2;
+ constant c_network_udp_port_w : natural := c_network_udp_port_len * c_8;
+ constant c_network_udp_total_length_len : natural := 2;
+ constant c_network_udp_total_length_w : natural := c_network_udp_total_length_len * c_8;
+ constant c_network_udp_checksum_len : natural := 2;
+ constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
+
+ -- [0:15] [16:31]
+ constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
+ c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+
+ -- default field values
+ constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
+ constant c_network_udp_checksum : natural := 0; -- init value
+
+ -- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
+
+ constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
+ constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
+ constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
+
+ type t_network_udp_header is record
+ src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
+ dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
+ total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
+ checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
+ end record;
+
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
end common_network_layers_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index 4bd7e15cc8..d6ca1b9008 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -30,9 +30,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
-- CONSTANT DECLARATIONS ----------------------------------------------------
@@ -332,7 +332,7 @@ package common_pkg is
function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
--- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
+ -- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
-- appropriate approach is to ignore the MSbit sign and just keep the LS part. For too large values this
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
@@ -353,7 +353,7 @@ package common_pkg is
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
+ -- Used in common_add_sub.vhd
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
@@ -429,20 +429,22 @@ package common_pkg is
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
function func_common_reorder2_is_there(I, J : natural) return boolean;
@@ -452,9 +454,10 @@ package common_pkg is
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
@@ -465,38 +468,38 @@ package body common_pkg is
end;
function ceil_pow2(n : integer) return natural is
- -- Also allows negative exponents and rounds up before returning the value
+ -- Also allows negative exponents and rounds up before returning the value
begin
return natural(integer(ceil(2**real(n))));
end;
function true_log2(n : natural) return natural is
- -- Purpose: For calculating extra vector width of existing vector
- -- Description: Return mathematical ceil(log2(n))
- -- n log2()
- -- 0 -> -oo --> FAILURE
- -- 1 -> 0
- -- 2 -> 1
- -- 3 -> 2
- -- 4 -> 2
- -- 5 -> 3
- -- 6 -> 3
- -- 7 -> 3
- -- 8 -> 3
- -- 9 -> 4
- -- etc, up to n = NATURAL'HIGH = 2**31-1
+ -- Purpose: For calculating extra vector width of existing vector
+ -- Description: Return mathematical ceil(log2(n))
+ -- n log2()
+ -- 0 -> -oo --> FAILURE
+ -- 1 -> 0
+ -- 2 -> 1
+ -- 3 -> 2
+ -- 4 -> 2
+ -- 5 -> 3
+ -- 6 -> 3
+ -- 7 -> 3
+ -- 8 -> 3
+ -- 9 -> 4
+ -- etc, up to n = NATURAL'HIGH = 2**31-1
begin
return natural(integer(ceil(log2(real(n)))));
end;
function ceil_log2(n : natural) return natural is
- -- Purpose: For calculating vector width of new vector
- -- Description:
- -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
- -- the vector width width for 1 address, to avoid NULL array for single
- -- word register address.
- -- If n = 0, return 0 so we get a NULL array when using
- -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
+ -- Purpose: For calculating vector width of new vector
+ -- Description:
+ -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
+ -- the vector width width for 1 address, to avoid NULL array for single
+ -- word register address.
+ -- If n = 0, return 0 so we get a NULL array when using
+ -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
return 0; -- Get NULL array
@@ -773,7 +776,7 @@ package body common_pkg is
function smallest(n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
@@ -1738,8 +1741,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
@@ -1748,8 +1751,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
@@ -2143,16 +2146,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2172,8 +2176,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -2276,8 +2281,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -2316,9 +2321,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index 7b6d1a2da0..696b4c8f66 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
------------------------------------------------------------------------------
@@ -120,15 +120,16 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(1, c_dp_stream_bsn_w),
+ to_unsigned(1, c_dp_stream_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ '1', '1', '1',
+ to_unsigned(1, c_dp_stream_empty_w),
+ to_unsigned(1, c_dp_stream_channel_w),
+ to_unsigned(1, c_dp_stream_error_w));
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -207,30 +208,34 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
-- . Use these functions to assign sosi data TO a record field
@@ -353,11 +358,11 @@ package dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
@@ -396,11 +401,12 @@ end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -415,20 +421,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -446,10 +454,11 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
@@ -1231,16 +1240,16 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
@@ -1264,7 +1273,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
@@ -1416,11 +1425,11 @@ package body dp_stream_pkg is
if data_order_im_re = true then
-- data = im&re
v_out_data := RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w) &
- RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
+ RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
else
-- data = re&im
v_out_data := RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w) &
- RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
+ RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
end if;
end if;
end if;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
index 1036675757..98bb5545f7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
@@ -44,12 +44,12 @@ package eth_pkg is
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
- -- yield simulation warning: Address pointed at port A is out of bound!
+ -- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
- -- when the module is used in an Nios II SOPC system
- -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
+ -- when the module is used in an Nios II SOPC system
+ -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
@@ -71,9 +71,10 @@ package eth_pkg is
is_dhcp : std_logic;
end record;
- constant c_eth_hdr_status_rst : t_eth_hdr_status := ('0', '0', '0', '0',
- (others => '0'), '0', '0',
- (others => '0'), '0');
+ constant c_eth_hdr_status_rst : t_eth_hdr_status := (
+ '0', '0', '0', '0',
+ (others => '0'), '0', '0',
+ (others => '0'), '0');
------------------------------------------------------------------------------
-- Definitions for eth demux udp
@@ -197,22 +198,22 @@ package eth_pkg is
-- Definitions for eth_mm_registers
------------------------------------------------------------------------------
- constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
- c_eth_reg_config_nof_words +
- c_eth_reg_control_nof_words +
- c_eth_reg_frame_nof_words +
- c_eth_reg_status_nof_words;
- constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
-
- ------------------------------------------------------------------------------
- -- Definitions for ETH Rx packet buffer and Tx packet buffer
- ------------------------------------------------------------------------------
-
- -- Use MM bus data width = c_word_w = 32
- constant c_eth_ram_rx_offset : natural := 0;
- constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
- constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
- constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
+ constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
+ c_eth_reg_config_nof_words +
+ c_eth_reg_control_nof_words +
+ c_eth_reg_frame_nof_words +
+ c_eth_reg_status_nof_words;
+ constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
+
+ ------------------------------------------------------------------------------
+ -- Definitions for ETH Rx packet buffer and Tx packet buffer
+ ------------------------------------------------------------------------------
+
+ -- Use MM bus data width = c_word_w = 32
+ constant c_eth_ram_rx_offset : natural := 0;
+ constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
+ constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
+ constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
end eth_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
index 177eb750c7..fd301389d3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package tech_tse_pkg is
constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
index 06df7d37f4..1db149d4b3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
@@ -1,84 +1,84 @@
- component qsys_unb2b_minimal_avs_eth_0 is
- port (
- coe_clk_export : out std_logic; -- export
- ins_interrupt_irq : out std_logic; -- irq
- coe_irq_export : in std_logic := 'X'; -- export
- csi_mm_clk : in std_logic := 'X'; -- clk
- csi_mm_reset : in std_logic := 'X'; -- reset
- mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_ram_write : in std_logic := 'X'; -- write
- mms_ram_read : in std_logic := 'X'; -- read
- mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_ram_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
- mms_reg_write : in std_logic := 'X'; -- write
- mms_reg_read : in std_logic := 'X'; -- read
- mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_reg_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_tse_write : in std_logic := 'X'; -- write
- mms_tse_read : in std_logic := 'X'; -- read
- mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_tse_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_waitrequest : out std_logic; -- waitrequest
- coe_ram_address_export : out std_logic_vector(9 downto 0); -- export
- coe_ram_read_export : out std_logic; -- export
- coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_write_export : out std_logic; -- export
- coe_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reg_address_export : out std_logic_vector(3 downto 0); -- export
- coe_reg_read_export : out std_logic; -- export
- coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reg_write_export : out std_logic; -- export
- coe_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reset_export : out std_logic; -- export
- coe_tse_address_export : out std_logic_vector(9 downto 0); -- export
- coe_tse_read_export : out std_logic; -- export
- coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_tse_waitrequest_export : in std_logic := 'X'; -- export
- coe_tse_write_export : out std_logic; -- export
- coe_tse_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_eth_0;
+component qsys_unb2b_minimal_avs_eth_0 is
+ port (
+ coe_clk_export : out std_logic; -- export
+ ins_interrupt_irq : out std_logic; -- irq
+ coe_irq_export : in std_logic := 'X'; -- export
+ csi_mm_clk : in std_logic := 'X'; -- clk
+ csi_mm_reset : in std_logic := 'X'; -- reset
+ mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mms_ram_write : in std_logic := 'X'; -- write
+ mms_ram_read : in std_logic := 'X'; -- read
+ mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_ram_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
+ mms_reg_write : in std_logic := 'X'; -- write
+ mms_reg_read : in std_logic := 'X'; -- read
+ mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_reg_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mms_tse_write : in std_logic := 'X'; -- write
+ mms_tse_read : in std_logic := 'X'; -- read
+ mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_tse_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_tse_waitrequest : out std_logic; -- waitrequest
+ coe_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ coe_ram_read_export : out std_logic; -- export
+ coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_write_export : out std_logic; -- export
+ coe_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ coe_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ coe_reg_read_export : out std_logic; -- export
+ coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reg_write_export : out std_logic; -- export
+ coe_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export : out std_logic; -- export
+ coe_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ coe_tse_read_export : out std_logic; -- export
+ coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_tse_waitrequest_export : in std_logic := 'X'; -- export
+ coe_tse_write_export : out std_logic; -- export
+ coe_tse_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_avs_eth_0;
- u0 : component qsys_unb2b_minimal_avs_eth_0
- port map (
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq, -- interrupt.irq
- coe_irq_export => CONNECTED_TO_coe_irq_export, -- irq.export
- csi_mm_clk => CONNECTED_TO_csi_mm_clk, -- mm.clk
- csi_mm_reset => CONNECTED_TO_csi_mm_reset, -- mm_reset.reset
- mms_ram_address => CONNECTED_TO_mms_ram_address, -- mms_ram.address
- mms_ram_write => CONNECTED_TO_mms_ram_write, -- .write
- mms_ram_read => CONNECTED_TO_mms_ram_read, -- .read
- mms_ram_writedata => CONNECTED_TO_mms_ram_writedata, -- .writedata
- mms_ram_readdata => CONNECTED_TO_mms_ram_readdata, -- .readdata
- mms_reg_address => CONNECTED_TO_mms_reg_address, -- mms_reg.address
- mms_reg_write => CONNECTED_TO_mms_reg_write, -- .write
- mms_reg_read => CONNECTED_TO_mms_reg_read, -- .read
- mms_reg_writedata => CONNECTED_TO_mms_reg_writedata, -- .writedata
- mms_reg_readdata => CONNECTED_TO_mms_reg_readdata, -- .readdata
- mms_tse_address => CONNECTED_TO_mms_tse_address, -- mms_tse.address
- mms_tse_write => CONNECTED_TO_mms_tse_write, -- .write
- mms_tse_read => CONNECTED_TO_mms_tse_read, -- .read
- mms_tse_writedata => CONNECTED_TO_mms_tse_writedata, -- .writedata
- mms_tse_readdata => CONNECTED_TO_mms_tse_readdata, -- .readdata
- mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest, -- .waitrequest
- coe_ram_address_export => CONNECTED_TO_coe_ram_address_export, -- ram_address.export
- coe_ram_read_export => CONNECTED_TO_coe_ram_read_export, -- ram_read.export
- coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export, -- ram_readdata.export
- coe_ram_write_export => CONNECTED_TO_coe_ram_write_export, -- ram_write.export
- coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export, -- ram_writedata.export
- coe_reg_address_export => CONNECTED_TO_coe_reg_address_export, -- reg_address.export
- coe_reg_read_export => CONNECTED_TO_coe_reg_read_export, -- reg_read.export
- coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export, -- reg_readdata.export
- coe_reg_write_export => CONNECTED_TO_coe_reg_write_export, -- reg_write.export
- coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export, -- reg_writedata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- coe_tse_address_export => CONNECTED_TO_coe_tse_address_export, -- tse_address.export
- coe_tse_read_export => CONNECTED_TO_coe_tse_read_export, -- tse_read.export
- coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export, -- tse_readdata.export
- coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
- coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
- coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
- );
+u0 : component qsys_unb2b_minimal_avs_eth_0
+ port map (
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq, -- interrupt.irq
+ coe_irq_export => CONNECTED_TO_coe_irq_export, -- irq.export
+ csi_mm_clk => CONNECTED_TO_csi_mm_clk, -- mm.clk
+ csi_mm_reset => CONNECTED_TO_csi_mm_reset, -- mm_reset.reset
+ mms_ram_address => CONNECTED_TO_mms_ram_address, -- mms_ram.address
+ mms_ram_write => CONNECTED_TO_mms_ram_write, -- .write
+ mms_ram_read => CONNECTED_TO_mms_ram_read, -- .read
+ mms_ram_writedata => CONNECTED_TO_mms_ram_writedata, -- .writedata
+ mms_ram_readdata => CONNECTED_TO_mms_ram_readdata, -- .readdata
+ mms_reg_address => CONNECTED_TO_mms_reg_address, -- mms_reg.address
+ mms_reg_write => CONNECTED_TO_mms_reg_write, -- .write
+ mms_reg_read => CONNECTED_TO_mms_reg_read, -- .read
+ mms_reg_writedata => CONNECTED_TO_mms_reg_writedata, -- .writedata
+ mms_reg_readdata => CONNECTED_TO_mms_reg_readdata, -- .readdata
+ mms_tse_address => CONNECTED_TO_mms_tse_address, -- mms_tse.address
+ mms_tse_write => CONNECTED_TO_mms_tse_write, -- .write
+ mms_tse_read => CONNECTED_TO_mms_tse_read, -- .read
+ mms_tse_writedata => CONNECTED_TO_mms_tse_writedata, -- .writedata
+ mms_tse_readdata => CONNECTED_TO_mms_tse_readdata, -- .readdata
+ mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest, -- .waitrequest
+ coe_ram_address_export => CONNECTED_TO_coe_ram_address_export, -- ram_address.export
+ coe_ram_read_export => CONNECTED_TO_coe_ram_read_export, -- ram_read.export
+ coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export, -- ram_readdata.export
+ coe_ram_write_export => CONNECTED_TO_coe_ram_write_export, -- ram_write.export
+ coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export, -- ram_writedata.export
+ coe_reg_address_export => CONNECTED_TO_coe_reg_address_export, -- reg_address.export
+ coe_reg_read_export => CONNECTED_TO_coe_reg_read_export, -- reg_read.export
+ coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export, -- reg_readdata.export
+ coe_reg_write_export => CONNECTED_TO_coe_reg_write_export, -- reg_write.export
+ coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export, -- reg_writedata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ coe_tse_address_export => CONNECTED_TO_coe_tse_address_export, -- tse_address.export
+ coe_tse_read_export => CONNECTED_TO_coe_tse_read_export, -- tse_read.export
+ coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export, -- tse_readdata.export
+ coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
+ coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
+ coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
index fafd41bbfa..f5b3868395 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
@@ -1,16 +1,16 @@
- component qsys_unb2b_minimal_clk_0 is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component qsys_unb2b_minimal_clk_0;
+component qsys_unb2b_minimal_clk_0 is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component qsys_unb2b_minimal_clk_0;
- u0 : component qsys_unb2b_minimal_clk_0
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component qsys_unb2b_minimal_clk_0
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
index 38fce9676f..530ffe2274 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
@@ -1,60 +1,60 @@
- component qsys_unb2b_minimal_cpu_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- dummy_ci_port : out std_logic; -- readra
- d_address : out std_logic_vector(19 downto 0); -- address
- d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
- d_read : out std_logic; -- read
- d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- d_waitrequest : in std_logic := 'X'; -- waitrequest
- d_write : out std_logic; -- write
- d_writedata : out std_logic_vector(31 downto 0); -- writedata
- debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
- debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
- debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
- debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
- debug_mem_slave_read : in std_logic := 'X'; -- read
- debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
- debug_mem_slave_waitrequest : out std_logic; -- waitrequest
- debug_mem_slave_write : in std_logic := 'X'; -- write
- debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- debug_reset_request : out std_logic; -- reset
- i_address : out std_logic_vector(17 downto 0); -- address
- i_read : out std_logic; -- read
- i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- i_waitrequest : in std_logic := 'X'; -- waitrequest
- irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- reset_req : in std_logic := 'X' -- reset_req
- );
- end component qsys_unb2b_minimal_cpu_0;
+component qsys_unb2b_minimal_cpu_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ dummy_ci_port : out std_logic; -- readra
+ d_address : out std_logic_vector(19 downto 0); -- address
+ d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ d_read : out std_logic; -- read
+ d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ d_waitrequest : in std_logic := 'X'; -- waitrequest
+ d_write : out std_logic; -- write
+ d_writedata : out std_logic_vector(31 downto 0); -- writedata
+ debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
+ debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
+ debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
+ debug_mem_slave_read : in std_logic := 'X'; -- read
+ debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
+ debug_mem_slave_waitrequest : out std_logic; -- waitrequest
+ debug_mem_slave_write : in std_logic := 'X'; -- write
+ debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ debug_reset_request : out std_logic; -- reset
+ i_address : out std_logic_vector(17 downto 0); -- address
+ i_read : out std_logic; -- read
+ i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ i_waitrequest : in std_logic := 'X'; -- waitrequest
+ irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_req : in std_logic := 'X' -- reset_req
+ );
+end component qsys_unb2b_minimal_cpu_0;
- u0 : component qsys_unb2b_minimal_cpu_0
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
- d_address => CONNECTED_TO_d_address, -- data_master.address
- d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
- d_read => CONNECTED_TO_d_read, -- .read
- d_readdata => CONNECTED_TO_d_readdata, -- .readdata
- d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
- d_write => CONNECTED_TO_d_write, -- .write
- d_writedata => CONNECTED_TO_d_writedata, -- .writedata
- debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
- debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
- debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
- debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
- debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
- debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
- debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
- debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
- debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
- debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
- i_address => CONNECTED_TO_i_address, -- instruction_master.address
- i_read => CONNECTED_TO_i_read, -- .read
- i_readdata => CONNECTED_TO_i_readdata, -- .readdata
- i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- reset_req => CONNECTED_TO_reset_req -- .reset_req
- );
+u0 : component qsys_unb2b_minimal_cpu_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
+ d_address => CONNECTED_TO_d_address, -- data_master.address
+ d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
+ d_read => CONNECTED_TO_d_read, -- .read
+ d_readdata => CONNECTED_TO_d_readdata, -- .readdata
+ d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
+ d_write => CONNECTED_TO_d_write, -- .write
+ d_writedata => CONNECTED_TO_d_writedata, -- .writedata
+ debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
+ debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
+ debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
+ debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
+ debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
+ debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
+ debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
+ debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
+ debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
+ debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
+ i_address => CONNECTED_TO_i_address, -- instruction_master.address
+ i_read => CONNECTED_TO_i_read, -- .read
+ i_readdata => CONNECTED_TO_i_readdata, -- .readdata
+ i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
+ irq => CONNECTED_TO_irq, -- irq.irq
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ reset_req => CONNECTED_TO_reset_req -- .reset_req
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
index c76f427acb..e1d0e8ddbe 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
@@ -1,100 +1,100 @@
- component qsys_unb2b_minimal_jesd204 is
- port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
- );
- end component qsys_unb2b_minimal_jesd204;
+component qsys_unb2b_minimal_jesd204 is
+ port (
+ alldev_lane_aligned : in std_logic := 'X'; -- export
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ dev_lane_aligned : out std_logic; -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_rx_avs_read : in std_logic := 'X'; -- read
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_rx_avs_write : in std_logic := 'X'; -- write
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_frame_error : in std_logic := 'X'; -- export
+ jesd204_rx_int : out std_logic; -- irq
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ jesd204_rx_link_valid : out std_logic; -- valid
+ jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ rxlink_clk : in std_logic := 'X'; -- clk
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxphy_clk : out std_logic_vector(0 downto 0); -- export
+ sof : out std_logic_vector(3 downto 0); -- export
+ somf : out std_logic_vector(3 downto 0); -- export
+ sysref : in std_logic := 'X' -- export
+ );
+end component qsys_unb2b_minimal_jesd204;
- u0 : component qsys_unb2b_minimal_jesd204
- port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
- );
+u0 : component qsys_unb2b_minimal_jesd204
+ port map (
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
+ csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
+ csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
+ csr_f => CONNECTED_TO_csr_f, -- csr_f.export
+ csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
+ csr_k => CONNECTED_TO_csr_k, -- csr_k.export
+ csr_l => CONNECTED_TO_csr_l, -- csr_l.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
+ csr_m => CONNECTED_TO_csr_m, -- csr_m.export
+ csr_n => CONNECTED_TO_csr_n, -- csr_n.export
+ csr_np => CONNECTED_TO_csr_np, -- csr_np.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
+ csr_s => CONNECTED_TO_csr_s, -- csr_s.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
+ rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
+ rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
+ rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
+ sof => CONNECTED_TO_sof, -- sof.export
+ somf => CONNECTED_TO_somf, -- somf.export
+ sysref => CONNECTED_TO_sysref -- sysref.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
index f745d32d0b..0d4b6170c8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
@@ -15,55 +15,56 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library std;
-use std.textio.all;
+ use std.textio.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
begin
---synthesis translate_off
- process (clk)
+ --synthesis translate_off
+ process (clk)
variable write_line : line;
- begin
- if clk'event and clk = '1' then
- if std_logic'(fifo_wr) = '1' then
- write(write_line, character'val(CONV_INTEGER(fifo_wdata)));
- write(write_line, string'(""));
- write(output, write_line.all);
- deallocate (write_line);
- end if;
+ begin
+ if clk'event and clk = '1' then
+ if std_logic'(fifo_wr) = '1' then
+ write(write_line, character'val(CONV_INTEGER(fifo_wdata)));
+ write(write_line, string'(""));
+ write(output, write_line.all);
+ deallocate (write_line);
end if;
- end process;
+ end if;
+ end process;
- wfifo_used <= A_REP(std_logic'('0'), 6);
- r_dat <= A_REP(std_logic'('0'), 8);
- fifo_FF <= std_logic'('0');
- wfifo_empty <= std_logic'('1');
---synthesis translate_on
+ wfifo_used <= A_REP(std_logic'('0'), 6);
+ r_dat <= A_REP(std_logic'('0'), 8);
+ fifo_FF <= std_logic'('0');
+ wfifo_empty <= std_logic'('1');
+ --synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
@@ -71,96 +72,98 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
- signal rd_wfifo : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+ signal rd_wfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
---synthesis translate_off
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- component scfifo is
---GENERIC (
--- lpm_hint : STRING;
--- lpm_numwords : NATURAL;
--- lpm_showahead : STRING;
--- lpm_type : STRING;
--- lpm_width : NATURAL;
--- lpm_widthu : NATURAL;
--- overflow_checking : STRING;
--- underflow_checking : STRING;
--- use_eab : STRING
--- );
--- PORT (
--- signal full : OUT STD_LOGIC;
--- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
--- signal empty : OUT STD_LOGIC;
--- signal rdreq : IN STD_LOGIC;
--- signal aclr : IN STD_LOGIC;
--- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal clock : IN STD_LOGIC;
--- signal wrreq : IN STD_LOGIC
--- );
--- end component scfifo;
---synthesis read_comments_as_HDL off
- signal internal_fifo_FF : std_logic;
- signal internal_r_dat : std_logic_vector(7 downto 0);
- signal internal_wfifo_empty : std_logic;
- signal internal_wfifo_used : std_logic_vector(5 downto 0);
-begin
- --vhdl renameroo for output signals
- fifo_FF <= internal_fifo_FF;
- --vhdl renameroo for output signals
- r_dat <= internal_r_dat;
- --vhdl renameroo for output signals
- wfifo_empty <= internal_wfifo_empty;
- --vhdl renameroo for output signals
- wfifo_used <= internal_wfifo_used;
---synthesis translate_off
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w
+ --synthesis translate_off
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- component scfifo is
+ --GENERIC (
+ -- lpm_hint : STRING;
+ -- lpm_numwords : NATURAL;
+ -- lpm_showahead : STRING;
+ -- lpm_type : STRING;
+ -- lpm_width : NATURAL;
+ -- lpm_widthu : NATURAL;
+ -- overflow_checking : STRING;
+ -- underflow_checking : STRING;
+ -- use_eab : STRING
+ -- );
+ -- PORT (
+ -- signal full : OUT STD_LOGIC;
+ -- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+ -- signal empty : OUT STD_LOGIC;
+ -- signal rdreq : IN STD_LOGIC;
+ -- signal aclr : IN STD_LOGIC;
+ -- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal clock : IN STD_LOGIC;
+ -- signal wrreq : IN STD_LOGIC
+ -- );
+ -- end component scfifo;
+ --synthesis read_comments_as_HDL off
+ signal internal_fifo_FF : std_logic;
+ signal internal_r_dat : std_logic_vector(7 downto 0);
+ signal internal_wfifo_empty : std_logic;
+ signal internal_wfifo_used : std_logic_vector(5 downto 0);
+ begin
+ --vhdl renameroo for output signals
+ fifo_FF <= internal_fifo_FF;
+ --vhdl renameroo for output signals
+ r_dat <= internal_r_dat;
+ --vhdl renameroo for output signals
+ wfifo_empty <= internal_wfifo_empty;
+ --vhdl renameroo for output signals
+ wfifo_used <= internal_wfifo_used;
+ --synthesis translate_off
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w
port map(
fifo_FF => internal_fifo_FF,
r_dat => internal_r_dat,
@@ -171,103 +174,104 @@ begin
fifo_wr => fifo_wr
);
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- wfifo : scfifo
--- generic map(
--- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
--- lpm_numwords => 64,
--- lpm_showahead => "OFF",
--- lpm_type => "scfifo",
--- lpm_width => 8,
--- lpm_widthu => 6,
--- overflow_checking => "OFF",
--- underflow_checking => "OFF",
--- use_eab => "ON"
--- )
--- port map(
--- aclr => fifo_clear,
--- clock => clk,
--- data => fifo_wdata,
--- empty => internal_wfifo_empty,
--- full => internal_fifo_FF,
--- q => internal_r_dat,
--- rdreq => rd_wfifo,
--- usedw => internal_wfifo_used,
--- wrreq => fifo_wr
--- );
---
---synthesis read_comments_as_HDL off
-end europa;
-
--- turn off superfluous VHDL processor warnings
--- altera message_level Level1
--- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- wfifo : scfifo
+ -- generic map(
+ -- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
+ -- lpm_numwords => 64,
+ -- lpm_showahead => "OFF",
+ -- lpm_type => "scfifo",
+ -- lpm_width => 8,
+ -- lpm_widthu => 6,
+ -- overflow_checking => "OFF",
+ -- underflow_checking => "OFF",
+ -- use_eab => "ON"
+ -- )
+ -- port map(
+ -- aclr => fifo_clear,
+ -- clock => clk,
+ -- data => fifo_wdata,
+ -- empty => internal_wfifo_empty,
+ -- full => internal_fifo_FF,
+ -- q => internal_r_dat,
+ -- rdreq => rd_wfifo,
+ -- usedw => internal_wfifo_used,
+ -- wrreq => fifo_wr
+ -- );
+ --
+ --synthesis read_comments_as_HDL off
+ end europa;
+
+ -- turn off superfluous VHDL processor warnings
+ -- altera message_level Level1
+ -- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- signal bytes_left : std_logic_vector(31 downto 0);
- signal fifo_rd_d : std_logic;
- signal internal_rfifo_full1 : std_logic;
- signal new_rom : std_logic;
- signal num_bytes : std_logic_vector(31 downto 0);
- signal rfifo_entries : std_logic_vector(6 downto 0);
+ signal bytes_left : std_logic_vector(31 downto 0);
+ signal fifo_rd_d : std_logic;
+ signal internal_rfifo_full1 : std_logic;
+ signal new_rom : std_logic;
+ signal num_bytes : std_logic_vector(31 downto 0);
+ signal rfifo_entries : std_logic_vector(6 downto 0);
begin
--vhdl renameroo for output signals
rfifo_full <= internal_rfifo_full1;
---synthesis translate_off
- -- Generate rfifo_entries for simulation
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- bytes_left <= std_logic_vector'("00000000000000000000000000000000");
- fifo_rd_d <= std_logic'('0');
- elsif clk'event and clk = '1' then
- fifo_rd_d <= fifo_rd;
- -- decrement on read
- if std_logic'(fifo_rd_d) = '1' then
- bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32);
- end if;
- -- catch new contents
- if std_logic'(new_rom) = '1' then
- bytes_left <= num_bytes;
- end if;
+ --synthesis translate_off
+ -- Generate rfifo_entries for simulation
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ bytes_left <= std_logic_vector'("00000000000000000000000000000000");
+ fifo_rd_d <= std_logic'('0');
+ elsif clk'event and clk = '1' then
+ fifo_rd_d <= fifo_rd;
+ -- decrement on read
+ if std_logic'(fifo_rd_d) = '1' then
+ bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32);
end if;
- end process;
-
- fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
- internal_rfifo_full1 <= to_std_logic((bytes_left > std_logic_vector'("00000000000000000000000001000000")));
- rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7);
- rfifo_used <= rfifo_entries(5 downto 0);
- new_rom <= std_logic'('0');
- num_bytes <= std_logic_vector'("00000000000000000000000000000000");
- fifo_rdata <= std_logic_vector'("00000000");
---synthesis translate_on
+ -- catch new contents
+ if std_logic'(new_rom) = '1' then
+ bytes_left <= num_bytes;
+ end if;
+ end if;
+ end process;
+
+ fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
+ internal_rfifo_full1 <= to_std_logic((bytes_left > std_logic_vector'("00000000000000000000000001000000")));
+ rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7);
+ rfifo_used <= rfifo_entries(5 downto 0);
+ new_rom <= std_logic'('0');
+ num_bytes <= std_logic_vector'("00000000000000000000000000000000");
+ fifo_rdata <= std_logic_vector'("00000000");
+ --synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
@@ -275,97 +279,99 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
- signal t_dat : in std_logic_vector(7 downto 0);
- signal wr_rfifo : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+ signal t_dat : in std_logic_vector(7 downto 0);
+ signal wr_rfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
---synthesis translate_off
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- component scfifo is
---GENERIC (
--- lpm_hint : STRING;
--- lpm_numwords : NATURAL;
--- lpm_showahead : STRING;
--- lpm_type : STRING;
--- lpm_width : NATURAL;
--- lpm_widthu : NATURAL;
--- overflow_checking : STRING;
--- underflow_checking : STRING;
--- use_eab : STRING
--- );
--- PORT (
--- signal full : OUT STD_LOGIC;
--- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
--- signal empty : OUT STD_LOGIC;
--- signal rdreq : IN STD_LOGIC;
--- signal aclr : IN STD_LOGIC;
--- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal clock : IN STD_LOGIC;
--- signal wrreq : IN STD_LOGIC
--- );
--- end component scfifo;
---synthesis read_comments_as_HDL off
- signal internal_fifo_EF : std_logic;
- signal internal_fifo_rdata : std_logic_vector(7 downto 0);
- signal internal_rfifo_full : std_logic;
- signal internal_rfifo_used : std_logic_vector(5 downto 0);
-begin
- --vhdl renameroo for output signals
- fifo_EF <= internal_fifo_EF;
- --vhdl renameroo for output signals
- fifo_rdata <= internal_fifo_rdata;
- --vhdl renameroo for output signals
- rfifo_full <= internal_rfifo_full;
- --vhdl renameroo for output signals
- rfifo_used <= internal_rfifo_used;
---synthesis translate_off
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r
+ --synthesis translate_off
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- component scfifo is
+ --GENERIC (
+ -- lpm_hint : STRING;
+ -- lpm_numwords : NATURAL;
+ -- lpm_showahead : STRING;
+ -- lpm_type : STRING;
+ -- lpm_width : NATURAL;
+ -- lpm_widthu : NATURAL;
+ -- overflow_checking : STRING;
+ -- underflow_checking : STRING;
+ -- use_eab : STRING
+ -- );
+ -- PORT (
+ -- signal full : OUT STD_LOGIC;
+ -- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+ -- signal empty : OUT STD_LOGIC;
+ -- signal rdreq : IN STD_LOGIC;
+ -- signal aclr : IN STD_LOGIC;
+ -- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal clock : IN STD_LOGIC;
+ -- signal wrreq : IN STD_LOGIC
+ -- );
+ -- end component scfifo;
+ --synthesis read_comments_as_HDL off
+ signal internal_fifo_EF : std_logic;
+ signal internal_fifo_rdata : std_logic_vector(7 downto 0);
+ signal internal_rfifo_full : std_logic;
+ signal internal_rfifo_used : std_logic_vector(5 downto 0);
+ begin
+ --vhdl renameroo for output signals
+ fifo_EF <= internal_fifo_EF;
+ --vhdl renameroo for output signals
+ fifo_rdata <= internal_fifo_rdata;
+ --vhdl renameroo for output signals
+ rfifo_full <= internal_rfifo_full;
+ --vhdl renameroo for output signals
+ rfifo_used <= internal_rfifo_used;
+ --synthesis translate_off
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r
port map(
fifo_EF => internal_fifo_EF,
fifo_rdata => internal_fifo_rdata,
@@ -376,344 +382,346 @@ begin
rst_n => rst_n
);
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- rfifo : scfifo
--- generic map(
--- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
--- lpm_numwords => 64,
--- lpm_showahead => "OFF",
--- lpm_type => "scfifo",
--- lpm_width => 8,
--- lpm_widthu => 6,
--- overflow_checking => "OFF",
--- underflow_checking => "OFF",
--- use_eab => "ON"
--- )
--- port map(
--- aclr => fifo_clear,
--- clock => clk,
--- data => t_dat,
--- empty => internal_fifo_EF,
--- full => internal_rfifo_full,
--- q => internal_fifo_rdata,
--- rdreq => fifo_rd,
--- usedw => internal_rfifo_used,
--- wrreq => wr_rfifo
--- );
---
---synthesis read_comments_as_HDL off
-end europa;
-
--- turn off superfluous VHDL processor warnings
--- altera message_level Level1
--- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- rfifo : scfifo
+ -- generic map(
+ -- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
+ -- lpm_numwords => 64,
+ -- lpm_showahead => "OFF",
+ -- lpm_type => "scfifo",
+ -- lpm_width => 8,
+ -- lpm_widthu => 6,
+ -- overflow_checking => "OFF",
+ -- underflow_checking => "OFF",
+ -- use_eab => "ON"
+ -- )
+ -- port map(
+ -- aclr => fifo_clear,
+ -- clock => clk,
+ -- data => t_dat,
+ -- empty => internal_fifo_EF,
+ -- full => internal_rfifo_full,
+ -- q => internal_fifo_rdata,
+ -- rdreq => fifo_rd,
+ -- usedw => internal_rfifo_used,
+ -- wrreq => wr_rfifo
+ -- );
+ --
+ --synthesis read_comments_as_HDL off
+ end europa;
+
+ -- turn off superfluous VHDL processor warnings
+ -- altera message_level Level1
+ -- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
- port (
- -- inputs:
- signal av_address : in std_logic;
- signal av_chipselect : in std_logic;
- signal av_read_n : in std_logic;
- signal av_write_n : in std_logic;
- signal av_writedata : in std_logic_vector(31 downto 0);
- signal clk : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal av_irq : out std_logic;
- signal av_readdata : out std_logic_vector(31 downto 0);
- signal av_waitrequest : out std_logic;
- signal dataavailable : out std_logic;
- signal readyfordata : out std_logic
- );
-attribute ALTERA_ATTRIBUTE : string;
-attribute ALTERA_ATTRIBUTE of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi : entity is "SUPPRESS_DA_RULE_INTERNAL=" "R101,C106,D101,D103" "";
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi;
+ port (
+ -- inputs:
+ signal av_address : in std_logic;
+ signal av_chipselect : in std_logic;
+ signal av_read_n : in std_logic;
+ signal av_write_n : in std_logic;
+ signal av_writedata : in std_logic_vector(31 downto 0);
+ signal clk : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal av_irq : out std_logic;
+ signal av_readdata : out std_logic_vector(31 downto 0);
+ signal av_waitrequest : out std_logic;
+ signal dataavailable : out std_logic;
+ signal readyfordata : out std_logic
+ );
+ attribute ALTERA_ATTRIBUTE : string;
+ attribute ALTERA_ATTRIBUTE of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi : entity is "SUPPRESS_DA_RULE_INTERNAL=" "R101,C106,D101,D103" "";
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
- signal rd_wfifo : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
-
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
- signal t_dat : in std_logic_vector(7 downto 0);
- signal wr_rfifo : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
-
---synthesis read_comments_as_HDL on
--- component alt_jtag_atlantic is
---GENERIC (
--- INSTANCE_ID : NATURAL;
--- LOG2_RXFIFO_DEPTH : NATURAL;
--- LOG2_TXFIFO_DEPTH : NATURAL;
--- SLD_AUTO_INSTANCE_INDEX : STRING
--- );
--- PORT (
--- signal t_pause : OUT STD_LOGIC;
--- signal r_ena : OUT STD_LOGIC;
--- signal t_ena : OUT STD_LOGIC;
--- signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal t_dav : IN STD_LOGIC;
--- signal rst_n : IN STD_LOGIC;
--- signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal r_val : IN STD_LOGIC;
--- signal clk : IN STD_LOGIC
--- );
--- end component alt_jtag_atlantic;
---synthesis read_comments_as_HDL off
- signal ac : std_logic;
- signal activity : std_logic;
- signal fifo_AE : std_logic;
- signal fifo_AF : std_logic;
- signal fifo_EF : std_logic;
- signal fifo_FF : std_logic;
- signal fifo_clear : std_logic;
- signal fifo_rd : std_logic;
- signal fifo_rdata : std_logic_vector(7 downto 0);
- signal fifo_wdata : std_logic_vector(7 downto 0);
- signal fifo_wr : std_logic;
- signal ien_AE : std_logic;
- signal ien_AF : std_logic;
- signal internal_av_waitrequest : std_logic;
- signal ipen_AE : std_logic;
- signal ipen_AF : std_logic;
- signal pause_irq : std_logic;
- signal r_dat : std_logic_vector(7 downto 0);
- signal r_ena : std_logic;
- signal r_val : std_logic;
- signal rd_wfifo : std_logic;
- signal read_0 : std_logic;
- signal rfifo_full : std_logic;
- signal rfifo_used : std_logic_vector(5 downto 0);
- signal rvalid : std_logic;
- signal sim_r_ena : std_logic;
- signal sim_t_dat : std_logic;
- signal sim_t_ena : std_logic;
- signal sim_t_pause : std_logic;
- signal t_dat : std_logic_vector(7 downto 0);
- signal t_dav : std_logic;
- signal t_ena : std_logic;
- signal t_pause : std_logic;
- signal wfifo_empty : std_logic;
- signal wfifo_used : std_logic_vector(5 downto 0);
- signal woverflow : std_logic;
- signal wr_rfifo : std_logic;
-begin
- --avalon_jtag_slave, which is an e_avalon_slave
- rd_wfifo <= r_ena and not wfifo_empty;
- wr_rfifo <= t_ena and not rfifo_full;
- fifo_clear <= not rst_n;
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w
- port map(
- fifo_FF => fifo_FF,
- r_dat => r_dat,
- wfifo_empty => wfifo_empty,
- wfifo_used => wfifo_used,
- clk => clk,
- fifo_clear => fifo_clear,
- fifo_wdata => fifo_wdata,
- fifo_wr => fifo_wr,
- rd_wfifo => rd_wfifo
- );
-
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r
- port map(
- fifo_EF => fifo_EF,
- fifo_rdata => fifo_rdata,
- rfifo_full => rfifo_full,
- rfifo_used => rfifo_used,
- clk => clk,
- fifo_clear => fifo_clear,
- fifo_rd => fifo_rd,
- rst_n => rst_n,
- t_dat => t_dat,
- wr_rfifo => wr_rfifo
- );
-
- ipen_AE <= ien_AE and fifo_AE;
- ipen_AF <= ien_AF and ((pause_irq or fifo_AF));
- av_irq <= ipen_AE or ipen_AF;
- activity <= t_pause or t_ena;
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- pause_irq <= std_logic'('0');
- elsif clk'event and clk = '1' then
- -- only if fifo is not empty...
- if std_logic'((t_pause and not fifo_EF)) = '1' then
- pause_irq <= std_logic'('1');
- elsif std_logic'(read_0) = '1' then
- pause_irq <= std_logic'('0');
- end if;
- end if;
- end process;
-
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- r_val <= std_logic'('0');
- t_dav <= std_logic'('1');
- elsif clk'event and clk = '1' then
- r_val <= r_ena and not wfifo_empty;
- t_dav <= not rfifo_full;
- end if;
- end process;
-
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- fifo_AE <= std_logic'('0');
- fifo_AF <= std_logic'('0');
- fifo_wr <= std_logic'('0');
- rvalid <= std_logic'('0');
- read_0 <= std_logic'('0');
- ien_AE <= std_logic'('0');
- ien_AF <= std_logic'('0');
- ac <= std_logic'('0');
- woverflow <= std_logic'('0');
- internal_av_waitrequest <= std_logic'('1');
- elsif clk'event and clk = '1' then
- fifo_AE <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))) <= std_logic_vector'("00000000000000000000000000001000")));
- fifo_AF <= to_std_logic(((std_logic_vector'("000000000000000000000000") & (((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(rfifo_full) & rfifo_used))))))) <= std_logic_vector'("00000000000000000000000000001000")));
- fifo_wr <= std_logic'('0');
- read_0 <= std_logic'('0');
- internal_av_waitrequest <= not (((av_chipselect and ((not av_write_n or not av_read_n))) and internal_av_waitrequest));
- if std_logic'(activity) = '1' then
- ac <= std_logic'('1');
- end if;
- -- write
- if std_logic'(((av_chipselect and not av_write_n) and internal_av_waitrequest)) = '1' then
- -- addr 1 is control; addr 0 is data
- if std_logic'(av_address) = '1' then
- ien_AF <= av_writedata(0);
- ien_AE <= av_writedata(1);
- if std_logic'((av_writedata(10) and not activity)) = '1' then
- ac <= std_logic'('0');
- end if;
- else
- fifo_wr <= not fifo_FF;
- woverflow <= fifo_FF;
- end if;
- end if;
- -- read
- if std_logic'(((av_chipselect and not av_read_n) and internal_av_waitrequest)) = '1' then
- -- addr 1 is interrupt; addr 0 is data
- if std_logic'(not av_address) = '1' then
- rvalid <= not fifo_EF;
- end if;
- read_0 <= not av_address;
- end if;
- end if;
- end process;
-
- fifo_wdata <= av_writedata(7 downto 0);
- fifo_rd <= A_WE_StdLogic((std_logic'(((((av_chipselect and not av_read_n) and internal_av_waitrequest) and not av_address))) = '1'), not fifo_EF, std_logic'('0'));
- av_readdata <= A_EXT (A_WE_StdLogicVector((std_logic'(read_0) = '1'), (std_logic_vector'("0") & ((A_REP(std_logic'('0'), 9) & A_ToStdLogicVector(rfifo_full) & rfifo_used & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & fifo_rdata))), (A_REP(std_logic'('0'), 9) & ((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))))) & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & A_REP(std_logic'('0'), 6) & A_ToStdLogicVector(ien_AE) & A_ToStdLogicVector(ien_AF))), 32);
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- readyfordata <= std_logic'('0');
- elsif clk'event and clk = '1' then
- readyfordata <= not fifo_FF;
- end if;
- end process;
-
- --vhdl renameroo for output signals
- av_waitrequest <= internal_av_waitrequest;
---synthesis translate_off
- -- Tie off Atlantic Interface signals not used for simulation
- process (clk)
- begin
- if clk'event and clk = '1' then
- sim_t_pause <= std_logic'('0');
- sim_t_ena <= std_logic'('0');
- sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
- sim_r_ena <= std_logic'('0');
- end if;
- end process;
-
- r_ena <= sim_r_ena;
- t_ena <= sim_t_ena;
- t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat));
- t_pause <= sim_t_pause;
- process (fifo_EF)
- begin
- dataavailable <= not fifo_EF;
- end process;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_alt_jtag_atlantic : alt_jtag_atlantic
--- generic map(
--- INSTANCE_ID => 0,
--- LOG2_RXFIFO_DEPTH => 6,
--- LOG2_TXFIFO_DEPTH => 6,
--- SLD_AUTO_INSTANCE_INDEX => "YES"
--- )
--- port map(
--- clk => clk,
--- r_dat => r_dat,
--- r_ena => r_ena,
--- r_val => r_val,
--- rst_n => rst_n,
--- t_dat => t_dat,
--- t_dav => t_dav,
--- t_ena => t_ena,
--- t_pause => t_pause
--- );
---
--- process (clk, rst_n)
--- begin
--- if rst_n = '0' then
--- dataavailable <= std_logic'('0');
--- elsif clk'event and clk = '1' then
--- dataavailable <= NOT fifo_EF;
--- end if;
---
--- end process;
---
---synthesis read_comments_as_HDL off
-end europa;
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+ signal rd_wfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
+
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+ signal t_dat : in std_logic_vector(7 downto 0);
+ signal wr_rfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(
+ 5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
+
+ --synthesis read_comments_as_HDL on
+ -- component alt_jtag_atlantic is
+ --GENERIC (
+ -- INSTANCE_ID : NATURAL;
+ -- LOG2_RXFIFO_DEPTH : NATURAL;
+ -- LOG2_TXFIFO_DEPTH : NATURAL;
+ -- SLD_AUTO_INSTANCE_INDEX : STRING
+ -- );
+ -- PORT (
+ -- signal t_pause : OUT STD_LOGIC;
+ -- signal r_ena : OUT STD_LOGIC;
+ -- signal t_ena : OUT STD_LOGIC;
+ -- signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal t_dav : IN STD_LOGIC;
+ -- signal rst_n : IN STD_LOGIC;
+ -- signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal r_val : IN STD_LOGIC;
+ -- signal clk : IN STD_LOGIC
+ -- );
+ -- end component alt_jtag_atlantic;
+ --synthesis read_comments_as_HDL off
+ signal ac : std_logic;
+ signal activity : std_logic;
+ signal fifo_AE : std_logic;
+ signal fifo_AF : std_logic;
+ signal fifo_EF : std_logic;
+ signal fifo_FF : std_logic;
+ signal fifo_clear : std_logic;
+ signal fifo_rd : std_logic;
+ signal fifo_rdata : std_logic_vector(7 downto 0);
+ signal fifo_wdata : std_logic_vector(7 downto 0);
+ signal fifo_wr : std_logic;
+ signal ien_AE : std_logic;
+ signal ien_AF : std_logic;
+ signal internal_av_waitrequest : std_logic;
+ signal ipen_AE : std_logic;
+ signal ipen_AF : std_logic;
+ signal pause_irq : std_logic;
+ signal r_dat : std_logic_vector(7 downto 0);
+ signal r_ena : std_logic;
+ signal r_val : std_logic;
+ signal rd_wfifo : std_logic;
+ signal read_0 : std_logic;
+ signal rfifo_full : std_logic;
+ signal rfifo_used : std_logic_vector(5 downto 0);
+ signal rvalid : std_logic;
+ signal sim_r_ena : std_logic;
+ signal sim_t_dat : std_logic;
+ signal sim_t_ena : std_logic;
+ signal sim_t_pause : std_logic;
+ signal t_dat : std_logic_vector(7 downto 0);
+ signal t_dav : std_logic;
+ signal t_ena : std_logic;
+ signal t_pause : std_logic;
+ signal wfifo_empty : std_logic;
+ signal wfifo_used : std_logic_vector(5 downto 0);
+ signal woverflow : std_logic;
+ signal wr_rfifo : std_logic;
+ begin
+ --avalon_jtag_slave, which is an e_avalon_slave
+ rd_wfifo <= r_ena and not wfifo_empty;
+ wr_rfifo <= t_ena and not rfifo_full;
+ fifo_clear <= not rst_n;
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w
+ port map(
+ fifo_FF => fifo_FF,
+ r_dat => r_dat,
+ wfifo_empty => wfifo_empty,
+ wfifo_used => wfifo_used,
+ clk => clk,
+ fifo_clear => fifo_clear,
+ fifo_wdata => fifo_wdata,
+ fifo_wr => fifo_wr,
+ rd_wfifo => rd_wfifo
+ );
+
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r
+ port map(
+ fifo_EF => fifo_EF,
+ fifo_rdata => fifo_rdata,
+ rfifo_full => rfifo_full,
+ rfifo_used => rfifo_used,
+ clk => clk,
+ fifo_clear => fifo_clear,
+ fifo_rd => fifo_rd,
+ rst_n => rst_n,
+ t_dat => t_dat,
+ wr_rfifo => wr_rfifo
+ );
+
+ ipen_AE <= ien_AE and fifo_AE;
+ ipen_AF <= ien_AF and ((pause_irq or fifo_AF));
+ av_irq <= ipen_AE or ipen_AF;
+ activity <= t_pause or t_ena;
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ pause_irq <= std_logic'('0');
+ elsif clk'event and clk = '1' then
+ -- only if fifo is not empty...
+ if std_logic'((t_pause and not fifo_EF)) = '1' then
+ pause_irq <= std_logic'('1');
+ elsif std_logic'(read_0) = '1' then
+ pause_irq <= std_logic'('0');
+ end if;
+ end if;
+ end process;
+
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ r_val <= std_logic'('0');
+ t_dav <= std_logic'('1');
+ elsif clk'event and clk = '1' then
+ r_val <= r_ena and not wfifo_empty;
+ t_dav <= not rfifo_full;
+ end if;
+ end process;
+
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ fifo_AE <= std_logic'('0');
+ fifo_AF <= std_logic'('0');
+ fifo_wr <= std_logic'('0');
+ rvalid <= std_logic'('0');
+ read_0 <= std_logic'('0');
+ ien_AE <= std_logic'('0');
+ ien_AF <= std_logic'('0');
+ ac <= std_logic'('0');
+ woverflow <= std_logic'('0');
+ internal_av_waitrequest <= std_logic'('1');
+ elsif clk'event and clk = '1' then
+ fifo_AE <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))) <= std_logic_vector'("00000000000000000000000000001000")));
+ fifo_AF <= to_std_logic(((std_logic_vector'("000000000000000000000000") & (((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(rfifo_full) & rfifo_used))))))) <= std_logic_vector'("00000000000000000000000000001000")));
+ fifo_wr <= std_logic'('0');
+ read_0 <= std_logic'('0');
+ internal_av_waitrequest <= not (((av_chipselect and ((not av_write_n or not av_read_n))) and internal_av_waitrequest));
+ if std_logic'(activity) = '1' then
+ ac <= std_logic'('1');
+ end if;
+ -- write
+ if std_logic'(((av_chipselect and not av_write_n) and internal_av_waitrequest)) = '1' then
+ -- addr 1 is control; addr 0 is data
+ if std_logic'(av_address) = '1' then
+ ien_AF <= av_writedata(0);
+ ien_AE <= av_writedata(1);
+ if std_logic'((av_writedata(10) and not activity)) = '1' then
+ ac <= std_logic'('0');
+ end if;
+ else
+ fifo_wr <= not fifo_FF;
+ woverflow <= fifo_FF;
+ end if;
+ end if;
+ -- read
+ if std_logic'(((av_chipselect and not av_read_n) and internal_av_waitrequest)) = '1' then
+ -- addr 1 is interrupt; addr 0 is data
+ if std_logic'(not av_address) = '1' then
+ rvalid <= not fifo_EF;
+ end if;
+ read_0 <= not av_address;
+ end if;
+ end if;
+ end process;
+
+ fifo_wdata <= av_writedata(7 downto 0);
+ fifo_rd <= A_WE_StdLogic((std_logic'(((((av_chipselect and not av_read_n) and internal_av_waitrequest) and not av_address))) = '1'), not fifo_EF, std_logic'('0'));
+ av_readdata <= A_EXT (A_WE_StdLogicVector((std_logic'(read_0) = '1'), (std_logic_vector'("0") & ((A_REP(std_logic'('0'), 9) & A_ToStdLogicVector(rfifo_full) & rfifo_used & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & fifo_rdata))), (A_REP(std_logic'('0'), 9) & ((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))))) & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & A_REP(std_logic'('0'), 6) & A_ToStdLogicVector(ien_AE) & A_ToStdLogicVector(ien_AF))), 32);
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ readyfordata <= std_logic'('0');
+ elsif clk'event and clk = '1' then
+ readyfordata <= not fifo_FF;
+ end if;
+ end process;
+
+ --vhdl renameroo for output signals
+ av_waitrequest <= internal_av_waitrequest;
+ --synthesis translate_off
+ -- Tie off Atlantic Interface signals not used for simulation
+ process (clk)
+ begin
+ if clk'event and clk = '1' then
+ sim_t_pause <= std_logic'('0');
+ sim_t_ena <= std_logic'('0');
+ sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
+ sim_r_ena <= std_logic'('0');
+ end if;
+ end process;
+
+ r_ena <= sim_r_ena;
+ t_ena <= sim_t_ena;
+ t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat));
+ t_pause <= sim_t_pause;
+ process (fifo_EF)
+ begin
+ dataavailable <= not fifo_EF;
+ end process;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_alt_jtag_atlantic : alt_jtag_atlantic
+ -- generic map(
+ -- INSTANCE_ID => 0,
+ -- LOG2_RXFIFO_DEPTH => 6,
+ -- LOG2_TXFIFO_DEPTH => 6,
+ -- SLD_AUTO_INSTANCE_INDEX => "YES"
+ -- )
+ -- port map(
+ -- clk => clk,
+ -- r_dat => r_dat,
+ -- r_ena => r_ena,
+ -- r_val => r_val,
+ -- rst_n => rst_n,
+ -- t_dat => t_dat,
+ -- t_dav => t_dav,
+ -- t_ena => t_ena,
+ -- t_pause => t_pause
+ -- );
+ --
+ -- process (clk, rst_n)
+ -- begin
+ -- if rst_n = '0' then
+ -- dataavailable <= std_logic'('0');
+ -- elsif clk'event and clk = '1' then
+ -- dataavailable <= NOT fifo_EF;
+ -- end if;
+ --
+ -- end process;
+ --
+ --synthesis read_comments_as_HDL off
+ end europa;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
index bc11c57e41..68a1b9756e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
@@ -1,28 +1,28 @@
- component qsys_unb2b_minimal_jtag_uart_0 is
- port (
- av_chipselect : in std_logic := 'X'; -- chipselect
- av_address : in std_logic := 'X'; -- address
- av_read_n : in std_logic := 'X'; -- read_n
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_write_n : in std_logic := 'X'; -- write_n
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_waitrequest : out std_logic; -- waitrequest
- clk : in std_logic := 'X'; -- clk
- av_irq : out std_logic; -- irq
- rst_n : in std_logic := 'X' -- reset_n
- );
- end component qsys_unb2b_minimal_jtag_uart_0;
+component qsys_unb2b_minimal_jtag_uart_0 is
+ port (
+ av_chipselect : in std_logic := 'X'; -- chipselect
+ av_address : in std_logic := 'X'; -- address
+ av_read_n : in std_logic := 'X'; -- read_n
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_write_n : in std_logic := 'X'; -- write_n
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_waitrequest : out std_logic; -- waitrequest
+ clk : in std_logic := 'X'; -- clk
+ av_irq : out std_logic; -- irq
+ rst_n : in std_logic := 'X' -- reset_n
+ );
+end component qsys_unb2b_minimal_jtag_uart_0;
- u0 : component qsys_unb2b_minimal_jtag_uart_0
- port map (
- av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
- av_address => CONNECTED_TO_av_address, -- .address
- av_read_n => CONNECTED_TO_av_read_n, -- .read_n
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_write_n => CONNECTED_TO_av_write_n, -- .write_n
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
- clk => CONNECTED_TO_clk, -- clk.clk
- av_irq => CONNECTED_TO_av_irq, -- irq.irq
- rst_n => CONNECTED_TO_rst_n -- reset.reset_n
- );
+u0 : component qsys_unb2b_minimal_jtag_uart_0
+ port map (
+ av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
+ av_address => CONNECTED_TO_av_address, -- .address
+ av_read_n => CONNECTED_TO_av_read_n, -- .read_n
+ av_readdata => CONNECTED_TO_av_readdata, -- .readdata
+ av_write_n => CONNECTED_TO_av_write_n, -- .write_n
+ av_writedata => CONNECTED_TO_av_writedata, -- .writedata
+ av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
+ clk => CONNECTED_TO_clk, -- clk.clk
+ av_irq => CONNECTED_TO_av_irq, -- irq.irq
+ rst_n => CONNECTED_TO_rst_n -- reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
index 64222401d7..d7a5f0bc08 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
@@ -15,99 +15,101 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y is
- generic (
- INIT_FILE : string := "onchip_memory2_0.hex"
- );
- port (
- -- inputs:
- signal address : in std_logic_vector(14 downto 0);
- signal byteenable : in std_logic_vector(3 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal clken : in std_logic;
- signal freeze : in std_logic;
- signal reset : in std_logic;
- signal reset_req : in std_logic;
- signal write : in std_logic;
- signal writedata : in std_logic_vector(31 downto 0);
+ generic (
+ INIT_FILE : string := "onchip_memory2_0.hex"
+ );
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(14 downto 0);
+ signal byteenable : in std_logic_vector(3 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal clken : in std_logic;
+ signal freeze : in std_logic;
+ signal reset : in std_logic;
+ signal reset_req : in std_logic;
+ signal write : in std_logic;
+ signal writedata : in std_logic_vector(31 downto 0);
- -- outputs:
- signal readdata : out std_logic_vector(31 downto 0)
- );
-end entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y;
+ -- outputs:
+ signal readdata : out std_logic_vector(
+ 31 downto 0)
+ );
+ end entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y;
architecture europa of qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y is
component altsyncram is
-generic (
+ generic (
byte_size : natural;
- init_file : string;
- lpm_type : string;
- maximum_depth : natural;
- numwords_a : natural;
- operation_mode : string;
- outdata_reg_a : string;
- ram_block_type : string;
- read_during_write_mode_mixed_ports : string;
- read_during_write_mode_port_a : string;
- width_a : natural;
- width_byteena_a : natural;
- widthad_a : natural
- );
+ init_file : string;
+ lpm_type : string;
+ maximum_depth : natural;
+ numwords_a : natural;
+ operation_mode : string;
+ outdata_reg_a : string;
+ ram_block_type : string;
+ read_during_write_mode_mixed_ports : string;
+ read_during_write_mode_port_a : string;
+ width_a : natural;
+ width_byteena_a : natural;
+ widthad_a : natural
+ );
port (
- signal q_a : out std_logic_vector(31 downto 0);
- signal wren_a : in std_logic;
- signal byteena_a : in std_logic_vector(3 downto 0);
- signal clock0 : in std_logic;
- signal address_a : in std_logic_vector(14 downto 0);
- signal clocken0 : in std_logic;
- signal data_a : in std_logic_vector(31 downto 0)
+ signal q_a : out std_logic_vector(31 downto 0);
+ signal wren_a : in std_logic;
+ signal byteena_a : in std_logic_vector(3 downto 0);
+ signal clock0 : in std_logic;
+ signal address_a : in std_logic_vector(14 downto 0);
+ signal clocken0 : in std_logic;
+ signal data_a : in std_logic_vector(
+ 31 downto 0)
+ );
+ end component altsyncram;
+ signal clocken0 : std_logic;
+ signal internal_readdata : std_logic_vector(31 downto 0);
+ signal wren : std_logic;
+ begin
+ wren <= chipselect and write;
+ clocken0 <= clken and not reset_req;
+ the_altsyncram : altsyncram
+ generic map(
+ byte_size => 8,
+ init_file => INIT_FILE,
+ lpm_type => "altsyncram",
+ maximum_depth => 32768,
+ numwords_a => 32768,
+ operation_mode => "SINGLE_PORT",
+ outdata_reg_a => "UNREGISTERED",
+ ram_block_type => "AUTO",
+ read_during_write_mode_mixed_ports => "DONT_CARE",
+ read_during_write_mode_port_a => "DONT_CARE",
+ width_a => 32,
+ width_byteena_a => 4,
+ widthad_a => 15
+ )
+ port map(
+ address_a => address,
+ byteena_a => byteenable,
+ clock0 => clk,
+ clocken0 => clocken0,
+ data_a => writedata,
+ q_a => internal_readdata,
+ wren_a => wren
);
- end component altsyncram;
- signal clocken0 : std_logic;
- signal internal_readdata : std_logic_vector(31 downto 0);
- signal wren : std_logic;
-begin
- wren <= chipselect and write;
- clocken0 <= clken and not reset_req;
- the_altsyncram : altsyncram
- generic map(
- byte_size => 8,
- init_file => INIT_FILE,
- lpm_type => "altsyncram",
- maximum_depth => 32768,
- numwords_a => 32768,
- operation_mode => "SINGLE_PORT",
- outdata_reg_a => "UNREGISTERED",
- ram_block_type => "AUTO",
- read_during_write_mode_mixed_ports => "DONT_CARE",
- read_during_write_mode_port_a => "DONT_CARE",
- width_a => 32,
- width_byteena_a => 4,
- widthad_a => 15
- )
- port map(
- address_a => address,
- byteena_a => byteenable,
- clock0 => clk,
- clocken0 => clocken0,
- data_a => writedata,
- q_a => internal_readdata,
- wren_a => wren
- );
- --s1, which is an e_avalon_slave
- --s2, which is an e_avalon_slave
- --vhdl renameroo for output signals
- readdata <= internal_readdata;
-end europa;
+ --s1, which is an e_avalon_slave
+ --s2, which is an e_avalon_slave
+ --vhdl renameroo for output signals
+ readdata <= internal_readdata;
+ end europa;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
index f453120efc..500649d8da 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
@@ -1,28 +1,28 @@
- component qsys_unb2b_minimal_onchip_memory2_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- reset_req : in std_logic := 'X'; -- reset_req
- address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
- clken : in std_logic := 'X'; -- clken
- chipselect : in std_logic := 'X'; -- chipselect
- write : in std_logic := 'X'; -- write
- readdata : out std_logic_vector(31 downto 0); -- readdata
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
- );
- end component qsys_unb2b_minimal_onchip_memory2_0;
+component qsys_unb2b_minimal_onchip_memory2_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ reset_req : in std_logic := 'X'; -- reset_req
+ address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
+ clken : in std_logic := 'X'; -- clken
+ chipselect : in std_logic := 'X'; -- chipselect
+ write : in std_logic := 'X'; -- write
+ readdata : out std_logic_vector(31 downto 0); -- readdata
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
+ );
+end component qsys_unb2b_minimal_onchip_memory2_0;
- u0 : component qsys_unb2b_minimal_onchip_memory2_0
- port map (
- clk => CONNECTED_TO_clk, -- clk1.clk
- reset => CONNECTED_TO_reset, -- reset1.reset
- reset_req => CONNECTED_TO_reset_req, -- .reset_req
- address => CONNECTED_TO_address, -- s1.address
- clken => CONNECTED_TO_clken, -- .clken
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write => CONNECTED_TO_write, -- .write
- readdata => CONNECTED_TO_readdata, -- .readdata
- writedata => CONNECTED_TO_writedata, -- .writedata
- byteenable => CONNECTED_TO_byteenable -- .byteenable
- );
+u0 : component qsys_unb2b_minimal_onchip_memory2_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk1.clk
+ reset => CONNECTED_TO_reset, -- reset1.reset
+ reset_req => CONNECTED_TO_reset_req, -- .reset_req
+ address => CONNECTED_TO_address, -- s1.address
+ clken => CONNECTED_TO_clken, -- .clken
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ write => CONNECTED_TO_write, -- .write
+ readdata => CONNECTED_TO_readdata, -- .readdata
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ byteenable => CONNECTED_TO_byteenable -- .byteenable
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
index 580187433d..faef008bb8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_pio_pps is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_pio_pps;
+component qsys_unb2b_minimal_pio_pps is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_pio_pps;
- u0 : component qsys_unb2b_minimal_pio_pps
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_pio_pps
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
index b05a01d444..031eaa0af9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_pio_system_info is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_pio_system_info;
+component qsys_unb2b_minimal_pio_system_info is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_pio_system_info;
- u0 : component qsys_unb2b_minimal_pio_system_info
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_pio_system_info
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
index 0cc60e970e..d01f9d0090 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
@@ -15,36 +15,37 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
- port (
- -- inputs:
- signal address : in std_logic_vector(1 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal reset_n : in std_logic;
- signal write_n : in std_logic;
- signal writedata : in std_logic_vector(31 downto 0);
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(1 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal reset_n : in std_logic;
+ signal write_n : in std_logic;
+ signal writedata : in std_logic_vector(31 downto 0);
- -- outputs:
- signal out_port : out std_logic;
- signal readdata : out std_logic_vector(31 downto 0)
- );
-end entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq;
+ -- outputs:
+ signal out_port : out std_logic;
+ signal readdata : out std_logic_vector(
+ 31 downto 0)
+ );
+ end entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq;
architecture europa of qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
- signal clk_en : std_logic;
- signal data_out : std_logic;
- signal read_mux_out : std_logic;
+ signal clk_en : std_logic;
+ signal data_out : std_logic;
+ signal read_mux_out : std_logic;
begin
clk_en <= std_logic'('1');
--s1, which is an e_avalon_slave
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
index 4639e141f5..0b7dcff402 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
@@ -1,24 +1,24 @@
- component qsys_unb2b_minimal_pio_wdi is
- port (
- clk : in std_logic := 'X'; -- clk
- out_port : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
- write_n : in std_logic := 'X'; -- write_n
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- chipselect : in std_logic := 'X'; -- chipselect
- readdata : out std_logic_vector(31 downto 0) -- readdata
- );
- end component qsys_unb2b_minimal_pio_wdi;
+component qsys_unb2b_minimal_pio_wdi is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ out_port : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
+ write_n : in std_logic := 'X'; -- write_n
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ chipselect : in std_logic := 'X'; -- chipselect
+ readdata : out std_logic_vector(31 downto 0) -- readdata
+ );
+end component qsys_unb2b_minimal_pio_wdi;
- u0 : component qsys_unb2b_minimal_pio_wdi
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- out_port => CONNECTED_TO_out_port, -- external_connection.export
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- write_n => CONNECTED_TO_write_n, -- .write_n
- writedata => CONNECTED_TO_writedata, -- .writedata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- readdata => CONNECTED_TO_readdata -- .readdata
- );
+u0 : component qsys_unb2b_minimal_pio_wdi
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ out_port => CONNECTED_TO_out_port, -- external_connection.export
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ address => CONNECTED_TO_address, -- s1.address
+ write_n => CONNECTED_TO_write_n, -- .write_n
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ readdata => CONNECTED_TO_readdata -- .readdata
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
index ec32464391..b7feaef425 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_dpmm_ctrl is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_dpmm_ctrl;
+component qsys_unb2b_minimal_reg_dpmm_ctrl is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_dpmm_ctrl;
- u0 : component qsys_unb2b_minimal_reg_dpmm_ctrl
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_dpmm_ctrl
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
index 902a48132b..c3c65aee84 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_dpmm_data is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_dpmm_data;
+component qsys_unb2b_minimal_reg_dpmm_data is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_dpmm_data;
- u0 : component qsys_unb2b_minimal_reg_dpmm_data
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_dpmm_data
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
index b7e771b662..7cae834a56 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_epcs is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_epcs;
+component qsys_unb2b_minimal_reg_epcs is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_epcs;
- u0 : component qsys_unb2b_minimal_reg_epcs
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_epcs
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
index 170f85ed58..7a32df88c6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_fpga_temp_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_fpga_temp_sens;
+component qsys_unb2b_minimal_reg_fpga_temp_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_fpga_temp_sens;
- u0 : component qsys_unb2b_minimal_reg_fpga_temp_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_fpga_temp_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
index 495dae0b21..cfde8e9176 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_fpga_voltage_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_fpga_voltage_sens;
+component qsys_unb2b_minimal_reg_fpga_voltage_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_fpga_voltage_sens;
- u0 : component qsys_unb2b_minimal_reg_fpga_voltage_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_fpga_voltage_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
index e099a81cd1..73c8f9c0cf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_mmdp_ctrl is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_mmdp_ctrl;
+component qsys_unb2b_minimal_reg_mmdp_ctrl is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_mmdp_ctrl;
- u0 : component qsys_unb2b_minimal_reg_mmdp_ctrl
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_mmdp_ctrl
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
index d25eb92a9c..c9c4463043 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_mmdp_data is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_mmdp_data;
+component qsys_unb2b_minimal_reg_mmdp_data is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_mmdp_data;
- u0 : component qsys_unb2b_minimal_reg_mmdp_data
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_mmdp_data
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
index 837cb45819..e54b9651be 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_remu is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_remu;
+component qsys_unb2b_minimal_reg_remu is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_remu;
- u0 : component qsys_unb2b_minimal_reg_remu
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_remu
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
index b97ef222ec..c9fdcffd9c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_unb_pmbus is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_unb_pmbus;
+component qsys_unb2b_minimal_reg_unb_pmbus is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_unb_pmbus;
- u0 : component qsys_unb2b_minimal_reg_unb_pmbus
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_unb_pmbus
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
index 1871be2f74..c80cce2d60 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_unb_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_unb_sens;
+component qsys_unb2b_minimal_reg_unb_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_unb_sens;
- u0 : component qsys_unb2b_minimal_reg_unb_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_unb_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
index 229a2d315e..f956b5a4e7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_wdi is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_wdi;
+component qsys_unb2b_minimal_reg_wdi is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_wdi;
- u0 : component qsys_unb2b_minimal_reg_wdi
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_wdi
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
index ae35f2bd19..ed9ccedfa9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_rom_system_info is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_rom_system_info;
+component qsys_unb2b_minimal_rom_system_info is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_rom_system_info;
- u0 : component qsys_unb2b_minimal_rom_system_info
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_rom_system_info
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
index a954c70405..70d139b638 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
@@ -15,51 +15,52 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
- port (
- -- inputs:
- signal address : in std_logic_vector(2 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal reset_n : in std_logic;
- signal write_n : in std_logic;
- signal writedata : in std_logic_vector(15 downto 0);
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(2 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal reset_n : in std_logic;
+ signal write_n : in std_logic;
+ signal writedata : in std_logic_vector(15 downto 0);
- -- outputs:
- signal irq : out std_logic;
- signal readdata : out std_logic_vector(15 downto 0)
- );
-end entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby;
+ -- outputs:
+ signal irq : out std_logic;
+ signal readdata : out std_logic_vector(
+ 15 downto 0)
+ );
+ end entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby;
architecture europa of qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
- signal clk_en : std_logic;
- signal control_interrupt_enable : std_logic;
- signal control_register : std_logic;
- signal control_wr_strobe : std_logic;
- signal counter_is_running : std_logic;
- signal counter_is_zero : std_logic;
- signal counter_load_value : std_logic_vector(16 downto 0);
- signal delayed_unxcounter_is_zeroxx0 : std_logic;
- signal do_start_counter : std_logic;
- signal do_stop_counter : std_logic;
- signal force_reload : std_logic;
- signal internal_counter : std_logic_vector(16 downto 0);
- signal period_h_wr_strobe : std_logic;
- signal period_l_wr_strobe : std_logic;
- signal read_mux_out : std_logic_vector(15 downto 0);
- signal status_wr_strobe : std_logic;
- signal timeout_event : std_logic;
- signal timeout_occurred : std_logic;
+ signal clk_en : std_logic;
+ signal control_interrupt_enable : std_logic;
+ signal control_register : std_logic;
+ signal control_wr_strobe : std_logic;
+ signal counter_is_running : std_logic;
+ signal counter_is_zero : std_logic;
+ signal counter_load_value : std_logic_vector(16 downto 0);
+ signal delayed_unxcounter_is_zeroxx0 : std_logic;
+ signal do_start_counter : std_logic;
+ signal do_stop_counter : std_logic;
+ signal force_reload : std_logic;
+ signal internal_counter : std_logic_vector(16 downto 0);
+ signal period_h_wr_strobe : std_logic;
+ signal period_l_wr_strobe : std_logic;
+ signal read_mux_out : std_logic_vector(15 downto 0);
+ signal status_wr_strobe : std_logic;
+ signal timeout_event : std_logic;
+ signal timeout_occurred : std_logic;
begin
clk_en <= std_logic'('1');
process (clk, reset_n)
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
index ff04a90d2b..e6864d98a9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
@@ -1,24 +1,24 @@
- component qsys_unb2b_minimal_timer_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- irq : out std_logic; -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
- writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
- readdata : out std_logic_vector(15 downto 0); -- readdata
- chipselect : in std_logic := 'X'; -- chipselect
- write_n : in std_logic := 'X' -- write_n
- );
- end component qsys_unb2b_minimal_timer_0;
+component qsys_unb2b_minimal_timer_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ irq : out std_logic; -- irq
+ reset_n : in std_logic := 'X'; -- reset_n
+ address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
+ writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
+ readdata : out std_logic_vector(15 downto 0); -- readdata
+ chipselect : in std_logic := 'X'; -- chipselect
+ write_n : in std_logic := 'X' -- write_n
+ );
+end component qsys_unb2b_minimal_timer_0;
- u0 : component qsys_unb2b_minimal_timer_0
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- writedata => CONNECTED_TO_writedata, -- .writedata
- readdata => CONNECTED_TO_readdata, -- .readdata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write_n => CONNECTED_TO_write_n -- .write_n
- );
+u0 : component qsys_unb2b_minimal_timer_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ irq => CONNECTED_TO_irq, -- irq.irq
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ address => CONNECTED_TO_address, -- s1.address
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ readdata => CONNECTED_TO_readdata, -- .readdata
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ write_n => CONNECTED_TO_write_n -- .write_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
index 514ae4a748..9f9849ac84 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, unb2b_jesd_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb2b_jesd_node3 is
generic (
@@ -45,7 +45,7 @@ entity unb2b_jesd_node3 is
);
port (
-- GENERAL
--- CLK : IN STD_LOGIC; -- System Clock
+ -- CLK : IN STD_LOGIC; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
INTA : inout std_logic; -- FPGA interconnect line
@@ -82,49 +82,49 @@ end unb2b_jesd_node3;
architecture str of unb2b_jesd_node3 is
begin
u_revision : entity unb2b_jesd_lib.unb2b_jesd
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_technology => g_technology,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- GENERAL
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- GENERAL
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
- -- 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED,
+ QSFP_LED => QSFP_LED,
- -- JESD signals
- jesd204_rx_serial_data => jesd204_rx_serial_data,
- jesd204_sync_n_out => jesd204_sync_n_out,
- jesd204_rx_sysref => jesd204_rx_sysref,
- jesd204_device_clk => jesd204_device_clk
- );
+ -- JESD signals
+ jesd204_rx_serial_data => jesd204_rx_serial_data,
+ jesd204_sync_n_out => jesd204_sync_n_out,
+ jesd204_rx_sysref => jesd204_rx_sysref,
+ jesd204_device_clk => jesd204_device_clk
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
index 91849daf0f..20491e1e8f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2b_jesd_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2b_jesd_pkg.all;
entity mmm_unb2b_jesd is
generic (
@@ -134,33 +134,42 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -333,56 +342,56 @@ begin
reg_diag_data_buf_jesd_read_export => reg_diag_data_buf_jesd_mosi.rd,
reg_diag_data_buf_jesd_readdata_export => reg_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
- -- connections to the JESD IP:
-
- --altjesd_reset_seq_irq_irq =>
- altjesd_reset_seq_pll_locked_in_reset1_dsrt_qual => i_reset_n,
- --altjesd_reset_seq_pll_reset_reset =>
- altjesd_reset_seq_reset_in0_reset => mm_rst,
- altjesd_reset_seq_rx_xcvr_ready_in_reset5_dsrt_qual => '1',
- altjesd_reset_seq_tx_xcvr_ready_in_reset2_dsrt_qual => rx_xcvr_ready_in,
- --altjesd_rx_csr_cf_export =>
- --altjesd_rx_csr_cs_export =>
- --altjesd_rx_csr_f_export =>
- --altjesd_rx_csr_hd_export =>
- --altjesd_rx_csr_k_export =>
- --altjesd_rx_csr_l_export =>
- altjesd_rx_csr_lane_powerdown_export => rx_csr_lane_powerdown,
- --altjesd_rx_csr_m_export =>
- --altjesd_rx_csr_n_export =>
- --altjesd_rx_csr_np_export =>
- --altjesd_rx_csr_rx_testmode_export =>
- --altjesd_rx_csr_s_export =>
- altjesd_rx_dev_sync_n_export => jesd204_sync_n_out,
- altjesd_rx_jesd204_rx_dlb_data_export => (others => '0'),
- altjesd_rx_jesd204_rx_dlb_data_valid_export => (others => '0'),
- altjesd_rx_jesd204_rx_dlb_disperr_export => (others => '0'),
- altjesd_rx_jesd204_rx_dlb_errdetect_export => (others => '0'),
- altjesd_rx_jesd204_rx_dlb_kchar_data_export => (others => '0'),
- altjesd_rx_jesd204_rx_frame_error_export => '0',
- altjesd_rx_jesd204_rx_int_irq => jesd204_rx_link_error,
- altjesd_rx_jesd204_rx_link_data => jesd204_rx_link_data,
- altjesd_rx_jesd204_rx_link_valid => jesd204_rx_link_valid,
- altjesd_rx_jesd204_rx_link_ready => jesd204_rx_link_ready,
- altjesd_rx_rx_serial_data_rx_serial_data(0) => jesd204_rx_serial_data,
- altjesd_rx_rxlink_rst_n_reset_n => rx_link_rst_n,
- altjesd_ss_rx_link_reset_out_reset_reset_n => rx_link_rst_n,
- --altjesd_ss_rx_frame_reset_out_reset_reset_n =>
- --altjesd_rx_rxphy_clk_export =>
- --altjesd_rx_sof_export =>
- --altjesd_rx_somf_export =>
- altjesd_rx_sysref_export => jesd204_rx_sysref,
- --altjesd_ss_rx_corepll_locked_export =>
- --altjesd_ss_rx_xcvr_reset_control_pll_powerdown_pll_powerdown =>
- altjesd_ss_rx_xcvr_reset_control_rx_ready_rx_ready => xcvr_rst_ctrl_rx_ready,
- device_clk_clk => jesd204_device_clk,
- device_clk_reset_reset_n => '1',
- frame_clk_clk => frame_clk,
- pll_out_frame_clk_clk => frame_clk,
- frame_clk_reset_reset_n => '1',
- link_clk_clk => link_clk,
- pll_out_link_clk_clk => link_clk,
- link_clk_reset_reset_n => '1'
- );
+ -- connections to the JESD IP:
+
+ --altjesd_reset_seq_irq_irq =>
+ altjesd_reset_seq_pll_locked_in_reset1_dsrt_qual => i_reset_n,
+ --altjesd_reset_seq_pll_reset_reset =>
+ altjesd_reset_seq_reset_in0_reset => mm_rst,
+ altjesd_reset_seq_rx_xcvr_ready_in_reset5_dsrt_qual => '1',
+ altjesd_reset_seq_tx_xcvr_ready_in_reset2_dsrt_qual => rx_xcvr_ready_in,
+ --altjesd_rx_csr_cf_export =>
+ --altjesd_rx_csr_cs_export =>
+ --altjesd_rx_csr_f_export =>
+ --altjesd_rx_csr_hd_export =>
+ --altjesd_rx_csr_k_export =>
+ --altjesd_rx_csr_l_export =>
+ altjesd_rx_csr_lane_powerdown_export => rx_csr_lane_powerdown,
+ --altjesd_rx_csr_m_export =>
+ --altjesd_rx_csr_n_export =>
+ --altjesd_rx_csr_np_export =>
+ --altjesd_rx_csr_rx_testmode_export =>
+ --altjesd_rx_csr_s_export =>
+ altjesd_rx_dev_sync_n_export => jesd204_sync_n_out,
+ altjesd_rx_jesd204_rx_dlb_data_export => (others => '0'),
+ altjesd_rx_jesd204_rx_dlb_data_valid_export => (others => '0'),
+ altjesd_rx_jesd204_rx_dlb_disperr_export => (others => '0'),
+ altjesd_rx_jesd204_rx_dlb_errdetect_export => (others => '0'),
+ altjesd_rx_jesd204_rx_dlb_kchar_data_export => (others => '0'),
+ altjesd_rx_jesd204_rx_frame_error_export => '0',
+ altjesd_rx_jesd204_rx_int_irq => jesd204_rx_link_error,
+ altjesd_rx_jesd204_rx_link_data => jesd204_rx_link_data,
+ altjesd_rx_jesd204_rx_link_valid => jesd204_rx_link_valid,
+ altjesd_rx_jesd204_rx_link_ready => jesd204_rx_link_ready,
+ altjesd_rx_rx_serial_data_rx_serial_data(0) => jesd204_rx_serial_data,
+ altjesd_rx_rxlink_rst_n_reset_n => rx_link_rst_n,
+ altjesd_ss_rx_link_reset_out_reset_reset_n => rx_link_rst_n,
+ --altjesd_ss_rx_frame_reset_out_reset_reset_n =>
+ --altjesd_rx_rxphy_clk_export =>
+ --altjesd_rx_sof_export =>
+ --altjesd_rx_somf_export =>
+ altjesd_rx_sysref_export => jesd204_rx_sysref,
+ --altjesd_ss_rx_corepll_locked_export =>
+ --altjesd_ss_rx_xcvr_reset_control_pll_powerdown_pll_powerdown =>
+ altjesd_ss_rx_xcvr_reset_control_rx_ready_rx_ready => xcvr_rst_ctrl_rx_ready,
+ device_clk_clk => jesd204_device_clk,
+ device_clk_reset_reset_n => '1',
+ frame_clk_clk => frame_clk,
+ pll_out_frame_clk_clk => frame_clk,
+ frame_clk_reset_reset_n => '1',
+ link_clk_clk => link_clk,
+ pll_out_link_clk_clk => link_clk,
+ link_clk_reset_reset_n => '1'
+ );
end generate;
end str;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
index fd4dfd48d2..b04a5b0081 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
@@ -20,198 +20,198 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2b_jesd_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v14 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+ -----------------------------------------------------------------------------
-component qsys_unb2b_jesd is
- port (
- altjesd_reset_seq_irq_irq : out std_logic; -- irq
- altjesd_reset_seq_pll_locked_in_reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
- altjesd_reset_seq_pll_reset_reset : out std_logic; -- reset
- altjesd_reset_seq_reset_in0_reset : in std_logic := 'X'; -- reset
- altjesd_reset_seq_rx_xcvr_ready_in_reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
- altjesd_reset_seq_tx_xcvr_ready_in_reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
- altjesd_rx_csr_cf_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_cs_export : out std_logic_vector(1 downto 0); -- export
- altjesd_rx_csr_f_export : out std_logic_vector(7 downto 0); -- export
- altjesd_rx_csr_hd_export : out std_logic; -- export
- altjesd_rx_csr_k_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_l_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_lane_powerdown_export : out std_logic_vector(0 downto 0); -- export
- altjesd_rx_csr_m_export : out std_logic_vector(7 downto 0); -- export
- altjesd_rx_csr_n_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_np_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_rx_testmode_export : out std_logic_vector(3 downto 0); -- export
- altjesd_rx_csr_s_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_dev_sync_n_export : out std_logic; -- export
- altjesd_rx_jesd204_rx_dlb_data_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_data_valid_export : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_disperr_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_errdetect_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_kchar_data_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_frame_error_export : in std_logic := 'X'; -- export
- altjesd_rx_jesd204_rx_int_irq : out std_logic; -- irq
- altjesd_rx_jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- altjesd_rx_jesd204_rx_link_valid : out std_logic; -- valid
- altjesd_rx_jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- altjesd_rx_rx_serial_data_rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- altjesd_rx_rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- altjesd_rx_rxphy_clk_export : out std_logic_vector(0 downto 0); -- export
- altjesd_rx_sof_export : out std_logic_vector(3 downto 0); -- export
- altjesd_rx_somf_export : out std_logic_vector(3 downto 0); -- export
- altjesd_rx_sysref_export : in std_logic := 'X'; -- export
- altjesd_ss_rx_corepll_locked_export : out std_logic; -- export
- altjesd_ss_rx_xcvr_reset_control_pll_powerdown_pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- altjesd_ss_rx_xcvr_reset_control_rx_ready_rx_ready : out std_logic_vector(0 downto 0); -- rx_ready
- altjesd_ss_rx_frame_reset_out_reset_reset_n : out std_logic; -- reset_n
- altjesd_ss_rx_link_reset_out_reset_reset_n : out std_logic; -- reset_n
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- device_clk_clk : in std_logic := 'X'; -- clk
- device_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
- frame_clk_clk : in std_logic := 'X'; -- clk
- frame_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
- link_clk_clk : in std_logic := 'X'; -- clk
- link_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- pll_out_frame_clk_clk : out std_logic; -- clk
- pll_out_link_clk_clk : out std_logic; -- clk
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(5 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_unb2b_jesd;
+ component qsys_unb2b_jesd is
+ port (
+ altjesd_reset_seq_irq_irq : out std_logic; -- irq
+ altjesd_reset_seq_pll_locked_in_reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
+ altjesd_reset_seq_pll_reset_reset : out std_logic; -- reset
+ altjesd_reset_seq_reset_in0_reset : in std_logic := 'X'; -- reset
+ altjesd_reset_seq_rx_xcvr_ready_in_reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
+ altjesd_reset_seq_tx_xcvr_ready_in_reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
+ altjesd_rx_csr_cf_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_cs_export : out std_logic_vector(1 downto 0); -- export
+ altjesd_rx_csr_f_export : out std_logic_vector(7 downto 0); -- export
+ altjesd_rx_csr_hd_export : out std_logic; -- export
+ altjesd_rx_csr_k_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_l_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_lane_powerdown_export : out std_logic_vector(0 downto 0); -- export
+ altjesd_rx_csr_m_export : out std_logic_vector(7 downto 0); -- export
+ altjesd_rx_csr_n_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_np_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_rx_testmode_export : out std_logic_vector(3 downto 0); -- export
+ altjesd_rx_csr_s_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_dev_sync_n_export : out std_logic; -- export
+ altjesd_rx_jesd204_rx_dlb_data_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_dlb_data_valid_export : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_dlb_disperr_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_dlb_errdetect_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_dlb_kchar_data_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_frame_error_export : in std_logic := 'X'; -- export
+ altjesd_rx_jesd204_rx_int_irq : out std_logic; -- irq
+ altjesd_rx_jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ altjesd_rx_jesd204_rx_link_valid : out std_logic; -- valid
+ altjesd_rx_jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ altjesd_rx_rx_serial_data_rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ altjesd_rx_rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ altjesd_rx_rxphy_clk_export : out std_logic_vector(0 downto 0); -- export
+ altjesd_rx_sof_export : out std_logic_vector(3 downto 0); -- export
+ altjesd_rx_somf_export : out std_logic_vector(3 downto 0); -- export
+ altjesd_rx_sysref_export : in std_logic := 'X'; -- export
+ altjesd_ss_rx_corepll_locked_export : out std_logic; -- export
+ altjesd_ss_rx_xcvr_reset_control_pll_powerdown_pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ altjesd_ss_rx_xcvr_reset_control_rx_ready_rx_ready : out std_logic_vector(0 downto 0); -- rx_ready
+ altjesd_ss_rx_frame_reset_out_reset_reset_n : out std_logic; -- reset_n
+ altjesd_ss_rx_link_reset_out_reset_reset_n : out std_logic; -- reset_n
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ device_clk_clk : in std_logic := 'X'; -- clk
+ device_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
+ frame_clk_clk : in std_logic := 'X'; -- clk
+ frame_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
+ link_clk_clk : in std_logic := 'X'; -- clk
+ link_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ pll_out_frame_clk_clk : out std_logic; -- clk
+ pll_out_link_clk_clk : out std_logic; -- clk
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_unb2b_jesd;
end qsys_unb2b_jesd_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
index 91de0e9f27..7f33484855 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb2b_jesd is
generic (
@@ -46,7 +46,7 @@ entity unb2b_jesd is
);
port (
-- GENERAL
--- CLK : IN STD_LOGIC; -- System Clock
+ -- CLK : IN STD_LOGIC; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
INTA : inout std_logic; -- FPGA interconnect line
@@ -183,212 +183,212 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => st_pps,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => st_pps,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2b_jesd
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- --
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
-
- jesd204_rx_serial_data => jesd204_rx_serial_data,
- jesd204_sync_n_out => jesd204_sync_n_out,
- jesd204_rx_link_error => jesd204_rx_link_error,
- jesd204_rx_link_data => jesd204_rx_link_data,
- jesd204_rx_link_valid => jesd204_rx_link_valid,
- jesd204_rx_link_ready => jesd204_rx_link_ready,
- jesd204_rx_sysref => jesd204_rx_sysref_n,
- jesd204_device_clk => st_clk
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ --
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+
+ jesd204_rx_serial_data => jesd204_rx_serial_data,
+ jesd204_sync_n_out => jesd204_sync_n_out,
+ jesd204_rx_link_error => jesd204_rx_link_error,
+ jesd204_rx_link_data => jesd204_rx_link_data,
+ jesd204_rx_link_valid => jesd204_rx_link_valid,
+ jesd204_rx_link_ready => jesd204_rx_link_ready,
+ jesd204_rx_sysref => jesd204_rx_sysref_n,
+ jesd204_device_clk => st_clk
+ );
CLK <= jesd204_device_clk;
--PPS <= jesd204_rx_sysref;
@@ -403,26 +403,26 @@ begin
end generate;
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => 1,
- g_data_w => 32,
- g_buf_nof_data => 16384, -- 8192,
- g_buf_use_sync => true, -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- g_use_rx_seq => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => mm_rst,
- dp_clk => st_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
- ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
- reg_data_buf_mosi => reg_diag_data_buf_jesd_mosi,
- reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
-
- in_sosi_arr => diag_data_buf_snk_in_arr,
- in_sync => st_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => 1,
+ g_data_w => 32,
+ g_buf_nof_data => 16384, -- 8192,
+ g_buf_use_sync => true, -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ g_use_rx_seq => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => mm_rst,
+ dp_clk => st_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
+
+ in_sosi_arr => diag_data_buf_snk_in_arr,
+ in_sync => st_pps
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
index ec0e76432a..dfc6a8483c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
@@ -43,20 +43,20 @@
--
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use i2c_lib.i2c_dev_unb2b_pkg.all;
-use i2c_lib.i2c_commander_unb2b_pmbus_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use i2c_lib.i2c_dev_unb2b_pkg.all;
+ use i2c_lib.i2c_commander_unb2b_pmbus_pkg.all;
entity tb_unb2b_minimal is
- generic (
- g_design_name : string := "unb2b_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2b_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2b_minimal;
architecture tb of tb_unb2b_minimal is
@@ -185,51 +185,51 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
u_pmbus_tcvr0 : entity i2c_lib.dev_pmbus
- generic map (
- g_address => c_pmbus_tcvr0_address
- )
- port map (
- scl => PMBUS_SC,
- sda => PMBUS_SD,
- vout_mode => 13,
- vin => 92,
- vout => 18,
- iout => 12,
- vcap => 0,
- temp => 36
- );
+ generic map (
+ g_address => c_pmbus_tcvr0_address
+ )
+ port map (
+ scl => PMBUS_SC,
+ sda => PMBUS_SD,
+ vout_mode => 13,
+ vin => 92,
+ vout => 18,
+ iout => 12,
+ vcap => 0,
+ temp => 36
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
index a915740dc5..c674e9c74e 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, unb2b_minimal_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2b_minimal_125m is
generic (
@@ -74,46 +74,46 @@ end unb2b_minimal_125m;
architecture str of unb2b_minimal_125m is
begin
u_revision : entity unb2b_minimal_lib.unb2b_minimal
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_technology => g_technology,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
index 94c4b4e447..0afcf1ab29 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2b_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2b_minimal_pkg.all;
entity mmm_unb2b_minimal is
generic (
@@ -114,36 +114,46 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -306,7 +316,7 @@ begin
ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
ram_scrap_read_export => ram_scrap_mosi.rd,
ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
- );
+ );
end generate;
end str;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
index 1470cca511..b70f45006b 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
@@ -20,143 +20,143 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2b_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v14 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_unb2b_minimal is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
- );
- end component qsys_unb2b_minimal;
+ component qsys_unb2b_minimal is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2b_minimal;
end qsys_unb2b_minimal_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
index af68ce0e0a..f9e1e1481f 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
entity unb2b_minimal is
generic (
@@ -163,226 +163,226 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- scrap ram
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- scrap ram
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2b_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- Scrap RAM
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- Scrap RAM
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
index 08f2d036be..6b169ce467 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
@@ -43,20 +43,20 @@
--
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
entity tb_unb2b_minimal is
- generic (
- g_design_name : string := "unb2b_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2b_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2b_minimal;
architecture tb of tb_unb2b_minimal is
@@ -185,51 +185,51 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
u_pmbus_tcvr0 : entity i2c_lib.dev_pmbus
- generic map (
- g_address => c_pmbus_tcvr0_address
- )
- port map (
- scl => PMBUS_SC,
- sda => PMBUS_SD,
- vout_mode => 13,
- vin => 92,
- vout => 18,
- iout => 12,
- vcap => 0,
- temp => 36
- );
+ generic map (
+ g_address => c_pmbus_tcvr0_address
+ )
+ port map (
+ scl => PMBUS_SC,
+ sda => PMBUS_SD,
+ vout_mode => 13,
+ vin => 92,
+ vout => 18,
+ iout => 12,
+ vcap => 0,
+ temp => 36
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
index cf02b0fabc..0028319fec 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2b_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2b_test_10GbE is
end tb_unb2b_test_10GbE;
@@ -29,7 +29,7 @@ end tb_unb2b_test_10GbE;
architecture tb of tb_unb2b_test_10GbE is
begin
u_tb_unb2b_test : entity unb2b_test_lib.tb_unb2b_test
- generic map (
- g_design_name => "unb2b_test_10GbE"
- );
+ generic map (
+ g_design_name => "unb2b_test_10GbE"
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
index b8d21e890e..bc018685b5 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, unb2b_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2b_test_10GbE is
generic (
@@ -66,20 +66,20 @@ entity unb2b_test_10GbE is
BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
--- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
--- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
+ -- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2b_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2b_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2b_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
- -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
- -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -109,78 +109,78 @@ end unb2b_test_10GbE;
architecture str of unb2b_test_10GbE is
begin
u_revision : entity unb2b_test_lib.unb2b_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
-
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
index a5b9924298..e89be39826 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2b_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2b_test_ddr_MB_I_II is
end tb_unb2b_test_ddr_MB_I_II;
@@ -29,8 +29,8 @@ end tb_unb2b_test_ddr_MB_I_II;
architecture tb of tb_unb2b_test_ddr_MB_I_II is
begin
u_tb_unb2b_test : entity unb2b_test_lib.tb_unb2b_test
- generic map (
- g_design_name => "unb2b_test_ddr_MB_I_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2b_test_ddr_MB_I_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
index 150e0d6304..d0255f5d2e 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, unb2b_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2b_test_ddr_MB_I_II is
generic (
@@ -86,56 +86,56 @@ end unb2b_test_ddr_MB_I_II;
architecture str of unb2b_test_ddr_MB_I_II is
begin
u_revision : entity unb2b_test_lib.unb2b_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index ab0300e724..85759a2e1e 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb2b_test_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
-use work.unb2b_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb2b_test_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use work.unb2b_test_pkg.all;
entity mmm_unb2b_test is
generic (
@@ -235,16 +235,16 @@ architecture str of mmm_unb2b_test is
constant c_ram_diag_databuffer_ddr_addr_w : natural := ceil_log2(2 * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
--- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2b_board_peripherals_mm_reg_default
--- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
---
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
---
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
+ -- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2b_board_peripherals_mm_reg_default
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
-- tr_10GbE
constant c_reg_tr_10GbE_adr_w : natural := func_tech_mac_10g_csr_addr_w(g_technology);
@@ -285,113 +285,153 @@ begin
eth1g_eth0_mm_rst <= mm_rst;
eth1g_eth1_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
-
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
-
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
-
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
-
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
-
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
-
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
-
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-
- u_mm_file_reg_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
- u_mm_file_ram_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
- u_mm_file_reg_diag_tx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
-
- u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
- u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
- u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
-
--- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
---
--- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
---
--- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
-
- u_mm_file_reg_bsn_monitor_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
- u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
- u_mm_file_ram_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
- u_mm_file_reg_diag_rx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
- u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
- u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
-
- u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
-
- u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ u_mm_file_reg_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+ u_mm_file_ram_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
+ u_mm_file_reg_diag_tx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
+
+ u_mm_file_reg_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+ u_mm_file_ram_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+ u_mm_file_reg_diag_tx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+
+ -- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+ --
+ -- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
+ --
+ -- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
+
+ u_mm_file_reg_bsn_monitor_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
+ u_mm_file_reg_bsn_monitor_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
+ u_mm_file_ram_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
+ u_mm_file_reg_diag_rx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+ u_mm_file_ram_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+ u_mm_file_reg_diag_rx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+
+ u_mm_file_reg_io_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+ u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+ u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+ u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+ u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_reg_io_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+ u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+ u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+ u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+ u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
- u_mm_file_reg_eth1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
-
- u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
- port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
- u_mm_file_reg_tr_10GbE_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
- u_mm_file_reg_tr_10GbE_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
-
- u_mm_file_reg_eth10g_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
- port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
- u_mm_file_reg_eth10g_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
- port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
- u_mm_file_reg_eth10g_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
- port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
+ u_mm_file_reg_eth0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
+ u_mm_file_reg_eth1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
+ port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
+
+ u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
+ u_mm_file_reg_tr_10GbE_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
+ u_mm_file_reg_tr_10GbE_back1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
+
+ u_mm_file_reg_eth10g_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
+ u_mm_file_reg_eth10g_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
+ port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
+ u_mm_file_reg_eth10g_back1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
+ port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -416,10 +456,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_eth0_reg_mosi, i_eth1g_eth0_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
- else
- eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
- end if;
+ eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
+ else
+ eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -647,32 +687,32 @@ begin
reg_eth10g_back1_read_export => reg_eth10g_back1_mosi.rd,
reg_eth10g_back1_readdata_export => reg_eth10g_back1_miso.rddata(c_word_w - 1 downto 0),
--- -- the_reg_dp_offload_tx_1GbE
--- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
--- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
--- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_tx_1GbE_hdr_dat
--- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_rx_1GbE_hdr_dat
--- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- -- the_reg_dp_offload_tx_1GbE
+ -- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_tx_1GbE_hdr_dat
+ -- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_rx_1GbE_hdr_dat
+ -- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_1gbe_reset_export => OPEN,
reg_bsn_monitor_1gbe_clk_export => OPEN,
@@ -770,21 +810,21 @@ begin
reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
index 02021567e2..b33806c247 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2b_test_pkg is
-----------------------------------------------------------------------------
@@ -28,361 +28,361 @@ package qsys_unb2b_test_pkg is
-- $HDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
-----------------------------------------------------------------------------
- component qsys_unb2b_test is
- port (
- avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
- avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
- avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
- avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
- avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
- avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
- avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
- avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
- avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
- avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
- avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
- avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
- avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
- avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
- avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
- avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
- avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
- avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
- avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
- avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
- clk_clk : in std_logic := '0'; -- clk.clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
- pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
- pio_pps_read_export : out std_logic; -- pio_pps_read.export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
- pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
- pio_pps_write_export : out std_logic; -- pio_pps_write.export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
- pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
- pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
- pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
- pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
- pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
- ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
- ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
- ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
- ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
- reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
- reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
- reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
- reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- reg_diag_data_buffer_10gbe_address.export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
- reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
- reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
- reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
- reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
- reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
- reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
- reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
- reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
- reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
- reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
- reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
- reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back0_address.export
- reg_eth10g_back0_clk_export : out std_logic; -- reg_eth10g_back0_clk.export
- reg_eth10g_back0_read_export : out std_logic; -- reg_eth10g_back0_read.export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back0_readdata.export
- reg_eth10g_back0_reset_export : out std_logic; -- reg_eth10g_back0_reset.export
- reg_eth10g_back0_write_export : out std_logic; -- reg_eth10g_back0_write.export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back0_writedata.export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back1_address.export
- reg_eth10g_back1_clk_export : out std_logic; -- reg_eth10g_back1_clk.export
- reg_eth10g_back1_read_export : out std_logic; -- reg_eth10g_back1_read.export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back1_readdata.export
- reg_eth10g_back1_reset_export : out std_logic; -- reg_eth10g_back1_reset.export
- reg_eth10g_back1_write_export : out std_logic; -- reg_eth10g_back1_write.export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back1_writedata.export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- reg_eth10g_qsfp_ring_address.export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- reg_eth10g_qsfp_ring_clk.export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- reg_eth10g_qsfp_ring_read.export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_qsfp_ring_readdata.export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- reg_eth10g_qsfp_ring_reset.export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- reg_eth10g_qsfp_ring_write.export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_qsfp_ring_writedata.export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- reg_fpga_temp_sens_address.export
- reg_fpga_temp_sens_clk_export : out std_logic; -- reg_fpga_temp_sens_clk.export
- reg_fpga_temp_sens_read_export : out std_logic; -- reg_fpga_temp_sens_read.export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_temp_sens_readdata.export
- reg_fpga_temp_sens_reset_export : out std_logic; -- reg_fpga_temp_sens_reset.export
- reg_fpga_temp_sens_write_export : out std_logic; -- reg_fpga_temp_sens_write.export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_temp_sens_writedata.export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- reg_fpga_voltage_sens_address.export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- reg_fpga_voltage_sens_clk.export
- reg_fpga_voltage_sens_read_export : out std_logic; -- reg_fpga_voltage_sens_read.export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_voltage_sens_readdata.export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- reg_fpga_voltage_sens_reset.export
- reg_fpga_voltage_sens_write_export : out std_logic; -- reg_fpga_voltage_sens_write.export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_voltage_sens_writedata.export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
- reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
- reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
- reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
- reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
- reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
- reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
- reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
- reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
- reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
- reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
- reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
- reg_remu_read_export : out std_logic; -- reg_remu_read.export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
- reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
- reg_remu_write_export : out std_logic; -- reg_remu_write.export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
- reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
- reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
- reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
- reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- reg_unb_pmbus_address.export
- reg_unb_pmbus_clk_export : out std_logic; -- reg_unb_pmbus_clk.export
- reg_unb_pmbus_read_export : out std_logic; -- reg_unb_pmbus_read.export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_pmbus_readdata.export
- reg_unb_pmbus_reset_export : out std_logic; -- reg_unb_pmbus_reset.export
- reg_unb_pmbus_write_export : out std_logic; -- reg_unb_pmbus_write.export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_pmbus_writedata.export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- reg_unb_sens_address.export
- reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
- reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
- reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
- reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
- reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
- reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
- reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
- reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
- reset_reset_n : in std_logic := '0'; -- reset.reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
- rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
- rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
- rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
- rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
- );
- end component qsys_unb2b_test;
+ component qsys_unb2b_test is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
+ avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
+ avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
+ avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
+ avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
+ avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
+ avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
+ avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
+ avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
+ avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
+ avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
+ avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
+ avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
+ avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
+ avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
+ avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
+ avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
+ avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
+ avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
+ avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
+ clk_clk : in std_logic := '0'; -- clk.clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
+ pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
+ pio_pps_read_export : out std_logic; -- pio_pps_read.export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
+ pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
+ pio_pps_write_export : out std_logic; -- pio_pps_write.export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
+ pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
+ pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
+ pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
+ pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
+ pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- reg_diag_data_buffer_10gbe_address.export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
+ reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
+ reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
+ reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
+ reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
+ reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
+ reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
+ reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
+ reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
+ reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
+ reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back0_address.export
+ reg_eth10g_back0_clk_export : out std_logic; -- reg_eth10g_back0_clk.export
+ reg_eth10g_back0_read_export : out std_logic; -- reg_eth10g_back0_read.export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back0_readdata.export
+ reg_eth10g_back0_reset_export : out std_logic; -- reg_eth10g_back0_reset.export
+ reg_eth10g_back0_write_export : out std_logic; -- reg_eth10g_back0_write.export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back0_writedata.export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back1_address.export
+ reg_eth10g_back1_clk_export : out std_logic; -- reg_eth10g_back1_clk.export
+ reg_eth10g_back1_read_export : out std_logic; -- reg_eth10g_back1_read.export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back1_readdata.export
+ reg_eth10g_back1_reset_export : out std_logic; -- reg_eth10g_back1_reset.export
+ reg_eth10g_back1_write_export : out std_logic; -- reg_eth10g_back1_write.export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back1_writedata.export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- reg_eth10g_qsfp_ring_address.export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- reg_eth10g_qsfp_ring_clk.export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- reg_eth10g_qsfp_ring_read.export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_qsfp_ring_readdata.export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- reg_eth10g_qsfp_ring_reset.export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- reg_eth10g_qsfp_ring_write.export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_qsfp_ring_writedata.export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- reg_fpga_temp_sens_address.export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- reg_fpga_temp_sens_clk.export
+ reg_fpga_temp_sens_read_export : out std_logic; -- reg_fpga_temp_sens_read.export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_temp_sens_readdata.export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- reg_fpga_temp_sens_reset.export
+ reg_fpga_temp_sens_write_export : out std_logic; -- reg_fpga_temp_sens_write.export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_temp_sens_writedata.export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- reg_fpga_voltage_sens_address.export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- reg_fpga_voltage_sens_clk.export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- reg_fpga_voltage_sens_read.export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_voltage_sens_readdata.export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- reg_fpga_voltage_sens_reset.export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- reg_fpga_voltage_sens_write.export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_voltage_sens_writedata.export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
+ reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
+ reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
+ reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
+ reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
+ reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
+ reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
+ reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
+ reg_remu_read_export : out std_logic; -- reg_remu_read.export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
+ reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
+ reg_remu_write_export : out std_logic; -- reg_remu_write.export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- reg_unb_pmbus_address.export
+ reg_unb_pmbus_clk_export : out std_logic; -- reg_unb_pmbus_clk.export
+ reg_unb_pmbus_read_export : out std_logic; -- reg_unb_pmbus_read.export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_pmbus_readdata.export
+ reg_unb_pmbus_reset_export : out std_logic; -- reg_unb_pmbus_reset.export
+ reg_unb_pmbus_write_export : out std_logic; -- reg_unb_pmbus_write.export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_pmbus_writedata.export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- reg_unb_sens_address.export
+ reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
+ reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
+ reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
+ reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
+ reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
+ reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
+ reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
+ reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
+ reset_reset_n : in std_logic := '0'; -- reset.reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
+ rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
+ rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
+ rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
+ rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
+ );
+ end component qsys_unb2b_test;
end qsys_unb2b_test_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
index db643432f2..39bf73dd75 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, unb2b_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb2b_test_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb2b_test_pkg.all;
+ use technology_lib.technology_pkg.all;
entity udp_stream is
generic (
@@ -102,14 +102,15 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable (disabled by default)
+ '0', -- enable_sync
+ TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
constant c_nof_crc_words : natural := 1;
constant c_max_nof_words_per_block : natural := g_bg_block_size;
@@ -150,127 +151,127 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl
--- g_use_tx_seq => TRUE
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ -- g_use_tx_seq => TRUE
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
- --reg_mosi => reg_dp_offload_tx_mosi,
- --reg_miso => reg_dp_offload_tx_miso,
- --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ --reg_mosi => reg_dp_offload_tx_mosi,
+ --reg_miso => reg_dp_offload_tx_miso,
+ --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
@@ -291,52 +292,52 @@ begin
end generate;
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
index 5886a9aef1..626ae4a3f1 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb2b_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb2b_test_pkg.all;
entity unb2b_test is
generic (
@@ -315,10 +315,10 @@ architecture str of unb2b_test is
signal i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
signal i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
- -- SIGNAL i_RING_TX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_RING_RX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_TX : t_unb2b_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_RX : t_unb2b_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_TX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_RX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_TX : t_unb2b_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_RX : t_unb2b_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
signal serial_10G_tx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0) := (others => '0');
signal serial_10G_rx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0);
@@ -351,13 +351,13 @@ architecture str of unb2b_test is
signal reg_diag_tx_seq_10GbE_mosi : t_mem_mosi;
signal reg_diag_tx_seq_10GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
---
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
+ --
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
signal reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
signal reg_bsn_monitor_1GbE_miso : t_mem_miso;
@@ -434,380 +434,380 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => sel_a_b(g_sim,c_unb2b_board_mm_clk_freq_25M,c_unb2b_board_mm_clk_freq_125M),
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_udp_offload => c_use_1GbE,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- g_dp_clk_use_pll => true,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
-
- ext_clk200 => ext_clk200,
- ext_rst200 => ext_rst200,
-
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_mm_rst => eth1g_eth0_mm_rst,
- eth1g_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_tse_miso => eth1g_eth0_tse_miso,
- eth1g_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_reg_miso => eth1g_eth0_reg_miso,
- eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => sel_a_b(g_sim,c_unb2b_board_mm_clk_freq_25M,c_unb2b_board_mm_clk_freq_125M),
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_udp_offload => c_use_1GbE,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ g_dp_clk_use_pll => true,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+
+ ext_clk200 => ext_clk200,
+ ext_rst200 => ext_rst200,
+
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2b_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_technology => g_technology,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr,
- g_nof_streams_1GbE => c_unb2b_board_nof_eth,
- g_nof_streams_qsfp => c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w,
- g_nof_streams_ring => 24, -- c_unb2b_board_tr_ring.nof_bus * c_unb2b_board_tr_ring.bus_w,
- g_nof_streams_back0 => 24, -- c_unb2b_board_tr_back.bus_w,
- g_nof_streams_back1 => 24 -- c_unb2b_board_tr_back.bus_w
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
- eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
- eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
- eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g ch1
- eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
- eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
- eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
- eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
- eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
- eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
- eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
- eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- block gen
- ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
- reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
- reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
-
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
--- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
---
--- -- dp_offload_rx
--- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-
- -- bsn
- reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
-
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- 10GbE
-
- reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
-
- reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
- reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
-
- reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
- reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
-
- -- eth10g status
- reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
-
- reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_back0_miso => reg_eth10g_back0_miso,
-
- reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
- reg_eth10g_back1_miso => reg_eth10g_back1_miso,
-
- -- DDR4 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR4 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
- );
-
- gen_udp_stream_1GbE : if c_use_1GbE = true generate
- u_udp_stream_1GbE : entity work.udp_stream
generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_1GbE,
- g_data_w => c_data_w_32,
- g_bg_block_size => c_def_1GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_1GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_1GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => true
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_technology => g_technology,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_nof_streams_1GbE => c_unb2b_board_nof_eth,
+ g_nof_streams_qsfp => c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w,
+ g_nof_streams_ring => 24, -- c_unb2b_board_tr_ring.nof_bus * c_unb2b_board_tr_ring.bus_w,
+ g_nof_streams_back0 => 24, -- c_unb2b_board_tr_back.bus_w,
+ g_nof_streams_back1 => 24 -- c_unb2b_board_tr_back.bus_w
)
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g ch1
+ eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
+ eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
+ eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
+ eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
+ eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
+ eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
+ eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
+ eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- block gen
+ ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
+
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-- dp_offload_tx
--- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
-
- -- dp_offload_rx
--- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+ -- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ --
+ -- -- dp_offload_rx
+ -- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
+
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- 10GbE
+
+ reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
+
+ reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
+ reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
+
+ reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
+ reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
+
+ -- eth10g status
+ reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
+
+ reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_back0_miso => reg_eth10g_back0_miso,
+
+ reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
+ reg_eth10g_back1_miso => reg_eth10g_back1_miso,
+
+ -- DDR4 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR4 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
+
+ gen_udp_stream_1GbE : if c_use_1GbE = true generate
+ u_udp_stream_1GbE : entity work.udp_stream
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_1GbE,
+ g_data_w => c_data_w_32,
+ g_bg_block_size => c_def_1GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_1GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_1GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+
+ -- dp_offload_tx
+ -- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+
+ -- dp_offload_rx
+ -- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ );
end generate;
-----------------------------------------------------------------------------
@@ -824,87 +824,87 @@ begin
gen_udp_stream_10GbE : if c_use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_bg_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ID => ID,
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- loopback:
- --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
- --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
-
- -- connect to dp_offload:
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ID => ID,
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+ -- loopback:
+ --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
+ --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ -- connect to dp_offload:
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
u_tr_10GbE_qsfp_and_ring: entity unb2b_board_10gbe_lib.unb2b_board_10gbe -- QSFP and Ring lines
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk => SA_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
- reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
-
- serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
- serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SA_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+ reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+
+ serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
+ serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
+ );
gen_qsfp_wires: for i in 0 to c_nof_streams_qsfp - 1 generate
- serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
+ serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
@@ -923,161 +923,161 @@ begin
QSFP_5_TX <= i_QSFP_TX(5);
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_qsfp_arr,
- serial_rx_arr => serial_10G_rx_qsfp_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
-
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
-
- --QSFP_SDA => QSFP_SDA,
- --QSFP_SCL => QSFP_SCL,
- --QSFP_RST => QSFP_RST,
-
- QSFP_LED => QSFP_LED
- );
-
--- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
--- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
--- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
--- END GENERATE;
---
--- i_RING_RX(0) <= RING_0_RX;
--- i_RING_RX(1) <= RING_1_RX;
--- RING_0_TX <= i_RING_TX(0);
--- RING_1_TX <= i_RING_TX(1);
---
--- u_ring_io : ENTITY unb2b_board_lib.unb2b_board_ring_io
--- GENERIC MAP (
--- g_nof_ring_bus => 2--c_nof_ring_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_ring_arr,
--- serial_rx_arr => serial_10G_rx_ring_arr,
--- RING_RX => i_RING_RX,
--- RING_TX => i_RING_TX
--- );
-
--- u_tr_10GbE_back: ENTITY unb2b_board_10gbe_lib.unb2b_board_10gbe -- BACK lines
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_sim_level => 1,
--- g_technology => g_technology,
--- g_nof_macs => c_nof_streams_back0,
--- g_tx_fifo_fill => c_def_10GbE_block_size,
--- g_tx_fifo_size => c_def_10GbE_block_size*2
--- )
--- PORT MAP (
--- tr_ref_clk => SB_CLK,
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
--- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
--- reg_mac_miso => reg_tr_10GbE_back0_miso,
--- reg_eth10g_mosi => reg_eth10g_back0_mosi,
--- reg_eth10g_miso => reg_eth10g_back0_miso,
--- dp_rst => dp_rst,
--- dp_clk => dp_clk,
---
--- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
----- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
---
--- serial_tx_arr => i_serial_10G_tx_back0_arr,
--- serial_rx_arr => i_serial_10G_rx_back0_arr
--- );
---
--- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
--- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
--- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
--- END GENERATE;
--- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
--- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
--- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
--- --END GENERATE;
---
--- u_back_io : ENTITY unb2b_board_lib.unb2b_board_back_io
--- GENERIC MAP (
--- g_nof_back_bus => c_nof_back_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_back_arr,
--- serial_rx_arr => serial_10G_rx_back_arr,
---
--- -- Serial I/O
--- -- back transceivers
--- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
--- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
--- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
--- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
---
--- BCK_SDA => BCK_SDA,
--- BCK_SCL => BCK_SCL,
--- BCK_ERR => BCK_ERR
--- );
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_qsfp_arr,
+ serial_rx_arr => serial_10G_rx_qsfp_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
+
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
+
+ --QSFP_SDA => QSFP_SDA,
+ --QSFP_SCL => QSFP_SCL,
+ --QSFP_RST => QSFP_RST,
+
+ QSFP_LED => QSFP_LED
+ );
+
+ -- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
+ -- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
+ -- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
+ -- END GENERATE;
+ --
+ -- i_RING_RX(0) <= RING_0_RX;
+ -- i_RING_RX(1) <= RING_1_RX;
+ -- RING_0_TX <= i_RING_TX(0);
+ -- RING_1_TX <= i_RING_TX(1);
+ --
+ -- u_ring_io : ENTITY unb2b_board_lib.unb2b_board_ring_io
+ -- GENERIC MAP (
+ -- g_nof_ring_bus => 2--c_nof_ring_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_ring_arr,
+ -- serial_rx_arr => serial_10G_rx_ring_arr,
+ -- RING_RX => i_RING_RX,
+ -- RING_TX => i_RING_TX
+ -- );
+
+ -- u_tr_10GbE_back: ENTITY unb2b_board_10gbe_lib.unb2b_board_10gbe -- BACK lines
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_sim_level => 1,
+ -- g_technology => g_technology,
+ -- g_nof_macs => c_nof_streams_back0,
+ -- g_tx_fifo_fill => c_def_10GbE_block_size,
+ -- g_tx_fifo_size => c_def_10GbE_block_size*2
+ -- )
+ -- PORT MAP (
+ -- tr_ref_clk => SB_CLK,
+ -- mm_rst => mm_rst,
+ -- mm_clk => mm_clk,
+ -- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
+ -- reg_mac_miso => reg_tr_10GbE_back0_miso,
+ -- reg_eth10g_mosi => reg_eth10g_back0_mosi,
+ -- reg_eth10g_miso => reg_eth10g_back0_miso,
+ -- dp_rst => dp_rst,
+ -- dp_clk => dp_clk,
+ --
+ -- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ ---- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ --
+ -- serial_tx_arr => i_serial_10G_tx_back0_arr,
+ -- serial_rx_arr => i_serial_10G_rx_back0_arr
+ -- );
+ --
+ -- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
+ -- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
+ -- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
+ -- END GENERATE;
+ -- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
+ -- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
+ -- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
+ -- --END GENERATE;
+ --
+ -- u_back_io : ENTITY unb2b_board_lib.unb2b_board_back_io
+ -- GENERIC MAP (
+ -- g_nof_back_bus => c_nof_back_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_back_arr,
+ -- serial_rx_arr => serial_10G_rx_back_arr,
+ --
+ -- -- Serial I/O
+ -- -- back transceivers
+ -- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
+ -- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
+ -- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ -- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ --
+ -- BCK_SDA => BCK_SDA,
+ -- BCK_SCL => BCK_SCL,
+ -- BCK_ERR => BCK_ERR
+ -- );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2b_board_ext_clk_freq_200M) -- nof clk cycles to get us period
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
-
- tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
- tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
- rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_unb2b_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+
+ tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
+ rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ );
end generate;
gen_no_udp_stream_10GbE : if c_use_10GbE = false generate
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
end generate;
-----------------------------------------------------------------------------
@@ -1088,156 +1088,156 @@ begin
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_I,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_I_clk200,
- ctlr_rst_out => ddr_I_rst200,
-
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_I,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_I_clk200,
+ ctlr_rst_out => ddr_I_rst200,
+
+ ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
gen_stream_MB_II : if c_use_MB_II = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_II,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_II_REF_CLK,
- ctlr_ref_rst => mb_II_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_II_clk200,
- ctlr_rst_out => ddr_II_rst200,
-
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_II_IN,
- phy4_io => MB_II_IO,
- phy4_ou => MB_II_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_II,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_II_REF_CLK,
+ ctlr_ref_rst => mb_II_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_II_clk200,
+ ctlr_rst_out => ddr_II_rst200,
+
+ ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_II_IN,
+ phy4_io => MB_II_IO,
+ phy4_ou => MB_II_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
end str;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
index 1fbcce3b6d..38d8b2218e 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
@@ -20,37 +20,38 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
package unb2b_test_pkg is
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
+ constant c_hdr_field_arr : t_common_field_arr(
+ c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
diff --git a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
index fbf404947d..881f9e5bcd 100644
--- a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
@@ -43,14 +43,14 @@
--
library IEEE, common_lib, unb2b_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb2b_test is
generic (
@@ -182,142 +182,142 @@ begin
-- DUT
------------------------------------------------------------------------------
u_unb2b_test : entity work.unb2b_test
- generic map (
- g_design_name => g_design_name,
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_sim_model_ddr => g_sim_model_ddr,
- g_ddr_MB_I => c_ddr_MB_I,
- g_ddr_MB_II => c_ddr_MB_II
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => sa_clk,
- SB_CLK => sb_clk,
- BCK_REF_CLK => bck_ref_clk,
-
- -- DDR reference clocks
- MB_I_REF_CLK => mb_I_ref_clk,
- MB_II_REF_CLK => mb_II_ref_clk,
-
- PMBUS_ALERT => '0',
-
- -- Serial I/O
- -- QSFP_0_TX => si_lpbk_0,
- -- QSFP_0_RX => si_lpbk_0,
--- QSFP_1_TX => si_lpbk_1,
--- QSFP_1_RX => si_lpbk_1,
--- QSFP_2_TX => si_lpbk_2,
--- QSFP_2_RX => si_lpbk_2,
--- QSFP_3_TX => si_lpbk_3,
--- QSFP_3_RX => si_lpbk_3,
--- QSFP_4_TX => si_lpbk_4,
--- QSFP_4_RX => si_lpbk_4,
--- QSFP_5_TX => si_lpbk_5,
--- QSFP_5_RX => si_lpbk_5,
---
--- RING_0_TX => si_lpbk_6,
--- RING_0_RX => si_lpbk_6,
--- RING_1_TX => si_lpbk_7,
--- RING_1_RX => si_lpbk_7,
---
--- BCK_TX => si_lpbk_8,
--- BCK_RX => si_lpbk_8,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- -- Leds
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_ddr_MB_I => c_ddr_MB_I,
+ g_ddr_MB_II => c_ddr_MB_II
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+ SB_CLK => sb_clk,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => mb_I_ref_clk,
+ MB_II_REF_CLK => mb_II_ref_clk,
+
+ PMBUS_ALERT => '0',
+
+ -- Serial I/O
+ -- QSFP_0_TX => si_lpbk_0,
+ -- QSFP_0_RX => si_lpbk_0,
+ -- QSFP_1_TX => si_lpbk_1,
+ -- QSFP_1_RX => si_lpbk_1,
+ -- QSFP_2_TX => si_lpbk_2,
+ -- QSFP_2_RX => si_lpbk_2,
+ -- QSFP_3_TX => si_lpbk_3,
+ -- QSFP_3_RX => si_lpbk_3,
+ -- QSFP_4_TX => si_lpbk_4,
+ -- QSFP_4_RX => si_lpbk_4,
+ -- QSFP_5_TX => si_lpbk_5,
+ -- QSFP_5_RX => si_lpbk_5,
+ --
+ -- RING_0_TX => si_lpbk_6,
+ -- RING_0_RX => si_lpbk_6,
+ -- RING_1_TX => si_lpbk_7,
+ -- RING_1_RX => si_lpbk_7,
+ --
+ -- BCK_TX => si_lpbk_8,
+ -- BCK_RX => si_lpbk_8,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ -- Leds
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- UniBoard sensors
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
------------------------------------------------------------------------------
-- UniBoard DDR4
------------------------------------------------------------------------------
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_I
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_I_OU,
- mem4_io => MB_I_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_I
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_I_OU,
+ mem4_io => MB_I_IO
+ );
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_II
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_II_OU,
- mem4_io => MB_II_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_II
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_II_OU,
+ mem4_io => MB_II_IO
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index a23d26634c..10344a9025 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -25,16 +25,16 @@
-- . ctrl_unb2b_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
library IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb2b_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb2b_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb2b_board is
generic (
@@ -335,15 +335,15 @@ begin
i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
u_common_areset_ext : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_ext_clk200,
- out_rst => ext_rst200
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_ext_clk200,
+ out_rst => ext_rst200
+ );
-----------------------------------------------------------------------------
-- xo_ethclk = ETH_CLK
@@ -352,15 +352,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
-- MB_I_REF_CLK --> mb_I_ref_rst
@@ -368,26 +368,26 @@ begin
-----------------------------------------------------------------------------
u_common_areset_mb_I : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_I_REF_CLK,
- out_rst => mb_I_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_I_REF_CLK,
+ out_rst => mb_I_ref_rst
+ );
u_common_areset_mb_II : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_II_REF_CLK,
- out_rst => mb_II_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_II_REF_CLK,
+ out_rst => mb_II_ref_rst
+ );
-----------------------------------------------------------------------------
-- dp_clk + dp_rst generation
@@ -401,29 +401,29 @@ begin
gen_pll: if g_sim = false and g_dp_clk_use_pll = true generate
u_unb2b_board_clk200_pll : entity work.unb2b_board_clk200_pll
+ generic map (
+ g_technology => g_technology,
+ g_use_fpll => true,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ port map (
+ arst => i_mm_rst,
+ clk200 => i_ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => common_areset_in_rst
+ );
+ end generate;
+
+ u_common_areset_dp_rst : entity common_lib.common_areset
generic map (
- g_technology => g_technology,
- g_use_fpll => true,
- g_clk200_phase_shift => g_dp_clk_phase
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
)
port map (
- arst => i_mm_rst,
- clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => common_areset_in_rst
+ in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
);
- end generate;
-
- u_common_areset_dp_rst : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
-----------------------------------------------------------------------------
-- mm_clk
@@ -437,48 +437,48 @@ begin
clk50; -- default
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
- sim_mm_clk <= not sim_mm_clk after g_sim_mm_clk_period / 2;
- mm_locked <= '0', '1' after 70 ns;
+ epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
+ clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
+ sim_mm_clk <= not sim_mm_clk after g_sim_mm_clk_period / 2;
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2b_board_clk125_pll : entity work.unb2b_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => epcs_clk,
+ c1_clk50 => clk50,
+ c2_clk100 => clk100,
+ c3_clk125 => clk125,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2b_board_node_ctrl : entity work.unb2b_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c0_clk20 => epcs_clk,
- c1_clk50 => clk50,
- c2_clk100 => clk100,
- c3_clk125 => clk125,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2b_board_node_ctrl : entity work.unb2b_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-----------------------------------------------------------------------------
-- System info
@@ -486,33 +486,33 @@ begin
cs_sim <= is_true(g_sim);
u_mms_unb2b_board_system_info : entity work.mms_unb2b_board_system_info
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
-- Red LED control
@@ -547,12 +547,12 @@ begin
led_toggle_green <= sel_a_b(g_factory_image = false, led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
-- WDI override
@@ -563,15 +563,15 @@ begin
WDI <= mm_wdi or temp_alarm or wdi_override;
u_unb2b_board_wdi_reg : entity work.unb2b_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
-- Remote upgrade
@@ -580,75 +580,75 @@ begin
-- So there is full control over the memory mapped registers to set start address of the flash
-- and reconfigure from that address.
u_mms_remu: entity remu_lib.mms_remu
- generic map (
- g_technology => g_technology
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
-------------------------------------------------------------------------------
---- EPCS
-------------------------------------------------------------------------------
u_mms_epcs: entity epcs_lib.mms_epcs
- generic map (
- g_technology => g_technology,
- g_protect_addr_range => g_protect_addr_range,
- g_protected_addr_lo => g_protected_addr_lo,
- g_protected_addr_hi => g_protected_addr_hi
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology,
+ g_protect_addr_range => g_protect_addr_range,
+ g_protected_addr_lo => g_protected_addr_lo,
+ g_protected_addr_hi => g_protected_addr_hi
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
------------------------------------------------------------------------------
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_technology => g_technology,
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => dp_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => dp_pps
+ );
------------------------------------------------------------------------------
-- I2C control for UniBoard sensors
@@ -657,74 +657,74 @@ begin
mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_s; -- mm_pulse_ms; ms pulse comes before the end of the I2C frame, this results in an overflow in simulation -- speed up in simulation
u_mms_unb2b_board_sens : entity work.mms_unb2b_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => c_i2c_peripheral_sens,
- g_sens_nof_result => 40,
- g_clk_freq => g_mm_clk_freq,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_sens_mosi,
- reg_miso => reg_unb_sens_miso,
-
- -- i2c bus
- scl => SENS_SC,
- sda => SENS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => c_i2c_peripheral_sens,
+ g_sens_nof_result => 40,
+ g_clk_freq => g_mm_clk_freq,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_sens_mosi,
+ reg_miso => reg_unb_sens_miso,
+
+ -- i2c bus
+ scl => SENS_SC,
+ sda => SENS_SD
+ );
u_mms_unb2b_board_pmbus : entity work.mms_unb2b_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => c_i2c_peripheral_pmbus,
- g_sens_nof_result => 42,
- g_clk_freq => g_mm_clk_freq,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_pmbus_mosi,
- reg_miso => reg_unb_pmbus_miso,
-
- -- i2c bus
- scl => PMBUS_SC,
- sda => PMBUS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => c_i2c_peripheral_pmbus,
+ g_sens_nof_result => 42,
+ g_clk_freq => g_mm_clk_freq,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_pmbus_mosi,
+ reg_miso => reg_unb_pmbus_miso,
+
+ -- i2c bus
+ scl => PMBUS_SC,
+ sda => PMBUS_SD
+ );
u_mms_unb2b_fpga_sens : entity work.mms_unb2b_fpga_sens
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
- mm_start => '1', -- this works
-
- -- Memory-mapped clock domain
- reg_temp_mosi => reg_fpga_temp_sens_mosi,
- reg_temp_miso => reg_fpga_temp_sens_miso,
- reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
- reg_voltage_miso => reg_fpga_voltage_sens_miso,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
+ mm_start => '1', -- this works
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
-- Ethernet 1GbE
@@ -733,18 +733,18 @@ begin
gen_tse_clk_buf: if g_tse_clk_buf = true generate
-- Separate clkbuf for the 1GbE tse_clk:
u_tse_clk_buf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => i_xo_ethclk,
- outclk => i_tse_clk
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => i_xo_ethclk,
+ outclk => i_tse_clk
+ );
end generate;
gen_tse_no_clk_buf: if g_tse_clk_buf = false generate
- i_tse_clk <= i_xo_ethclk;
+ i_tse_clk <= i_xo_ethclk;
end generate;
wire_udp_offload: for i in 0 to g_udp_offload_nof_streams - 1 generate
@@ -769,60 +769,60 @@ begin
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
u_eth : entity eth_lib.eth
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_frm_discard_en => true,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => i_mm_clk, -- use mm_clk direct
+ eth_clk => i_tse_clk, -- 125 MHz clock
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT(0),
+ eth_rxp => ETH_SGIN(0),
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
+ end generate;
+
+ u_ram_scrap : entity common_lib.common_ram_r_w
generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_frm_discard_en => true,
- g_sim => g_sim,
- g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ g_ram => c_ram_scrap
)
port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT(0),
- eth_rxp => ETH_SGIN(0),
-
- -- LED interface
- tse_led => eth1g_led
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ wr_en => ram_scrap_mosi.wr,
+ wr_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
+ wr_dat => ram_scrap_mosi.wrdata(c_ram_scrap.dat_w - 1 downto 0),
+ rd_en => ram_scrap_mosi.rd,
+ rd_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
+ rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w - 1 downto 0),
+ rd_val => ram_scrap_miso.rdval
);
- end generate;
-
- u_ram_scrap : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram_scrap
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- wr_en => ram_scrap_mosi.wr,
- wr_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
- wr_dat => ram_scrap_mosi.wrdata(c_ram_scrap.dat_w - 1 downto 0),
- rd_en => ram_scrap_mosi.rd,
- rd_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
- rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w - 1 downto 0),
- rd_val => ram_scrap_miso.rdval
- );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
index 80d5432cf6..e205ce4a2a 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
@@ -23,10 +23,10 @@
-- Description: See unb2b_board_sens.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_unb2b_board_sens is
generic (
@@ -65,48 +65,48 @@ architecture str of mms_unb2b_board_sens is
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
begin
u_unb2b_board_sens_reg : entity work.unb2b_board_sens_reg
- generic map (
- g_sens_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_sens_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers
- sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- sens_data => sens_data,
+ -- MM registers
+ sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ sens_data => sens_data,
- -- Max temp threshold
- temp_high => temp_high
- );
+ -- Max temp threshold
+ temp_high => temp_high
+ );
u_unb2b_board_sens : entity work.unb2b_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => g_i2c_peripheral,
- g_clk_freq => g_clk_freq,
- g_temp_high => g_temp_high,
- g_sens_nof_result => g_sens_nof_result,
- g_comma_w => g_comma_w
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
- start => mm_start,
- -- i2c bus
- scl => scl,
- sda => sda,
- -- read results
- sens_evt => OPEN,
- sens_err => sens_err,
- sens_data => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => g_i2c_peripheral,
+ g_clk_freq => g_clk_freq,
+ g_temp_high => g_temp_high,
+ g_sens_nof_result => g_sens_nof_result,
+ g_comma_w => g_comma_w
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+ start => mm_start,
+ -- i2c bus
+ scl => scl,
+ sda => sda,
+ -- read results
+ sens_evt => OPEN,
+ sens_err => sens_err,
+ sens_data => sens_data
+ );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
index 690b1507ac..4de647f7ba 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2b_board_system_info is
generic (
@@ -58,7 +58,7 @@ entity mms_unb2b_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb2b_board_system_info;
architecture str of mms_unb2b_board_system_info is
@@ -68,68 +68,69 @@ architecture str of mms_unb2b_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/";
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 13; -- 2^13 = 8192 addresses * 32 bits = 32 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb2b_board_system_info: entity work.unb2b_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb2b_board_system_info_reg: entity work.unb2b_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_technology => g_technology,
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
index 8debc61a00..a85af1b037 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
@@ -23,11 +23,11 @@
-- Description: See unb2b_fpga_sens.vhd
library IEEE, technology_lib, common_lib, fpga_sense_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2b_fpga_sens is
generic (
@@ -55,22 +55,22 @@ end mms_unb2b_fpga_sens;
architecture str of mms_unb2b_fpga_sens is
begin
u_fpga_sense: entity fpga_sense_lib.fpga_sense
- generic map (
- g_technology => g_technology,
- g_sim => g_sim,
- g_temp_high => g_temp_high
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- start_sense => mm_start,
- temp_alarm => temp_alarm,
+ start_sense => mm_start,
+ temp_alarm => temp_alarm,
- reg_temp_mosi => reg_temp_mosi,
- reg_temp_miso => reg_temp_miso,
+ reg_temp_mosi => reg_temp_mosi,
+ reg_temp_miso => reg_temp_miso,
- reg_voltage_store_mosi => reg_voltage_mosi,
- reg_voltage_store_miso => reg_voltage_miso
- );
+ reg_voltage_store_mosi => reg_voltage_mosi,
+ reg_voltage_store_miso => reg_voltage_miso
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
index 4054420d21..1cf453cbca 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_back_io is
generic (
@@ -57,4 +57,4 @@ begin
serial_rx_arr(i * c_unb2b_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
-end;
+ end;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
index f2886ef970..86d3532d9a 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
@@ -21,17 +21,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Purpose: PLL for UniBoard node CLK input @ 125 MHz
--- Description:
--- c0 = 20 MHz
--- c1 = 50 MHz
--- c2 = 100 MHz
--- c3 = 125 MHz
---
+ -- Purpose: PLL for UniBoard node CLK input @ 125 MHz
+ -- Description:
+ -- c0 = 20 MHz
+ -- c1 = 50 MHz
+ -- c2 = 100 MHz
+ -- c3 = 125 MHz
+ --
entity unb2b_board_clk125_pll is
generic (
@@ -60,46 +60,46 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk125,
- outclk => clk125buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk125,
+ outclk => clk125buf
+ );
end generate;
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
gen_fractional_pll : if g_use_fpll = true generate
u_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
end arria10;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
index ac2db2f0ca..82c3f9e756 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
@@ -21,74 +21,74 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Purpose: PLL for UniBoard node CLK input @ 200 MHz
--- Description:
--- . The PLL runs in normal mode using c0 to compensate for the internal clock
--- network delay, so that c0 = st_clk200 is aligned to the input clk200.
--- . The assumption is that default the streaming DSP will run on the 200 MHz
--- clock from the CLK input via c1 = st_clk200p.
--- . The PLL normal mode operation compensates for internal clock network
--- delays of c0. This compensations aligns c0 to inclk0. With
--- tb_unb2b_board_clk200_pll.vhd it appears that the phase setting for c0 does
--- not influence the compensation. Therefore it is llso possible to use
--- g_clk200_phase_shift /= 0 and touse c0 as processing clock instead of c1.
--- . The phase offset of c0 and c1 in the clk200_pll MegaWizard component
--- can be set in steps of 11.25 degrees (and even finer):
--- g_clk200_phase_shift (for c0)
--- phase [degrees] g_clk200p_phase_shift (for c1)
--- 0 "0"
--- 11.25 "156"
--- 22.5 "313"
--- 33.75 "469"
--- 45 "625"
--- 56.25 "781"
--- 67.5 "938"
--- 78.75 "1094"
--- 90 "1250"
--- 101.25 "1406" = 1250+ 156
--- 112.5 "1563" = 1250+ 313
--- 123.75 "1719" = 1250+ 469
--- 135 "1875" = 1250+ 625
--- 146.25 "2031" = 1250+ 781
--- 157.5 "2188" = 1250+ 938
--- 168.75 "2344" = 1250+1094
--- 180 "2500" = 1250+1250
--- 191.25 "2656" = 2500+ 156
--- 202.5 "2813" = 2500+ 313
--- 213.75 "2969" = 2500+ 469
--- 225 "3125" = 2500+ 625
--- 236.25 "3281" = 2500+ 781
--- 247.5 "3438" = 2500+ 938
--- 258.75 "3594" = 2500+1094
--- 270 "3750" = 2500+1250
--- 281.25 "3906" = 3750+ 156
--- 292.5 "4063" = 3750+ 313
--- 303.75 "4219" = 3750+ 469
--- 315 "4375" = 3750+ 625
--- 326.25 "4531" = 3750+ 781
--- 337.5 "4688" = 3750+ 938
--- 348.75 "4844" = 3750+1094
--- 360 "5000" = 3750+1250
--- . With a phase offset of 22.5 degrees the c1 = clk200p is offset by a 1/16
--- period of 200 MHz, so 1/8 period of the 400 MHz DCLK from ADU and 1/4
--- period of the 800 MHz sample SCLK of ADU. This phase offset can be used
--- to achieve stable timing between the DCLK and the clk200p domain.
--- . Some DSP may also be possible at 400 MHz via st_clk400. Note that this
--- 400 MHz can also be used at places where only a little more than 200 MHz
--- would be needed, e.g. to create packets at full data rate.
--- Therefore it is not necessary to create yet another st clock frequency.
--- This to also avoid the EMI or RFI that a non integer factor of 200 MHz
--- like e.g. 250 MHz would cause.
--- . At 400 MHz ADC samples can be clocked in at 800 MSps using DDIO. At 800
--- MSps the sample period is 1250 ns. Input timing can be tuned via fixed
--- pad input delays and/or by using another phase of the PLL output clock.
--- Remarks:
--- . If necessary more 400 M clock phase could be made available, via g_sel.
---
+ -- Purpose: PLL for UniBoard node CLK input @ 200 MHz
+ -- Description:
+ -- . The PLL runs in normal mode using c0 to compensate for the internal clock
+ -- network delay, so that c0 = st_clk200 is aligned to the input clk200.
+ -- . The assumption is that default the streaming DSP will run on the 200 MHz
+ -- clock from the CLK input via c1 = st_clk200p.
+ -- . The PLL normal mode operation compensates for internal clock network
+ -- delays of c0. This compensations aligns c0 to inclk0. With
+ -- tb_unb2b_board_clk200_pll.vhd it appears that the phase setting for c0 does
+ -- not influence the compensation. Therefore it is llso possible to use
+ -- g_clk200_phase_shift /= 0 and touse c0 as processing clock instead of c1.
+ -- . The phase offset of c0 and c1 in the clk200_pll MegaWizard component
+ -- can be set in steps of 11.25 degrees (and even finer):
+ -- g_clk200_phase_shift (for c0)
+ -- phase [degrees] g_clk200p_phase_shift (for c1)
+ -- 0 "0"
+ -- 11.25 "156"
+ -- 22.5 "313"
+ -- 33.75 "469"
+ -- 45 "625"
+ -- 56.25 "781"
+ -- 67.5 "938"
+ -- 78.75 "1094"
+ -- 90 "1250"
+ -- 101.25 "1406" = 1250+ 156
+ -- 112.5 "1563" = 1250+ 313
+ -- 123.75 "1719" = 1250+ 469
+ -- 135 "1875" = 1250+ 625
+ -- 146.25 "2031" = 1250+ 781
+ -- 157.5 "2188" = 1250+ 938
+ -- 168.75 "2344" = 1250+1094
+ -- 180 "2500" = 1250+1250
+ -- 191.25 "2656" = 2500+ 156
+ -- 202.5 "2813" = 2500+ 313
+ -- 213.75 "2969" = 2500+ 469
+ -- 225 "3125" = 2500+ 625
+ -- 236.25 "3281" = 2500+ 781
+ -- 247.5 "3438" = 2500+ 938
+ -- 258.75 "3594" = 2500+1094
+ -- 270 "3750" = 2500+1250
+ -- 281.25 "3906" = 3750+ 156
+ -- 292.5 "4063" = 3750+ 313
+ -- 303.75 "4219" = 3750+ 469
+ -- 315 "4375" = 3750+ 625
+ -- 326.25 "4531" = 3750+ 781
+ -- 337.5 "4688" = 3750+ 938
+ -- 348.75 "4844" = 3750+1094
+ -- 360 "5000" = 3750+1250
+ -- . With a phase offset of 22.5 degrees the c1 = clk200p is offset by a 1/16
+ -- period of 200 MHz, so 1/8 period of the 400 MHz DCLK from ADU and 1/4
+ -- period of the 800 MHz sample SCLK of ADU. This phase offset can be used
+ -- to achieve stable timing between the DCLK and the clk200p domain.
+ -- . Some DSP may also be possible at 400 MHz via st_clk400. Note that this
+ -- 400 MHz can also be used at places where only a little more than 200 MHz
+ -- would be needed, e.g. to create packets at full data rate.
+ -- Therefore it is not necessary to create yet another st clock frequency.
+ -- This to also avoid the EMI or RFI that a non integer factor of 200 MHz
+ -- like e.g. 250 MHz would cause.
+ -- . At 400 MHz ADC samples can be clocked in at 800 MSps using DDIO. At 800
+ -- MSps the sample period is 1250 ns. Input timing can be tuned via fixed
+ -- pad input delays and/or by using another phase of the PLL output clock.
+ -- Remarks:
+ -- . If necessary more 400 M clock phase could be made available, via g_sel.
+ --
entity unb2b_board_clk200_pll is
generic (
@@ -136,82 +136,82 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk200,
- outclk => clk200buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk200,
+ outclk => clk200buf
+ );
end generate;
gen_st_pll : if g_use_fpll = false generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200buf,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_st_fractional_pll : if g_use_fpll = true generate
u_st_fractional_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk200
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf, -- 200 MHz
+ c0 => i_st_clk200, -- 200 MHz
+ c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
+ c2 => i_st_clk400, -- 400 MHz
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end arria10;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
index 24625f7333..eb7de7d44e 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
@@ -21,17 +21,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Purpose: PLL for UniBoard node CLK input @ 25 MHz
--- Description:
--- c0 = 20 MHz
--- c1 = 50 MHz
--- c2 = 100 MHz
--- c3 = 125 MHz
---
+ -- Purpose: PLL for UniBoard node CLK input @ 25 MHz
+ -- Description:
+ -- c0 = 20 MHz
+ -- c1 = 50 MHz
+ -- c2 = 100 MHz
+ -- c3 = 125 MHz
+ --
entity unb2b_board_clk25_pll is
generic (
@@ -52,16 +52,16 @@ end unb2b_board_clk25_pll;
architecture arria10 of unb2b_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end arria10;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
index a5877c96a4..8f133e2a83 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose:
--- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
--- reset_n).
--- 2) sys_rst released when the sys_clk PLL from the SOPC system has locked,
--- can be used as a system reset for the sys_clk domain.
+ -- Purpose:
+ -- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
+ -- reset_n).
+ -- 2) sys_rst released when the sys_clk PLL from the SOPC system has locked,
+ -- can be used as a system reset for the sys_clk domain.
entity unb2b_board_clk_rst is
port (
@@ -55,27 +55,27 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
index 8eaa8e52bc..61acfae82a 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_front_io is
generic (
@@ -62,8 +62,8 @@ begin
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2b_board_tr_qsfp.bus_w - 1 generate
- si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j);
- serial_rx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
-end;
+ end;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
index 06b87a197e..b3431dbeba 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2b_board_hmc_ctrl is
generic (
@@ -89,7 +89,7 @@ architecture rtl of unb2b_board_hmc_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- );
+ );
constant c_seq_len : natural := c_SEQ'length - 1;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
index affbc014cb..8c42803465 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose: Provide the basic node clock control (resets, pulses, WDI)
--- Description:
--- . Create mm_rst for mm_clk:
--- . Extend WDI to avoid watchdog reset during software reload
--- . Pulse every 1 us, 1 ms and 1 s
+ -- Purpose: Provide the basic node clock control (resets, pulses, WDI)
+ -- Description:
+ -- . Create mm_rst for mm_clk:
+ -- . Extend WDI to avoid watchdog reset during software reload
+ -- . Pulse every 1 us, 1 ms and 1 s
entity unb2b_board_node_ctrl is
generic (
@@ -67,43 +67,43 @@ begin
mm_locked_n <= not mm_locked;
u_common_areset_mm : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => mm_clk,
- out_rst => i_mm_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => mm_clk,
+ out_rst => i_mm_rst
+ );
-- Create 1 pulse per us, per ms and per s
mm_pulse_ms <= i_mm_pulse_ms;
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_us => mm_pulse_us,
- pulse_ms => i_mm_pulse_ms,
- pulse_s => mm_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_us => mm_pulse_us,
+ pulse_ms => i_mm_pulse_ms,
+ pulse_s => mm_pulse_s
+ );
-- Toggle the WDI every 1 ms
u_unb2b_board_wdi_extend : entity work.unb2b_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_ms => i_mm_pulse_ms,
- wdi_in => mm_wdi_in,
- wdi_out => mm_wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_ms => i_mm_pulse_ms,
+ wdi_in => mm_wdi_in,
+ wdi_out => mm_wdi_out
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
index 50a6d2d7a5..6be352109c 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb2b_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
@@ -74,10 +74,10 @@ package unb2b_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
index ecc6fbb01b..58edee6b41 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb2b_board_pkg is
-- UniBoard
@@ -145,21 +145,23 @@ package unb2b_board_pkg is
type t_c_unb2b_board_system_info is record
version : natural; -- UniBoard board HW version (2 bit value)
id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
+ -- Derived ID info:
bck_id : natural; -- = id[7:2], ID part from back plane
chip_id : natural; -- = id[1:0], ID part from UniBoard
node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
is_node2 : natural; -- 1 for Node 2, else 0.
end record;
- function func_unb2b_board_system_info(VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2b_board_aux.id_w - 1 downto 0)) return t_c_unb2b_board_system_info;
+ function func_unb2b_board_system_info(
+ VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2b_board_aux.id_w - 1 downto 0)) return t_c_unb2b_board_system_info;
-end unb2b_board_pkg;
+ end unb2b_board_pkg;
package body unb2b_board_pkg is
- function func_unb2b_board_system_info(VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2b_board_aux.id_w - 1 downto 0)) return t_c_unb2b_board_system_info is
+ function func_unb2b_board_system_info(
+ VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2b_board_aux.id_w - 1 downto 0)) return t_c_unb2b_board_system_info is
variable v_system_info : t_c_unb2b_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
@@ -171,4 +173,4 @@ package body unb2b_board_pkg is
return v_system_info;
end;
-end unb2b_board_pkg;
+ end unb2b_board_pkg;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
index c900196512..6fc54360dd 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2b_board_pmbus_ctrl is
generic (
@@ -89,7 +89,7 @@ architecture rtl of unb2b_board_pmbus_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- );
+ );
constant c_seq_len : natural := c_SEQ'length - 1;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
index 08ffbbe35b..dc93dec90c 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
@@ -21,48 +21,48 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
--- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
--- Description:
--- The testio LED on UniBoard2 is not visible via the front panel. The
--- front panel does have a dual colour LED for each QSFP lane. Therefore
--- these QSFP LEDs are used to signal some application information and lane
--- status/activity information.
---
--- LED lights:
---
--- 1) Default behaviour for all QSFP leds:
--- . off = no FPGA image is running
---
--- 2) For factory image:
--- . green off
--- . red toggling every 1 s = factory image is running (g_factory_image=TRUE)
---
--- 3) For a user image without Gbps lane functionality:
--- . red off
--- . green toggling every 1 s = user image is running (g_factory_image=FALSE and green_on_arr(I)='0' default)
---
--- 4) For a user image with Gbps lane functionality:
--- . red off
--- . green toggling every 1 s when the lane status is not OK (green_on_arr(I)=xon='0')
--- . green on continously when the lane status is OK (green_on_arr(I)=xon='1')
--- . green led goes off briefly off when there is an Tx or Rx packet (green_evt_arr(I).sop='1')
---
--- The combined colour amber (= red + green) is not used. The factory image
--- only uses the red led and the user image only uses the green led.
---
--- Each QSFP carries c_quad = 4 lanes, therefore the green led LED can only
--- signal a combined status of the lanes. The combined status eg. be:
---
--- 'and-status' = combined status is on when all lanes are on
--- 'or-status' = combined status is on when at least 1 lane is on
---
--- Choose using 'or-status', because then the LED can give lane status
--- information when less than all 4 lane are connected.
---
+ -- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
+ -- Description:
+ -- The testio LED on UniBoard2 is not visible via the front panel. The
+ -- front panel does have a dual colour LED for each QSFP lane. Therefore
+ -- these QSFP LEDs are used to signal some application information and lane
+ -- status/activity information.
+ --
+ -- LED lights:
+ --
+ -- 1) Default behaviour for all QSFP leds:
+ -- . off = no FPGA image is running
+ --
+ -- 2) For factory image:
+ -- . green off
+ -- . red toggling every 1 s = factory image is running (g_factory_image=TRUE)
+ --
+ -- 3) For a user image without Gbps lane functionality:
+ -- . red off
+ -- . green toggling every 1 s = user image is running (g_factory_image=FALSE and green_on_arr(I)='0' default)
+ --
+ -- 4) For a user image with Gbps lane functionality:
+ -- . red off
+ -- . green toggling every 1 s when the lane status is not OK (green_on_arr(I)=xon='0')
+ -- . green on continously when the lane status is OK (green_on_arr(I)=xon='1')
+ -- . green led goes off briefly off when there is an Tx or Rx packet (green_evt_arr(I).sop='1')
+ --
+ -- The combined colour amber (= red + green) is not used. The factory image
+ -- only uses the red led and the user image only uses the green led.
+ --
+ -- Each QSFP carries c_quad = 4 lanes, therefore the green led LED can only
+ -- signal a combined status of the lanes. The combined status eg. be:
+ --
+ -- 'and-status' = combined status is on when all lanes are on
+ -- 'or-status' = combined status is on when at least 1 lane is on
+ --
+ -- Choose using 'or-status', because then the LED can give lane status
+ -- information when less than all 4 lane are connected.
+ --
entity unb2b_board_qsfp_leds is
generic (
@@ -107,43 +107,43 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => i_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => i_pulse_s
+ );
u_common_toggle_s : entity common_lib.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => i_pulse_s,
- out_dat => toggle_s
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => i_pulse_s,
+ out_dat => toggle_s
+ );
gen_factory_image : if g_factory_image = true generate
green_led_arr <= (others => '0');
gen_red_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
u_red_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- -- led control
- ctrl_input => toggle_s,
- -- led output
- led => red_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- led control
+ ctrl_input => toggle_s,
+ -- led output
+ led => red_led_arr(I)
+ );
end generate;
end generate;
@@ -160,20 +160,20 @@ begin
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
u_green_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => i_pulse_ms,
- -- led control
- ctrl_on => qsfp_on_arr(I),
- ctrl_evt => qsfp_evt_arr(I),
- ctrl_input => toggle_s,
- -- led output
- led => green_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => i_pulse_ms,
+ -- led control
+ ctrl_on => qsfp_on_arr(I),
+ ctrl_evt => qsfp_evt_arr(I),
+ ctrl_input => toggle_s,
+ -- led output
+ led => green_led_arr(I)
+ );
end generate;
end generate;
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
index 4d89b79a08..6406d76c4b 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_ring_io is
generic (
@@ -52,4 +52,4 @@ begin
serial_rx_arr(i * c_unb2b_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
-end;
+ end;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
index bdcc956341..a2ccb72c6b 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_sens is
generic (
@@ -52,18 +52,18 @@ architecture str of unb2b_board_sens is
-- I2C clock rate settings
constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
--CONSTANT c_sens_comma_w : NATURAL := 13; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
- -- 0 = no comma time
+ -- 0 = no comma time
--- octave:4> t=1/50e6
--- t = 2.0000e-08
--- octave:5> delay=2^13 * t
--- delay = 1.6384e-04
--- octave:6> delay/t
--- ans = 8192
--- octave:7> log2(ans)
--- ans = 13
--- octave:8> log2(delay/t)
--- ans = 13
+ -- octave:4> t=1/50e6
+ -- t = 2.0000e-08
+ -- octave:5> delay=2^13 * t
+ -- delay = 1.6384e-04
+ -- octave:6> delay/t
+ -- ans = 8192
+ -- octave:7> log2(ans)
+ -- ans = 13
+ -- octave:8> log2(delay/t)
+ -- ans = 13
--CONSTANT c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, g_comma_w);
@@ -78,93 +78,93 @@ architecture str of unb2b_board_sens is
begin
gen_unb2b_board_sens_ctrl : if g_i2c_peripheral = c_i2c_peripheral_sens generate
u_unb2b_board_sens_ctrl : entity work.unb2b_board_sens_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2b_board_pmbus_ctrl : if g_i2c_peripheral = c_i2c_peripheral_pmbus generate
u_unb2b_board_pmbus_ctrl : entity work.unb2b_board_pmbus_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2b_board_hmc_ctrl : if g_i2c_peripheral = c_i2c_peripheral_hmc generate
u_unb2b_board_hmc_ctrl : entity work.unb2b_board_hmc_ctrl
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
+ end generate;
+
+ u_i2c_smbus : entity i2c_lib.i2c_smbus
generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
+ g_i2c_phy => c_sens_phy,
+ g_clock_stretch_sense_scl => true
)
port map (
+ gs_sim => g_sim,
clk => clk,
rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
+ in_dat => smbus_in_dat,
+ in_req => smbus_in_val,
+ out_dat => smbus_out_dat,
+ out_val => smbus_out_val,
+ out_err => smbus_out_err,
+ out_ack => smbus_out_ack,
+ st_end => smbus_out_end,
+ scl => scl,
+ sda => sda
);
- end generate;
-
- u_i2c_smbus : entity i2c_lib.i2c_smbus
- generic map (
- g_i2c_phy => c_sens_phy,
- g_clock_stretch_sense_scl => true
- )
- port map (
- gs_sim => g_sim,
- clk => clk,
- rst => rst,
- in_dat => smbus_in_dat,
- in_req => smbus_in_val,
- out_dat => smbus_out_dat,
- out_val => smbus_out_val,
- out_err => smbus_out_err,
- out_ack => smbus_out_ack,
- st_end => smbus_out_end,
- scl => scl,
- sda => sda
- );
-end architecture;
+ end architecture;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
index 60b4028d32..f11b8ad431 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2b_board_sens_ctrl is
generic (
@@ -105,7 +105,7 @@ architecture rtl of unb2b_board_sens_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- );
+ );
constant c_seq_len : natural := c_SEQ'length - 1;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
index b7b2e852c0..a6e57d0bf9 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
@@ -60,10 +60,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2b_board_sens_reg is
generic (
@@ -92,13 +92,14 @@ end unb2b_board_sens_reg;
architecture rtl of unb2b_board_sens_reg is
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
- -- +1 to fit sens_err in the last address
+ -- +1 to fit sens_err in the last address
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_mm_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_mm_nof_dat),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_mm_nof_dat,
+ init_sl => '0');
signal i_temp_high : std_logic_vector(6 downto 0);
begin
@@ -130,14 +131,14 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
if vA = g_sens_nof_result + 1 then
- -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
- -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
- if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
- i_temp_high <= sla_in.wrdata(6 downto 0);
- end if;
+ -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
+ -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
+ if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
+ i_temp_high <= sla_in.wrdata(6 downto 0);
+ end if;
end if;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
index adf5baaffb..f12b1e6172 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
@@ -21,14 +21,14 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Keep the UniBoard system info knowledge in this HDL entity and in the
--- corresponding software functions in unb_common.c,h. This avoids having to
--- define named constants for indexing the fields in the info word.
+ -- Keep the UniBoard system info knowledge in this HDL entity and in the
+ -- corresponding software functions in unb_common.c,h. This avoids having to
+ -- define named constants for indexing the fields in the info word.
entity unb2b_board_system_info is
generic (
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
index c3f5a857aa..77dc408ce5 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_system_info_reg is
generic (
@@ -68,7 +68,7 @@ entity unb2b_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb2b_board_system_info_reg;
architecture rtl of unb2b_board_system_info_reg is
@@ -86,11 +86,12 @@ architecture rtl of unb2b_board_system_info_reg is
constant c_revision_id_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
constant c_design_note_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs; -- = 2+13+2+3+12 = 32
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0');
constant c_use_phy_w : natural := 8;
constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
index 74ccf1459b..fe7fdd3dc7 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose:
--- Extend the input WDI that is controlled in SW (as it should be) to avoid
--- that the watchdog reset will occur when new SW is loaded, while keeping
--- the HDL image. This component extends the last input WDI by toggling the
--- output WDI for about 2**(g_extend_w-1) ms more.
+ -- Purpose:
+ -- Extend the input WDI that is controlled in SW (as it should be) to avoid
+ -- that the watchdog reset will occur when new SW is loaded, while keeping
+ -- the HDL image. This component extends the last input WDI by toggling the
+ -- output WDI for about 2**(g_extend_w-1) ms more.
entity unb2b_board_wdi_extend is
generic (
@@ -68,26 +68,26 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
index f052cbb7b2..66a546c8fa 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2b_board_wdi_reg is
port (
@@ -40,16 +40,17 @@ entity unb2b_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb2b_board_wdi_reg;
architecture rtl of unb2b_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
@@ -60,7 +61,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
index ef80a940f5..d2b3584882 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
@@ -32,12 +32,12 @@ entity tb_mms_unb2b_board_sens is
end tb_mms_unb2b_board_sens;
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.unb2b_board_pkg.all;
architecture tb of tb_mms_unb2b_board_sens is
constant c_sim : boolean := true; -- FALSE;
@@ -148,61 +148,61 @@ begin
-- I2C sensors master
u_mms_unb2b_board_sens : entity work.mms_unb2b_board_sens
- generic map (
- g_sim => c_sim,
- g_i2c_peripheral => c_i2c_peripheral_sens,
- g_sens_nof_result => 40,
- g_clk_freq => c_clk_freq,
- g_temp_high => c_temp_high,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- mm_start => start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- i2c bus
- scl => scl,
- sda => sda
- );
+ generic map (
+ g_sim => c_sim,
+ g_i2c_peripheral => c_i2c_peripheral_sens,
+ g_sens_nof_result => 40,
+ g_clk_freq => c_clk_freq,
+ g_temp_high => c_temp_high,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ mm_start => start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- i2c bus
+ scl => scl,
+ sda => sda
+ );
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => scl,
- sda => sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
index df9a474f61..9030c140a8 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2b_board_clk125_pll is
end tb_unb2b_board_clk125_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2b_board_clk125_pll
- port map (
- arst => ext_rst,
- clk125 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk125 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
index e0559528e8..d330a1fe32 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2b_board_clk200_pll is
end tb_unb2b_board_clk200_pll;
@@ -66,44 +66,44 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2b_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb2b_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb2b_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
index 02d31bf344..ed44f1a5f7 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2b_board_clk25_pll is
end tb_unb2b_board_clk25_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2b_board_clk25_pll
- port map (
- arst => ext_rst,
- clk25 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk25 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
index 9f41504493..d7f9dbb21f 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2b_board_node_ctrl is
end tb_unb2b_board_node_ctrl;
@@ -71,23 +71,23 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb2b_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- -- MM clock domain reset
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => wdi_in,
- mm_wdi_out => wdi_out,
- -- Pulses
- mm_pulse_us => pulse_us,
- mm_pulse_ms => pulse_ms,
- mm_pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => wdi_in,
+ mm_wdi_out => wdi_out,
+ -- Pulses
+ mm_pulse_us => pulse_us,
+ mm_pulse_ms => pulse_ms,
+ mm_pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
index b7d1a8ba03..4b02b044d1 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
@@ -37,10 +37,10 @@
-- > run -a
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_unb2b_board_qsfp_leds is
end tb_unb2b_board_qsfp_leds;
@@ -139,48 +139,48 @@ begin
end process;
u_unb2b_factory_qsfp_leds : entity work.unb2b_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => factory_green_led_arr,
- red_led_arr => factory_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => true, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => factory_green_led_arr,
+ red_led_arr => factory_red_led_arr
+ );
u_unb2b_user_qsfp_leds : entity work.unb2b_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => user_green_led_arr,
- red_led_arr => user_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => false, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => user_green_led_arr,
+ red_led_arr => user_red_led_arr
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
index 615aa3863a..249c026b7a 100644
--- a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2b_board_10gbe is
generic (
@@ -77,17 +77,17 @@ architecture str of unb2b_board_10gbe is
signal tr_ref_rst_156 : std_logic;
begin
u_unb2b_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => g_technology
- )
- port map (
- refclk_644 => tr_ref_clk,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ refclk_644 => tr_ref_clk,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
diff --git a/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd b/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
index 40e4278b6c..a1afbf0bfd 100644
--- a/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
+++ b/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
entity unb2c_led is
generic (
@@ -114,57 +114,57 @@ begin
-- by using the fpll, the CLKUSR is used for calibration. So in case fpll does not work, check CLKUSR
u_unb2c_board_clk200_pll : entity unb2c_board_lib.unb2c_board_clk200_pll
- generic map (
- g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
- g_technology => g_technology
- )
- port map (
- arst => xo_rst,
- clk200 => CLK,
- st_clk200 => clk200
- );
+ generic map (
+ g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
+ g_technology => g_technology
+ )
+ port map (
+ arst => xo_rst,
+ clk200 => CLK,
+ st_clk200 => clk200
+ );
xo_ethclk <= ETH_CLK(0); -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_ethclk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_ethclk,
+ out_rst => xo_rst
+ );
u_unb2c_board_clk125_pll : entity unb2c_board_lib.unb2c_board_clk125_pll
- generic map (
- g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
- g_technology => g_technology
- )
- port map (
- arst => xo_rst,
- clk125 => xo_ethclk,
- c1_clk50 => clk50,
- pll_locked => mm_locked
- );
+ generic map (
+ g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
+ g_technology => g_technology
+ )
+ port map (
+ arst => xo_rst,
+ clk125 => xo_ethclk,
+ c1_clk50 => clk50,
+ pll_locked => mm_locked
+ );
u_unb2c_board_node_ctrl : entity unb2c_board_lib.unb2c_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => clk50,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => mm_pulse_s,
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
+ generic map (
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => clk50,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => mm_pulse_s,
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
+ );
------------------------------------------------------------------------------
-- Toggle red LED when unb2c_minimal is running, green LED for other designs.
@@ -173,15 +173,15 @@ begin
led_flash_green <= sel_a_b(g_factory_image = false, led_flash, '0');
u_extend : entity common_lib.common_pulse_extend
- generic map (
- g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
- )
- port map (
- rst => mm_rst,
- clk => clk50,
- p_in => mm_pulse_s,
- ep_out => led_flash
- );
+ generic map (
+ g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
+ )
+ port map (
+ rst => mm_rst,
+ clk => clk50,
+ p_in => mm_pulse_s,
+ ep_out => led_flash
+ );
-- Red LED control
TESTIO(c_unb2c_board_testio_led_red) <= led_flash_red;
@@ -190,36 +190,36 @@ begin
TESTIO(c_unb2c_board_testio_led_green) <= led_flash_green;
u_common_pulser_10Hz : entity common_lib.common_pulser
- generic map (
- g_pulse_period => 100,
- g_pulse_phase => 100 - 1
- )
- port map (
- rst => mm_rst,
- clk => clk50,
- clken => '1',
- pulse_en => mm_pulse_ms,
- pulse_out => pulse_10Hz
- );
+ generic map (
+ g_pulse_period => 100,
+ g_pulse_phase => 100 - 1
+ )
+ port map (
+ rst => mm_rst,
+ clk => clk50,
+ clken => '1',
+ pulse_en => mm_pulse_ms,
+ pulse_out => pulse_10Hz
+ );
u_extend_10Hz : entity common_lib.common_pulse_extend
- generic map (
- g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
- )
- port map (
- rst => mm_rst,
- clk => clk50,
- p_in => pulse_10Hz,
- ep_out => pulse_10Hz_extended
- );
+ generic map (
+ g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
+ )
+ port map (
+ rst => mm_rst,
+ clk => clk50,
+ p_in => pulse_10Hz,
+ ep_out => pulse_10Hz_extended
+ );
u_toggle : entity common_lib.common_toggle
- port map (
- rst => mm_rst,
- clk => clk50,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => mm_rst,
+ clk => clk50,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
QSFP_LED(2) <= pulse_10Hz_extended;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
index c93a01d6ed..69da2e47a8 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2c_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2c_minimal_pkg.all;
entity mmm_unb2c_minimal is
generic (
@@ -107,30 +107,38 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -277,7 +285,7 @@ begin
ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
ram_scrap_read_export => ram_scrap_mosi.rd,
ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
- );
+ );
end generate;
end str;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
index 0d31242e08..63a16d3654 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
@@ -20,129 +20,129 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2c_minimal_pkg is
- ----------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus QSYS builder
- ----------------------------------------------------------------------
+ ----------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus QSYS builder
+ ----------------------------------------------------------------------
- component qsys_unb2c_minimal is
- port (
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_unb2c_minimal;
+ component qsys_unb2c_minimal is
+ port (
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_unb2c_minimal;
end qsys_unb2c_minimal_pkg;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
index 87ec585053..d004b289a4 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
entity unb2c_minimal is
generic (
@@ -146,209 +146,209 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- scrap ram
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . 1GbE Control Interface
--- ETH_clk => ETH_CLK(0),
--- ETH_SGIN => ETH_SGIN(0),
--- ETH_SGOUT => ETH_SGOUT(0)
-
- ETH_clk => ETH_CLK(1),
- ETH_SGIN => ETH_SGIN(1),
- ETH_SGOUT => ETH_SGOUT(1)
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- scrap ram
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . 1GbE Control Interface
+ -- ETH_clk => ETH_CLK(0),
+ -- ETH_SGIN => ETH_SGIN(0),
+ -- ETH_SGOUT => ETH_SGOUT(0)
+
+ ETH_clk => ETH_CLK(1),
+ ETH_SGIN => ETH_SGIN(1),
+ ETH_SGOUT => ETH_SGOUT(1)
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2c_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- Scrap RAM
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- Scrap RAM
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
index 5fc724c707..d885913a24 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
@@ -42,20 +42,20 @@
--
library IEEE, common_lib, unb2c_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
entity tb_unb2c_minimal is
- generic (
- g_design_name : string := "unb2c_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2c_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2c_minimal;
architecture tb of tb_unb2c_minimal is
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
index cb584d11aa..9360603d06 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_10GbE is
end tb_unb2c_test_10GbE;
@@ -29,7 +29,7 @@ end tb_unb2c_test_10GbE;
architecture tb of tb_unb2c_test_10GbE is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_10GbE"
- );
+ generic map (
+ g_design_name => "unb2c_test_10GbE"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
index b7c61245b6..904184ba9e 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_10GbE is
generic (
@@ -92,63 +92,63 @@ end unb2c_test_10GbE;
architecture str of unb2c_test_10GbE is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- back transceivers
- --BCK_RX => BCK_RX,
- --BCK_TX => BCK_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- back transceivers
+ --BCK_RX => BCK_RX,
+ --BCK_TX => BCK_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
index 55beabab75..0c8dcdaa05 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
@@ -43,7 +43,7 @@
-- > tc_unb2_test_eth.py --gn2 0 --stream 0 --dest loopback -r 10000 --sizes 1000 --interval 100 --scheme tx_rx --sim
-- stop simulation.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_1GbE_I is
end tb_unb2c_test_1GbE_I;
@@ -66,27 +66,27 @@ begin
eth_sgin <= eth_sgout; -- loopback eth0 and eth1
u_unb2c_test_1GbE_I : entity work.unb2c_test_1GbE_I
- generic map (
- g_sim => true
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => wdi,
- INTA => OPEN,
- INTB => OPEN,
+ generic map (
+ g_sim => true
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => wdi,
+ INTA => OPEN,
+ INTB => OPEN,
- -- Others
- VERSION => "00",
- ID => "00000000",
- TESTIO => OPEN,
+ -- Others
+ VERSION => "00",
+ ID => "00000000",
+ TESTIO => OPEN,
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_sgin,
- ETH_SGOUT => eth_sgout,
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_sgin,
+ ETH_SGOUT => eth_sgout,
- QSFP_LED => open
- );
+ QSFP_LED => open
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
index 14e29aca56..8ccd3f755e 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
@@ -25,11 +25,11 @@
-- Description:
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_1GbE_I is
generic (
@@ -67,34 +67,34 @@ end unb2c_test_1GbE_I;
architecture str of unb2c_test_1GbE_I is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
index 0d481eb327..85b2717521 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
@@ -45,7 +45,7 @@
-- for faster sim.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_1GbE_II is
end tb_unb2c_test_1GbE_II;
@@ -68,27 +68,27 @@ begin
eth_sgin <= eth_sgout; -- loopback eth0 and eth1
u_unb2c_test_1GbE_II : entity work.unb2c_test_1GbE_II
- generic map (
- g_sim => true
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => wdi,
- INTA => OPEN,
- INTB => OPEN,
+ generic map (
+ g_sim => true
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => wdi,
+ INTA => OPEN,
+ INTB => OPEN,
- -- Others
- VERSION => "00",
- ID => "00000000",
- TESTIO => OPEN,
+ -- Others
+ VERSION => "00",
+ ID => "00000000",
+ TESTIO => OPEN,
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_sgin,
- ETH_SGOUT => eth_sgout,
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_sgin,
+ ETH_SGOUT => eth_sgout,
- QSFP_LED => open
- );
+ QSFP_LED => open
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
index 850e616ac8..e07f77e72f 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
@@ -25,11 +25,11 @@
-- Description:
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_1GbE_II is
generic (
@@ -67,34 +67,34 @@ end unb2c_test_1GbE_II;
architecture str of unb2c_test_1GbE_II is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
index d25bb0a613..aea05dd7b0 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_ddr is
end tb_unb2c_test_ddr;
@@ -29,7 +29,7 @@ end tb_unb2c_test_ddr;
architecture tb of tb_unb2c_test_ddr is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_ddr"
- );
+ generic map (
+ g_design_name => "unb2c_test_ddr"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
index b5b75bb185..91be6ded84 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2c_test_ddr is
generic (
@@ -78,48 +78,48 @@ end unb2c_test_ddr;
architecture str of unb2c_test_ddr is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
index b3a43fdf88..d2989beca7 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_ddr_16G is
end tb_unb2c_test_ddr_16G;
@@ -29,7 +29,7 @@ end tb_unb2c_test_ddr_16G;
architecture tb of tb_unb2c_test_ddr_16G is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_ddr_16G"
- );
+ generic map (
+ g_design_name => "unb2c_test_ddr_16G"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
index a19523ddca..d7fea759e2 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2c_test_ddr_16G is
generic (
@@ -78,48 +78,48 @@ end unb2c_test_ddr_16G;
architecture str of unb2c_test_ddr_16G is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
index 33951098a3..dbaca1d260 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_heater is
end tb_unb2c_test_heater;
@@ -29,7 +29,7 @@ end tb_unb2c_test_heater;
architecture tb of tb_unb2c_test_heater is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_heater"
- );
+ generic map (
+ g_design_name => "unb2c_test_heater"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
index e85b07f9c1..047ad42c6f 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_heater is
generic (
@@ -63,34 +63,34 @@ end unb2c_test_heater;
architecture str of unb2c_test_heater is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
index 9c8cc77e4e..7edfbe592e 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_jesd204b is
end tb_unb2c_test_jesd204b;
@@ -29,7 +29,7 @@ end tb_unb2c_test_jesd204b;
architecture tb of tb_unb2c_test_jesd204b is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_jesd204b"
- );
+ generic map (
+ g_design_name => "unb2c_test_jesd204b"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
index 3c61c07680..709947100c 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_jesd204b is
generic (
@@ -69,40 +69,40 @@ end unb2c_test_jesd204b;
architecture str of unb2c_test_jesd204b is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- jesd204b
- BCK_REF_CLK => BCK_REF_CLK,
- BCK_RX => BCK_RX,
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC => JESD204B_SYNC,
+ -- jesd204b
+ BCK_REF_CLK => BCK_REF_CLK,
+ BCK_RX => BCK_RX,
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC => JESD204B_SYNC,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
index 85260e0c01..3eabc49a20 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_minimal is
generic (
@@ -63,34 +63,34 @@ end unb2c_test_minimal;
architecture str of unb2c_test_minimal is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index 468e48a1a4..19fd41867b 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb2c_test_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
-use work.unb2c_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb2c_test_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use work.unb2c_test_pkg.all;
entity mmm_unb2c_test is
generic (
@@ -280,115 +280,160 @@ begin
eth_0_mm_rst <= mm_rst;
eth_1_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
-
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
-
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
-
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
-
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
-
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-
- u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
- u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
- u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
-
- u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
- u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
- u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
-
- u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
-
- u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ u_mm_file_reg_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+ u_mm_file_ram_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+ u_mm_file_reg_diag_tx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+
+ u_mm_file_reg_bsn_monitor_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+ u_mm_file_ram_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+ u_mm_file_reg_diag_rx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+
+ u_mm_file_reg_io_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+ u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+ u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+ u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+ u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_reg_io_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+ u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+ u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+ u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+ u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
-- . 1GbE_I with TSE setup by NiosII
- u_mm_file_reg_eth_0_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_TSE")
- port map(mm_rst, mm_clk, eth_0_tse_mosi, eth_0_tse_miso);
- u_mm_file_reg_eth_0_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_REG")
- port map(mm_rst, mm_clk, i_eth_0_reg_mosi, eth_0_reg_miso);
- u_mm_file_reg_eth_0_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_RAM")
- port map(mm_rst, mm_clk, eth_0_ram_mosi, eth_0_ram_miso);
+ u_mm_file_reg_eth_0_tse : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_TSE")
+ port map(mm_rst, mm_clk, eth_0_tse_mosi, eth_0_tse_miso);
+ u_mm_file_reg_eth_0_reg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_REG")
+ port map(mm_rst, mm_clk, i_eth_0_reg_mosi, eth_0_reg_miso);
+ u_mm_file_reg_eth_0_ram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_RAM")
+ port map(mm_rst, mm_clk, eth_0_ram_mosi, eth_0_ram_miso);
-- . 1GbE_II with TSE setup in VHDL
- u_mm_file_reg_eth_1_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_TSE")
- port map(mm_rst, mm_clk, eth_1_tse_mosi, eth_1_tse_miso);
-
- u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
- port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
- u_mm_file_reg_tr_10GbE_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
-
- u_mm_file_reg_eth10g_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
- port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
- u_mm_file_reg_eth10g_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
- port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
-
- u_mm_file_reg_heater : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
- port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
-
- u_mm_file_reg_reg_diag_bg_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_ETH_0")
- port map(mm_rst, mm_clk, reg_diag_bg_eth_0_copi, reg_diag_bg_eth_0_cipo );
- u_mm_file_reg_hdr_dat_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT_ETH_0")
- port map(mm_rst, mm_clk, reg_hdr_dat_eth_0_copi, reg_hdr_dat_eth_0_cipo );
- u_mm_file_reg_bsn_monitor_v2_tx_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX_ETH_0")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_0_copi, reg_bsn_monitor_v2_tx_eth_0_cipo );
- u_mm_file_reg_strobe_total_count_tx_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_TX_ETH_0")
- port map(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_0_copi, reg_strobe_total_count_tx_eth_0_cipo );
- u_mm_file_reg_bsn_monitor_v2_rx_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ETH_0")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_0_copi, reg_bsn_monitor_v2_rx_eth_0_cipo );
- u_mm_file_reg_strobe_total_count_rx_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_RX_ETH_0")
- port map(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_0_copi, reg_strobe_total_count_rx_eth_0_cipo );
-
- u_mm_file_reg_reg_diag_bg_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_ETH_1")
- port map(mm_rst, mm_clk, reg_diag_bg_eth_1_copi, reg_diag_bg_eth_1_cipo );
- u_mm_file_reg_hdr_dat_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT_ETH_1")
- port map(mm_rst, mm_clk, reg_hdr_dat_eth_1_copi, reg_hdr_dat_eth_1_cipo );
- u_mm_file_reg_bsn_monitor_v2_tx_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX_ETH_1")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_1_copi, reg_bsn_monitor_v2_tx_eth_1_cipo );
- u_mm_file_reg_strobe_total_count_tx_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_TX_ETH_1")
- port map(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_1_copi, reg_strobe_total_count_tx_eth_1_cipo );
- u_mm_file_reg_bsn_monitor_v2_rx_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ETH_1")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_1_copi, reg_bsn_monitor_v2_rx_eth_1_cipo );
- u_mm_file_reg_strobe_total_count_rx_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_RX_ETH_1")
- port map(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_1_copi, reg_strobe_total_count_rx_eth_1_cipo );
+ u_mm_file_reg_eth_1_tse : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_TSE")
+ port map(mm_rst, mm_clk, eth_1_tse_mosi, eth_1_tse_miso);
+
+ u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
+ u_mm_file_reg_tr_10GbE_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
+
+ u_mm_file_reg_eth10g_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
+ u_mm_file_reg_eth10g_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
+ port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
+
+ u_mm_file_reg_heater : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
+ port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+
+ u_mm_file_reg_reg_diag_bg_eth_0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_ETH_0")
+ port map(mm_rst, mm_clk, reg_diag_bg_eth_0_copi, reg_diag_bg_eth_0_cipo );
+ u_mm_file_reg_hdr_dat_eth_0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT_ETH_0")
+ port map(mm_rst, mm_clk, reg_hdr_dat_eth_0_copi, reg_hdr_dat_eth_0_cipo );
+ u_mm_file_reg_bsn_monitor_v2_tx_eth_0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX_ETH_0")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_0_copi, reg_bsn_monitor_v2_tx_eth_0_cipo );
+ u_mm_file_reg_strobe_total_count_tx_eth_0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_TX_ETH_0")
+ port map(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_0_copi, reg_strobe_total_count_tx_eth_0_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_eth_0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ETH_0")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_0_copi, reg_bsn_monitor_v2_rx_eth_0_cipo );
+ u_mm_file_reg_strobe_total_count_rx_eth_0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_RX_ETH_0")
+ port map(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_0_copi, reg_strobe_total_count_rx_eth_0_cipo );
+
+ u_mm_file_reg_reg_diag_bg_eth_1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_ETH_1")
+ port map(mm_rst, mm_clk, reg_diag_bg_eth_1_copi, reg_diag_bg_eth_1_cipo );
+ u_mm_file_reg_hdr_dat_eth_1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT_ETH_1")
+ port map(mm_rst, mm_clk, reg_hdr_dat_eth_1_copi, reg_hdr_dat_eth_1_cipo );
+ u_mm_file_reg_bsn_monitor_v2_tx_eth_1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX_ETH_1")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_1_copi, reg_bsn_monitor_v2_tx_eth_1_cipo );
+ u_mm_file_reg_strobe_total_count_tx_eth_1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_TX_ETH_1")
+ port map(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_1_copi, reg_strobe_total_count_tx_eth_1_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_eth_1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ETH_1")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_1_copi, reg_bsn_monitor_v2_rx_eth_1_cipo );
+ u_mm_file_reg_strobe_total_count_rx_eth_1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_RX_ETH_1")
+ port map(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_1_copi, reg_strobe_total_count_rx_eth_1_cipo );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -413,10 +458,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth_0_reg_mosi, i_eth_0_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth_0_reg_mosi <= sim_eth_0_reg_mosi;
- else
- eth_0_reg_mosi <= i_eth_0_reg_mosi;
- end if;
+ eth_0_reg_mosi <= sim_eth_0_reg_mosi;
+ else
+ eth_0_reg_mosi <= i_eth_0_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
index 082cb25503..c80a0d6c8e 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
@@ -27,15 +27,15 @@
-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
library IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity node_adc_input_and_timing_nowg is
generic (
@@ -86,11 +86,12 @@ entity node_adc_input_and_timing_nowg is
end node_adc_input_and_timing_nowg;
architecture str of node_adc_input_and_timing_nowg is
- constant c_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_jesd_ctrl_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0');
-- Frame parameters TBC
constant c_bs_bsn_w : natural := 64; -- 51;
@@ -133,62 +134,62 @@ begin
-----------------------------------------------------------------------------
u_jesd204b: entity tech_jesd204b_lib.tech_jesd204b
- generic map(
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_nof_sync_n => g_nof_sync_n,
- g_jesd_freq => g_jesd_freq
- )
- port map(
- jesd204b_refclk => jesd204b_refclk,
- jesd204b_sysref => jesd204b_sysref,
- jesd204b_sync_n_arr => jesd204b_sync_n,
-
- rx_sosi_arr => rx_sosi_arr,
- rx_clk => rx_clk,
- rx_rst => rx_rst,
- rx_sysref => rx_sysref,
-
- jesd204b_disable_arr => jesd204b_disable_arr,
-
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst_internal,
-
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
-
- -- Serial
- serial_tx_arr => open,
- serial_rx_arr => jesd204b_serial_data(g_nof_streams - 1 downto 0)
- );
+ generic map(
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_nof_sync_n => g_nof_sync_n,
+ g_jesd_freq => g_jesd_freq
+ )
+ port map(
+ jesd204b_refclk => jesd204b_refclk,
+ jesd204b_sysref => jesd204b_sysref,
+ jesd204b_sync_n_arr => jesd204b_sync_n,
+
+ rx_sosi_arr => rx_sosi_arr,
+ rx_clk => rx_clk,
+ rx_rst => rx_rst,
+ rx_sysref => rx_sysref,
+
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst_internal,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => jesd204b_serial_data(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- Timestamp
-----------------------------------------------------------------------------
u_bsn_source : entity dp_lib.mms_dp_bsn_source
- generic map (
- g_cross_clock_domain => true,
- g_block_size => c_bs_block_size,
- g_nof_block_per_sync => c_bs_nof_block_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- dp_pps => rx_sysref,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_mosi,
- reg_miso => reg_bsn_source_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_block_size => c_bs_block_size,
+ g_nof_block_per_sync => c_bs_nof_block_per_sync,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ dp_pps => rx_sysref,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_bsn_source_mosi,
+ reg_miso => reg_bsn_source_miso,
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi
+ );
mux_sosi_arr <= rx_sosi_arr when rising_edge(rx_clk);
@@ -215,73 +216,73 @@ begin
-- BSN monitor (Block Checker)
---------------------------------------------------------------------------------------
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- They're all the same
- g_sync_timeout => g_bsn_sync_timeout,
- g_bsn_w => c_bs_bsn_w,
- g_log_first_bsn => false
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_input_mosi,
- reg_miso => reg_bsn_monitor_input_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- in_sosi_arr => st_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- They're all the same
+ g_sync_timeout => g_bsn_sync_timeout,
+ g_bsn_w => c_bs_bsn_w,
+ g_log_first_bsn => false
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_input_mosi,
+ reg_miso => reg_bsn_monitor_input_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ in_sosi_arr => st_sosi_arr(0 downto 0)
+ );
- -----------------------------------------------------------------------------
--- Diagnostic Data Buffer
+ -----------------------------------------------------------------------------
+ -- Diagnostic Data Buffer
-----------------------------------------------------------------------------
u_diag_data_buffer_bsn : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => c_data_w,
- g_buf_nof_data => g_buf_nof_data,
- g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
- ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
- reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
- reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
-
- in_sosi_arr => st_sosi_arr,
- in_sync => st_sosi_arr(0).sync
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => c_data_w,
+ g_buf_nof_data => g_buf_nof_data,
+ g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
+
+ in_sosi_arr => st_sosi_arr,
+ in_sync => st_sosi_arr(0).sync
+ );
-----------------------------------------------------------------------------
-- JESD Control register
-----------------------------------------------------------------------------
u_mm_jesd_ctrl_reg : entity common_lib.common_reg_r_w
- generic map (
- g_reg => c_mm_jesd_ctrl_reg,
- g_init_reg => (others => '0')
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- control side
- wr_en => jesd_ctrl_mosi.wr,
- wr_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- wr_dat => jesd_ctrl_mosi.wrdata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_en => jesd_ctrl_mosi.rd,
- rd_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- rd_dat => jesd_ctrl_miso.rddata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_val => OPEN,
- -- data side
- out_reg => mm_jesd_ctrl_reg,
- in_reg => mm_jesd_ctrl_reg
- );
+ generic map (
+ g_reg => c_mm_jesd_ctrl_reg,
+ g_init_reg => (others => '0')
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- control side
+ wr_en => jesd_ctrl_mosi.wr,
+ wr_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ wr_dat => jesd_ctrl_mosi.wrdata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_en => jesd_ctrl_mosi.rd,
+ rd_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ rd_dat => jesd_ctrl_miso.rddata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_val => OPEN,
+ -- data side
+ out_reg => mm_jesd_ctrl_reg,
+ in_reg => mm_jesd_ctrl_reg
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
index ee430f809c..cd6a237870 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
@@ -20,448 +20,448 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2c_test_pkg is
- component qsys_unb2c_test is
- port (
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_1_reset_export : out std_logic; -- export
- avs_eth_1_clk_export : out std_logic; -- export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_tse_write_export : out std_logic; -- export
- avs_eth_1_tse_read_export : out std_logic; -- export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_1_reg_write_export : out std_logic; -- export
- avs_eth_1_reg_read_export : out std_logic; -- export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_ram_write_export : out std_logic; -- export
- avs_eth_1_ram_read_export : out std_logic; -- export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_eth_0_reset_export : out std_logic; -- export
- reg_diag_bg_eth_0_clk_export : out std_logic; -- export
- reg_diag_bg_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_bg_eth_0_write_export : out std_logic; -- export
- reg_diag_bg_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_eth_0_read_export : out std_logic; -- export
- reg_diag_bg_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_eth_1_reset_export : out std_logic; -- export
- reg_diag_bg_eth_1_clk_export : out std_logic; -- export
- reg_diag_bg_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_eth_1_write_export : out std_logic; -- export
- reg_diag_bg_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_eth_1_read_export : out std_logic; -- export
- reg_diag_bg_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back0_reset_export : out std_logic; -- export
- reg_eth10g_back0_clk_export : out std_logic; -- export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back0_write_export : out std_logic; -- export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back0_read_export : out std_logic; -- export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back1_reset_export : out std_logic; -- export
- reg_eth10g_back1_clk_export : out std_logic; -- export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back1_write_export : out std_logic; -- export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back1_read_export : out std_logic; -- export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_eth_1_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_1_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_1_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_tx_eth_1_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_1_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_1_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_eth_1_reset_export : out std_logic; -- export
- reg_hdr_dat_eth_1_clk_export : out std_logic; -- export
- reg_hdr_dat_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
- reg_hdr_dat_eth_1_write_export : out std_logic; -- export
- reg_hdr_dat_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_eth_1_read_export : out std_logic; -- export
- reg_hdr_dat_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_rx_eth_1_reset_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_clk_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
- reg_strobe_total_count_rx_eth_1_write_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_rx_eth_1_read_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_tx_eth_1_reset_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_clk_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
- reg_strobe_total_count_tx_eth_1_write_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_tx_eth_1_read_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_eth_0_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_0_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_0_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_tx_eth_0_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_0_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_0_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_eth_0_reset_export : out std_logic; -- export
- reg_hdr_dat_eth_0_clk_export : out std_logic; -- export
- reg_hdr_dat_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_eth_0_write_export : out std_logic; -- export
- reg_hdr_dat_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_eth_0_read_export : out std_logic; -- export
- reg_hdr_dat_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_rx_eth_0_reset_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_clk_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
- reg_strobe_total_count_rx_eth_0_write_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_rx_eth_0_read_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_tx_eth_0_reset_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_clk_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
- reg_strobe_total_count_tx_eth_0_write_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_tx_eth_0_read_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_reset_export : out std_logic; -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back0_write_export : out std_logic; -- export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back0_read_export : out std_logic; -- export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back1_write_export : out std_logic; -- export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back1_read_export : out std_logic; -- export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_unb2c_test;
+ component qsys_unb2c_test is
+ port (
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_1_reset_export : out std_logic; -- export
+ avs_eth_1_clk_export : out std_logic; -- export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_tse_write_export : out std_logic; -- export
+ avs_eth_1_tse_read_export : out std_logic; -- export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_1_reg_write_export : out std_logic; -- export
+ avs_eth_1_reg_read_export : out std_logic; -- export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_ram_write_export : out std_logic; -- export
+ avs_eth_1_ram_read_export : out std_logic; -- export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_irq_export : in std_logic := 'X'; -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_eth_0_reset_export : out std_logic; -- export
+ reg_diag_bg_eth_0_clk_export : out std_logic; -- export
+ reg_diag_bg_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_bg_eth_0_write_export : out std_logic; -- export
+ reg_diag_bg_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_eth_0_read_export : out std_logic; -- export
+ reg_diag_bg_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_eth_1_reset_export : out std_logic; -- export
+ reg_diag_bg_eth_1_clk_export : out std_logic; -- export
+ reg_diag_bg_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_eth_1_write_export : out std_logic; -- export
+ reg_diag_bg_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_eth_1_read_export : out std_logic; -- export
+ reg_diag_bg_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back0_reset_export : out std_logic; -- export
+ reg_eth10g_back0_clk_export : out std_logic; -- export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back0_write_export : out std_logic; -- export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back0_read_export : out std_logic; -- export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back1_reset_export : out std_logic; -- export
+ reg_eth10g_back1_clk_export : out std_logic; -- export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back1_write_export : out std_logic; -- export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back1_read_export : out std_logic; -- export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_eth_1_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_1_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_1_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_tx_eth_1_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_1_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_1_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_eth_1_reset_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_clk_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_hdr_dat_eth_1_write_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_eth_1_read_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_rx_eth_1_reset_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_clk_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_strobe_total_count_rx_eth_1_write_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_rx_eth_1_read_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_tx_eth_1_reset_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_clk_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_strobe_total_count_tx_eth_1_write_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_tx_eth_1_read_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_eth_0_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_0_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_0_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_tx_eth_0_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_0_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_0_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_eth_0_reset_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_clk_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_eth_0_write_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_eth_0_read_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_rx_eth_0_reset_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_clk_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_strobe_total_count_rx_eth_0_write_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_rx_eth_0_read_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_tx_eth_0_reset_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_clk_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_strobe_total_count_tx_eth_0_write_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_tx_eth_0_read_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_reset_export : out std_logic; -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_unb2c_test;
end qsys_unb2c_test_pkg;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
index bb282b576a..5f1e1db454 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, unb2c_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb2c_test_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb2c_test_pkg.all;
+ use technology_lib.technology_pkg.all;
entity udp_stream is
generic (
@@ -102,14 +102,15 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable (disabled by default)
+ '0', -- enable_sync
+ TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
constant c_nof_crc_words : natural := 1;
constant c_max_nof_words_per_block : natural := g_bg_block_size;
@@ -150,127 +151,127 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl
--- g_use_tx_seq => TRUE
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ -- g_use_tx_seq => TRUE
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
- --reg_mosi => reg_dp_offload_tx_mosi,
- --reg_miso => reg_dp_offload_tx_miso,
- --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ --reg_mosi => reg_dp_offload_tx_mosi,
+ --reg_miso => reg_dp_offload_tx_miso,
+ --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
@@ -291,52 +292,52 @@ begin
end generate;
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index bed4ac8d3e..a5ab34ae20 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -21,22 +21,22 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, tech_jesd204b_lib, util_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use eth_lib.eth_tester_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb2c_test_pkg.all;
-use util_lib.util_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use eth_lib.eth_tester_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb2c_test_pkg.all;
+ use util_lib.util_heater_pkg.all;
entity unb2c_test is
generic (
@@ -337,7 +337,7 @@ architecture str of unb2c_test is
signal serial_10G_tx_back_arr : std_logic_vector(c_nof_streams_back0 - 1 downto 0) := (others => '0');
signal serial_10G_rx_back_arr : std_logic_vector(c_nof_streams_back0 - 1 downto 0);
--- SIGNAL serial_rx_jesd204b_back_arr : STD_LOGIC_VECTOR(24-1 DOWNTO 0);
+ -- SIGNAL serial_rx_jesd204b_back_arr : STD_LOGIC_VECTOR(24-1 DOWNTO 0);
signal reg_10gbase_r_24_mosi : t_mem_mosi;
signal reg_10gbase_r_24_miso : t_mem_miso;
@@ -471,327 +471,327 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_base_ip => c_base_ip, -- = X"0A63" is base IP address used by unb_osy: 10.99.xx.yy
- g_udp_offload => c_use_eth_0_UDP,
- g_udp_offload_nof_streams => c_nof_udp_streams_eth_0,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
-
- ext_clk200 => ext_clk200,
- ext_rst200 => ext_rst200,
-
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_mm_rst => eth_0_mm_rst,
- eth1g_tse_mosi => eth_0_tse_mosi,
- eth1g_tse_miso => eth_0_tse_miso,
- eth1g_reg_mosi => eth_0_reg_mosi,
- eth1g_reg_miso => eth_0_reg_miso,
- eth1g_reg_interrupt => eth_0_reg_interrupt,
- eth1g_ram_mosi => eth_0_ram_mosi,
- eth1g_ram_miso => eth_0_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth_0_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth_0_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth_0_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth_0_udp_rx_siso_arr,
-
- -- scrap ram
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK(0),
- ETH_SGIN => ETH_SGIN(0),
- ETH_SGOUT => ETH_SGOUT(0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_base_ip => c_base_ip, -- = X"0A63" is base IP address used by unb_osy: 10.99.xx.yy
+ g_udp_offload => c_use_eth_0_UDP,
+ g_udp_offload_nof_streams => c_nof_udp_streams_eth_0,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+
+ ext_clk200 => ext_clk200,
+ ext_rst200 => ext_rst200,
+
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_mm_rst => eth_0_mm_rst,
+ eth1g_tse_mosi => eth_0_tse_mosi,
+ eth1g_tse_miso => eth_0_tse_miso,
+ eth1g_reg_mosi => eth_0_reg_mosi,
+ eth1g_reg_miso => eth_0_reg_miso,
+ eth1g_reg_interrupt => eth_0_reg_interrupt,
+ eth1g_ram_mosi => eth_0_ram_mosi,
+ eth1g_ram_miso => eth_0_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth_0_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth_0_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth_0_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth_0_udp_rx_siso_arr,
+
+ -- scrap ram
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK(0),
+ ETH_SGIN => ETH_SGIN(0),
+ ETH_SGOUT => ETH_SGOUT(0)
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2c_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_technology => g_technology,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr,
- g_nof_streams_qsfp => c_unb2c_board_tr_qsfp.nof_bus * c_unb2c_board_tr_qsfp.bus_w,
- g_nof_streams_ring => c_unb2c_board_tr_ring.nof_bus * c_unb2c_board_tr_ring.bus_w,
- g_nof_streams_back0 => c_unb2c_board_tr_back.bus_w
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth_0_mm_rst => eth_0_mm_rst,
- eth_0_tse_mosi => eth_0_tse_mosi,
- eth_0_tse_miso => eth_0_tse_miso,
- eth_0_reg_mosi => eth_0_reg_mosi,
- eth_0_reg_miso => eth_0_reg_miso,
- eth_0_reg_interrupt => eth_0_reg_interrupt,
- eth_0_ram_mosi => eth_0_ram_mosi,
- eth_0_ram_miso => eth_0_ram_miso,
-
- reg_diag_bg_eth_0_copi => reg_diag_bg_eth_0_copi,
- reg_diag_bg_eth_0_cipo => reg_diag_bg_eth_0_cipo,
- reg_hdr_dat_eth_0_copi => reg_hdr_dat_eth_0_copi,
- reg_hdr_dat_eth_0_cipo => reg_hdr_dat_eth_0_cipo,
- reg_bsn_monitor_v2_tx_eth_0_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
- reg_bsn_monitor_v2_tx_eth_0_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
- reg_strobe_total_count_tx_eth_0_copi => reg_strobe_total_count_tx_eth_0_copi,
- reg_strobe_total_count_tx_eth_0_cipo => reg_strobe_total_count_tx_eth_0_cipo,
-
- reg_bsn_monitor_v2_rx_eth_0_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
- reg_bsn_monitor_v2_rx_eth_0_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
- reg_strobe_total_count_rx_eth_0_copi => reg_strobe_total_count_rx_eth_0_copi,
- reg_strobe_total_count_rx_eth_0_cipo => reg_strobe_total_count_rx_eth_0_cipo,
-
- -- eth1g ch1
- eth_1_mm_rst => eth_1_mm_rst,
- eth_1_tse_mosi => eth_1_tse_mosi,
- eth_1_tse_miso => eth_1_tse_miso,
- eth_1_reg_mosi => OPEN,
- eth_1_reg_miso => c_mem_cipo_rst,
- eth_1_reg_interrupt => '0',
- eth_1_ram_mosi => OPEN,
- eth_1_ram_miso => c_mem_cipo_rst,
-
- reg_diag_bg_eth_1_copi => reg_diag_bg_eth_1_copi,
- reg_diag_bg_eth_1_cipo => reg_diag_bg_eth_1_cipo,
- reg_hdr_dat_eth_1_copi => reg_hdr_dat_eth_1_copi,
- reg_hdr_dat_eth_1_cipo => reg_hdr_dat_eth_1_cipo,
- reg_bsn_monitor_v2_tx_eth_1_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
- reg_bsn_monitor_v2_tx_eth_1_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
- reg_strobe_total_count_tx_eth_1_copi => reg_strobe_total_count_tx_eth_1_copi,
- reg_strobe_total_count_tx_eth_1_cipo => reg_strobe_total_count_tx_eth_1_cipo,
-
- reg_bsn_monitor_v2_rx_eth_1_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
- reg_bsn_monitor_v2_rx_eth_1_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
- reg_strobe_total_count_rx_eth_1_copi => reg_strobe_total_count_rx_eth_1_copi,
- reg_strobe_total_count_rx_eth_1_cipo => reg_strobe_total_count_rx_eth_1_cipo,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- heater:
- reg_heater_mosi => reg_heater_mosi,
- reg_heater_miso => reg_heater_miso,
-
- -- block gen
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- bsn
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- 10GbE
-
- --reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- --reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
-
- reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
-
- reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
- reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
-
- -- eth10g status
- reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
-
- reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_back0_miso => reg_eth10g_back0_miso,
-
- -- DDR4 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR4 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- -- Jesd reset control
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
-
- -- Scrap RAM
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_technology => g_technology,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_nof_streams_qsfp => c_unb2c_board_tr_qsfp.nof_bus * c_unb2c_board_tr_qsfp.bus_w,
+ g_nof_streams_ring => c_unb2c_board_tr_ring.nof_bus * c_unb2c_board_tr_ring.bus_w,
+ g_nof_streams_back0 => c_unb2c_board_tr_back.bus_w
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth_0_mm_rst => eth_0_mm_rst,
+ eth_0_tse_mosi => eth_0_tse_mosi,
+ eth_0_tse_miso => eth_0_tse_miso,
+ eth_0_reg_mosi => eth_0_reg_mosi,
+ eth_0_reg_miso => eth_0_reg_miso,
+ eth_0_reg_interrupt => eth_0_reg_interrupt,
+ eth_0_ram_mosi => eth_0_ram_mosi,
+ eth_0_ram_miso => eth_0_ram_miso,
+
+ reg_diag_bg_eth_0_copi => reg_diag_bg_eth_0_copi,
+ reg_diag_bg_eth_0_cipo => reg_diag_bg_eth_0_cipo,
+ reg_hdr_dat_eth_0_copi => reg_hdr_dat_eth_0_copi,
+ reg_hdr_dat_eth_0_cipo => reg_hdr_dat_eth_0_cipo,
+ reg_bsn_monitor_v2_tx_eth_0_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
+ reg_bsn_monitor_v2_tx_eth_0_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
+ reg_strobe_total_count_tx_eth_0_copi => reg_strobe_total_count_tx_eth_0_copi,
+ reg_strobe_total_count_tx_eth_0_cipo => reg_strobe_total_count_tx_eth_0_cipo,
+
+ reg_bsn_monitor_v2_rx_eth_0_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
+ reg_bsn_monitor_v2_rx_eth_0_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
+ reg_strobe_total_count_rx_eth_0_copi => reg_strobe_total_count_rx_eth_0_copi,
+ reg_strobe_total_count_rx_eth_0_cipo => reg_strobe_total_count_rx_eth_0_cipo,
+
+ -- eth1g ch1
+ eth_1_mm_rst => eth_1_mm_rst,
+ eth_1_tse_mosi => eth_1_tse_mosi,
+ eth_1_tse_miso => eth_1_tse_miso,
+ eth_1_reg_mosi => OPEN,
+ eth_1_reg_miso => c_mem_cipo_rst,
+ eth_1_reg_interrupt => '0',
+ eth_1_ram_mosi => OPEN,
+ eth_1_ram_miso => c_mem_cipo_rst,
+
+ reg_diag_bg_eth_1_copi => reg_diag_bg_eth_1_copi,
+ reg_diag_bg_eth_1_cipo => reg_diag_bg_eth_1_cipo,
+ reg_hdr_dat_eth_1_copi => reg_hdr_dat_eth_1_copi,
+ reg_hdr_dat_eth_1_cipo => reg_hdr_dat_eth_1_cipo,
+ reg_bsn_monitor_v2_tx_eth_1_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
+ reg_bsn_monitor_v2_tx_eth_1_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
+ reg_strobe_total_count_tx_eth_1_copi => reg_strobe_total_count_tx_eth_1_copi,
+ reg_strobe_total_count_tx_eth_1_cipo => reg_strobe_total_count_tx_eth_1_cipo,
+
+ reg_bsn_monitor_v2_rx_eth_1_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
+ reg_bsn_monitor_v2_rx_eth_1_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
+ reg_strobe_total_count_rx_eth_1_copi => reg_strobe_total_count_rx_eth_1_copi,
+ reg_strobe_total_count_rx_eth_1_cipo => reg_strobe_total_count_rx_eth_1_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- heater:
+ reg_heater_mosi => reg_heater_mosi,
+ reg_heater_miso => reg_heater_miso,
+
+ -- block gen
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
+
+ -- bsn
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
+
+ -- databuffer
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- 10GbE
+
+ --reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ --reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+
+ reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
+
+ reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
+ reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
+
+ -- eth10g status
+ reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
+
+ reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_back0_miso => reg_eth10g_back0_miso,
+
+ -- DDR4 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR4 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ -- Jesd reset control
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+
+ -- Scrap RAM
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
gen_eth_0_udp : if c_use_eth_0_UDP = true generate
-- Derive MAC/IP/UDP from gn_index
@@ -801,48 +801,48 @@ begin
-- Generate UDP Tx and monitor UDP Rx
u_eth_tester_I : entity eth_lib.eth_tester
- generic map (
- g_nof_streams => c_nof_udp_streams_eth_0,
- g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
- g_remove_crc => true -- use TRUE when using TSE link interface
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
- st_pps => dp_pps,
-
- -- UDP transmit interface
- eth_src_mac => gn_eth_src_mac_I,
- ip_src_addr => gn_ip_src_addr_I,
- udp_src_port => gn_udp_src_port_I,
-
- tx_fifo_rd_emp_arr => OPEN,
-
- tx_udp_sosi_arr => eth_0_udp_tx_sosi_arr,
- tx_udp_siso_arr => eth_0_udp_tx_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => eth_0_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- -- . Tx
- reg_bg_ctrl_copi => reg_diag_bg_eth_0_copi,
- reg_bg_ctrl_cipo => reg_diag_bg_eth_0_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_eth_0_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_eth_0_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_0_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_0_cipo,
- -- . Rx
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_0_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_0_cipo
- );
+ generic map (
+ g_nof_streams => c_nof_udp_streams_eth_0,
+ g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
+ g_remove_crc => true -- use TRUE when using TSE link interface
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+ st_pps => dp_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => gn_eth_src_mac_I,
+ ip_src_addr => gn_ip_src_addr_I,
+ udp_src_port => gn_udp_src_port_I,
+
+ tx_fifo_rd_emp_arr => OPEN,
+
+ tx_udp_sosi_arr => eth_0_udp_tx_sosi_arr,
+ tx_udp_siso_arr => eth_0_udp_tx_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => eth_0_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ -- . Tx
+ reg_bg_ctrl_copi => reg_diag_bg_eth_0_copi,
+ reg_bg_ctrl_cipo => reg_diag_bg_eth_0_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_eth_0_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_eth_0_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_0_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_0_cipo,
+ -- . Rx
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_0_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_0_cipo
+ );
-- Uses eth.vhd with ETH/TSE interface with UDP streams in ctrl_unb2c_board
-- to stream UDP data via eth_0 = 1GbE-I.
@@ -858,218 +858,218 @@ begin
-- Generate UDP Tx and monitor UDP Rx
u_eth_tester_II : entity eth_lib.eth_tester
- generic map (
- g_nof_streams => c_nof_udp_streams_eth_1,
- g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
- g_remove_crc => true -- use TRUE when using TSE link interface
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
- st_pps => dp_pps,
-
- -- UDP transmit interface
- eth_src_mac => gn_eth_src_mac_II,
- ip_src_addr => gn_ip_src_addr_II,
- udp_src_port => gn_udp_src_port_II,
-
- tx_fifo_rd_emp_arr => OPEN,
-
- tx_udp_sosi_arr => eth_1_udp_tx_sosi_arr,
- tx_udp_siso_arr => eth_1_udp_tx_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => eth_1_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- -- . Tx
- reg_bg_ctrl_copi => reg_diag_bg_eth_1_copi,
- reg_bg_ctrl_cipo => reg_diag_bg_eth_1_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_eth_1_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_eth_1_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_1_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_1_cipo,
- -- . Rx
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_1_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_1_cipo
- );
+ generic map (
+ g_nof_streams => c_nof_udp_streams_eth_1,
+ g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
+ g_remove_crc => true -- use TRUE when using TSE link interface
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+ st_pps => dp_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => gn_eth_src_mac_II,
+ ip_src_addr => gn_ip_src_addr_II,
+ udp_src_port => gn_udp_src_port_II,
+
+ tx_fifo_rd_emp_arr => OPEN,
+
+ tx_udp_sosi_arr => eth_1_udp_tx_sosi_arr,
+ tx_udp_siso_arr => eth_1_udp_tx_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => eth_1_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ -- . Tx
+ reg_bg_ctrl_copi => reg_diag_bg_eth_1_copi,
+ reg_bg_ctrl_cipo => reg_diag_bg_eth_1_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_eth_1_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_eth_1_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_1_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_1_cipo,
+ -- . Rx
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_1_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_1_cipo
+ );
-- Use eth_stream with ETH/TSE interface for UDP port g_rx_udp_port to
-- stream UDP data via eth_1 = 1GbE-II
u_eth_stream : entity eth_lib.eth_stream
- generic map (
- g_technology => g_technology,
- g_rx_udp_port => TO_UINT(c_eth_rx_udp_port), -- = 0x1771 = 6001
- g_jumbo_en => true,
- g_sim => g_sim,
- g_sim_level => 1 -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst, -- eth_1_mm_rst
- mm_clk => mm_clk,
- eth_clk => ETH_CLK(1),
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- TSE setup
- src_mac => gn_eth_src_mac_II,
- setup_done => OPEN,
-
- -- UDP transmit interface
- udp_tx_snk_in => eth_1_udp_tx_sosi_arr(0),
- udp_tx_snk_out => eth_1_udp_tx_siso_arr(0),
-
- -- UDP receive interface
- udp_rx_src_in => c_dp_siso_rdy,
- udp_rx_src_out => eth_1_udp_rx_sosi_arr(0),
-
- -- Memory Mapped Slaves
- tse_ctlr_copi => eth_1_tse_mosi,
- tse_ctlr_cipo => eth_1_tse_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT(1),
- eth_rxp => ETH_SGIN(1),
-
- -- LED interface
- tse_led => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_rx_udp_port => TO_UINT(c_eth_rx_udp_port), -- = 0x1771 = 6001
+ g_jumbo_en => true,
+ g_sim => g_sim,
+ g_sim_level => 1 -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst, -- eth_1_mm_rst
+ mm_clk => mm_clk,
+ eth_clk => ETH_CLK(1),
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- TSE setup
+ src_mac => gn_eth_src_mac_II,
+ setup_done => OPEN,
+
+ -- UDP transmit interface
+ udp_tx_snk_in => eth_1_udp_tx_sosi_arr(0),
+ udp_tx_snk_out => eth_1_udp_tx_siso_arr(0),
+
+ -- UDP receive interface
+ udp_rx_src_in => c_dp_siso_rdy,
+ udp_rx_src_out => eth_1_udp_rx_sosi_arr(0),
+
+ -- Memory Mapped Slaves
+ tse_ctlr_copi => eth_1_tse_mosi,
+ tse_ctlr_cipo => eth_1_tse_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT(1),
+ eth_rxp => ETH_SGIN(1),
+
+ -- LED interface
+ tse_led => open
+ );
end generate;
gen_udp_stream_10GbE : if c_use_10GbE = true and c_use_loopback = false generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_bg_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ID => ID,
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- loopback:
- --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
- --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
-
- -- connect to dp_offload:
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ID => ID,
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+ -- loopback:
+ --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
+ --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ -- connect to dp_offload:
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
end generate;
gen_jesd204b : if c_use_jesd204b = true generate
u_jesd204b: entity work.node_adc_input_and_timing_nowg
- generic map(
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_jesd204b,
- g_jesd_freq => "200MHz",
- g_nof_sync_n => c_unb2c_board_nof_sync_jesd204b,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => BCK_RX(c_nof_streams_jesd204b - 1 downto 0),
- jesd204b_refclk => BCK_REF_CLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC
- );
+ generic map(
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_jesd204b,
+ g_jesd_freq => "200MHz",
+ g_nof_sync_n => c_unb2c_board_nof_sync_jesd204b,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => BCK_RX(c_nof_streams_jesd204b - 1 downto 0),
+ jesd204b_refclk => BCK_REF_CLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC
+ );
end generate;
gen_front_10GbE : if c_use_10GbE = true generate
u_tr_10GbE_qsfp_and_ring: entity unb2c_board_10gbe_lib.unb2c_board_10gbe -- QSFP and Ring lines
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_use_loopback => c_use_loopback,
- g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk => SA_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
- reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
- --reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- --reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_use_loopback => c_use_loopback,
+ g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SA_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+ reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
+ --reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ --reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
- serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
- );
+ serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
+ serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
+ );
gen_qsfp_wires: for i in 0 to c_nof_streams_qsfp - 1 generate
- serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
+ serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
@@ -1088,24 +1088,24 @@ begin
QSFP_5_TX <= i_QSFP_TX(5);
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_qsfp_arr,
- serial_rx_arr => serial_10G_rx_qsfp_arr,
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_qsfp_arr,
+ serial_rx_arr => serial_10G_rx_qsfp_arr,
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
gen_ring_wires: for i in 0 to c_nof_streams_ring - 1 generate
- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i + c_nof_streams_qsfp);
+ serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i + c_nof_streams_qsfp);
i_serial_10G_rx_qsfp_ring_arr(i + c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
end generate;
@@ -1115,45 +1115,45 @@ begin
RING_1_TX <= i_RING_TX(1);
u_ring_io : entity unb2c_board_lib.unb2c_board_ring_io
- generic map (
- g_nof_ring_bus => 2 -- c_nof_ring_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_ring_arr,
- serial_rx_arr => serial_10G_rx_ring_arr,
- RING_RX => i_RING_RX,
- RING_TX => i_RING_TX
- );
-
- gen_10gbe_back0 : if c_use_10GbE_back0 = true generate
- u_tr_10GbE_back: entity unb2c_board_10gbe_lib.unb2c_board_10gbe -- BACK lines (upper)
generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_use_loopback => c_use_loopback,
- g_nof_macs => c_nof_streams_back0,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
+ g_nof_ring_bus => 2 -- c_nof_ring_bus
)
port map (
- tr_ref_clk => SB_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
- reg_mac_miso => reg_tr_10GbE_back0_miso,
- reg_eth10g_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_miso => reg_eth10g_back0_miso,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
- serial_tx_arr => i_serial_10G_tx_back0_arr,
- serial_rx_arr => i_serial_10G_rx_back0_arr
+ serial_tx_arr => serial_10G_tx_ring_arr,
+ serial_rx_arr => serial_10G_rx_ring_arr,
+ RING_RX => i_RING_RX,
+ RING_TX => i_RING_TX
);
+
+ gen_10gbe_back0 : if c_use_10GbE_back0 = true generate
+ u_tr_10GbE_back: entity unb2c_board_10gbe_lib.unb2c_board_10gbe -- BACK lines (upper)
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_use_loopback => c_use_loopback,
+ g_nof_macs => c_nof_streams_back0,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SB_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_back0_mosi,
+ reg_mac_miso => reg_tr_10GbE_back0_miso,
+ reg_eth10g_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_miso => reg_eth10g_back0_miso,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
+ serial_tx_arr => i_serial_10G_tx_back0_arr,
+ serial_rx_arr => i_serial_10G_rx_back0_arr
+ );
end generate;
gen_back_wiring : if c_use_10GbE_back0 = true generate
@@ -1163,92 +1163,92 @@ begin
end generate;
u_back_io : entity unb2c_board_lib.unb2c_board_back_io
- generic map (
- g_nof_back_bus => c_nof_back_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_back_arr,
- serial_rx_arr => serial_10G_rx_back_arr,
-
- -- Serial I/O
- -- back transceivers
- BCK_RX(0) => BCK_RX(c_nof_streams_back0 - 1 downto 0),
- BCK_TX(0) => BCK_TX(c_nof_streams_back0 - 1 downto 0)
- );
+ generic map (
+ g_nof_back_bus => c_nof_back_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_back_arr,
+ serial_rx_arr => serial_10G_rx_back_arr,
+
+ -- Serial I/O
+ -- back transceivers
+ BCK_RX(0) => BCK_RX(c_nof_streams_back0 - 1 downto 0),
+ BCK_TX(0) => BCK_TX(c_nof_streams_back0 - 1 downto 0)
+ );
end generate;
--- gen_jesd204b_wiring : IF c_use_jesd204b = TRUE GENERATE
--- gen_jesd204b_wires: FOR i IN 0 TO c_nof_streams_jesd204b-1 GENERATE
--- serial_rx_jesd204b_arr(i) <= serial_rx_jesd204b_back_arr(i);
--- END GENERATE;
---
--- u_back_io : ENTITY unb2c_board_lib.unb2c_board_back_io
--- GENERIC MAP (
--- g_nof_back_bus => 1
--- )
--- PORT MAP (
--- --serial_tx_arr => serial_10G_tx_back_arr,
--- serial_rx_arr => serial_rx_jesd204b_back_arr,
---
--- -- Serial I/O
--- -- back transceivers
--- BCK_RX(0) => BCK_RX(c_nof_streams_jesd204b-1 downto 0),
--- BCK_TX(0) => open
--- );
--- END GENERATE;
+ -- gen_jesd204b_wiring : IF c_use_jesd204b = TRUE GENERATE
+ -- gen_jesd204b_wires: FOR i IN 0 TO c_nof_streams_jesd204b-1 GENERATE
+ -- serial_rx_jesd204b_arr(i) <= serial_rx_jesd204b_back_arr(i);
+ -- END GENERATE;
+ --
+ -- u_back_io : ENTITY unb2c_board_lib.unb2c_board_back_io
+ -- GENERIC MAP (
+ -- g_nof_back_bus => 1
+ -- )
+ -- PORT MAP (
+ -- --serial_tx_arr => serial_10G_tx_back_arr,
+ -- serial_rx_arr => serial_rx_jesd204b_back_arr,
+ --
+ -- -- Serial I/O
+ -- -- back transceivers
+ -- BCK_RX(0) => BCK_RX(c_nof_streams_jesd204b-1 downto 0),
+ -- BCK_TX(0) => open
+ -- );
+ -- END GENERATE;
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2c_board_ext_clk_freq_200M) -- nof clk cycles to get us period
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_unb2c_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
- tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
- rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
+ rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
- );
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ );
end generate;
gen_no_udp_stream_10GbE : if c_use_10GbE = false generate
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
end generate;
-----------------------------------------------------------------------------
@@ -1259,183 +1259,183 @@ begin
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => c_ddr_MB_I,
+ -- IO_DDR
+ g_io_tech_ddr => c_ddr_MB_I,
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_I_clk200,
- ctlr_rst_out => ddr_I_rst200,
-
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_I_clk200,
+ ctlr_rst_out => ddr_I_rst200,
+
+ ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
gen_stream_MB_II : if c_use_MB_II = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => c_ddr_MB_II,
+ -- IO_DDR
+ g_io_tech_ddr => c_ddr_MB_II,
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_II_REF_CLK,
- ctlr_ref_rst => mb_II_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_II_clk200,
- ctlr_rst_out => ddr_II_rst200,
-
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_II_IN,
- phy4_io => MB_II_IO,
- phy4_ou => MB_II_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_II_REF_CLK,
+ ctlr_ref_rst => mb_II_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_II_clk200,
+ ctlr_rst_out => ddr_II_rst200,
+
+ ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_II_IN,
+ phy4_io => MB_II_IO,
+ phy4_ou => MB_II_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
gen_heater : if c_use_heater = true generate
u_heater : entity util_lib.util_heater
- generic map (
- g_technology => g_technology,
- --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
- --g_nof_mac4 => 630 --
+ generic map (
+ g_technology => g_technology,
+ --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
+ --g_nof_mac4 => 630 --
- --g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
- g_nof_mac4 => 750,
+ --g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
+ g_nof_mac4 => 750,
- g_pipeline => 72, -- max 72
- g_nof_ram => 4, -- max 4
+ g_pipeline => 72, -- max 72
+ g_nof_ram => 4, -- max 4
- g_nof_logic => 24 -- max 24
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ g_nof_logic => 24 -- max 24
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- sla_in => reg_heater_mosi,
- sla_out => reg_heater_miso
- );
+ sla_in => reg_heater_mosi,
+ sla_out => reg_heater_miso
+ );
end generate;
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
index ecd624929c..4bb7e419ad 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
@@ -22,38 +22,39 @@
-- Purpose: Define selections for revisions of the unb2c_test design
library IEEE, common_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
package unb2c_test_pkg is
-- dp_offload_tx (carried over from unb2a_test_pkg
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
+ constant c_hdr_field_arr : t_common_field_arr(
+ c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
@@ -74,21 +75,21 @@ package unb2c_test_pkg is
use_heater : boolean;
type_MB_I : t_c_tech_ddr;
type_MB_II : t_c_tech_ddr;
- end record;
+ end record;
- -- loop 1GbE 1GbE qsfp ring bk0 jesd DDR4 DDR4 heatr
- constant c_test_minimal : t_unb2c_test_config := (false,false,false,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_1GbE_I_UDP : t_unb2c_test_config := (false, true,false,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_1GbE_II_UDP : t_unb2c_test_config := (false, true, true,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_10GbE : t_unb2c_test_config := (false,false,false, true, true,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_10GbE_qb : t_unb2c_test_config := (false,false,false, true,false, true,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_ddr : t_unb2c_test_config := (false,false,false,false,false,false,false, true, true,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_ddr_16G : t_unb2c_test_config := (false,false,false,false,false,false,false, true, true,false,c_tech_ddr4_16g_1600m_64, c_tech_ddr4_16g_1600m_72_64);
- constant c_test_heater : t_unb2c_test_config := (false,false,false,false,false,false,false,false,false, true,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_jesd204b : t_unb2c_test_config := (false,false,false,false,false,false, true,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ -- loop 1GbE 1GbE qsfp ring bk0 jesd DDR4 DDR4 heatr
+ constant c_test_minimal : t_unb2c_test_config := (false,false,false,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_1GbE_I_UDP : t_unb2c_test_config := (false, true,false,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_1GbE_II_UDP : t_unb2c_test_config := (false, true, true,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_10GbE : t_unb2c_test_config := (false,false,false, true, true,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_10GbE_qb : t_unb2c_test_config := (false,false,false, true,false, true,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_ddr : t_unb2c_test_config := (false,false,false,false,false,false,false, true, true,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_ddr_16G : t_unb2c_test_config := (false,false,false,false,false,false,false, true, true,false,c_tech_ddr4_16g_1600m_64, c_tech_ddr4_16g_1600m_72_64);
+ constant c_test_heater : t_unb2c_test_config := (false,false,false,false,false,false,false,false,false, true,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_jesd204b : t_unb2c_test_config := (false,false,false,false,false,false, true,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- -- Function to select the revision configuration.
- function func_sel_revision_rec(g_design_name : string) return t_unb2c_test_config;
+ -- Function to select the revision configuration.
+ function func_sel_revision_rec(g_design_name : string) return t_unb2c_test_config;
end unb2c_test_pkg;
diff --git a/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
index a34e6633db..6b5ac9bd41 100644
--- a/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
@@ -42,14 +42,14 @@
--
library IEEE, common_lib, unb2c_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb2c_test is
generic (
@@ -161,97 +161,97 @@ begin
-- DUT
------------------------------------------------------------------------------
u_unb2c_test : entity work.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_sim_model_ddr => g_sim_model_ddr
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => sa_clk,
- SB_CLK => sb_clk,
- BCK_REF_CLK => bck_ref_clk,
-
- -- DDR reference clocks
- MB_I_REF_CLK => mb_I_ref_clk,
- MB_II_REF_CLK => mb_II_ref_clk,
-
- -- Serial I/O
--- QSFP_0_TX => si_lpbk_0,
--- QSFP_0_RX => si_lpbk_0,
--- QSFP_1_TX => si_lpbk_1,
--- QSFP_1_RX => si_lpbk_1,
--- QSFP_2_TX => si_lpbk_2,
--- QSFP_2_RX => si_lpbk_2,
--- QSFP_3_TX => si_lpbk_3,
--- QSFP_3_RX => si_lpbk_3,
--- QSFP_4_TX => si_lpbk_4,
--- QSFP_4_RX => si_lpbk_4,
--- QSFP_5_TX => si_lpbk_5,
--- QSFP_5_RX => si_lpbk_5,
---
--- RING_0_TX => si_lpbk_6,
--- RING_0_RX => si_lpbk_6,
--- RING_1_TX => si_lpbk_7,
--- RING_1_RX => si_lpbk_7,
---
--- BCK_TX => si_lpbk_8,
--- BCK_RX => si_lpbk_8,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- -- Leds
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_sim_model_ddr => g_sim_model_ddr
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+ SB_CLK => sb_clk,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => mb_I_ref_clk,
+ MB_II_REF_CLK => mb_II_ref_clk,
+
+ -- Serial I/O
+ -- QSFP_0_TX => si_lpbk_0,
+ -- QSFP_0_RX => si_lpbk_0,
+ -- QSFP_1_TX => si_lpbk_1,
+ -- QSFP_1_RX => si_lpbk_1,
+ -- QSFP_2_TX => si_lpbk_2,
+ -- QSFP_2_RX => si_lpbk_2,
+ -- QSFP_3_TX => si_lpbk_3,
+ -- QSFP_3_RX => si_lpbk_3,
+ -- QSFP_4_TX => si_lpbk_4,
+ -- QSFP_4_RX => si_lpbk_4,
+ -- QSFP_5_TX => si_lpbk_5,
+ -- QSFP_5_RX => si_lpbk_5,
+ --
+ -- RING_0_TX => si_lpbk_6,
+ -- RING_0_RX => si_lpbk_6,
+ -- RING_1_TX => si_lpbk_7,
+ -- RING_1_RX => si_lpbk_7,
+ --
+ -- BCK_TX => si_lpbk_8,
+ -- BCK_RX => si_lpbk_8,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ -- Leds
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- UniBoard DDR4
------------------------------------------------------------------------------
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_I
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_I_OU,
- mem4_io => MB_I_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_I
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_I_OU,
+ mem4_io => MB_I_IO
+ );
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_II
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_II_OU,
- mem4_io => MB_II_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_II
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_II_OU,
+ mem4_io => MB_II_IO
+ );
end tb;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
index 2b7934b9c8..e9e9b6e1a6 100644
--- a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
@@ -41,91 +41,91 @@
-- --------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_unsigned.all;
entity bscan2 is
- -- enter the number of BSCAN2 blocks to create. This is the only place that
- -- needs to be modified to control the number of local scan ports created.
- generic ( bscan_ports : positive := 2 );
- port( TDI, TCK, TMS : in std_logic;
- TRST : in std_logic;
- -- Turn on slow slew in fitter for output signals
- TDO : out std_logic;
- -- OE control for MSP ports (Active high)
- ENABLE_MSP : in std_logic;
- MSPTCK : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTDI : in std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTDO : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTMS : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTRST : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- -- one set of addresses to check for device
- IDN : in std_logic_vector(3 downto 0)
- );
-end;
+ -- enter the number of BSCAN2 blocks to create. This is the only place that
+ -- needs to be modified to control the number of local scan ports created.
+ generic ( bscan_ports : positive := 2 );
+ port( TDI, TCK, TMS : in std_logic;
+ TRST : in std_logic;
+ -- Turn on slow slew in fitter for output signals
+ TDO : out std_logic;
+ -- OE control for MSP ports (Active high)
+ ENABLE_MSP : in std_logic;
+ MSPTCK : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTDI : in std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTDO : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTMS : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTRST : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ -- one set of addresses to check for device
+ IDN : in std_logic_vector(3 downto 0)
+ );
+ end;
architecture behave of bscan2 is
- component top_linker is
- -- do not use the generic map to prevent the synthesis tool from
- -- appending the number of ports to the components name.
- port(TDI, TCK, TMS : in std_logic;
- TRST : in std_logic;
- -- enable logic for TDO pins.
- TDO_enable : out std_logic;
- TDO : out std_logic;
- MSPCLK : out std_logic_vector(4 * bscan_ports downto 1);
- MSPTDI : in std_logic_vector(4 * bscan_ports downto 1);
- MSPTDO : out std_logic_vector(4 * bscan_ports downto 1);
- MSPTMS : out std_logic_vector(4 * bscan_ports downto 1);
- MSPTRST : out std_logic_vector(4 * bscan_ports downto 1);
- -- one set of addresses to check for device
- IDN : in std_logic_vector(4 downto 1)
- );
-end component top_linker;
--- synthesis FILE="top_linker.ngo"
+ component top_linker is
+ -- do not use the generic map to prevent the synthesis tool from
+ -- appending the number of ports to the components name.
+ port(TDI, TCK, TMS : in std_logic;
+ TRST : in std_logic;
+ -- enable logic for TDO pins.
+ TDO_enable : out std_logic;
+ TDO : out std_logic;
+ MSPCLK : out std_logic_vector(4 * bscan_ports downto 1);
+ MSPTDI : in std_logic_vector(4 * bscan_ports downto 1);
+ MSPTDO : out std_logic_vector(4 * bscan_ports downto 1);
+ MSPTMS : out std_logic_vector(4 * bscan_ports downto 1);
+ MSPTRST : out std_logic_vector(4 * bscan_ports downto 1);
+ -- one set of addresses to check for device
+ IDN : in std_logic_vector(4 downto 1)
+ );
+ end component top_linker;
+ -- synthesis FILE="top_linker.ngo"
--- logic to enable TDO pins
-signal ENABLE_TDO : std_logic;
--- signal from tap controler that enables all TDOs.
-signal tdoENABLE : std_logic;
--- logic to generate tdo_sp and tdo_hdr
-signal LSPTMS : std_logic_vector(4 * bscan_ports - 1 downto 0);
-signal LSPTCK : std_logic_vector(4 * bscan_ports - 1 downto 0);
-signal LSPTDO : std_logic_vector(4 * bscan_ports - 1 downto 0);
-signal LSPTRST : std_logic_vector(4 * bscan_ports - 1 downto 0);
--- output of Port Mux
-signal TDO_int : std_logic;
+ -- logic to enable TDO pins
+ signal ENABLE_TDO : std_logic;
+ -- signal from tap controler that enables all TDOs.
+ signal tdoENABLE : std_logic;
+ -- logic to generate tdo_sp and tdo_hdr
+ signal LSPTMS : std_logic_vector(4 * bscan_ports - 1 downto 0);
+ signal LSPTCK : std_logic_vector(4 * bscan_ports - 1 downto 0);
+ signal LSPTDO : std_logic_vector(4 * bscan_ports - 1 downto 0);
+ signal LSPTRST : std_logic_vector(4 * bscan_ports - 1 downto 0);
+ -- output of Port Mux
+ signal TDO_int : std_logic;
begin
- -- Wire up all of the tri-state controlled lines automatically
- tri_state_lines : for lvar1 in 0 to (4 * bscan_ports - 1) generate
- MSPTCK(lvar1) <= LSPTCK(lvar1) when ENABLE_MSP = '1' else 'Z';
- MSPTMS(lvar1) <= LSPTMS(lvar1) when ENABLE_MSP = '1' else 'Z';
- MSPTRST(lvar1) <= LSPTRST(lvar1) when ENABLE_MSP = '1' else 'Z';
- -- enable MSPTDOs for 1149.1
- MSPTDO(lvar1) <= LSPTDO(lvar1) when ENABLE_TDO = '1' else 'Z';
- end generate tri_state_lines;
+ -- Wire up all of the tri-state controlled lines automatically
+ tri_state_lines : for lvar1 in 0 to (4 * bscan_ports - 1) generate
+ MSPTCK(lvar1) <= LSPTCK(lvar1) when ENABLE_MSP = '1' else 'Z';
+ MSPTMS(lvar1) <= LSPTMS(lvar1) when ENABLE_MSP = '1' else 'Z';
+ MSPTRST(lvar1) <= LSPTRST(lvar1) when ENABLE_MSP = '1' else 'Z';
+ -- enable MSPTDOs for 1149.1
+ MSPTDO(lvar1) <= LSPTDO(lvar1) when ENABLE_TDO = '1' else 'Z';
+ end generate tri_state_lines;
- -- MSP Port enable controls
- -- enable logic for all TDO pins
- ENABLE_TDO <= ENABLE_MSP and tdoENABLE;
+ -- MSP Port enable controls
+ -- enable logic for all TDO pins
+ ENABLE_TDO <= ENABLE_MSP and tdoENABLE;
- TDO <= TDO_int when tdoENABLE = '1' else 'Z';
+ TDO <= TDO_int when tdoENABLE = '1' else 'Z';
- TopLinkerModule : component top_linker
- port map(
- TDO => TDO_int,
- TMS => TMS,
- TCK => TCK,
- TRST => TRST,
- TDI => TDI,
- TDO_enable => tdoENABLE,
- MSPTDI => MSPTDI,
- MSPTDO => LSPTDO,
- MSPTMS => LSPTMS,
- MSPCLK => LSPTCK,
- MSPTRST => LSPTRST,
- IDN => IDN
- );
+ TopLinkerModule : component top_linker
+ port map(
+ TDO => TDO_int,
+ TMS => TMS,
+ TCK => TCK,
+ TRST => TRST,
+ TDI => TDI,
+ TDO_enable => tdoENABLE,
+ MSPTDI => MSPTDI,
+ MSPTDO => LSPTDO,
+ MSPTMS => LSPTMS,
+ MSPCLK => LSPTCK,
+ MSPTRST => LSPTRST,
+ IDN => IDN
+ );
end behave;
--------------------------------- E O F --------------------------------------
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
index a26751236a..b3169201d3 100644
--- a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
@@ -21,128 +21,128 @@
-------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_unsigned.all;
architecture str of jtag_top is
- component bscan2 is
+ component bscan2 is
-- enter the number of BSCAN2 blocks to create. This is the only place that
-- needs to be modified to control the number of local scan ports created.
- generic (
- bscan_ports : positive := 2
+ generic (
+ bscan_ports : positive := 2
- );
- port (
- TDI, TCK, TMS : in std_logic;
- TRST : in std_logic;
- -- Turn on slow slew in fitter for output signals
- TDO : out std_logic;
- -- OE control for MSP ports (Active high)
- ENABLE_MSP : in std_logic;
- MSPTCK : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTDI : in std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTDO : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTMS : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTRST : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- -- one set of addresses to check for device
- IDN : in std_logic_vector(3 downto 0)
- );
- end component bscan2;
+ );
+ port (
+ TDI, TCK, TMS : in std_logic;
+ TRST : in std_logic;
+ -- Turn on slow slew in fitter for output signals
+ TDO : out std_logic;
+ -- OE control for MSP ports (Active high)
+ ENABLE_MSP : in std_logic;
+ MSPTCK : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTDI : in std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTDO : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTMS : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTRST : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ -- one set of addresses to check for device
+ IDN : in std_logic_vector(3 downto 0)
+ );
+ end component bscan2;
--- internal enable signal for tri-stating the scanbridge
- constant jtag_chains : natural := 5;
- signal ENABLE_SB : std_logic;
- signal TDO_BSCAN : std_logic;
- signal TDA : std_logic;
- signal TDB : std_logic;
- signal TDC : std_logic;
- signal TDD : std_logic;
- signal MSPTDO_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
- signal MSPTCK_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
- signal MSPTMS_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
- signal MSPTRST_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
- begin
- bscan : component bscan2
- port map (
- TDI => TDI,
- TCK => TCK,
- TMS => TMS,
- TRST => TRST,
- TDO => TDO_BSCAN,
- ENABLE_MSP => ENABLE_SB,
- MSPTCK(jtag_chains - 1 downto 0) => MSPTCK_BSCAN,
- MSPTDI(jtag_chains - 1 downto 0) => MSPTDI,
- MSPTDO(jtag_chains - 1 downto 0) => MSPTDO_BSCAN,
- MSPTMS(jtag_chains - 1 downto 0) => MSPTMS_BSCAN,
- MSPTRST(jtag_chains - 1 downto 0) => MSPTRST_BSCAN,
- IDN => "0000"
- );
+ -- internal enable signal for tri-stating the scanbridge
+ constant jtag_chains : natural := 5;
+ signal ENABLE_SB : std_logic;
+ signal TDO_BSCAN : std_logic;
+ signal TDA : std_logic;
+ signal TDB : std_logic;
+ signal TDC : std_logic;
+ signal TDD : std_logic;
+ signal MSPTDO_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
+ signal MSPTCK_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
+ signal MSPTMS_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
+ signal MSPTRST_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
+begin
+ bscan : component bscan2
+ port map (
+ TDI => TDI,
+ TCK => TCK,
+ TMS => TMS,
+ TRST => TRST,
+ TDO => TDO_BSCAN,
+ ENABLE_MSP => ENABLE_SB,
+ MSPTCK(jtag_chains - 1 downto 0) => MSPTCK_BSCAN,
+ MSPTDI(jtag_chains - 1 downto 0) => MSPTDI,
+ MSPTDO(jtag_chains - 1 downto 0) => MSPTDO_BSCAN,
+ MSPTMS(jtag_chains - 1 downto 0) => MSPTMS_BSCAN,
+ MSPTRST(jtag_chains - 1 downto 0) => MSPTRST_BSCAN,
+ IDN => "0000"
+ );
- p_jtagselect: process(TDI,MSPTDI(jtag_chains - 1 downto 0),TCK,TMS,TRST)
- begin
- ENABLE_SB <= '0';
- MSPTDO(jtag_chains - 1 downto 0) <= "ZZZZZ";
- MSPTCK(jtag_chains - 1 downto 0) <= "ZZZZZ";
- MSPTMS(jtag_chains - 1 downto 0) <= "ZZZZZ";
- MSPTRST(jtag_chains - 1 downto 0) <= "ZZZZZ";
+ p_jtagselect: process(TDI,MSPTDI(jtag_chains - 1 downto 0),TCK,TMS,TRST)
+ begin
+ ENABLE_SB <= '0';
+ MSPTDO(jtag_chains - 1 downto 0) <= "ZZZZZ";
+ MSPTCK(jtag_chains - 1 downto 0) <= "ZZZZZ";
+ MSPTMS(jtag_chains - 1 downto 0) <= "ZZZZZ";
+ MSPTRST(jtag_chains - 1 downto 0) <= "ZZZZZ";
- if CTRL(1) = '1' then
- ENABLE_SB <= '1';
- MSPTDO <= MSPTDO_BSCAN;
- TDO <= TDO_BSCAN;
- MSPTCK <= MSPTCK_BSCAN;
- MSPTMS <= MSPTMS_BSCAN;
- MSPTRST <= MSPTRST_BSCAN;
- else
- if LPSEL(0) = '0' then
- MSPTDO(0) <= TDI;
- TDA <= MSPTDI(0);
- MSPTCK(0) <= TCK;
- MSPTMS(0) <= TMS;
- MSPTRST(0) <= TRST;
- else
- TDA <= TDI;
- end if;
+ if CTRL(1) = '1' then
+ ENABLE_SB <= '1';
+ MSPTDO <= MSPTDO_BSCAN;
+ TDO <= TDO_BSCAN;
+ MSPTCK <= MSPTCK_BSCAN;
+ MSPTMS <= MSPTMS_BSCAN;
+ MSPTRST <= MSPTRST_BSCAN;
+ else
+ if LPSEL(0) = '0' then
+ MSPTDO(0) <= TDI;
+ TDA <= MSPTDI(0);
+ MSPTCK(0) <= TCK;
+ MSPTMS(0) <= TMS;
+ MSPTRST(0) <= TRST;
+ else
+ TDA <= TDI;
+ end if;
- if LPSEL(1) = '0' then
- MSPTDO(1) <= TDA;
- TDB <= MSPTDI(1);
- MSPTCK(1) <= TCK;
- MSPTMS(1) <= TMS;
- MSPTRST(1) <= TRST;
- else
- TDB <= TDA;
- end if;
+ if LPSEL(1) = '0' then
+ MSPTDO(1) <= TDA;
+ TDB <= MSPTDI(1);
+ MSPTCK(1) <= TCK;
+ MSPTMS(1) <= TMS;
+ MSPTRST(1) <= TRST;
+ else
+ TDB <= TDA;
+ end if;
- if LPSEL(2) = '0' then
- MSPTDO(2) <= TDB;
- TDC <= MSPTDI(2);
- MSPTCK(2) <= TCK;
- MSPTMS(2) <= TMS;
- MSPTRST(2) <= TRST;
- else
- TDC <= TDB;
- end if;
+ if LPSEL(2) = '0' then
+ MSPTDO(2) <= TDB;
+ TDC <= MSPTDI(2);
+ MSPTCK(2) <= TCK;
+ MSPTMS(2) <= TMS;
+ MSPTRST(2) <= TRST;
+ else
+ TDC <= TDB;
+ end if;
- if LPSEL(3) = '0' then
- MSPTDO(3) <= TDC;
- TDD <= MSPTDI(3);
- MSPTCK(3) <= TCK;
- MSPTMS(3) <= TMS;
- MSPTRST(3) <= TRST;
- else
- TDD <= TDC;
- end if;
+ if LPSEL(3) = '0' then
+ MSPTDO(3) <= TDC;
+ TDD <= MSPTDI(3);
+ MSPTCK(3) <= TCK;
+ MSPTMS(3) <= TMS;
+ MSPTRST(3) <= TRST;
+ else
+ TDD <= TDC;
+ end if;
- if LPSEL(4) = '0' then
- MSPTDO(4) <= TDD;
- TDO <= MSPTDI(4);
- MSPTCK(4) <= TCK;
- MSPTMS(4) <= TMS;
- MSPTRST(4) <= TRST;
- else
- TDO <= TDD;
- end if;
- end if;
+ if LPSEL(4) = '0' then
+ MSPTDO(4) <= TDD;
+ TDO <= MSPTDI(4);
+ MSPTCK(4) <= TCK;
+ MSPTMS(4) <= TMS;
+ MSPTRST(4) <= TRST;
+ else
+ TDO <= TDD;
+ end if;
+ end if;
end process;
end str;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
index 1968d26ac9..7aa11d383d 100644
--- a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
@@ -6,23 +6,23 @@
---------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity jtag_top is
- port (
- CTRL : in std_logic_vector(1 downto 0);
- ENABLE_MSP : in std_logic;
- IDN : in std_logic_vector(3 downto 0);
- LPSEL : in std_logic_vector(4 downto 0);
- MSPTCK : out std_logic_vector(4 downto 0);
- MSPTDI : in std_logic_vector(4 downto 0);
- MSPTDO : out std_logic_vector(4 downto 0);
- MSPTMS : out std_logic_vector(4 downto 0);
- MSPTRST : out std_logic_vector(4 downto 0);
- TCK : in std_logic;
- TDI : in std_logic;
- TDO : out std_logic;
- TMS : in std_logic;
- TRST : in std_logic
- );
+ port (
+ CTRL : in std_logic_vector(1 downto 0);
+ ENABLE_MSP : in std_logic;
+ IDN : in std_logic_vector(3 downto 0);
+ LPSEL : in std_logic_vector(4 downto 0);
+ MSPTCK : out std_logic_vector(4 downto 0);
+ MSPTDI : in std_logic_vector(4 downto 0);
+ MSPTDO : out std_logic_vector(4 downto 0);
+ MSPTMS : out std_logic_vector(4 downto 0);
+ MSPTRST : out std_logic_vector(4 downto 0);
+ TCK : in std_logic;
+ TDI : in std_logic;
+ TDO : out std_logic;
+ TMS : in std_logic;
+ TRST : in std_logic
+ );
end jtag_top;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index 74bc5570a9..de253c110b 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -25,16 +25,16 @@
-- . ctrl_unb2c_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
library IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb2c_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb2c_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb2c_board is
generic (
@@ -318,15 +318,15 @@ begin
i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
u_common_areset_ext : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_ext_clk200,
- out_rst => ext_rst200
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_ext_clk200,
+ out_rst => ext_rst200
+ );
-----------------------------------------------------------------------------
-- xo_ethclk = ETH_CLK
@@ -335,15 +335,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
-- MB_I_REF_CLK --> mb_I_ref_rst
@@ -351,26 +351,26 @@ begin
-----------------------------------------------------------------------------
u_common_areset_mb_I : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_I_REF_CLK,
- out_rst => mb_I_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_I_REF_CLK,
+ out_rst => mb_I_ref_rst
+ );
u_common_areset_mb_II : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_II_REF_CLK,
- out_rst => mb_II_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_II_REF_CLK,
+ out_rst => mb_II_ref_rst
+ );
-----------------------------------------------------------------------------
-- dp_clk + dp_rst generation
@@ -384,29 +384,29 @@ begin
gen_pll: if g_sim = false and g_dp_clk_use_pll = true generate
u_unb2c_board_clk200_pll : entity work.unb2c_board_clk200_pll
+ generic map (
+ g_technology => g_technology,
+ g_use_fpll => true,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ port map (
+ arst => i_mm_rst,
+ clk200 => i_ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => common_areset_in_rst
+ );
+ end generate;
+
+ u_common_areset_dp_rst : entity common_lib.common_areset
generic map (
- g_technology => g_technology,
- g_use_fpll => true,
- g_clk200_phase_shift => g_dp_clk_phase
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
)
port map (
- arst => i_mm_rst,
- clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => common_areset_in_rst
+ in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
);
- end generate;
-
- u_common_areset_dp_rst : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
-----------------------------------------------------------------------------
-- mm_clk
@@ -421,48 +421,48 @@ begin
clk50; -- default
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
- sim_mm_clk <= not sim_mm_clk after g_sim_mm_clk_period / 2;
- mm_locked <= '0', '1' after 70 ns;
+ epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
+ clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
+ sim_mm_clk <= not sim_mm_clk after g_sim_mm_clk_period / 2;
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2c_board_clk125_pll : entity work.unb2c_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => epcs_clk,
+ c1_clk50 => clk50,
+ c2_clk100 => clk100,
+ c3_clk125 => clk125,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2c_board_node_ctrl : entity work.unb2c_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c0_clk20 => epcs_clk,
- c1_clk50 => clk50,
- c2_clk100 => clk100,
- c3_clk125 => clk125,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2c_board_node_ctrl : entity work.unb2c_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-----------------------------------------------------------------------------
-- System info
@@ -470,33 +470,33 @@ begin
cs_sim <= is_true(g_sim);
u_mms_unb2c_board_system_info : entity work.mms_unb2c_board_system_info
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
-- Red LED control
@@ -531,12 +531,12 @@ begin
led_toggle_green <= sel_a_b(g_factory_image = false, led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
-- WDI override
@@ -547,15 +547,15 @@ begin
WDI <= mm_wdi or temp_alarm or wdi_override;
u_unb2c_board_wdi_reg : entity work.unb2c_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
-- Remote upgrade
@@ -564,98 +564,98 @@ begin
-- So there is full control over the memory mapped registers to set start address of the flash
-- and reconfigure from that address.
u_mms_remu: entity remu_lib.mms_remu
- generic map (
- g_technology => g_technology
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
-------------------------------------------------------------------------------
---- EPCS
-------------------------------------------------------------------------------
u_mms_epcs: entity epcs_lib.mms_epcs
- generic map (
- g_technology => g_technology,
- g_protect_addr_range => g_protect_addr_range,
- g_protected_addr_lo => g_protected_addr_lo,
- g_protected_addr_hi => g_protected_addr_hi
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology,
+ g_protect_addr_range => g_protect_addr_range,
+ g_protected_addr_lo => g_protected_addr_lo,
+ g_protected_addr_hi => g_protected_addr_hi
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
------------------------------------------------------------------------------
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_technology => g_technology,
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => dp_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => dp_pps
+ );
u_mms_unb2c_fpga_sens : entity work.mms_unb2c_fpga_sens
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- mm_start => '1',
-
- -- Memory-mapped clock domain
- reg_temp_mosi => reg_fpga_temp_sens_mosi,
- reg_temp_miso => reg_fpga_temp_sens_miso,
- reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
- reg_voltage_miso => reg_fpga_voltage_sens_miso,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ mm_start => '1',
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
-- Ethernet 1GbE
@@ -664,18 +664,18 @@ begin
gen_tse_clk_buf: if g_tse_clk_buf = true generate
-- Separate clkbuf for the 1GbE tse_clk:
u_tse_clk_buf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => i_xo_ethclk,
- outclk => i_tse_clk
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => i_xo_ethclk,
+ outclk => i_tse_clk
+ );
end generate;
gen_tse_no_clk_buf: if g_tse_clk_buf = false generate
- i_tse_clk <= i_xo_ethclk;
+ i_tse_clk <= i_xo_ethclk;
end generate;
wire_udp_offload: for i in 0 to g_udp_offload_nof_streams - 1 generate
@@ -700,60 +700,60 @@ begin
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
u_eth : entity eth_lib.eth
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_frm_discard_en => true,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => i_mm_clk, -- use mm_clk direct
+ eth_clk => i_tse_clk, -- 125 MHz clock
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT,
+ eth_rxp => ETH_SGIN,
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
+ end generate;
+
+ u_ram_scrap : entity common_lib.common_ram_r_w
generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_frm_discard_en => true,
- g_sim => g_sim,
- g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ g_ram => c_ram_scrap
)
port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT,
- eth_rxp => ETH_SGIN,
-
- -- LED interface
- tse_led => eth1g_led
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ wr_en => ram_scrap_mosi.wr,
+ wr_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
+ wr_dat => ram_scrap_mosi.wrdata(c_ram_scrap.dat_w - 1 downto 0),
+ rd_en => ram_scrap_mosi.rd,
+ rd_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
+ rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w - 1 downto 0),
+ rd_val => ram_scrap_miso.rdval
);
- end generate;
-
- u_ram_scrap : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram_scrap
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- wr_en => ram_scrap_mosi.wr,
- wr_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
- wr_dat => ram_scrap_mosi.wrdata(c_ram_scrap.dat_w - 1 downto 0),
- rd_en => ram_scrap_mosi.rd,
- rd_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
- rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w - 1 downto 0),
- rd_val => ram_scrap_miso.rdval
- );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
index 699c38a4d2..4cfabd6676 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2c_board_system_info is
generic (
@@ -58,7 +58,7 @@ entity mms_unb2c_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb2c_board_system_info;
architecture str of mms_unb2c_board_system_info is
@@ -68,68 +68,69 @@ architecture str of mms_unb2c_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/"; -- TODO: change path
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 13; -- 2^13 = 8192 addresses * 32 bits = 32 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb2c_board_system_info: entity work.unb2c_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb2c_board_system_info_reg: entity work.unb2c_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_technology => g_technology,
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
index 6b19f5aad1..806297da80 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
@@ -23,11 +23,11 @@
-- Description: See unb2c_fpga_sens.vhd
library IEEE, technology_lib, common_lib, fpga_sense_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2c_fpga_sens is
generic (
@@ -55,22 +55,22 @@ end mms_unb2c_fpga_sens;
architecture str of mms_unb2c_fpga_sens is
begin
u_fpga_sense: entity fpga_sense_lib.fpga_sense
- generic map (
- g_technology => g_technology,
- g_sim => g_sim,
- g_temp_high => g_temp_high
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- start_sense => mm_start,
- temp_alarm => temp_alarm,
+ start_sense => mm_start,
+ temp_alarm => temp_alarm,
- reg_temp_mosi => reg_temp_mosi,
- reg_temp_miso => reg_temp_miso,
+ reg_temp_mosi => reg_temp_mosi,
+ reg_temp_miso => reg_temp_miso,
- reg_voltage_store_mosi => reg_voltage_mosi,
- reg_voltage_store_miso => reg_voltage_miso
- );
+ reg_voltage_store_mosi => reg_voltage_mosi,
+ reg_voltage_store_miso => reg_voltage_miso
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
index f50eaf95d2..e07049c7de 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2c_board_pkg.all;
entity unb2c_board_back_io is
generic (
@@ -53,4 +53,4 @@ begin
serial_rx_arr(i * c_unb2c_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
-end;
+ end;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
index 1c0b8a5d37..ac5d1cc199 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
@@ -21,17 +21,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Purpose: PLL for UniBoard node CLK input @ 125 MHz
--- Description:
--- c0 = 20 MHz
--- c1 = 50 MHz
--- c2 = 100 MHz
--- c3 = 125 MHz
---
+ -- Purpose: PLL for UniBoard node CLK input @ 125 MHz
+ -- Description:
+ -- c0 = 20 MHz
+ -- c1 = 50 MHz
+ -- c2 = 100 MHz
+ -- c3 = 125 MHz
+ --
entity unb2c_board_clk125_pll is
generic (
@@ -60,46 +60,46 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk125,
- outclk => clk125buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk125,
+ outclk => clk125buf
+ );
end generate;
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
gen_fractional_pll : if g_use_fpll = true generate
u_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
end arria10;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
index ac16a08d15..d73b54f195 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
@@ -21,74 +21,74 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Purpose: PLL for UniBoard node CLK input @ 200 MHz
--- Description:
--- . The PLL runs in normal mode using c0 to compensate for the internal clock
--- network delay, so that c0 = st_clk200 is aligned to the input clk200.
--- . The assumption is that default the streaming DSP will run on the 200 MHz
--- clock from the CLK input via c1 = st_clk200p.
--- . The PLL normal mode operation compensates for internal clock network
--- delays of c0. This compensations aligns c0 to inclk0. With
--- tb_unb2c_board_clk200_pll.vhd it appears that the phase setting for c0 does
--- not influence the compensation. Therefore it is llso possible to use
--- g_clk200_phase_shift /= 0 and touse c0 as processing clock instead of c1.
--- . The phase offset of c0 and c1 in the clk200_pll MegaWizard component
--- can be set in steps of 11.25 degrees (and even finer):
--- g_clk200_phase_shift (for c0)
--- phase [degrees] g_clk200p_phase_shift (for c1)
--- 0 "0"
--- 11.25 "156"
--- 22.5 "313"
--- 33.75 "469"
--- 45 "625"
--- 56.25 "781"
--- 67.5 "938"
--- 78.75 "1094"
--- 90 "1250"
--- 101.25 "1406" = 1250+ 156
--- 112.5 "1563" = 1250+ 313
--- 123.75 "1719" = 1250+ 469
--- 135 "1875" = 1250+ 625
--- 146.25 "2031" = 1250+ 781
--- 157.5 "2188" = 1250+ 938
--- 168.75 "2344" = 1250+1094
--- 180 "2500" = 1250+1250
--- 191.25 "2656" = 2500+ 156
--- 202.5 "2813" = 2500+ 313
--- 213.75 "2969" = 2500+ 469
--- 225 "3125" = 2500+ 625
--- 236.25 "3281" = 2500+ 781
--- 247.5 "3438" = 2500+ 938
--- 258.75 "3594" = 2500+1094
--- 270 "3750" = 2500+1250
--- 281.25 "3906" = 3750+ 156
--- 292.5 "4063" = 3750+ 313
--- 303.75 "4219" = 3750+ 469
--- 315 "4375" = 3750+ 625
--- 326.25 "4531" = 3750+ 781
--- 337.5 "4688" = 3750+ 938
--- 348.75 "4844" = 3750+1094
--- 360 "5000" = 3750+1250
--- . With a phase offset of 22.5 degrees the c1 = clk200p is offset by a 1/16
--- period of 200 MHz, so 1/8 period of the 400 MHz DCLK from ADU and 1/4
--- period of the 800 MHz sample SCLK of ADU. This phase offset can be used
--- to achieve stable timing between the DCLK and the clk200p domain.
--- . Some DSP may also be possible at 400 MHz via st_clk400. Note that this
--- 400 MHz can also be used at places where only a little more than 200 MHz
--- would be needed, e.g. to create packets at full data rate.
--- Therefore it is not necessary to create yet another st clock frequency.
--- This to also avoid the EMI or RFI that a non integer factor of 200 MHz
--- like e.g. 250 MHz would cause.
--- . At 400 MHz ADC samples can be clocked in at 800 MSps using DDIO. At 800
--- MSps the sample period is 1250 ns. Input timing can be tuned via fixed
--- pad input delays and/or by using another phase of the PLL output clock.
--- Remarks:
--- . If necessary more 400 M clock phase could be made available, via g_sel.
---
+ -- Purpose: PLL for UniBoard node CLK input @ 200 MHz
+ -- Description:
+ -- . The PLL runs in normal mode using c0 to compensate for the internal clock
+ -- network delay, so that c0 = st_clk200 is aligned to the input clk200.
+ -- . The assumption is that default the streaming DSP will run on the 200 MHz
+ -- clock from the CLK input via c1 = st_clk200p.
+ -- . The PLL normal mode operation compensates for internal clock network
+ -- delays of c0. This compensations aligns c0 to inclk0. With
+ -- tb_unb2c_board_clk200_pll.vhd it appears that the phase setting for c0 does
+ -- not influence the compensation. Therefore it is llso possible to use
+ -- g_clk200_phase_shift /= 0 and touse c0 as processing clock instead of c1.
+ -- . The phase offset of c0 and c1 in the clk200_pll MegaWizard component
+ -- can be set in steps of 11.25 degrees (and even finer):
+ -- g_clk200_phase_shift (for c0)
+ -- phase [degrees] g_clk200p_phase_shift (for c1)
+ -- 0 "0"
+ -- 11.25 "156"
+ -- 22.5 "313"
+ -- 33.75 "469"
+ -- 45 "625"
+ -- 56.25 "781"
+ -- 67.5 "938"
+ -- 78.75 "1094"
+ -- 90 "1250"
+ -- 101.25 "1406" = 1250+ 156
+ -- 112.5 "1563" = 1250+ 313
+ -- 123.75 "1719" = 1250+ 469
+ -- 135 "1875" = 1250+ 625
+ -- 146.25 "2031" = 1250+ 781
+ -- 157.5 "2188" = 1250+ 938
+ -- 168.75 "2344" = 1250+1094
+ -- 180 "2500" = 1250+1250
+ -- 191.25 "2656" = 2500+ 156
+ -- 202.5 "2813" = 2500+ 313
+ -- 213.75 "2969" = 2500+ 469
+ -- 225 "3125" = 2500+ 625
+ -- 236.25 "3281" = 2500+ 781
+ -- 247.5 "3438" = 2500+ 938
+ -- 258.75 "3594" = 2500+1094
+ -- 270 "3750" = 2500+1250
+ -- 281.25 "3906" = 3750+ 156
+ -- 292.5 "4063" = 3750+ 313
+ -- 303.75 "4219" = 3750+ 469
+ -- 315 "4375" = 3750+ 625
+ -- 326.25 "4531" = 3750+ 781
+ -- 337.5 "4688" = 3750+ 938
+ -- 348.75 "4844" = 3750+1094
+ -- 360 "5000" = 3750+1250
+ -- . With a phase offset of 22.5 degrees the c1 = clk200p is offset by a 1/16
+ -- period of 200 MHz, so 1/8 period of the 400 MHz DCLK from ADU and 1/4
+ -- period of the 800 MHz sample SCLK of ADU. This phase offset can be used
+ -- to achieve stable timing between the DCLK and the clk200p domain.
+ -- . Some DSP may also be possible at 400 MHz via st_clk400. Note that this
+ -- 400 MHz can also be used at places where only a little more than 200 MHz
+ -- would be needed, e.g. to create packets at full data rate.
+ -- Therefore it is not necessary to create yet another st clock frequency.
+ -- This to also avoid the EMI or RFI that a non integer factor of 200 MHz
+ -- like e.g. 250 MHz would cause.
+ -- . At 400 MHz ADC samples can be clocked in at 800 MSps using DDIO. At 800
+ -- MSps the sample period is 1250 ns. Input timing can be tuned via fixed
+ -- pad input delays and/or by using another phase of the PLL output clock.
+ -- Remarks:
+ -- . If necessary more 400 M clock phase could be made available, via g_sel.
+ --
entity unb2c_board_clk200_pll is
generic (
@@ -136,82 +136,82 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk200,
- outclk => clk200buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk200,
+ outclk => clk200buf
+ );
end generate;
gen_st_pll : if g_use_fpll = false generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200buf,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_st_fractional_pll : if g_use_fpll = true generate
u_st_fractional_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk200
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf, -- 200 MHz
+ c0 => i_st_clk200, -- 200 MHz
+ c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
+ c2 => i_st_clk400, -- 400 MHz
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end arria10;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
index 71a8f3000c..4631c789c2 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
@@ -21,17 +21,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Purpose: PLL for UniBoard node CLK input @ 25 MHz
--- Description:
--- c0 = 20 MHz
--- c1 = 50 MHz
--- c2 = 100 MHz
--- c3 = 125 MHz
---
+ -- Purpose: PLL for UniBoard node CLK input @ 25 MHz
+ -- Description:
+ -- c0 = 20 MHz
+ -- c1 = 50 MHz
+ -- c2 = 100 MHz
+ -- c3 = 125 MHz
+ --
entity unb2c_board_clk25_pll is
generic (
@@ -52,16 +52,16 @@ end unb2c_board_clk25_pll;
architecture arria10 of unb2c_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end arria10;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
index 25dd597531..8fd26a5e88 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose:
--- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
--- reset_n).
--- 2) sys_rst released when the sys_clk PLL from the SOPC system has locked,
--- can be used as a system reset for the sys_clk domain.
+ -- Purpose:
+ -- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
+ -- reset_n).
+ -- 2) sys_rst released when the sys_clk PLL from the SOPC system has locked,
+ -- can be used as a system reset for the sys_clk domain.
entity unb2c_board_clk_rst is
port (
@@ -55,27 +55,27 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
index ca19220a75..a85c7a902c 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2c_board_pkg.all;
entity unb2c_board_front_io is
generic (
@@ -60,8 +60,8 @@ begin
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2c_board_tr_qsfp.bus_w - 1 generate
- si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j);
- serial_rx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
-end;
+ end;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
index cd18bbc40c..0eabf44fb1 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose: Provide the basic node clock control (resets, pulses, WDI)
--- Description:
--- . Create mm_rst for mm_clk:
--- . Extend WDI to avoid watchdog reset during software reload
--- . Pulse every 1 us, 1 ms and 1 s
+ -- Purpose: Provide the basic node clock control (resets, pulses, WDI)
+ -- Description:
+ -- . Create mm_rst for mm_clk:
+ -- . Extend WDI to avoid watchdog reset during software reload
+ -- . Pulse every 1 us, 1 ms and 1 s
entity unb2c_board_node_ctrl is
generic (
@@ -67,43 +67,43 @@ begin
mm_locked_n <= not mm_locked;
u_common_areset_mm : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => mm_clk,
- out_rst => i_mm_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => mm_clk,
+ out_rst => i_mm_rst
+ );
-- Create 1 pulse per us, per ms and per s
mm_pulse_ms <= i_mm_pulse_ms;
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_us => mm_pulse_us,
- pulse_ms => i_mm_pulse_ms,
- pulse_s => mm_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_us => mm_pulse_us,
+ pulse_ms => i_mm_pulse_ms,
+ pulse_s => mm_pulse_s
+ );
-- Toggle the WDI every 1 ms
u_unb2c_board_wdi_extend : entity work.unb2c_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_ms => i_mm_pulse_ms,
- wdi_in => mm_wdi_in,
- wdi_out => mm_wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_ms => i_mm_pulse_ms,
+ wdi_in => mm_wdi_in,
+ wdi_out => mm_wdi_out
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
index 09f3d31eb0..7f398a16be 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb2c_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
@@ -74,10 +74,10 @@ package unb2c_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
index 58d1247754..f1b23b7b1f 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb2c_board_pkg is
-- UniBoard
@@ -124,21 +124,23 @@ package unb2c_board_pkg is
type t_c_unb2c_board_system_info is record
version : natural; -- UniBoard board HW version (2 bit value)
id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
+ -- Derived ID info:
bck_id : natural; -- = id[7:2], ID part from back plane
chip_id : natural; -- = id[1:0], ID part from UniBoard
node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
is_node2 : natural; -- 1 for Node 2, else 0.
end record;
- function func_unb2c_board_system_info(VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0)) return t_c_unb2c_board_system_info;
+ function func_unb2c_board_system_info(
+ VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0)) return t_c_unb2c_board_system_info;
-end unb2c_board_pkg;
+ end unb2c_board_pkg;
package body unb2c_board_pkg is
- function func_unb2c_board_system_info(VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0)) return t_c_unb2c_board_system_info is
+ function func_unb2c_board_system_info(
+ VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0)) return t_c_unb2c_board_system_info is
variable v_system_info : t_c_unb2c_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
@@ -150,4 +152,4 @@ package body unb2c_board_pkg is
return v_system_info;
end;
-end unb2c_board_pkg;
+ end unb2c_board_pkg;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
index 47ba71e8f1..40dd4054f2 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
@@ -21,48 +21,48 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
--- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
--- Description:
--- The testio LED on UniBoard2 is not visible via the front panel. The
--- front panel does have a dual colour LED for each QSFP lane. Therefore
--- these QSFP LEDs are used to signal some application information and lane
--- status/activity information.
---
--- LED lights:
---
--- 1) Default behaviour for all QSFP leds:
--- . off = no FPGA image is running
---
--- 2) For factory image:
--- . green off
--- . red toggling every 1 s = factory image is running (g_factory_image=TRUE)
---
--- 3) For a user image without Gbps lane functionality:
--- . red off
--- . green toggling every 1 s = user image is running (g_factory_image=FALSE and green_on_arr(I)='0' default)
---
--- 4) For a user image with Gbps lane functionality:
--- . red off
--- . green toggling every 1 s when the lane status is not OK (green_on_arr(I)=xon='0')
--- . green on continously when the lane status is OK (green_on_arr(I)=xon='1')
--- . green led goes off briefly off when there is an Tx or Rx packet (green_evt_arr(I).sop='1')
---
--- The combined colour amber (= red + green) is not used. The factory image
--- only uses the red led and the user image only uses the green led.
---
--- Each QSFP carries c_quad = 4 lanes, therefore the green led LED can only
--- signal a combined status of the lanes. The combined status eg. be:
---
--- 'and-status' = combined status is on when all lanes are on
--- 'or-status' = combined status is on when at least 1 lane is on
---
--- Choose using 'or-status', because then the LED can give lane status
--- information when less than all 4 lane are connected.
---
+ -- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
+ -- Description:
+ -- The testio LED on UniBoard2 is not visible via the front panel. The
+ -- front panel does have a dual colour LED for each QSFP lane. Therefore
+ -- these QSFP LEDs are used to signal some application information and lane
+ -- status/activity information.
+ --
+ -- LED lights:
+ --
+ -- 1) Default behaviour for all QSFP leds:
+ -- . off = no FPGA image is running
+ --
+ -- 2) For factory image:
+ -- . green off
+ -- . red toggling every 1 s = factory image is running (g_factory_image=TRUE)
+ --
+ -- 3) For a user image without Gbps lane functionality:
+ -- . red off
+ -- . green toggling every 1 s = user image is running (g_factory_image=FALSE and green_on_arr(I)='0' default)
+ --
+ -- 4) For a user image with Gbps lane functionality:
+ -- . red off
+ -- . green toggling every 1 s when the lane status is not OK (green_on_arr(I)=xon='0')
+ -- . green on continously when the lane status is OK (green_on_arr(I)=xon='1')
+ -- . green led goes off briefly off when there is an Tx or Rx packet (green_evt_arr(I).sop='1')
+ --
+ -- The combined colour amber (= red + green) is not used. The factory image
+ -- only uses the red led and the user image only uses the green led.
+ --
+ -- Each QSFP carries c_quad = 4 lanes, therefore the green led LED can only
+ -- signal a combined status of the lanes. The combined status eg. be:
+ --
+ -- 'and-status' = combined status is on when all lanes are on
+ -- 'or-status' = combined status is on when at least 1 lane is on
+ --
+ -- Choose using 'or-status', because then the LED can give lane status
+ -- information when less than all 4 lane are connected.
+ --
entity unb2c_board_qsfp_leds is
generic (
@@ -107,43 +107,43 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => i_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => i_pulse_s
+ );
u_common_toggle_s : entity common_lib.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => i_pulse_s,
- out_dat => toggle_s
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => i_pulse_s,
+ out_dat => toggle_s
+ );
gen_factory_image : if g_factory_image = true generate
green_led_arr <= (others => '0');
gen_red_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
u_red_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- -- led control
- ctrl_input => toggle_s,
- -- led output
- led => red_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- led control
+ ctrl_input => toggle_s,
+ -- led output
+ led => red_led_arr(I)
+ );
end generate;
end generate;
@@ -160,20 +160,20 @@ begin
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
u_green_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => i_pulse_ms,
- -- led control
- ctrl_on => qsfp_on_arr(I),
- ctrl_evt => qsfp_evt_arr(I),
- ctrl_input => toggle_s,
- -- led output
- led => green_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => i_pulse_ms,
+ -- led control
+ ctrl_on => qsfp_on_arr(I),
+ ctrl_evt => qsfp_evt_arr(I),
+ ctrl_input => toggle_s,
+ -- led output
+ led => green_led_arr(I)
+ );
end generate;
end generate;
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
index 1ae3b3d7e6..6074895849 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2c_board_pkg.all;
entity unb2c_board_ring_io is
generic (
@@ -52,4 +52,4 @@ begin
serial_rx_arr(i * c_unb2c_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
-end;
+ end;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
index ca28bdf487..2d8a199e2b 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
@@ -21,14 +21,14 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
--- Keep the UniBoard system info knowledge in this HDL entity and in the
--- corresponding software functions in unb_common.c,h. This avoids having to
--- define named constants for indexing the fields in the info word.
+ -- Keep the UniBoard system info knowledge in this HDL entity and in the
+ -- corresponding software functions in unb_common.c,h. This avoids having to
+ -- define named constants for indexing the fields in the info word.
entity unb2c_board_system_info is
generic (
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
index 355bf6c3af..cfce22041d 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2c_board_pkg.all;
entity unb2c_board_system_info_reg is
generic (
@@ -68,7 +68,7 @@ entity unb2c_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb2c_board_system_info_reg;
architecture rtl of unb2c_board_system_info_reg is
@@ -86,11 +86,12 @@ architecture rtl of unb2c_board_system_info_reg is
constant c_revision_id_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
constant c_design_note_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs; -- = 2+13+2+3+12 = 32
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0');
constant c_use_phy_w : natural := 8;
constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
index 4c53cdcc41..3cd66c6ec1 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose:
--- Extend the input WDI that is controlled in SW (as it should be) to avoid
--- that the watchdog reset will occur when new SW is loaded, while keeping
--- the HDL image. This component extends the last input WDI by toggling the
--- output WDI for about 2**(g_extend_w-1) ms more.
+ -- Purpose:
+ -- Extend the input WDI that is controlled in SW (as it should be) to avoid
+ -- that the watchdog reset will occur when new SW is loaded, while keeping
+ -- the HDL image. This component extends the last input WDI by toggling the
+ -- output WDI for about 2**(g_extend_w-1) ms more.
entity unb2c_board_wdi_extend is
generic (
@@ -68,26 +68,26 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
index 6c9a33e383..7caeebca66 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2c_board_wdi_reg is
port (
@@ -40,16 +40,17 @@ entity unb2c_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb2c_board_wdi_reg;
architecture rtl of unb2c_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
@@ -60,7 +61,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
index 320d5febe6..d9442c1441 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2c_board_clk125_pll is
end tb_unb2c_board_clk125_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2c_board_clk125_pll
- port map (
- arst => ext_rst,
- clk125 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk125 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
index 4a035d2eb5..f0837780b5 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2c_board_clk200_pll is
end tb_unb2c_board_clk200_pll;
@@ -66,44 +66,44 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2c_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb2c_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb2c_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
index 9923168e21..f2563fc31c 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2c_board_clk25_pll is
end tb_unb2c_board_clk25_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2c_board_clk25_pll
- port map (
- arst => ext_rst,
- clk25 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk25 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
index a7a9084716..152a4d3e6e 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2c_board_node_ctrl is
end tb_unb2c_board_node_ctrl;
@@ -71,23 +71,23 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb2c_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- -- MM clock domain reset
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => wdi_in,
- mm_wdi_out => wdi_out,
- -- Pulses
- mm_pulse_us => pulse_us,
- mm_pulse_ms => pulse_ms,
- mm_pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => wdi_in,
+ mm_wdi_out => wdi_out,
+ -- Pulses
+ mm_pulse_us => pulse_us,
+ mm_pulse_ms => pulse_ms,
+ mm_pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
index 9ee6059b7f..5c3d21f27f 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
@@ -37,10 +37,10 @@
-- > run -a
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_unb2c_board_qsfp_leds is
end tb_unb2c_board_qsfp_leds;
@@ -139,48 +139,48 @@ begin
end process;
u_unb2c_factory_qsfp_leds : entity work.unb2c_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => factory_green_led_arr,
- red_led_arr => factory_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => true, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => factory_green_led_arr,
+ red_led_arr => factory_red_led_arr
+ );
u_unb2c_user_qsfp_leds : entity work.unb2c_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => user_green_led_arr,
- red_led_arr => user_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => false, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => user_green_led_arr,
+ red_led_arr => user_red_led_arr
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd b/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
index 92199c7404..0fd65d94c6 100644
--- a/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_board_10gbe is
generic (
@@ -78,17 +78,17 @@ architecture str of unb2c_board_10gbe is
signal tr_ref_rst_156 : std_logic;
begin
u_unb2c_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => g_technology
- )
- port map (
- refclk_644 => tr_ref_clk,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ refclk_644 => tr_ref_clk,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
diff --git a/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
index e95d9eaf75..ba3f309723 100644
--- a/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
@@ -35,10 +35,10 @@
-- registers.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.axi4_lite_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.axi4_lite_pkg.all;
entity axi4_lite_mm_bridge is
generic (
@@ -106,12 +106,12 @@ begin
if mm_out_cipo.waitrequest = '0' and axi4_in_copi.wvalid = '1' then
d_bvalid <= '1';
- -- BVALID is acknowledged by BREADY, so deassert BVALID.
+ -- BVALID is acknowledged by BREADY, so deassert BVALID.
elsif axi4_in_copi.bready = '1' then
d_bvalid <= '0';
end if;
if i_rst = '1' then
- d_bvalid <= '0';
+ d_bvalid <= '0';
end if;
end process;
end str;
diff --git a/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
index 6f94af5302..6101128da2 100644
--- a/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
@@ -28,12 +28,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use std.textio.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use std.textio.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
package axi4_lite_pkg is
------------------------------------------------------------------------------
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
index 35b1086347..934a72044e 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
@@ -48,10 +48,10 @@
-- . AXI4 does not have a DP Xon or sync equivalent.
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.axi4_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.axi4_stream_pkg.all;
entity axi4_stream_dp_bridge is
generic (
@@ -113,20 +113,20 @@ begin
-- Adapt Ready Latency
u_dp_latency_adapter_dp_to_axi : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => g_dp_rl,
- g_out_latency => g_axi4_rl
- )
- port map (
- clk => in_clk,
- rst => i_rst,
-
- snk_in => dp_in_sosi,
- snk_out => dp_in_siso,
-
- src_out => axi4_from_dp_sosi,
- src_in => axi4_from_dp_siso
- );
+ generic map (
+ g_in_latency => g_dp_rl,
+ g_out_latency => g_axi4_rl
+ )
+ port map (
+ clk => in_clk,
+ rst => i_rst,
+
+ snk_in => dp_in_sosi,
+ snk_out => dp_in_siso,
+
+ src_out => axi4_from_dp_sosi,
+ src_in => axi4_from_dp_siso
+ );
----------------------------
-- Translate AXI4 to DP
@@ -177,18 +177,18 @@ begin
-- Adapt Ready Latency
u_dp_latency_adapter_axi_to_dp : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => g_axi4_rl,
- g_out_latency => g_dp_rl
- )
- port map (
- clk => in_clk,
- rst => i_rst,
-
- snk_in => dp_from_axi4_sosi,
- snk_out => dp_from_axi4_siso,
-
- src_out => dp_out_sosi,
- src_in => dp_out_siso
- );
+ generic map (
+ g_in_latency => g_axi4_rl,
+ g_out_latency => g_dp_rl
+ )
+ port map (
+ clk => in_clk,
+ rst => i_rst,
+
+ snk_in => dp_from_axi4_sosi,
+ snk_out => dp_from_axi4_siso,
+
+ src_out => dp_out_sosi,
+ src_in => dp_out_siso
+ );
end str;
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
index 713f1ed150..4780bb47f2 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
@@ -47,10 +47,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package axi4_stream_pkg is
constant c_axi4_stream_data_w : natural := 512; -- Data width, upto 512bit for Xilinx IP
@@ -101,30 +101,34 @@ package axi4_stream_pkg is
type t_axi4_sosi_mat is array (integer range <>, integer range <>) of t_axi4_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_axi4_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_axi4_sosi;
- signal siso : in t_axi4_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_axi4_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_axi4_sosi;
+ signal siso : in t_axi4_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_axi4_siso_alert(signal clk : in std_logic;
- signal sosi : in t_axi4_sosi;
- signal siso : in t_axi4_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_axi4_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_axi4_sosi;
+ signal siso : in t_axi4_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_axi4_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_axi4_sosi_arr;
- signal siso_arr : in t_axi4_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_axi4_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_axi4_sosi_arr;
+ signal siso_arr : in t_axi4_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_axi4_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_axi4_sosi_arr;
- signal siso_arr : in t_axi4_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_axi4_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_axi4_sosi_arr;
+ signal siso_arr : in t_axi4_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Keep part of head data and combine part of tail data, use the other sosi from head_sosi
function func_axi4_data_shift_first(head_sosi, tail_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_axi4_sosi;
@@ -191,11 +195,12 @@ end axi4_stream_pkg;
package body axi4_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_axi4_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_axi4_sosi;
- signal siso : in t_axi4_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_axi4_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_axi4_sosi;
+ signal siso : in t_axi4_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.tready;
-- Register siso.ready in c_ready_latency registers
@@ -210,20 +215,22 @@ package body axi4_stream_pkg is
end proc_axi4_siso_alert;
-- Default RL=1
- procedure proc_axi4_siso_alert(signal clk : in std_logic;
- signal sosi : in t_axi4_sosi;
- signal siso : in t_axi4_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_axi4_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_axi4_sosi;
+ signal siso : in t_axi4_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_axi4_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_axi4_siso_alert;
-- SOSI/SISO array version
- procedure proc_axi4_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_axi4_sosi_arr;
- signal siso_arr : in t_axi4_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_axi4_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_axi4_sosi_arr;
+ signal siso_arr : in t_axi4_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).tready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -241,10 +248,11 @@ package body axi4_stream_pkg is
end proc_axi4_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_axi4_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_axi4_sosi_arr;
- signal siso_arr : in t_axi4_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_axi4_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_axi4_sosi_arr;
+ signal siso_arr : in t_axi4_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_axi4_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_axi4_siso_alert;
@@ -720,7 +728,7 @@ package body axi4_stream_pkg is
function func_axi4_stream_from_dp_siso(dp_siso : t_dp_siso) return t_axi4_siso is
variable v_axi4_siso : t_axi4_siso := c_axi4_siso_rst;
- -- Note that dp_siso.xon is not used.
+ -- Note that dp_siso.xon is not used.
begin
v_axi4_siso.tready := dp_siso.ready;
return v_axi4_siso;
diff --git a/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
index ca7be826cf..0e784728f3 100644
--- a/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
@@ -26,12 +26,12 @@
-- DP stream. The resulting DP stream is verified.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.axi4_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.axi4_stream_pkg.all;
entity tb_axi4_stream_dp_bridge is
generic (
@@ -164,26 +164,26 @@ begin
dut_sosi.eop <= in_eop;
dut : entity work.axi4_stream_dp_bridge
- generic map (
- g_use_empty => true,
- g_axi4_rl => g_axi4_rl,
- g_dp_rl => g_dp_rl
- )
- port map (
- in_rst => rst,
- in_clk => clk,
- -- ST sink
- dp_in_siso => dut_siso,
- dp_in_sosi => dut_sosi,
- -- ST source
- dp_out_siso => dut_out_siso,
- dp_out_sosi => dut_out_sosi,
- -- AXI4 Loopback
- axi4_in_sosi => dut_axi4_sosi,
- axi4_in_siso => dut_axi4_siso,
- axi4_out_sosi => dut_axi4_sosi,
- axi4_out_siso => dut_axi4_siso
- );
+ generic map (
+ g_use_empty => true,
+ g_axi4_rl => g_axi4_rl,
+ g_dp_rl => g_dp_rl
+ )
+ port map (
+ in_rst => rst,
+ in_clk => clk,
+ -- ST sink
+ dp_in_siso => dut_siso,
+ dp_in_sosi => dut_sosi,
+ -- ST source
+ dp_out_siso => dut_out_siso,
+ dp_out_sosi => dut_out_sosi,
+ -- AXI4 Loopback
+ axi4_in_sosi => dut_axi4_sosi,
+ axi4_in_siso => dut_axi4_siso,
+ axi4_out_sosi => dut_axi4_sosi,
+ axi4_out_siso => dut_axi4_siso
+ );
-- map record to sl, slv
dut_out_siso.ready <= out_ready; -- SISO
diff --git a/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
index 28f6ea68f5..ee636ba2b0 100644
--- a/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
@@ -25,7 +25,7 @@
-- ready-latency configurations.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_axi4_stream_dp_bridge is
end tb_tb_axi4_stream_dp_bridge;
diff --git a/libraries/base/common/src/vhdl/avs_common_mm.vhd b/libraries/base/common/src/vhdl/avs_common_mm.vhd
index 3739dffc6f..8a6932b17c 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd b/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
index 1f9b9ac8d3..da8aa33e94 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
@@ -27,7 +27,7 @@
-- . The avs_common_mm_irq_hw.tcl determines the read latency, which is 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm_irq is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd b/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd
index 474b078567..d5765820e2 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd
@@ -29,7 +29,7 @@
-- Read latency 0 implies that the MM bus needs to use the waitrequest signal.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm_readlatency0 is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd b/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd
index a3cdecdfc3..f11e33c9a0 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd
@@ -28,7 +28,7 @@
-- avs_common_mm_hw.tcl.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm_readlatency2 is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd b/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd
index c07a16f315..b9e68f8d6c 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd
@@ -28,7 +28,7 @@
-- avs_common_mm_hw.tcl.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm_readlatency4 is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
index bdf118db20..c683498e5e 100644
--- a/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
@@ -31,8 +31,8 @@
-- 4) Connect wr_adr and rd_adr to have a shared address bus register.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
entity avs_common_ram_crw_crw is
generic ( -- t_c_mem := (c_mem_ram_rd_latency, 10, 9, 2**10, 'X'); -- 1 M9K
@@ -71,27 +71,27 @@ architecture wrap of avs_common_ram_crw_crw is
begin
u_common_ram_crw_crw : entity work.common_ram_crw_crw
generic map(
- g_ram => c_avs_memrec,
- g_init_file => g_init_file
+ g_ram => c_avs_memrec,
+ g_init_file => g_init_file
)
port map(
- rst_a => csi_system_reset,
- rst_b => coe_rst_export,
- clk_a => csi_system_clk,
- clk_b => coe_clk_export,
- clken_a => '1',
- clken_b => '1',
- wr_en_a => avs_ram_write,
- wr_en_b => coe_wr_en_export,
- wr_dat_a => avs_ram_writedata,
- wr_dat_b => coe_wr_dat_export,
- adr_a => avs_ram_address,
- adr_b => coe_adr_export,
- rd_en_a => avs_ram_read,
- rd_en_b => coe_rd_en_export,
- rd_dat_a => avs_ram_readdata,
- rd_dat_b => coe_rd_dat_export,
- rd_val_a => OPEN,
- rd_val_b => coe_rd_val_export
+ rst_a => csi_system_reset,
+ rst_b => coe_rst_export,
+ clk_a => csi_system_clk,
+ clk_b => coe_clk_export,
+ clken_a => '1',
+ clken_b => '1',
+ wr_en_a => avs_ram_write,
+ wr_en_b => coe_wr_en_export,
+ wr_dat_a => avs_ram_writedata,
+ wr_dat_b => coe_wr_dat_export,
+ adr_a => avs_ram_address,
+ adr_b => coe_adr_export,
+ rd_en_a => avs_ram_read,
+ rd_en_b => coe_rd_en_export,
+ rd_dat_a => avs_ram_readdata,
+ rd_dat_b => coe_rd_dat_export,
+ rd_val_a => OPEN,
+ rd_val_b => coe_rd_val_export
);
end wrap;
diff --git a/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd b/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
index dda7949904..c9ea1cc9e4 100644
--- a/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
@@ -31,9 +31,9 @@
-- 4) Connect wr_adr and rd_adr to have a shared address bus register.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
entity avs_common_reg_r_w is
generic (
diff --git a/libraries/base/common/src/vhdl/common_acapture.vhd b/libraries/base/common/src/vhdl/common_acapture.vhd
index cd7ccca147..5f8cc188c6 100644
--- a/libraries/base/common/src/vhdl/common_acapture.vhd
+++ b/libraries/base/common/src/vhdl/common_acapture.vhd
@@ -38,8 +38,8 @@
-- = 1 could be used.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity common_acapture is
generic (
@@ -64,28 +64,28 @@ begin
-- pipeline input (all in input clock domain)
u_async_in : entity work.common_async
- generic map (
- g_rst_level => g_rst_level,
- g_delay_len => g_in_delay_len
- )
- port map (
- rst => in_rst,
- clk => in_clk,
- din => in_dat,
- dout => i_in_cap
- );
+ generic map (
+ g_rst_level => g_rst_level,
+ g_delay_len => g_in_delay_len
+ )
+ port map (
+ rst => in_rst,
+ clk => in_clk,
+ din => in_dat,
+ dout => i_in_cap
+ );
-- capture input into output clock domain with first FF, and
-- additional pipeline output with extra FF when g_out_delay_len > 1 to combat potential meta-stability
u_async_out : entity work.common_async
- generic map (
- g_rst_level => g_rst_level,
- g_delay_len => g_out_delay_len
- )
- port map (
- rst => in_rst,
- clk => out_clk,
- din => i_in_cap,
- dout => out_cap
- );
+ generic map (
+ g_rst_level => g_rst_level,
+ g_delay_len => g_out_delay_len
+ )
+ port map (
+ rst => in_rst,
+ clk => out_clk,
+ din => i_in_cap,
+ dout => out_cap
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_acapture_slv.vhd b/libraries/base/common/src/vhdl/common_acapture_slv.vhd
index 04aa197055..0a2a553c19 100644
--- a/libraries/base/common/src/vhdl/common_acapture_slv.vhd
+++ b/libraries/base/common/src/vhdl/common_acapture_slv.vhd
@@ -27,8 +27,8 @@
-- fit in 1 LAB if in_dat'LENGTH <= 10.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity common_acapture_slv is
generic (
@@ -51,19 +51,19 @@ architecture str of common_acapture_slv is
begin
gen_slv: for I in in_dat'range generate
u_acap : entity work.common_acapture
- generic map (
- g_rst_level => g_rst_level,
- g_in_delay_len => g_in_delay_len,
- g_out_delay_len => g_out_delay_len
- )
- port map (
- in_rst => in_rst,
- in_clk => in_clk,
- in_dat => in_dat(I),
- in_cap => in_cap(I),
- out_clk => out_clk,
- out_cap => out_cap(I)
- );
+ generic map (
+ g_rst_level => g_rst_level,
+ g_in_delay_len => g_in_delay_len,
+ g_out_delay_len => g_out_delay_len
+ )
+ port map (
+ in_rst => in_rst,
+ in_clk => in_clk,
+ in_dat => in_dat(I),
+ in_cap => in_cap(I),
+ out_clk => out_clk,
+ out_cap => out_cap(I)
+ );
end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_accumulate.vhd b/libraries/base/common/src/vhdl/common_accumulate.vhd
index f891ae560a..ee0479631a 100644
--- a/libraries/base/common/src/vhdl/common_accumulate.vhd
+++ b/libraries/base/common/src/vhdl/common_accumulate.vhd
@@ -26,9 +26,9 @@
-- active.
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use work.common_pkg.all;
entity common_accumulate is
generic (
@@ -46,9 +46,9 @@ entity common_accumulate is
end common_accumulate;
architecture rtl of common_accumulate is
- constant c_acc_w : natural := out_dat'length;
+ constant c_acc_w : natural := out_dat'length;
- signal result : std_logic_vector(c_acc_w - 1 downto 0);
+ signal result : std_logic_vector(c_acc_w - 1 downto 0);
begin
process(rst, clk)
begin
diff --git a/libraries/base/common/src/vhdl/common_add_sub.vhd b/libraries/base/common/src/vhdl/common_add_sub.vhd
index 62efa07c4d..d71dbaa1e7 100644
--- a/libraries/base/common/src/vhdl/common_add_sub.vhd
+++ b/libraries/base/common/src/vhdl/common_add_sub.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_add_sub is
generic (
@@ -82,16 +82,16 @@ begin
end generate;
u_output_pipe : entity work.common_pipeline -- pipeline output
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline_output, -- 0 for wires, >0 for register stages
- g_in_dat_w => result'LENGTH,
- g_out_dat_w => result'length
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => result_p(result'range),
- out_dat => result
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline_output, -- 0 for wires, >0 for register stages
+ g_in_dat_w => result'LENGTH,
+ g_out_dat_w => result'length
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => result_p(result'range),
+ out_dat => result
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_add_symbol.vhd b/libraries/base/common/src/vhdl/common_add_symbol.vhd
index 5472ab24a5..9bc7d05535 100644
--- a/libraries/base/common/src/vhdl/common_add_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_add_symbol.vhd
@@ -20,19 +20,19 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
--- Purpose: Per symbol add of the two input data stream
--- Description:
--- The in_a, in_b and out_data are slv with g_nof_symbols-1:0 concatenated
--- symbols. The out_data contains the sum of each pair of symbols in in_a
--- and in_b. The symbol width is g_symbol_w. The output can be pipelined via
--- g_pipeline.
--- Remarks:
--- . No need for g_representation = "SIGNED" or "UNSIGNED", because that is
--- only important if output width > input width, and not relevant here where
--- both output width and input width are g_symbol_w
+ -- Purpose: Per symbol add of the two input data stream
+ -- Description:
+ -- The in_a, in_b and out_data are slv with g_nof_symbols-1:0 concatenated
+ -- symbols. The out_data contains the sum of each pair of symbols in in_a
+ -- and in_b. The symbol width is g_symbol_w. The output can be pipelined via
+ -- g_pipeline.
+ -- Remarks:
+ -- . No need for g_representation = "SIGNED" or "UNSIGNED", because that is
+ -- only important if output width > input width, and not relevant here where
+ -- both output width and input width are g_symbol_w
entity common_add_symbol is
generic (
@@ -79,49 +79,49 @@ begin
-- pipeline data output
u_out_data : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_symbols * g_symbol_w,
- g_out_dat_w => g_nof_symbols * g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sum_data,
- out_dat => out_data
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_symbols * g_symbol_w,
+ g_out_dat_w => g_nof_symbols * g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sum_data,
+ out_dat => out_data
+ );
-- pipeline control output
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => out_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => out_sop
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => out_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => out_eop
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => out_eop
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_adder_tree.vhd b/libraries/base/common/src/vhdl/common_adder_tree.vhd
index 7d95c7b027..f00c9fad46 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree.vhd
@@ -20,21 +20,21 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
--- Purpose: Parallel adder tree.
--- Description:
--- . Add g_nof_inputs from an input vector in_dat. The number of stages in the
--- adder tree is ceil_log2(g_nof_inputs). Each amount of pipelining per stage
--- is set by g_pipeline.
--- Remarks:
--- . Use ceil_log2(g_nof_inputs) instead of true_log2() for the number of
--- stages in the adder tree, to have also for g_nof_inputs = 1 one stage that
--- effectively adds 0 to the single in_dat. In this way this 'str'
--- architecture behaves the same as the 'recursive' architecture for
--- g_nof_inputs = 1. The 'recursive' architecture uses this one bit growth
--- for g_nof_inputs = 1 to match the bit growth of a parallel adder in the
--- same stage when g_nof_inputs is odd.
+ -- Purpose: Parallel adder tree.
+ -- Description:
+ -- . Add g_nof_inputs from an input vector in_dat. The number of stages in the
+ -- adder tree is ceil_log2(g_nof_inputs). Each amount of pipelining per stage
+ -- is set by g_pipeline.
+ -- Remarks:
+ -- . Use ceil_log2(g_nof_inputs) instead of true_log2() for the number of
+ -- stages in the adder tree, to have also for g_nof_inputs = 1 one stage that
+ -- effectively adds 0 to the single in_dat. In this way this 'str'
+ -- architecture behaves the same as the 'recursive' architecture for
+ -- g_nof_inputs = 1. The 'recursive' architecture uses this one bit growth
+ -- for g_nof_inputs = 1 to match the bit growth of a parallel adder in the
+ -- same stage when g_nof_inputs is odd.
entity common_adder_tree is
generic (
diff --git a/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd b/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
index ece19109a0..29c0276357 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
architecture recursive of common_adder_tree is
-- common_add_sub pipelining
@@ -77,37 +77,37 @@ architecture recursive of common_adder_tree is
begin
leaf_pipe : if g_nof_inputs = 1 generate
u_reg : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w + 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- out_dat => result
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w + 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ out_dat => result
+ );
end generate;
leaf_add : if g_nof_inputs = 2 generate
u_add : entity work.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => g_representation,
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => c_sum_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => in_dat( g_dat_w - 1 downto 0 ),
- in_b => in_dat(2 * g_dat_w - 1 downto g_dat_w),
- result => result
- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => g_representation,
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => c_sum_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => in_dat( g_dat_w - 1 downto 0 ),
+ in_b => in_dat(2 * g_dat_w - 1 downto g_dat_w),
+ result => result
+ );
end generate;
gen_tree : if g_nof_inputs > 2 generate
@@ -147,36 +147,36 @@ begin
gen_reg_h1 : if c_stage_h1 = true generate
u_reg_h1 : entity work.common_pipeline
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => c_sum_h1_w,
+ g_out_dat_w => c_sum_h2_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => sum_h1,
+ out_dat => sum_h1_reg
+ );
+ end generate;
+
+ trunk_add : entity work.common_add_sub
generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => c_sum_h1_w,
- g_out_dat_w => c_sum_h2_w
+ g_direction => "ADD",
+ g_representation => g_representation,
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => c_sum_h_w,
+ g_out_dat_w => c_sum_w
)
port map (
clk => clk,
clken => clken,
- in_dat => sum_h1,
- out_dat => sum_h1_reg
+ in_a => sum_h1_reg,
+ in_b => sum_h2,
+ result => result
);
- end generate;
-
- trunk_add : entity work.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => g_representation,
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => c_sum_h_w,
- g_out_dat_w => c_sum_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => sum_h1_reg,
- in_b => sum_h2,
- result => result
- );
end generate;
sum <= RESIZE_SVEC(result, g_sum_w) when g_representation = "SIGNED" else RESIZE_UVEC(result, g_sum_w);
diff --git a/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd b/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
index 579de011dc..fc7dda3d50 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
architecture str of common_adder_tree is
-- common_add_sub pipelining
@@ -91,39 +91,39 @@ begin
gen_stage : for j in 0 to c_nof_stages - 1 generate
gen_add : for i in 0 to (c_N + (2**j) - 1) / (2**(j + 1)) - 1 generate
u_addj : entity work.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => g_representation,
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => c_w + j,
- g_out_dat_w => c_w + j + 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => adds(j - 1)((2 * i + 1) * (c_w + j) - 1 downto (2 * i + 0) * (c_w + j)),
- in_b => adds(j - 1)((2 * i + 2) * (c_w + j) - 1 downto (2 * i + 1) * (c_w + j)),
- result => adds(j)((i + 1) * (c_w + j + 1) - 1 downto i * (c_w + j + 1))
- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => g_representation,
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => c_w + j,
+ g_out_dat_w => c_w + j + 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => adds(j - 1)((2 * i + 1) * (c_w + j) - 1 downto (2 * i + 0) * (c_w + j)),
+ in_b => adds(j - 1)((2 * i + 2) * (c_w + j) - 1 downto (2 * i + 1) * (c_w + j)),
+ result => adds(j)((i + 1) * (c_w + j + 1) - 1 downto i * (c_w + j + 1))
+ );
end generate;
gen_pipe : if ((c_N + (2**j) - 1) / (2**j)) mod 2 /= 0 generate
u_pipej : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => c_w + j,
- g_out_dat_w => c_w + j + 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => adds(j - 1)((2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 1) * (c_w + j) - 1 downto
- (2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 0) * (c_w + j)),
- out_dat => adds(j)(((c_N + (2**j) - 1) / (2**(j + 1)) + 1) * (c_w + j + 1) - 1 downto
- ((c_N + (2**j) - 1) / (2**(j + 1)) ) * (c_w + j + 1))
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => c_w + j,
+ g_out_dat_w => c_w + j + 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => adds(j - 1)((2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 1) * (c_w + j) - 1 downto
+ (2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 0) * (c_w + j)),
+ out_dat => adds(j)(((c_N + (2**j) - 1) / (2**(j + 1)) + 1) * (c_w + j + 1) - 1 downto
+ ((c_N + (2**j) - 1) / (2**(j + 1)) ) * (c_w + j + 1))
+ );
end generate;
end generate;
@@ -138,18 +138,18 @@ begin
-- g_dat_w+1 also for g_nof_inputs = 1, because we assume an adder stage
-- that adds 0 to the single in_dat.
u_reg : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_sum_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- out_dat => sum
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_sum_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ out_dat => sum
+ );
end generate; -- no_tree
end str;
diff --git a/libraries/base/common/src/vhdl/common_areset.vhd b/libraries/base/common/src/vhdl/common_areset.vhd
index 13c3a2454c..e0e4232ad4 100644
--- a/libraries/base/common/src/vhdl/common_areset.vhd
+++ b/libraries/base/common/src/vhdl/common_areset.vhd
@@ -32,14 +32,14 @@
-- . The in_rst can also synchronise other signals than a reset, e.g. a locked signal from a PLL.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_areset is
generic (
g_in_rst_level : std_logic := '1'; -- = in_rst level
g_rst_level : std_logic := '1'; -- = out_rst level (keep original generic
- -- name for backward compatibility)
+ -- name for backward compatibility)
g_delay_len : natural := c_meta_delay_len
);
port (
@@ -58,14 +58,14 @@ begin
i_rst <= in_rst when g_in_rst_level = '1' else not in_rst;
u_async : entity work.common_async
- generic map (
- g_rst_level => c_out_rst_level,
- g_delay_len => g_delay_len
- )
- port map (
- rst => i_rst,
- clk => clk,
- din => c_out_rst_level_n,
- dout => out_rst
- );
+ generic map (
+ g_rst_level => c_out_rst_level,
+ g_delay_len => g_delay_len
+ )
+ port map (
+ rst => i_rst,
+ clk => clk,
+ din => c_out_rst_level_n,
+ dout => out_rst
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_async.vhd b/libraries/base/common/src/vhdl/common_async.vhd
index e4a037445b..26eb0e144d 100644
--- a/libraries/base/common/src/vhdl/common_async.vhd
+++ b/libraries/base/common/src/vhdl/common_async.vhd
@@ -24,8 +24,8 @@
-- The delay line combats the potential meta-stability of clocked in data.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity common_async is
generic (
diff --git a/libraries/base/common/src/vhdl/common_async_slv.vhd b/libraries/base/common/src/vhdl/common_async_slv.vhd
index 1ff3d1454a..208129c0ae 100644
--- a/libraries/base/common/src/vhdl/common_async_slv.vhd
+++ b/libraries/base/common/src/vhdl/common_async_slv.vhd
@@ -25,8 +25,8 @@
-- Remark:
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_async_slv is
generic (
@@ -45,16 +45,16 @@ architecture str of common_async_slv is
begin
gen_slv: for I in dout'range generate
u_common_async : entity work.common_async
- generic map (
- g_rst_level => g_rst_level,
- g_delay_len => g_delay_len
- )
- port map (
- rst => rst,
- clk => clk,
- din => din(I),
- dout => dout(I)
- );
+ generic map (
+ g_rst_level => g_rst_level,
+ g_delay_len => g_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ din => din(I),
+ dout => dout(I)
+ );
end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_bit_delay.vhd b/libraries/base/common/src/vhdl/common_bit_delay.vhd
index 2f3dc51f73..bc1c16125e 100644
--- a/libraries/base/common/src/vhdl/common_bit_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_bit_delay.vhd
@@ -34,7 +34,7 @@
-- to remove in_clr or to not use shift_reg(0) combinatorially.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_bit_delay is
generic (
diff --git a/libraries/base/common/src/vhdl/common_blockreg.vhd b/libraries/base/common/src/vhdl/common_blockreg.vhd
index dafbf3163e..def58f21bd 100755
--- a/libraries/base/common/src/vhdl/common_blockreg.vhd
+++ b/libraries/base/common/src/vhdl/common_blockreg.vhd
@@ -37,10 +37,10 @@
-- valid-dependent like the rest).
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_blockreg is
generic (
@@ -79,25 +79,25 @@ begin
out_val <= i_out_val;
u_fifo : entity work.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => false,
- g_dat_w => g_dat_w,
- g_nof_words => g_block_size+1
- )
- port map (
- clk => clk,
- rst => rst,
-
- wr_dat => in_dat,
- wr_req => in_val,
-
- usedw => usedw,
- rd_req => rd_req,
-
- rd_dat => out_dat,
- rd_val => i_out_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => false,
+ g_dat_w => g_dat_w,
+ g_nof_words => g_block_size+1
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ wr_dat => in_dat,
+ wr_req => in_val,
+
+ usedw => usedw,
+ rd_req => rd_req,
+
+ rd_dat => out_dat,
+ rd_val => i_out_val
+ );
-----------------------------------------------------------------------------
-- Toggle rd_req to create output blocks of g_block_size
@@ -138,11 +138,11 @@ begin
p_clk : process(rst, clk)
begin
if rst = '1' then
- out_cnt <= (others => '0');
- prev_rd_req <= '0';
- elsif rising_edge(clk) then
- out_cnt <= nxt_out_cnt;
- prev_rd_req <= rd_req;
+ out_cnt <= (others => '0');
+ prev_rd_req <= '0';
+ elsif rising_edge(clk) then
+ out_cnt <= nxt_out_cnt;
+ prev_rd_req <= rd_req;
end if;
end process;
diff --git a/libraries/base/common/src/vhdl/common_clip.vhd b/libraries/base/common/src/vhdl/common_clip.vhd
index 3f83c3d3a8..17abe7a33c 100644
--- a/libraries/base/common/src/vhdl/common_clip.vhd
+++ b/libraries/base/common/src/vhdl/common_clip.vhd
@@ -20,21 +20,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
--- Function:
--- When enabled clip input, else pass input on unchanged. Report clippled
--- output data via overflow bit.
--- . Clip signed input to range [-g_full_scale +g_full_scale]
--- . Clip unsigned input to range [ 0 +g_full_scale]
--- Remark:
--- . Define g_full_scale as SIGNED to avoid NATURAL limited to <= 2**31-1.
--- . Input and output must have the same width
--- . Use g_full_scale = 2**(c_dat_w-1)-1 to achieve a symmetrical range which
--- allow skipping one sign bit after multiplication. E.g. 18b*18b --> 35b
--- are sufficient for the signed product instead of 36b.
+ -- Function:
+ -- When enabled clip input, else pass input on unchanged. Report clippled
+ -- output data via overflow bit.
+ -- . Clip signed input to range [-g_full_scale +g_full_scale]
+ -- . Clip unsigned input to range [ 0 +g_full_scale]
+ -- Remark:
+ -- . Define g_full_scale as SIGNED to avoid NATURAL limited to <= 2**31-1.
+ -- . Input and output must have the same width
+ -- . Use g_full_scale = 2**(c_dat_w-1)-1 to achieve a symmetrical range which
+ -- allow skipping one sign bit after multiplication. E.g. 18b*18b --> 35b
+ -- are sufficient for the signed product instead of 36b.
entity common_clip is
generic (
@@ -118,18 +118,18 @@ begin
pipe_in <= clip_ovr & clip_dat;
u_output_pipe : entity work.common_pipeline
- generic map (
- g_pipeline => c_output_pipe,
- g_in_dat_w => c_dat_w + 1,
- g_out_dat_w => c_dat_w + 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_dat => pipe_in,
- out_dat => pipe_out
- );
+ generic map (
+ g_pipeline => c_output_pipe,
+ g_in_dat_w => c_dat_w + 1,
+ g_out_dat_w => c_dat_w + 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_dat => pipe_in,
+ out_dat => pipe_out
+ );
out_ovr <= pipe_out(pipe_out'high);
out_dat <= pipe_out(pipe_out'high - 1 downto 0);
diff --git a/libraries/base/common/src/vhdl/common_clock_active_detector.vhd b/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
index 246e57815e..a8e0359faa 100644
--- a/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
+++ b/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
--- Purpose: Detect 400 MHz in_clk active in the 200 MHz dp_clk domain
--- Description:
+ -- Purpose: Detect 400 MHz in_clk active in the 200 MHz dp_clk domain
+ -- Description:
entity common_clock_active_detector is
generic (
@@ -74,55 +74,55 @@ architecture str of common_clock_active_detector is
signal nxt_dp_in_clk_detected : std_logic;
begin
u_common_counter_in_clk : entity work.common_counter
- generic map (
- g_width => g_in_period_w
- )
- port map (
- rst => '0',
- clk => in_clk,
- count => in_clk_cnt
- );
+ generic map (
+ g_width => g_in_period_w
+ )
+ port map (
+ rst => '0',
+ clk => in_clk,
+ count => in_clk_cnt
+ );
in_toggle <= in_clk_cnt(in_clk_cnt'high);
u_common_async_dp_toggle : entity work.common_async
- generic map (
- g_rst_level => '1',
- g_delay_len => c_delay_len
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- din => in_toggle,
- dout => dp_toggle
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_delay_len
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ din => in_toggle,
+ dout => dp_toggle
+ );
u_common_evt : entity work.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_reg => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_sig => dp_toggle,
- out_evt => dp_toggle_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_reg => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_sig => dp_toggle,
+ out_evt => dp_toggle_revt
+ );
dp_clk_cnt_en <= '1' when unsigned(dp_clk_cnt) < c_dp_clk_cnt_max else '0';
dp_clk_cnt_clr <= dp_toggle_revt or not dp_clk_cnt_en;
u_common_counter_dp_clk : entity work.common_counter
- generic map (
- g_width => c_dp_clk_cnt_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- cnt_clr => dp_clk_cnt_clr,
- cnt_en => dp_clk_cnt_en,
- count => dp_clk_cnt
- );
+ generic map (
+ g_width => c_dp_clk_cnt_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ cnt_clr => dp_clk_cnt_clr,
+ cnt_en => dp_clk_cnt_en,
+ count => dp_clk_cnt
+ );
nxt_dp_clk_interval <= INCR_UVEC(dp_clk_cnt, 1) when dp_clk_cnt_clr = '1' else dp_clk_interval;
@@ -142,12 +142,12 @@ begin
dp_in_clk_detected <= i_dp_in_clk_detected;
u_common_stable_monitor : entity work.common_stable_monitor
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- MM
- r_in => i_dp_in_clk_detected,
- r_stable => dp_in_clk_stable,
- r_stable_ack => dp_in_clk_stable_ack
- );
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- MM
+ r_in => i_dp_in_clk_detected,
+ r_stable => dp_in_clk_stable,
+ r_stable_ack => dp_in_clk_stable_ack
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd b/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
index b44ac564c5..75a84912a0 100644
--- a/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
+++ b/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
@@ -93,8 +93,8 @@
-- pipeline stage.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_clock_phase_detector is
generic (
@@ -129,17 +129,17 @@ architecture str of common_clock_phase_detector is
begin
-- Capture the in_clk in the clk domain
u_async : entity work.common_async
- generic map (
- g_rising_edge => g_rising_edge,
- g_rst_level => g_phase_rst_level,
- g_delay_len => c_delay_len
- )
- port map (
- rst => rst,
- clk => clk,
- din => in_clk,
- dout => in_phs_cap
- );
+ generic map (
+ g_rising_edge => g_rising_edge,
+ g_rst_level => g_phase_rst_level,
+ g_delay_len => c_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ din => in_clk,
+ dout => in_phs_cap
+ );
-- Process the registers in the rising edge clk domain
gen_r_wire : if g_rising_edge = true generate
diff --git a/libraries/base/common/src/vhdl/common_complex_add_sub.vhd b/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
index 51192d7b4c..1fa4bff9b0 100644
--- a/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
+++ b/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_complex_add_sub is
generic (
@@ -46,36 +46,36 @@ end common_complex_add_sub;
architecture str of common_complex_add_sub is
begin
add_re : entity work.common_add_sub
- generic map (
- g_direction => g_direction,
- g_representation => g_representation,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => in_ar,
- in_b => in_br,
- result => out_re
- );
+ generic map (
+ g_direction => g_direction,
+ g_representation => g_representation,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => in_ar,
+ in_b => in_br,
+ result => out_re
+ );
add_im : entity work.common_add_sub
- generic map (
- g_direction => g_direction,
- g_representation => g_representation,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => in_ai,
- in_b => in_bi,
- result => out_im
- );
+ generic map (
+ g_direction => g_direction,
+ g_representation => g_representation,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => in_ai,
+ in_b => in_bi,
+ result => out_im
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_complex_round.vhd b/libraries/base/common/src/vhdl/common_complex_round.vhd
index b365d78a72..71336ba9c1 100644
--- a/libraries/base/common/src/vhdl/common_complex_round.vhd
+++ b/libraries/base/common/src/vhdl/common_complex_round.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_complex_round is
generic (
@@ -45,36 +45,36 @@ end;
architecture str of common_complex_round is
begin
re: entity work.common_round
- generic map (
- g_representation => g_representation,
- g_round => g_round,
- g_round_clip => g_round_clip,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_re,
- out_dat => out_re
- );
+ generic map (
+ g_representation => g_representation,
+ g_round => g_round,
+ g_round_clip => g_round_clip,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_re,
+ out_dat => out_re
+ );
im: entity work.common_round
- generic map (
- g_representation => g_representation,
- g_round => g_round,
- g_round_clip => g_round_clip,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_im,
- out_dat => out_im
- );
+ generic map (
+ g_representation => g_representation,
+ g_round => g_round,
+ g_round_clip => g_round_clip,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_im,
+ out_dat => out_im
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_components_pkg.vhd b/libraries/base/common/src/vhdl/common_components_pkg.vhd
index ba5e04a595..2aee371913 100644
--- a/libraries/base/common/src/vhdl/common_components_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_components_pkg.vhd
@@ -20,32 +20,32 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
--- Purpose: Component declarations to check positional mapping
--- Description:
--- Remarks:
+ -- Purpose: Component declarations to check positional mapping
+ -- Description:
+ -- Remarks:
package common_components_pkg is
component common_pipeline is
- generic (
- g_representation : string := "SIGNED"; -- or "UNSIGNED"
- g_pipeline : natural := 1; -- 0 for wires, > 0 for registers,
- g_reset_value : integer := 0;
- g_in_dat_w : natural := 8;
- g_out_dat_w : natural := 9
- );
- port (
- rst : in std_logic := '0';
- clk : in std_logic;
- clken : in std_logic := '1';
- in_clr : in std_logic := '0';
- in_en : in std_logic := '1';
- in_dat : in std_logic_vector(g_in_dat_w - 1 downto 0);
- out_dat : out std_logic_vector(g_out_dat_w - 1 downto 0)
- );
+ generic (
+ g_representation : string := "SIGNED"; -- or "UNSIGNED"
+ g_pipeline : natural := 1; -- 0 for wires, > 0 for registers,
+ g_reset_value : integer := 0;
+ g_in_dat_w : natural := 8;
+ g_out_dat_w : natural := 9
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_clr : in std_logic := '0';
+ in_en : in std_logic := '1';
+ in_dat : in std_logic_vector(g_in_dat_w - 1 downto 0);
+ out_dat : out std_logic_vector(g_out_dat_w - 1 downto 0)
+ );
end component;
component common_pipeline_sl is
diff --git a/libraries/base/common/src/vhdl/common_counter.vhd b/libraries/base/common/src/vhdl/common_counter.vhd
index e5a449527e..526622268b 100644
--- a/libraries/base/common/src/vhdl/common_counter.vhd
+++ b/libraries/base/common/src/vhdl/common_counter.vhd
@@ -33,8 +33,8 @@
-- via ceil_log2(g_max+1)>g_width and use this to init the cnt_max input.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_counter is
generic (
@@ -53,7 +53,7 @@ entity common_counter is
cnt_ld : in std_logic := '0'; -- cnt_ld loads the output count with the input load value, independent of cnt_en
cnt_en : in std_logic := '1';
cnt_max : in std_logic_vector(g_width - 1 downto 0) := sel_a_b( g_step_size > 0 and g_max = 0, array_init('1', g_width),
- sel_a_b( ceil_log2(g_max + 1) > g_width, array_init('1', g_width), TO_UVEC(g_max, g_width) )); -- see remarks
+ sel_a_b( ceil_log2(g_max + 1) > g_width, array_init('1', g_width), TO_UVEC(g_max, g_width) )); -- see remarks
load : in std_logic_vector(g_width - 1 downto 0) := TO_SVEC(g_init, g_width);
count : out std_logic_vector(g_width - 1 downto 0)
);
diff --git a/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd b/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
index a89e287f0d..cbae24e810 100644
--- a/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
@@ -50,8 +50,8 @@
-- out_sop and other strobes.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_create_strobes_from_valid is
generic (
diff --git a/libraries/base/common/src/vhdl/common_ddio_in.vhd b/libraries/base/common/src/vhdl/common_ddio_in.vhd
index 4a1e3e3d6c..a179198b61 100644
--- a/libraries/base/common/src/vhdl/common_ddio_in.vhd
+++ b/libraries/base/common/src/vhdl/common_ddio_in.vhd
@@ -22,8 +22,8 @@
-- Purpose: Capture double data rate FPGA input
library IEEE, technology_lib, tech_iobuf_lib;
-use IEEE.std_logic_1164.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ddio_in is
generic(
@@ -43,16 +43,16 @@ end common_ddio_in;
architecture str of common_ddio_in is
begin
u_ddio_in : entity tech_iobuf_lib.tech_iobuf_ddio_in
- generic map (
- g_technology => g_technology,
- g_width => g_width
- )
- port map (
- in_dat => in_dat,
- in_clk => in_clk,
- in_clk_en => in_clk_en,
- rst => rst,
- out_dat_hi => out_dat_hi,
- out_dat_lo => out_dat_lo
- );
+ generic map (
+ g_technology => g_technology,
+ g_width => g_width
+ )
+ port map (
+ in_dat => in_dat,
+ in_clk => in_clk,
+ in_clk_en => in_clk_en,
+ rst => rst,
+ out_dat_hi => out_dat_hi,
+ out_dat_lo => out_dat_lo
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ddio_out.vhd b/libraries/base/common/src/vhdl/common_ddio_out.vhd
index 1806830f51..68db6376c8 100644
--- a/libraries/base/common/src/vhdl/common_ddio_out.vhd
+++ b/libraries/base/common/src/vhdl/common_ddio_out.vhd
@@ -22,8 +22,8 @@
-- Purpose: Double data rate FPGA output or register single data rate FPGA output
library IEEE, technology_lib, tech_iobuf_lib;
-use IEEE.std_logic_1164.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ddio_out is
generic(
@@ -43,16 +43,16 @@ end common_ddio_out;
architecture str of common_ddio_out is
begin
u_ddio_out : entity tech_iobuf_lib.tech_iobuf_ddio_out
- generic map (
- g_technology => g_technology,
- g_width => g_width
- )
- port map (
- rst => rst,
- in_clk => in_clk,
- in_clk_en => in_clk_en,
- in_dat_hi => in_dat_hi,
- in_dat_lo => in_dat_lo,
- out_dat => out_dat
- );
+ generic map (
+ g_technology => g_technology,
+ g_width => g_width
+ )
+ port map (
+ rst => rst,
+ in_clk => in_clk,
+ in_clk_en => in_clk_en,
+ in_dat_hi => in_dat_hi,
+ in_dat_lo => in_dat_lo,
+ out_dat => out_dat
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ddreg.vhd b/libraries/base/common/src/vhdl/common_ddreg.vhd
index 74638cc7e1..6289cd1675 100644
--- a/libraries/base/common/src/vhdl/common_ddreg.vhd
+++ b/libraries/base/common/src/vhdl/common_ddreg.vhd
@@ -70,8 +70,8 @@
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg_r is
generic (
@@ -93,29 +93,29 @@ architecture str of common_ddreg_r is
signal in_dat_d : std_logic;
begin
u_in : entity work.common_async
- generic map (
- g_delay_len => g_in_delay_len
- )
- port map (
- rst => rst,
- clk => in_clk,
- din => in_dat,
- dout => in_dat_r
- );
+ generic map (
+ g_delay_len => g_in_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => in_clk,
+ din => in_dat,
+ dout => in_dat_r
+ );
in_dat_d <= in_dat_r when g_tsetup_delay_hi = false else in_dat_r when rising_edge(out_clk);
-- Output at rising edge
u_out_hi : entity work.common_async
- generic map (
- g_delay_len => g_out_delay_len
- )
- port map (
- rst => rst,
- clk => out_clk,
- din => in_dat_d,
- dout => out_dat_r
- );
+ generic map (
+ g_delay_len => g_out_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => out_clk,
+ din => in_dat_d,
+ dout => out_dat_r
+ );
end str;
--------------------------------------------------------------------------------
@@ -123,8 +123,8 @@ end str;
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg_f is
generic (
@@ -146,30 +146,30 @@ architecture str of common_ddreg_f is
signal in_dat_d : std_logic;
begin
u_in : entity work.common_async
- generic map (
- g_delay_len => g_in_delay_len
- )
- port map (
- rst => rst,
- clk => in_clk,
- din => in_dat,
- dout => in_dat_r
- );
+ generic map (
+ g_delay_len => g_in_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => in_clk,
+ din => in_dat,
+ dout => in_dat_r
+ );
in_dat_d <= in_dat_r when g_tsetup_delay_lo = false else in_dat_r when falling_edge(out_clk);
-- Capture input at falling edge
u_fall : entity work.common_async
- generic map (
- g_rising_edge => false,
- g_delay_len => g_out_delay_len
- )
- port map (
- rst => rst,
- clk => out_clk,
- din => in_dat_d,
- dout => out_dat_f
- );
+ generic map (
+ g_rising_edge => false,
+ g_delay_len => g_out_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => out_clk,
+ din => in_dat_d,
+ dout => out_dat_f
+ );
end str;
--------------------------------------------------------------------------------
@@ -177,8 +177,8 @@ end str;
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg_fr is
port (
@@ -201,8 +201,8 @@ end str;
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg is
generic (
@@ -226,39 +226,39 @@ architecture str of common_ddreg is
begin
-- out_dat_hi
u_ddreg_hi : entity work.common_ddreg_r
- generic map (
- g_in_delay_len => g_in_delay_len,
- g_out_delay_len => g_out_delay_len,
- g_tsetup_delay_hi => g_tsetup_delay_hi
- )
- port map (
- in_clk => in_clk,
- in_dat => in_dat,
- rst => rst,
- out_clk => out_clk,
- out_dat_r => out_dat_hi
- );
+ generic map (
+ g_in_delay_len => g_in_delay_len,
+ g_out_delay_len => g_out_delay_len,
+ g_tsetup_delay_hi => g_tsetup_delay_hi
+ )
+ port map (
+ in_clk => in_clk,
+ in_dat => in_dat,
+ rst => rst,
+ out_clk => out_clk,
+ out_dat_r => out_dat_hi
+ );
-- out_dat_lo
u_ddreg_fall : entity work.common_ddreg_f
- generic map (
- g_in_delay_len => g_in_delay_len,
- g_out_delay_len => g_out_delay_len - 1,
- g_tsetup_delay_lo => g_tsetup_delay_lo
- )
- port map (
- in_clk => in_clk,
- in_dat => in_dat,
- rst => rst,
- out_clk => out_clk,
- out_dat_f => out_dat_f -- clocked at falling edge of out_clk
- );
+ generic map (
+ g_in_delay_len => g_in_delay_len,
+ g_out_delay_len => g_out_delay_len - 1,
+ g_tsetup_delay_lo => g_tsetup_delay_lo
+ )
+ port map (
+ in_clk => in_clk,
+ in_dat => in_dat,
+ rst => rst,
+ out_clk => out_clk,
+ out_dat_f => out_dat_f -- clocked at falling edge of out_clk
+ );
u_ddreg_lo : entity work.common_ddreg_fr
- port map (
- rst => rst,
- clk => out_clk,
- in_dat_f => out_dat_f,
- out_dat_r => out_dat_lo -- clocked at rising edge of out_clk
- );
+ port map (
+ rst => rst,
+ clk => out_clk,
+ in_dat_f => out_dat_f,
+ out_dat_r => out_dat_lo -- clocked at rising edge of out_clk
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ddreg_slv.vhd b/libraries/base/common/src/vhdl/common_ddreg_slv.vhd
index 3b8b40e132..a20243c15e 100644
--- a/libraries/base/common/src/vhdl/common_ddreg_slv.vhd
+++ b/libraries/base/common/src/vhdl/common_ddreg_slv.vhd
@@ -24,8 +24,8 @@
-- Remark:
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg_slv is
generic (
@@ -46,18 +46,18 @@ architecture str of common_ddreg_slv is
begin
gen_slv: for I in in_dat'range generate
u_ddreg : entity work.common_ddreg
- generic map (
- g_in_delay_len => g_in_delay_len,
- g_out_delay_len => g_out_delay_len
- )
- port map (
- in_clk => in_clk,
- in_dat => in_dat(I),
- rst => rst,
- out_clk => out_clk,
- out_dat_hi => out_dat_hi(I),
- out_dat_lo => out_dat_lo(I)
- );
+ generic map (
+ g_in_delay_len => g_in_delay_len,
+ g_out_delay_len => g_out_delay_len
+ )
+ port map (
+ in_clk => in_clk,
+ in_dat => in_dat(I),
+ rst => rst,
+ out_clk => out_clk,
+ out_dat_hi => out_dat_hi(I),
+ out_dat_lo => out_dat_lo(I)
+ );
end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_debounce.vhd b/libraries/base/common/src/vhdl/common_debounce.vhd
index fa2d76a017..22d3567471 100644
--- a/libraries/base/common/src/vhdl/common_debounce.vhd
+++ b/libraries/base/common/src/vhdl/common_debounce.vhd
@@ -20,20 +20,20 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
--- Purpose:
---
--- The output follows the input, but only if the input is stable for at least
--- g_latency clock cycles.
+ -- Purpose:
+ --
+ -- The output follows the input, but only if the input is stable for at least
+ -- g_latency clock cycles.
entity common_debounce is
generic (
g_type : string := "BOTH"; -- "BOTH" = debounce g_latency clk cycles for both bgoing high when d_in='1' and for going low when d_in='0'
- -- "HIGH" = debounce g_latency clk cycles for going high when d_in='1', go low immediately when d_in='0'
- -- "LOW" = debounce g_latency clk cycles for going low when d_in='0', go high immediately when d_in='1'
+ -- "HIGH" = debounce g_latency clk cycles for going high when d_in='1', go low immediately when d_in='0'
+ -- "LOW" = debounce g_latency clk cycles for going low when d_in='0', go high immediately when d_in='1'
g_delay_len : natural := c_meta_delay_len; -- = 3, combat meta stability
g_latency : natural := 8; -- >= 1, combat debounces over nof clk cycles
g_init_level : std_logic := '1'
@@ -99,15 +99,15 @@ begin
end generate;
u_counter : entity work.common_counter
- generic map (
- g_width => c_latency_w
- )
- port map (
- rst => '0',
- clk => clk,
- clken => clken,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => c_latency_w
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => clken,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_deinterleave.vhd b/libraries/base/common/src/vhdl/common_deinterleave.vhd
index 50f2901035..98e50420d2 100644
--- a/libraries/base/common/src/vhdl/common_deinterleave.vhd
+++ b/libraries/base/common/src/vhdl/common_deinterleave.vhd
@@ -20,17 +20,17 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-
--- Purpose: Deinterleave input into g_nof_out output streams based on g_block_size.
--- Description:
--- The output streams are concatenated into one SLV. Only one output is active
--- at a time. The active output is selected automatically and incrementally,
--- starting with output 0. The next output is selected after g_block_size
--- valid words on the currently selected output.
--- Remarks:
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+
+ -- Purpose: Deinterleave input into g_nof_out output streams based on g_block_size.
+ -- Description:
+ -- The output streams are concatenated into one SLV. Only one output is active
+ -- at a time. The active output is selected automatically and incrementally,
+ -- starting with output 0. The next output is selected after g_block_size
+ -- valid words on the currently selected output.
+ -- Remarks:
entity common_deinterleave is
generic (
@@ -38,7 +38,7 @@ entity common_deinterleave is
g_dat_w : natural;
g_block_size : natural;
g_align_out : boolean := false
- );
+ );
port (
clk : in std_logic;
rst : in std_logic;
@@ -69,18 +69,18 @@ architecture rtl of common_deinterleave is
signal nxt_demux_val_cnt : std_logic_vector(c_demux_val_cnt_w - 1 downto 0);
begin
u_demux : entity work.common_demultiplexer
- generic map (
- g_nof_out => g_nof_out,
- g_dat_w => g_dat_w
- )
- port map (
- in_dat => in_dat,
- in_val => in_val,
-
- out_sel => demux_out_sel,
- out_dat => demux_out_dat,
- out_val => demux_out_val
- );
+ generic map (
+ g_nof_out => g_nof_out,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ in_dat => in_dat,
+ in_val => in_val,
+
+ out_sel => demux_out_sel,
+ out_dat => demux_out_dat,
+ out_val => demux_out_val
+ );
-----------------------------------------------------------------------------
-- Demultiplexer output selection
@@ -131,21 +131,21 @@ begin
gen_align_out: if g_align_out = true generate
gen_inter: for i in 0 to g_nof_out - 1 generate
u_shiftreg : entity work.common_shiftreg
- generic map (
- g_pipeline => g_nof_out * g_block_size - (i + 1) * g_block_size,
- g_nof_dat => 1,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => demux_out_dat(i * g_dat_w + g_dat_w - 1 downto i * g_dat_w),
- in_val => demux_out_val(i),
-
- out_dat => out_dat(i * g_dat_w + g_dat_w - 1 downto i * g_dat_w),
- out_val => out_val(i)
- );
+ generic map (
+ g_pipeline => g_nof_out * g_block_size - (i + 1) * g_block_size,
+ g_nof_dat => 1,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => demux_out_dat(i * g_dat_w + g_dat_w - 1 downto i * g_dat_w),
+ in_val => demux_out_val(i),
+
+ out_dat => out_dat(i * g_dat_w + g_dat_w - 1 downto i * g_dat_w),
+ out_val => out_val(i)
+ );
end generate;
end generate;
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_delay.vhd b/libraries/base/common/src/vhdl/common_delay.vhd
index 0e72b75743..f26e36c3db 100644
--- a/libraries/base/common/src/vhdl/common_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_delay.vhd
@@ -25,7 +25,7 @@
-- indicates an active clock cycle.
library ieee;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_delay is
generic (
diff --git a/libraries/base/common/src/vhdl/common_demultiplexer.vhd b/libraries/base/common/src/vhdl/common_demultiplexer.vhd
index 52f37b9cd5..0ea051b431 100644
--- a/libraries/base/common/src/vhdl/common_demultiplexer.vhd
+++ b/libraries/base/common/src/vhdl/common_demultiplexer.vhd
@@ -20,14 +20,14 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_components_pkg.all;
--- Purpose: Assign input to one of g_nof_out output streams based on out_sel input
--- Description: The output streams are concatenated into one SLV.
--- Remarks:
--- . Same scheme for pipeline handling and g_nof_out=1 handling as in common_select_symbol
+ -- Purpose: Assign input to one of g_nof_out output streams based on out_sel input
+ -- Description: The output streams are concatenated into one SLV.
+ -- Remarks:
+ -- . Same scheme for pipeline handling and g_nof_out=1 handling as in common_select_symbol
entity common_demultiplexer is
generic (
@@ -35,7 +35,7 @@ entity common_demultiplexer is
g_pipeline_out : natural := 0;
g_nof_out : natural;
g_dat_w : natural
- );
+ );
port (
rst : in std_logic := '0';
clk : in std_logic := '0'; -- for g_pipeline_* = 0 no rst and clk are needed, because then the demultiplexer works combinatorialy
diff --git a/libraries/base/common/src/vhdl/common_duty_cycle.vhd b/libraries/base/common/src/vhdl/common_duty_cycle.vhd
index 8c09e6292f..c2afc0e71f 100644
--- a/libraries/base/common/src/vhdl/common_duty_cycle.vhd
+++ b/libraries/base/common/src/vhdl/common_duty_cycle.vhd
@@ -34,9 +34,9 @@
-- s_assert
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use WORK.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use WORK.common_pkg.all;
entity common_duty_cycle is
generic (
@@ -85,21 +85,21 @@ begin
case r.state is
when s_idle => v.state := s_idle;
- if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_act_cnt or dc_act_cnt = TO_UVEC(0, c_cycle_cnt_w) then
- v.state := s_deassert;
- elsif TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_per_cnt or dc_act_cnt = dc_per_cnt then
- v.state := s_assert;
- end if;
+ if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_act_cnt or dc_act_cnt = TO_UVEC(0, c_cycle_cnt_w) then
+ v.state := s_deassert;
+ elsif TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_per_cnt or dc_act_cnt = dc_per_cnt then
+ v.state := s_assert;
+ end if;
when s_assert => v.dc_pulse := g_act_lvl;
- if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_act_cnt and dc_act_cnt < dc_per_cnt then
- v.state := s_deassert;
- end if;
+ if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_act_cnt and dc_act_cnt < dc_per_cnt then
+ v.state := s_deassert;
+ end if;
when s_deassert => v.dc_pulse := not(g_act_lvl);
- if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_per_cnt and dc_act_cnt /= TO_UVEC(0, c_cycle_cnt_w) then
- v.state := s_assert;
- end if;
+ if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_per_cnt and dc_act_cnt /= TO_UVEC(0, c_cycle_cnt_w) then
+ v.state := s_assert;
+ end if;
end case;
if rst = '1' then
diff --git a/libraries/base/common/src/vhdl/common_evt.vhd b/libraries/base/common/src/vhdl/common_evt.vhd
index c4ad6d2bfd..210fd60fe4 100644
--- a/libraries/base/common/src/vhdl/common_evt.vhd
+++ b/libraries/base/common/src/vhdl/common_evt.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_evt is
generic (
diff --git a/libraries/base/common/src/vhdl/common_fanout.vhd b/libraries/base/common/src/vhdl/common_fanout.vhd
index 77143e1487..464f7c1db2 100644
--- a/libraries/base/common/src/vhdl/common_fanout.vhd
+++ b/libraries/base/common/src/vhdl/common_fanout.vhd
@@ -28,8 +28,8 @@
-- registers maintain their value.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_fanout is
generic (
@@ -53,42 +53,42 @@ architecture str of common_fanout is
begin
gen_fanout : for i in g_nof_output - 1 downto 0 generate
u_pipe_en : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(i)
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_en,
- in_en => '1',
- out_dat => out_en_vec(i)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(i)
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_en,
+ in_en => '1',
+ out_dat => out_en_vec(i)
+ );
u_pipe_valid : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(i)
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_val,
- in_en => in_en,
- out_dat => out_val_vec(i)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(i)
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_val,
+ in_en => in_en,
+ out_dat => out_val_vec(i)
+ );
u_pipe_data : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline_arr(i),
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- in_en => in_en,
- out_dat => out_dat_vec((i + 1) * g_dat_w - 1 downto i * g_dat_w)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(i),
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ in_en => in_en,
+ out_dat => out_dat_vec((i + 1) * g_dat_w - 1 downto i * g_dat_w)
+ );
end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_fanout_tree.vhd b/libraries/base/common/src/vhdl/common_fanout_tree.vhd
index d0dcc9ba25..7c51bc53ae 100644
--- a/libraries/base/common/src/vhdl/common_fanout_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_fanout_tree.vhd
@@ -20,62 +20,62 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
--- Purpose: Parallel fanout tree.
--- Description:
--- . Pipelined fanout of 1 input to g_nof_output.
--- . Suppose g_nof_output_per_cell=2 and g_nof_stages=3, so g_nof_output <=
--- g_nof_output_per_cell**g_nof_stages = c_nof_outputs = 8.
---
--- The pipeline fanout cell for g_nof_output_per_cell=2 is:
---
--- out
--- . 1 --> [1
--- in 0 --> 0]
---
--- The pipeline stage diagram for g_nof_stages=3 consists of 1+2+4=7 fanout
--- cells:
--- out
--- . . . 111 --> [7
--- 3 . . . 110 --> 6
--- . . . 101 --> 5
--- 2 . . . 100 --> 4
--- . . 11 011 --> 3
--- 1 . . 10 010 --> 2
--- . 1 01 001 --> 1
--- 0 in 0 00 000 --> 0]
--- cell i
--- stage j -1 0 1 2
---
--- The binary numbers at each stage indicate the fanout trajectory from input
--- to outputs. Stage -1 is the input data.
--- Internally define c_nof_outputs >= g_nof_output. Synthesis will optimise
--- away any unused outputs c_nof_outputs-1 DOWNTO g_nof_output.
---
--- The g_cell_pipeline_arr and g_cell_pipeline_factor_arr together define the
--- pipelining per cell as calculated by func_output_pipelining. In practise
--- this provides sufficient freedom and ease for defining the entire fanout
--- pipelining scheme.
---
--- Pipeline examples:
---
--- . Same number of pipeline cycles for all g_nof_output
--- g_cell_pipeline_factor_arr = (1, 1, 1)
--- g_cell_pipeline_arr = (1, 1)
--- . Same number of pipeline cycles for all g_nof_output, but with wires
--- so no pipelining at somes stages use:
--- g_cell_pipeline_factor_arr = (1, 0, 1)
--- g_cell_pipeline_arr = (1, 1)
--- . Pipelining the g_nof_output by g_nof_output-1:0 cycles:
--- g_cell_pipeline_factor_arr = (1, 2, 4)
--- g_cell_pipeline_arr = (1, 0)
---
--- Remarks:
--- . Alternatively a matrix g_pipeline_mat could be defined with dimensions
--- g_nof_stages * g_nof_outputs to have complete freedom for defining the
--- pipelining.
+ -- Purpose: Parallel fanout tree.
+ -- Description:
+ -- . Pipelined fanout of 1 input to g_nof_output.
+ -- . Suppose g_nof_output_per_cell=2 and g_nof_stages=3, so g_nof_output <=
+ -- g_nof_output_per_cell**g_nof_stages = c_nof_outputs = 8.
+ --
+ -- The pipeline fanout cell for g_nof_output_per_cell=2 is:
+ --
+ -- out
+ -- . 1 --> [1
+ -- in 0 --> 0]
+ --
+ -- The pipeline stage diagram for g_nof_stages=3 consists of 1+2+4=7 fanout
+ -- cells:
+ -- out
+ -- . . . 111 --> [7
+ -- 3 . . . 110 --> 6
+ -- . . . 101 --> 5
+ -- 2 . . . 100 --> 4
+ -- . . 11 011 --> 3
+ -- 1 . . 10 010 --> 2
+ -- . 1 01 001 --> 1
+ -- 0 in 0 00 000 --> 0]
+ -- cell i
+ -- stage j -1 0 1 2
+ --
+ -- The binary numbers at each stage indicate the fanout trajectory from input
+ -- to outputs. Stage -1 is the input data.
+ -- Internally define c_nof_outputs >= g_nof_output. Synthesis will optimise
+ -- away any unused outputs c_nof_outputs-1 DOWNTO g_nof_output.
+ --
+ -- The g_cell_pipeline_arr and g_cell_pipeline_factor_arr together define the
+ -- pipelining per cell as calculated by func_output_pipelining. In practise
+ -- this provides sufficient freedom and ease for defining the entire fanout
+ -- pipelining scheme.
+ --
+ -- Pipeline examples:
+ --
+ -- . Same number of pipeline cycles for all g_nof_output
+ -- g_cell_pipeline_factor_arr = (1, 1, 1)
+ -- g_cell_pipeline_arr = (1, 1)
+ -- . Same number of pipeline cycles for all g_nof_output, but with wires
+ -- so no pipelining at somes stages use:
+ -- g_cell_pipeline_factor_arr = (1, 0, 1)
+ -- g_cell_pipeline_arr = (1, 1)
+ -- . Pipelining the g_nof_output by g_nof_output-1:0 cycles:
+ -- g_cell_pipeline_factor_arr = (1, 2, 4)
+ -- g_cell_pipeline_arr = (1, 0)
+ --
+ -- Remarks:
+ -- . Alternatively a matrix g_pipeline_mat could be defined with dimensions
+ -- g_nof_stages * g_nof_outputs to have complete freedom for defining the
+ -- pipelining.
entity common_fanout_tree is
generic (
@@ -123,21 +123,21 @@ begin
gen_cell : for i in 0 to g_nof_output_per_cell**j - 1 generate
-- output k =
u_fanout : entity work.common_fanout
- generic map (
- g_nof_output => g_nof_output_per_cell,
- g_pipeline_arr => c_cell_pipeline_factor_arr(j) * c_cell_pipeline_arr,
- g_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_en => stage_en_vec_arr( j - 1)( i),
- in_val => stage_val_vec_arr(j - 1)( i),
- in_dat => stage_dat_vec_arr(j - 1)((i + 1) * g_dat_w - 1 downto i * g_dat_w),
- out_en_vec => stage_en_vec_arr( j)((i + 1) * g_nof_output_per_cell - 1 downto i * g_nof_output_per_cell),
- out_val_vec => stage_val_vec_arr(j)((i + 1) * g_nof_output_per_cell - 1 downto i * g_nof_output_per_cell),
- out_dat_vec => stage_dat_vec_arr(j)((i + 1) * g_nof_output_per_cell * g_dat_w - 1 downto i * g_nof_output_per_cell * g_dat_w)
- );
+ generic map (
+ g_nof_output => g_nof_output_per_cell,
+ g_pipeline_arr => c_cell_pipeline_factor_arr(j) * c_cell_pipeline_arr,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_en => stage_en_vec_arr( j - 1)( i),
+ in_val => stage_val_vec_arr(j - 1)( i),
+ in_dat => stage_dat_vec_arr(j - 1)((i + 1) * g_dat_w - 1 downto i * g_dat_w),
+ out_en_vec => stage_en_vec_arr( j)((i + 1) * g_nof_output_per_cell - 1 downto i * g_nof_output_per_cell),
+ out_val_vec => stage_val_vec_arr(j)((i + 1) * g_nof_output_per_cell - 1 downto i * g_nof_output_per_cell),
+ out_dat_vec => stage_dat_vec_arr(j)((i + 1) * g_nof_output_per_cell * g_dat_w - 1 downto i * g_nof_output_per_cell * g_dat_w)
+ );
end generate;
end generate;
@@ -148,21 +148,21 @@ begin
no_tree : if g_nof_output = 1 generate
u_reg : entity work.common_fanout
- generic map (
- g_nof_output => 1,
- g_pipeline_arr => c_cell_pipeline_factor_arr(0) * c_cell_pipeline_arr,
- g_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_en => in_en,
- in_val => in_val,
- in_dat => in_dat,
- out_en_vec => out_en_vec,
- out_val_vec => out_val_vec,
- out_dat_vec => out_dat_vec
- );
+ generic map (
+ g_nof_output => 1,
+ g_pipeline_arr => c_cell_pipeline_factor_arr(0) * c_cell_pipeline_arr,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_en => in_en,
+ in_val => in_val,
+ in_dat => in_dat,
+ out_en_vec => out_en_vec,
+ out_val_vec => out_val_vec,
+ out_dat_vec => out_dat_vec
+ );
end generate; -- no_tree
end str;
diff --git a/libraries/base/common/src/vhdl/common_field_pkg.vhd b/libraries/base/common/src/vhdl/common_field_pkg.vhd
index 7f3d90b4ee..a64786077d 100644
--- a/libraries/base/common/src/vhdl/common_field_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_field_pkg.vhd
@@ -20,24 +20,24 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_str_pkg.all;
-
--- Purpose:
--- . Dynamically map record-like field structures onto SLVs.
--- Description:
--- . The MM register is defined by mm_fields.vhd.
--- . The MM register consists of "RO" = input fields (status) and "RW" = output fields (control) in
--- arbitrary order. The entire register is kept in a word_arr slv. The functions can extract the
--- "RO" fields into a slv_in and the "RW" fields into a slv_out. Hence the slv_in'LENGTH +
--- slv_out'LENGTH = word_arr'LENGTH.
---
--- . Advantages:
--- . Replaces non-generic (dedicated) records;
--- . Field widths are variable
--- Remarks:
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_str_pkg.all;
+
+ -- Purpose:
+ -- . Dynamically map record-like field structures onto SLVs.
+ -- Description:
+ -- . The MM register is defined by mm_fields.vhd.
+ -- . The MM register consists of "RO" = input fields (status) and "RW" = output fields (control) in
+ -- arbitrary order. The entire register is kept in a word_arr slv. The functions can extract the
+ -- "RO" fields into a slv_in and the "RW" fields into a slv_out. Hence the slv_in'LENGTH +
+ -- slv_out'LENGTH = word_arr'LENGTH.
+ --
+ -- . Advantages:
+ -- . Replaces non-generic (dedicated) records;
+ -- . Field widths are variable
+ -- Remarks:
package common_field_pkg is
constant c_common_field_name_len : natural := 64;
@@ -111,7 +111,7 @@ package body common_field_pkg is
end field_map_defaults;
function field_mode(field_arr : t_common_field_arr; name: string) return string is
- -- Returns the mode string of the passed (via name) field
+ -- Returns the mode string of the passed (via name) field
begin
if field_exists(field_arr, name) then
for i in 0 to field_arr'high loop
@@ -125,7 +125,7 @@ package body common_field_pkg is
end field_mode;
function field_size(field_arr : t_common_field_arr; name: string) return natural is
- -- Returns the size of the passed (via name) field
+ -- Returns the size of the passed (via name) field
begin
for i in 0 to field_arr'high loop
if field_arr(i).name = field_name_pad(name) then
@@ -135,7 +135,7 @@ package body common_field_pkg is
end field_size;
function field_hi(field_arr : t_common_field_arr; name: string) return integer is
- -- Returns the high (=left) bit range index of the field within the field_arr interpreted as concatenated IN or OUT SLV
+ -- Returns the high (=left) bit range index of the field within the field_arr interpreted as concatenated IN or OUT SLV
variable v_acc_hi : natural := 0;
begin
if field_exists(field_arr, name) then
@@ -153,7 +153,7 @@ package body common_field_pkg is
end field_hi;
function field_hi(field_arr : t_common_field_arr; index : natural) return natural is
- -- Returns the high (=left) bit range index of the field within the field_arr interpreted as concatenated SLV
+ -- Returns the high (=left) bit range index of the field within the field_arr interpreted as concatenated SLV
variable v_acc_hi : natural := 0;
begin
for i in 0 to index loop
@@ -165,7 +165,7 @@ package body common_field_pkg is
end field_hi;
function field_lo(field_arr : t_common_field_arr; name: string) return natural is
- -- Returns the low (=right) bit range index of the field within the field_arr interpreted as concatenated IN or OUT SLV
+ -- Returns the low (=right) bit range index of the field within the field_arr interpreted as concatenated IN or OUT SLV
variable v_acc_hi : natural := 0;
begin
if field_exists(field_arr, name) then
@@ -183,7 +183,7 @@ package body common_field_pkg is
end field_lo;
function field_lo(field_arr : t_common_field_arr; index : natural) return natural is
- -- Returns the low (=right) bit range index of the field within the field_arr interpreted as concatenated SLV
+ -- Returns the low (=right) bit range index of the field within the field_arr interpreted as concatenated SLV
variable v_acc_hi : natural := 0;
begin
for i in 0 to index loop
@@ -195,7 +195,7 @@ package body common_field_pkg is
end field_lo;
function field_slv_len(field_arr : t_common_field_arr) return natural is
- -- Return the total length of all fields in field_arr
+ -- Return the total length of all fields in field_arr
variable v_len : natural := 0;
begin
for i in 0 to field_arr'high loop
@@ -205,7 +205,7 @@ package body common_field_pkg is
end field_slv_len;
function field_slv_in_len(field_arr : t_common_field_arr) return natural is
- -- Return the total length of the input fields in field_arr (= all "RO")
+ -- Return the total length of the input fields in field_arr (= all "RO")
variable v_len : natural := 0;
begin
for f in 0 to field_arr'high loop
@@ -217,7 +217,7 @@ package body common_field_pkg is
end field_slv_in_len;
function field_slv_out_len(field_arr : t_common_field_arr) return natural is
- -- Return the total length of the output fields in field_arr (= all "RW")
+ -- Return the total length of the output fields in field_arr (= all "RW")
variable v_len : natural := 0;
begin
for f in 0 to field_arr'high loop
@@ -229,7 +229,7 @@ package body common_field_pkg is
end field_slv_out_len;
function field_nof_words(field_arr : t_common_field_arr; word_w : natural) return natural is
- -- Return the number of words (of width word_w) required to hold field_arr
+ -- Return the number of words (of width word_w) required to hold field_arr
variable v_word_cnt : natural := 0;
variable v_nof_reg_words : natural;
begin
@@ -244,12 +244,12 @@ package body common_field_pkg is
end field_nof_words;
function field_map_in(field_arr : t_common_field_arr; slv: std_logic_vector; word_w : natural; mode : string) return std_logic_vector is
- -- Re-map a field SLV into a larger SLV, support mapping both the slv_in or the slv_out that dependents on mode; each field starting at a word boundary (word_w)
+ -- Re-map a field SLV into a larger SLV, support mapping both the slv_in or the slv_out that dependents on mode; each field starting at a word boundary (word_w)
variable v_word_arr : std_logic_vector(field_nof_words(field_arr, word_w) * word_w - 1 downto 0) := (others => '0');
variable v_word_cnt : natural := 0;
begin
for f in 0 to field_arr'high loop
- -- Only extract the fields that are inputs
+ -- Only extract the fields that are inputs
if field_arr(f).mode = mode then -- if mode="RO" then slv = slv_in, else if mode="RW" then slv = slv_out
-- Extract the field
v_word_arr( v_word_cnt * word_w + field_arr(f).size-1 downto v_word_cnt * word_w) := slv( field_hi(field_arr, field_arr(f).name) downto field_lo(field_arr, field_arr(f).name) );
@@ -261,7 +261,7 @@ package body common_field_pkg is
end field_map_in;
function field_map_out(field_arr : t_common_field_arr; word_arr: std_logic_vector; word_w : natural) return std_logic_vector is
- -- Reverse of field_map_in
+ -- Reverse of field_map_in
variable v_slv_out : std_logic_vector(field_slv_out_len(field_arr) - 1 downto 0) := (others => '0');
variable v_word_cnt : natural := 0;
begin
@@ -278,7 +278,7 @@ package body common_field_pkg is
end field_map_out;
function field_map(field_arr : t_common_field_arr; word_arr_in: std_logic_vector; word_arr_out: std_logic_vector; word_w : natural) return std_logic_vector is
- -- Create one SLV consisting of both read-only and output-readback fields, e.g. as input to an MM reg
+ -- Create one SLV consisting of both read-only and output-readback fields, e.g. as input to an MM reg
variable v_word_arr : std_logic_vector(field_nof_words(field_arr, word_w) * word_w - 1 downto 0);
variable v_word_cnt : natural := 0;
begin
@@ -296,7 +296,7 @@ package body common_field_pkg is
end field_map;
function field_ovr_arr(field_arr : t_common_field_arr; ovr_init: std_logic_vector) return t_common_field_arr is
- -- Copy field_arr but change widths to 1 to create a 1-bit override field for each field in field_arr.
+ -- Copy field_arr but change widths to 1 to create a 1-bit override field for each field in field_arr.
variable v_ovr_field_arr : t_common_field_arr(field_arr'range);
begin
v_ovr_field_arr := field_arr;
@@ -314,7 +314,7 @@ package body common_field_pkg is
return true;
end if;
end loop;
- return false;
+ return false;
end field_exists;
function field_arr_set_mode(field_arr : t_common_field_arr; mode : string) return t_common_field_arr is
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc.vhd b/libraries/base/common/src/vhdl/common_fifo_dc.vhd
index 08ad5365de..4eefe9c356 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc.vhd
@@ -22,9 +22,9 @@
-- Purpose: Dual clock FIFO
library IEEE, technology_lib, tech_fifo_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_fifo_dc is
generic (
@@ -73,27 +73,27 @@ begin
-- . synchronize release of rst to wr_clk domain
-- Using common_areset is equivalent to using common_async with same signal applied to rst and din.
u_wr_rst : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 3
- )
- port map (
- in_rst => rst,
- clk => wr_clk,
- out_rst => wr_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 3
+ )
+ port map (
+ in_rst => rst,
+ clk => wr_clk,
+ out_rst => wr_rst
+ );
-- Delay wr_init to ensure that FIFO ful has gone low after reset release
u_wr_init : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map (
- in_rst => wr_rst,
- clk => wr_clk,
- out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map (
+ in_rst => wr_rst,
+ clk => wr_clk,
+ out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
+ );
wr_init_out <= wr_init;
@@ -115,24 +115,24 @@ begin
end process;
u_fifo : entity tech_fifo_lib.tech_fifo_dc
- generic map (
- g_technology => g_technology,
- g_dat_w => g_dat_w,
- g_nof_words => c_nof_words
- )
- port map (
- aclr => wr_rst, -- MegaWizard fifo_dc seems to use aclr synchronous with wr_clk
- data => wr_dat,
- rdclk => rd_clk,
- rdreq => rd_en,
- wrclk => wr_clk,
- wrreq => wr_en,
- q => rd_dat,
- rdempty => emp,
- rdusedw => rdusedw,
- wrfull => ful,
- wrusedw => wrusedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_dat_w => g_dat_w,
+ g_nof_words => c_nof_words
+ )
+ port map (
+ aclr => wr_rst, -- MegaWizard fifo_dc seems to use aclr synchronous with wr_clk
+ data => wr_dat,
+ rdclk => rd_clk,
+ rdreq => rd_en,
+ wrclk => wr_clk,
+ wrreq => wr_en,
+ q => rd_dat,
+ rdempty => emp,
+ rdusedw => rdusedw,
+ wrfull => ful,
+ wrusedw => wrusedw
+ );
proc_common_fifo_asserts("common_fifo_dc", g_note_is_ful, g_fail_rd_emp, wr_rst, wr_clk, ful, wr_en, rd_clk, emp, rd_en);
end str;
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd b/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
index f94b9e1054..d113bfe60c 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
@@ -20,62 +20,62 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-
--- Purpose: Control the FIFO fill level and report the dual clock lock status
--- Description:
--- When the FIFO has been filled in state s_detect_wr_clk then wr_clk_rst goes
--- high, because then the input write clock to the FIFO is active. The
--- wr_clk_rst pulse is then issued to reset the phase of the FIFO wr_clk.
--- This assumes that the FIFO wr_clk comes from an external clock divider
--- that divides a higher rate sample clock.
--- The dual clock FIFO is held in reset by means of the g_hold_dc_fifo_rst
--- timeout in state s_reset_fifo until it is sure that the wr_clk has
--- restarted again. After that the c_fifo_latency timeout in state
--- s_init_fifo is used to ensure that the FIFO filling must have started
--- after that dc_fifo_rst was released.
--- When the dual clock FIFO has been filled again in state s_fill_fifo then
--- the wr_clk and the rd_clk are assumed to be in lock and the state becomes
--- s_fill_level. In state s_fill_level the c_fifo_latency timeout is used
--- to wait until the rd_usedw is stable. The rd_usedw still increments a few
--- because the FIFO has some latency between applying rd_req and rd_usedw
--- reacting on that in case rd_usedw is derived from wr_usedw directly. The
--- actual FIFO fill level is then registered in fill_level and used in the
--- state s_dc_locked.
--- If the dual clocks of the dual clock (dc) fifo are in lock in then the
--- rd_usedw will remain constant +-g_rd_fill_margin, because then the
--- FIFO wr_clk and FIFO rd_clk have the same rate but can have a different
--- phase. Default g_rd_fill_margin = 0.
--- If rd_usedw goes below fill_level-0 then the FIFO wr_clk has stopped or
--- is slower than the FIFO rd_clk. If the rd_usedw goes above fill_level+0
--- then the FIFO wr_clk is faster than the FIFO rd_clk. Both these cases
--- indicate that the wr_clk and rd_clk lost lock.
--- The +- g_rd_fill_margin can be used to cope with phase jitter on the
--- clocks, but typically it should be 0 for systems that have a stable phase
--- relation between the wr_clk and the rd_clk, also after each powerup.
--- The control tries to recover from the loss of lock between the wr_clk and
--- the rd_clk by resetting the FIFO and letting it fill again to the
--- g_rd_fill_level in the state s_detect_wr_clk.
--- The dual clock lock status is indicated by dc_locked, when '1' then the
---- wr_clk and rd_clk are currently in lock. Whether one or multiple losses
--- of dc lock occured is reported via dc_stable. The dc_stable is '1' when
---- the dc_locked is '1' and has not gone low (i.e. no loss of lock occured)
--- since the last time that dc_stable was acknowledged via dc_stable_ack.
--- Hence by pulsing dc_stable_ack the user can start a new fresh period for
--- dc_stable.
--- Remarks:
--- . See tb_lvdsh_dd for a test bench that uses common_fifo_dc_lock_control
--- . Use the FIFO rd_clk clock domain to clock this common_fifo_dc_lock_control
--- . Best use a FIFO of at least size 16 and a fill level of 4, >= 3 to have
--- margin from empty at the read side and <= 8 (= 16 - 8 = 8), to have margin
--- from full at the write side.
--- . Increase g_rd_fill_level to have more time between wr_clk_rst going high
--- and dc_locked going high.
--- . The rd_fill_level can also be set via MM control to support different a
--- fill level per signal path, e.g. to compensate for cable length
--- differences between these signal paths in units of the rd_clk period.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+
+ -- Purpose: Control the FIFO fill level and report the dual clock lock status
+ -- Description:
+ -- When the FIFO has been filled in state s_detect_wr_clk then wr_clk_rst goes
+ -- high, because then the input write clock to the FIFO is active. The
+ -- wr_clk_rst pulse is then issued to reset the phase of the FIFO wr_clk.
+ -- This assumes that the FIFO wr_clk comes from an external clock divider
+ -- that divides a higher rate sample clock.
+ -- The dual clock FIFO is held in reset by means of the g_hold_dc_fifo_rst
+ -- timeout in state s_reset_fifo until it is sure that the wr_clk has
+ -- restarted again. After that the c_fifo_latency timeout in state
+ -- s_init_fifo is used to ensure that the FIFO filling must have started
+ -- after that dc_fifo_rst was released.
+ -- When the dual clock FIFO has been filled again in state s_fill_fifo then
+ -- the wr_clk and the rd_clk are assumed to be in lock and the state becomes
+ -- s_fill_level. In state s_fill_level the c_fifo_latency timeout is used
+ -- to wait until the rd_usedw is stable. The rd_usedw still increments a few
+ -- because the FIFO has some latency between applying rd_req and rd_usedw
+ -- reacting on that in case rd_usedw is derived from wr_usedw directly. The
+ -- actual FIFO fill level is then registered in fill_level and used in the
+ -- state s_dc_locked.
+ -- If the dual clocks of the dual clock (dc) fifo are in lock in then the
+ -- rd_usedw will remain constant +-g_rd_fill_margin, because then the
+ -- FIFO wr_clk and FIFO rd_clk have the same rate but can have a different
+ -- phase. Default g_rd_fill_margin = 0.
+ -- If rd_usedw goes below fill_level-0 then the FIFO wr_clk has stopped or
+ -- is slower than the FIFO rd_clk. If the rd_usedw goes above fill_level+0
+ -- then the FIFO wr_clk is faster than the FIFO rd_clk. Both these cases
+ -- indicate that the wr_clk and rd_clk lost lock.
+ -- The +- g_rd_fill_margin can be used to cope with phase jitter on the
+ -- clocks, but typically it should be 0 for systems that have a stable phase
+ -- relation between the wr_clk and the rd_clk, also after each powerup.
+ -- The control tries to recover from the loss of lock between the wr_clk and
+ -- the rd_clk by resetting the FIFO and letting it fill again to the
+ -- g_rd_fill_level in the state s_detect_wr_clk.
+ -- The dual clock lock status is indicated by dc_locked, when '1' then the
+ --- wr_clk and rd_clk are currently in lock. Whether one or multiple losses
+ -- of dc lock occured is reported via dc_stable. The dc_stable is '1' when
+ --- the dc_locked is '1' and has not gone low (i.e. no loss of lock occured)
+ -- since the last time that dc_stable was acknowledged via dc_stable_ack.
+ -- Hence by pulsing dc_stable_ack the user can start a new fresh period for
+ -- dc_stable.
+ -- Remarks:
+ -- . See tb_lvdsh_dd for a test bench that uses common_fifo_dc_lock_control
+ -- . Use the FIFO rd_clk clock domain to clock this common_fifo_dc_lock_control
+ -- . Best use a FIFO of at least size 16 and a fill level of 4, >= 3 to have
+ -- margin from empty at the read side and <= 8 (= 16 - 8 = 8), to have margin
+ -- from full at the write side.
+ -- . Increase g_rd_fill_level to have more time between wr_clk_rst going high
+ -- and dc_locked going high.
+ -- . The rd_fill_level can also be set via MM control to support different a
+ -- fill level per signal path, e.g. to compensate for cable length
+ -- differences between these signal paths in units of the rd_clk period.
entity common_fifo_dc_lock_control is
generic (
@@ -225,24 +225,24 @@ begin
end process;
u_cnt : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_w
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => c_cnt_w
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
u_dc_locked_monitor : entity work.common_stable_monitor
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- MM
- r_in => i_dc_locked,
- r_stable => dc_stable,
- r_stable_ack => dc_stable_ack
- );
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- MM
+ r_in => i_dc_locked,
+ r_stable => dc_stable,
+ r_stable_ack => dc_stable_ack
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd b/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
index 32aaf05a36..cd36c17434 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
@@ -41,9 +41,9 @@
-- been written to the FIFO the rdusedw will wrap and the output goes wrong.
library IEEE, technology_lib, tech_fifo_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_fifo_dc_mixed_widths is
generic (
@@ -92,27 +92,27 @@ begin
-- . synchronize release of rst to wr_clk domain
-- Using common_areset is equivalent to using common_async with same signal applied to rst and din.
u_wr_rst : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 3
- )
- port map (
- in_rst => rst,
- clk => wr_clk,
- out_rst => wr_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 3
+ )
+ port map (
+ in_rst => rst,
+ clk => wr_clk,
+ out_rst => wr_rst
+ );
-- Delay wr_init to ensure that FIFO ful has gone low after reset release
u_wr_init : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map (
- in_rst => wr_rst,
- clk => wr_clk,
- out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map (
+ in_rst => wr_rst,
+ clk => wr_clk,
+ out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
+ );
-- The FIFO under read and over write protection are kept enabled in the MegaWizard
wr_en <= wr_req and not wr_init; -- check on NOT ful is not necessary according to fifo_generator_ug175.pdf
@@ -131,25 +131,25 @@ begin
end process;
u_fifo : entity tech_fifo_lib.tech_fifo_dc_mixed_widths
- generic map (
- g_technology => g_technology,
- g_nof_words => c_nof_words,
- g_wrdat_w => g_wr_dat_w,
- g_rddat_w => g_rd_dat_w
- )
- port map (
- aclr => wr_rst, -- MegaWizard fifo_dc_mixed_widths seems to use aclr synchronous with wr_clk
- data => wr_dat,
- rdclk => rd_clk,
- rdreq => rd_en,
- wrclk => wr_clk,
- wrreq => wr_en,
- q => rd_dat,
- rdempty => emp,
- rdusedw => rdusedw,
- wrfull => ful,
- wrusedw => wrusedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_words => c_nof_words,
+ g_wrdat_w => g_wr_dat_w,
+ g_rddat_w => g_rd_dat_w
+ )
+ port map (
+ aclr => wr_rst, -- MegaWizard fifo_dc_mixed_widths seems to use aclr synchronous with wr_clk
+ data => wr_dat,
+ rdclk => rd_clk,
+ rdreq => rd_en,
+ wrclk => wr_clk,
+ wrreq => wr_en,
+ q => rd_dat,
+ rdempty => emp,
+ rdusedw => rdusedw,
+ wrfull => ful,
+ wrusedw => wrusedw
+ );
proc_common_fifo_asserts("common_fifo_dc_mixed_widths", g_note_is_ful, g_fail_rd_emp, wr_rst, wr_clk, ful, wr_en, rd_clk, emp, rd_en);
end str;
diff --git a/libraries/base/common/src/vhdl/common_fifo_rd.vhd b/libraries/base/common/src/vhdl/common_fifo_rd.vhd
index 25ec1cdeeb..cbb29da6b1 100644
--- a/libraries/base/common/src/vhdl/common_fifo_rd.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_rd.vhd
@@ -21,16 +21,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
--- Purpose: Adapt from ready latency 1 to 0 to make a look ahead FIFO
--- Description: -
--- Remark:
--- . Derived from dp_latency_adapter.vhd.
--- . There is no need for a rd_emp output signal, because a show ahead FIFO
--- will have rd_val='0' when it is empty.
+ -- Purpose: Adapt from ready latency 1 to 0 to make a look ahead FIFO
+ -- Description: -
+ -- Remark:
+ -- . Derived from dp_latency_adapter.vhd.
+ -- . There is no need for a rd_emp output signal, because a show ahead FIFO
+ -- will have rd_val='0' when it is empty.
entity common_fifo_rd is
generic (
@@ -53,20 +53,20 @@ end common_fifo_rd;
architecture wrap of common_fifo_rd is
begin
u_rl0 : entity work.common_rl_decrease
- generic map (
- g_adapt => true,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink: RL = 1
- snk_out_ready => fifo_req,
- snk_in_dat => fifo_dat,
- snk_in_val => fifo_val,
- -- ST source: RL = 0
- src_in_ready => rd_req,
- src_out_dat => rd_dat,
- src_out_val => rd_val
- );
+ generic map (
+ g_adapt => true,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink: RL = 1
+ snk_out_ready => fifo_req,
+ snk_in_dat => fifo_dat,
+ snk_in_val => fifo_val,
+ -- ST source: RL = 0
+ src_in_ready => rd_req,
+ src_out_dat => rd_dat,
+ src_out_val => rd_val
+ );
end wrap;
diff --git a/libraries/base/common/src/vhdl/common_fifo_sc.vhd b/libraries/base/common/src/vhdl/common_fifo_sc.vhd
index 302f5c2225..55f89923ba 100644
--- a/libraries/base/common/src/vhdl/common_fifo_sc.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_sc.vhd
@@ -22,9 +22,9 @@
-- Purpose: Single clock FIFO
library IEEE, technology_lib, tech_fifo_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_fifo_sc is
generic (
@@ -32,8 +32,8 @@ entity common_fifo_sc is
g_note_is_ful : boolean := true; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_fail_rd_emp : boolean := false; -- when TRUE report FAILURE when read from an empty FIFO
g_use_lut : boolean := false; -- when TRUE then force using LUTs via Altera eab="OFF",
- -- else use default eab="ON" and ram_block_type="AUTO", default ram_block_type="AUTO" is sufficient, because
- -- there seems no need to force using RAM and there are two types of Stratix IV RAM (M9K and M144K)
+ -- else use default eab="ON" and ram_block_type="AUTO", default ram_block_type="AUTO" is sufficient, because
+ -- there seems no need to force using RAM and there are two types of Stratix IV RAM (M9K and M144K)
g_reset : boolean := false; -- when TRUE release FIFO reset some cycles after rst release, else use rst directly
g_init : boolean := false; -- when TRUE force wr_req inactive for some cycles after FIFO reset release, else use wr_req as is
g_dat_w : natural := 36; -- 36 * 256 = 1 M9K
@@ -81,15 +81,15 @@ begin
-- Make sure the reset lasts at least 3 cycles (see fifo_generator_ug175.pdf). This is necessary in case
-- the FIFO reset is also used functionally to flush it, so not only after power up.
u_fifo_rst : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map (
- in_rst => rst,
- clk => clk,
- out_rst => fifo_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map (
+ in_rst => rst,
+ clk => clk,
+ out_rst => fifo_rst
+ );
end generate;
no_fifo_rst : if g_reset = false generate
@@ -99,15 +99,15 @@ begin
gen_init : if g_init = true generate
-- Wait at least 3 cycles after reset release before allowing fifo_wr_en (see fifo_generator_ug175.pdf)
u_fifo_init : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map (
- in_rst => fifo_rst,
- clk => clk,
- out_rst => fifo_init
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map (
+ in_rst => fifo_rst,
+ clk => clk,
+ out_rst => fifo_init
+ );
p_init_reg : process(fifo_rst, clk)
begin
@@ -152,23 +152,23 @@ begin
-- 0 < some threshold < usedw < g_nof_words can be used as FIFO almost_full
-- 0 < usedw < some threshold < g_nof_words can be used as FIFO almost_empty
u_fifo : entity tech_fifo_lib.tech_fifo_sc
- generic map (
- g_technology => g_technology,
- g_use_eab => c_use_eab,
- g_dat_w => g_dat_w,
- g_nof_words => g_nof_words
- )
- port map (
- aclr => fifo_rst,
- clock => clk,
- data => fifo_wr_dat,
- rdreq => fifo_rd_en,
- wrreq => fifo_wr_en,
- empty => fifo_empty,
- full => fifo_full,
- q => rd_dat,
- usedw => fifo_usedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_use_eab => c_use_eab,
+ g_dat_w => g_dat_w,
+ g_nof_words => g_nof_words
+ )
+ port map (
+ aclr => fifo_rst,
+ clock => clk,
+ data => fifo_wr_dat,
+ rdreq => fifo_rd_en,
+ wrreq => fifo_wr_en,
+ empty => fifo_empty,
+ full => fifo_full,
+ q => rd_dat,
+ usedw => fifo_usedw
+ );
proc_common_fifo_asserts("common_fifo_sc", g_note_is_ful, g_fail_rd_emp, fifo_rst, clk, fifo_full, fifo_wr_en, clk, fifo_empty, fifo_rd_en);
end str;
diff --git a/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd b/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
index 9eeeeaf25c..fb438d1e5d 100644
--- a/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
+++ b/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
@@ -21,7 +21,7 @@
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_flank_to_pulse is
port (
@@ -35,7 +35,7 @@ end common_flank_to_pulse;
architecture str of common_flank_to_pulse is
signal flank_in_dly : std_logic;
begin
- p_in_dly : process(rst, clk)
+ p_in_dly : process(rst, clk)
begin
if rst = '1' then
flank_in_dly <= '0';
diff --git a/libraries/base/common/src/vhdl/common_frame_busy.vhd b/libraries/base/common/src/vhdl/common_frame_busy.vhd
index 6357f11447..94443c87e5 100644
--- a/libraries/base/common/src/vhdl/common_frame_busy.vhd
+++ b/libraries/base/common/src/vhdl/common_frame_busy.vhd
@@ -20,14 +20,14 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
--- Purpose: Determine when there is an active frame
--- Description:
--- . The frame_busy goes high combinatorially with the in_sop and low after the
--- in_eop.
--- . The frame_idle = NOT frame_busy.
--- Remark:
+ -- Purpose: Determine when there is an active frame
+ -- Description:
+ -- . The frame_busy goes high combinatorially with the in_sop and low after the
+ -- in_eop.
+ -- . The frame_idle = NOT frame_busy.
+ -- Remark:
entity common_frame_busy is
port (
diff --git a/libraries/base/common/src/vhdl/common_init.vhd b/libraries/base/common/src/vhdl/common_init.vhd
index 0dbfdf1c99..ddbbbd82a9 100644
--- a/libraries/base/common/src/vhdl/common_init.vhd
+++ b/libraries/base/common/src/vhdl/common_init.vhd
@@ -20,24 +20,24 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
--- Purpose:
---
--- 1) The hold can be used as a synchronous reset for the rest of the logic.
--- The difference with common_areset is that common_init uses a counter
--- whereas common_areset uses a shift register to set the hold time for the
--- hold. Hence with common_init it is possible to define very long reset
--- hold times with minimal logic.
--- 2) The init can be used to ensure that all subsequent logic starts
--- at the same clock cycle. Due to no constraint on rst timing, the rst
--- signal could be released 1 or even 2 cycles earlier for one register in
--- the FPGA than for another register. The init pulse can be used to start
--- the init action, when rst has been released for all registers in the
--- whole FPGA for sure.
---
--- Remarks:
--- . In LOFAR only init was used
+ -- Purpose:
+ --
+ -- 1) The hold can be used as a synchronous reset for the rest of the logic.
+ -- The difference with common_areset is that common_init uses a counter
+ -- whereas common_areset uses a shift register to set the hold time for the
+ -- hold. Hence with common_init it is possible to define very long reset
+ -- hold times with minimal logic.
+ -- 2) The init can be used to ensure that all subsequent logic starts
+ -- at the same clock cycle. Due to no constraint on rst timing, the rst
+ -- signal could be released 1 or even 2 cycles earlier for one register in
+ -- the FPGA than for another register. The init pulse can be used to start
+ -- the init action, when rst has been released for all registers in the
+ -- whole FPGA for sure.
+ --
+ -- Remarks:
+ -- . In LOFAR only init was used
entity common_init is
generic (
@@ -83,14 +83,14 @@ begin
nxt_init_reg <= '1' when cnt_en = '0' and prev_cnt_en = '1' else '0';
u_counter : entity common_lib.common_counter
- generic map (
- g_width => g_latency_w + 1
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => '0',
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => g_latency_w + 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => '0',
+ cnt_en => cnt_en,
+ count => cnt
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_inout.vhd b/libraries/base/common/src/vhdl/common_inout.vhd
index ba4efdbf26..70979eb433 100644
--- a/libraries/base/common/src/vhdl/common_inout.vhd
+++ b/libraries/base/common/src/vhdl/common_inout.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
--- Tristate buffer
+ -- Tristate buffer
entity common_inout is
port (
diff --git a/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd b/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
index 42890418c2..c900b52a32 100644
--- a/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use IEEE.numeric_std.all;
package common_interface_layers_pkg is
------------------------------------------------------------------------------
@@ -61,7 +61,7 @@ package common_interface_layers_pkg is
type t_xgmii_dc_arr is array(integer range <>) of std_logic_vector(c_xgmii_w - 1 downto 0);
type t_xgmii_d_arr is array(integer range <>) of std_logic_vector(c_xgmii_data_w - 1 downto 0);
type t_xgmii_c_arr is array(integer range <>) of std_logic_vector(c_xgmii_nof_lanes - 1 downto 0);
- end common_interface_layers_pkg;
+end common_interface_layers_pkg;
package body common_interface_layers_pkg is
-- Refer to the 10GBASE-R PHY IP Core section of the Altera Transceiver PHY IP Core User Guide
diff --git a/libraries/base/common/src/vhdl/common_interleave.vhd b/libraries/base/common/src/vhdl/common_interleave.vhd
index 11645c0f29..4bc4fde3c0 100644
--- a/libraries/base/common/src/vhdl/common_interleave.vhd
+++ b/libraries/base/common/src/vhdl/common_interleave.vhd
@@ -20,27 +20,27 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-
--- Purpose: Interleave g_nof_in inputs into one output stream based on g_block_size.
--- Description:
--- The input streams are concatenated into one SLV. The incoming streams are
--- sequentially multiplexed onto the output, starting from input 0. During
--- multiplexing of the current input, the other input(s) are buffered and
--- will be put on the output after g_block_size valid words on the current
--- input.
--- Remarks:
--- . One valid input applies to all input data streams;
--- . The user must take care of the correct valid/gap ratio on the inputs.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+
+ -- Purpose: Interleave g_nof_in inputs into one output stream based on g_block_size.
+ -- Description:
+ -- The input streams are concatenated into one SLV. The incoming streams are
+ -- sequentially multiplexed onto the output, starting from input 0. During
+ -- multiplexing of the current input, the other input(s) are buffered and
+ -- will be put on the output after g_block_size valid words on the current
+ -- input.
+ -- Remarks:
+ -- . One valid input applies to all input data streams;
+ -- . The user must take care of the correct valid/gap ratio on the inputs.
entity common_interleave is
generic (
g_nof_in : natural; -- >= 2
g_dat_w : natural;
g_block_size : natural
- );
+ );
port (
clk : in std_logic;
rst : in std_logic;
@@ -112,46 +112,46 @@ begin
-----------------------------------------------------------------------------
gen_blockregs: for i in 0 to g_nof_in - 1 generate
u_blockreg : entity work.common_blockreg
- generic map (
- g_block_size => g_block_size,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => bkr_in_dat_arr(i),
- in_val => in_val,
-
- out_dat => bkr_out_dat_arr(i),
- out_val => bkr_out_val_arr(i)
+ generic map (
+ g_block_size => g_block_size,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => bkr_in_dat_arr(i),
+ in_val => in_val,
+
+ out_dat => bkr_out_dat_arr(i),
+ out_val => bkr_out_val_arr(i)
);
u_dat_block_offset_pipe : entity work.common_pipeline
- generic map (
- g_pipeline => i * g_block_size,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => bkr_out_dat_arr(i),
- out_dat => piped_bkr_out_dat_arr(i)
- );
+ generic map (
+ g_pipeline => i * g_block_size,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => bkr_out_dat_arr(i),
+ out_dat => piped_bkr_out_dat_arr(i)
+ );
u_val_block_offset_pipe : entity work.common_pipeline
- generic map (
- g_pipeline => i * g_block_size,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => slv(bkr_out_val_arr(i)),
- sl(out_dat) => piped_bkr_out_val_arr(i)
- );
+ generic map (
+ g_pipeline => i * g_block_size,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => slv(bkr_out_val_arr(i)),
+ sl(out_dat) => piped_bkr_out_val_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -165,21 +165,21 @@ begin
-- The multiplexer
-----------------------------------------------------------------------------
u_mux : entity work.common_multiplexer
- generic map (
- g_nof_in => g_nof_in,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_sel => mux_in_sel,
- in_dat => mux_in_concat_dat_arr,
- in_val => mux_in_val,
-
- out_dat => out_dat,
- out_val => out_val
- );
+ generic map (
+ g_nof_in => g_nof_in,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_sel => mux_in_sel,
+ in_dat => mux_in_concat_dat_arr,
+ in_val => mux_in_val,
+
+ out_dat => out_dat,
+ out_val => out_val
+ );
-----------------------------------------------------------------------------
-- Multiplexer input selection
diff --git a/libraries/base/common/src/vhdl/common_interval_monitor.vhd b/libraries/base/common/src/vhdl/common_interval_monitor.vhd
index 0056a8bce9..ff86616c79 100644
--- a/libraries/base/common/src/vhdl/common_interval_monitor.vhd
+++ b/libraries/base/common/src/vhdl/common_interval_monitor.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
--- Purpose: Monitor the nof valid clock cycles between two in_evt pulses
--- Description:
--- The in_evt pulses define the interval. Leave in_val not connected to count
--- every clock cycle.
--- Remarks:
+ -- Purpose: Monitor the nof valid clock cycles between two in_evt pulses
+ -- Description:
+ -- The in_evt pulses define the interval. Leave in_val not connected to count
+ -- every clock cycle.
+ -- Remarks:
entity common_interval_monitor is
generic (
diff --git a/libraries/base/common/src/vhdl/common_iobuf_in.vhd b/libraries/base/common/src/vhdl/common_iobuf_in.vhd
index 688910ed0d..7cde91658e 100644
--- a/libraries/base/common/src/vhdl/common_iobuf_in.vhd
+++ b/libraries/base/common/src/vhdl/common_iobuf_in.vhd
@@ -22,8 +22,8 @@
-- Purpose: Delay differential FPGA input
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity common_iobuf_in is
generic(
diff --git a/libraries/base/common/src/vhdl/common_led_controller.vhd b/libraries/base/common/src/vhdl/common_led_controller.vhd
index b0d2adbb0e..2a1651f864 100644
--- a/libraries/base/common/src/vhdl/common_led_controller.vhd
+++ b/libraries/base/common/src/vhdl/common_led_controller.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose: Provide visual activity information via a LED.
--- Description:
--- ctrl_on = '0' : then led = ctrl_input, so completely driven by external control
--- ctrl_on = '1' : then led = '1' but pulses '0' for g_nof_ms each time that a ctrl_evt clk pulse occurs
--- Remark:
--- The p_state machine ensures that after g_nof_ms off the led also stays on
--- for at least g_nof_ms, to avoid that a too fast ctrl_evt rate would cause
--- the led too stay off. Therefore the maximum event rate that can be
--- signalled is 1/(2*g_nof_ms). If events occur faster then these can not be
--- visualized exactly anymore and will get lost.
+ -- Purpose: Provide visual activity information via a LED.
+ -- Description:
+ -- ctrl_on = '0' : then led = ctrl_input, so completely driven by external control
+ -- ctrl_on = '1' : then led = '1' but pulses '0' for g_nof_ms each time that a ctrl_evt clk pulse occurs
+ -- Remark:
+ -- The p_state machine ensures that after g_nof_ms off the led also stays on
+ -- for at least g_nof_ms, to avoid that a too fast ctrl_evt rate would cause
+ -- the led too stay off. Therefore the maximum event rate that can be
+ -- signalled is 1/(2*g_nof_ms). If events occur faster then these can not be
+ -- visualized exactly anymore and will get lost.
entity common_led_controller is
generic (
diff --git a/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd b/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
index 3f11c037e9..aa4769b5b1 100644
--- a/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
@@ -30,9 +30,9 @@
-- . Based on Xilinx application note xapp052.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_lfsr_sequences_pkg is
constant c_common_lfsr_max_nof_feedbacks : natural := 6;
@@ -51,89 +51,91 @@ package common_lfsr_sequences_pkg is
-- (0,0,0,0, 2, 1) yields repeat <0, 1, 2>
-- XNOR feedbacks from outputs for n = 3 .. 72 from Xilinx xapp052.pdf (that lists feedbacks for in total 168 sequences)
- constant c_common_lfsr_sequences : t_SEQUENCES := ((0,0,0,0,0, 1), -- 1 : <0, 1>
- (0,0,0,0, 0, 2), -- 2 : <0, 1, 3, 2>
- (0,0,0,0, 3, 2), -- 3
- (0,0,0,0, 4, 3), -- 4
- (0,0,0,0, 5, 3), -- 5
- (0,0,0,0, 6, 5), -- 6
- (0,0,0,0, 7, 6), -- 7
- (0,0, 8, 6, 5, 4), -- 8
- (0,0,0,0, 9, 5), -- 9
- (0,0,0,0, 10, 7), -- 10
- (0,0,0,0, 11, 9), -- 11
- (0,0, 12, 6, 4, 1), -- 12
- (0,0, 13, 4, 3, 1), -- 13
- (0,0, 14, 5, 3, 1), -- 14
- (0,0,0,0, 15,14 ), -- 15
- (0,0, 16,15,13, 4), -- 16
- (0,0,0,0, 17,14 ), -- 17
- (0,0,0,0, 18,11 ), -- 18
- (0,0, 19, 6, 2, 1), -- 19
- (0,0,0,0, 20,17 ), -- 20
- (0,0,0,0, 21,19 ), -- 21
- (0,0,0,0, 22,21 ), -- 22
- (0,0,0,0, 23,18 ), -- 23
- (0,0, 24,23,22,17), -- 24
- (0,0,0,0, 25,22 ), -- 25
- (0,0, 26, 6, 2, 1), -- 26
- (0,0, 27, 5, 2, 1), -- 27
- (0,0,0,0, 28,25 ), -- 28
- (0,0,0,0, 29,27 ), -- 29
- (0,0, 30, 6, 4, 1), -- 30
- (0,0,0,0, 31,28 ), -- 31
- (0,0, 32,22, 2, 1), -- 32
- (0,0,0,0, 33,20 ), -- 33
- (0,0, 34,27, 2, 1), -- 34
- (0,0,0,0, 35,33 ), -- 35
- (0,0,0,0, 36,25 ), -- 36
- ( 37, 5, 4, 3, 2, 1), -- 37
- (0,0, 38, 6, 5, 1), -- 38
- (0,0,0,0, 39,35 ), -- 39
- (0,0, 40,38,21,19), -- 40
- (0,0,0,0, 41,38 ), -- 41
- (0,0, 42,41,20,19), -- 42
- (0,0, 43,42,38,37), -- 43
- (0,0, 44,43,18,17), -- 44
- (0,0, 45,44,42,41), -- 45
- (0,0, 46,45,26,25), -- 46
- (0,0,0,0, 47,42 ), -- 47
- (0,0, 48,47,21,20), -- 48
- (0,0,0,0, 49,40 ), -- 49
- (0,0, 50,49,24,23), -- 50
- (0,0, 51,50,36,35), -- 51
- (0,0,0,0, 52,49 ), -- 52
- (0,0, 53,52,38,37), -- 53
- (0,0, 54,53,18,17), -- 54
- (0,0,0,0, 55,31 ), -- 55
- (0,0, 56,55,35,34), -- 56
- (0,0,0,0, 57,50 ), -- 57
- (0,0,0,0, 58,39 ), -- 58
- (0,0, 59,58,38,37), -- 59
- (0,0,0,0, 60,59 ), -- 60
- (0,0, 61,60,46,45), -- 61
- (0,0, 62,61, 6, 5), -- 62
- (0,0,0,0, 63,62 ), -- 63
- (0,0, 64,63,61,60), -- 64
- (0,0,0,0, 65,47 ), -- 65
- (0,0, 66,65,57,56), -- 66
- (0,0, 67,66,58,57), -- 67
- (0,0,0,0, 68,59 ), -- 68
- (0,0, 69,67,42,40), -- 69
- (0,0, 70,69,55,54), -- 70
- (0,0,0,0, 71,65 ), -- 71
- (0,0, 72,66,25,19)); -- 72
+ constant c_common_lfsr_sequences : t_SEQUENCES := (
+ (0,0,0,0,0, 1), -- 1 : <0, 1>
+ (0,0,0,0, 0, 2), -- 2 : <0, 1, 3, 2>
+ (0,0,0,0, 3, 2), -- 3
+ (0,0,0,0, 4, 3), -- 4
+ (0,0,0,0, 5, 3), -- 5
+ (0,0,0,0, 6, 5), -- 6
+ (0,0,0,0, 7, 6), -- 7
+ (0,0, 8, 6, 5, 4), -- 8
+ (0,0,0,0, 9, 5), -- 9
+ (0,0,0,0, 10, 7), -- 10
+ (0,0,0,0, 11, 9), -- 11
+ (0,0, 12, 6, 4, 1), -- 12
+ (0,0, 13, 4, 3, 1), -- 13
+ (0,0, 14, 5, 3, 1), -- 14
+ (0,0,0,0, 15,14 ), -- 15
+ (0,0, 16,15,13, 4), -- 16
+ (0,0,0,0, 17,14 ), -- 17
+ (0,0,0,0, 18,11 ), -- 18
+ (0,0, 19, 6, 2, 1), -- 19
+ (0,0,0,0, 20,17 ), -- 20
+ (0,0,0,0, 21,19 ), -- 21
+ (0,0,0,0, 22,21 ), -- 22
+ (0,0,0,0, 23,18 ), -- 23
+ (0,0, 24,23,22,17), -- 24
+ (0,0,0,0, 25,22 ), -- 25
+ (0,0, 26, 6, 2, 1), -- 26
+ (0,0, 27, 5, 2, 1), -- 27
+ (0,0,0,0, 28,25 ), -- 28
+ (0,0,0,0, 29,27 ), -- 29
+ (0,0, 30, 6, 4, 1), -- 30
+ (0,0,0,0, 31,28 ), -- 31
+ (0,0, 32,22, 2, 1), -- 32
+ (0,0,0,0, 33,20 ), -- 33
+ (0,0, 34,27, 2, 1), -- 34
+ (0,0,0,0, 35,33 ), -- 35
+ (0,0,0,0, 36,25 ), -- 36
+ ( 37, 5, 4, 3, 2, 1), -- 37
+ (0,0, 38, 6, 5, 1), -- 38
+ (0,0,0,0, 39,35 ), -- 39
+ (0,0, 40,38,21,19), -- 40
+ (0,0,0,0, 41,38 ), -- 41
+ (0,0, 42,41,20,19), -- 42
+ (0,0, 43,42,38,37), -- 43
+ (0,0, 44,43,18,17), -- 44
+ (0,0, 45,44,42,41), -- 45
+ (0,0, 46,45,26,25), -- 46
+ (0,0,0,0, 47,42 ), -- 47
+ (0,0, 48,47,21,20), -- 48
+ (0,0,0,0, 49,40 ), -- 49
+ (0,0, 50,49,24,23), -- 50
+ (0,0, 51,50,36,35), -- 51
+ (0,0,0,0, 52,49 ), -- 52
+ (0,0, 53,52,38,37), -- 53
+ (0,0, 54,53,18,17), -- 54
+ (0,0,0,0, 55,31 ), -- 55
+ (0,0, 56,55,35,34), -- 56
+ (0,0,0,0, 57,50 ), -- 57
+ (0,0,0,0, 58,39 ), -- 58
+ (0,0, 59,58,38,37), -- 59
+ (0,0,0,0, 60,59 ), -- 60
+ (0,0, 61,60,46,45), -- 61
+ (0,0, 62,61, 6, 5), -- 62
+ (0,0,0,0, 63,62 ), -- 63
+ (0,0, 64,63,61,60), -- 64
+ (0,0,0,0, 65,47 ), -- 65
+ (0,0, 66,65,57,56), -- 66
+ (0,0, 67,66,58,57), -- 67
+ (0,0,0,0, 68,59 ), -- 68
+ (0,0, 69,67,42,40), -- 69
+ (0,0, 70,69,55,54), -- 70
+ (0,0,0,0, 71,65 ), -- 71
+ (0,0, 72,66,25,19)); -- 72
-- Procedure for calculating the next PSRG and COUNTER sequence value
- procedure common_lfsr_nxt_seq(constant c_lfsr_nr : in natural;
- constant g_incr : in integer;
- in_en : in std_logic;
- in_req : in std_logic;
- in_dat : in std_logic_vector;
- prsg : in std_logic_vector;
- cntr : in std_logic_vector;
- signal nxt_prsg : out std_logic_vector;
- signal nxt_cntr : out std_logic_vector);
+ procedure common_lfsr_nxt_seq(
+ constant c_lfsr_nr : in natural;
+ constant g_incr : in integer;
+ in_en : in std_logic;
+ in_req : in std_logic;
+ in_dat : in std_logic_vector;
+ prsg : in std_logic_vector;
+ cntr : in std_logic_vector;
+ signal nxt_prsg : out std_logic_vector;
+ signal nxt_cntr : out std_logic_vector);
-- Use lfsr part of common_lfsr_nxt_seq to make a random bit generator function
-- . width of lfsr selects the LFSR sequence
@@ -143,15 +145,16 @@ package common_lfsr_sequences_pkg is
end common_lfsr_sequences_pkg;
package body common_lfsr_sequences_pkg is
- procedure common_lfsr_nxt_seq(constant c_lfsr_nr : in natural;
- constant g_incr : in integer;
- in_en : in std_logic;
- in_req : in std_logic;
- in_dat : in std_logic_vector;
- prsg : in std_logic_vector;
- cntr : in std_logic_vector;
- signal nxt_prsg : out std_logic_vector;
- signal nxt_cntr : out std_logic_vector) is
+ procedure common_lfsr_nxt_seq(
+ constant c_lfsr_nr : in natural;
+ constant g_incr : in integer;
+ in_en : in std_logic;
+ in_req : in std_logic;
+ in_dat : in std_logic_vector;
+ prsg : in std_logic_vector;
+ cntr : in std_logic_vector;
+ signal nxt_prsg : out std_logic_vector;
+ signal nxt_cntr : out std_logic_vector) is
variable v_feedback : std_logic;
begin
nxt_prsg <= prsg;
diff --git a/libraries/base/common/src/vhdl/common_math_pkg.vhd b/libraries/base/common/src/vhdl/common_math_pkg.vhd
index 2dfec614b7..232c258a5b 100644
--- a/libraries/base/common/src/vhdl/common_math_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_math_pkg.vhd
@@ -32,10 +32,10 @@
-- is reduced to within the [0:2pi> range inside SIN() or COS().
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.math_real.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.math_real.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
package common_math_pkg is
-- Function to create the cos/sin lookup table with amplitude, frequency and phase
diff --git a/libraries/base/common/src/vhdl/common_mem_demux.vhd b/libraries/base/common/src/vhdl/common_mem_demux.vhd
index 2669234188..9e5725231c 100644
--- a/libraries/base/common/src/vhdl/common_mem_demux.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_demux.vhd
@@ -50,9 +50,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity common_mem_demux is
generic (
diff --git a/libraries/base/common/src/vhdl/common_mem_mux.vhd b/libraries/base/common/src/vhdl/common_mem_mux.vhd
index 17b494471e..15e944a96d 100644
--- a/libraries/base/common/src/vhdl/common_mem_mux.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_mux.vhd
@@ -57,9 +57,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity common_mem_mux is
generic (
diff --git a/libraries/base/common/src/vhdl/common_mem_pkg.vhd b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
index 9f035bdfd4..781d2e13c3 100644
--- a/libraries/base/common/src/vhdl/common_mem_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
@@ -48,9 +48,9 @@
-- sufficient widths.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_mem_pkg is
-- Choose smallest maximum slv lengths that fit all use cases, because unconstrained record fields slv is not allowed
@@ -118,16 +118,19 @@ package common_mem_pkg is
-- check and wait for mm_copi.waitrequest = '0' before removing the MM
-- access.
------------------------------------------------------------------------------
- procedure proc_mem_bus_wr(constant wr_addr : in natural;
- constant wr_data : in integer;
- signal mm_copi : out t_mem_copi);
+ procedure proc_mem_bus_wr(
+ constant wr_addr : in natural;
+ constant wr_data : in integer;
+ signal mm_copi : out t_mem_copi);
- procedure proc_mem_bus_wr(constant wr_addr : in natural;
- constant wr_data : in std_logic_vector;
- signal mm_copi : out t_mem_copi);
+ procedure proc_mem_bus_wr(
+ constant wr_addr : in natural;
+ constant wr_data : in std_logic_vector;
+ signal mm_copi : out t_mem_copi);
- procedure proc_mem_bus_rd(constant wr_addr : in natural;
- signal mm_copi : out t_mem_copi);
+ procedure proc_mem_bus_rd(
+ constant wr_addr : in natural;
+ signal mm_copi : out t_mem_copi);
------------------------------------------------------------------------------
-- Burst memory access (for DDR access interface)
@@ -296,26 +299,29 @@ package body common_mem_pkg is
end RESIZE_MEM_XDATA;
-- Procedures to access MM bus
- procedure proc_mem_bus_wr(constant wr_addr : in natural;
- constant wr_data : in integer;
- signal mm_copi : out t_mem_copi) is
+ procedure proc_mem_bus_wr(
+ constant wr_addr : in natural;
+ constant wr_data : in integer;
+ signal mm_copi : out t_mem_copi) is
begin
mm_copi.address <= TO_MEM_ADDRESS(wr_addr);
mm_copi.wrdata <= TO_MEM_DATA(wr_data);
mm_copi.wr <= '1';
end proc_mem_bus_wr;
- procedure proc_mem_bus_wr(constant wr_addr : in natural;
- constant wr_data : in std_logic_vector;
- signal mm_copi : out t_mem_copi) is
+ procedure proc_mem_bus_wr(
+ constant wr_addr : in natural;
+ constant wr_data : in std_logic_vector;
+ signal mm_copi : out t_mem_copi) is
begin
mm_copi.address <= TO_MEM_ADDRESS(wr_addr);
mm_copi.wrdata <= RESIZE_MEM_DATA(wr_data);
mm_copi.wr <= '1';
end proc_mem_bus_wr;
- procedure proc_mem_bus_rd(constant wr_addr : in natural;
- signal mm_copi : out t_mem_copi) is
+ procedure proc_mem_bus_rd(
+ constant wr_addr : in natural;
+ signal mm_copi : out t_mem_copi) is
begin
mm_copi.address <= TO_MEM_ADDRESS(wr_addr);
mm_copi.rd <= '1';
diff --git a/libraries/base/common/src/vhdl/common_multiplexer.vhd b/libraries/base/common/src/vhdl/common_multiplexer.vhd
index b93832dae0..193d6e3abe 100644
--- a/libraries/base/common/src/vhdl/common_multiplexer.vhd
+++ b/libraries/base/common/src/vhdl/common_multiplexer.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
--- Purpose: Assign one of g_nof_in input streams to the output based on in_sel input
--- Description: The input streams are concatenated into one SLV.
--- Remarks:
+ -- Purpose: Assign one of g_nof_in input streams to the output based on in_sel input
+ -- Description: The input streams are concatenated into one SLV.
+ -- Remarks:
entity common_multiplexer is
generic (
@@ -33,7 +33,7 @@ entity common_multiplexer is
g_pipeline_out : natural := 0;
g_nof_in : natural;
g_dat_w : natural
- );
+ );
port (
clk : in std_logic;
rst : in std_logic;
@@ -50,23 +50,23 @@ end;
architecture str of common_multiplexer is
begin
u_select_symbol : entity work.common_select_symbol
- generic map (
- g_pipeline_in => g_pipeline_in,
- g_pipeline_out => g_pipeline_out,
- g_nof_symbols => g_nof_in,
- g_symbol_w => g_dat_w,
- g_sel_w => ceil_log2(g_nof_in)
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_out => g_pipeline_out,
+ g_nof_symbols => g_nof_in,
+ g_symbol_w => g_dat_w,
+ g_sel_w => ceil_log2(g_nof_in)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_data => in_dat,
- in_val => in_val,
+ in_data => in_dat,
+ in_val => in_val,
- in_sel => in_sel,
+ in_sel => in_sel,
- out_symbol => out_dat,
- out_val => out_val
- );
+ out_symbol => out_dat,
+ out_val => out_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd b/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
index 904b55d3df..2439c0a409 100644
--- a/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
@@ -23,10 +23,10 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_field_pkg.all;
package common_network_layers_pkg is
-- All *_len constants are in nof octets = nof bytes = c_8 bits
@@ -90,9 +90,10 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001");
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -139,223 +140,227 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
- constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
- c_network_ip_identification_len + c_network_ip_flags_fragment_len +
- c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
- c_network_ip_addr_len +
- c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
- -- default field values
- constant c_network_ip_version : natural := 4; -- 4 = IPv4,
- constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
- constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
- constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
- constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
- constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
- constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
- constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
- constant c_network_ip_header_checksum : natural := 0; -- init value
-
- -- useful field values
- constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
- constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
- constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
-
- constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
-
- type t_network_ip_header is record
- version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
- header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
- services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
- total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
- identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
- flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
- fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
- time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
- protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
- header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
- src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- end record;
-
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
-
- ------------------------------------------------------------------------------
- -- ARP Packet
- --
- -- 0 7 8 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Hardware Type | Protocol Type | 4
- -- |----------------------------------------------------------------------|
- -- | HW Addr Len | Prot Addr Len | Operation | 5
- -- |----------------------------------------------------------------------|
- -- | Sender Hardware Address | 6
- -- | ------------------------------------|
- -- | | | 7
- -- |---------------------------------/ /----------------------------------|
- -- | Sender Protocol Address | | 8
- -- |----------------------------------- |
- -- | Target Hardware Address | 9
- -- |----------------------------------------------------------------------|
- -- | Target Protocol Address | 10
- -- |----------------------------------------------------------------------|
- --
- -- Note that ARP header = ARP packet, because ARP has no payload
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_arp_htype_len : natural := 2;
- constant c_network_arp_htype_w : natural := c_network_arp_htype_len * c_8;
- constant c_network_arp_ptype_len : natural := 2;
- constant c_network_arp_ptype_w : natural := c_network_arp_ptype_len * c_8;
- constant c_network_arp_hlen_len : natural := 1;
- constant c_network_arp_hlen_w : natural := c_network_arp_hlen_len * c_8;
- constant c_network_arp_plen_len : natural := 1;
- constant c_network_arp_plen_w : natural := c_network_arp_plen_len * c_8;
- constant c_network_arp_oper_len : natural := 2;
- constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
-
- -- [0:15] [16:31]
- constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
- c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-
- -- default field values
- constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
- constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
- constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
- constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
- constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
- constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
-
- -- useful field values
- constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
- constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
-
- type t_network_arp_packet is record
- htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
- ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
- hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
- plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
- oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
- sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
- spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
- tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
- tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
- end record;
-
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
-
- ------------------------------------------------------------------------------
- -- ICMP (for ping)
- --
- -- 0 7 8 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Type | Code | Checksum | 9
- -- |----------------------------------------------------------------------|
- -- | ID | Sequence | 10
- -- |----------------------------------------------------------------------|
- -- | |
- -- | ICMP Payload (padding data) |
- -- | |
- -- |------------------------------------------------------------ // ------|
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_icmp_msg_type_len : natural := 1;
- constant c_network_icmp_msg_type_w : natural := c_network_icmp_msg_type_len * c_8;
- constant c_network_icmp_code_len : natural := 1;
- constant c_network_icmp_code_w : natural := c_network_icmp_code_len * c_8;
- constant c_network_icmp_checksum_len : natural := 2;
- constant c_network_icmp_checksum_w : natural := c_network_icmp_checksum_len * c_8;
- constant c_network_icmp_id_len : natural := 2;
- constant c_network_icmp_id_w : natural := c_network_icmp_id_len * c_8;
- constant c_network_icmp_sequence_len : natural := 2;
- constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
- constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
- c_network_icmp_id_len + c_network_icmp_sequence_len;
-
- -- default field values
- constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
- constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
- constant c_network_icmp_checksum : natural := 0; -- init value
-
- -- useful field values
- constant c_network_icmp_code : natural := 0; -- default
- constant c_network_icmp_id : natural := 3; -- arbitrary value
- constant c_network_icmp_sequence : natural := 4; -- arbitrary value
-
- type t_network_icmp_header is record
- msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
- code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
- checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
- id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
- sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
- end record;
-
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
-
- ------------------------------------------------------------------------------
- -- UDP Packet
- --
- -- 0 15 16 31 wi
- -- |----------------------------------------------------------------------|
- -- | Source Port | Destination Port | 9
- -- |----------------------------------------------------------------------|
- -- | Total Length | Checksum | 10
- -- |----------------------------------------------------------------------|
- -- | |
- -- | UDP Payload |
- -- | |
- -- |----------------------------------------------------------- // -------|
- --
-
- -- field widths in bits '_w' or in bytes '_len'
- constant c_network_udp_port_len : natural := 2;
- constant c_network_udp_port_w : natural := c_network_udp_port_len * c_8;
- constant c_network_udp_total_length_len : natural := 2;
- constant c_network_udp_total_length_w : natural := c_network_udp_total_length_len * c_8;
- constant c_network_udp_checksum_len : natural := 2;
- constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
-
- -- [0:15] [16:31]
- constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
-
- -- default field values
- constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
- constant c_network_udp_checksum : natural := 0; -- init value
-
- -- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
-
- constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
- constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
- constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
-
- type t_network_udp_header is record
- src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
- checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
- end record;
-
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
-
- function func_network_ip_header_checksum(field_arr : t_common_field_arr; hdr_fields_slv : std_logic_vector) return std_logic_vector;
+ -- [0:7] [8:15] [16:31]
+ constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
+ c_network_ip_identification_len + c_network_ip_flags_fragment_len +
+ c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
+ c_network_ip_addr_len +
+ c_network_ip_addr_len;
+ -- = c_network_ip_header_length * c_word_sz = 20
+ -- default field values
+ constant c_network_ip_version : natural := 4; -- 4 = IPv4,
+ constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
+ constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
+ constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
+ constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
+ constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
+ constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
+ constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
+ constant c_network_ip_header_checksum : natural := 0; -- init value
+
+ -- useful field values
+ constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
+ constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
+ constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
+
+ constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
+
+ type t_network_ip_header is record
+ version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
+ header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
+ services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
+ total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
+ identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
+ flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
+ fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
+ time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
+ protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
+ header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
+ src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ end record;
+
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001", "0001", "00000001", "0000000000000001",
+ "0000000000000001", "001", "0000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- ARP Packet
+ --
+ -- 0 7 8 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Hardware Type | Protocol Type | 4
+ -- |----------------------------------------------------------------------|
+ -- | HW Addr Len | Prot Addr Len | Operation | 5
+ -- |----------------------------------------------------------------------|
+ -- | Sender Hardware Address | 6
+ -- | ------------------------------------|
+ -- | | | 7
+ -- |---------------------------------/ /----------------------------------|
+ -- | Sender Protocol Address | | 8
+ -- |----------------------------------- |
+ -- | Target Hardware Address | 9
+ -- |----------------------------------------------------------------------|
+ -- | Target Protocol Address | 10
+ -- |----------------------------------------------------------------------|
+ --
+ -- Note that ARP header = ARP packet, because ARP has no payload
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_arp_htype_len : natural := 2;
+ constant c_network_arp_htype_w : natural := c_network_arp_htype_len * c_8;
+ constant c_network_arp_ptype_len : natural := 2;
+ constant c_network_arp_ptype_w : natural := c_network_arp_ptype_len * c_8;
+ constant c_network_arp_hlen_len : natural := 1;
+ constant c_network_arp_hlen_w : natural := c_network_arp_hlen_len * c_8;
+ constant c_network_arp_plen_len : natural := 1;
+ constant c_network_arp_plen_w : natural := c_network_arp_plen_len * c_8;
+ constant c_network_arp_oper_len : natural := 2;
+ constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
+
+ -- [0:15] [16:31]
+ constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
+ c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len;
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+
+ -- default field values
+ constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
+ constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
+ constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
+ constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
+ constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
+ constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
+
+ -- useful field values
+ constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
+ constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
+
+ type t_network_arp_packet is record
+ htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
+ ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
+ hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
+ plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
+ oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
+ sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
+ spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
+ tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
+ tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
+ end record;
+
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001", "0000000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- ICMP (for ping)
+ --
+ -- 0 7 8 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Type | Code | Checksum | 9
+ -- |----------------------------------------------------------------------|
+ -- | ID | Sequence | 10
+ -- |----------------------------------------------------------------------|
+ -- | |
+ -- | ICMP Payload (padding data) |
+ -- | |
+ -- |------------------------------------------------------------ // ------|
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_icmp_msg_type_len : natural := 1;
+ constant c_network_icmp_msg_type_w : natural := c_network_icmp_msg_type_len * c_8;
+ constant c_network_icmp_code_len : natural := 1;
+ constant c_network_icmp_code_w : natural := c_network_icmp_code_len * c_8;
+ constant c_network_icmp_checksum_len : natural := 2;
+ constant c_network_icmp_checksum_w : natural := c_network_icmp_checksum_len * c_8;
+ constant c_network_icmp_id_len : natural := 2;
+ constant c_network_icmp_id_w : natural := c_network_icmp_id_len * c_8;
+ constant c_network_icmp_sequence_len : natural := 2;
+ constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
+ constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
+ c_network_icmp_id_len + c_network_icmp_sequence_len;
+
+ -- default field values
+ constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
+ constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
+ constant c_network_icmp_checksum : natural := 0; -- init value
+
+ -- useful field values
+ constant c_network_icmp_code : natural := 0; -- default
+ constant c_network_icmp_id : natural := 3; -- arbitrary value
+ constant c_network_icmp_sequence : natural := 4; -- arbitrary value
+
+ type t_network_icmp_header is record
+ msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
+ code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
+ checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
+ id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
+ sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
+ end record;
+
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001", "00000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
+
+ ------------------------------------------------------------------------------
+ -- UDP Packet
+ --
+ -- 0 15 16 31 wi
+ -- |----------------------------------------------------------------------|
+ -- | Source Port | Destination Port | 9
+ -- |----------------------------------------------------------------------|
+ -- | Total Length | Checksum | 10
+ -- |----------------------------------------------------------------------|
+ -- | |
+ -- | UDP Payload |
+ -- | |
+ -- |----------------------------------------------------------- // -------|
+ --
+
+ -- field widths in bits '_w' or in bytes '_len'
+ constant c_network_udp_port_len : natural := 2;
+ constant c_network_udp_port_w : natural := c_network_udp_port_len * c_8;
+ constant c_network_udp_total_length_len : natural := 2;
+ constant c_network_udp_total_length_w : natural := c_network_udp_total_length_len * c_8;
+ constant c_network_udp_checksum_len : natural := 2;
+ constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
+
+ -- [0:15] [16:31]
+ constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
+ c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+
+ -- default field values
+ constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
+ constant c_network_udp_checksum : natural := 0; -- init value
+
+ -- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
+
+ constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
+ constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
+ constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
+
+ type t_network_udp_header is record
+ src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
+ dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
+ total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
+ checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
+ end record;
+
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
+
+ function func_network_ip_header_checksum(field_arr : t_common_field_arr; hdr_fields_slv : std_logic_vector) return std_logic_vector;
end common_network_layers_pkg;
@@ -371,8 +376,8 @@ package body common_network_layers_pkg is
begin
-- vec = whole ip header excluding ip_header_checksum.
vec :=
- hdr_fields_slv(field_hi(field_arr, "ip_version" ) downto field_lo(field_arr, "ip_protocol" ))
- & hdr_fields_slv(field_hi(field_arr, "ip_src_addr" ) downto field_lo(field_arr, "ip_dst_addr" ));
+ hdr_fields_slv(field_hi(field_arr, "ip_version" ) downto field_lo(field_arr, "ip_protocol" ))
+ & hdr_fields_slv(field_hi(field_arr, "ip_src_addr" ) downto field_lo(field_arr, "ip_dst_addr" ));
-- sum up vec in halfwords
for i in 0 to c_nof_halfword - 1 loop
diff --git a/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd b/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
index 32587a2aff..d7e85eabe7 100644
--- a/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
@@ -50,10 +50,10 @@
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_network_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_network_layers_pkg.all;
package common_network_total_header_pkg is
-- Define total network header that fits all relevant packets in common_network_layers_pkg, because they have the same total header length
@@ -75,11 +75,12 @@ package common_network_total_header_pkg is
udp : t_network_udp_header;
end record;
- constant c_network_total_header_ones : t_network_total_header := (c_network_eth_header_ones,
- c_network_arp_packet_ones,
- c_network_ip_header_ones,
- c_network_icmp_header_ones,
- c_network_udp_header_ones);
+ constant c_network_total_header_ones : t_network_total_header := (
+ c_network_eth_header_ones,
+ c_network_arp_packet_ones,
+ c_network_ip_header_ones,
+ c_network_icmp_header_ones,
+ c_network_udp_header_ones);
-----------------------------------------------------------------------------
-- Map total network header in words array
@@ -249,12 +250,14 @@ package common_network_total_header_pkg is
-- Construct the response total header array for a total header array
function func_network_total_header_response_eth( eth_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
function func_network_total_header_response_eth( eth_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
- function func_network_total_header_response_arp( arp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
- return t_network_total_header_32b_arr;
- function func_network_total_header_response_arp( arp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
- return t_network_total_header_64b_arr;
+ function func_network_total_header_response_arp(
+ arp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
+ return t_network_total_header_32b_arr;
+ function func_network_total_header_response_arp(
+ arp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
+ return t_network_total_header_64b_arr;
function func_network_total_header_response_ip( ip_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
function func_network_total_header_response_ip( ip_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
function func_network_total_header_response_icmp(icmp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
@@ -265,12 +268,14 @@ package common_network_total_header_pkg is
-- Construct the response total header array for a total header array without alignment bytes
function func_network_total_header_no_align_response_eth( eth_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
function func_network_total_header_no_align_response_eth( eth_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
- function func_network_total_header_no_align_response_arp( arp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
- return t_network_total_header_32b_arr;
- function func_network_total_header_no_align_response_arp( arp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
- return t_network_total_header_64b_arr;
+ function func_network_total_header_no_align_response_arp(
+ arp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
+ return t_network_total_header_32b_arr;
+ function func_network_total_header_no_align_response_arp(
+ arp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
+ return t_network_total_header_64b_arr;
function func_network_total_header_no_align_response_ip( ip_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
function func_network_total_header_no_align_response_ip( ip_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
function func_network_total_header_no_align_response_icmp(icmp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
@@ -717,8 +722,9 @@ package body common_network_total_header_pkg is
end;
-- Construct the response headers
- function func_network_total_header_response_eth(eth_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_eth(
+ eth_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- Default
@@ -733,8 +739,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_eth(eth_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_eth(
+ eth_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- Default
@@ -749,9 +756,10 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_arp(arp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_arp(
+ arp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH
@@ -773,9 +781,10 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_arp(arp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_arp(
+ arp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH
@@ -796,8 +805,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_ip(ip_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_ip(
+ ip_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH
@@ -811,8 +821,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_ip(ip_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_ip(
+ ip_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH
@@ -826,8 +837,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_icmp(icmp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_icmp(
+ icmp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH, IP
@@ -839,8 +851,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_icmp(icmp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_icmp(
+ icmp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH, IP
@@ -852,8 +865,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_udp(udp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_udp(
+ udp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH, IP
@@ -865,8 +879,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_udp(udp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_udp(
+ udp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH, IP
@@ -879,8 +894,9 @@ package body common_network_total_header_pkg is
end;
-- Construct the response headers for headers without word align padding
- function func_network_total_header_no_align_response_eth(eth_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_eth(
+ eth_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- Default
@@ -895,8 +911,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_eth(eth_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_eth(
+ eth_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- Default
@@ -910,9 +927,10 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_arp(arp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_arp(
+ arp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH
@@ -934,9 +952,10 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_arp(arp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_arp(
+ arp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH
@@ -957,8 +976,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_ip(ip_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_ip(
+ ip_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH
@@ -974,8 +994,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_ip(ip_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_ip(
+ ip_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH
@@ -990,8 +1011,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_icmp(icmp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_icmp(
+ icmp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH, IP
@@ -1003,8 +1025,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_icmp(icmp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_icmp(
+ icmp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH, IP
@@ -1016,8 +1039,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_udp(udp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_udp(
+ udp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH, IP
@@ -1029,8 +1053,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_udp(udp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_udp(
+ udp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH, IP
diff --git a/libraries/base/common/src/vhdl/common_operation.vhd b/libraries/base/common/src/vhdl/common_operation.vhd
index d807bdcd3f..fb9d795812 100644
--- a/libraries/base/common/src/vhdl/common_operation.vhd
+++ b/libraries/base/common/src/vhdl/common_operation.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity common_operation is
generic (
@@ -103,16 +103,16 @@ begin
nxt_result <= func_operation(g_operation, g_representation, a, b);
u_output_pipe : entity work.common_pipeline -- pipeline output
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline_output, -- 0 for wires, >0 for register stages
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => nxt_result,
- out_dat => result
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline_output, -- 0 for wires, >0 for register stages
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => nxt_result,
+ out_dat => result
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_operation_tree.vhd b/libraries/base/common/src/vhdl/common_operation_tree.vhd
index 0ad7a72e6a..155294fd75 100644
--- a/libraries/base/common/src/vhdl/common_operation_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_operation_tree.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
--- Purpose: Parallel operation tree.
--- Description:
--- . Perform the operation on g_nof_inputs from an input vector in_data_vec.
--- Remarks:
--- . The implementation follows the same scheme as common_adder_tree_a_str
--- . Instead of using common_pipeline in case g_nof_inputs is not a power of 2
--- it would have been easier to internally extend the input in_data_vec to a
--- power of 2 using default input values for the unused inputs or by
--- setting in_en_vec fixed to '0' for them. Synthesis will then optimise them
--- away.
--- . More operations can be added e.g.:
--- - Operation "ADD" to provide same as common_adder_tree.vhd, but with more
--- control over the stage pipelining thanks to g_pipeline_mod
--- - Operation "SEL" with in_sel input to provide same as
--- common_select_symbol.vhd but with pipelining per stage instead of only
--- at the output
+ -- Purpose: Parallel operation tree.
+ -- Description:
+ -- . Perform the operation on g_nof_inputs from an input vector in_data_vec.
+ -- Remarks:
+ -- . The implementation follows the same scheme as common_adder_tree_a_str
+ -- . Instead of using common_pipeline in case g_nof_inputs is not a power of 2
+ -- it would have been easier to internally extend the input in_data_vec to a
+ -- power of 2 using default input values for the unused inputs or by
+ -- setting in_en_vec fixed to '0' for them. Synthesis will then optimise them
+ -- away.
+ -- . More operations can be added e.g.:
+ -- - Operation "ADD" to provide same as common_adder_tree.vhd, but with more
+ -- control over the stage pipelining thanks to g_pipeline_mod
+ -- - Operation "SEL" with in_sel input to provide same as
+ -- common_select_symbol.vhd but with pipelining per stage instead of only
+ -- at the output
entity common_operation_tree is
generic (
@@ -83,22 +83,22 @@ begin
gen_stage : for j in 0 to c_nof_stages - 1 generate
gen_oper : for i in 0 to (c_N + (2**j) - 1) / (2**(j + 1)) - 1 generate
u_operj : entity work.common_operation
- generic map (
- g_operation => g_operation,
- g_representation => g_representation,
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => sel_a_b((j + 1) mod g_pipeline_mod = 0, c_pipeline_out, 0),
- g_dat_w => c_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => stage_arr(j - 1)((2 * i + 1) * c_w - 1 downto (2 * i + 0) * c_w),
- in_b => stage_arr(j - 1)((2 * i + 2) * c_w - 1 downto (2 * i + 1) * c_w),
- in_en_a => sl(stage_en_arr(j - 1)(2 * i downto 2 * i )),
- in_en_b => sl(stage_en_arr(j - 1)(2 * i + 1 downto 2 * i + 1)),
- result => stage_arr(j)((i + 1) * c_w - 1 downto i * c_w)
- );
+ generic map (
+ g_operation => g_operation,
+ g_representation => g_representation,
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => sel_a_b((j + 1) mod g_pipeline_mod = 0, c_pipeline_out, 0),
+ g_dat_w => c_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => stage_arr(j - 1)((2 * i + 1) * c_w - 1 downto (2 * i + 0) * c_w),
+ in_b => stage_arr(j - 1)((2 * i + 2) * c_w - 1 downto (2 * i + 1) * c_w),
+ in_en_a => sl(stage_en_arr(j - 1)(2 * i downto 2 * i )),
+ in_en_b => sl(stage_en_arr(j - 1)(2 * i + 1 downto 2 * i + 1)),
+ result => stage_arr(j)((i + 1) * c_w - 1 downto i * c_w)
+ );
-- In case two adjacent inputs are disbaled, the result of their operation should be disabled in the next stage as well.
-- Therfor a logic OR creates the stage_en vector for the next stage.
@@ -111,20 +111,20 @@ begin
stage_en_arr(j)(c_N / (2**(j + 1))) <= in_en_vec(g_nof_inputs - 1);
u_pipej : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => sel_a_b((j + 1) mod g_pipeline_mod = 0, c_pipeline_out, 0),
- g_in_dat_w => c_w,
- g_out_dat_w => c_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => stage_arr(j - 1)((2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 1) * c_w - 1 downto
- (2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 0) * c_w),
- out_dat => stage_arr(j)(((c_N + (2**j) - 1) / (2**(j + 1)) + 1) * c_w - 1 downto
- ((c_N + (2**j) - 1) / (2**(j + 1)) ) * c_w)
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => sel_a_b((j + 1) mod g_pipeline_mod = 0, c_pipeline_out, 0),
+ g_in_dat_w => c_w,
+ g_out_dat_w => c_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => stage_arr(j - 1)((2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 1) * c_w - 1 downto
+ (2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 0) * c_w),
+ out_dat => stage_arr(j)(((c_N + (2**j) - 1) / (2**(j + 1)) + 1) * c_w - 1 downto
+ ((c_N + (2**j) - 1) / (2**(j + 1)) ) * c_w)
+ );
end generate;
end generate;
@@ -133,18 +133,18 @@ begin
no_tree : if g_nof_inputs = 1 generate
u_reg : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_data_vec,
- out_dat => result
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_data_vec,
+ out_dat => result
+ );
end generate; -- no_tree
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
index 4bc889b7fe..5540d3b90e 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
@@ -35,12 +35,12 @@
-- . The "use_adr" variant is optimal for speed, so that is set as default.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_crw_crw is
generic (
@@ -84,11 +84,12 @@ architecture rtl of common_paged_ram_crw_crw is
constant c_page_addr_w : natural := ceil_log2(g_page_sz);
-- g_str = "use_mux" :
- constant c_page_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_page_addr_w,
- dat_w => g_data_w,
- nof_dat => g_page_sz,
- init_sl => '0');
+ constant c_page_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_page_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_page_sz,
+ init_sl => '0');
type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
@@ -97,21 +98,23 @@ architecture rtl of common_paged_ram_crw_crw is
constant c_mem_addr_w : natural := c_mem_nof_pages_w + c_page_addr_w;
constant c_mem_nof_words : natural := g_nof_pages * 2**c_page_addr_w; -- <= 2**c_mem_addr_w
- constant c_mem_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_mem_addr_w,
- dat_w => g_data_w,
- nof_dat => c_mem_nof_words,
- init_sl => '0');
+ constant c_mem_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_mem_addr_w,
+ dat_w => g_data_w,
+ nof_dat => c_mem_nof_words,
+ init_sl => '0');
-- g_str = "use_ofs" :
constant c_buf_addr_w : natural := ceil_log2(g_nof_pages * g_page_sz);
constant c_buf_nof_words : natural := g_nof_pages * g_page_sz;
- constant c_buf_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_buf_addr_w,
- dat_w => g_data_w,
- nof_dat => c_buf_nof_words,
- init_sl => '0');
+ constant c_buf_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_buf_addr_w,
+ dat_w => g_data_w,
+ nof_dat => c_buf_nof_words,
+ init_sl => '0');
-- >>> Page control
@@ -222,36 +225,36 @@ begin
gen_mux : if g_str = "use_mux" generate
gen_pages : for I in 0 to g_nof_pages - 1 generate
u_ram : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => c_page_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst_a => rst_a,
- rst_b => rst_b,
- clk_a => clk_a,
- clk_b => clk_b,
- clken_a => clken_a,
- clken_b => clken_b,
- adr_a => adr_a,
- wr_en_a => page_wr_en_a(I),
- wr_dat_a => wr_dat_a,
- rd_en_a => page_rd_en_a(I),
- rd_dat_a => page_rd_dat_a(I),
- rd_val_a => page_rd_val_a(I),
- adr_b => adr_b,
- wr_en_b => page_wr_en_b(I),
- wr_dat_b => wr_dat_b,
- rd_en_b => page_rd_en_b(I),
- rd_dat_b => page_rd_dat_b(I),
- rd_val_b => page_rd_val_b(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_page_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst_a => rst_a,
+ rst_b => rst_b,
+ clk_a => clk_a,
+ clk_b => clk_b,
+ clken_a => clken_a,
+ clken_b => clken_b,
+ adr_a => adr_a,
+ wr_en_a => page_wr_en_a(I),
+ wr_dat_a => wr_dat_a,
+ rd_en_a => page_rd_en_a(I),
+ rd_dat_a => page_rd_dat_a(I),
+ rd_val_a => page_rd_val_a(I),
+ adr_b => adr_b,
+ wr_en_b => page_wr_en_b(I),
+ wr_dat_b => wr_dat_b,
+ rd_en_b => page_rd_en_b(I),
+ rd_dat_b => page_rd_dat_b(I),
+ rd_val_b => page_rd_val_b(I)
+ );
end generate;
p_mux : process(page_sel_a, wr_en_a, rd_en_a, page_sel_a_dly, page_rd_dat_a, page_rd_val_a,
- page_sel_b, wr_en_b, rd_en_b, page_sel_b_dly, page_rd_dat_b, page_rd_val_b)
+ page_sel_b, wr_en_b, rd_en_b, page_sel_b_dly, page_rd_dat_b, page_rd_val_b)
begin
-- use page_sel direct for control
page_wr_en_a <= (others => '0');
@@ -273,32 +276,32 @@ begin
gen_adr : if g_str = "use_adr" generate
u_mem : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => c_mem_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst_a => rst_a,
- rst_b => rst_b,
- clk_a => clk_a,
- clk_b => clk_b,
- clken_a => clken_a,
- clken_b => clken_b,
- adr_a => mem_adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => rd_en_a,
- rd_dat_a => rd_dat_a,
- rd_val_a => rd_val_a,
- adr_b => mem_adr_b,
- wr_en_b => wr_en_b,
- wr_dat_b => wr_dat_b,
- rd_en_b => rd_en_b,
- rd_dat_b => rd_dat_b,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mem_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst_a => rst_a,
+ rst_b => rst_b,
+ clk_a => clk_a,
+ clk_b => clk_b,
+ clken_a => clken_a,
+ clken_b => clken_b,
+ adr_a => mem_adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => rd_en_a,
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ adr_b => mem_adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ rd_en_b => rd_en_b,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
mem_adr_a <= TO_UVEC(page_sel_a, c_mem_nof_pages_w) & adr_a;
mem_adr_b <= TO_UVEC(page_sel_b, c_mem_nof_pages_w) & adr_b;
@@ -306,32 +309,32 @@ begin
gen_ofs : if g_str = "use_ofs" generate
u_buf : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => c_buf_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst_a => rst_a,
- rst_b => rst_b,
- clk_a => clk_a,
- clk_b => clk_b,
- clken_a => clken_a,
- clken_b => clken_b,
- adr_a => buf_adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => rd_en_a,
- rd_dat_a => rd_dat_a,
- rd_val_a => rd_val_a,
- adr_b => buf_adr_b,
- wr_en_b => wr_en_b,
- wr_dat_b => wr_dat_b,
- rd_en_b => rd_en_b,
- rd_dat_b => rd_dat_b,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_buf_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst_a => rst_a,
+ rst_b => rst_b,
+ clk_a => clk_a,
+ clk_b => clk_b,
+ clken_a => clken_a,
+ clken_b => clken_b,
+ adr_a => buf_adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => rd_en_a,
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ adr_b => buf_adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ rd_en_b => rd_en_b,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
buf_adr_a <= INCR_UVEC(RESIZE_UVEC(adr_a, c_buf_addr_w), page_ofs_a);
buf_adr_b <= INCR_UVEC(RESIZE_UVEC(adr_b, c_buf_addr_w), page_ofs_b);
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd b/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
index 254a426c53..28534d7d45 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
@@ -26,11 +26,11 @@
-- . See common_paged_ram_crw_crw for details.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_r_w is
generic (
@@ -62,34 +62,34 @@ end common_paged_ram_r_w;
architecture str of common_paged_ram_r_w is
begin
u_rw_rw : entity work.common_paged_ram_rw_rw
- generic map (
- g_technology => g_technology,
- g_str => g_str,
- g_data_w => g_data_w,
- g_nof_pages => g_nof_pages,
- g_page_sz => g_page_sz,
- g_start_page_a => g_wr_start_page,
- g_start_page_b => g_rd_start_page,
- g_rd_latency => g_rd_latency,
- g_true_dual_port => false
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- next_page_a => wr_next_page,
- adr_a => wr_adr,
- wr_en_a => wr_en,
- wr_dat_a => wr_dat,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => rd_next_page,
- adr_b => rd_adr,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en,
- rd_dat_b => rd_dat,
- rd_val_b => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_str => g_str,
+ g_data_w => g_data_w,
+ g_nof_pages => g_nof_pages,
+ g_page_sz => g_page_sz,
+ g_start_page_a => g_wr_start_page,
+ g_start_page_b => g_rd_start_page,
+ g_rd_latency => g_rd_latency,
+ g_true_dual_port => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ next_page_a => wr_next_page,
+ adr_a => wr_adr,
+ wr_en_a => wr_en,
+ wr_dat_a => wr_dat,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => rd_next_page,
+ adr_b => rd_adr,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en,
+ rd_dat_b => rd_dat,
+ rd_val_b => rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
index 22dc9992af..ce1ecd636f 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
@@ -26,11 +26,11 @@
-- . See common_paged_ram_crw_crw for details.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_rw_rw is
generic (
@@ -68,37 +68,37 @@ end common_paged_ram_rw_rw;
architecture str of common_paged_ram_rw_rw is
begin
u_crw_crw : entity work.common_paged_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_str => g_str,
- g_data_w => g_data_w,
- g_nof_pages => g_nof_pages,
- g_page_sz => g_page_sz,
- g_start_page_a => g_start_page_a,
- g_start_page_b => g_start_page_b,
- g_rd_latency => g_rd_latency,
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => clken,
- clken_b => clken,
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => rd_en_a,
- rd_dat_a => rd_dat_a,
- rd_val_a => rd_val_a,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => wr_en_b,
- wr_dat_b => wr_dat_b,
- rd_en_b => rd_en_b,
- rd_dat_b => rd_dat_b,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_str => g_str,
+ g_data_w => g_data_w,
+ g_nof_pages => g_nof_pages,
+ g_page_sz => g_page_sz,
+ g_start_page_a => g_start_page_a,
+ g_start_page_b => g_start_page_b,
+ g_rd_latency => g_rd_latency,
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst_a => rst,
+ rst_b => rst,
+ clk_a => clk,
+ clk_b => clk,
+ clken_a => clken,
+ clken_b => clken,
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => rd_en_a,
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ rd_en_b => rd_en_b,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd b/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
index 4c25313123..98034f12ce 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
@@ -26,9 +26,9 @@
-- Each page uses one or more RAM blocks.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_w_rr is
generic (
@@ -65,33 +65,33 @@ end common_paged_ram_w_rr;
architecture str of common_paged_ram_w_rr is
begin
u_ww_rr : entity work.common_paged_ram_ww_rr
- generic map (
- g_technology => g_technology,
- g_pipeline_in => g_pipeline_in,
- g_pipeline_out => g_pipeline_out,
- g_data_w => g_data_w,
- g_page_sz => g_page_sz,
- g_ram_rd_latency => g_ram_rd_latency
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- -- next page control
- next_page => next_page,
- -- double write access to one page --> use only page a
- wr_adr_a => wr_adr,
- wr_en_a => wr_en,
- wr_dat_a => wr_dat,
- -- double read access from the other one page
- rd_adr_a => rd_adr_a,
- rd_en_a => rd_en_a,
- rd_adr_b => rd_adr_b,
- rd_en_b => rd_en_b,
- -- double read data from the other one page after c_rd_latency
- rd_dat_a => rd_dat_a,
- rd_val_a => rd_val_a,
- rd_dat_b => rd_dat_b,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_out => g_pipeline_out,
+ g_data_w => g_data_w,
+ g_page_sz => g_page_sz,
+ g_ram_rd_latency => g_ram_rd_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ -- next page control
+ next_page => next_page,
+ -- double write access to one page --> use only page a
+ wr_adr_a => wr_adr,
+ wr_en_a => wr_en,
+ wr_dat_a => wr_dat,
+ -- double read access from the other one page
+ rd_adr_a => rd_adr_a,
+ rd_en_a => rd_en_a,
+ rd_adr_b => rd_adr_b,
+ rd_en_b => rd_en_b,
+ -- double read data from the other one page after c_rd_latency
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd b/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
index 8a0e60be2e..be50f313ef 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
@@ -26,11 +26,11 @@
-- Each page uses one or more RAM blocks.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use work.common_components_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use work.common_components_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_ww_rr is
generic (
@@ -76,11 +76,12 @@ architecture rtl of common_paged_ram_ww_rr is
constant c_addr_w : natural := ceil_log2(g_page_sz);
- constant c_page_ram : t_c_mem := (latency => g_ram_rd_latency,
- adr_w => c_addr_w,
- dat_w => g_data_w,
- nof_dat => g_page_sz,
- init_sl => '0');
+ constant c_page_ram : t_c_mem := (
+ latency => g_ram_rd_latency,
+ adr_w => c_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_page_sz,
+ init_sl => '0');
type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
type t_addr_arr is array (integer range <>) of std_logic_vector(c_addr_w - 1 downto 0);
@@ -177,28 +178,28 @@ begin
u_pipe_page_adr_b : common_pipeline generic map ("SIGNED", g_pipeline_in, 0, c_addr_w, c_addr_w) port map (rst, clk, clken, '0', '1', nxt_page_adr_b(I), page_adr_b(I));
u_page : entity work.common_ram_rw_rw
- generic map (
- g_technology => g_technology,
- g_ram => c_page_ram,
- g_init_file => "UNUSED"
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- adr_a => page_adr_a(I),
- wr_en_a => page_wr_en_a(I),
- wr_dat_a => page_wr_dat_a,
- rd_en_a => page_rd_en_a(I),
- rd_dat_a => page_rd_dat_a(I),
- rd_val_a => page_rd_val_a(I),
- adr_b => page_adr_b(I),
- wr_en_b => page_wr_en_b(I),
- wr_dat_b => page_wr_dat_b,
- rd_en_b => page_rd_en_b(I),
- rd_dat_b => page_rd_dat_b(I),
- rd_val_b => page_rd_val_b(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_page_ram,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ adr_a => page_adr_a(I),
+ wr_en_a => page_wr_en_a(I),
+ wr_dat_a => page_wr_dat_a,
+ rd_en_a => page_rd_en_a(I),
+ rd_dat_a => page_rd_dat_a(I),
+ rd_val_a => page_rd_val_a(I),
+ adr_b => page_adr_b(I),
+ wr_en_b => page_wr_en_b(I),
+ wr_dat_b => page_wr_dat_b,
+ rd_en_b => page_rd_en_b(I),
+ rd_dat_b => page_rd_dat_b(I),
+ rd_val_b => page_rd_val_b(I)
+ );
end generate;
-- use page_sel_out to account for the RAM read latency
diff --git a/libraries/base/common/src/vhdl/common_paged_reg.vhd b/libraries/base/common/src/vhdl/common_paged_reg.vhd
index 1e02358fc6..8dedd58a3d 100644
--- a/libraries/base/common/src/vhdl/common_paged_reg.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_reg.vhd
@@ -27,8 +27,8 @@
-- Remarks:
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_paged_reg is
generic (
@@ -56,17 +56,17 @@ begin
-- Shift the intermediate data pages when enabled
gen_pages : for I in g_nof_pages - 1 downto 0 generate
u_page : entity work.common_pipeline
- generic map (
- g_in_dat_w => g_data_w,
- g_out_dat_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_en => wr_en(I),
- in_dat => reg_dat(I + 1),
- out_dat => reg_dat(I)
- );
+ generic map (
+ g_in_dat_w => g_data_w,
+ g_out_dat_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_en => wr_en(I),
+ in_dat => reg_dat(I + 1),
+ out_dat => reg_dat(I)
+ );
end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_peak.vhd b/libraries/base/common/src/vhdl/common_peak.vhd
index 0e71cf50f5..9889852803 100644
--- a/libraries/base/common/src/vhdl/common_peak.vhd
+++ b/libraries/base/common/src/vhdl/common_peak.vhd
@@ -28,8 +28,8 @@
--
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_peak is
generic (
@@ -72,8 +72,8 @@ begin
end if;
if(rst = '1') then
- v.peak := (others => '0');
- v.out_val := '0';
+ v.peak := (others => '0');
+ v.out_val := '0';
end if;
rin <= v;
diff --git a/libraries/base/common/src/vhdl/common_pipeline.vhd b/libraries/base/common/src/vhdl/common_pipeline.vhd
index 27d000cd2b..bacc5a29b5 100644
--- a/libraries/base/common/src/vhdl/common_pipeline.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_pipeline is
generic (
diff --git a/libraries/base/common/src/vhdl/common_pipeline_integer.vhd b/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
index 5965cde936..c081c4bb29 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_pipeline_integer is
generic (
@@ -49,20 +49,20 @@ begin
out_dat <= TO_SINT(out_dat_slv) when g_representation = "SIGNED" else TO_UINT(out_dat_slv);
u_int : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_reset_value => g_reset_value,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_clr => in_clr,
- in_en => in_en,
- in_dat => in_dat_slv,
- out_dat => out_dat_slv
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_reset_value => g_reset_value,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_clr => in_clr,
+ in_en => in_en,
+ in_dat => in_dat_slv,
+ out_dat => out_dat_slv
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_pipeline_natural.vhd b/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
index 971946f8d4..dbd5261009 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_pipeline_natural is
generic (
@@ -48,20 +48,20 @@ begin
out_dat <= TO_UINT(out_dat_slv);
u_int : entity work.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => g_pipeline,
- g_reset_value => g_reset_value,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_clr => in_clr,
- in_en => in_en,
- in_dat => in_dat_slv,
- out_dat => out_dat_slv
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => g_pipeline,
+ g_reset_value => g_reset_value,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_clr => in_clr,
+ in_en => in_en,
+ in_dat => in_dat_slv,
+ out_dat => out_dat_slv
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_pipeline_sl.vhd b/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
index 0d592b7241..803c854134 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity common_pipeline_sl is
generic (
@@ -49,20 +49,20 @@ begin
out_dat <= out_dat_slv(0);
u_sl : entity work.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => g_pipeline,
- g_reset_value => sel_a_b(g_out_invert, 1 - g_reset_value, g_reset_value),
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_clr => in_clr,
- in_en => in_en,
- in_dat => in_dat_slv,
- out_dat => out_dat_slv
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => g_pipeline,
+ g_reset_value => sel_a_b(g_out_invert, 1 - g_reset_value, g_reset_value),
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_clr => in_clr,
+ in_en => in_en,
+ in_dat => in_dat_slv,
+ out_dat => out_dat_slv
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd b/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
index 8d883bbf79..3258dee78f 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
--- Purpose: Per symbol pipeline of the input data stream
--- Description:
--- The in_data is a concatenation of g_nof_symbols, that are each g_symbol_w
--- bits wide. The g_nof_symbols in the in_data slv can be pipelined
--- individualy as set by g_pipeline_arr(g_nof_symbols-1:0). The output
--- control signals val, sop and eop are also pipelined per symbol.
--- Remarks:
+ -- Purpose: Per symbol pipeline of the input data stream
+ -- Description:
+ -- The in_data is a concatenation of g_nof_symbols, that are each g_symbol_w
+ -- bits wide. The g_nof_symbols in the in_data slv can be pipelined
+ -- individualy as set by g_pipeline_arr(g_nof_symbols-1:0). The output
+ -- control signals val, sop and eop are also pipelined per symbol.
+ -- Remarks:
entity common_pipeline_symbol is
generic (
@@ -65,50 +65,50 @@ begin
-- pipeline per symbol
u_pipe_symbol : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline_arr(I),
- g_in_dat_w => g_symbol_w,
- g_out_dat_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_dat_arr(I),
- out_dat => out_dat_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(I),
+ g_in_dat_w => g_symbol_w,
+ g_out_dat_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_dat_arr(I),
+ out_dat => out_dat_arr(I)
+ );
u_pipe_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(I)
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => out_val_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(I)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => out_val_arr(I)
+ );
u_pipe_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(I)
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => out_sop_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(I)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => out_sop_arr(I)
+ );
u_pipe_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(I)
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => out_eop_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(I)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => out_eop_arr(I)
+ );
-- map arr to output vector
out_data((I + 1) * g_symbol_w - 1 downto I * g_symbol_w) <= out_dat_arr(I);
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index e1c2f98ffb..3e722fcbed 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -27,9 +27,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
-- CONSTANT DECLARATIONS ----------------------------------------------------
@@ -463,7 +463,7 @@ package common_pkg is
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
+ -- Used in common_add_sub.vhd
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
@@ -563,20 +563,22 @@ package common_pkg is
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
function func_common_reorder2_is_there(I, J : natural) return boolean;
@@ -586,9 +588,10 @@ package common_pkg is
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
@@ -599,38 +602,38 @@ package body common_pkg is
end;
function ceil_pow2(n : integer) return natural is
- -- Also allows negative exponents and rounds up before returning the value
+ -- Also allows negative exponents and rounds up before returning the value
begin
return natural(integer(ceil(2**real(n))));
end;
function true_log2(n : natural) return natural is
- -- Purpose: For calculating extra vector width of existing vector
- -- Description: Return mathematical ceil(log2(n))
- -- n log2()
- -- 0 -> -oo --> FAILURE
- -- 1 -> 0
- -- 2 -> 1
- -- 3 -> 2
- -- 4 -> 2
- -- 5 -> 3
- -- 6 -> 3
- -- 7 -> 3
- -- 8 -> 3
- -- 9 -> 4
- -- etc, up to n = NATURAL'HIGH = 2**31-1
+ -- Purpose: For calculating extra vector width of existing vector
+ -- Description: Return mathematical ceil(log2(n))
+ -- n log2()
+ -- 0 -> -oo --> FAILURE
+ -- 1 -> 0
+ -- 2 -> 1
+ -- 3 -> 2
+ -- 4 -> 2
+ -- 5 -> 3
+ -- 6 -> 3
+ -- 7 -> 3
+ -- 8 -> 3
+ -- 9 -> 4
+ -- etc, up to n = NATURAL'HIGH = 2**31-1
begin
return natural(integer(ceil(log2(real(n)))));
end;
function ceil_log2(n : natural) return natural is
- -- Purpose: For calculating vector width of new vector
- -- Description:
- -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
- -- the vector width width for 1 address, to avoid NULL array for single
- -- word register address.
- -- If n = 0, return 0 so we get a NULL array when using
- -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
+ -- Purpose: For calculating vector width of new vector
+ -- Description:
+ -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
+ -- the vector width width for 1 address, to avoid NULL array for single
+ -- word register address.
+ -- If n = 0, return 0 so we get a NULL array when using
+ -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
return 0; -- Get NULL array
@@ -1038,7 +1041,7 @@ package body common_pkg is
function smallest(n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
@@ -2052,8 +2055,8 @@ package body common_pkg is
constant c_min : real := -2.0**REAL(w - 1);
constant c_resolution : real := 1.0 / 2.0**REAL(resolution_w);
constant c_sreal : real := ROUND(sdec / c_resolution); -- rounds away from zero
- -- Convert to positive using TO_UVEC, so if sdec is negative, then
- -- negate sdec to have positive c_udec.
+ -- Convert to positive using TO_UVEC, so if sdec is negative, then
+ -- negate sdec to have positive c_udec.
constant c_pos : boolean := sdec >= 0.0;
constant c_udec : real := sel_a_b(c_pos, sdec, -sdec);
-- Determine SLV value for positive REAL, use w+1 to fit negate of most negative value
@@ -2412,10 +2415,10 @@ package body common_pkg is
begin
if shift < 0 then
return std_logic_vector(ROTATE_LEFT(unsigned(vec), -shift)); -- /<-- vec <--\
- -- \---------->/
+ -- \---------->/
else
return std_logic_vector(ROTATE_RIGHT(unsigned(vec), shift)); -- /--> vec -->\
- -- \<----------/
+ -- \<----------/
end if;
end;
@@ -2439,8 +2442,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
@@ -2449,8 +2452,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
@@ -2898,16 +2901,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2927,8 +2931,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -3031,8 +3036,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -3071,9 +3076,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
diff --git a/libraries/base/common/src/vhdl/common_pulse_delay.vhd b/libraries/base/common/src/vhdl/common_pulse_delay.vhd
index 66ffa0296b..dd5c9a345d 100644
--- a/libraries/base/common/src/vhdl/common_pulse_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_delay.vhd
@@ -26,8 +26,8 @@
-- . Note: pulse_out must have occurured before the next pulse_in can be delayed.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_pulse_delay is
generic (
@@ -58,17 +58,17 @@ begin
-- Switch to start counter @ pulse_in, and stop counter @ pulse_out.
-------------------------------------------------------------------------------
u_common_switch : entity work.common_switch
- generic map (
- g_or_high => true,
- g_priority_lo => false
- )
- port map (
- clk => clk,
- rst => rst,
- switch_high => pulse_in,
- switch_low => nxt_pulse_out,
- out_level => common_counter_cnt_en
- );
+ generic map (
+ g_or_high => true,
+ g_priority_lo => false
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => pulse_in,
+ switch_low => nxt_pulse_out,
+ out_level => common_counter_cnt_en
+ );
-------------------------------------------------------------------------------
-- Count delay cycles relative to pulse_in
@@ -78,18 +78,18 @@ begin
-- output count value after cnt_en (also 0).
-------------------------------------------------------------------------------
u_common_counter : entity work.common_counter
- generic map (
- g_width => c_pulse_delay_max_width,
- g_init => 1
- )
- port map (
- clk => clk,
- rst => rst,
- cnt_ld => pulse_in, -- Clear (load "1") the counter on every pulse_in
- cnt_en => common_counter_cnt_en,
- load => TO_UVEC(1, c_pulse_delay_max_width),
- count => common_counter_count
- );
+ generic map (
+ g_width => c_pulse_delay_max_width,
+ g_init => 1
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ cnt_ld => pulse_in, -- Clear (load "1") the counter on every pulse_in
+ cnt_en => common_counter_cnt_en,
+ load => TO_UVEC(1, c_pulse_delay_max_width),
+ count => common_counter_count
+ );
-------------------------------------------------------------------------------
-- Assign nxt_pulse_out
@@ -98,7 +98,7 @@ begin
nxt_pulse_delay_reg <= pulse_delay when pulse_in = '1' else pulse_delay_reg;
nxt_pulse_out <= pulse_in when pulse_delay = TO_UVEC(0, c_pulse_delay_max_width) else -- 0 cycles delay (pulse_delay_reg not valid yet; using pulse_delay)
- '1' when common_counter_count = pulse_delay_reg else '0'; -- >=1 cycles delay (so pulse_delay_reg will contain registered pulse_delay)
+ '1' when common_counter_count = pulse_delay_reg else '0'; -- >=1 cycles delay (so pulse_delay_reg will contain registered pulse_delay)
-------------------------------------------------------------------------------
-- Optional output register
diff --git a/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd b/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
index f4e02fa89d..80d27299c6 100644
--- a/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
@@ -27,15 +27,15 @@
-- Set pulse_delay between incoming and outgoing pulse, in units of dp_clk cycles (5ns)
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity common_pulse_delay_reg is
generic (
g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and pulse_clk are the same, else use TRUE to cross the clock domain
g_pulse_delay_max : natural := 0 -- Maximum number of clk cycles that pulse can be delayed
- );
+ );
port (
pulse_clk : in std_logic;
pulse_rst : in std_logic;
@@ -51,11 +51,12 @@ end common_pulse_delay_reg;
architecture rtl of common_pulse_delay_reg is
constant c_nof_mm_regs : natural := 1;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_mm_regs),
- dat_w => c_word_w,
- nof_dat => c_nof_mm_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_mm_regs),
+ dat_w => c_word_w,
+ nof_dat => c_nof_mm_regs,
+ init_sl => '0');
signal mm_pulse_delay : std_logic_vector(ceil_log2(g_pulse_delay_max) - 1 downto 0);
begin
@@ -88,7 +89,7 @@ begin
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -124,16 +125,16 @@ begin
gen_common_reg_cross_domain : if g_cross_clock_domain = true generate
u_common_reg_cross_domain : entity work.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_pulse_delay,
- in_done => OPEN,
- out_rst => pulse_rst,
- out_clk => pulse_clk,
- out_dat => pulse_delay,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_pulse_delay,
+ in_done => OPEN,
+ out_rst => pulse_rst,
+ out_clk => pulse_clk,
+ out_dat => pulse_delay,
+ out_new => open
+ );
end generate; -- gen_common_reg_cross_domain
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_pulse_extend.vhd b/libraries/base/common/src/vhdl/common_pulse_extend.vhd
index 23b38e1ebf..e08184ff45 100644
--- a/libraries/base/common/src/vhdl/common_pulse_extend.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_extend.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
--- Purpose: Extend the active high time of a pulse
--- Description:
--- Extend an input pulse p_in to an output pulse ep_out that is delayed by 1
--- clock cycle and lasts for 2**g_extend_w number of clock cycles longer
--- after that p_in went low.
+ -- Purpose: Extend the active high time of a pulse
+ -- Description:
+ -- Extend an input pulse p_in to an output pulse ep_out that is delayed by 1
+ -- clock cycle and lasts for 2**g_extend_w number of clock cycles longer
+ -- after that p_in went low.
entity common_pulse_extend is
generic (
@@ -90,4 +90,4 @@ begin
end if;
end if;
end process;
-end architecture;
+ end architecture;
diff --git a/libraries/base/common/src/vhdl/common_pulser.vhd b/libraries/base/common/src/vhdl/common_pulser.vhd
index 5100346bb5..b17d2d0f56 100644
--- a/libraries/base/common/src/vhdl/common_pulser.vhd
+++ b/libraries/base/common/src/vhdl/common_pulser.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
--- Purpose: Output a one cycle pulse every period
--- Description:
--- The pulse period can dynamically be set via the input pulse_period.
--- Default pulse_period = g_pulse_period, to also support static setting of
--- the pulse period. The pulse_clr can be used to synchronise the pulser.
--- The g_pulse_phase defines when the first pulse occurs after rst release:
--- . g_pulse_phase=0 : first pulse after g_pulse_period cycles
--- . g_pulse_phase=g_pulse_period : first pulse after g_pulse_period cycles
--- . g_pulse_phase=g_pulse_period-1 : first pulse after 1 cycles
--- . g_pulse_phase=g_pulse_period-N : first pulse after N cycles
+ -- Purpose: Output a one cycle pulse every period
+ -- Description:
+ -- The pulse period can dynamically be set via the input pulse_period.
+ -- Default pulse_period = g_pulse_period, to also support static setting of
+ -- the pulse period. The pulse_clr can be used to synchronise the pulser.
+ -- The g_pulse_phase defines when the first pulse occurs after rst release:
+ -- . g_pulse_phase=0 : first pulse after g_pulse_period cycles
+ -- . g_pulse_phase=g_pulse_period : first pulse after g_pulse_period cycles
+ -- . g_pulse_phase=g_pulse_period-1 : first pulse after 1 cycles
+ -- . g_pulse_phase=g_pulse_period-N : first pulse after N cycles
entity common_pulser is
generic (
g_pulse_period : natural := 25000; -- nof clk cycles to get pulse period
@@ -83,16 +83,16 @@ begin
cnt_clr <= pulse_clr or cnt_period;
u_cnt : entity common_lib.common_counter
- generic map (
- g_init => c_pulse_init,
- g_width => c_pulse_period_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_init => c_pulse_init,
+ g_width => c_pulse_period_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd b/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
index 0afbe95fb9..773a31b746 100644
--- a/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
+++ b/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
--- Purpose: Provide timing pulses for interval 1 us, 1 ms and 1 s
+ -- Purpose: Provide timing pulses for interval 1 us, 1 ms and 1 s
entity common_pulser_us_ms_s is
generic (
@@ -73,44 +73,44 @@ begin
end process;
u_common_pulser_us : entity common_lib.common_pulser
- generic map (
- g_pulse_period => g_pulse_us,
- g_pulse_phase => g_pulse_us - 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => '1',
- pulse_clr => sync,
- pulse_out => pulse_us_pp
- );
+ generic map (
+ g_pulse_period => g_pulse_us,
+ g_pulse_phase => g_pulse_us - 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => '1',
+ pulse_clr => sync,
+ pulse_out => pulse_us_pp
+ );
u_common_pulser_ms : entity common_lib.common_pulser
- generic map (
- g_pulse_period => g_pulse_ms,
- g_pulse_phase => g_pulse_ms - 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => pulse_us_pp,
- pulse_clr => sync,
- pulse_out => pulse_ms_p
- );
+ generic map (
+ g_pulse_period => g_pulse_ms,
+ g_pulse_phase => g_pulse_ms - 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => pulse_us_pp,
+ pulse_clr => sync,
+ pulse_out => pulse_ms_p
+ );
u_common_pulser_s : entity common_lib.common_pulser
- generic map (
- g_pulse_period => g_pulse_s,
- g_pulse_phase => g_pulse_s - 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => pulse_ms_p,
- pulse_clr => sync,
- pulse_out => pulse_s_reg
- );
+ generic map (
+ g_pulse_period => g_pulse_s,
+ g_pulse_phase => g_pulse_s - 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => pulse_ms_p,
+ pulse_clr => sync,
+ pulse_out => pulse_s_reg
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
index 748ab33ce8..0adc0132bb 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_cr_cw is
generic (
@@ -56,29 +56,29 @@ begin
-- Use port b only for read in read clock domain
u_cr_cw : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file
- )
- port map (
- rst_a => wr_rst,
- rst_b => rd_rst,
- clk_a => wr_clk,
- clk_b => rd_clk,
- clken_a => wr_clken,
- clken_b => rd_clken,
- wr_en_a => wr_en,
- wr_en_b => '0',
- wr_dat_a => wr_dat,
- wr_dat_b => (others => '0'),
- adr_a => wr_adr,
- adr_b => rd_adr,
- rd_en_a => '0',
- rd_en_b => rd_en,
- rd_dat_a => OPEN,
- rd_dat_b => rd_dat,
- rd_val_a => OPEN,
- rd_val_b => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file
+ )
+ port map (
+ rst_a => wr_rst,
+ rst_b => rd_rst,
+ clk_a => wr_clk,
+ clk_b => rd_clk,
+ clken_a => wr_clken,
+ clken_b => rd_clken,
+ wr_en_a => wr_en,
+ wr_en_b => '0',
+ wr_dat_a => wr_dat,
+ wr_dat_b => (others => '0'),
+ adr_a => wr_adr,
+ adr_b => rd_adr,
+ rd_en_a => '0',
+ rd_en_b => rd_en,
+ rd_dat_a => OPEN,
+ rd_dat_b => rd_dat,
+ rd_val_a => OPEN,
+ rd_val_b => rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
index b2a595644f..b1dce1990b 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_cr_cw_ratio is
generic (
@@ -57,30 +57,30 @@ begin
-- Use port b only for read in read clock domain
u_cr_cw : entity work.common_ram_crw_crw_ratio
- generic map (
- g_technology => g_technology,
- g_ram_a => g_ram_wr,
- g_ram_b => g_ram_rd,
- g_init_file => g_init_file
- )
- port map (
- rst_a => wr_rst,
- rst_b => rd_rst,
- clk_a => wr_clk,
- clk_b => rd_clk,
- clken_a => wr_clken,
- clken_b => rd_clken,
- wr_en_a => wr_en,
- wr_en_b => '0',
- wr_dat_a => wr_dat,
- wr_dat_b => (others => '0'),
- adr_a => wr_adr,
- adr_b => rd_adr,
- rd_en_a => '0',
- rd_en_b => rd_en,
- rd_dat_a => OPEN,
- rd_dat_b => rd_dat,
- rd_val_a => OPEN,
- rd_val_b => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram_a => g_ram_wr,
+ g_ram_b => g_ram_rd,
+ g_init_file => g_init_file
+ )
+ port map (
+ rst_a => wr_rst,
+ rst_b => rd_rst,
+ clk_a => wr_clk,
+ clk_b => rd_clk,
+ clken_a => wr_clken,
+ clken_b => rd_clken,
+ wr_en_a => wr_en,
+ wr_en_b => '0',
+ wr_dat_a => wr_dat,
+ wr_dat_b => (others => '0'),
+ adr_a => wr_adr,
+ adr_b => rd_adr,
+ rd_en_a => '0',
+ rd_en_b => rd_en,
+ rd_dat_a => OPEN,
+ rd_dat_b => rd_dat,
+ rd_val_a => OPEN,
+ rd_val_b => rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
index c49f6b3957..e55b84c5c0 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_crw_cr is
generic (
@@ -60,29 +60,29 @@ begin
-- Use port b for read only in ST clock domain
u_crw_cr : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file
- )
- port map (
- rst_a => mm_rst,
- rst_b => st_rst,
- clk_a => mm_clk,
- clk_b => st_clk,
- clken_a => mm_clken,
- clken_b => st_clken,
- wr_en_a => mm_wr_en,
- wr_en_b => '0',
- wr_dat_a => mm_wr_dat,
- wr_dat_b => (others => '0'),
- adr_a => mm_adr,
- adr_b => st_adr,
- rd_en_a => mm_rd_en,
- rd_en_b => st_rd_en,
- rd_dat_a => mm_rd_dat,
- rd_dat_b => st_rd_dat,
- rd_val_a => mm_rd_val,
- rd_val_b => st_rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file
+ )
+ port map (
+ rst_a => mm_rst,
+ rst_b => st_rst,
+ clk_a => mm_clk,
+ clk_b => st_clk,
+ clken_a => mm_clken,
+ clken_b => st_clken,
+ wr_en_a => mm_wr_en,
+ wr_en_b => '0',
+ wr_dat_a => mm_wr_dat,
+ wr_dat_b => (others => '0'),
+ adr_a => mm_adr,
+ adr_b => st_adr,
+ rd_en_a => mm_rd_en,
+ rd_en_b => st_rd_en,
+ rd_dat_a => mm_rd_dat,
+ rd_dat_b => st_rd_dat,
+ rd_val_a => mm_rd_val,
+ rd_val_b => st_rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
index 021d7638b8..61bda7456d 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_crw_cw is
generic (
@@ -59,29 +59,29 @@ begin
-- Use port b for write only in ST clock domain
u_crw_cw : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file
- )
- port map (
- rst_a => mm_rst,
- rst_b => st_rst,
- clk_a => mm_clk,
- clk_b => st_clk,
- clken_a => mm_clken,
- clken_b => st_clken,
- wr_en_a => mm_wr_en,
- wr_en_b => st_wr_en,
- wr_dat_a => mm_wr_dat,
- wr_dat_b => st_wr_dat,
- adr_a => mm_adr,
- adr_b => st_adr,
- rd_en_a => mm_rd_en,
- rd_en_b => '0',
- rd_dat_a => mm_rd_dat,
- rd_dat_b => OPEN,
- rd_val_a => mm_rd_val,
- rd_val_b => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file
+ )
+ port map (
+ rst_a => mm_rst,
+ rst_b => st_rst,
+ clk_a => mm_clk,
+ clk_b => st_clk,
+ clken_a => mm_clken,
+ clken_b => st_clken,
+ wr_en_a => mm_wr_en,
+ wr_en_b => st_wr_en,
+ wr_dat_a => mm_wr_dat,
+ wr_dat_b => st_wr_dat,
+ adr_a => mm_adr,
+ adr_b => st_adr,
+ rd_en_a => mm_rd_en,
+ rd_en_b => '0',
+ rd_dat_a => mm_rd_dat,
+ rd_dat_b => OPEN,
+ rd_val_a => mm_rd_val,
+ rd_val_b => open
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_r_w.vhd b/libraries/base/common/src/vhdl/common_ram_r_w.vhd
index 099cbb831f..6965672ba8 100644
--- a/libraries/base/common/src/vhdl/common_ram_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_r_w.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_r_w is
generic (
@@ -51,27 +51,27 @@ begin
-- Use port b only for read
u_rw_rw : entity work.common_ram_rw_rw
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file,
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- wr_en_a => wr_en,
- wr_en_b => '0',
- wr_dat_a => wr_dat,
- --wr_dat_b => (OTHERS=>'0'),
- adr_a => wr_adr,
- adr_b => rd_adr,
- rd_en_a => '0',
- rd_en_b => rd_en,
- rd_dat_a => OPEN,
- rd_dat_b => rd_dat,
- rd_val_a => OPEN,
- rd_val_b => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file,
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ wr_en_a => wr_en,
+ wr_en_b => '0',
+ wr_dat_a => wr_dat,
+ --wr_dat_b => (OTHERS=>'0'),
+ adr_a => wr_adr,
+ adr_b => rd_adr,
+ rd_en_a => '0',
+ rd_en_b => rd_en,
+ rd_dat_a => OPEN,
+ rd_dat_b => rd_dat,
+ rd_val_a => OPEN,
+ rd_val_b => rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
index 5c333e5405..25b5061a8f 100644
--- a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_rw_rw is
generic (
@@ -55,30 +55,30 @@ begin
-- Use only one clock domain
u_crw_crw : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file,
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => clken,
- clken_b => clken,
- wr_en_a => wr_en_a,
- wr_en_b => wr_en_b,
- wr_dat_a => wr_dat_a,
- wr_dat_b => wr_dat_b,
- adr_a => adr_a,
- adr_b => adr_b,
- rd_en_a => rd_en_a,
- rd_en_b => rd_en_b,
- rd_dat_a => rd_dat_a,
- rd_dat_b => rd_dat_b,
- rd_val_a => rd_val_a,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file,
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst_a => rst,
+ rst_b => rst,
+ clk_a => clk,
+ clk_b => clk,
+ clken_a => clken,
+ clken_b => clken,
+ wr_en_a => wr_en_a,
+ wr_en_b => wr_en_b,
+ wr_dat_a => wr_dat_a,
+ wr_dat_b => wr_dat_b,
+ adr_a => adr_a,
+ adr_b => adr_b,
+ rd_en_a => rd_en_a,
+ rd_en_b => rd_en_b,
+ rd_dat_a => rd_dat_a,
+ rd_dat_b => rd_dat_b,
+ rd_val_a => rd_val_a,
+ rd_val_b => rd_val_b
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd b/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
index 84e56f935c..b3e5bc8dc6 100644
--- a/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
@@ -21,21 +21,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.common_mem_pkg.all;
-
--- Purpose: Get in_dat from in_clk to out_clk domain when in_new is asserted.
--- Remarks:
--- . If in_new is a pulse, then new in_dat is available after g_in_new_latency.
--- . It is also allowed to hold in_new high, then out_new will pulse once for
--- every 24 out_clk cycles.
--- . Use in_done to be sure that in_dat due to in_new has crossed the clock
--- domain, in case of multiple in_new pulses in a row the in_done will only
--- pulse when this state remains s_idle, so after the last in_new.
--- . If the in_dat remains unchanged during the crossing of in_new to out_en
--- then g_input_buf=FALSE may be used to save some flipflops
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.common_mem_pkg.all;
+
+ -- Purpose: Get in_dat from in_clk to out_clk domain when in_new is asserted.
+ -- Remarks:
+ -- . If in_new is a pulse, then new in_dat is available after g_in_new_latency.
+ -- . It is also allowed to hold in_new high, then out_new will pulse once for
+ -- every 24 out_clk cycles.
+ -- . Use in_done to be sure that in_dat due to in_new has crossed the clock
+ -- domain, in case of multiple in_new pulses in a row the in_done will only
+ -- pulse when this state remains s_idle, so after the last in_new.
+ -- . If the in_dat remains unchanged during the crossing of in_new to out_en
+ -- then g_input_buf=FALSE may be used to save some flipflops
entity common_reg_cross_domain is
generic (
@@ -166,15 +166,15 @@ begin
-- cross clock domain
------------------------------------------------------------------------------
u_cross_req : entity common_lib.common_spulse
- port map (
- in_rst => in_rst,
- in_clk => in_clk,
- in_pulse => cross_req,
- in_busy => cross_busy,
- out_rst => out_rst,
- out_clk => out_clk,
- out_pulse => out_en
- );
+ port map (
+ in_rst => in_rst,
+ in_clk => in_clk,
+ in_pulse => cross_req,
+ in_busy => cross_busy,
+ out_rst => out_rst,
+ out_clk => out_clk,
+ out_pulse => out_en
+ );
------------------------------------------------------------------------------
-- out_clk domain
diff --git a/libraries/base/common/src/vhdl/common_reg_r_w.vhd b/libraries/base/common/src/vhdl/common_reg_r_w.vhd
index f58ac2c3b0..369eadfaaa 100644
--- a/libraries/base/common/src/vhdl/common_reg_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_r_w.vhd
@@ -20,39 +20,39 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-
--- Derived from LOFAR cfg_single_reg
-
--- Purpose: Provide a MM interface to a register vector
---
--- Description:
--- The register has g_reg.nof_dat words and each word is g_reg.dat_w bits
--- wide. At the control side the register is accessed per word using the
--- address input wr_adr or rd_adr as index. At the data side the whole
--- register of g_reg.dat_w*g_reg.nof_dat bits is available at once. This is
--- the key difference with using a RAM.
--- E.g. for g_reg.nof_dat = 3 and g_reg.dat_w = 32 the addressing accesses
--- the register bits as follows:
--- wr_adr[1:0], rd_adr[1:0] = 0 --> reg[31:0]
--- wr_adr[1:0], rd_adr[1:0] = 1 --> reg[63:32]
--- wr_adr[1:0], rd_adr[1:0] = 2 --> reg[95:64]
--- E.g. for wr_adr = 0 and wr_en = '1': out_reg[31:0] = wr_dat[31:0]
--- E.g. for rd_adr = 0 and rd_en = '1': rd_dat[31:0] = in_reg[31:0]
---
--- The word in the register that got accessed is reported via reg_wr_arr
--- or via reg_rd_arr depended on whether it was a write access or an read
--- access.
---
--- Usage:
--- 1) Connect out_reg to in_reg for write and readback register.
--- 2) Do not connect out_reg to in_reg for seperate write only register and
--- read only register at the same address.
--- 3) Leave out_reg OPEN for read only register.
--- 4) Connect wr_adr and rd_adr to have a shared address bus register.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+
+ -- Derived from LOFAR cfg_single_reg
+
+ -- Purpose: Provide a MM interface to a register vector
+ --
+ -- Description:
+ -- The register has g_reg.nof_dat words and each word is g_reg.dat_w bits
+ -- wide. At the control side the register is accessed per word using the
+ -- address input wr_adr or rd_adr as index. At the data side the whole
+ -- register of g_reg.dat_w*g_reg.nof_dat bits is available at once. This is
+ -- the key difference with using a RAM.
+ -- E.g. for g_reg.nof_dat = 3 and g_reg.dat_w = 32 the addressing accesses
+ -- the register bits as follows:
+ -- wr_adr[1:0], rd_adr[1:0] = 0 --> reg[31:0]
+ -- wr_adr[1:0], rd_adr[1:0] = 1 --> reg[63:32]
+ -- wr_adr[1:0], rd_adr[1:0] = 2 --> reg[95:64]
+ -- E.g. for wr_adr = 0 and wr_en = '1': out_reg[31:0] = wr_dat[31:0]
+ -- E.g. for rd_adr = 0 and rd_en = '1': rd_dat[31:0] = in_reg[31:0]
+ --
+ -- The word in the register that got accessed is reported via reg_wr_arr
+ -- or via reg_rd_arr depended on whether it was a write access or an read
+ -- access.
+ --
+ -- Usage:
+ -- 1) Connect out_reg to in_reg for write and readback register.
+ -- 2) Do not connect out_reg to in_reg for seperate write only register and
+ -- read only register at the same address.
+ -- 3) Leave out_reg OPEN for read only register.
+ -- 4) Connect wr_adr and rd_adr to have a shared address bus register.
entity common_reg_r_w is
generic (
@@ -113,17 +113,17 @@ begin
-- Pipeline to support read data latency > 1
u_pipe_rd : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => c_pipe_dat_w,
- g_out_dat_w => c_pipe_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => pipe_dat_in,
- out_dat => pipe_dat_out
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => c_pipe_dat_w,
+ g_out_dat_w => c_pipe_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => pipe_dat_in,
+ out_dat => pipe_dat_out
+ );
pipe_dat_in <= int_rd_val & int_rd_dat;
diff --git a/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd b/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
index 63e5a8a45f..4e2b911a2e 100644
--- a/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
@@ -52,9 +52,9 @@
-- the data.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
entity common_reg_r_w_dc is
generic (
@@ -108,27 +108,27 @@ begin
sla_out <= i_sla_out;
u_reg : entity work.common_reg_r_w
- generic map (
- g_reg => g_reg,
- g_init_reg => g_init_reg
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- control side
- wr_en => sla_in.wr,
- wr_adr => sla_in.address(g_reg.adr_w - 1 downto 0),
- wr_dat => sla_in.wrdata(g_reg.dat_w - 1 downto 0),
- rd_en => sla_in.rd,
- rd_adr => sla_in.address(g_reg.adr_w - 1 downto 0),
- rd_dat => i_sla_out.rddata(g_reg.dat_w - 1 downto 0),
- rd_val => i_sla_out.rdval,
- -- data side
- reg_wr_arr => vector_wr_arr,
- reg_rd_arr => vector_rd_arr,
- out_reg => out_vector,
- in_reg => in_vector
- );
+ generic map (
+ g_reg => g_reg,
+ g_init_reg => g_init_reg
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- control side
+ wr_en => sla_in.wr,
+ wr_adr => sla_in.address(g_reg.adr_w - 1 downto 0),
+ wr_dat => sla_in.wrdata(g_reg.dat_w - 1 downto 0),
+ rd_en => sla_in.rd,
+ rd_adr => sla_in.address(g_reg.adr_w - 1 downto 0),
+ rd_dat => i_sla_out.rddata(g_reg.dat_w - 1 downto 0),
+ rd_val => i_sla_out.rdval,
+ -- data side
+ reg_wr_arr => vector_wr_arr,
+ reg_rd_arr => vector_rd_arr,
+ out_reg => out_vector,
+ in_reg => in_vector
+ );
------------------------------------------------------------------------------
-- Transfer register value between mm_clk and st_clk domain.
@@ -162,51 +162,51 @@ begin
gen_rd : if g_readback = false generate
u_in_vector : entity work.common_reg_cross_domain
- generic map (
- g_in_new_latency => g_in_new_latency
+ generic map (
+ g_in_new_latency => g_in_new_latency
+ )
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_new => in_new,
+ in_dat => in_reg,
+ in_done => OPEN,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => in_vector,
+ out_new => open
+ );
+ end generate;
+
+ u_out_reg : entity work.common_reg_cross_domain
+ generic map(
+ g_out_dat_init => g_init_reg
)
port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_new => in_new,
- in_dat => in_reg,
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => out_vector,
in_done => OPEN,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => in_vector,
- out_new => open
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => out_reg,
+ out_new => out_new_i
);
- end generate;
-
- u_out_reg : entity work.common_reg_cross_domain
- generic map(
- g_out_dat_init => g_init_reg
- )
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => out_vector,
- in_done => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => out_reg,
- out_new => out_new_i
- );
u_toggle : entity work.common_switch
- generic map (
- g_rst_level => '0',
- g_priority_lo => false,
- g_or_high => false,
- g_and_low => false
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- switch_high => wr_pulse,
- switch_low => out_new_i,
- out_level => toggle
- );
+ generic map (
+ g_rst_level => '0',
+ g_priority_lo => false,
+ g_or_high => false,
+ g_and_low => false
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ switch_high => wr_pulse,
+ switch_low => out_new_i,
+ out_level => toggle
+ );
wr_pulse <= '0' when vector_or(reg_wr_arr_i) = '0' else '1';
out_new <= out_new_i and toggle;
@@ -214,26 +214,26 @@ begin
gen_access_evt : for I in 0 to g_reg.nof_dat - 1 generate
u_reg_wr_arr : entity work.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => vector_wr_arr(I),
- in_busy => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => reg_wr_arr_i(I)
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => vector_wr_arr(I),
+ in_busy => OPEN,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => reg_wr_arr_i(I)
+ );
u_reg_rd_arr : entity work.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => vector_rd_arr(I),
- in_busy => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => reg_rd_arr(I)
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => vector_rd_arr(I),
+ in_busy => OPEN,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => reg_rd_arr(I)
+ );
end generate;
end generate; -- gen_cross
diff --git a/libraries/base/common/src/vhdl/common_reinterleave.vhd b/libraries/base/common/src/vhdl/common_reinterleave.vhd
index af7766e68e..94fe282525 100644
--- a/libraries/base/common/src/vhdl/common_reinterleave.vhd
+++ b/libraries/base/common/src/vhdl/common_reinterleave.vhd
@@ -20,18 +20,18 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-
--- Purpose:
--- Deinterleave g_nof_in inputs based on g_deint_block_size and re-interleave
--- these streams onto g_nof_out outputs based on g_inter_block_size.
--- Description:
--- The input and output streams are concatenated into one SLV.
--- Remarks:
--- . g_inter_block_size >= g_deint_block_size;
--- . One valid input applies to all input data streams;
--- . The user must take care of the correct valid/gap ratio on the inputs.
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+
+ -- Purpose:
+ -- Deinterleave g_nof_in inputs based on g_deint_block_size and re-interleave
+ -- these streams onto g_nof_out outputs based on g_inter_block_size.
+ -- Description:
+ -- The input and output streams are concatenated into one SLV.
+ -- Remarks:
+ -- . g_inter_block_size >= g_deint_block_size;
+ -- . One valid input applies to all input data streams;
+ -- . The user must take care of the correct valid/gap ratio on the inputs.
entity common_reinterleave is
generic (
@@ -41,7 +41,7 @@ entity common_reinterleave is
g_inter_block_size : natural;
g_dat_w : natural;
g_align_out : boolean := false
- );
+ );
port (
clk : in std_logic;
rst : in std_logic;
@@ -71,15 +71,17 @@ architecture rtl of common_reinterleave is
constant c_deinterleave_only : boolean := g_nof_in = 1 and g_nof_out > 1;
constant c_wires_only : boolean := g_nof_in = 1 and g_nof_out = 1;
- constant c_nof_deint : natural := sel_a_b( c_interleave_only, 0,
- sel_a_b( c_deinterleave_only, 1,
- sel_a_b( c_wires_only, 0,
- g_nof_in)));
+ constant c_nof_deint : natural := sel_a_b(
+ c_interleave_only, 0,
+ sel_a_b( c_deinterleave_only, 1,
+ sel_a_b( c_wires_only, 0,
+ g_nof_in)));
- constant c_nof_inter : natural := sel_a_b( c_interleave_only, 1,
- sel_a_b( c_deinterleave_only, 0,
- sel_a_b( c_wires_only, 0,
- g_nof_out)));
+ constant c_nof_inter : natural := sel_a_b(
+ c_interleave_only, 1,
+ sel_a_b( c_deinterleave_only, 0,
+ sel_a_b( c_wires_only, 0,
+ g_nof_out)));
constant c_nof_deint_out : natural := g_nof_out;
constant c_nof_inter_in : natural := g_nof_in;
@@ -140,22 +142,22 @@ begin
deint_in_val <= in_val;
u_deinterleave : entity work.common_deinterleave
- generic map (
- g_nof_out => c_nof_deint_out,
- g_dat_w => g_dat_w,
- g_block_size => g_deint_block_size,
- g_align_out => g_align_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => deint_in_dat_arr(i),
- in_val => deint_in_val,
-
- out_dat => deint_out_concat_dat_arr(i),
- out_val => deint_out_concat_val_arr(i)
- );
+ generic map (
+ g_nof_out => c_nof_deint_out,
+ g_dat_w => g_dat_w,
+ g_block_size => g_deint_block_size,
+ g_align_out => g_align_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => deint_in_dat_arr(i),
+ in_val => deint_in_val,
+
+ out_dat => deint_out_concat_dat_arr(i),
+ out_val => deint_out_concat_val_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -216,21 +218,21 @@ begin
-----------------------------------------------------------------------------
gen_inter: for i in 0 to c_nof_inter - 1 generate
u_interleave : entity work.common_interleave
- generic map (
- g_nof_in => c_nof_inter_in,
- g_dat_w => g_dat_w,
- g_block_size => g_inter_block_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => inter_in_concat_dat_arr(i),
- in_val => inter_in_concat_val_arr(i)(0), -- All input streams are valid at the same time.
-
- out_dat => inter_out_dat_arr(i),
- out_val => inter_out_val(i)
- );
+ generic map (
+ g_nof_in => c_nof_inter_in,
+ g_dat_w => g_dat_w,
+ g_block_size => g_inter_block_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => inter_in_concat_dat_arr(i),
+ in_val => inter_in_concat_val_arr(i)(0), -- All input streams are valid at the same time.
+
+ out_dat => inter_out_dat_arr(i),
+ out_val => inter_out_val(i)
+ );
out_dat( i * g_dat_w + g_dat_w - 1 downto i * g_dat_w) <= inter_out_dat_arr(i);
out_val(i) <= inter_out_val(i);
diff --git a/libraries/base/common/src/vhdl/common_reorder_symbol.vhd b/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
index a3bcf0c3c6..7af6fd441b 100644
--- a/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
@@ -20,71 +20,71 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
--- Purpose: Reorder symbols from input data stream
---
--- Description:
--- The in_data is a concatenation of g_nof_input symbols.
--- The out_data is a concatenation of g_nof_output symbols.
--- The symbols are each g_symbol_w bits wide.
--- Each input symbol can be directed to each output symbol by making the
--- appropriate settings via in_select.
--- Each stage is constructed of 2-input-2-output reorder cells.
--- Each stage can be pipelined or not dependent on g_pipeline_arr.
---
--- Two-input-two-output reorder:
--- The function func_reorder2() performs the mapping of two inputs data to
--- two output data. When select = '0' the pass on the own input else pass
--- on the other output. The short notation for func_reorder2() is X. The
--- scheme below shows the connections for X dependent on the two select bits.
---
--- input[1] ---- -\-- . /- -\/- output[1]
--- input[0] ---- . \- -/-- -/\- output[0]
--- select[1:0] "00" "01" "10" "11"
--- = 0 = 1 = 2 = 3
---
--- Note that when select is "00" or "11" the inputs are passed on or swapped,
--- else when select is "01" or "10" then one of the inputs is duplicated and
--- the other input is then not passed on.
---
--- The function func_common_reorder2_get_select() gets the select setting
--- from select_2arr for the reorder2 cell.
---
--- Example:
--- The example shows how the in_data and out_data are mapped on to a general
--- two-dimensional reorder array that maps c_N inputs to c_N outputs using
--- c_N stages.
---
--- select_2arr(I)(K)
--- reorder_2arr(I)(J) for c_N = 4
---
--- row J
--- 0 [4] . . . . . . [4] --> OPEN
--- X X --> these X will get optimized to pipeline
--- in_data [3] . . . . . . [3] out_data
--- X1 X4
--- [2] . . . . . . [2]
--- X2 X5
--- [1] . . . . . . [1]
--- X0 X3 --> the X# number is the index in in_select[]
--- [0] . . . . . . [0]
--- X X --> these X will get optimized to pipeline
--- 0 [-1] . . . . . . [-1] --> OPEN
--- -1 0 1 2 3 4
--- Stage I --> the stage number I is the index in g_pipeline_arr
---
--- Remarks:
--- . The input data maps to stage -1 and gets input pipelined to stage 0. The
--- output data maps to stage c_N.
--- . If g_nof_input /= g_nof_output then some in_select bits will be don't
--- care, because the in_select array is dimensioned for c_N.
--- . The implementation makes use of the fact that synthesis will optimize
--- away redundant logic. Therefore row -1 and row c_N can be used in
--- reorder_2arr whereby the X will reduce to wires. Similar the in_select
--- bits that are not used in subsequent stages will get removed from the
--- pipeline select_2arr.
+ -- Purpose: Reorder symbols from input data stream
+ --
+ -- Description:
+ -- The in_data is a concatenation of g_nof_input symbols.
+ -- The out_data is a concatenation of g_nof_output symbols.
+ -- The symbols are each g_symbol_w bits wide.
+ -- Each input symbol can be directed to each output symbol by making the
+ -- appropriate settings via in_select.
+ -- Each stage is constructed of 2-input-2-output reorder cells.
+ -- Each stage can be pipelined or not dependent on g_pipeline_arr.
+ --
+ -- Two-input-two-output reorder:
+ -- The function func_reorder2() performs the mapping of two inputs data to
+ -- two output data. When select = '0' the pass on the own input else pass
+ -- on the other output. The short notation for func_reorder2() is X. The
+ -- scheme below shows the connections for X dependent on the two select bits.
+ --
+ -- input[1] ---- -\-- . /- -\/- output[1]
+ -- input[0] ---- . \- -/-- -/\- output[0]
+ -- select[1:0] "00" "01" "10" "11"
+ -- = 0 = 1 = 2 = 3
+ --
+ -- Note that when select is "00" or "11" the inputs are passed on or swapped,
+ -- else when select is "01" or "10" then one of the inputs is duplicated and
+ -- the other input is then not passed on.
+ --
+ -- The function func_common_reorder2_get_select() gets the select setting
+ -- from select_2arr for the reorder2 cell.
+ --
+ -- Example:
+ -- The example shows how the in_data and out_data are mapped on to a general
+ -- two-dimensional reorder array that maps c_N inputs to c_N outputs using
+ -- c_N stages.
+ --
+ -- select_2arr(I)(K)
+ -- reorder_2arr(I)(J) for c_N = 4
+ --
+ -- row J
+ -- 0 [4] . . . . . . [4] --> OPEN
+ -- X X --> these X will get optimized to pipeline
+ -- in_data [3] . . . . . . [3] out_data
+ -- X1 X4
+ -- [2] . . . . . . [2]
+ -- X2 X5
+ -- [1] . . . . . . [1]
+ -- X0 X3 --> the X# number is the index in in_select[]
+ -- [0] . . . . . . [0]
+ -- X X --> these X will get optimized to pipeline
+ -- 0 [-1] . . . . . . [-1] --> OPEN
+ -- -1 0 1 2 3 4
+ -- Stage I --> the stage number I is the index in g_pipeline_arr
+ --
+ -- Remarks:
+ -- . The input data maps to stage -1 and gets input pipelined to stage 0. The
+ -- output data maps to stage c_N.
+ -- . If g_nof_input /= g_nof_output then some in_select bits will be don't
+ -- care, because the in_select array is dimensioned for c_N.
+ -- . The implementation makes use of the fact that synthesis will optimize
+ -- away redundant logic. Therefore row -1 and row c_N can be used in
+ -- reorder_2arr whereby the X will reduce to wires. Similar the in_select
+ -- bits that are not used in subsequent stages will get removed from the
+ -- pipeline select_2arr.
entity common_reorder_symbol is
generic (
@@ -152,17 +152,17 @@ begin
-- optional input pipelining
u_pipe_input : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline_arr(0),
- g_in_dat_w => g_symbol_w,
- g_out_dat_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => reorder_2arr(-1)(J),
- out_dat => reorder_2arr(0)(J)
- );
+ generic map (
+ g_pipeline => c_pipeline_arr(0),
+ g_in_dat_w => g_symbol_w,
+ g_out_dat_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => reorder_2arr(-1)(J),
+ out_dat => reorder_2arr(0)(J)
+ );
end generate;
-- in_select
@@ -172,16 +172,16 @@ begin
-- align in_select to the optional input pipelining
u_pipe_input : entity work.common_pipeline_natural
- generic map (
- g_pipeline => c_pipeline_arr(0),
- g_dat_w => g_select_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => select_2arr(-1)(K),
- out_dat => select_2arr(0)(K)
- );
+ generic map (
+ g_pipeline => c_pipeline_arr(0),
+ g_dat_w => g_select_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => select_2arr(-1)(K),
+ out_dat => select_2arr(0)(K)
+ );
end generate;
------------------------------------------------------------------------------
@@ -198,32 +198,32 @@ begin
-- optional pipelining per reorder stage
u_pipe_stage : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline_arr(I),
- g_in_dat_w => g_symbol_w,
- g_out_dat_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => nxt_reorder_2arr(I)(J),
- out_dat => reorder_2arr(I)(J)
- );
+ generic map (
+ g_pipeline => c_pipeline_arr(I),
+ g_in_dat_w => g_symbol_w,
+ g_out_dat_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => nxt_reorder_2arr(I)(J),
+ out_dat => reorder_2arr(I)(J)
+ );
end generate;
-- align in_select to the optional pipelining per reorder stage
gen_select : for K in 0 to g_nof_select - 1 generate
u_pipe_stage : entity work.common_pipeline_natural
- generic map (
- g_pipeline => c_pipeline_arr(I),
- g_dat_w => g_select_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => select_2arr(I - 1)(K),
- out_dat => select_2arr(I)(K)
- );
+ generic map (
+ g_pipeline => c_pipeline_arr(I),
+ g_dat_w => g_select_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => select_2arr(I - 1)(K),
+ out_dat => select_2arr(I)(K)
+ );
end generate;
end generate;
@@ -240,46 +240,46 @@ begin
------------------------------------------------------------------------------
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => out_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => out_sop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => out_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => out_eop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => out_eop
+ );
u_out_sync : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sync,
- out_dat => out_sync
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sync,
+ out_dat => out_sync
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_requantize.vhd b/libraries/base/common/src/vhdl/common_requantize.vhd
index e60f590d78..e801c6dc05 100644
--- a/libraries/base/common/src/vhdl/common_requantize.vhd
+++ b/libraries/base/common/src/vhdl/common_requantize.vhd
@@ -20,49 +20,49 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
--- Purpose: Requantize the input data to the output data width by removing
--- LSbits and/or MSbits
--- Description:
---
--- . in_dat --> remove LSbits --> rem_dat --> remove MSbits --> shift left by c_gain_w --> out_dat
---
--- . Remove LSBits by means of ROUND or TRUNCATE
--- . Remove LSBits when c_lsb_w>0
---
--- . Remove MSBits by means of CLIP or WRAP
--- . Remove MSbits when g_in_dat_w-c_lsb_w > g_out_dat_w:
--- in_dat <---------------------g_in_dat_w--------------------->
--- rem_dat <---------------------c_rem_dat_w-------><--c_lsb_w-->
--- res_dat <-------------g_out_dat_w-------><--c_lsb_w-->
---
--- . Extend MSbits when g_in_dat_w-c_lsb_w <= g_out_dat_w::
--- in_dat <-------------g_in_dat_w--------------------->
--- rem_dat <-------------c_rem_dat_w-------><--c_lsb_w-->
--- res_dat <---------------------g_out_dat_w-------><--c_lsb_w-->
---
--- . Shift left res_dat before resizing to out_dat'LENGTH, which is useful to keep the res_dat in the MSbits when out_dat'LENGTH > g_out_dat_w
--- gain_dat <-------g_out_dat_w-------><--c_gain_w-->
---
--- Remarks:
--- . It is not necessary to define g_msb_w, because the number of MSbits that
--- need to be removed (or extended) follows from the other widths.
+ -- Purpose: Requantize the input data to the output data width by removing
+ -- LSbits and/or MSbits
+ -- Description:
+ --
+ -- . in_dat --> remove LSbits --> rem_dat --> remove MSbits --> shift left by c_gain_w --> out_dat
+ --
+ -- . Remove LSBits by means of ROUND or TRUNCATE
+ -- . Remove LSBits when c_lsb_w>0
+ --
+ -- . Remove MSBits by means of CLIP or WRAP
+ -- . Remove MSbits when g_in_dat_w-c_lsb_w > g_out_dat_w:
+ -- in_dat <---------------------g_in_dat_w--------------------->
+ -- rem_dat <---------------------c_rem_dat_w-------><--c_lsb_w-->
+ -- res_dat <-------------g_out_dat_w-------><--c_lsb_w-->
+ --
+ -- . Extend MSbits when g_in_dat_w-c_lsb_w <= g_out_dat_w::
+ -- in_dat <-------------g_in_dat_w--------------------->
+ -- rem_dat <-------------c_rem_dat_w-------><--c_lsb_w-->
+ -- res_dat <---------------------g_out_dat_w-------><--c_lsb_w-->
+ --
+ -- . Shift left res_dat before resizing to out_dat'LENGTH, which is useful to keep the res_dat in the MSbits when out_dat'LENGTH > g_out_dat_w
+ -- gain_dat <-------g_out_dat_w-------><--c_gain_w-->
+ --
+ -- Remarks:
+ -- . It is not necessary to define g_msb_w, because the number of MSbits that
+ -- need to be removed (or extended) follows from the other widths.
entity common_requantize is
generic (
g_representation : string := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
g_lsb_w : integer := 4; -- when > 0, number of LSbits to remove from in_dat
- -- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
- -- when 0 then no effect
+ -- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
+ -- when 0 then no effect
g_lsb_round : boolean := true; -- when TRUE round else truncate the input LSbits
g_lsb_round_clip : boolean := false; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
g_lsb_round_even : boolean := true; -- when TRUE round half to even, else round half away from zero
g_msb_clip : boolean := true; -- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric : boolean := false; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
- -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
+ -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
g_gain_w : natural := 0; -- do not use, must be 0, use negative g_lsb_w instead
g_pipeline_remove_lsb : natural := 0; -- >= 0
g_pipeline_remove_msb : natural := 0; -- >= 0, use g_pipeline_remove_lsb=0 and g_pipeline_remove_msb=0 for combinatorial output
@@ -94,41 +94,41 @@ begin
-- Remove LSBits using ROUND or TRUNCATE
u_remove_lsb : entity common_lib.common_round
- generic map (
- g_representation => g_representation,
- g_round => g_lsb_round,
- g_round_clip => g_lsb_round_clip,
- g_round_even => g_lsb_round_even,
- g_pipeline_input => 0,
- g_pipeline_output => g_pipeline_remove_lsb,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_rem_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat(g_in_dat_w - 1 downto 0),
- out_dat => rem_dat
- );
+ generic map (
+ g_representation => g_representation,
+ g_round => g_lsb_round,
+ g_round_clip => g_lsb_round_clip,
+ g_round_even => g_lsb_round_even,
+ g_pipeline_input => 0,
+ g_pipeline_output => g_pipeline_remove_lsb,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_rem_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat(g_in_dat_w - 1 downto 0),
+ out_dat => rem_dat
+ );
-- Remove MSBits using CLIP or WRAP
u_remove_msb : entity common_lib.common_resize
- generic map (
- g_representation => g_representation,
- g_pipeline_input => 0,
- g_pipeline_output => g_pipeline_remove_msb,
- g_clip => g_msb_clip,
- g_clip_symmetric => g_msb_clip_symmetric,
- g_in_dat_w => c_rem_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => rem_dat,
- out_dat => res_dat,
- out_ovr => out_ovr
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline_input => 0,
+ g_pipeline_output => g_pipeline_remove_msb,
+ g_clip => g_msb_clip,
+ g_clip_symmetric => g_msb_clip_symmetric,
+ g_in_dat_w => c_rem_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => rem_dat,
+ out_dat => res_dat,
+ out_ovr => out_ovr
+ );
-- Output gain
gain_dat(g_out_dat_w + c_gain_w - 1 downto c_gain_w) <= res_dat;
diff --git a/libraries/base/common/src/vhdl/common_request.vhd b/libraries/base/common/src/vhdl/common_request.vhd
index 47506edcb2..bfd75dc50a 100644
--- a/libraries/base/common/src/vhdl/common_request.vhd
+++ b/libraries/base/common/src/vhdl/common_request.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_request is
port (
@@ -79,14 +79,14 @@ begin
in_req_evt <= in_req_reg and not in_req_prev;
u_protocol_act : entity work.common_switch
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- switch_high => in_req_evt,
- switch_low => out_req,
- out_level => req_pending
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ switch_high => in_req_evt,
+ switch_low => out_req,
+ out_level => req_pending
+ );
out_req <= req_pending and sync_reg;
nxt_out_req_evt <= out_req and not out_req_prev;
diff --git a/libraries/base/common/src/vhdl/common_resize.vhd b/libraries/base/common/src/vhdl/common_resize.vhd
index 04ae5e8e6d..0175000a2f 100644
--- a/libraries/base/common/src/vhdl/common_resize.vhd
+++ b/libraries/base/common/src/vhdl/common_resize.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use work.common_pkg.all;
entity common_resize is
generic (
g_representation : string := "SIGNED"; -- SIGNED or UNSIGNED resizing
g_clip : boolean := false; -- when TRUE clip input if it is outside the output range, else wrap
g_clip_symmetric : boolean := false; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
- -- for wrapping when g_clip=FALSE the g_clip_symmetric is ignored, so signed wrapping is done asymmetric
+ -- for wrapping when g_clip=FALSE the g_clip_symmetric is ignored, so signed wrapping is done asymmetric
g_pipeline_input : natural := 0; -- >= 0
g_pipeline_output : natural := 1; -- >= 0
g_in_dat_w : integer := 36;
@@ -65,18 +65,18 @@ architecture rtl of common_resize is
signal out_vec : std_logic_vector(g_out_dat_w downto 0);
begin
u_input_pipe : entity work.common_pipeline -- pipeline input
- generic map (
- g_representation => "SIGNED",
- g_pipeline => g_pipeline_input,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_in_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- out_dat => reg_dat
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => g_pipeline_input,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ out_dat => reg_dat
+ );
no_clip : if c_clip = false generate
-- Note that g_pipeline_input=0 AND g_clip=FALSE is equivalent to using RESIZE_SVEC or RESIZE_UVEC directly.
@@ -115,18 +115,18 @@ begin
res_vec <= res_ovr & res_dat;
u_output_pipe : entity work.common_pipeline -- pipeline output
- generic map (
- g_representation => "SIGNED",
- g_pipeline => g_pipeline_output,
- g_in_dat_w => g_out_dat_w + 1,
- g_out_dat_w => g_out_dat_w + 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => res_vec,
- out_dat => out_vec
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => g_pipeline_output,
+ g_in_dat_w => g_out_dat_w + 1,
+ g_out_dat_w => g_out_dat_w + 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => res_vec,
+ out_dat => out_vec
+ );
out_ovr <= out_vec(g_out_dat_w);
out_dat <= out_vec(g_out_dat_w - 1 downto 0);
diff --git a/libraries/base/common/src/vhdl/common_reverse_n_data.vhd b/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
index 783c41fe81..8f3ef2e35d 100644
--- a/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
+++ b/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
@@ -19,34 +19,34 @@
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-
--- Author:
--- . Eric Kooistra, 14 Feb 2023
--- Purpose:
--- . Reverse the order of time multiplexed, serial data per set of every
--- g_reverse_len data values in time.
--- Description:
--- . The implementation does:
--- serial in_data -->
--- parallel demux_data_vec -->
--- reversed parallel reverse_data_vec -->
--- serial out_data
--- . The first in_val after rst release is treated as start of the time
--- multiplexed sets of data.
--- . For example with g_reverse_len = 3, then input in_data 012_345_678
--- becomes 210_543_876 output out_data.
--- . If in_eop is used to mark the end of in_data blocks, then the in_data
--- blocks size should be an integer multiple of g_reverse_len. If after rst
--- release, the in_val is always marking all in_data block data, then it is
--- fine to leave in_eop = '0', so not connected.
--- Remark:
--- . Typically g_reverse_len should not be too large (~< 4), because then the
--- implementation takes relatively too much logic.
--- . This common_reverse_n_data.vhd is used in dp_reverse_n.vhd and verified
--- in tb_dp_reverse_n.vhd.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+
+ -- Author:
+ -- . Eric Kooistra, 14 Feb 2023
+ -- Purpose:
+ -- . Reverse the order of time multiplexed, serial data per set of every
+ -- g_reverse_len data values in time.
+ -- Description:
+ -- . The implementation does:
+ -- serial in_data -->
+ -- parallel demux_data_vec -->
+ -- reversed parallel reverse_data_vec -->
+ -- serial out_data
+ -- . The first in_val after rst release is treated as start of the time
+ -- multiplexed sets of data.
+ -- . For example with g_reverse_len = 3, then input in_data 012_345_678
+ -- becomes 210_543_876 output out_data.
+ -- . If in_eop is used to mark the end of in_data blocks, then the in_data
+ -- blocks size should be an integer multiple of g_reverse_len. If after rst
+ -- release, the in_val is always marking all in_data block data, then it is
+ -- fine to leave in_eop = '0', so not connected.
+ -- Remark:
+ -- . Typically g_reverse_len should not be too large (~< 4), because then the
+ -- implementation takes relatively too much logic.
+ -- . This common_reverse_n_data.vhd is used in dp_reverse_n.vhd and verified
+ -- in tb_dp_reverse_n.vhd.
entity common_reverse_n_data is
generic (
@@ -72,22 +72,22 @@ end common_reverse_n_data;
architecture str of common_reverse_n_data is
constant c_pipeline_total : natural := g_pipeline_demux_in + g_pipeline_demux_out +
- g_reverse_len - 1 +
- g_pipeline_mux_in + g_pipeline_mux_out;
+ g_reverse_len - 1 +
+ g_pipeline_mux_in + g_pipeline_mux_out;
- constant c_sel_w : natural := ceil_log2(g_reverse_len);
+ constant c_sel_w : natural := ceil_log2(g_reverse_len);
- signal in_sel : std_logic_vector(c_sel_w - 1 downto 0);
- signal nxt_in_sel : std_logic_vector(c_sel_w - 1 downto 0);
+ signal in_sel : std_logic_vector(c_sel_w - 1 downto 0);
+ signal nxt_in_sel : std_logic_vector(c_sel_w - 1 downto 0);
- signal demux_data : std_logic_vector(g_data_w - 1 downto 0);
- signal demux_data_vec : std_logic_vector(g_reverse_len * g_data_w - 1 downto 0);
- signal demux_val_vec : std_logic_vector(g_reverse_len - 1 downto 0);
+ signal demux_data : std_logic_vector(g_data_w - 1 downto 0);
+ signal demux_data_vec : std_logic_vector(g_reverse_len * g_data_w - 1 downto 0);
+ signal demux_val_vec : std_logic_vector(g_reverse_len - 1 downto 0);
- signal reverse_sel : std_logic_vector(c_sel_w - 1 downto 0);
- signal reverse_data_vec : std_logic_vector(g_reverse_len * g_data_w - 1 downto 0);
- signal reverse_val_vec : std_logic_vector(g_reverse_len - 1 downto 0);
- signal reverse_val : std_logic;
+ signal reverse_sel : std_logic_vector(c_sel_w - 1 downto 0);
+ signal reverse_data_vec : std_logic_vector(g_reverse_len * g_data_w - 1 downto 0);
+ signal reverse_val_vec : std_logic_vector(g_reverse_len - 1 downto 0);
+ signal reverse_val : std_logic;
begin
p_clk : process(rst, clk)
begin
@@ -119,23 +119,23 @@ begin
end process;
u_common_demultiplexer : entity work.common_demultiplexer
- generic map (
- g_pipeline_in => g_pipeline_demux_in,
- g_pipeline_out => g_pipeline_demux_out,
- g_nof_out => g_reverse_len,
- g_dat_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => in_data,
- in_val => in_val,
-
- out_sel => in_sel,
- out_dat => demux_data_vec,
- out_val => demux_val_vec
- );
+ generic map (
+ g_pipeline_in => g_pipeline_demux_in,
+ g_pipeline_out => g_pipeline_demux_out,
+ g_nof_out => g_reverse_len,
+ g_dat_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_data,
+ in_val => in_val,
+
+ out_sel => in_sel,
+ out_dat => demux_data_vec,
+ out_val => demux_val_vec
+ );
-- All g_reverse_len parts in demux_data_vec carry the same data, the
-- demux_val_vec determines for which demux stream it is. Use demux_data
@@ -185,62 +185,62 @@ begin
--
gen_reverse : for I in 0 to g_reverse_len - 1 generate
u_reverse_data : entity work.common_pipeline
+ generic map (
+ g_pipeline => 2 * I,
+ g_in_dat_w => g_data_w,
+ g_out_dat_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => demux_data_vec((g_reverse_len - 1 - I + 1) * g_data_w - 1 downto (g_reverse_len - 1 - I) * g_data_w),
+ out_dat => reverse_data_vec((I + 1) * g_data_w - 1 downto I * g_data_w)
+ );
+
+ u_reverse_val : entity work.common_pipeline_sl
+ generic map (
+ g_pipeline => 2 * I
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => demux_val_vec(g_reverse_len - 1 - I),
+ out_dat => reverse_val_vec(I)
+ );
+ end generate;
+
+ reverse_val <= vector_or(reverse_val_vec);
+
+ -- pipeline in_sel to align reverse_sel to reverse_data_vec and reverse_val_vec
+ u_pipe_sel : entity work.common_pipeline
generic map (
- g_pipeline => 2 * I,
- g_in_dat_w => g_data_w,
- g_out_dat_w => g_data_w
+ g_pipeline => g_pipeline_demux_in + g_pipeline_demux_out + g_reverse_len - 1,
+ g_in_dat_w => c_sel_w,
+ g_out_dat_w => c_sel_w
)
port map (
rst => rst,
clk => clk,
- in_dat => demux_data_vec((g_reverse_len - 1 - I + 1) * g_data_w - 1 downto (g_reverse_len - 1 - I) * g_data_w),
- out_dat => reverse_data_vec((I + 1) * g_data_w - 1 downto I * g_data_w)
+ in_dat => in_sel,
+ out_dat => reverse_sel
);
- u_reverse_val : entity work.common_pipeline_sl
+ u_common_multiplexer : entity work.common_multiplexer
generic map (
- g_pipeline => 2 * I
+ g_pipeline_in => g_pipeline_mux_in,
+ g_pipeline_out => g_pipeline_mux_out,
+ g_nof_in => g_reverse_len,
+ g_dat_w => g_data_w
)
port map (
- rst => rst,
- clk => clk,
- in_dat => demux_val_vec(g_reverse_len - 1 - I),
- out_dat => reverse_val_vec(I)
- );
- end generate;
-
- reverse_val <= vector_or(reverse_val_vec);
+ rst => rst,
+ clk => clk,
- -- pipeline in_sel to align reverse_sel to reverse_data_vec and reverse_val_vec
- u_pipe_sel : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline_demux_in + g_pipeline_demux_out + g_reverse_len - 1,
- g_in_dat_w => c_sel_w,
- g_out_dat_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sel,
- out_dat => reverse_sel
- );
+ in_sel => reverse_sel,
+ in_dat => reverse_data_vec,
+ in_val => reverse_val,
- u_common_multiplexer : entity work.common_multiplexer
- generic map (
- g_pipeline_in => g_pipeline_mux_in,
- g_pipeline_out => g_pipeline_mux_out,
- g_nof_in => g_reverse_len,
- g_dat_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_sel => reverse_sel,
- in_dat => reverse_data_vec,
- in_val => reverse_val,
-
- out_dat => out_data,
- out_val => out_val -- = in_val delayed by c_pipeline_total
- );
+ out_dat => out_data,
+ out_val => out_val -- = in_val delayed by c_pipeline_total
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_rl_decrease.vhd b/libraries/base/common/src/vhdl/common_rl_decrease.vhd
index 41fa78b559..d1baa56997 100644
--- a/libraries/base/common/src/vhdl/common_rl_decrease.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_decrease.vhd
@@ -23,13 +23,13 @@
-- >>> Ported from UniBoard dp_latency_adapter for fixed RL 0 --> 1
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
--- Purpose: Adapt from ready latency 1 to 0 to make a look ahead FIFO
--- Description: -
--- Remark:
--- . A show ahead FIFO with RL=0 does not need a rd_emp output signal, because
--- with RL=0 the rd_val='0' when it is empty (so emp <= NOT rd_val).
+ -- Purpose: Adapt from ready latency 1 to 0 to make a look ahead FIFO
+ -- Description: -
+ -- Remark:
+ -- . A show ahead FIFO with RL=0 does not need a rd_emp output signal, because
+ -- with RL=0 the rd_val='0' when it is empty (so emp <= NOT rd_val).
entity common_rl_decrease is
generic (
diff --git a/libraries/base/common/src/vhdl/common_rl_increase.vhd b/libraries/base/common/src/vhdl/common_rl_increase.vhd
index 43f002b9f5..c40e345920 100644
--- a/libraries/base/common/src/vhdl/common_rl_increase.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_increase.vhd
@@ -20,21 +20,21 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
--- >>> Ported from UniBoard dp_latency_increase for fixed RL 0 --> 1
---
--- Purpose:
--- Increase the ready latency from RL=0 to RL=1.
--- Description:
--- Increasing the RL makes a look ahead FIFO appear as a normal FIFO.
--- Remark:
--- . The data are passed on as wires when g_hold_dat_en=FALSE. When TRUE then
--- the data is held until the next active src_out_val to ease applications
--- that still depend on the src_out_dat value after src_out_val has gone low.
--- With RL=0 at the snk_in a new valid snk_in_dat can arrive before it is
--- acknowledged by the registered src_in_ready.
--- . The src_out_val control is internally AND with the snk_out_ready.
+ -- >>> Ported from UniBoard dp_latency_increase for fixed RL 0 --> 1
+ --
+ -- Purpose:
+ -- Increase the ready latency from RL=0 to RL=1.
+ -- Description:
+ -- Increasing the RL makes a look ahead FIFO appear as a normal FIFO.
+ -- Remark:
+ -- . The data are passed on as wires when g_hold_dat_en=FALSE. When TRUE then
+ -- the data is held until the next active src_out_val to ease applications
+ -- that still depend on the src_out_dat value after src_out_val has gone low.
+ -- With RL=0 at the snk_in a new valid snk_in_dat can arrive before it is
+ -- acknowledged by the registered src_in_ready.
+ -- . The src_out_val control is internally AND with the snk_out_ready.
entity common_rl_increase is
generic (
diff --git a/libraries/base/common/src/vhdl/common_rl_register.vhd b/libraries/base/common/src/vhdl/common_rl_register.vhd
index 1a4f287ddc..4fba6986eb 100644
--- a/libraries/base/common/src/vhdl/common_rl_register.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_register.vhd
@@ -23,19 +23,19 @@
-- >>> Ported from UniBoard dp_pipeline_ready for fixed RL 1 --> 0 --> 1
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
--- Purpose: Register both the data and the ready by going from RL=1 to 0 to 1.
--- Description: -
--- Remark:
--- . To only register the data dp_pipeline is suited. To register the ready
--- this ported dp_pipeline_ready is needed. Pipelining the ready also
--- pipelines the data, because the RL goes from 1 --> 0 --> 1.
--- . Conform the RL specification it is correct to use g_hold_dat_en = FALSE.
--- However use g_hold_dat_en = TRUE if functionaly the application requires
--- src_out_dat to hold the last valid value when src_out_val goes low.
--- Otherwise a new valid snk_in_dat that arrives with RL = 0 will already
--- set src_out_dat before src_out_val becomes valid due to src_in_ready.
+ -- Purpose: Register both the data and the ready by going from RL=1 to 0 to 1.
+ -- Description: -
+ -- Remark:
+ -- . To only register the data dp_pipeline is suited. To register the ready
+ -- this ported dp_pipeline_ready is needed. Pipelining the ready also
+ -- pipelines the data, because the RL goes from 1 --> 0 --> 1.
+ -- . Conform the RL specification it is correct to use g_hold_dat_en = FALSE.
+ -- However use g_hold_dat_en = TRUE if functionaly the application requires
+ -- src_out_dat to hold the last valid value when src_out_val goes low.
+ -- Otherwise a new valid snk_in_dat that arrives with RL = 0 will already
+ -- set src_out_dat before src_out_val becomes valid due to src_in_ready.
entity common_rl_register is
generic (
@@ -63,39 +63,39 @@ architecture str of common_rl_register is
signal reg_val : std_logic;
begin
u_rl0 : entity common_lib.common_rl_decrease
- generic map (
- g_adapt => g_adapt,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink: RL = 1
- snk_out_ready => snk_out_ready,
- snk_in_dat => snk_in_dat,
- snk_in_val => snk_in_val,
- -- ST source: RL = 0
- src_in_ready => reg_ready,
- src_out_dat => reg_dat,
- src_out_val => reg_val
- );
+ generic map (
+ g_adapt => g_adapt,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink: RL = 1
+ snk_out_ready => snk_out_ready,
+ snk_in_dat => snk_in_dat,
+ snk_in_val => snk_in_val,
+ -- ST source: RL = 0
+ src_in_ready => reg_ready,
+ src_out_dat => reg_dat,
+ src_out_val => reg_val
+ );
u_rl1 : entity common_lib.common_rl_increase
- generic map (
- g_adapt => g_adapt,
- g_hold_dat_en => g_hold_dat_en,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- Sink
- snk_out_ready => reg_ready, -- sink RL = 0
- snk_in_dat => reg_dat,
- snk_in_val => reg_val,
- -- Source
- src_in_ready => src_in_ready, -- source RL = 1
- src_out_dat => src_out_dat,
- src_out_val => src_out_val
- );
+ generic map (
+ g_adapt => g_adapt,
+ g_hold_dat_en => g_hold_dat_en,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Sink
+ snk_out_ready => reg_ready, -- sink RL = 0
+ snk_in_dat => reg_dat,
+ snk_in_val => reg_val,
+ -- Source
+ src_in_ready => src_in_ready, -- source RL = 1
+ src_out_dat => src_out_dat,
+ src_out_val => src_out_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_rom.vhd b/libraries/base/common/src/vhdl/common_rom.vhd
index 0637ea290b..12b37088cf 100644
--- a/libraries/base/common/src/vhdl/common_rom.vhd
+++ b/libraries/base/common/src/vhdl/common_rom.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_rom is
generic (
@@ -46,21 +46,21 @@ begin
-- Only use the read port
u_r_w : entity work.common_ram_r_w
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- wr_en => '0',
- --wr_adr => (OTHERS=>'0'),
- --wr_dat => (OTHERS=>'0'),
- rd_en => rd_en,
- rd_adr => rd_adr,
- rd_dat => rd_dat,
- rd_val => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ wr_en => '0',
+ --wr_adr => (OTHERS=>'0'),
+ --wr_dat => (OTHERS=>'0'),
+ rd_en => rd_en,
+ rd_adr => rd_adr,
+ rd_dat => rd_dat,
+ rd_val => rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_round.vhd b/libraries/base/common/src/vhdl/common_round.vhd
index 6f7aae19d2..5f1367dbf3 100644
--- a/libraries/base/common/src/vhdl/common_round.vhd
+++ b/libraries/base/common/src/vhdl/common_round.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use work.common_pkg.all;
entity common_round is
--
@@ -62,18 +62,18 @@ architecture rtl of common_round is
signal res_dat : std_logic_vector(out_dat'range);
begin
u_input_pipe : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline_input,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_in_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- out_dat => reg_dat
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline_input,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ out_dat => reg_dat
+ );
-- Increase to out_dat width
no_s : if c_remove_w <= 0 and g_representation = "SIGNED" generate
@@ -100,16 +100,16 @@ begin
end generate;
u_output_pipe : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline_output,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => res_dat,
- out_dat => out_dat
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline_output,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => res_dat,
+ out_dat => out_dat
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_select_m_symbols.vhd b/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
index 9c5981c47a..662040aba7 100644
--- a/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
+++ b/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
@@ -20,24 +20,24 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_components_pkg.all;
-
--- Purpose: Select M symbols from an input data stream with N symbols
--- Description:
--- The in_data is a concatenation of N=g_nof_input, that are each g_symbol_w
--- bits wide. The out_data is a concatenation of M=g_nof_output, that are
--- each g_symbol_w bits wide. The input symbol with index set by in_select m
--- is passed on to the output symbol m in out_data.
--- Remarks:
--- . If the in_select index is too large for g_nof_input range then the output
--- passes on symbol 0.
--- . This common_select_m_symbols is functionally equivalent to
--- common_reorder_symbol. The advantage of common_select_m_symbols is that
--- the definition of in_select is more intinutive. The advantage of
--- common_reorder_symbol may be that the structure of reorder2 cells with
--- minimal line crossings allow achieving a higher f_max.
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_components_pkg.all;
+
+ -- Purpose: Select M symbols from an input data stream with N symbols
+ -- Description:
+ -- The in_data is a concatenation of N=g_nof_input, that are each g_symbol_w
+ -- bits wide. The out_data is a concatenation of M=g_nof_output, that are
+ -- each g_symbol_w bits wide. The input symbol with index set by in_select m
+ -- is passed on to the output symbol m in out_data.
+ -- Remarks:
+ -- . If the in_select index is too large for g_nof_input range then the output
+ -- passes on symbol 0.
+ -- . This common_select_m_symbols is functionally equivalent to
+ -- common_reorder_symbol. The advantage of common_select_m_symbols is that
+ -- the definition of in_select is more intinutive. The advantage of
+ -- common_reorder_symbol may be that the structure of reorder2 cells with
+ -- minimal line crossings allow achieving a higher f_max.
entity common_select_m_symbols is
generic (
@@ -108,32 +108,32 @@ begin
in_select_arr(I) <= in_select_reg((I + 1) * c_sel_w - 1 downto I * c_sel_w);
u_sel : entity work.common_select_symbol
- generic map (
- g_pipeline_in => g_pipeline_in_m,
- g_pipeline_out => g_pipeline_out,
- g_nof_symbols => g_nof_input,
- g_symbol_w => g_symbol_w,
- g_sel_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => in_data_reg,
- in_val => in_val_reg,
- in_sop => in_sop_reg,
- in_eop => in_eop_reg,
- in_sync => in_sync_reg,
-
- in_sel => in_select_arr(I),
- out_sel => OPEN,
-
- out_symbol => out_data_arr(I),
- out_val => out_val_arr(I), -- pipelined in_val
- out_sop => out_sop_arr(I), -- pipelined in_sop
- out_eop => out_eop_arr(I), -- pipelined in_eop
- out_sync => out_sync_arr(I) -- pipelined in_sync
- );
+ generic map (
+ g_pipeline_in => g_pipeline_in_m,
+ g_pipeline_out => g_pipeline_out,
+ g_nof_symbols => g_nof_input,
+ g_symbol_w => g_symbol_w,
+ g_sel_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => in_data_reg,
+ in_val => in_val_reg,
+ in_sop => in_sop_reg,
+ in_eop => in_eop_reg,
+ in_sync => in_sync_reg,
+
+ in_sel => in_select_arr(I),
+ out_sel => OPEN,
+
+ out_symbol => out_data_arr(I),
+ out_val => out_val_arr(I), -- pipelined in_val
+ out_sop => out_sop_arr(I), -- pipelined in_sop
+ out_eop => out_eop_arr(I), -- pipelined in_eop
+ out_sync => out_sync_arr(I) -- pipelined in_sync
+ );
out_data((I + 1) * g_symbol_w - 1 downto I * g_symbol_w) <= out_data_arr(I);
end generate;
diff --git a/libraries/base/common/src/vhdl/common_select_symbol.vhd b/libraries/base/common/src/vhdl/common_select_symbol.vhd
index 117fb8c133..e08fc5444e 100644
--- a/libraries/base/common/src/vhdl/common_select_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_select_symbol.vhd
@@ -20,18 +20,18 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_components_pkg.all;
--- Purpose: Select symbol from input data stream
--- Description:
--- The in_data is a concatenation of g_nof_symbols, that are each g_symbol_w
--- bits wide. The symbol with index set by in_sel is passed on to the output
--- out_dat.
--- Remarks:
--- . If the in_select index is too large for g_nof_input range then the output
--- passes on symbol 0.
+ -- Purpose: Select symbol from input data stream
+ -- Description:
+ -- The in_data is a concatenation of g_nof_symbols, that are each g_symbol_w
+ -- bits wide. The symbol with index set by in_sel is passed on to the output
+ -- out_dat.
+ -- Remarks:
+ -- . If the in_select index is too large for g_nof_input range then the output
+ -- passes on symbol 0.
entity common_select_symbol is
generic (
diff --git a/libraries/base/common/src/vhdl/common_shiftram.vhd b/libraries/base/common/src/vhdl/common_shiftram.vhd
index 382a87a482..80b7053146 100644
--- a/libraries/base/common/src/vhdl/common_shiftram.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftram.vhd
@@ -50,11 +50,11 @@
-- r0..r2 = register stages.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_shiftram is
generic (
@@ -85,8 +85,9 @@ architecture rtl of common_shiftram is
constant c_ram_data_w : natural := g_data_w;
constant c_ram_nof_dat : natural := g_nof_words;
constant c_ram_init_sl : std_logic := '0';
- constant c_ram : t_c_mem := (c_ram_rl, c_ram_addr_w, c_ram_data_w,
- c_ram_nof_dat, c_ram_init_sl);
+ constant c_ram : t_c_mem := (
+ c_ram_rl, c_ram_addr_w, c_ram_data_w,
+ c_ram_nof_dat, c_ram_init_sl);
signal ram_data_out : std_logic_vector(g_data_w - 1 downto 0);
signal ram_data_out_val : std_logic;
@@ -100,11 +101,12 @@ architecture rtl of common_shiftram is
ram_wr_shift_incr : boolean;
end record;
- constant c_reg_0_defaults : t_reg_0 := ( (others => '0'),
- (others => '0'),
- '0',
- (others => '0'),
- false);
+ constant c_reg_0_defaults : t_reg_0 := (
+ (others => '0'),
+ (others => '0'),
+ '0',
+ (others => '0'),
+ false);
signal r0, nxt_r0 : t_reg_0 := c_reg_0_defaults;
@@ -115,9 +117,10 @@ architecture rtl of common_shiftram is
ram_rd_shift : std_logic_vector(c_ram_addr_w - 1 downto 0);
end record;
- constant c_reg_1_defaults : t_reg_1 := ( (others => '0'),
- '0',
- (others => '0'));
+ constant c_reg_1_defaults : t_reg_1 := (
+ (others => '0'),
+ '0',
+ (others => '0'));
signal r1, nxt_r1 : t_reg_1 := c_reg_1_defaults;
@@ -137,9 +140,10 @@ architecture rtl of common_shiftram is
data_out_val : std_logic;
end record;
- constant c_reg_3_defaults : t_reg_3 := ( (others => '0'),
- (others => '0'),
- '0');
+ constant c_reg_3_defaults : t_reg_3 := (
+ (others => '0'),
+ (others => '0'),
+ '0');
signal r3, nxt_r3 : t_reg_3 := c_reg_3_defaults;
begin
@@ -159,7 +163,7 @@ begin
if data_in_val = '1' then
-- Limit max shift to g_nof_words-2
- v_data_in_shift := data_in_shift;
+ v_data_in_shift := data_in_shift;
if v_data_in_shift = TO_UVEC(g_nof_words - 1, c_ram_addr_w) then
v_data_in_shift := TO_UVEC(g_nof_words - 2, c_ram_addr_w);
@@ -250,30 +254,30 @@ begin
nxt_r2 <= v;
end process;
--- data_out_shift <= r2.data_out_shift;
+ -- data_out_shift <= r2.data_out_shift;
-----------------------------------------------------------------------------
-- RAM
-----------------------------------------------------------------------------
u_common_ram_r_w: entity common_lib.common_ram_r_w
- generic map (
- g_technology => g_technology,
- g_ram => c_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => false
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- wr_en => r0.ram_wr_en,
- wr_adr => r0.ram_wr_addr,
- wr_dat => r0.ram_wr_data,
- rd_en => r1.ram_rd_en,
- rd_adr => r1.ram_rd_addr,
- rd_dat => ram_data_out,
- rd_val => ram_data_out_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ wr_en => r0.ram_wr_en,
+ wr_adr => r0.ram_wr_addr,
+ wr_dat => r0.ram_wr_data,
+ rd_en => r1.ram_rd_en,
+ rd_adr => r1.ram_rd_addr,
+ rd_dat => ram_data_out,
+ rd_val => ram_data_out_val
+ );
gen_outputs: if g_output_invalid_during_shift_incr = false generate
data_out_shift <= r2.data_out_shift;
diff --git a/libraries/base/common/src/vhdl/common_shiftreg.vhd b/libraries/base/common/src/vhdl/common_shiftreg.vhd
index e18a57174a..1d4da55e9e 100644
--- a/libraries/base/common/src/vhdl/common_shiftreg.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftreg.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-
--- Purpose: Shift register when in_val is active with optional flush at in_eop.
--- Description:
--- The shift register contains g_nof_dat-1 shift registers, so it directly
--- combinatorially includes in_dat. The shift register shifts when in_val
--- is active.
--- If g_flush_en is FALSE then the shift register is always filled when valid
--- data comes out. Hence the out_dat then shifts out with in_val.
--- If g_flush_en is TRUE then the shift register flushes itself when in_eop
--- = '1'. The in_eop marks the last valid in_dat of a block.
--- The out_cnt counts the number of in_val modulo g_nof_dat and restarts at
--- the in_eop. The in_cnt starts at 1, in this way the out_cnt=0 marks the
--- out_data_vec that contain a complete set of g_nof_dat number of new
--- out_dat.
--- Remarks:
--- . Optionally the output can be pipelined via g_pipeline.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+
+ -- Purpose: Shift register when in_val is active with optional flush at in_eop.
+ -- Description:
+ -- The shift register contains g_nof_dat-1 shift registers, so it directly
+ -- combinatorially includes in_dat. The shift register shifts when in_val
+ -- is active.
+ -- If g_flush_en is FALSE then the shift register is always filled when valid
+ -- data comes out. Hence the out_dat then shifts out with in_val.
+ -- If g_flush_en is TRUE then the shift register flushes itself when in_eop
+ -- = '1'. The in_eop marks the last valid in_dat of a block.
+ -- The out_cnt counts the number of in_val modulo g_nof_dat and restarts at
+ -- the in_eop. The in_cnt starts at 1, in this way the out_cnt=0 marks the
+ -- out_data_vec that contain a complete set of g_nof_dat number of new
+ -- out_dat.
+ -- Remarks:
+ -- . Optionally the output can be pipelined via g_pipeline.
entity common_shiftreg is
generic (
@@ -134,16 +134,16 @@ begin
-- Shift control
u_flush : entity work.common_switch
- generic map (
- g_rst_level => '0'
- )
- port map (
- clk => clk,
- rst => rst,
- switch_high => in_eop,
- switch_low => eop_arr(0),
- out_level => flush
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => in_eop,
+ switch_low => eop_arr(0),
+ out_level => flush
+ );
shift_en <= in_val or flush when g_flush_en = true else in_val or out_req;
@@ -186,67 +186,67 @@ begin
out_eop <= i_out_eop_vec(0);
u_out_data_vec : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_dat * g_dat_w,
- g_out_dat_w => g_nof_dat * g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => data_vec,
- out_dat => i_out_data_vec
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_dat * g_dat_w,
+ g_out_dat_w => g_nof_dat * g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => data_vec,
+ out_dat => i_out_data_vec
+ );
u_out_val_vec : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_dat,
- g_out_dat_w => g_nof_dat
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => val_vec,
- out_dat => i_out_val_vec
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_dat,
+ g_out_dat_w => g_nof_dat
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => val_vec,
+ out_dat => i_out_val_vec
+ );
u_out_sop_vec : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_dat,
- g_out_dat_w => g_nof_dat
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sop_vec,
- out_dat => i_out_sop_vec
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_dat,
+ g_out_dat_w => g_nof_dat
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sop_vec,
+ out_dat => i_out_sop_vec
+ );
u_out_eop_vec : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_dat,
- g_out_dat_w => g_nof_dat
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => eop_vec,
- out_dat => i_out_eop_vec
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_dat,
+ g_out_dat_w => g_nof_dat
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => eop_vec,
+ out_dat => i_out_eop_vec
+ );
u_out_cnt : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => c_cnt_w,
- g_out_dat_w => c_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_cnt,
- out_dat => out_cnt
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => c_cnt_w,
+ g_out_dat_w => c_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_cnt,
+ out_dat => out_cnt
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd b/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
index e5a3137af0..1f120a8ad8 100644
--- a/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
@@ -20,18 +20,18 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
--- Purpose: Per symbol shift register of the input data stream
--- Description:
--- The in_data is a concatenation of g_nof_symbols, that are each g_symbol_w
--- bits wide. The g_nof_symbols in the in_data slv can be shifted
--- individualy as set by g_shiftline_arr(g_nof_symbols-1:0). The output
--- control signals val, sop and eop are also shifted per symbol.
--- Remarks:
--- . For the behaviour of the actual shift register see the desciption of
--- common_shiftreg.
+ -- Purpose: Per symbol shift register of the input data stream
+ -- Description:
+ -- The in_data is a concatenation of g_nof_symbols, that are each g_symbol_w
+ -- bits wide. The g_nof_symbols in the in_data slv can be shifted
+ -- individualy as set by g_shiftline_arr(g_nof_symbols-1:0). The output
+ -- control signals val, sop and eop are also shifted per symbol.
+ -- Remarks:
+ -- . For the behaviour of the actual shift register see the desciption of
+ -- common_shiftreg.
entity common_shiftreg_symbol is
generic (
@@ -69,26 +69,26 @@ begin
-- pipeline per symbol
u_shiftreg : entity work.common_shiftreg
- generic map (
- g_pipeline => g_pipeline,
- g_flush_en => g_flush_en,
- g_nof_dat => g_shiftline_arr(I),
- g_dat_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline => g_pipeline,
+ g_flush_en => g_flush_en,
+ g_nof_dat => g_shiftline_arr(I),
+ g_dat_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_dat => in_dat_arr(I),
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
+ in_dat => in_dat_arr(I),
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
- out_dat => out_dat_arr(I),
- out_val => out_val_arr(I),
- out_sop => out_sop_arr(I),
- out_eop => out_eop_arr(I)
- );
+ out_dat => out_dat_arr(I),
+ out_val => out_val_arr(I),
+ out_sop => out_sop_arr(I),
+ out_eop => out_eop_arr(I)
+ );
-- map arr to output vector
out_data((I + 1) * g_symbol_w - 1 downto I * g_symbol_w) <= out_dat_arr(I);
diff --git a/libraries/base/common/src/vhdl/common_spulse.vhd b/libraries/base/common/src/vhdl/common_spulse.vhd
index d24c3034ff..58f8568815 100644
--- a/libraries/base/common/src/vhdl/common_spulse.vhd
+++ b/libraries/base/common/src/vhdl/common_spulse.vhd
@@ -31,8 +31,8 @@
-- the out_clk rate.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_spulse is
generic (
@@ -61,14 +61,14 @@ architecture rtl of common_spulse is
signal nxt_out_pulse : std_logic;
begin
capture_in_pulse : entity work.common_switch
- port map (
- clk => in_clk,
- clken => in_clken,
- rst => in_rst,
- switch_high => in_pulse,
- switch_low => pulse_ack,
- out_level => in_level
- );
+ port map (
+ clk => in_clk,
+ clken => in_clken,
+ rst => in_rst,
+ switch_high => in_pulse,
+ switch_low => pulse_ack,
+ out_level => in_level
+ );
in_busy <= in_level or pulse_ack;
diff --git a/libraries/base/common/src/vhdl/common_stable_delayed.vhd b/libraries/base/common/src/vhdl/common_stable_delayed.vhd
index e9d5ae3197..6c0eba02a2 100644
--- a/libraries/base/common/src/vhdl/common_stable_delayed.vhd
+++ b/libraries/base/common/src/vhdl/common_stable_delayed.vhd
@@ -20,24 +20,24 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
--- Purpose:
--- Output active r_in if it is still active after some delay.
--- Description:
--- This function can be used to filter out temporary toggling in r_in. The
--- r_stable only becomes active after r_in has remained active for
--- 2**g_delayed_w - 2**g_delayed_lo clk cycles. The r_stable always goes
--- inactive when r_in is inactive.
--- The active level can be set with g_active_level to '1' or '0'.
--- Remarks:
--- . Verified with tb_lvdsh_dd_phs4.vhd, because there this was used first.
--- . Instead of the combination of g_delayed_w and g_delayed_lo a single
--- g_delayed NATURAL could have been used to exactly specify the delay.
--- However then delays larger than 2**31 would be complicated due to the
--- limited 31 bit range of a NATURAL in VHDL.
+ -- Purpose:
+ -- Output active r_in if it is still active after some delay.
+ -- Description:
+ -- This function can be used to filter out temporary toggling in r_in. The
+ -- r_stable only becomes active after r_in has remained active for
+ -- 2**g_delayed_w - 2**g_delayed_lo clk cycles. The r_stable always goes
+ -- inactive when r_in is inactive.
+ -- The active level can be set with g_active_level to '1' or '0'.
+ -- Remarks:
+ -- . Verified with tb_lvdsh_dd_phs4.vhd, because there this was used first.
+ -- . Instead of the combination of g_delayed_w and g_delayed_lo a single
+ -- g_delayed NATURAL could have been used to exactly specify the delay.
+ -- However then delays larger than 2**31 would be complicated due to the
+ -- limited 31 bit range of a NATURAL in VHDL.
entity common_stable_delayed is
generic (
@@ -80,14 +80,14 @@ begin
end process;
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_delayed_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => g_delayed_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_stable_monitor.vhd b/libraries/base/common/src/vhdl/common_stable_monitor.vhd
index fe41dae0f8..782bdd7075 100644
--- a/libraries/base/common/src/vhdl/common_stable_monitor.vhd
+++ b/libraries/base/common/src/vhdl/common_stable_monitor.vhd
@@ -20,17 +20,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
--- Purpose: Monitor whether r_in did not go low since the previous ack
--- Description:
--- When r_in = '0' then r_stable = '0'. The r_stable is '1' if r_in = '1' and
--- remains '1'. The r_stable measurement interval restarts after an pulse on
--- r_stable_ack. Hence by pulsing r_stable_ack the user can start a new fresh
--- interval for monitoring r_stable.
--- Remarks:
+ -- Purpose: Monitor whether r_in did not go low since the previous ack
+ -- Description:
+ -- When r_in = '0' then r_stable = '0'. The r_stable is '1' if r_in = '1' and
+ -- remains '1'. The r_stable measurement interval restarts after an pulse on
+ -- r_stable_ack. Hence by pulsing r_stable_ack the user can start a new fresh
+ -- interval for monitoring r_stable.
+ -- Remarks:
entity common_stable_monitor is
port (
@@ -60,29 +60,29 @@ begin
nxt_r_stable <= r_in and not r_evt_occured;
u_r_evt : entity work.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => r_in,
- out_evt => r_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => r_in,
+ out_evt => r_evt
+ );
u_r_evt_occured : entity work.common_switch
- generic map (
- g_rst_level => '0',
- g_priority_lo => false,
- g_or_high => true,
- g_and_low => false
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => r_evt,
- switch_low => r_stable_ack,
- out_level => r_evt_occured
- );
+ generic map (
+ g_rst_level => '0',
+ g_priority_lo => false,
+ g_or_high => true,
+ g_and_low => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => r_evt,
+ switch_low => r_stable_ack,
+ out_level => r_evt_occured
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_str_pkg.vhd b/libraries/base/common/src/vhdl/common_str_pkg.vhd
index e309a4d10a..c8d413838a 100644
--- a/libraries/base/common/src/vhdl/common_str_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_str_pkg.vhd
@@ -29,11 +29,11 @@
-- . None
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use STD.TEXTIO.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use STD.TEXTIO.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_pkg.all;
package common_str_pkg is
type t_str_4_arr is array (integer range <>) of string(1 to 4);
@@ -55,8 +55,10 @@ package common_str_pkg is
function int_to_str(int: integer) return string;
function real_to_str(re: real; width : integer; digits : integer) return string;
- procedure print_str(str : string);
- procedure print_str(str: string; enable: boolean);
+ procedure print_str(
+ str : string);
+ procedure print_str(
+ str: string; enable: boolean);
function str_to_ascii_integer_arr(s: string) return t_integer_arr;
function str_to_ascii_slv_8_arr( s: string) return t_slv_8_arr;
@@ -66,13 +68,13 @@ end common_str_pkg;
package body common_str_pkg is
function nof_digits(number: natural) return natural is
- -- Returns number of digits in a natural number. Only used in string processing, so defined here.
- -- log10(0) is not allowed so:
- -- . nof_digits(0) = 1
- -- We're adding 1 so:
- -- . nof_digits(1) = 1
- -- . nof_digits(9) = 1
- -- . nof_digits(10) = 2
+ -- Returns number of digits in a natural number. Only used in string processing, so defined here.
+ -- log10(0) is not allowed so:
+ -- . nof_digits(0) = 1
+ -- We're adding 1 so:
+ -- . nof_digits(1) = 1
+ -- . nof_digits(9) = 1
+ -- . nof_digits(10) = 2
begin
if number > 0 then
return floor_log10(number) + 1;
@@ -83,14 +85,14 @@ package body common_str_pkg is
end;
function nof_digits_int(number: integer) return natural is
- -- Returns number of digits in a natural number. Only used in string processing, so defined here.
- -- log10(0) is not allowed so:
- -- . nof_digits(0) = 1
- -- We're adding 1 so:
- -- . nof_digits(1) = 1
- -- . nof_digits(9) = 1
- -- . nof_digits(10) = 2
- -- . nof_digits(1) = 2
+ -- Returns number of digits in a natural number. Only used in string processing, so defined here.
+ -- log10(0) is not allowed so:
+ -- . nof_digits(0) = 1
+ -- We're adding 1 so:
+ -- . nof_digits(1) = 1
+ -- . nof_digits(9) = 1
+ -- . nof_digits(10) = 2
+ -- . nof_digits(1) = 2
begin
if number = 0 then
return 1;
@@ -116,13 +118,13 @@ package body common_str_pkg is
function time_to_str(in_time : time) return string is
constant c_max_len_time : natural := 20;
- variable v_line : LINE;
- variable v_str : string(1 to c_max_len_time) := (others => ' ');
+ variable v_line : LINE;
+ variable v_str : string(1 to c_max_len_time) := (others => ' ');
begin
write(v_line, in_time);
- v_str(v_line.ALL'range) := v_line.all;
- deallocate(v_line);
- return v_str;
+ v_str(v_line.ALL'range) := v_line.all;
+ deallocate(v_line);
+ return v_str;
end;
function str_to_time(in_str : string) return time is
@@ -134,15 +136,15 @@ package body common_str_pkg is
variable v_line : LINE;
variable v_str : string(1 to slv'length) := (others => ' ');
begin
- write(v_line, slv);
- v_str(v_line.ALL'range) := v_line.all;
- deallocate(v_line);
- return v_str;
+ write(v_line, slv);
+ v_str(v_line.ALL'range) := v_line.all;
+ deallocate(v_line);
+ return v_str;
end;
function sl_to_str(sl : std_logic) return string is
begin
- return slv_to_str(slv(sl));
+ return slv_to_str(slv(sl));
end;
function str_to_hex(str : string) return string is
@@ -182,14 +184,14 @@ package body common_str_pkg is
end;
function hex_to_slv(str: string) return std_logic_vector is
- constant c_length : natural := str'length;
- variable v_str : string(1 to str'length) := str; -- Keep local copy of str to prevent range mismatch
- variable v_result : std_logic_vector(c_length * 4 - 1 downto 0);
+ constant c_length : natural := str'length;
+ variable v_str : string(1 to str'length) := str; -- Keep local copy of str to prevent range mismatch
+ variable v_result : std_logic_vector(c_length * 4 - 1 downto 0);
begin
- for i in c_length downto 1 loop
- v_result(3 + (c_length - i) * 4 downto (c_length - i) * 4) := hex_nibble_to_slv(v_str(i));
- end loop;
- return v_result;
+ for i in c_length downto 1 loop
+ v_result(3 + (c_length - i) * 4 downto (c_length - i) * 4) := hex_nibble_to_slv(v_str(i));
+ end loop;
+ return v_result;
end;
function hex_nibble_to_slv(c: character) return std_logic_vector is
@@ -223,9 +225,9 @@ package body common_str_pkg is
when 'z' => v_result := "ZZZZ";
when 'Z' => v_result := "ZZZZ";
- when others => v_result := "0000";
- end case;
- return v_result;
+ when others => v_result := "0000";
+ end case;
+ return v_result;
end hex_nibble_to_slv;
function int_to_str(int: integer) return string is
@@ -261,7 +263,7 @@ package body common_str_pkg is
end;
procedure print_str(str: string) is
- variable v_line: LINE;
+ variable v_line: LINE;
begin
write(v_line, str);
writeline(output, v_line);
@@ -269,7 +271,7 @@ package body common_str_pkg is
end;
procedure print_str(str: string; enable: boolean) is
- variable v_line: LINE;
+ variable v_line: LINE;
begin
if enable then
print_str(str);
diff --git a/libraries/base/common/src/vhdl/common_switch.vhd b/libraries/base/common/src/vhdl/common_switch.vhd
index ae38d1382f..7d01ee152a 100644
--- a/libraries/base/common/src/vhdl/common_switch.vhd
+++ b/libraries/base/common/src/vhdl/common_switch.vhd
@@ -30,7 +30,7 @@
-- switch_low are active simultaneously.
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
entity common_switch is
generic (
diff --git a/libraries/base/common/src/vhdl/common_toggle.vhd b/libraries/base/common/src/vhdl/common_toggle.vhd
index 79d9a4a67d..b479a0dba5 100644
--- a/libraries/base/common/src/vhdl/common_toggle.vhd
+++ b/libraries/base/common/src/vhdl/common_toggle.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_toggle is
generic (
@@ -65,18 +65,18 @@ begin
-- Detect in_dat event
u_in_evt : entity work.common_evt
- generic map (
- g_evt_type => g_evt_type,
- g_out_invert => false,
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_sig => in_hld,
- out_evt => in_evt
- );
+ generic map (
+ g_evt_type => g_evt_type,
+ g_out_invert => false,
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_sig => in_hld,
+ out_evt => in_evt
+ );
-- Toggle output at in_dat event
nxt_out_dat <= not i_out_dat when in_evt = '1' else i_out_dat;
diff --git a/libraries/base/common/src/vhdl/common_toggle_align.vhd b/libraries/base/common/src/vhdl/common_toggle_align.vhd
index 6739bf67d4..4612fb4ef4 100644
--- a/libraries/base/common/src/vhdl/common_toggle_align.vhd
+++ b/libraries/base/common/src/vhdl/common_toggle_align.vhd
@@ -33,7 +33,7 @@
-- even when in_toggle stops toggling or change phase for some reason.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_toggle_align is
generic (
@@ -95,14 +95,14 @@ begin
end process;
u_common_pipeline_sl : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline,
- g_reset_value => g_reset_value
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => nxt_out_toggle,
- out_dat => out_toggle
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_reset_value => g_reset_value
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => nxt_out_toggle,
+ out_dat => out_toggle
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_transpose.vhd b/libraries/base/common/src/vhdl/common_transpose.vhd
index 0408bdf486..788763b0c5 100644
--- a/libraries/base/common/src/vhdl/common_transpose.vhd
+++ b/libraries/base/common/src/vhdl/common_transpose.vhd
@@ -20,19 +20,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-
--- Purpose: Transpose the g_nof_data symbols in g_nof_data in_data to
--- g_nof_data symbols in g_nof_data out_data,
--- with support for interleaved address calculation via in_offset.
--- Description:
--- . Each in_data has g_nof_data symbols. After every g_nof_data in_data the
--- symbols in the g_nof_data by g_nof_data matrix transposed.
--- . In parallel for each out_data the in_addr is incremented by 0, 1, ...,
--- or (g_nof_data-1) * in_offset. The in_offset can be set fixed via
--- g_addr_offset or dynamically via in_offset.
--- Remarks:
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+
+ -- Purpose: Transpose the g_nof_data symbols in g_nof_data in_data to
+ -- g_nof_data symbols in g_nof_data out_data,
+ -- with support for interleaved address calculation via in_offset.
+ -- Description:
+ -- . Each in_data has g_nof_data symbols. After every g_nof_data in_data the
+ -- symbols in the g_nof_data by g_nof_data matrix transposed.
+ -- . In parallel for each out_data the in_addr is incremented by 0, 1, ...,
+ -- or (g_nof_data-1) * in_offset. The in_offset can be set fixed via
+ -- g_addr_offset or dynamically via in_offset.
+ -- Remarks:
entity common_transpose is
generic (
@@ -90,204 +90,204 @@ architecture str of common_transpose is
signal hold_sel : std_logic_vector(c_sel_w - 1 downto 0);
begin
u_sreg_data : entity common_lib.common_shiftreg
- generic map (
- g_pipeline => g_pipeline_shiftreg,
- g_flush_en => true,
- g_nof_dat => g_nof_data,
- g_dat_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => in_data,
- in_val => in_val,
- in_eop => in_eop,
-
- out_data_vec => sreg_data_vec,
- out_cnt => sreg_sel,
-
- out_val => sreg_val,
- out_eop => sreg_eop
- );
+ generic map (
+ g_pipeline => g_pipeline_shiftreg,
+ g_flush_en => true,
+ g_nof_dat => g_nof_data,
+ g_dat_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_data,
+ in_val => in_val,
+ in_eop => in_eop,
+
+ out_data_vec => sreg_data_vec,
+ out_cnt => sreg_sel,
+
+ out_val => sreg_val,
+ out_eop => sreg_eop
+ );
u_sreg_addr : entity common_lib.common_shiftreg
- generic map (
- g_pipeline => g_pipeline_shiftreg,
- g_flush_en => true,
- g_nof_dat => g_nof_data,
- g_dat_w => g_addr_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => in_addr,
- in_val => in_val,
- in_eop => in_eop,
-
- out_data_vec => sreg_addr_vec
- );
+ generic map (
+ g_pipeline => g_pipeline_shiftreg,
+ g_flush_en => true,
+ g_nof_dat => g_nof_data,
+ g_dat_w => g_addr_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_addr,
+ in_val => in_val,
+ in_eop => in_eop,
+
+ out_data_vec => sreg_addr_vec
+ );
sreg_full <= '1' when sreg_val = '1' and TO_UINT(sreg_sel) = 0 else '0';
u_transpose_data : entity common_lib.common_transpose_symbol
- generic map (
- g_pipeline => g_pipeline_transpose,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => sreg_data_vec,
- out_data => trans_data_vec
- );
+ generic map (
+ g_pipeline => g_pipeline_transpose,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => sreg_data_vec,
+ out_data => trans_data_vec
+ );
gen_offsets : for I in g_nof_data - 1 downto 0 generate
offset_addr_vec((I + 1) * g_addr_w - 1 downto I * g_addr_w) <= TO_UVEC(I * TO_UINT(in_offset), g_addr_w);
end generate;
u_add_addr : entity common_lib.common_add_symbol
- generic map (
- g_pipeline => g_pipeline_transpose,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_addr_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_a => offset_addr_vec,
- in_b => sreg_addr_vec,
-
- out_data => add_addr_vec
- );
+ generic map (
+ g_pipeline => g_pipeline_transpose,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_addr_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_a => offset_addr_vec,
+ in_b => sreg_addr_vec,
+
+ out_data => add_addr_vec
+ );
u_trans_full : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_transpose
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sreg_full,
- out_dat => trans_full
- );
+ generic map (
+ g_pipeline => g_pipeline_transpose
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sreg_full,
+ out_dat => trans_full
+ );
u_hold_data : entity common_lib.common_shiftreg_symbol
- generic map (
- g_shiftline_arr => c_holdline_arr(g_nof_data - 1 downto 0),
- g_pipeline => g_pipeline_hold,
- g_flush_en => false,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => trans_data_vec,
- in_val => trans_full,
-
- out_data => hold_data_vec
- );
+ generic map (
+ g_shiftline_arr => c_holdline_arr(g_nof_data - 1 downto 0),
+ g_pipeline => g_pipeline_hold,
+ g_flush_en => false,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => trans_data_vec,
+ in_val => trans_full,
+
+ out_data => hold_data_vec
+ );
u_hold_addr : entity common_lib.common_shiftreg_symbol
- generic map (
- g_shiftline_arr => c_holdline_arr(g_nof_data - 1 downto 0),
- g_pipeline => g_pipeline_hold,
- g_flush_en => false,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_addr_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => add_addr_vec,
- in_val => trans_full,
-
- out_data => hold_addr_vec
- );
+ generic map (
+ g_shiftline_arr => c_holdline_arr(g_nof_data - 1 downto 0),
+ g_pipeline => g_pipeline_hold,
+ g_flush_en => false,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_addr_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => add_addr_vec,
+ in_val => trans_full,
+
+ out_data => hold_addr_vec
+ );
u_hold_sel : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_pipeline_sel,
- g_in_dat_w => c_sel_w,
- g_out_dat_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sreg_sel,
- out_dat => hold_sel
- );
+ generic map (
+ g_pipeline => c_pipeline_sel,
+ g_in_dat_w => c_sel_w,
+ g_out_dat_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sreg_sel,
+ out_dat => hold_sel
+ );
u_hold_val : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_sel
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sreg_val,
- out_dat => hold_val
- );
+ generic map (
+ g_pipeline => c_pipeline_sel
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sreg_val,
+ out_dat => hold_val
+ );
u_hold_eop : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_sel
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sreg_eop,
- out_dat => hold_eop
- );
+ generic map (
+ g_pipeline => c_pipeline_sel
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sreg_eop,
+ out_dat => hold_eop
+ );
u_output_data : entity common_lib.common_select_symbol
- generic map (
- g_pipeline_in => 0,
- g_pipeline_out => g_pipeline_select,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_data_w,
- g_sel_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => hold_data_vec,
- in_val => hold_val,
- in_eop => hold_eop,
-
- in_sel => hold_sel,
-
- out_symbol => out_data,
- out_val => out_val,
- out_eop => out_eop
- );
+ generic map (
+ g_pipeline_in => 0,
+ g_pipeline_out => g_pipeline_select,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_data_w,
+ g_sel_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => hold_data_vec,
+ in_val => hold_val,
+ in_eop => hold_eop,
+
+ in_sel => hold_sel,
+
+ out_symbol => out_data,
+ out_val => out_val,
+ out_eop => out_eop
+ );
u_output_addr : entity common_lib.common_select_symbol
- generic map (
- g_pipeline_in => 0,
- g_pipeline_out => g_pipeline_select,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_addr_w,
- g_sel_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => hold_addr_vec,
- in_val => hold_val,
- in_eop => hold_eop,
-
- in_sel => hold_sel,
-
- out_symbol => out_addr
- );
+ generic map (
+ g_pipeline_in => 0,
+ g_pipeline_out => g_pipeline_select,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_addr_w,
+ g_sel_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => hold_addr_vec,
+ in_val => hold_val,
+ in_eop => hold_eop,
+
+ in_sel => hold_sel,
+
+ out_symbol => out_addr
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_transpose_symbol.vhd b/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
index bd6fc252d0..a91aedad71 100644
--- a/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
@@ -20,29 +20,29 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-
--- Purpose: Transpose of in_data to out_data
--- Description:
--- The in_data is a concatenation of g_nof_data input streams, that are each
--- g_data_w bits wide. The data in each input stream consists of a
--- concatenation of g_nof_data symbols, that are g_data_w/g_nof_data bits
--- wide. The out_data contains the transpose of in_data. For example for
--- g_nof_data=2 this becomes:
---
--- |- b[1,0] ---> 1[b,a] -|
--- | \/ |
--- | /\ |
--- in_data[b[1,0,a[1,0]] -+- a[1,0] ---> 0[b,a] -+-> out_data[1[b,a],0[b,a]]
---
--- Idem for g_nof_data=4:
---
--- in_data[d[3:0],c[3:0],b[3:0],a[3:0]] -> out_data[3[d:a],2[d:a],1[d:a],0[d:a]]
---
--- Remarks:
--- . The transpose assumes that the in_data is square, so
--- c_nof_symbols = g_nof_data
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+
+ -- Purpose: Transpose of in_data to out_data
+ -- Description:
+ -- The in_data is a concatenation of g_nof_data input streams, that are each
+ -- g_data_w bits wide. The data in each input stream consists of a
+ -- concatenation of g_nof_data symbols, that are g_data_w/g_nof_data bits
+ -- wide. The out_data contains the transpose of in_data. For example for
+ -- g_nof_data=2 this becomes:
+ --
+ -- |- b[1,0] ---> 1[b,a] -|
+ -- | \/ |
+ -- | /\ |
+ -- in_data[b[1,0,a[1,0]] -+- a[1,0] ---> 0[b,a] -+-> out_data[1[b,a],0[b,a]]
+ --
+ -- Idem for g_nof_data=4:
+ --
+ -- in_data[d[3:0],c[3:0],b[3:0],a[3:0]] -> out_data[3[d:a],2[d:a],1[d:a],0[d:a]]
+ --
+ -- Remarks:
+ -- . The transpose assumes that the in_data is square, so
+ -- c_nof_symbols = g_nof_data
entity common_transpose_symbol is
generic (
@@ -99,49 +99,49 @@ begin
-- pipeline data output
u_out_data : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_data * g_data_w,
- g_out_dat_w => g_nof_data * g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => trans_data,
- out_dat => out_data
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_data * g_data_w,
+ g_out_dat_w => g_nof_data * g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => trans_data,
+ out_dat => out_data
+ );
-- pipeline control output
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => out_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => out_sop
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => out_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => out_eop
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => out_eop
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_variable_delay.vhd b/libraries/base/common/src/vhdl/common_variable_delay.vhd
index 10ddd4a1eb..ba7c0fd445 100644
--- a/libraries/base/common/src/vhdl/common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_variable_delay.vhd
@@ -27,8 +27,8 @@
-- --------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_variable_delay is
generic (
diff --git a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
index 4327b27652..c196edb38b 100644
--- a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
+++ b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
@@ -32,8 +32,8 @@
-- eases the use of this scope within a design.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_wideband_data_scope is
generic (
diff --git a/libraries/base/common/src/vhdl/common_zip.vhd b/libraries/base/common/src/vhdl/common_zip.vhd
index 2bb1bd6abd..12024ec7fc 100644
--- a/libraries/base/common/src/vhdl/common_zip.vhd
+++ b/libraries/base/common/src/vhdl/common_zip.vhd
@@ -25,8 +25,8 @@
-- to avoid the loss of data.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_zip is
generic (
@@ -62,25 +62,25 @@ begin
v.out_val := '0'; -- Default the output valid signal is low.
if(in_val = '1') then -- Wait for incoming data
- v.index := 1;
- v.out_val := '1';
- v.out_dat := in_dat_arr(0)(g_dat_w - 1 downto 0); -- Output the first stream already
- for I in 1 to g_nof_streams - 1 loop
- v.in_dat_arr(I) := in_dat_arr(I)(g_dat_w - 1 downto 0); -- Store input data in register
- end loop;
+ v.index := 1;
+ v.out_val := '1';
+ v.out_dat := in_dat_arr(0)(g_dat_w - 1 downto 0); -- Output the first stream already
+ for I in 1 to g_nof_streams - 1 loop
+ v.in_dat_arr(I) := in_dat_arr(I)(g_dat_w - 1 downto 0); -- Store input data in register
+ end loop;
end if;
if(r.index < g_nof_streams) then
- v.out_val := '1';
- v.out_dat := r.in_dat_arr(r.index); -- Output the next input stream
- v.index := r.index + 1;
+ v.out_val := '1';
+ v.out_dat := r.in_dat_arr(r.index); -- Output the next input stream
+ v.index := r.index + 1;
end if;
if(rst = '1') then
- v.in_dat_arr := (others => (others => '0'));
- v.index := g_nof_streams;
- v.out_dat := (others => '0');
- v.out_val := '0';
+ v.in_dat_arr := (others => (others => '0'));
+ v.index := g_nof_streams;
+ v.out_dat := (others => '0');
+ v.out_val := '0';
end if;
rin <= v;
diff --git a/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd b/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
index ea0228354d..9b9570750d 100644
--- a/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
@@ -25,17 +25,17 @@
-- . MM wrapper for common_pulse_delay.vhd
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_common_pulse_delay is
generic (
g_pulse_delay_max : natural := 0; -- Maximum number of clk cycles that pulse can be delayed
g_register_out : boolean
- );
+ );
port (
pulse_clk : in std_logic;
pulse_rst : in std_logic;
@@ -56,34 +56,34 @@ begin
-- common_pulse_delay
------------------------------------------------------------------------------
u_common_pulse_delay : entity common_lib.common_pulse_delay
- generic map (
- g_pulse_delay_max => g_pulse_delay_max,
- g_register_out => true
- )
- port map (
- clk => pulse_clk,
- rst => pulse_rst,
- pulse_in => pulse_in,
- pulse_delay => pulse_delay,
- pulse_out => pulse_out
- );
+ generic map (
+ g_pulse_delay_max => g_pulse_delay_max,
+ g_register_out => true
+ )
+ port map (
+ clk => pulse_clk,
+ rst => pulse_rst,
+ pulse_in => pulse_in,
+ pulse_delay => pulse_delay,
+ pulse_out => pulse_out
+ );
------------------------------------------------------------------------------
-- New MM interface via avs_common_mm
------------------------------------------------------------------------------
u_common_pulse_delay_reg : entity work.common_pulse_delay_reg
- generic map (
- g_cross_clock_domain => true,
- g_pulse_delay_max => g_pulse_delay_max
- )
- port map (
- pulse_clk => pulse_clk,
- pulse_rst => pulse_rst,
- pulse_delay => pulse_delay,
+ generic map (
+ g_cross_clock_domain => true,
+ g_pulse_delay_max => g_pulse_delay_max
+ )
+ port map (
+ pulse_clk => pulse_clk,
+ pulse_rst => pulse_rst,
+ pulse_delay => pulse_delay,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- sla_in => reg_mosi,
- sla_out => reg_miso
- );
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ sla_in => reg_mosi,
+ sla_out => reg_miso
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/mms_common_reg.vhd b/libraries/base/common/src/vhdl/mms_common_reg.vhd
index 56fb4f3865..29af1c6621 100644
--- a/libraries/base/common/src/vhdl/mms_common_reg.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_reg.vhd
@@ -23,9 +23,9 @@
-- Description: Wrapper, see common_reg_r_w_dc.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_common_reg is
generic (
@@ -61,27 +61,27 @@ architecture str of mms_common_reg is
constant c_init_reg : std_logic_vector(c_mem_reg_init_w - 1 downto 0) := (others => g_mm_reg.init_sl);
begin
u_common_reg_r_w_dc : entity work.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => g_mm_reg,
- g_init_reg => c_init_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => g_mm_reg,
+ g_init_reg => c_init_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => in_reg,
- out_reg => out_reg
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => in_reg,
+ out_reg => out_reg
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd b/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
index c1bf30f4e7..5ac4cd9066 100644
--- a/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
@@ -23,9 +23,9 @@
-- Description: See common_stable_monitor.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_common_stable_monitor is
generic (
@@ -53,11 +53,12 @@ architecture str of mms_common_stable_monitor is
constant c_adr_w : natural := ceil_log2(c_nof_dat);
constant c_dat_w : natural := sel_a_b(c_nof_dat = 1, g_nof_input, c_word_w);
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => c_adr_w,
- dat_w => c_dat_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_adr_w,
+ dat_w => c_dat_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_dat,
+ init_sl => '0');
signal reg_rd_arr : std_logic_vector(c_mm_reg.nof_dat - 1 downto 0);
@@ -67,28 +68,28 @@ architecture str of mms_common_stable_monitor is
signal in_reg : std_logic_vector(c_nof_dat * c_word_w - 1 downto 0);
begin
u_mm_reg : entity work.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => reg_rd_arr,
- in_reg => in_reg,
- out_reg => open
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => reg_rd_arr,
+ in_reg => in_reg,
+ out_reg => open
+ );
in_reg(g_nof_input - 1 downto 0) <= st_stable_arr;
@@ -97,14 +98,14 @@ begin
gen_mon : for I in g_nof_input - 1 downto 0 generate
u_stable_monitor : entity work.common_stable_monitor
- port map (
- rst => st_rst,
- clk => st_clk,
- -- MM
- r_in => st_in_arr(I),
- r_stable => st_stable_arr(I),
- r_stable_ack => st_stable_ack
- );
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- MM
+ r_in => st_in_arr(I),
+ r_stable => st_stable_arr(I),
+ r_stable_ack => st_stable_ack
+ );
end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd b/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
index 57d388d15f..5c69a15352 100644
--- a/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
@@ -26,10 +26,10 @@
-- --------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
entity mms_common_variable_delay is
port (
@@ -61,30 +61,30 @@ begin
-- device under test
u_common_variable_delay : entity work.common_variable_delay
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- delay => delay,
- enable => enable,
- in_pulse => trigger,
- out_pulse => trigger_dly
- );
+ delay => delay,
+ enable => enable,
+ in_pulse => trigger,
+ out_pulse => trigger_dly
+ );
u_mms_common_reg : entity work.mms_common_reg
- generic map (
- g_mm_reg => c_enable_mem_reg
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_mm_reg => c_enable_mem_reg
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- reg_mosi => reg_enable_mosi,
- reg_miso => reg_enable_miso,
+ reg_mosi => reg_enable_mosi,
+ reg_miso => reg_enable_miso,
- in_reg => enable_reg,
- out_reg => enable_reg
- );
-end;
+ in_reg => enable_reg,
+ out_reg => enable_reg
+ );
+ end;
diff --git a/libraries/base/common/tb/vhdl/tb_common_acapture.vhd b/libraries/base/common/tb/vhdl/tb_common_acapture.vhd
index 615f744bf2..c6addaeb0a 100644
--- a/libraries/base/common/tb/vhdl/tb_common_acapture.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_acapture.vhd
@@ -27,10 +27,10 @@
-- Description:
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_acapture is
end tb_common_acapture;
@@ -75,14 +75,14 @@ begin
end process;
u_acapture : entity work.common_acapture
- generic map (
- g_rst_level => '0'
- )
- port map (
- in_rst => in_rst,
- in_clk => in_clk,
- in_dat => in_dat,
- out_clk => out_clk,
- out_cap => out_cap
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ in_rst => in_rst,
+ in_clk => in_clk,
+ in_dat => in_dat,
+ out_clk => out_clk,
+ out_cap => out_cap
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd b/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
index b415d43577..17e7c3d0b9 100644
--- a/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_add_sub is
generic (
@@ -127,38 +127,38 @@ begin
out_result <= func_result(in_a, in_b);
u_result : entity work.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => out_result,
- out_dat => result_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => out_result,
+ out_dat => result_expected
+ );
u_dut_rtl : entity work.common_add_sub
- generic map (
- g_direction => g_direction,
- g_representation => "SIGNED",
- g_pipeline_input => g_pipeline_in,
- g_pipeline_output => g_pipeline_out,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => '1',
- sel_add => g_sel_add,
- in_a => in_a,
- in_b => in_b,
- result => result_rtl
- );
+ generic map (
+ g_direction => g_direction,
+ g_representation => "SIGNED",
+ g_pipeline_input => g_pipeline_in,
+ g_pipeline_output => g_pipeline_out,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ sel_add => g_sel_add,
+ in_a => in_a,
+ in_b => in_b,
+ result => result_rtl
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
index 1686b6f4e3..872b8eb94e 100644
--- a/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
@@ -31,10 +31,10 @@
-- . The p_verify makes the tb self checking and asserts when the results are not equal
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_adder_tree is
generic (
@@ -124,20 +124,20 @@ begin
-- . Pipeline the in_data_vec to align with the result
-- . Map the concatenated symbols in in_data_vec into an in_data_arr_p array
u_data_vec_p : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0,
- g_in_dat_w => c_data_vec_w,
- g_out_dat_w => c_data_vec_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_data_vec,
- out_dat => in_data_vec_p
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0,
+ g_in_dat_w => c_data_vec_w,
+ g_out_dat_w => c_data_vec_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_data_vec,
+ out_dat => in_data_vec_p
+ );
p_data_arr : process(in_data_vec_p)
begin
@@ -149,36 +149,36 @@ begin
result_comb <= func_result(in_data_vec);
u_result : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0,
- g_in_dat_w => g_sum_w,
- g_out_dat_w => g_sum_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => result_comb,
- out_dat => result_expected
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0,
+ g_in_dat_w => g_sum_w,
+ g_out_dat_w => g_sum_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => result_comb,
+ out_dat => result_expected
+ );
-- Using work.common_adder_tree(recursive) will only invoke the recursive architecture once, because the next recursive level will default to using the last compiled architecture
-- Therefore only instatiatiate the DUT once in this tb and use compile order to influence which architecture is used.
dut : entity work.common_adder_tree -- uses last compile architecture
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_nof_inputs => g_nof_inputs,
- g_dat_w => g_symbol_w,
- g_sum_w => g_sum_w
- )
- port map (
- clk => clk,
- in_dat => in_data_vec,
- sum => result_dut
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_nof_inputs => g_nof_inputs,
+ g_dat_w => g_symbol_w,
+ g_sum_w => g_sum_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_data_vec,
+ sum => result_dut
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common/tb/vhdl/tb_common_async.vhd b/libraries/base/common/tb/vhdl/tb_common_async.vhd
index e6bf4e8c47..4f572784c2 100644
--- a/libraries/base/common/tb/vhdl/tb_common_async.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_async.vhd
@@ -27,10 +27,10 @@
-- Description:
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_async is
end tb_common_async;
@@ -82,25 +82,25 @@ begin
end process;
u_async : entity work.common_async
- generic map (
- g_rst_level => '1',
- g_delay_len => c_delay_len
- )
- port map (
- rst => in_rst,
- clk => clk,
- din => in_dat,
- dout => out_async
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_delay_len
+ )
+ port map (
+ rst => in_rst,
+ clk => clk,
+ din => in_dat,
+ dout => out_async
+ );
u_areset : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_delay_len
- )
- port map (
- in_rst => in_rst,
- clk => clk,
- out_rst => out_areset
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_delay_len
+ )
+ port map (
+ in_rst => in_rst,
+ clk => clk,
+ out_rst => out_areset
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd b/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
index 27265014b5..04bdd96be7 100644
--- a/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
@@ -27,10 +27,10 @@
-- Description:
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_clock_phase_detector is
generic (
@@ -87,30 +87,30 @@ begin
end process;
u_common_clock_phase_detector_r : entity work.common_clock_phase_detector
- generic map (
- g_rising_edge => true,
- g_meta_delay_len => c_delay_len,
- g_clk_factor => c_clk_factor_num
- )
- port map (
- in_clk => in_clk, -- used as data input for clk domain
- rst => rst,
- clk => clk,
- phase => phase_r,
- phase_det => phase_r_det
- );
+ generic map (
+ g_rising_edge => true,
+ g_meta_delay_len => c_delay_len,
+ g_clk_factor => c_clk_factor_num
+ )
+ port map (
+ in_clk => in_clk, -- used as data input for clk domain
+ rst => rst,
+ clk => clk,
+ phase => phase_r,
+ phase_det => phase_r_det
+ );
u_common_clock_phase_detector_f : entity work.common_clock_phase_detector
- generic map (
- g_rising_edge => false,
- g_meta_delay_len => c_delay_len,
- g_clk_factor => c_clk_factor_num
- )
- port map (
- in_clk => in_clk, -- used as data input for clk domain
- rst => rst,
- clk => clk,
- phase => phase_f,
- phase_det => phase_f_det
- );
+ generic map (
+ g_rising_edge => false,
+ g_meta_delay_len => c_delay_len,
+ g_clk_factor => c_clk_factor_num
+ )
+ port map (
+ in_clk => in_clk, -- used as data input for clk domain
+ rst => rst,
+ clk => clk,
+ phase => phase_f,
+ phase_det => phase_f_det
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_counter.vhd b/libraries/base/common/tb/vhdl/tb_common_counter.vhd
index ff4e5fd21d..5d09a1fce7 100644
--- a/libraries/base/common/tb/vhdl/tb_common_counter.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_counter.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_counter is
end tb_common_counter;
@@ -87,19 +87,19 @@ begin
-- device under test
u_dut : entity work.common_counter
- generic map (
- g_init => c_cnt_init,
- g_width => c_cnt_w,
- g_step_size => 1
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => cnt_clr,
- cnt_ld => cnt_ld,
- cnt_en => cnt_en,
- cnt_max => cnt_max,
- load => load,
- count => count
- );
+ generic map (
+ g_init => c_cnt_init,
+ g_width => c_cnt_w,
+ g_step_size => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => cnt_clr,
+ cnt_ld => cnt_ld,
+ cnt_en => cnt_en,
+ cnt_max => cnt_max,
+ load => load,
+ count => count
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd b/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
index c42ebccaee..410f19137e 100644
--- a/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
@@ -24,9 +24,9 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_create_strobes_from_valid is
generic (
@@ -121,18 +121,18 @@ begin
end process;
u_in_sync : entity work.common_create_strobes_from_valid
- generic map (
- g_pipeline => g_pipeline,
- g_nof_clk_per_sync => g_nof_clk_per_sync,
- g_nof_clk_per_block => g_nof_clk_per_block
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop,
- out_sync => out_sync
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_nof_clk_per_sync => g_nof_clk_per_sync,
+ g_nof_clk_per_block => g_nof_clk_per_block
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop,
+ out_sync => out_sync
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd b/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd
index c333692fd1..a7ad038aae 100644
--- a/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd
@@ -27,10 +27,10 @@
-- Description: See common_ddreg.vhd
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_ddreg_slv is
end tb_common_ddreg_slv;
@@ -66,18 +66,18 @@ begin
end process;
u_common_ddreg_slv : entity work.common_ddreg_slv
- generic map (
- g_in_delay_len => 1,
- g_out_delay_len => c_meta_delay_len
- )
- port map (
- in_clk => in_clk,
- in_dat => in_dat,
- rst => rst,
- out_clk => out_clk,
- out_dat_hi => out_dat_hi,
- out_dat_lo => out_dat_lo
- );
+ generic map (
+ g_in_delay_len => 1,
+ g_out_delay_len => c_meta_delay_len
+ )
+ port map (
+ in_clk => in_clk,
+ in_dat => in_dat,
+ rst => rst,
+ out_clk => out_clk,
+ out_dat_hi => out_dat_hi,
+ out_dat_lo => out_dat_lo
+ );
out_dat <= out_dat_hi & out_dat_lo;
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_debounce.vhd b/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
index bbd52cac85..5d92056377 100644
--- a/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
@@ -38,8 +38,8 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_common_debounce is
end tb_common_debounce;
@@ -168,46 +168,46 @@ begin
end process;
u_debounce_both : entity work.common_debounce
- generic map (
- g_delay_len => c_meta_delay_len,
- g_latency => c_latency,
- g_init_level => c_rst_level_both
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- d_in => d_in,
- q_out => q_both
- );
+ generic map (
+ g_delay_len => c_meta_delay_len,
+ g_latency => c_latency,
+ g_init_level => c_rst_level_both
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ d_in => d_in,
+ q_out => q_both
+ );
u_debounce_high : entity work.common_debounce
- generic map (
- g_type => "HIGH",
- g_delay_len => c_meta_delay_len,
- g_latency => c_latency,
- g_init_level => c_rst_level_high
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- d_in => d_in,
- q_out => q_high
- );
+ generic map (
+ g_type => "HIGH",
+ g_delay_len => c_meta_delay_len,
+ g_latency => c_latency,
+ g_init_level => c_rst_level_high
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ d_in => d_in,
+ q_out => q_high
+ );
u_debounce_low : entity work.common_debounce
- generic map (
- g_type => "LOW",
- g_delay_len => c_meta_delay_len,
- g_latency => c_latency,
- g_init_level => c_rst_level_low
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- d_in => d_in,
- q_out => q_low
- );
+ generic map (
+ g_type => "LOW",
+ g_delay_len => c_meta_delay_len,
+ g_latency => c_latency,
+ g_init_level => c_rst_level_low
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ d_in => d_in,
+ q_out => q_low
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd b/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd
index 861bc4118f..ac59a92fde 100644
--- a/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_common_duty_cycle is
end tb_common_duty_cycle;
@@ -110,21 +110,21 @@ begin
-----------------------------------------------------------------------------
dut : entity work.common_duty_cycle
- generic map (
- g_rst_lvl => '0',
- g_dis_lvl => '0',
- g_act_lvl => '1',
- g_per_cnt => c_dc_max_period_cnt,
- g_act_cnt => 10
- )
- port map (
- rst => rst,
- clk => clk,
-
- dc_per_cnt => dc_per_cnt,
- dc_act_cnt => dc_act_cnt,
-
- dc_out_en => dc_out_en,
- dc_out => dc_out
- );
+ generic map (
+ g_rst_lvl => '0',
+ g_dis_lvl => '0',
+ g_act_lvl => '1',
+ g_per_cnt => c_dc_max_period_cnt,
+ g_act_cnt => 10
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ dc_per_cnt => dc_per_cnt,
+ dc_act_cnt => dc_act_cnt,
+
+ dc_out_en => dc_out_en,
+ dc_out => dc_out
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
index d5b732914c..550ff67c70 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
@@ -27,11 +27,11 @@
-- when the fanout data is not incrementing.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_fanout_tree is
generic (
@@ -55,8 +55,9 @@ architecture tb of tb_common_fanout_tree is
constant c_dat_w : natural := 8;
constant c_nof_output : natural := g_nof_output_per_cell**g_nof_stages;
- constant c_tree_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := func_common_fanout_tree_pipelining(g_nof_stages, g_nof_output_per_cell, c_nof_output,
- g_cell_pipeline_factor_arr, g_cell_pipeline_arr);
+ constant c_tree_pipeline_arr : t_natural_arr(
+ c_nof_output - 1 downto 0) := func_common_fanout_tree_pipelining(g_nof_stages, g_nof_output_per_cell, c_nof_output,
+ g_cell_pipeline_factor_arr, g_cell_pipeline_arr);
constant c_tree_pipeline_max : natural := largest(c_tree_pipeline_arr);
type t_data_arr is array (integer range <>) of std_logic_vector(c_dat_w - 1 downto 0);
@@ -110,23 +111,23 @@ begin
proc_common_gen_data(c_rl, c_init, rst, clk, cnt_en, ready, in_dat, in_val);
dut : entity work.common_fanout_tree
- generic map (
- g_nof_stages => g_nof_stages,
- g_nof_output_per_cell => g_nof_output_per_cell,
- g_nof_output => g_nof_output,
- g_cell_pipeline_factor_arr => g_cell_pipeline_factor_arr,
- g_cell_pipeline_arr => g_cell_pipeline_arr,
- g_dat_w => c_dat_w
- )
- port map (
- clk => clk,
- in_en => in_en,
- in_dat => in_dat,
- in_val => in_val,
- out_en_vec => out_en_vec,
- out_dat_vec => out_dat_vec,
- out_val_vec => out_val_vec
- );
+ generic map (
+ g_nof_stages => g_nof_stages,
+ g_nof_output_per_cell => g_nof_output_per_cell,
+ g_nof_output => g_nof_output,
+ g_cell_pipeline_factor_arr => g_cell_pipeline_factor_arr,
+ g_cell_pipeline_arr => g_cell_pipeline_arr,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ clk => clk,
+ in_en => in_en,
+ in_dat => in_dat,
+ in_val => in_val,
+ out_en_vec => out_en_vec,
+ out_dat_vec => out_dat_vec,
+ out_val_vec => out_val_vec
+ );
-- Verify data for fanout output 0
proc_common_verify_data(c_rl, clk, verify_en, ready, out_val_vec(0), out_dat_arr(0), prev_out_dat_arr(0));
diff --git a/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd b/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
index 59082dfeef..4b306e23ed 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
@@ -26,10 +26,10 @@
-- . observe rd_dat in wave window
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_fifo_dc_mixed_widths is
generic (
@@ -103,23 +103,23 @@ begin
rd_req <= '1';
u_dut : entity work.common_fifo_dc_mixed_widths
- generic map (
- g_nof_words => c_wr_fifo_nof_words,
- g_wr_dat_w => g_wr_dat_w,
- g_rd_dat_w => g_rd_dat_w
- )
- port map (
- rst => rst,
- wr_clk => wr_clk,
- wr_dat => wr_dat,
- wr_req => wr_val,
- wr_ful => wr_ful,
- wrusedw => wr_usedw,
- rd_clk => rd_clk,
- rd_dat => rd_dat,
- rd_req => rd_req,
- rd_emp => rd_emp,
- rdusedw => rd_usedw,
- rd_val => rd_val
- );
+ generic map (
+ g_nof_words => c_wr_fifo_nof_words,
+ g_wr_dat_w => g_wr_dat_w,
+ g_rd_dat_w => g_rd_dat_w
+ )
+ port map (
+ rst => rst,
+ wr_clk => wr_clk,
+ wr_dat => wr_dat,
+ wr_req => wr_val,
+ wr_ful => wr_ful,
+ wrusedw => wr_usedw,
+ rd_clk => rd_clk,
+ rd_dat => rd_dat,
+ rd_req => rd_req,
+ rd_emp => rd_emp,
+ rdusedw => rd_usedw,
+ rd_val => rd_val
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd b/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
index ca6a2b06dc..cb4da944a0 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_fifo_rd is
generic (
@@ -78,19 +78,19 @@ begin
proc_common_verify_valid(c_read_rl, clk, verify_en, rd_req, prev_rd_req, rd_val);
u_dut : entity work.common_fifo_rd
- generic map (
- g_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink: RL = 1
- fifo_req => fifo_req,
- fifo_dat => fifo_dat,
- fifo_val => fifo_val,
- -- ST source: RL = 0
- rd_req => rd_req,
- rd_dat => rd_dat,
- rd_val => rd_val
- );
+ generic map (
+ g_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink: RL = 1
+ fifo_req => fifo_req,
+ fifo_dat => fifo_dat,
+ fifo_val => fifo_val,
+ -- ST source: RL = 0
+ rd_req => rd_req,
+ rd_dat => rd_dat,
+ rd_val => rd_val
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd b/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd
index 4a83e2948f..f035606ace 100644
--- a/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_flank_to_pulse is
end tb_common_flank_to_pulse;
@@ -55,10 +55,10 @@ begin
end process;
u_dut: entity work.common_flank_to_pulse
- port map (
- clk => clk,
- rst => rst,
- flank_in => flank_in,
- pulse_out => pulse_out
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ flank_in => flank_in,
+ pulse_out => pulse_out
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_gcd.vhd b/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
index 2acc79d324..a98da0f5ae 100644
--- a/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
@@ -25,9 +25,9 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_gcd is
end tb_common_gcd;
diff --git a/libraries/base/common/tb/vhdl/tb_common_init.vhd b/libraries/base/common/tb/vhdl/tb_common_init.vhd
index 04488cf096..5a55a9eb80 100644
--- a/libraries/base/common/tb/vhdl/tb_common_init.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_init.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_init is
end tb_common_init;
@@ -41,24 +41,24 @@ begin
clk <= not clk after clk_period / 2;
u_reset : entity work.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => clk,
- out_rst => rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => clk,
+ out_rst => rst
+ );
u_init: entity work.common_init
- generic map (
- g_latency_w => c_latency_w
- )
- port map (
- rst => rst,
- clk => clk,
- hold => hold,
- init => init
- );
+ generic map (
+ g_latency_w => c_latency_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ hold => hold,
+ init => init
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_int2float.vhd b/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
index 507ce94cc1..7a5de989c8 100644
--- a/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
@@ -1,7 +1,7 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_common_int2float is
end tb_common_int2float;
@@ -83,12 +83,12 @@ begin
end process;
u_float : entity work.common_int2float
- generic map (
- g_pipeline => c_pipeline
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_dat
- );
+ generic map (
+ g_pipeline => c_pipeline
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_dat
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd b/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
index 48aad92238..87daf9c963 100644
--- a/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
@@ -25,9 +25,9 @@
-- in Wave window zoom in and expand out_dat to see the 50 ps delays
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_iobuf_in is
end tb_common_iobuf_in;
@@ -52,14 +52,14 @@ begin
in_dat <= not(in_dat) when rising_edge(clk);
u_dut : entity work.common_iobuf_in
- generic map (
- g_width => c_width,
- g_delay_arr => c_delay_arr
- )
- port map (
- config_rst => rst,
- config_clk => clk,
- in_dat => in_dat,
- out_dat => out_dat
- );
+ generic map (
+ g_width => c_width,
+ g_delay_arr => c_delay_arr
+ )
+ port map (
+ config_rst => rst,
+ config_clk => clk,
+ in_dat => in_dat,
+ out_dat => out_dat
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd b/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
index 3934f37a7c..1ea5e0f070 100644
--- a/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
@@ -32,8 +32,8 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_common_led_controller is
end tb_common_led_controller;
@@ -101,38 +101,38 @@ begin
end process;
u_common_pulser_us_ms_s : entity work.common_pulser_us_ms_s
- generic map (
- g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
- g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => pulse_ms -- pulses after every g_pulse_us*g_pulse_ms clock cycles
- );
+ generic map (
+ g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
+ g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => pulse_ms -- pulses after every g_pulse_us*g_pulse_ms clock cycles
+ );
u_common_toggle_ms : entity work.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => pulse_ms,
- out_dat => toggle_ms
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => pulse_ms,
+ out_dat => toggle_ms
+ );
u_common_led_controller : entity work.common_led_controller
- generic map (
- g_nof_ms => c_led_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => pulse_ms,
- -- led control
- ctrl_on => ctrl_on,
- ctrl_evt => ctrl_evt,
- ctrl_input => toggle_ms,
- -- led output
- led => LED
- );
+ generic map (
+ g_nof_ms => c_led_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => pulse_ms,
+ -- led control
+ ctrl_on => ctrl_on,
+ ctrl_evt => ctrl_evt,
+ ctrl_input => toggle_ms,
+ -- led output
+ led => LED
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_log.vhd b/libraries/base/common/tb/vhdl/tb_common_log.vhd
index a93bcbce95..67aebd2d99 100644
--- a/libraries/base/common/tb/vhdl/tb_common_log.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_log.vhd
@@ -22,9 +22,9 @@
-- Usage:
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_str_pkg.all;
entity tb_common_log is
end tb_common_log;
@@ -38,29 +38,29 @@ begin
print_str("I: pow2, ceil_pow2");
for I in 1 to 20 loop
print_str(int_to_str(I) & ": " &
- int_to_str(pow2(I)) & ", " &
- int_to_str(ceil_pow2(I)));
+ int_to_str(pow2(I)) & ", " &
+ int_to_str(ceil_pow2(I)));
end loop;
print_str("");
print_str("I: ceil_log2, true_log2, true_log_pow2, is_pow2, floor_log10");
for I in 1 to 20 loop
print_str(int_to_str(I) & ": " &
- int_to_str(ceil_log2(I)) & ", " &
- int_to_str(true_log2(I)) & ", " &
- int_to_str(true_log_pow2(I)) & ", " &
- bool_to_str(is_pow2(I)) & ", " &
- int_to_str(floor_log10(I)));
+ int_to_str(ceil_log2(I)) & ", " &
+ int_to_str(true_log2(I)) & ", " &
+ int_to_str(true_log_pow2(I)) & ", " &
+ bool_to_str(is_pow2(I)) & ", " &
+ int_to_str(floor_log10(I)));
end loop;
print_str("");
print_str("I: ceil_log2, true_log2, true_log_pow2, is_pow2, floor_log10");
for I in c_range'range loop
vI := c_range(I);
print_str(int_to_str(vI) & ": " &
- int_to_str(ceil_log2(vI)) & ", " &
- int_to_str(true_log2(vI)) & ", " &
- int_to_str(true_log_pow2(vI)) & ", " &
- bool_to_str(is_pow2(vI)) & ", " &
- int_to_str(floor_log10(vI)));
+ int_to_str(ceil_log2(vI)) & ", " &
+ int_to_str(true_log2(vI)) & ", " &
+ int_to_str(true_log_pow2(vI)) & ", " &
+ bool_to_str(is_pow2(vI)) & ", " &
+ int_to_str(floor_log10(vI)));
end loop;
wait;
end process;
diff --git a/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd b/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
index 76794c62a8..6f22f8b211 100644
--- a/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use work.tb_common_pkg.all;
-use work.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use work.tb_common_pkg.all;
+ use work.tb_common_mem_pkg.all;
entity tb_common_mem_mux is
- generic (
+ generic (
g_nof_mosi : positive := 16; -- Number of memory interfaces in the array.
g_mult_addr_w : positive := 4 -- Address width of each memory-interface element in the array.
);
@@ -42,11 +42,12 @@ architecture tb of tb_common_mem_mux is
constant clk_period : time := 10 ns;
constant c_data_w : natural := 32;
- constant c_test_ram : t_c_mem := (latency => 1,
- adr_w => g_mult_addr_w,
- dat_w => c_data_w,
- nof_dat => 2**g_mult_addr_w,
- init_sl => '0');
+ constant c_test_ram : t_c_mem := (
+ latency => 1,
+ adr_w => g_mult_addr_w,
+ dat_w => c_data_w,
+ nof_dat => 2**g_mult_addr_w,
+ init_sl => '0');
signal rst : std_logic;
signal clk : std_logic := '1';
signal tb_end : std_logic;
@@ -79,7 +80,7 @@ begin
proc_common_wait_some_cycles(clk, 1);
temp := TO_UINT(miso.rddata(31 downto 0));
if(temp /= I + J) then
- report "Error! Readvalue is not as expected" severity ERROR;
+ report "Error! Readvalue is not as expected" severity ERROR;
end if;
end loop;
end loop;
@@ -89,33 +90,33 @@ begin
generation_of_test_rams : for I in 0 to g_nof_mosi - 1 generate
u_test_rams : entity work.common_ram_r_w
+ generic map (
+ g_ram => c_test_ram,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ wr_en => mosi_arr(I).wr,
+ wr_adr => mosi_arr(I).address(g_mult_addr_w - 1 downto 0),
+ wr_dat => mosi_arr(I).wrdata(c_data_w - 1 downto 0),
+ rd_en => mosi_arr(I).rd,
+ rd_adr => mosi_arr(I).address(g_mult_addr_w - 1 downto 0),
+ rd_dat => miso_arr(I).rddata(c_data_w - 1 downto 0),
+ rd_val => miso_arr(I).rdval
+ );
+ end generate;
+
+ d_dut : entity work.common_mem_mux
generic map (
- g_ram => c_test_ram,
- g_init_file => "UNUSED"
+ g_nof_mosi => g_nof_mosi,
+ g_mult_addr_w => g_mult_addr_w
)
port map (
- rst => rst,
- clk => clk,
- clken => '1',
- wr_en => mosi_arr(I).wr,
- wr_adr => mosi_arr(I).address(g_mult_addr_w - 1 downto 0),
- wr_dat => mosi_arr(I).wrdata(c_data_w - 1 downto 0),
- rd_en => mosi_arr(I).rd,
- rd_adr => mosi_arr(I).address(g_mult_addr_w - 1 downto 0),
- rd_dat => miso_arr(I).rddata(c_data_w - 1 downto 0),
- rd_val => miso_arr(I).rdval
+ mosi_arr => mosi_arr,
+ miso_arr => miso_arr,
+ mosi => mosi,
+ miso => miso
);
- end generate;
-
- d_dut : entity work.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_mosi,
- g_mult_addr_w => g_mult_addr_w
- )
- port map (
- mosi_arr => mosi_arr,
- miso_arr => miso_arr,
- mosi => mosi,
- miso => miso
- );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
index 94e5f10bbf..877a4bd4a1 100644
--- a/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
package tb_common_mem_pkg is
------------------------------------------------------------------------------
@@ -35,65 +35,76 @@ package tb_common_mem_pkg is
-- as signal).
-- Write data to the MM bus
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural; -- [31:0]
- constant wr_data : in integer; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_mem_mm_bus_wr(constant wr_addr : in integer; -- [31:0]
- signal wr_data : in std_logic_vector; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural; -- [31:0]
- constant wr_data : in integer; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural; -- [31:0]
- constant wr_data : in std_logic_vector; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_mem_mm_bus_wr(
+ constant wr_addr : in natural; -- [31:0]
+ constant wr_data : in integer; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso; -- used for waitrequest
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_mem_mm_bus_wr(
+ constant wr_addr : in integer; -- [31:0]
+ signal wr_data : in std_logic_vector; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso; -- used for waitrequest
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_mem_mm_bus_wr(
+ constant wr_addr : in natural; -- [31:0]
+ constant wr_data : in integer; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_mem_mm_bus_wr(
+ constant wr_addr : in natural; -- [31:0]
+ constant wr_data : in std_logic_vector; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
-- Read data request to the MM bus
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_mem_mm_bus_rd(
+ constant rd_addr : in natural; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso; -- used for waitrequest
+ signal mm_mosi : out t_mem_mosi);
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_mem_mm_bus_rd(
+ constant rd_addr : in natural; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
-- Wait for read data valid after read latency mm_clk cycles
- procedure proc_mem_mm_bus_rd_latency(constant c_rd_latency : in natural;
- signal mm_clk : in std_logic);
+ procedure proc_mem_mm_bus_rd_latency(
+ constant c_rd_latency : in natural;
+ signal mm_clk : in std_logic);
-- Write array of data words to the memory
- procedure proc_mem_write_ram(constant offset : in natural;
- constant nof_data : in natural;
- constant data_arr : in t_slv_32_arr;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_mem_write_ram(
+ constant offset : in natural;
+ constant nof_data : in natural;
+ constant data_arr : in t_slv_32_arr;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
- procedure proc_mem_write_ram(constant data_arr : in t_slv_32_arr;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_mem_write_ram(
+ constant data_arr : in t_slv_32_arr;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
-- Read array of data words from the memory
- procedure proc_mem_read_ram(constant offset : in natural;
- constant nof_data : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- signal data_arr : out t_slv_32_arr);
-
- procedure proc_mem_read_ram(signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- signal data_arr : out t_slv_32_arr);
+ procedure proc_mem_read_ram(
+ constant offset : in natural;
+ constant nof_data : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ signal data_arr : out t_slv_32_arr);
+
+ procedure proc_mem_read_ram(
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ signal data_arr : out t_slv_32_arr);
end tb_common_mem_pkg;
package body tb_common_mem_pkg is
@@ -102,8 +113,9 @@ package body tb_common_mem_pkg is
------------------------------------------------------------------------------
-- Issues a rd or a wr MM access
- procedure proc_mm_access(signal mm_clk : in std_logic;
- signal mm_access : out std_logic) is
+ procedure proc_mm_access(
+ signal mm_clk : in std_logic;
+ signal mm_access : out std_logic) is
begin
mm_access <= '1';
wait until rising_edge(mm_clk);
@@ -111,9 +123,10 @@ package body tb_common_mem_pkg is
end proc_mm_access;
-- Issues a rd or a wr MM access and wait for it to have finished
- procedure proc_mm_access(signal mm_clk : in std_logic;
- signal mm_waitreq : in std_logic;
- signal mm_access : out std_logic) is
+ procedure proc_mm_access(
+ signal mm_clk : in std_logic;
+ signal mm_waitreq : in std_logic;
+ signal mm_access : out std_logic) is
begin
mm_access <= '1';
wait until rising_edge(mm_clk);
@@ -128,42 +141,46 @@ package body tb_common_mem_pkg is
------------------------------------------------------------------------------
-- Write data to the MM bus
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural;
- constant wr_data : in integer;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_wr(
+ constant wr_addr : in natural;
+ constant wr_data : in integer;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(wr_addr);
mm_mosi.wrdata <= TO_MEM_DATA(wr_data);
proc_mm_access(mm_clk, mm_miso.waitrequest, mm_mosi.wr);
end proc_mem_mm_bus_wr;
- procedure proc_mem_mm_bus_wr(constant wr_addr : in integer;
- signal wr_data : in std_logic_vector;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_wr(
+ constant wr_addr : in integer;
+ signal wr_data : in std_logic_vector;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(wr_addr);
mm_mosi.wrdata <= RESIZE_MEM_DATA(wr_data);
proc_mm_access(mm_clk, mm_miso.waitrequest, mm_mosi.wr);
end proc_mem_mm_bus_wr;
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural;
- constant wr_data : in integer;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_wr(
+ constant wr_addr : in natural;
+ constant wr_data : in integer;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(wr_addr);
mm_mosi.wrdata <= TO_MEM_DATA(wr_data);
proc_mm_access(mm_clk, mm_mosi.wr);
end proc_mem_mm_bus_wr;
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural;
- constant wr_data : in std_logic_vector;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_wr(
+ constant wr_addr : in natural;
+ constant wr_data : in std_logic_vector;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(wr_addr);
mm_mosi.wrdata <= RESIZE_UVEC(wr_data, c_mem_data_w);
@@ -173,18 +190,20 @@ package body tb_common_mem_pkg is
-- Read data request to the MM bus
-- Use proc_mem_mm_bus_rd_latency() to wait for the MM MISO rd_data signal
-- to show the data after some read latency
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_rd(
+ constant rd_addr : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(rd_addr);
proc_mm_access(mm_clk, mm_miso.waitrequest, mm_mosi.rd);
end proc_mem_mm_bus_rd;
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_rd(
+ constant rd_addr : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(rd_addr);
proc_mm_access(mm_clk, mm_mosi.rd);
@@ -192,18 +211,20 @@ package body tb_common_mem_pkg is
-- Wait for read data valid after read latency mm_clk cycles
-- Directly assign mm_miso.rddata to capture the read data
- procedure proc_mem_mm_bus_rd_latency(constant c_rd_latency : in natural;
- signal mm_clk : in std_logic) is
+ procedure proc_mem_mm_bus_rd_latency(
+ constant c_rd_latency : in natural;
+ signal mm_clk : in std_logic) is
begin
for I in 0 to c_rd_latency - 1 loop wait until rising_edge(mm_clk); end loop;
end proc_mem_mm_bus_rd_latency;
-- Write array of data words to the memory
- procedure proc_mem_write_ram(constant offset : in natural;
- constant nof_data : in natural;
- constant data_arr : in t_slv_32_arr;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_write_ram(
+ constant offset : in natural;
+ constant nof_data : in natural;
+ constant data_arr : in t_slv_32_arr;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
constant c_data_arr : t_slv_32_arr(data_arr'length - 1 downto 0) := data_arr; -- map to fixed range [h:0]
begin
for I in 0 to nof_data - 1 loop
@@ -211,9 +232,10 @@ package body tb_common_mem_pkg is
end loop;
end proc_mem_write_ram;
- procedure proc_mem_write_ram(constant data_arr : in t_slv_32_arr;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_write_ram(
+ constant data_arr : in t_slv_32_arr;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
constant c_offset : natural := 0;
constant c_nof_data : natural := data_arr'length;
begin
@@ -221,12 +243,13 @@ package body tb_common_mem_pkg is
end proc_mem_write_ram;
-- Read array of data words from the memory
- procedure proc_mem_read_ram(constant offset : in natural;
- constant nof_data : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- signal data_arr : out t_slv_32_arr) is
+ procedure proc_mem_read_ram(
+ constant offset : in natural;
+ constant nof_data : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ signal data_arr : out t_slv_32_arr) is
begin
for I in 0 to nof_data - 1 loop
proc_mem_mm_bus_rd(offset + I, mm_clk, mm_mosi);
@@ -237,10 +260,11 @@ package body tb_common_mem_pkg is
wait until rising_edge(mm_clk);
end proc_mem_read_ram;
- procedure proc_mem_read_ram(signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- signal data_arr : out t_slv_32_arr) is
+ procedure proc_mem_read_ram(
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ signal data_arr : out t_slv_32_arr) is
constant c_offset : natural := 0;
constant c_nof_data : natural := data_arr'length;
begin
diff --git a/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd b/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
index f07dd4db30..7c7339b88d 100644
--- a/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
@@ -20,21 +20,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
-
--- Purpose: Test bench for common_multiplexer.vhd and common_demultiplexer.vhd
--- Usage:
--- > as 6
--- > run -all
--- The tb p_verify self-checks the output by using first a 1->g_nof_streams
--- demultiplexer and then a g_nof_streams->1 multiplexer. Both the use the
--- same output and input selection so that the expected output data is again
--- the same as the input stimuli data.
--- Remark:
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
+
+ -- Purpose: Test bench for common_multiplexer.vhd and common_demultiplexer.vhd
+ -- Usage:
+ -- > as 6
+ -- > run -all
+ -- The tb p_verify self-checks the output by using first a 1->g_nof_streams
+ -- demultiplexer and then a g_nof_streams->1 multiplexer. Both the use the
+ -- same output and input selection so that the expected output data is again
+ -- the same as the input stimuli data.
+ -- Remark:
entity tb_common_multiplexer is
generic (
@@ -127,59 +127,59 @@ begin
-- . Demultiplex single input to output[in_sel]
u_demux : entity work.common_demultiplexer
- generic map (
- g_pipeline_in => g_pipeline_demux_in,
- g_pipeline_out => g_pipeline_demux_out,
- g_nof_out => g_nof_streams,
- g_dat_w => g_dat_w
- )
- port map(
- rst => rst,
- clk => clk,
-
- in_dat => in_dat,
- in_val => in_val,
-
- out_sel => in_sel,
- out_dat => demux_dat_vec,
- out_val => demux_val_vec
- );
+ generic map (
+ g_pipeline_in => g_pipeline_demux_in,
+ g_pipeline_out => g_pipeline_demux_out,
+ g_nof_out => g_nof_streams,
+ g_dat_w => g_dat_w
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_dat,
+ in_val => in_val,
+
+ out_sel => in_sel,
+ out_dat => demux_dat_vec,
+ out_val => demux_val_vec
+ );
-- . pipeline in_sel to align demux_sel to demux_*_vec
u_pipe_sel : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_pipeline_demux,
- g_in_dat_w => c_sel_w,
- g_out_dat_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sel,
- out_dat => demux_sel
- );
+ generic map (
+ g_pipeline => c_pipeline_demux,
+ g_in_dat_w => c_sel_w,
+ g_out_dat_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sel,
+ out_dat => demux_sel
+ );
demux_val <= demux_val_vec(TO_UINT(demux_sel));
-- . Multiplex input[demux_sel] back to a single output
u_mux : entity work.common_multiplexer
- generic map (
- g_pipeline_in => g_pipeline_mux_in,
- g_pipeline_out => g_pipeline_mux_out,
- g_nof_in => g_nof_streams,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_sel => demux_sel,
- in_dat => demux_dat_vec,
- in_val => demux_val,
-
- out_dat => out_dat,
- out_val => out_val
- );
+ generic map (
+ g_pipeline_in => g_pipeline_mux_in,
+ g_pipeline_out => g_pipeline_mux_out,
+ g_nof_in => g_nof_streams,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_sel => demux_sel,
+ in_dat => demux_dat_vec,
+ in_val => demux_val,
+
+ out_dat => out_dat,
+ out_val => out_val
+ );
------------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
index 255bb24dd4..06f6a93a5a 100644
--- a/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
@@ -29,11 +29,11 @@
-- not equal
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_operation_tree is
generic (
@@ -149,19 +149,19 @@ begin
-- . Pipeline the in_data_vec to align with the result
-- . Map the concatenated dat in in_data_vec into an in_data_arr_p array
u_data_vec_p : entity work.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0,
- g_in_dat_w => c_data_vec_w,
- g_out_dat_w => c_data_vec_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_data_vec,
- out_dat => in_data_vec_p
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0,
+ g_in_dat_w => c_data_vec_w,
+ g_out_dat_w => c_data_vec_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_data_vec,
+ out_dat => in_data_vec_p
+ );
p_data_arr : process(in_data_vec_p)
begin
@@ -173,47 +173,47 @@ begin
expected_comb <= func_result(g_operation, g_representation, in_data_vec);
u_result : entity work.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0,
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => expected_comb,
- out_dat => expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0,
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => expected_comb,
+ out_dat => expected
+ );
u_expected_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => expected_val
- );
+ generic map (
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => expected_val
+ );
dut : entity work.common_operation_tree
- generic map (
- g_operation => g_operation,
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_pipeline_mod => g_pipeline_mod,
- g_nof_inputs => g_nof_inputs,
- g_dat_w => c_dat_w
- )
- port map (
- clk => clk,
- in_data_vec => in_data_vec,
- in_en_vec => in_en_vec,
- result => result
- );
+ generic map (
+ g_operation => g_operation,
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_pipeline_mod => g_pipeline_mod,
+ g_nof_inputs => g_nof_inputs,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ clk => clk,
+ in_data_vec => in_data_vec,
+ in_en_vec => in_en_vec,
+ result => result
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
index ae4a886e08..b633f663e5 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
@@ -21,21 +21,21 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
-
--- Purpose: Test bench for common_paged_ram_crw_crw
---
--- Features:
--- . Use c_gap_sz = 0 to try writing and reading multiple page without idle
--- cycles
--- . Most applications use c_nof_pages = 2, but use > 2 is supported too.
---
--- Usage:
--- > as 10
--- > run -all
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
+
+ -- Purpose: Test bench for common_paged_ram_crw_crw
+ --
+ -- Features:
+ -- . Use c_gap_sz = 0 to try writing and reading multiple page without idle
+ -- cycles
+ -- . Most applications use c_nof_pages = 2, but use > 2 is supported too.
+ --
+ -- Usage:
+ -- > as 10
+ -- > run -all
entity tb_common_paged_ram_crw_crw is
end tb_common_paged_ram_crw_crw;
@@ -123,100 +123,100 @@ begin
end process;
u_dut_mux : entity work.common_paged_ram_crw_crw
- generic map (
- g_str => "use_mux",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_start_page_a => c_start_page_a,
- g_start_page_b => c_start_page_b
- )
- port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => '1',
- clken_b => '1',
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en_b,
- rd_dat_b => mux_rd_dat_b,
- rd_val_b => mux_rd_val_b
- );
+ generic map (
+ g_str => "use_mux",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst_a => rst,
+ rst_b => rst,
+ clk_a => clk,
+ clk_b => clk,
+ clken_a => '1',
+ clken_b => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => mux_rd_dat_b,
+ rd_val_b => mux_rd_val_b
+ );
u_dut_adr : entity work.common_paged_ram_crw_crw
- generic map (
- g_str => "use_adr",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_start_page_a => c_start_page_a,
- g_start_page_b => c_start_page_b
- )
- port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => '1',
- clken_b => '1',
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en_b,
- rd_dat_b => adr_rd_dat_b,
- rd_val_b => adr_rd_val_b
- );
+ generic map (
+ g_str => "use_adr",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst_a => rst,
+ rst_b => rst,
+ clk_a => clk,
+ clk_b => clk,
+ clken_a => '1',
+ clken_b => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => adr_rd_dat_b,
+ rd_val_b => adr_rd_val_b
+ );
u_dut_ofs : entity work.common_paged_ram_crw_crw
- generic map (
- g_str => "use_ofs",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_start_page_a => c_start_page_a,
- g_start_page_b => c_start_page_b
- )
- port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => '1',
- clken_b => '1',
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en_b,
- rd_dat_b => ofs_rd_dat_b,
- rd_val_b => ofs_rd_val_b
- );
+ generic map (
+ g_str => "use_ofs",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst_a => rst,
+ rst_b => rst,
+ clk_a => clk,
+ clk_b => clk,
+ clken_a => '1',
+ clken_b => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => ofs_rd_dat_b,
+ rd_val_b => ofs_rd_val_b
+ );
-- Verify that the read data is incrementing data
proc_common_verify_data(c_rl, clk, verify_en, ready, mux_rd_val_b, mux_rd_dat_b, prev_mux_rd_dat_b);
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
index 5b632a2f4c..7d4ee088a6 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
@@ -21,22 +21,22 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
-
--- Purpose: Test bench for common_paged_ram_ww_rr
--- Description:
--- Verifies two DUTs ww_rr and w_rr using incrementing data.
--- Features:
--- . Page size can be any size g_page_sz >= 1, so not only powers of 2
--- . Use c_gap_sz = 0 to try writing and reading multiple page without idle
--- cycles
---
--- Usage:
--- > as 10
--- > run -all
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
+
+ -- Purpose: Test bench for common_paged_ram_ww_rr
+ -- Description:
+ -- Verifies two DUTs ww_rr and w_rr using incrementing data.
+ -- Features:
+ -- . Page size can be any size g_page_sz >= 1, so not only powers of 2
+ -- . Use c_gap_sz = 0 to try writing and reading multiple page without idle
+ -- cycles
+ --
+ -- Usage:
+ -- > as 10
+ -- > run -all
entity tb_common_paged_ram_ww_rr is
generic (
@@ -182,66 +182,66 @@ begin
-- Double write - double read
u_dut_ww_rr : entity work.common_paged_ram_ww_rr
- generic map (
- g_pipeline_in => g_pipeline_in,
- g_pipeline_out => g_pipeline_out,
- g_data_w => c_data_w,
- g_page_sz => g_page_sz
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- -- next page control
- next_page => next_page,
- -- double write access to one page
- wr_adr_a => wr_adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- wr_adr_b => wr_adr_b,
- wr_en_b => wr_en_b,
- wr_dat_b => wr_dat_b,
- -- double read access from the other one page
- rd_adr_a => rd_adr_a,
- rd_en_a => rd_en_a,
- rd_adr_b => rd_adr_b,
- rd_en_b => rd_en_b,
- -- double read data from the other one page after c_rd_latency
- rd_dat_a => wwrr_rd_dat_a,
- rd_val_a => wwrr_rd_val_a,
- rd_dat_b => wwrr_rd_dat_b,
- rd_val_b => wwrr_rd_val_b
- );
+ generic map (
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_out => g_pipeline_out,
+ g_data_w => c_data_w,
+ g_page_sz => g_page_sz
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ -- next page control
+ next_page => next_page,
+ -- double write access to one page
+ wr_adr_a => wr_adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ wr_adr_b => wr_adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ -- double read access from the other one page
+ rd_adr_a => rd_adr_a,
+ rd_en_a => rd_en_a,
+ rd_adr_b => rd_adr_b,
+ rd_en_b => rd_en_b,
+ -- double read data from the other one page after c_rd_latency
+ rd_dat_a => wwrr_rd_dat_a,
+ rd_val_a => wwrr_rd_val_a,
+ rd_dat_b => wwrr_rd_dat_b,
+ rd_val_b => wwrr_rd_val_b
+ );
-- Single write - double read
u_dut_w_rr : entity work.common_paged_ram_w_rr
- generic map (
- g_pipeline_in => g_pipeline_in,
- g_pipeline_out => g_pipeline_out,
- g_data_w => c_data_w,
- g_page_sz => g_page_sz
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- -- next page control
- next_page => next_page,
- -- double write access to one page
- wr_adr => in_adr,
- wr_en => in_en,
- wr_dat => in_dat,
- -- double read access from the other one page
- rd_adr_a => rd_adr_a,
- rd_en_a => rd_en_a,
- rd_adr_b => rd_adr_b,
- rd_en_b => rd_en_b,
- -- double read data from the other one page after c_rd_latency
- rd_dat_a => wrr_rd_dat_a,
- rd_val_a => wrr_rd_val_a,
- rd_dat_b => wrr_rd_dat_b,
- rd_val_b => wrr_rd_val_b
- );
+ generic map (
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_out => g_pipeline_out,
+ g_data_w => c_data_w,
+ g_page_sz => g_page_sz
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ -- next page control
+ next_page => next_page,
+ -- double write access to one page
+ wr_adr => in_adr,
+ wr_en => in_en,
+ wr_dat => in_dat,
+ -- double read access from the other one page
+ rd_adr_a => rd_adr_a,
+ rd_en_a => rd_en_a,
+ rd_adr_b => rd_adr_b,
+ rd_en_b => rd_en_b,
+ -- double read data from the other one page after c_rd_latency
+ rd_dat_a => wrr_rd_dat_a,
+ rd_val_a => wrr_rd_val_a,
+ rd_dat_b => wrr_rd_dat_b,
+ rd_val_b => wrr_rd_val_b
+ );
------------------------------------------------------------------------------
-- Verify
diff --git a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
index de11904870..4f5c9be24a 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
@@ -30,11 +30,11 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use std.textio.all; -- for boolean, integer file IO
-use IEEE.std_logic_textio.all; -- for std_logic, std_logic_vector file IO
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use std.textio.all; -- for boolean, integer file IO
+ use IEEE.std_logic_textio.all; -- for std_logic, std_logic_vector file IO
+ use work.common_pkg.all;
package tb_common_pkg is
-- Constants
@@ -47,282 +47,338 @@ package tb_common_pkg is
constant c_common_cross_clock_domain_latency : natural := 20;
-- Wait for some time or until
- procedure proc_common_wait_some_cycles(signal clk : in std_logic;
- c_nof_cycles : in natural);
-
- procedure proc_common_wait_some_cycles(signal clk : in std_logic;
- c_nof_cycles : in real);
-
- procedure proc_common_wait_some_cycles(signal clk_in : in std_logic;
- signal clk_out : in std_logic;
- c_nof_cycles : in natural);
-
- procedure proc_common_wait_some_pulses(signal clk : in std_logic;
- signal pulse : in std_logic;
- c_nof_pulses : in natural);
-
- procedure proc_common_wait_until_evt(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_evt(signal clk : in std_logic;
- signal level : in integer);
-
- procedure proc_common_wait_until_evt(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_high(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_high(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_clk_and_high(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_low(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_low(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_clk_and_low(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_hi_lo(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_hi_lo(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_lo_hi(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_lo_hi(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_value(constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in integer);
-
- procedure proc_common_wait_until_value(constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in std_logic_vector);
-
- procedure proc_common_wait_until_value(constant c_timeout : in natural;
- constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in std_logic_vector);
+ procedure proc_common_wait_some_cycles(
+ signal clk : in std_logic;
+ c_nof_cycles : in natural);
+
+ procedure proc_common_wait_some_cycles(
+ signal clk : in std_logic;
+ c_nof_cycles : in real);
+
+ procedure proc_common_wait_some_cycles(
+ signal clk_in : in std_logic;
+ signal clk_out : in std_logic;
+ c_nof_cycles : in natural);
+
+ procedure proc_common_wait_some_pulses(
+ signal clk : in std_logic;
+ signal pulse : in std_logic;
+ c_nof_pulses : in natural);
+
+ procedure proc_common_wait_until_evt(
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_evt(
+ signal clk : in std_logic;
+ signal level : in integer);
+
+ procedure proc_common_wait_until_evt(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_high(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_high(
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_clk_and_high(
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_low(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_low(
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_clk_and_low(
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_hi_lo(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_hi_lo(
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_lo_hi(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_lo_hi(
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_value(
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in integer);
+
+ procedure proc_common_wait_until_value(
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in std_logic_vector);
+
+ procedure proc_common_wait_until_value(
+ constant c_timeout : in natural;
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in std_logic_vector);
-- Wait until absolute simulation time NOW = c_time
- procedure proc_common_wait_until_time(signal clk : in std_logic;
- constant c_time : in time);
+ procedure proc_common_wait_until_time(
+ signal clk : in std_logic;
+ constant c_time : in time);
-- Exit simulation on timeout failure
- procedure proc_common_timeout_failure(constant c_timeout : in time;
- signal tb_end : in std_logic);
+ procedure proc_common_timeout_failure(
+ constant c_timeout : in time;
+ signal tb_end : in std_logic);
-- Stop simulation using severity FAILURE when g_tb_end=TRUE, else for use in multi tb report as severity NOTE
- procedure proc_common_stop_simulation(signal tb_end : in std_logic);
-
- procedure proc_common_stop_simulation(constant g_tb_end : in boolean;
- constant g_latency : in natural; -- latency between tb_done and tb_)end
- signal clk : in std_logic;
- signal tb_done : in std_logic;
- signal tb_end : out std_logic);
-
- procedure proc_common_stop_simulation(constant g_tb_end : in boolean;
- signal clk : in std_logic;
- signal tb_done : in std_logic;
- signal tb_end : out std_logic);
+ procedure proc_common_stop_simulation(
+ signal tb_end : in std_logic);
+
+ procedure proc_common_stop_simulation(
+ constant g_tb_end : in boolean;
+ constant g_latency : in natural; -- latency between tb_done and tb_)end
+ signal clk : in std_logic;
+ signal tb_done : in std_logic;
+ signal tb_end : out std_logic);
+
+ procedure proc_common_stop_simulation(
+ constant g_tb_end : in boolean;
+ signal clk : in std_logic;
+ signal tb_done : in std_logic;
+ signal tb_end : out std_logic);
-- Handle stream ready signal, only support ready latency c_rl = 0 or 1.
- procedure proc_common_ready_latency(constant c_rl : in natural;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '1' then active output when ready
- signal ready : in std_logic;
- signal out_valid : out std_logic);
+ procedure proc_common_ready_latency(
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '1' then active output when ready
+ signal ready : in std_logic;
+ signal out_valid : out std_logic);
-- Wait for clock domain crossing latency, e.g. for MM readback after MM write
- procedure proc_common_wait_cross_clock_domain_latency(signal mm_clk : in std_logic;
- signal st_clk : in std_logic;
- constant c_nof_cycles : in natural);
+ procedure proc_common_wait_cross_clock_domain_latency(
+ signal mm_clk : in std_logic;
+ signal st_clk : in std_logic;
+ constant c_nof_cycles : in natural);
- procedure proc_common_wait_cross_clock_domain_latency(signal mm_clk : in std_logic;
- signal st_clk : in std_logic);
+ procedure proc_common_wait_cross_clock_domain_latency(
+ signal mm_clk : in std_logic;
+ signal st_clk : in std_logic);
- procedure proc_common_wait_cross_clock_domain_latency(constant c_mm_clk_period : in time;
- constant c_st_clk_period : in time;
- constant c_nof_cycles : in natural);
+ procedure proc_common_wait_cross_clock_domain_latency(
+ constant c_mm_clk_period : in time;
+ constant c_st_clk_period : in time;
+ constant c_nof_cycles : in natural);
- procedure proc_common_wait_cross_clock_domain_latency(constant c_mm_clk_period : in time;
- constant c_st_clk_period : in time);
+ procedure proc_common_wait_cross_clock_domain_latency(
+ constant c_mm_clk_period : in time;
+ constant c_st_clk_period : in time);
-- Generate a single active, inactive pulse
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal clk : in std_logic;
- signal pulse : out std_logic);
+ procedure proc_common_gen_pulse(
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal clk : in std_logic;
+ signal pulse : out std_logic);
-- Pulse forever after rst was released
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal pulse : out std_logic);
+ procedure proc_common_gen_pulse(
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal pulse : out std_logic);
-- Generate a single '1', '0' pulse
- procedure proc_common_gen_pulse(signal clk : in std_logic;
- signal pulse : out std_logic);
+ procedure proc_common_gen_pulse(
+ signal clk : in std_logic;
+ signal pulse : out std_logic);
-- Generate a periodic pulse with arbitrary duty cycle
- procedure proc_common_gen_duty_pulse(constant c_delay : in natural; -- delay pulse for nof_clk after enable
- constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- once enabled, the pulse remains enabled
- signal pulse : out std_logic);
-
- procedure proc_common_gen_duty_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- once enabled, the pulse remains enabled
- signal pulse : out std_logic);
+ procedure proc_common_gen_duty_pulse(
+ constant c_delay : in natural; -- delay pulse for nof_clk after enable
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- once enabled, the pulse remains enabled
+ signal pulse : out std_logic);
+
+ procedure proc_common_gen_duty_pulse(
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- once enabled, the pulse remains enabled
+ signal pulse : out std_logic);
-- Generate counter data with valid and arbitrary increment or fixed increment=1
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
- constant c_init : in integer;
- constant c_incr : in integer;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
- signal ready : in std_logic;
- signal out_data : out std_logic_vector;
- signal out_valid : out std_logic);
-
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
- constant c_init : in integer;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
- signal ready : in std_logic;
- signal out_data : out std_logic_vector;
- signal out_valid : out std_logic);
+ procedure proc_common_gen_data(
+ constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
+ constant c_init : in integer;
+ constant c_incr : in integer;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ signal ready : in std_logic;
+ signal out_data : out std_logic_vector;
+ signal out_valid : out std_logic);
+
+ procedure proc_common_gen_data(
+ constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
+ constant c_init : in integer;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ signal ready : in std_logic;
+ signal out_data : out std_logic_vector;
+ signal out_valid : out std_logic);
-- Generate frame control
- procedure proc_common_sop(signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_sop : out std_logic);
-
- procedure proc_common_eop(signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_eop : out std_logic);
-
- procedure proc_common_val(constant c_val_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic);
-
- procedure proc_common_val_duty(constant c_hi_len : in natural;
- constant c_lo_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic);
-
- procedure proc_common_eop_flush(constant c_flush_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_eop : out std_logic);
+ procedure proc_common_sop(
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_sop : out std_logic);
+
+ procedure proc_common_eop(
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_eop : out std_logic);
+
+ procedure proc_common_val(
+ constant c_val_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic);
+
+ procedure proc_common_val_duty(
+ constant c_hi_len : in natural;
+ constant c_lo_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic);
+
+ procedure proc_common_eop_flush(
+ constant c_flush_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_eop : out std_logic);
-- Verify the DUT output incrementing data, only support ready latency c_rl = 0 or 1.
- procedure proc_common_verify_data(constant c_rl : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal ready : in std_logic;
- signal out_valid : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector);
+ procedure proc_common_verify_data(
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal ready : in std_logic;
+ signal out_valid : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector);
-- Verify the DUT output valid for ready latency, only support ready latency c_rl = 0 or 1.
- procedure proc_common_verify_valid(constant c_rl : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal ready : in std_logic;
- signal prev_ready : inout std_logic;
- signal out_valid : in std_logic);
+ procedure proc_common_verify_valid(
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal ready : in std_logic;
+ signal prev_ready : inout std_logic;
+ signal out_valid : in std_logic);
-- Verify the DUT input to output latency for SL ctrl signals
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "valid", "sop", "eop"
- constant c_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal in_ctrl : in std_logic;
- signal pipe_ctrl_vec : inout std_logic_vector; -- range [0:c_latency]
- signal out_ctrl : in std_logic);
+ procedure proc_common_verify_latency(
+ constant c_str : in string; -- e.g. "valid", "sop", "eop"
+ constant c_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal in_ctrl : in std_logic;
+ signal pipe_ctrl_vec : inout std_logic_vector; -- range [0:c_latency]
+ signal out_ctrl : in std_logic);
-- Verify the DUT input to output latency for SLV data signals
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "data"
- constant c_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal in_data : in std_logic_vector;
- signal pipe_data_vec : inout std_logic_vector; -- range [0:(1 + c_latency)*c_data_w-1]
- signal out_data : in std_logic_vector);
+ procedure proc_common_verify_latency(
+ constant c_str : in string; -- e.g. "data"
+ constant c_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal in_data : in std_logic_vector;
+ signal pipe_data_vec : inout std_logic_vector; -- range [0:(1 + c_latency)*c_data_w-1]
+ signal out_data : in std_logic_vector);
-- Verify the expected value, e.g. to check that a test has ran at all
- procedure proc_common_verify_value(constant mode : in natural;
- signal clk : in std_logic;
- signal en : in std_logic;
- signal exp : in std_logic_vector;
- signal res : in std_logic_vector);
+ procedure proc_common_verify_value(
+ constant mode : in natural;
+ signal clk : in std_logic;
+ signal en : in std_logic;
+ signal exp : in std_logic_vector;
+ signal res : in std_logic_vector);
-- open, read line, close file
- procedure proc_common_open_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- file_name : in string;
- file_mode : in FILE_OPEN_KIND);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_value_0 : out integer);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_value_0 : out integer;
- read_value_1 : out integer);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- value_array : out t_integer_arr;
- nof_reads : in integer);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_slv : out std_logic_vector);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- res_string : out string);
-
- procedure proc_common_close_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT);
+ procedure proc_common_open_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ file_name : in string;
+ file_mode : in FILE_OPEN_KIND);
+
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_value_0 : out integer);
+
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_value_0 : out integer;
+ read_value_1 : out integer);
+
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ value_array : out t_integer_arr;
+ nof_reads : in integer);
+
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_slv : out std_logic_vector);
+
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ res_string : out string);
+
+ procedure proc_common_close_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT);
-- read entire file
- procedure proc_common_read_integer_file(file_name : in string;
- nof_header_lines : natural;
- nof_row : natural;
- nof_col : natural;
- signal return_array : out t_integer_arr);
+ procedure proc_common_read_integer_file(
+ file_name : in string;
+ nof_header_lines : natural;
+ nof_row : natural;
+ nof_col : natural;
+ signal return_array : out t_integer_arr);
- procedure proc_common_read_mif_file(file_name : in string;
- signal return_array : out t_integer_arr);
+ procedure proc_common_read_mif_file(
+ file_name : in string;
+ signal return_array : out t_integer_arr);
-- Complex multiply function with conjugate option for input b
function func_complex_multiply(in_ar, in_ai, in_br, in_bi : std_logic_vector; conjugate_b : boolean; str : string; g_out_dat_w : natural) return std_logic_vector;
@@ -340,21 +396,24 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Wait some clock cycles
------------------------------------------------------------------------------
- procedure proc_common_wait_some_cycles(signal clk : in std_logic;
- c_nof_cycles : in natural) is
+ procedure proc_common_wait_some_cycles(
+ signal clk : in std_logic;
+ c_nof_cycles : in natural) is
begin
for I in 0 to c_nof_cycles - 1 loop wait until rising_edge(clk); end loop;
end proc_common_wait_some_cycles;
- procedure proc_common_wait_some_cycles(signal clk : in std_logic;
- c_nof_cycles : in real) is
+ procedure proc_common_wait_some_cycles(
+ signal clk : in std_logic;
+ c_nof_cycles : in real) is
begin
proc_common_wait_some_cycles(clk, natural(c_nof_cycles));
end proc_common_wait_some_cycles;
- procedure proc_common_wait_some_cycles(signal clk_in : in std_logic;
- signal clk_out : in std_logic;
- c_nof_cycles : in natural) is
+ procedure proc_common_wait_some_cycles(
+ signal clk_in : in std_logic;
+ signal clk_out : in std_logic;
+ c_nof_cycles : in natural) is
begin
proc_common_wait_some_cycles(clk_in, c_nof_cycles);
proc_common_wait_some_cycles(clk_out, c_nof_cycles);
@@ -363,9 +422,10 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Wait some pulses
------------------------------------------------------------------------------
- procedure proc_common_wait_some_pulses(signal clk : in std_logic;
- signal pulse : in std_logic;
- c_nof_pulses : in natural) is
+ procedure proc_common_wait_some_pulses(
+ signal clk : in std_logic;
+ signal pulse : in std_logic;
+ c_nof_pulses : in natural) is
begin
for I in 0 to c_nof_pulses - 1 loop
proc_common_wait_until_hi_lo(clk, pulse);
@@ -378,8 +438,9 @@ package body tb_common_pkg is
-- PROCEDURE: Wait until the level input is low
-- PROCEDURE: Wait until the input is equal to c_value
------------------------------------------------------------------------------
- procedure proc_common_wait_until_evt(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_evt(
+ signal clk : in std_logic;
+ signal level : in std_logic) is
variable v_level : std_logic := level;
begin
wait until rising_edge(clk);
@@ -389,8 +450,9 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_evt;
- procedure proc_common_wait_until_evt(signal clk : in std_logic;
- signal level : in integer) is
+ procedure proc_common_wait_until_evt(
+ signal clk : in std_logic;
+ signal level : in integer) is
variable v_level : integer := level;
begin
wait until rising_edge(clk);
@@ -400,9 +462,10 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_evt;
- procedure proc_common_wait_until_evt(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_evt(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
variable v_level : std_logic := level;
variable v_I : natural := 0;
begin
@@ -418,23 +481,26 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_evt;
- procedure proc_common_wait_until_high(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_high(
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '1' then
wait until rising_edge(clk) and level = '1';
end if;
end proc_common_wait_until_high;
- procedure proc_common_wait_until_clk_and_high(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_clk_and_high(
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
wait until rising_edge(clk) and level = '1';
end proc_common_wait_until_clk_and_high;
- procedure proc_common_wait_until_high(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_high(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
for I in 0 to c_timeout - 1 loop
if level = '1' then
@@ -448,23 +514,26 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_high;
- procedure proc_common_wait_until_low(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_low(
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '0' then
wait until rising_edge(clk) and level = '0';
end if;
end proc_common_wait_until_low;
- procedure proc_common_wait_until_clk_and_low(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_clk_and_low(
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
wait until rising_edge(clk) and level = '0';
end proc_common_wait_until_clk_and_low;
- procedure proc_common_wait_until_low(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_low(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
for I in 0 to c_timeout - 1 loop
if level = '0' then
@@ -478,8 +547,9 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_low;
- procedure proc_common_wait_until_hi_lo(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_hi_lo(
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '1' then
proc_common_wait_until_high(clk, level);
@@ -487,9 +557,10 @@ package body tb_common_pkg is
proc_common_wait_until_low(clk, level);
end proc_common_wait_until_hi_lo;
- procedure proc_common_wait_until_hi_lo(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_hi_lo(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '1' then
proc_common_wait_until_high(c_timeout, clk, level);
@@ -497,8 +568,9 @@ package body tb_common_pkg is
proc_common_wait_until_low(c_timeout, clk, level);
end proc_common_wait_until_hi_lo;
- procedure proc_common_wait_until_lo_hi(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_lo_hi(
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '0' then
proc_common_wait_until_low(clk, level);
@@ -506,9 +578,10 @@ package body tb_common_pkg is
proc_common_wait_until_high(clk, level);
end proc_common_wait_until_lo_hi;
- procedure proc_common_wait_until_lo_hi(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_lo_hi(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '0' then
proc_common_wait_until_low(c_timeout, clk, level);
@@ -516,28 +589,31 @@ package body tb_common_pkg is
proc_common_wait_until_high(c_timeout, clk, level);
end proc_common_wait_until_lo_hi;
- procedure proc_common_wait_until_value(constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in integer) is
+ procedure proc_common_wait_until_value(
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in integer) is
begin
while level /= c_value loop
wait until rising_edge(clk);
end loop;
end proc_common_wait_until_value;
- procedure proc_common_wait_until_value(constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in std_logic_vector) is
+ procedure proc_common_wait_until_value(
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in std_logic_vector) is
begin
while signed(level) /= c_value loop
wait until rising_edge(clk);
end loop;
end proc_common_wait_until_value;
- procedure proc_common_wait_until_value(constant c_timeout : in natural;
- constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in std_logic_vector) is
+ procedure proc_common_wait_until_value(
+ constant c_timeout : in natural;
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in std_logic_vector) is
begin
for I in 0 to c_timeout - 1 loop
if signed(level) = c_value then
@@ -551,16 +627,18 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_value;
- procedure proc_common_wait_until_time(signal clk : in std_logic;
- constant c_time : in time) is
+ procedure proc_common_wait_until_time(
+ signal clk : in std_logic;
+ constant c_time : in time) is
begin
while NOW < c_time loop
wait until rising_edge(clk);
end loop;
end procedure;
- procedure proc_common_timeout_failure(constant c_timeout : in time;
- signal tb_end : in std_logic) is
+ procedure proc_common_timeout_failure(
+ constant c_timeout : in time;
+ signal tb_end : in std_logic) is
begin
while tb_end = '0' loop
assert NOW < c_timeout report "Test bench timeout." severity ERROR;
@@ -580,11 +658,12 @@ package body tb_common_pkg is
wait;
end procedure;
- procedure proc_common_stop_simulation(constant g_tb_end : in boolean;
- constant g_latency : in natural;
- signal clk : in std_logic;
- signal tb_done : in std_logic;
- signal tb_end : out std_logic) is
+ procedure proc_common_stop_simulation(
+ constant g_tb_end : in boolean;
+ constant g_latency : in natural;
+ signal clk : in std_logic;
+ signal tb_done : in std_logic;
+ signal tb_end : out std_logic) is
begin
-- Wait until simulation indicates done
proc_common_wait_until_high(clk, tb_done);
@@ -606,10 +685,11 @@ package body tb_common_pkg is
wait;
end procedure;
- procedure proc_common_stop_simulation(constant g_tb_end : in boolean;
- signal clk : in std_logic;
- signal tb_done : in std_logic;
- signal tb_end : out std_logic) is
+ procedure proc_common_stop_simulation(
+ constant g_tb_end : in boolean;
+ signal clk : in std_logic;
+ signal tb_done : in std_logic;
+ signal tb_end : out std_logic) is
begin
proc_common_stop_simulation(g_tb_end, 0, clk, tb_done, tb_end);
end procedure;
@@ -619,11 +699,12 @@ package body tb_common_pkg is
-- . output active when ready='1' and enable='1'
-- . only support ready latency c_rl = 0 or 1
------------------------------------------------------------------------------
- procedure proc_common_ready_latency(constant c_rl : in natural;
- signal clk : in std_logic;
- signal enable : in std_logic;
- signal ready : in std_logic;
- signal out_valid : out std_logic) is
+ procedure proc_common_ready_latency(
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal enable : in std_logic;
+ signal ready : in std_logic;
+ signal out_valid : out std_logic) is
begin
-- skip ready cycles until enable='1'
out_valid <= '0';
@@ -663,31 +744,35 @@ package body tb_common_pkg is
-- PROCEDURE: Wait for clock domain crossing latency, e.g. for MM readback after MM write
------------------------------------------------------------------------------
- procedure proc_common_wait_cross_clock_domain_latency(signal mm_clk : in std_logic;
- signal st_clk : in std_logic;
- constant c_nof_cycles : in natural) is
+ procedure proc_common_wait_cross_clock_domain_latency(
+ signal mm_clk : in std_logic;
+ signal st_clk : in std_logic;
+ constant c_nof_cycles : in natural) is
begin
proc_common_wait_some_cycles(mm_clk, c_nof_cycles);
proc_common_wait_some_cycles(st_clk, c_nof_cycles);
end proc_common_wait_cross_clock_domain_latency;
- procedure proc_common_wait_cross_clock_domain_latency(signal mm_clk : in std_logic;
- signal st_clk : in std_logic) is
+ procedure proc_common_wait_cross_clock_domain_latency(
+ signal mm_clk : in std_logic;
+ signal st_clk : in std_logic) is
begin
proc_common_wait_some_cycles(mm_clk, c_common_cross_clock_domain_latency);
proc_common_wait_some_cycles(st_clk, c_common_cross_clock_domain_latency);
end proc_common_wait_cross_clock_domain_latency;
- procedure proc_common_wait_cross_clock_domain_latency(constant c_mm_clk_period : in time;
- constant c_st_clk_period : in time;
- constant c_nof_cycles : in natural) is
+ procedure proc_common_wait_cross_clock_domain_latency(
+ constant c_mm_clk_period : in time;
+ constant c_st_clk_period : in time;
+ constant c_nof_cycles : in natural) is
begin
wait for c_nof_cycles * c_mm_clk_period;
wait for c_nof_cycles * c_st_clk_period;
end proc_common_wait_cross_clock_domain_latency;
- procedure proc_common_wait_cross_clock_domain_latency(constant c_mm_clk_period : in time;
- constant c_st_clk_period : in time) is
+ procedure proc_common_wait_cross_clock_domain_latency(
+ constant c_mm_clk_period : in time;
+ constant c_st_clk_period : in time) is
begin
wait for c_common_cross_clock_domain_latency * c_mm_clk_period;
wait for c_common_cross_clock_domain_latency * c_st_clk_period;
@@ -696,11 +781,12 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Generate a single active, inactive pulse
------------------------------------------------------------------------------
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal clk : in std_logic;
- signal pulse : out std_logic) is
+ procedure proc_common_gen_pulse(
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal clk : in std_logic;
+ signal pulse : out std_logic) is
variable v_cnt : natural range 0 to c_period := 0;
begin
while v_cnt < c_period loop
@@ -715,12 +801,13 @@ package body tb_common_pkg is
end proc_common_gen_pulse;
-- Pulse forever after rst was released
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal pulse : out std_logic) is
+ procedure proc_common_gen_pulse(
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal pulse : out std_logic) is
variable v_cnt : natural range 0 to c_period := 0;
begin
pulse <= not c_level;
@@ -733,8 +820,9 @@ package body tb_common_pkg is
end proc_common_gen_pulse;
-- pulse '1', '0'
- procedure proc_common_gen_pulse(signal clk : in std_logic;
- signal pulse : out std_logic) is
+ procedure proc_common_gen_pulse(
+ signal clk : in std_logic;
+ signal pulse : out std_logic) is
begin
proc_common_gen_pulse(1, 2, '1', clk, pulse);
end proc_common_gen_pulse;
@@ -742,14 +830,15 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Generate a periodic pulse with arbitrary duty cycle
------------------------------------------------------------------------------
- procedure proc_common_gen_duty_pulse(constant c_delay : in natural; -- delay pulse for nof_clk after enable
- constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic;
- signal pulse : out std_logic) is
+ procedure proc_common_gen_duty_pulse(
+ constant c_delay : in natural; -- delay pulse for nof_clk after enable
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic;
+ signal pulse : out std_logic) is
variable v_cnt : natural range 0 to c_period - 1 := 0;
begin
pulse <= not c_level;
@@ -772,13 +861,14 @@ package body tb_common_pkg is
end if;
end proc_common_gen_duty_pulse;
- procedure proc_common_gen_duty_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic;
- signal pulse : out std_logic) is
+ procedure proc_common_gen_duty_pulse(
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic;
+ signal pulse : out std_logic) is
begin
proc_common_gen_duty_pulse(0, c_active, c_period, c_level, rst, clk, enable, pulse);
end proc_common_gen_duty_pulse;
@@ -788,39 +878,41 @@ package body tb_common_pkg is
-- . Output counter data dependent on enable and ready
------------------------------------------------------------------------------
-- arbitrary c_incr
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
- constant c_init : in integer;
- constant c_incr : in integer;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
- signal ready : in std_logic;
- signal out_data : out std_logic_vector;
- signal out_valid : out std_logic) is
+ procedure proc_common_gen_data(
+ constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
+ constant c_init : in integer;
+ constant c_incr : in integer;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ signal ready : in std_logic;
+ signal out_data : out std_logic_vector;
+ signal out_valid : out std_logic) is
constant c_data_w : natural := out_data'length;
variable v_data : std_logic_vector(c_data_w - 1 downto 0) := TO_SVEC(c_init, c_data_w);
begin
- out_valid <= '0';
- out_data <= v_data;
- if rst = '0' then
- wait until rising_edge(clk);
- while true loop
- out_data <= v_data;
- proc_common_ready_latency(c_rl, clk, enable, ready, out_valid);
- v_data := INCR_UVEC(v_data, c_incr);
- end loop;
- end if;
+ out_valid <= '0';
+ out_data <= v_data;
+ if rst = '0' then
+ wait until rising_edge(clk);
+ while true loop
+ out_data <= v_data;
+ proc_common_ready_latency(c_rl, clk, enable, ready, out_valid);
+ v_data := INCR_UVEC(v_data, c_incr);
+ end loop;
+ end if;
end proc_common_gen_data;
-- c_incr = 1
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
- constant c_init : in integer;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
- signal ready : in std_logic;
- signal out_data : out std_logic_vector;
- signal out_valid : out std_logic) is
+ procedure proc_common_gen_data(
+ constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
+ constant c_init : in integer;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ signal ready : in std_logic;
+ signal out_data : out std_logic_vector;
+ signal out_valid : out std_logic) is
begin
proc_common_gen_data(c_rl, c_init, 1, rst, clk, enable, ready, out_data, out_valid);
end proc_common_gen_data;
@@ -828,9 +920,10 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Generate frame control
------------------------------------------------------------------------------
- procedure proc_common_sop(signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_sop : out std_logic) is
+ procedure proc_common_sop(
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_sop : out std_logic) is
begin
in_val <= '1';
in_sop <= '1';
@@ -838,9 +931,10 @@ package body tb_common_pkg is
in_sop <= '0';
end proc_common_sop;
- procedure proc_common_eop(signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_eop : out std_logic) is
+ procedure proc_common_eop(
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_eop : out std_logic) is
begin
in_val <= '1';
in_eop <= '1';
@@ -849,19 +943,21 @@ package body tb_common_pkg is
in_eop <= '0';
end proc_common_eop;
- procedure proc_common_val(constant c_val_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic) is
+ procedure proc_common_val(
+ constant c_val_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic) is
begin
in_val <= '1';
proc_common_wait_some_cycles(clk, c_val_len);
in_val <= '0';
end proc_common_val;
- procedure proc_common_val_duty(constant c_hi_len : in natural;
- constant c_lo_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic) is
+ procedure proc_common_val_duty(
+ constant c_hi_len : in natural;
+ constant c_lo_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic) is
begin
in_val <= '1';
proc_common_wait_some_cycles(clk, c_hi_len);
@@ -869,10 +965,11 @@ package body tb_common_pkg is
proc_common_wait_some_cycles(clk, c_lo_len);
end proc_common_val_duty;
- procedure proc_common_eop_flush(constant c_flush_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_eop : out std_logic) is
+ procedure proc_common_eop_flush(
+ constant c_flush_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_eop : out std_logic) is
begin
-- . eop
proc_common_eop(clk, in_val, in_eop);
@@ -883,41 +980,43 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Verify incrementing data
------------------------------------------------------------------------------
- procedure proc_common_verify_data(constant c_rl : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal ready : in std_logic;
- signal out_valid : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector) is
+ procedure proc_common_verify_data(
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal ready : in std_logic;
+ signal out_valid : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector) is
variable v_exp_data : std_logic_vector(out_data'range);
begin
- if rising_edge(clk) then
- -- out_valid must be active, because only the out_data will it differ from the previous out_data
- if out_valid = '1' then
- -- for ready_latency = 1 out_valid indicates new data
- -- for ready_latency = 0 out_valid only indicates new data when it is confirmed by ready
- if c_rl = 1 or (c_rl = 0 and ready = '1') then
- prev_out_data <= out_data;
- v_exp_data := INCR_UVEC(prev_out_data, 1); -- increment first then compare to also support increment wrap around
- if verify_en = '1' and unsigned(out_data) /= unsigned(v_exp_data) then
- report "COMMON : Wrong out_data count" severity ERROR;
- end if;
+ if rising_edge(clk) then
+ -- out_valid must be active, because only the out_data will it differ from the previous out_data
+ if out_valid = '1' then
+ -- for ready_latency = 1 out_valid indicates new data
+ -- for ready_latency = 0 out_valid only indicates new data when it is confirmed by ready
+ if c_rl = 1 or (c_rl = 0 and ready = '1') then
+ prev_out_data <= out_data;
+ v_exp_data := INCR_UVEC(prev_out_data, 1); -- increment first then compare to also support increment wrap around
+ if verify_en = '1' and unsigned(out_data) /= unsigned(v_exp_data) then
+ report "COMMON : Wrong out_data count" severity ERROR;
end if;
end if;
end if;
+ end if;
end proc_common_verify_data;
------------------------------------------------------------------------------
-- PROCEDURE: Verify the DUT output valid
-- . only support ready latency c_rl = 0 or 1
------------------------------------------------------------------------------
- procedure proc_common_verify_valid(constant c_rl : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal ready : in std_logic;
- signal prev_ready : inout std_logic;
- signal out_valid : in std_logic) is
+ procedure proc_common_verify_valid(
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal ready : in std_logic;
+ signal prev_ready : inout std_logic;
+ signal out_valid : in std_logic) is
begin
if rising_edge(clk) then
-- for ready latency c_rl = 1 out_valid may only be asserted after ready
@@ -938,13 +1037,14 @@ package body tb_common_pkg is
-- PROCEDURE: Verify the DUT input to output latency
------------------------------------------------------------------------------
-- for SL ctrl
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "valid", "sop", "eop"
- constant c_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal in_ctrl : in std_logic;
- signal pipe_ctrl_vec : inout std_logic_vector; -- range [0:c_latency]
- signal out_ctrl : in std_logic) is
+ procedure proc_common_verify_latency(
+ constant c_str : in string; -- e.g. "valid", "sop", "eop"
+ constant c_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal in_ctrl : in std_logic;
+ signal pipe_ctrl_vec : inout std_logic_vector; -- range [0:c_latency]
+ signal out_ctrl : in std_logic) is
begin
if rising_edge(clk) then
pipe_ctrl_vec <= in_ctrl & pipe_ctrl_vec(0 to c_latency - 1); -- note: pipe_ctrl_vec(c_latency) is a dummy place holder to avoid [0:-1] range
@@ -963,13 +1063,14 @@ package body tb_common_pkg is
end proc_common_verify_latency;
-- for SLV data
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "data"
- constant c_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal in_data : in std_logic_vector;
- signal pipe_data_vec : inout std_logic_vector; -- range [0:(1 + c_latency)*c_data_w-1]
- signal out_data : in std_logic_vector) is
+ procedure proc_common_verify_latency(
+ constant c_str : in string; -- e.g. "data"
+ constant c_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal in_data : in std_logic_vector;
+ signal pipe_data_vec : inout std_logic_vector; -- range [0:(1 + c_latency)*c_data_w-1]
+ signal out_data : in std_logic_vector) is
constant c_data_w : natural := in_data'length;
constant c_data_vec_w : natural := pipe_data_vec'length; -- = (1 + c_latency) * c_data_w
begin
@@ -993,11 +1094,12 @@ package body tb_common_pkg is
-- PROCEDURE: Verify the expected value
-- . e.g. to check that a test has ran at all
------------------------------------------------------------------------------
- procedure proc_common_verify_value(constant mode : in natural;
- signal clk : in std_logic;
- signal en : in std_logic;
- signal exp : in std_logic_vector;
- signal res : in std_logic_vector) is
+ procedure proc_common_verify_value(
+ constant mode : in natural;
+ signal clk : in std_logic;
+ signal en : in std_logic;
+ signal exp : in std_logic_vector;
+ signal res : in std_logic_vector) is
begin
if rising_edge(clk) then
if en = '1' then
@@ -1014,10 +1116,11 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Opens a file for access and reports fail or success of opening.
------------------------------------------------------------------------------
- procedure proc_common_open_file( file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- file_name : in string;
- file_mode : in FILE_OPEN_KIND) is
+ procedure proc_common_open_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ file_name : in string;
+ file_mode : in FILE_OPEN_KIND) is
begin
if file_status = OPEN_OK then
file_close(in_file);
@@ -1030,14 +1133,15 @@ package body tb_common_pkg is
end if;
end proc_common_open_file;
- ------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
-- PROCEDURE: Reads an integer from a file.
------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_value_0 : out integer) is
- variable v_line : LINE;
- variable v_good : boolean;
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_value_0 : out integer) is
+ variable v_line : LINE;
+ variable v_good : boolean;
begin
if file_status /= OPEN_OK then
report "COMMON : file is not opened " severity FAILURE;
@@ -1057,12 +1161,13 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Reads two integers from two columns in a file.
------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_value_0 : out integer;
- read_value_1 : out integer) is
- variable v_line : LINE;
- variable v_good : boolean;
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_value_0 : out integer;
+ read_value_1 : out integer) is
+ variable v_line : LINE;
+ variable v_good : boolean;
begin
if file_status /= OPEN_OK then
report "COMMON : file is not opened " severity FAILURE;
@@ -1083,15 +1188,16 @@ package body tb_common_pkg is
end if;
end proc_common_readline_file;
-------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
-- PROCEDURE: Reads an array of integer from a file.
------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- value_array : out t_integer_arr;
- nof_reads : in integer) is
- variable v_line : LINE;
- variable v_good : boolean;
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ value_array : out t_integer_arr;
+ nof_reads : in integer) is
+ variable v_line : LINE;
+ variable v_good : boolean;
begin
if file_status /= OPEN_OK then
report "COMMON : file is not opened " severity FAILURE;
@@ -1113,11 +1219,12 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Reads an std_logic_vector from a file
------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_slv : out std_logic_vector) is
- variable v_line : LINE;
- variable v_good : boolean;
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_slv : out std_logic_vector) is
+ variable v_line : LINE;
+ variable v_good : boolean;
begin
if file_status /= OPEN_OK then
report "COMMON : file is not opened " severity FAILURE;
@@ -1137,9 +1244,10 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Reads a string of any length from a file pointer.
------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- res_string : out string) is
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ res_string : out string) is
variable v_line : LINE;
variable v_char : character;
variable is_string : boolean;
@@ -1153,16 +1261,16 @@ package body tb_common_pkg is
readline(in_file, v_line);
-- clear the contents of the result string
for I in res_string'range loop
- res_string(I) := ' ';
+ res_string(I) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for I in res_string'range loop
- read(v_line, v_char, is_string);
- if not is_string then -- found end of line
- exit;
- end if;
- res_string(I) := v_char;
+ read(v_line, v_char, is_string);
+ if not is_string then -- found end of line
+ exit;
+ end if;
+ res_string(I) := v_char;
end loop;
end if;
end if;
@@ -1171,8 +1279,9 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Closes a file.
------------------------------------------------------------------------------
- procedure proc_common_close_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT) is
+ procedure proc_common_close_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT) is
begin
if file_status /= OPEN_OK then
report "COMMON : file was not opened " severity WARNING;
@@ -1186,86 +1295,88 @@ package body tb_common_pkg is
-- row from a file and returns it row by row in an array of
-- integers.
------------------------------------------------------------------------------
- procedure proc_common_read_integer_file(file_name : in string;
- nof_header_lines : natural;
- nof_row : natural;
- nof_col : natural;
- signal return_array : out t_integer_arr) is
+ procedure proc_common_read_integer_file(
+ file_name : in string;
+ nof_header_lines : natural;
+ nof_row : natural;
+ nof_col : natural;
+ signal return_array : out t_integer_arr) is
variable v_file_status : FILE_OPEN_STATUS;
file v_in_file : TEXT;
variable v_input_line : LINE;
variable v_string : string(1 to 80);
- variable v_row_arr : t_integer_arr(0 to nof_col - 1);
+ variable v_row_arr : t_integer_arr(0 to nof_col - 1);
begin
- if file_name /= "UNUSED" and file_name /= "unused" then
- -- Open the file for reading
- proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE);
- -- Read and skip the header
- for J in 0 to nof_header_lines - 1 loop
- proc_common_readline_file(v_file_status, v_in_file, v_string);
+ if file_name /= "UNUSED" and file_name /= "unused" then
+ -- Open the file for reading
+ proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE);
+ -- Read and skip the header
+ for J in 0 to nof_header_lines - 1 loop
+ proc_common_readline_file(v_file_status, v_in_file, v_string);
+ end loop;
+ for J in 0 to nof_row - 1 loop
+ proc_common_readline_file(v_file_status, v_in_file, v_row_arr, nof_col);
+ for I in 0 to nof_col - 1 loop
+ return_array(J * nof_col + I) <= v_row_arr(I); -- use loop to be independent of t_integer_arr downto or to range
end loop;
- for J in 0 to nof_row - 1 loop
- proc_common_readline_file(v_file_status, v_in_file, v_row_arr, nof_col);
- for I in 0 to nof_col - 1 loop
- return_array(J * nof_col + I) <= v_row_arr(I); -- use loop to be independent of t_integer_arr downto or to range
- end loop;
- if ENDFILE(v_in_file) then
- if J /= nof_row - 1 then
- report "COMMON : Unexpected end of file" severity FAILURE;
- end if;
- exit;
+ if ENDFILE(v_in_file) then
+ if J /= nof_row - 1 then
+ report "COMMON : Unexpected end of file" severity FAILURE;
end if;
- end loop;
- -- Close the file
- proc_common_close_file(v_file_status, v_in_file);
- else
- return_array <= (return_array'range => 0);
- end if;
+ exit;
+ end if;
+ end loop;
+ -- Close the file
+ proc_common_close_file(v_file_status, v_in_file);
+ else
+ return_array <= (return_array'range => 0);
+ end if;
end proc_common_read_integer_file;
------------------------------------------------------------------------------
-- PROCEDURE: Reads the data column from a .mif file and returns it in an
-- array of integers
------------------------------------------------------------------------------
- procedure proc_common_read_mif_file( file_name : in string;
- signal return_array : out t_integer_arr) is
+ procedure proc_common_read_mif_file(
+ file_name : in string;
+ signal return_array : out t_integer_arr) is
variable v_file_status : FILE_OPEN_STATUS;
file v_in_file : TEXT;
variable v_input_line : LINE;
variable v_string : string(1 to 80);
- variable v_mem_width : natural := 0;
- variable v_mem_depth : natural := 0;
- variable v_up_bound : natural := 0;
- variable v_low_bound : natural := 0;
- variable v_end_header : boolean := false;
- variable v_char : character;
+ variable v_mem_width : natural := 0;
+ variable v_mem_depth : natural := 0;
+ variable v_up_bound : natural := 0;
+ variable v_low_bound : natural := 0;
+ variable v_end_header : boolean := false;
+ variable v_char : character;
begin
- -- Open the .mif file for reading
- proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE);
- -- Read the header.
- while not v_end_header loop
- proc_common_readline_file(v_file_status, v_in_file, v_string);
- if(func_find_string_in_string(v_string, "WIDTH=")) then -- check for "WIDTH="
- v_up_bound := func_find_char_in_string(v_string, ';');
- v_low_bound := func_find_char_in_string(v_string, '=');
- v_mem_width := func_decstring_to_integer(v_string(v_low_bound + 1 to v_up_bound - 1));
- elsif(func_find_string_in_string(v_string, "DEPTH=")) then -- check for "DEPTH="
- v_up_bound := func_find_char_in_string(v_string, ';');
- v_low_bound := func_find_char_in_string(v_string, '=');
- v_mem_depth := func_decstring_to_integer(v_string(v_low_bound + 1 to v_up_bound - 1));
- elsif(func_find_string_in_string(v_string, "CONTENT BEGIN")) then
- v_end_header := true;
- end if;
- end loop;
- -- Read the data
- for I in 0 to v_mem_depth - 1 loop
- proc_common_readline_file(v_file_status, v_in_file, v_string); -- Read the next line from the file.
- v_low_bound := func_find_char_in_string(v_string, ':'); -- Find the left position of the string that contains the data field
- v_up_bound := func_find_char_in_string(v_string, ';'); -- Find the right position of the string that contains the data field
- return_array(I) <= func_hexstring_to_integer(v_string(v_low_bound + 1 to v_up_bound - 1));
- end loop;
- -- Close the file
- proc_common_close_file(v_file_status, v_in_file);
+ -- Open the .mif file for reading
+ proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE);
+ -- Read the header.
+ while not v_end_header loop
+ proc_common_readline_file(v_file_status, v_in_file, v_string);
+ if(func_find_string_in_string(v_string, "WIDTH=")) then -- check for "WIDTH="
+ v_up_bound := func_find_char_in_string(v_string, ';');
+ v_low_bound := func_find_char_in_string(v_string, '=');
+ v_mem_width := func_decstring_to_integer(v_string(v_low_bound + 1 to v_up_bound - 1));
+ elsif(func_find_string_in_string(v_string, "DEPTH=")) then -- check for "DEPTH="
+ v_up_bound := func_find_char_in_string(v_string, ';');
+ v_low_bound := func_find_char_in_string(v_string, '=');
+ v_mem_depth := func_decstring_to_integer(v_string(v_low_bound + 1 to v_up_bound - 1));
+ elsif(func_find_string_in_string(v_string, "CONTENT BEGIN")) then
+ v_end_header := true;
+ end if;
+ end loop;
+ -- Read the data
+ for I in 0 to v_mem_depth - 1 loop
+ proc_common_readline_file(v_file_status, v_in_file, v_string); -- Read the next line from the file.
+ v_low_bound := func_find_char_in_string(v_string, ':'); -- Find the left position of the string that contains the data field
+ v_up_bound := func_find_char_in_string(v_string, ';'); -- Find the right position of the string that contains the data field
+ return_array(I) <= func_hexstring_to_integer(v_string(v_low_bound + 1 to v_up_bound - 1));
+ end loop;
+ -- Close the file
+ proc_common_close_file(v_file_status, v_in_file);
end proc_common_read_mif_file;
------------------------------------------------------------------------------
@@ -1339,17 +1450,17 @@ package body tb_common_pkg is
for I in c_nof_digits - 1 downto 0 loop
v_char := in_string(I + in_string'low);
case v_char is
- when '0' => v_return_int := v_return_int + 0 * v_weight;
- when '1' => v_return_int := v_return_int + 1 * v_weight;
- when '2' => v_return_int := v_return_int + 2 * v_weight;
- when '3' => v_return_int := v_return_int + 3 * v_weight;
- when '4' => v_return_int := v_return_int + 4 * v_weight;
- when '5' => v_return_int := v_return_int + 5 * v_weight;
- when '6' => v_return_int := v_return_int + 6 * v_weight;
- when '7' => v_return_int := v_return_int + 7 * v_weight;
- when '8' => v_return_int := v_return_int + 8 * v_weight;
- when '9' => v_return_int := v_return_int + 9 * v_weight;
- when others => null;
+ when '0' => v_return_int := v_return_int + 0 * v_weight;
+ when '1' => v_return_int := v_return_int + 1 * v_weight;
+ when '2' => v_return_int := v_return_int + 2 * v_weight;
+ when '3' => v_return_int := v_return_int + 3 * v_weight;
+ when '4' => v_return_int := v_return_int + 4 * v_weight;
+ when '5' => v_return_int := v_return_int + 5 * v_weight;
+ when '6' => v_return_int := v_return_int + 6 * v_weight;
+ when '7' => v_return_int := v_return_int + 7 * v_weight;
+ when '8' => v_return_int := v_return_int + 8 * v_weight;
+ when '9' => v_return_int := v_return_int + 9 * v_weight;
+ when others => null;
end case;
if (v_char /= ' ') then -- Only increment the weight when the character is NOT a spacebar.
v_weight := v_weight * 10; -- Addapt the weight for the next decimal digit.
@@ -1371,23 +1482,23 @@ package body tb_common_pkg is
for I in c_nof_digits - 1 downto 0 loop
v_char := in_string(I + in_string'low);
case v_char is
- when '0' => v_return_int := v_return_int + 0 * v_weight;
- when '1' => v_return_int := v_return_int + 1 * v_weight;
- when '2' => v_return_int := v_return_int + 2 * v_weight;
- when '3' => v_return_int := v_return_int + 3 * v_weight;
- when '4' => v_return_int := v_return_int + 4 * v_weight;
- when '5' => v_return_int := v_return_int + 5 * v_weight;
- when '6' => v_return_int := v_return_int + 6 * v_weight;
- when '7' => v_return_int := v_return_int + 7 * v_weight;
- when '8' => v_return_int := v_return_int + 8 * v_weight;
- when '9' => v_return_int := v_return_int + 9 * v_weight;
- when 'A' | 'a' => v_return_int := v_return_int + 10 * v_weight;
- when 'B' | 'b' => v_return_int := v_return_int + 11 * v_weight;
- when 'C' | 'c' => v_return_int := v_return_int + 12 * v_weight;
- when 'D' | 'd' => v_return_int := v_return_int + 13 * v_weight;
- when 'E' | 'e' => v_return_int := v_return_int + 14 * v_weight;
- when 'F' | 'f' => v_return_int := v_return_int + 15 * v_weight;
- when others => null;
+ when '0' => v_return_int := v_return_int + 0 * v_weight;
+ when '1' => v_return_int := v_return_int + 1 * v_weight;
+ when '2' => v_return_int := v_return_int + 2 * v_weight;
+ when '3' => v_return_int := v_return_int + 3 * v_weight;
+ when '4' => v_return_int := v_return_int + 4 * v_weight;
+ when '5' => v_return_int := v_return_int + 5 * v_weight;
+ when '6' => v_return_int := v_return_int + 6 * v_weight;
+ when '7' => v_return_int := v_return_int + 7 * v_weight;
+ when '8' => v_return_int := v_return_int + 8 * v_weight;
+ when '9' => v_return_int := v_return_int + 9 * v_weight;
+ when 'A' | 'a' => v_return_int := v_return_int + 10 * v_weight;
+ when 'B' | 'b' => v_return_int := v_return_int + 11 * v_weight;
+ when 'C' | 'c' => v_return_int := v_return_int + 12 * v_weight;
+ when 'D' | 'd' => v_return_int := v_return_int + 13 * v_weight;
+ when 'E' | 'e' => v_return_int := v_return_int + 14 * v_weight;
+ when 'F' | 'f' => v_return_int := v_return_int + 15 * v_weight;
+ when others => null;
end case;
if (v_char /= ' ') then -- Only increment the weight when the character is NOT a spacebar.
v_weight := v_weight * 16; -- Addapt the weight for the next hexadecimal digit.
@@ -1405,7 +1516,7 @@ package body tb_common_pkg is
begin
for I in 1 to in_string'length loop
if(in_string(I) = find_char) then
- v_char_position := I;
+ v_char_position := I;
end if;
end loop;
return(v_char_position);
@@ -1422,7 +1533,7 @@ package body tb_common_pkg is
begin
for I in 1 to c_in_length - c_find_length loop
if(in_string(I to (I + c_find_length - 1)) = find_string) then
- v_found_it := true;
+ v_found_it := true;
end if;
end loop;
return(v_found_it);
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
index 5a9bddedde..fc4449fdd3 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
@@ -30,9 +30,9 @@
-- . if no failure messages are printed, TB ran OK.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_common_pulse_delay is
end tb_common_pulse_delay;
@@ -102,18 +102,18 @@ begin
-- common_pulse_delay
-----------------------------------------------------------------------------
u_common_pulse_delay : entity work.common_pulse_delay
- generic map (
- g_pulse_delay_max => c_pulse_delay_max,
- g_register_out => true
- )
- port map (
- clk => clk,
- rst => rst,
-
- pulse_in => pulse_in,
- pulse_delay => pulse_delay,
- pulse_out => pulse_out
- );
+ generic map (
+ g_pulse_delay_max => c_pulse_delay_max,
+ g_register_out => true
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ pulse_in => pulse_in,
+ pulse_delay => pulse_delay,
+ pulse_out => pulse_out
+ );
-----------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd b/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd
index 514326c77b..3f4be0f2fa 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_pulse_extend is
generic (
@@ -71,16 +71,16 @@ begin
end process;
u_spulse : entity work.common_pulse_extend
- generic map (
- g_rst_level => '0',
- g_p_in_level => g_p_in_level,
- g_ep_out_level => g_ep_out_level,
- g_extend_w => c_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- p_in => pulse_in,
- ep_out => pulse_out
- );
+ generic map (
+ g_rst_level => '0',
+ g_p_in_level => g_p_in_level,
+ g_ep_out_level => g_ep_out_level,
+ g_extend_w => c_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ p_in => pulse_in,
+ ep_out => pulse_out
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulser.vhd b/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
index 4dec90a01d..353d3010ce 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_pulser is
end tb_common_pulser;
@@ -66,53 +66,53 @@ begin
end process;
u_reset : entity work.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => clk,
- out_rst => rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => clk,
+ out_rst => rst
+ );
u_pulse_us : entity work.common_pulser
- generic map (
- g_pulse_period => c_pulse_us,
- g_pulse_phase => c_pulse_us - 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => '1',
- pulse_clr => '0',
- pulse_out => pulse_us
- );
+ generic map (
+ g_pulse_period => c_pulse_us,
+ g_pulse_phase => c_pulse_us - 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => '1',
+ pulse_clr => '0',
+ pulse_out => pulse_us
+ );
u_pulse_ms_via_clk_en : entity work.common_pulser
- generic map (
- g_pulse_period => c_pulse_ms
- )
- port map (
- rst => rst,
- clk => clk,
- clken => pulse_us,
- pulse_en => '1',
- pulse_clr => pulse_ms_clr,
- pulse_out => pulse_ms_via_clk_en
- );
+ generic map (
+ g_pulse_period => c_pulse_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => pulse_us,
+ pulse_en => '1',
+ pulse_clr => pulse_ms_clr,
+ pulse_out => pulse_ms_via_clk_en
+ );
u_pulse_ms_via_pulse_en : entity work.common_pulser
- generic map (
- g_pulse_period => c_pulse_ms
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => pulse_us,
- pulse_clr => pulse_ms_clr,
- pulse_out => pulse_ms_via_pulse_en
- );
+ generic map (
+ g_pulse_period => c_pulse_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => pulse_us,
+ pulse_clr => pulse_ms_clr,
+ pulse_out => pulse_ms_via_pulse_en
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd b/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
index 7f99b12610..51c756b706 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
@@ -30,9 +30,9 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_pulser_us_ms_s is
end tb_common_pulser_us_ms_s;
@@ -89,17 +89,17 @@ begin
end process;
u_common_pulser_us_ms_s : entity work.common_pulser_us_ms_s
- generic map (
- g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
- g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- sync => sync,
- pulse_us => pulse_us, -- pulses after every g_pulse_us clock cycles
- pulse_ms => pulse_ms, -- pulses after every g_pulse_us*g_pulse_ms clock cycles
- pulse_s => pulse_s -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
- );
+ generic map (
+ g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
+ g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ sync => sync,
+ pulse_us => pulse_us, -- pulses after every g_pulse_us clock cycles
+ pulse_ms => pulse_ms, -- pulses after every g_pulse_us*g_pulse_ms clock cycles
+ pulse_s => pulse_s -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd b/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
index 5cdd3da0d1..f1d2aa2072 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_reg_cross_domain is
end tb_common_reg_cross_domain;
@@ -108,25 +108,25 @@ begin
end process;
u_out_rst : entity work.common_areset
- port map (
- in_rst => in_rst,
- clk => out_clk,
- out_rst => out_rst
- );
+ port map (
+ in_rst => in_rst,
+ clk => out_clk,
+ out_rst => out_rst
+ );
u_reg_cross_domain : entity work.common_reg_cross_domain
- generic map (
- g_in_new_latency => c_in_new_latency
- )
- port map (
- in_rst => in_rst,
- in_clk => in_clk,
- in_new => in_new, -- when '1' then new in_dat is available after g_in_new_latency
- in_dat => in_dat,
- in_done => in_done,
- out_rst => out_rst,
- out_clk => out_clk,
- out_dat => out_dat,
- out_new => out_new -- when '1' then the out_dat was updated with in_dat due to in_new
- );
+ generic map (
+ g_in_new_latency => c_in_new_latency
+ )
+ port map (
+ in_rst => in_rst,
+ in_clk => in_clk,
+ in_new => in_new, -- when '1' then new in_dat is available after g_in_new_latency
+ in_dat => in_dat,
+ in_done => in_done,
+ out_rst => out_rst,
+ out_clk => out_clk,
+ out_dat => out_dat,
+ out_new => out_new -- when '1' then the out_dat was updated with in_dat due to in_new
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd b/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
index 842665e03e..091df772b6 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
--- Purpose: Test bench to check reinterleave function visually
--- Usage:
--- > do wave_reinterleave.do
--- > run 400ns
--- > observe how the DUT inputs are reinterleaved onto the DUT outputs.
--- Remark: This TB is meant to be easy to the eyes. For stress-testing, use the tb_tb.
+ -- Purpose: Test bench to check reinterleave function visually
+ -- Usage:
+ -- > do wave_reinterleave.do
+ -- > run 400ns
+ -- > observe how the DUT inputs are reinterleaved onto the DUT outputs.
+ -- Remark: This TB is meant to be easy to the eyes. For stress-testing, use the tb_tb.
entity tb_common_reinterleave is
generic (
@@ -40,7 +40,7 @@ entity tb_common_reinterleave is
g_inter_block_size : natural := 2;
g_concat_id : boolean := true; -- Concatenate a 1 byte stream ID 0xA..F @ MSB so user can follow streams in wave window
g_cnt_sync : boolean := true -- When TRUE all generated streams start at 0, else they're offset by 16 counter values.
- );
+ );
end;
architecture rtl of tb_common_reinterleave is
@@ -143,23 +143,23 @@ begin
-- DUT
-----------------------------------------------------------------------------
u_reinterleave : entity work.common_reinterleave
- generic map (
- g_nof_in => g_nof_in,
- g_deint_block_size => g_deint_block_size,
- g_nof_out => g_nof_out,
- g_inter_block_size => g_inter_block_size,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => dut_in_dat,
- in_val => dut_in_val_arr(0), -- All input streams should be synchronous in terms of timing
-
- out_dat => dut_out_dat,
- out_val => dut_out_val
- );
+ generic map (
+ g_nof_in => g_nof_in,
+ g_deint_block_size => g_deint_block_size,
+ g_nof_out => g_nof_out,
+ g_inter_block_size => g_inter_block_size,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => dut_in_dat,
+ in_val => dut_in_val_arr(0), -- All input streams should be synchronous in terms of timing
+
+ out_dat => dut_out_dat,
+ out_val => dut_out_val
+ );
-----------------------------------------------------------------------------
-- Map DUT output SLV to array of streams (to ease viewing in wave window)
@@ -172,23 +172,23 @@ begin
-- REVERSE FUNCTION; the outputs should match the DUT inputs (with delay)
-----------------------------------------------------------------------------
u_rev_reinterleave : entity work.common_reinterleave
- generic map (
- g_nof_in => g_nof_out, -- Note the reversed generics
- g_deint_block_size => g_inter_block_size,
- g_nof_out => g_nof_in,
- g_inter_block_size => g_deint_block_size,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => dut_out_dat,
- in_val => dut_out_val(0),
-
- out_dat => rev_out_dat,
- out_val => rev_out_val
- );
+ generic map (
+ g_nof_in => g_nof_out, -- Note the reversed generics
+ g_deint_block_size => g_inter_block_size,
+ g_nof_out => g_nof_in,
+ g_inter_block_size => g_deint_block_size,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => dut_out_dat,
+ in_val => dut_out_val(0),
+
+ out_dat => rev_out_dat,
+ out_val => rev_out_val
+ );
-----------------------------------------------------------------------------
-- Map REV output SLV to array of streams
diff --git a/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd b/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
index a2e3cb2e3b..c8e3e727b0 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
@@ -20,36 +20,36 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-
--- Purpose: Test bench for common_reorder_symbol.vhd
--- Usage:
--- > as 3
--- > run -all
--- p_verify self-checks the output of the reorder by using a inverse reorder
--- Remark:
--- . The verification assumes that the reorderings can be inversed, so all
--- inputs are output. The inverse reorder to get back to the original input
--- order can be derived from the DUT reorder(stage 1:c_N) using two reorder
--- instances:
--- u_inverse_in: u_inverse_out:
--- c_N = odd --> inverse = reorder(stage 1:c_N) + identity
--- c_N = even --> inverse = reorder(stage c_N:2) + reorder(stage 1)
--- . An alternative approach is to derive the select settings from a specified
--- input to output mapping list. Manually it is relatively easy to find a
--- suitable select_arr setting. A simple algorithm to find a select_arr
--- setting is to try all possible select_arr settings, which is feasible
--- for practical c_N.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+
+ -- Purpose: Test bench for common_reorder_symbol.vhd
+ -- Usage:
+ -- > as 3
+ -- > run -all
+ -- p_verify self-checks the output of the reorder by using a inverse reorder
+ -- Remark:
+ -- . The verification assumes that the reorderings can be inversed, so all
+ -- inputs are output. The inverse reorder to get back to the original input
+ -- order can be derived from the DUT reorder(stage 1:c_N) using two reorder
+ -- instances:
+ -- u_inverse_in: u_inverse_out:
+ -- c_N = odd --> inverse = reorder(stage 1:c_N) + identity
+ -- c_N = even --> inverse = reorder(stage c_N:2) + reorder(stage 1)
+ -- . An alternative approach is to derive the select settings from a specified
+ -- input to output mapping list. Manually it is relatively easy to find a
+ -- suitable select_arr setting. A simple algorithm to find a select_arr
+ -- setting is to try all possible select_arr settings, which is feasible
+ -- for practical c_N.
entity tb_common_reorder_symbol is
generic (
--- g_nof_input : NATURAL := 3;
--- g_nof_output : NATURAL := 3;
--- g_symbol_w : NATURAL := 8;
--- g_select_arr : t_natural_arr := (3, 3, 3); --array_init(3, 6) -- range must fit [c_N*(c_N-1)/2-1:0]
--- g_pipeline_arr : t_natural_arr := (0,0,0,0) --array_init(0, 5) -- range must fit [0:c_N]
+ -- g_nof_input : NATURAL := 3;
+ -- g_nof_output : NATURAL := 3;
+ -- g_symbol_w : NATURAL := 8;
+ -- g_select_arr : t_natural_arr := (3, 3, 3); --array_init(3, 6) -- range must fit [c_N*(c_N-1)/2-1:0]
+ -- g_pipeline_arr : t_natural_arr := (0,0,0,0) --array_init(0, 5) -- range must fit [0:c_N]
g_nof_input : natural := 5;
g_nof_output : natural := 5;
g_symbol_w : natural := 8;
@@ -151,32 +151,32 @@ begin
-- DUT
u_reorder_in : entity work.common_reorder_symbol
- generic map (
- g_nof_input => g_nof_input,
- g_nof_output => g_nof_output,
- g_symbol_w => g_symbol_w,
- g_select_w => c_select_w,
- g_nof_select => c_nof_select,
- g_pipeline_arr => g_pipeline_arr
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => in_data_vec,
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
- in_sync => in_sync,
-
- in_select => in_select_vec,
-
- out_data => reorder_data_vec,
- out_val => reorder_val,
- out_sop => reorder_sop,
- out_eop => reorder_eop,
- out_sync => reorder_sync
- );
+ generic map (
+ g_nof_input => g_nof_input,
+ g_nof_output => g_nof_output,
+ g_symbol_w => g_symbol_w,
+ g_select_w => c_select_w,
+ g_nof_select => c_nof_select,
+ g_pipeline_arr => g_pipeline_arr
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => in_data_vec,
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
+ in_sync => in_sync,
+
+ in_select => in_select_vec,
+
+ out_data => reorder_data_vec,
+ out_val => reorder_val,
+ out_sop => reorder_sop,
+ out_eop => reorder_eop,
+ out_sync => reorder_sync
+ );
-- inverse DUT
inverse_select_arr <= func_common_reorder2_inverse_select(c_N, in_select_arr);
@@ -186,60 +186,60 @@ begin
end generate;
u_inverse_in : entity work.common_reorder_symbol
- generic map (
- g_nof_input => g_nof_output,
- g_nof_output => g_nof_input,
- g_symbol_w => g_symbol_w,
- g_select_w => c_select_w,
- g_nof_select => c_nof_select,
- g_pipeline_arr => g_pipeline_arr
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => reorder_data_vec,
- in_val => reorder_val,
- in_sop => reorder_sop,
- in_eop => reorder_eop,
- in_sync => reorder_sync,
-
- in_select => inverse_select_vec(c_nof_select * c_select_w - 1 downto 0),
-
- out_data => inverse_data_vec,
- out_val => inverse_val,
- out_sop => inverse_sop,
- out_eop => inverse_eop,
- out_sync => inverse_sync
- );
+ generic map (
+ g_nof_input => g_nof_output,
+ g_nof_output => g_nof_input,
+ g_symbol_w => g_symbol_w,
+ g_select_w => c_select_w,
+ g_nof_select => c_nof_select,
+ g_pipeline_arr => g_pipeline_arr
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => reorder_data_vec,
+ in_val => reorder_val,
+ in_sop => reorder_sop,
+ in_eop => reorder_eop,
+ in_sync => reorder_sync,
+
+ in_select => inverse_select_vec(c_nof_select * c_select_w - 1 downto 0),
+
+ out_data => inverse_data_vec,
+ out_val => inverse_val,
+ out_sop => inverse_sop,
+ out_eop => inverse_eop,
+ out_sync => inverse_sync
+ );
u_inverse_out : entity work.common_reorder_symbol
- generic map (
- g_nof_input => g_nof_output,
- g_nof_output => g_nof_input,
- g_symbol_w => g_symbol_w,
- g_select_w => c_select_w,
- g_nof_select => c_nof_select,
- g_pipeline_arr => g_pipeline_arr
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => inverse_data_vec,
- in_val => inverse_val,
- in_sop => inverse_sop,
- in_eop => inverse_eop,
- in_sync => inverse_sync,
-
- in_select => inverse_select_vec(2 * c_nof_select * c_select_w - 1 downto c_nof_select * c_select_w),
-
- out_data => out_data_vec,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop,
- out_sync => out_sync
- );
+ generic map (
+ g_nof_input => g_nof_output,
+ g_nof_output => g_nof_input,
+ g_symbol_w => g_symbol_w,
+ g_select_w => c_select_w,
+ g_nof_select => c_nof_select,
+ g_pipeline_arr => g_pipeline_arr
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => inverse_data_vec,
+ in_val => inverse_val,
+ in_sop => inverse_sop,
+ in_eop => inverse_eop,
+ in_sync => inverse_sync,
+
+ in_select => inverse_select_vec(2 * c_nof_select * c_select_w - 1 downto c_nof_select * c_select_w),
+
+ out_data => out_data_vec,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop,
+ out_sync => out_sync
+ );
-- Verification
p_verify : process(rst, clk)
@@ -256,60 +256,60 @@ begin
-- pipeline data input
u_out_dat : entity work.common_pipeline
- generic map (
- g_pipeline => c_total_pipeline,
- g_in_dat_w => g_nof_input * g_symbol_w,
- g_out_dat_w => g_nof_input * g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_data_vec,
- out_dat => exp_data_vec
- );
+ generic map (
+ g_pipeline => c_total_pipeline,
+ g_in_dat_w => g_nof_input * g_symbol_w,
+ g_out_dat_w => g_nof_input * g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_data_vec,
+ out_dat => exp_data_vec
+ );
-- pipeline control input
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => exp_val
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => exp_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => exp_sop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => exp_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => exp_eop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => exp_eop
+ );
u_out_sync : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sync,
- out_dat => exp_sync
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sync,
+ out_dat => exp_sync
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_rl.vhd b/libraries/base/common/tb/vhdl/tb_common_rl.vhd
index 2eb0d6329b..e96d412b8f 100644
--- a/libraries/base/common/tb/vhdl/tb_common_rl.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_rl.vhd
@@ -38,11 +38,11 @@
-- works when g_rl_increase_en is FALSE or both are FALSE.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_rl is
generic (
@@ -151,62 +151,62 @@ begin
fifo_out_ready <= '1';
u_fifo_sc : entity work.common_fifo_sc
- generic map (
- g_note_is_ful => true, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_dat_w => c_dat_w,
- g_nof_words => g_fifo_size,
- g_af_margin => c_fifo_af_margin
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => fifo_in_dat,
- wr_req => fifo_in_val,
- wr_ful => fifo_ful,
- wr_aful => fifo_almost_full, -- get FIFO almost full to be used to force rl_increase_in_ready
- rd_dat => fifo_out_dat,
- rd_req => fifo_in_ready,
- rd_emp => fifo_emp,
- rd_val => fifo_out_val,
- usedw => fifo_usedw
- );
+ generic map (
+ g_note_is_ful => true, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_dat_w => c_dat_w,
+ g_nof_words => g_fifo_size,
+ g_af_margin => c_fifo_af_margin
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => fifo_in_dat,
+ wr_req => fifo_in_val,
+ wr_ful => fifo_ful,
+ wr_aful => fifo_almost_full, -- get FIFO almost full to be used to force rl_increase_in_ready
+ rd_dat => fifo_out_dat,
+ rd_req => fifo_in_ready,
+ rd_emp => fifo_emp,
+ rd_val => fifo_out_val,
+ usedw => fifo_usedw
+ );
-- RL 1 --> 0
u_rl_decrease : entity work.common_rl_decrease
- generic map (
- g_adapt => g_rl_decrease_en,
- g_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink: RL = 1
- snk_out_ready => fifo_in_ready,
- snk_in_dat => fifo_out_dat,
- snk_in_val => fifo_out_val,
- -- ST source: RL = 0
- src_in_ready => rl_decrease_in_ready,
- src_out_dat => rl_decrease_out_dat,
- src_out_val => rl_decrease_out_val
- );
+ generic map (
+ g_adapt => g_rl_decrease_en,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink: RL = 1
+ snk_out_ready => fifo_in_ready,
+ snk_in_dat => fifo_out_dat,
+ snk_in_val => fifo_out_val,
+ -- ST source: RL = 0
+ src_in_ready => rl_decrease_in_ready,
+ src_out_dat => rl_decrease_out_dat,
+ src_out_val => rl_decrease_out_val
+ );
-- RL 0 --> 1
u_rl_increase : entity work.common_rl_increase
- generic map (
- g_adapt => c_rl_increase_en,
- g_hold_dat_en => g_rl_increase_hold_dat_en,
- g_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- Sink
- snk_out_ready => rl_decrease_in_ready,
- snk_in_dat => rl_decrease_out_dat,
- snk_in_val => rl_decrease_out_val,
- -- Source
- src_in_ready => rl_increase_in_ready,
- src_out_dat => rl_increase_out_dat,
- src_out_val => rl_increase_out_val
- );
+ generic map (
+ g_adapt => c_rl_increase_en,
+ g_hold_dat_en => g_rl_increase_hold_dat_en,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Sink
+ snk_out_ready => rl_decrease_in_ready,
+ snk_in_dat => rl_decrease_out_dat,
+ snk_in_val => rl_decrease_out_val,
+ -- Source
+ src_in_ready => rl_increase_in_ready,
+ src_out_dat => rl_increase_out_dat,
+ src_out_val => rl_increase_out_val
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd b/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
index f6a1689128..4c21d36799 100644
--- a/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
@@ -30,11 +30,11 @@
-- rl_register_in_ready='1' to avoid FIFO overflow.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_rl_register is
generic (
@@ -130,43 +130,43 @@ begin
fifo_out_ready <= '1';
u_fifo_sc : entity work.common_fifo_sc
- generic map (
- g_note_is_ful => true, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_dat_w => c_dat_w,
- g_nof_words => g_fifo_size,
- g_af_margin => c_fifo_af_margin
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => fifo_in_dat,
- wr_req => fifo_in_val,
- wr_ful => fifo_ful,
- wr_aful => fifo_almost_full, -- get FIFO almost full to be used to force rl_register_in_ready
- rd_dat => fifo_out_dat,
- rd_req => fifo_in_ready,
- rd_emp => fifo_emp,
- rd_val => fifo_out_val,
- usedw => fifo_usedw
- );
+ generic map (
+ g_note_is_ful => true, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_dat_w => c_dat_w,
+ g_nof_words => g_fifo_size,
+ g_af_margin => c_fifo_af_margin
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => fifo_in_dat,
+ wr_req => fifo_in_val,
+ wr_ful => fifo_ful,
+ wr_aful => fifo_almost_full, -- get FIFO almost full to be used to force rl_register_in_ready
+ rd_dat => fifo_out_dat,
+ rd_req => fifo_in_ready,
+ rd_emp => fifo_emp,
+ rd_val => fifo_out_val,
+ usedw => fifo_usedw
+ );
-- RL 1 --> 0 --> 1
u_rl_register : entity work.common_rl_register
- generic map (
- g_adapt => g_rl_register_en,
- g_hold_dat_en => g_rl_register_hold_dat_en,
- g_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink: RL = 1
- snk_out_ready => fifo_in_ready,
- snk_in_dat => fifo_out_dat,
- snk_in_val => fifo_out_val,
- -- ST source: RL = 0
- src_in_ready => rl_register_in_ready,
- src_out_dat => rl_register_out_dat,
- src_out_val => rl_register_out_val
- );
+ generic map (
+ g_adapt => g_rl_register_en,
+ g_hold_dat_en => g_rl_register_hold_dat_en,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink: RL = 1
+ snk_out_ready => fifo_in_ready,
+ snk_in_dat => fifo_out_dat,
+ snk_in_val => fifo_out_val,
+ -- ST source: RL = 0
+ src_in_ready => rl_register_in_ready,
+ src_out_dat => rl_register_out_dat,
+ src_out_val => rl_register_out_val
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd b/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
index 5fc43a60f2..825c32351a 100644
--- a/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
@@ -20,20 +20,20 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-
--- Purpose: Test bench for common_select_m_symbols.vhd
--- Usage:
--- > as 3
--- > run -all
--- p_verify self-checks the output of the reorder by using an inverse reorder
--- Remark:
--- . The verification assumes that the reorderings can be inversed, so all
--- inputs are output. It requires only one extra common_select_m_symbols
--- unit that has the same selection settings to obtain the original
--- input data.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+
+ -- Purpose: Test bench for common_select_m_symbols.vhd
+ -- Usage:
+ -- > as 3
+ -- > run -all
+ -- p_verify self-checks the output of the reorder by using an inverse reorder
+ -- Remark:
+ -- . The verification assumes that the reorderings can be inversed, so all
+ -- inputs are output. It requires only one extra common_select_m_symbols
+ -- unit that has the same selection settings to obtain the original
+ -- input data.
entity tb_common_select_m_symbols is
generic (
@@ -134,64 +134,64 @@ begin
-- DUT
u_reorder_in : entity work.common_select_m_symbols
- generic map (
- g_nof_input => g_nof_input,
- g_nof_output => g_nof_output,
- g_symbol_w => g_symbol_w,
- g_pipeline_in => g_pipeline_in,
- g_pipeline_in_m => g_pipeline_in_m,
- g_pipeline_out => g_pipeline_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => in_data_vec,
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
- in_sync => in_sync,
-
- in_select => in_select_vec,
-
- out_data => reorder_data_vec,
- out_val => reorder_val,
- out_sop => reorder_sop,
- out_eop => reorder_eop,
- out_sync => reorder_sync
- );
+ generic map (
+ g_nof_input => g_nof_input,
+ g_nof_output => g_nof_output,
+ g_symbol_w => g_symbol_w,
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_in_m => g_pipeline_in_m,
+ g_pipeline_out => g_pipeline_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => in_data_vec,
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
+ in_sync => in_sync,
+
+ in_select => in_select_vec,
+
+ out_data => reorder_data_vec,
+ out_val => reorder_val,
+ out_sop => reorder_sop,
+ out_eop => reorder_eop,
+ out_sync => reorder_sync
+ );
gen_inverse_select_vec: for K in g_nof_output - 1 downto 0 generate
inverse_select_vec((K + 1) * c_select_w - 1 downto K * c_select_w) <= TO_UVEC(inverse_select_arr(K), c_select_w);
end generate;
u_inverse_out : entity work.common_select_m_symbols
- generic map (
- g_nof_input => g_nof_output,
- g_nof_output => g_nof_input,
- g_symbol_w => g_symbol_w,
- g_pipeline_in => g_pipeline_in,
- g_pipeline_in_m => g_pipeline_in_m,
- g_pipeline_out => g_pipeline_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => reorder_data_vec,
- in_val => reorder_val,
- in_sop => reorder_sop,
- in_eop => reorder_eop,
- in_sync => reorder_sync,
-
- in_select => inverse_select_vec,
-
- out_data => out_data_vec,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop,
- out_sync => out_sync
- );
+ generic map (
+ g_nof_input => g_nof_output,
+ g_nof_output => g_nof_input,
+ g_symbol_w => g_symbol_w,
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_in_m => g_pipeline_in_m,
+ g_pipeline_out => g_pipeline_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => reorder_data_vec,
+ in_val => reorder_val,
+ in_sop => reorder_sop,
+ in_eop => reorder_eop,
+ in_sync => reorder_sync,
+
+ in_select => inverse_select_vec,
+
+ out_data => out_data_vec,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop,
+ out_sync => out_sync
+ );
-- Verification
p_verify : process(rst, clk)
@@ -208,60 +208,60 @@ begin
-- pipeline data input
u_out_dat : entity work.common_pipeline
- generic map (
- g_pipeline => c_total_pipeline,
- g_in_dat_w => g_nof_input * g_symbol_w,
- g_out_dat_w => g_nof_input * g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_data_vec,
- out_dat => exp_data_vec
- );
+ generic map (
+ g_pipeline => c_total_pipeline,
+ g_in_dat_w => g_nof_input * g_symbol_w,
+ g_out_dat_w => g_nof_input * g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_data_vec,
+ out_dat => exp_data_vec
+ );
-- pipeline control input
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => exp_val
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => exp_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => exp_sop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => exp_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => exp_eop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => exp_eop
+ );
u_out_sync : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sync,
- out_dat => exp_sync
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sync,
+ out_dat => exp_sync
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd b/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
index 14f400a91f..6c662ab8e5 100644
--- a/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
@@ -30,10 +30,10 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_common_shiftram is
generic (
@@ -107,22 +107,22 @@ begin
-- DUT
u_common_shiftram : entity work.common_shiftram
- generic map (
- g_data_w => g_data_w,
- g_nof_words => g_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_in => data_in,
- data_in_val => data_in_val,
- data_in_shift => data_in_shift,
-
- data_out => data_out,
- data_out_val => data_out_val,
- data_out_shift => data_out_shift
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_nof_words => g_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_in => data_in,
+ data_in_val => data_in_val,
+ data_in_shift => data_in_shift,
+
+ data_out => data_out,
+ data_out_val => data_out_val,
+ data_out_shift => data_out_shift
+ );
-- Make sure prev_data_out has been assigned
p_verify_start: process
diff --git a/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd b/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
index 306d94849f..efd9563207 100644
--- a/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
--- Purpose: Test bench for common_shiftreg.vhd
--- Usage:
--- > as 3
--- > run -all
--- proc_common_verify_data self-checks the incrementing output
+ -- Purpose: Test bench for common_shiftreg.vhd
+ -- Usage:
+ -- > as 3
+ -- > run -all
+ -- proc_common_verify_data self-checks the incrementing output
entity tb_common_shiftreg is
generic (
@@ -155,32 +155,32 @@ begin
-- DUT
u_shiftreg : entity work.common_shiftreg
- generic map (
- g_pipeline => g_pipeline,
- g_flush_en => g_flush_en,
- g_nof_dat => g_nof_dat,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => in_dat,
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
-
- out_data_vec => out_data_vec,
- out_val_vec => out_val_vec,
- out_sop_vec => out_sop_vec,
- out_eop_vec => out_eop_vec,
- out_cnt => out_cnt,
-
- out_dat => out_dat,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_flush_en => g_flush_en,
+ g_nof_dat => g_nof_dat,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_dat,
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
+
+ out_data_vec => out_data_vec,
+ out_val_vec => out_val_vec,
+ out_sop_vec => out_sop_vec,
+ out_eop_vec => out_eop_vec,
+ out_cnt => out_cnt,
+
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop
+ );
-- Verification
proc_common_verify_data(1, clk, verify_en, ready, out_val, out_dat, prev_out_dat);
diff --git a/libraries/base/common/tb/vhdl/tb_common_spulse.vhd b/libraries/base/common/tb/vhdl/tb_common_spulse.vhd
index 70dfeed5e0..8c3c7e045c 100644
--- a/libraries/base/common/tb/vhdl/tb_common_spulse.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_spulse.vhd
@@ -27,9 +27,9 @@
-- > run 1 us
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_spulse is
end tb_common_spulse;
@@ -67,22 +67,22 @@ begin
end process;
u_out_rst : entity work.common_areset
- port map (
- in_rst => in_rst,
- clk => out_clk,
- out_rst => out_rst
- );
+ port map (
+ in_rst => in_rst,
+ clk => out_clk,
+ out_rst => out_rst
+ );
u_spulse : entity work.common_spulse
- generic map (
- g_delay_len => c_meta_delay
- )
- port map (
- in_clk => in_clk,
- in_rst => in_rst,
- in_pulse => in_pulse,
- out_clk => out_clk,
- out_rst => out_rst,
- out_pulse => out_pulse
- );
+ generic map (
+ g_delay_len => c_meta_delay
+ )
+ port map (
+ in_clk => in_clk,
+ in_rst => in_rst,
+ in_pulse => in_pulse,
+ out_clk => out_clk,
+ out_rst => out_rst,
+ out_pulse => out_pulse
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_switch.vhd b/libraries/base/common/tb/vhdl/tb_common_switch.vhd
index 457290cb5c..2e50147e9e 100644
--- a/libraries/base/common/tb/vhdl/tb_common_switch.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_switch.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_switch is
end tb_common_switch;
@@ -46,14 +46,15 @@ architecture tb of tb_common_switch is
constant c_nof_generics : natural := 3;
constant c_nof_dut : natural := 2**c_nof_generics;
- constant c_generics_matrix : t_boolean_matrix(0 to c_nof_dut - 1, 0 to c_nof_generics - 1) := ((false, false, false),
- (false, false, true),
- (false, true, false),
- (false, true, true),
- ( true, false, false),
- ( true, false, true),
- ( true, true, false),
- ( true, true, true));
+ constant c_generics_matrix : t_boolean_matrix(
+ 0 to c_nof_dut - 1, 0 to c_nof_generics - 1) := ((false, false, false),
+ (false, false, true),
+ (false, true, false),
+ (false, true, true),
+ ( true, false, false),
+ ( true, false, true),
+ ( true, true, false),
+ ( true, true, true));
-- View constants in Wave window
signal dbg_c_generics_matrix : t_boolean_matrix(0 to c_nof_dut - 1, 0 to c_nof_generics - 1) := c_generics_matrix;
signal dbg_state : natural;
@@ -222,20 +223,20 @@ begin
gen_dut : for I in 0 to c_nof_dut - 1 generate
u_switch : entity work.common_switch
- generic map (
- g_rst_level => '0', -- output level at reset.
- --g_rst_level => '1',
- g_priority_lo => c_generics_matrix(I,0),
- g_or_high => c_generics_matrix(I,1),
- g_and_low => c_generics_matrix(I,2)
- )
- port map (
- clk => clk,
- rst => rst,
- switch_high => in_hi,
- switch_low => in_lo,
- out_level => out_level(I)
- );
+ generic map (
+ g_rst_level => '0', -- output level at reset.
+ --g_rst_level => '1',
+ g_priority_lo => c_generics_matrix(I,0),
+ g_or_high => c_generics_matrix(I,1),
+ g_and_low => c_generics_matrix(I,2)
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => in_hi,
+ switch_low => in_lo,
+ out_level => out_level(I)
+ );
end generate;
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_toggle.vhd b/libraries/base/common/tb/vhdl/tb_common_toggle.vhd
index fb66383f1a..72d5a8a0e1 100644
--- a/libraries/base/common/tb/vhdl/tb_common_toggle.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_toggle.vhd
@@ -26,9 +26,9 @@
-- Observe the out_toggle during the different stimuli indicated by tb_state.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_toggle is
end tb_common_toggle;
@@ -96,16 +96,16 @@ begin
end process;
u_toggle : entity work.common_toggle
- generic map (
- g_evt_type => "RISING",
- g_rst_level => '0'
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_dat,
- in_val => in_val,
- out_dat => out_toggle
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_rst_level => '0'
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_dat,
+ in_val => in_val,
+ out_dat => out_toggle
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd b/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd
index e150948888..dbc05a9855 100644
--- a/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd
@@ -27,9 +27,9 @@
-- Observe out_toggle in Wave Window in relation to in_toggle and align
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_toggle_align is
end tb_common_toggle_align;
@@ -126,15 +126,15 @@ begin
end process;
u_toggle : entity work.common_toggle_align
- generic map (
- g_pipeline => c_pipeline,
- g_nof_clk_per_period => c_toggle_period
- )
- port map (
- rst => rst,
- clk => clk,
- in_align => in_align,
- in_toggle => in_toggle,
- out_toggle => out_toggle
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_nof_clk_per_period => c_toggle_period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_align => in_align,
+ in_toggle => in_toggle,
+ out_toggle => out_toggle
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_transpose.vhd b/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
index 922093695f..cfa9f058f7 100644
--- a/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
@@ -20,17 +20,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
--- Purpose: Test bench for common_transpose.vhd
--- Usage:
--- > as 3
--- > run -all
--- p_verify self-checks the data output and the addr output of two times the
--- transpose.
+ -- Purpose: Test bench for common_transpose.vhd
+ -- Usage:
+ -- > as 3
+ -- > run -all
+ -- p_verify self-checks the data output and the addr output of two times the
+ -- transpose.
entity tb_common_transpose is
generic (
@@ -60,9 +60,10 @@ architecture tb of tb_common_transpose is
constant c_frame_len : natural := 7 * g_nof_data;
constant c_frame_eop : natural := (c_frame_len - 1) mod c_frame_len;
- procedure proc_align_eop(signal clk : in std_logic;
- signal stimuli_phase : in std_logic;
- signal in_val : out std_logic) is
+ procedure proc_align_eop(
+ signal clk : in std_logic;
+ signal stimuli_phase : in std_logic;
+ signal in_val : out std_logic) is
begin
while stimuli_phase = '0' loop
in_val <= '1';
@@ -206,58 +207,58 @@ begin
-- DUT
u_transpose_in : entity common_lib.common_transpose
- generic map (
- g_pipeline_shiftreg => g_pipeline_shiftreg,
- g_pipeline_transpose => g_pipeline_transpose,
- g_pipeline_hold => g_pipeline_hold,
- g_pipeline_select => g_pipeline_select,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w,
- g_addr_w => g_addr_w,
- g_addr_offset => g_addr_offset
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline_shiftreg => g_pipeline_shiftreg,
+ g_pipeline_transpose => g_pipeline_transpose,
+ g_pipeline_hold => g_pipeline_hold,
+ g_pipeline_select => g_pipeline_select,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w,
+ g_addr_w => g_addr_w,
+ g_addr_offset => g_addr_offset
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_offset => in_offset,
- in_addr => in_addr,
- in_data => in_data,
- in_val => in_val,
- in_eop => in_eop,
+ in_offset => in_offset,
+ in_addr => in_addr,
+ in_data => in_data,
+ in_val => in_val,
+ in_eop => in_eop,
- out_addr => trans_addr,
- out_data => trans_data,
- out_val => trans_val,
- out_eop => trans_eop
- );
+ out_addr => trans_addr,
+ out_data => trans_data,
+ out_val => trans_val,
+ out_eop => trans_eop
+ );
u_transpose_out : entity common_lib.common_transpose
- generic map (
- g_pipeline_shiftreg => g_pipeline_shiftreg,
- g_pipeline_transpose => g_pipeline_transpose,
- g_pipeline_hold => g_pipeline_hold,
- g_pipeline_select => g_pipeline_select,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w,
- g_addr_w => g_addr_w,
- g_addr_offset => g_addr_offset
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline_shiftreg => g_pipeline_shiftreg,
+ g_pipeline_transpose => g_pipeline_transpose,
+ g_pipeline_hold => g_pipeline_hold,
+ g_pipeline_select => g_pipeline_select,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w,
+ g_addr_w => g_addr_w,
+ g_addr_offset => g_addr_offset
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_offset => trans_offset,
- in_addr => trans_addr,
- in_data => trans_data,
- in_val => trans_val,
- in_eop => trans_eop,
+ in_offset => trans_offset,
+ in_addr => trans_addr,
+ in_data => trans_data,
+ in_val => trans_val,
+ in_eop => trans_eop,
- out_addr => out_addr,
- out_data => out_data,
- out_val => out_val,
- out_eop => out_eop
- );
+ out_addr => out_addr,
+ out_data => out_data,
+ out_val => out_val,
+ out_eop => out_eop
+ );
-- Verification p_verify
proc_common_verify_data(1, clk, verify_en, ready, out_val, out_addr, prev_out_addr);
diff --git a/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd b/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd
index 7bef3d07b0..57577fa817 100644
--- a/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
--- Purpose: Test bench for common_transpose_symbol.vhd
--- Usage:
--- > as 3
--- > run -all
--- p_verify self-checks the output of two time the transpose
+ -- Purpose: Test bench for common_transpose_symbol.vhd
+ -- Usage:
+ -- > as 3
+ -- > run -all
+ -- p_verify self-checks the output of two time the transpose
entity tb_common_transpose_symbol is
generic (
@@ -101,46 +101,46 @@ begin
-- DUT
u_transpose_in : entity work.common_transpose_symbol
- generic map (
- g_pipeline => g_pipeline,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => in_data_vec,
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
-
- out_data => trans_data_vec,
- out_val => trans_val,
- out_sop => trans_sop,
- out_eop => trans_eop
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => in_data_vec,
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
+
+ out_data => trans_data_vec,
+ out_val => trans_val,
+ out_sop => trans_sop,
+ out_eop => trans_eop
+ );
u_transpose_out : entity work.common_transpose_symbol
- generic map (
- g_pipeline => g_pipeline,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => trans_data_vec,
- in_val => trans_val,
- in_sop => trans_sop,
- in_eop => trans_eop,
-
- out_data => out_data_vec,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => trans_data_vec,
+ in_val => trans_val,
+ in_sop => trans_sop,
+ in_eop => trans_eop,
+
+ out_data => out_data_vec,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop
+ );
-- Verification
p_verify : process(rst, clk)
@@ -156,49 +156,49 @@ begin
-- pipeline data input
u_out_dat : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline * 2,
- g_in_dat_w => g_nof_data * g_data_w,
- g_out_dat_w => g_nof_data * g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_data_vec,
- out_dat => exp_data_vec
- );
+ generic map (
+ g_pipeline => g_pipeline * 2,
+ g_in_dat_w => g_nof_data * g_data_w,
+ g_out_dat_w => g_nof_data * g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_data_vec,
+ out_dat => exp_data_vec
+ );
-- pipeline control input
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline * 2
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => exp_val
- );
+ generic map (
+ g_pipeline => g_pipeline * 2
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => exp_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline * 2
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => exp_sop
- );
+ generic map (
+ g_pipeline => g_pipeline * 2
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => exp_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline * 2
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => exp_eop
- );
+ generic map (
+ g_pipeline => g_pipeline * 2
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => exp_eop
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
index e83313ab6c..d94f3bb6df 100644
--- a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
@@ -26,11 +26,11 @@
-- --------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_str_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_str_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_variable_delay is
end tb_common_variable_delay;
@@ -67,7 +67,7 @@ begin
proc_common_gen_pulse(1, c_trigger_interval, '1', rst, clk, trigger);
p_in_stimuli : process
- variable clk_cnt : natural := 0;
+ variable clk_cnt : natural := 0;
begin
delay <= 0;
enable <= '0';
@@ -105,13 +105,13 @@ begin
-- device under test
u_dut : entity work.common_variable_delay
- port map (
- rst => rst,
- clk => clk,
-
- delay => delay,
- enable => enable,
- in_pulse => trigger,
- out_pulse => trigger_dly
- );
+ port map (
+ rst => rst,
+ clk => clk,
+
+ delay => delay,
+ enable => enable,
+ in_pulse => trigger,
+ out_pulse => trigger_dly
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_zip.vhd b/libraries/base/common/tb/vhdl/tb_common_zip.vhd
index 5dd2390947..49b4700411 100644
--- a/libraries/base/common/tb/vhdl/tb_common_zip.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_zip.vhd
@@ -29,11 +29,11 @@
-- to the out_dat vector.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_zip is
generic (
@@ -76,16 +76,16 @@ begin
enable <= ena and ena_mask;
u_dut : entity work.common_zip
- generic map (
- g_nof_streams => g_nof_streams,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- in_dat_arr => in_dat_arr,
- out_val => out_val,
- out_dat => out_dat
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ in_dat_arr => in_dat_arr,
+ out_val => out_val,
+ out_dat => out_dat
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd b/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd
index 352ac9ae47..079f7e44ef 100644
--- a/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd
+++ b/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd
@@ -86,8 +86,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity tb_delta_cycle_demo is
end tb_delta_cycle_demo;
diff --git a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
index 93022fd6a2..9a6c58aad2 100644
--- a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
@@ -29,13 +29,13 @@
-- --------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_str_pkg.all;
-use work.tb_common_pkg.all;
-use work.common_mem_pkg.all;
-use work.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_str_pkg.all;
+ use work.tb_common_pkg.all;
+ use work.common_mem_pkg.all;
+ use work.tb_common_mem_pkg.all;
entity tb_mms_common_variable_delay is
end tb_mms_common_variable_delay;
@@ -93,17 +93,17 @@ begin
-- device under test
u_dut : entity work.mms_common_variable_delay
- port map (
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
-
- reg_enable_mosi => mm_mosi,
- reg_enable_miso => mm_miso,
-
- delay => delay,
- trigger => trigger,
- trigger_dly => trigger_dly
- );
+ port map (
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+
+ reg_enable_mosi => mm_mosi,
+ reg_enable_miso => mm_miso,
+
+ delay => delay,
+ trigger => trigger,
+ trigger_dly => trigger_dly
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_requantize.vhd b/libraries/base/common/tb/vhdl/tb_requantize.vhd
index 68fd97cdd1..73e5dedb4f 100644
--- a/libraries/base/common/tb/vhdl/tb_requantize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_requantize.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-
--- Purpose: Test bench for common_requantize.vhd
--- Usage:
--- > do wave_requantize.do
--- > run 1 us
--- . Do a diff with the golden reference output files for the DUTs. These files
--- are created using run 1 us and:
--- . c_in_dat_w = 6
--- . c_out_dat_w = 3
--- . c_lsb_w = 2
--- . c_lsb_round_clip = TRUE
--- . c_lsb_round_even = FALSE
--- . c_msb_clip_symmetric = TRUE
--- . Observe reg_dat with respect to the out_s_*_*.dat and out_u_*_*.dat
--- . Try also c_lsb_round_clip=FALSE
--- . Try also c_msb_clip_symmetric=FALSE
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+
+ -- Purpose: Test bench for common_requantize.vhd
+ -- Usage:
+ -- > do wave_requantize.do
+ -- > run 1 us
+ -- . Do a diff with the golden reference output files for the DUTs. These files
+ -- are created using run 1 us and:
+ -- . c_in_dat_w = 6
+ -- . c_out_dat_w = 3
+ -- . c_lsb_w = 2
+ -- . c_lsb_round_clip = TRUE
+ -- . c_lsb_round_even = FALSE
+ -- . c_msb_clip_symmetric = TRUE
+ -- . Observe reg_dat with respect to the out_s_*_*.dat and out_u_*_*.dat
+ -- . Try also c_lsb_round_clip=FALSE
+ -- . Try also c_msb_clip_symmetric=FALSE
entity tb_requantize is
end tb_requantize;
@@ -135,190 +135,190 @@ begin
in_vec <= in_val & in_dat;
u_pipe : entity work.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_in_dat_w => c_in_dat_w + 1,
- g_out_dat_w => c_in_dat_w + 1
- )
- port map (
- clk => clk,
- in_dat => in_vec,
- out_dat => reg_vec
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_in_dat_w => c_in_dat_w + 1,
+ g_out_dat_w => c_in_dat_w + 1
+ )
+ port map (
+ clk => clk,
+ in_dat => in_vec,
+ out_dat => reg_vec
+ );
reg_val <= reg_vec(c_in_dat_w);
reg_dat <= reg_vec(c_in_dat_w - 1 downto 0);
-- DUT for "SIGNED"
u_s_r_c : entity work.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => true,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_s_r_c_dat,
- out_ovr => out_s_r_c_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_s_r_c_dat,
+ out_ovr => out_s_r_c_ovr
+ );
u_s_r_w : entity work.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => false,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_s_r_w_dat,
- out_ovr => out_s_r_w_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_s_r_w_dat,
+ out_ovr => out_s_r_w_ovr
+ );
u_s_t_c : entity work.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => false,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => true,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_s_t_c_dat,
- out_ovr => out_s_t_c_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => false,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_s_t_c_dat,
+ out_ovr => out_s_t_c_ovr
+ );
u_s_t_w : entity work.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => false,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => false,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_s_t_w_dat,
- out_ovr => out_s_t_w_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => false,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_s_t_w_dat,
+ out_ovr => out_s_t_w_ovr
+ );
-- DUT for "UNSIGNED"
u_u_r_c : entity work.common_requantize
- generic map (
- g_representation => "UNSIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => true,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_u_r_c_dat,
- out_ovr => out_u_r_c_ovr
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_u_r_c_dat,
+ out_ovr => out_u_r_c_ovr
+ );
u_u_r_w : entity work.common_requantize
- generic map (
- g_representation => "UNSIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => false,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_u_r_w_dat,
- out_ovr => out_u_r_w_ovr
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_u_r_w_dat,
+ out_ovr => out_u_r_w_ovr
+ );
u_u_t_c : entity work.common_requantize
- generic map (
- g_representation => "UNSIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => false,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => true,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_u_t_c_dat,
- out_ovr => out_u_t_c_ovr
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => false,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_u_t_c_dat,
+ out_ovr => out_u_t_c_ovr
+ );
u_u_t_w : entity work.common_requantize
- generic map (
- g_representation => "UNSIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => false,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => false,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_u_t_w_dat,
- out_ovr => out_u_t_w_ovr
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => false,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_u_t_w_dat,
+ out_ovr => out_u_t_w_ovr
+ );
-- Verification usign golden results from file
p_verify : process
@@ -338,126 +338,126 @@ begin
out_u_ovr_vec <= out_u_r_c_ovr & out_u_r_w_ovr & out_u_t_c_ovr & out_u_t_w_ovr;
u_output_file_s_dat : entity tst_lib.tst_output
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_s_dat.out",
- g_nof_data => c_nof_dut,
- g_data_width => c_out_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => out_s_dat_vec,
- in_val => reg_val
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_s_dat.out",
+ g_nof_data => c_nof_dut,
+ g_data_width => c_out_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => out_s_dat_vec,
+ in_val => reg_val
+ );
u_ref_file_s_dat : entity tst_lib.tst_input
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_s_dat.gold",
- g_file_repeat => 1,
- g_nof_data => c_nof_dut,
- g_data_width => c_out_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_val,
- out_dat => ref_s_dat_vec,
- out_val => ref_val,
- out_eof => ref_eof
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_s_dat.gold",
+ g_file_repeat => 1,
+ g_nof_data => c_nof_dut,
+ g_data_width => c_out_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_val,
+ out_dat => ref_s_dat_vec,
+ out_val => ref_val,
+ out_eof => ref_eof
+ );
u_output_file_s_ovr : entity tst_lib.tst_output
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_s_ovr.out",
- g_nof_data => c_nof_dut,
- g_data_width => 1,
- g_data_type => "UNSIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => out_s_ovr_vec,
- in_val => reg_val
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_s_ovr.out",
+ g_nof_data => c_nof_dut,
+ g_data_width => 1,
+ g_data_type => "UNSIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => out_s_ovr_vec,
+ in_val => reg_val
+ );
u_ref_file_s_ovr : entity tst_lib.tst_input
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_s_ovr.gold",
- g_file_repeat => 1,
- g_nof_data => c_nof_dut,
- g_data_width => 1,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_val,
- out_dat => ref_s_ovr_vec,
- out_val => OPEN,
- out_eof => open
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_s_ovr.gold",
+ g_file_repeat => 1,
+ g_nof_data => c_nof_dut,
+ g_data_width => 1,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_val,
+ out_dat => ref_s_ovr_vec,
+ out_val => OPEN,
+ out_eof => open
+ );
u_output_file_u_dat : entity tst_lib.tst_output
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_u_dat.out",
- g_nof_data => c_nof_dut,
- g_data_width => c_out_dat_w,
- g_data_type => "UNSIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => out_u_dat_vec,
- in_val => reg_val
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_u_dat.out",
+ g_nof_data => c_nof_dut,
+ g_data_width => c_out_dat_w,
+ g_data_type => "UNSIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => out_u_dat_vec,
+ in_val => reg_val
+ );
u_ref_file_u_dat : entity tst_lib.tst_input
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_u_dat.gold",
- g_file_repeat => 1,
- g_nof_data => c_nof_dut,
- g_data_width => c_out_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_val,
- out_dat => ref_u_dat_vec,
- out_val => OPEN,
- out_eof => open
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_u_dat.gold",
+ g_file_repeat => 1,
+ g_nof_data => c_nof_dut,
+ g_data_width => c_out_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_val,
+ out_dat => ref_u_dat_vec,
+ out_val => OPEN,
+ out_eof => open
+ );
u_output_file_u_ovr : entity tst_lib.tst_output
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_u_ovr.out",
- g_nof_data => c_nof_dut,
- g_data_width => 1,
- g_data_type => "UNSIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => out_u_ovr_vec,
- in_val => reg_val
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_u_ovr.out",
+ g_nof_data => c_nof_dut,
+ g_data_width => 1,
+ g_data_type => "UNSIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => out_u_ovr_vec,
+ in_val => reg_val
+ );
u_ref_file_u_ovr : entity tst_lib.tst_input
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_u_ovr.gold",
- g_file_repeat => 1,
- g_nof_data => c_nof_dut,
- g_data_width => 1,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_val,
- out_dat => ref_u_ovr_vec,
- out_val => OPEN,
- out_eof => open
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_u_ovr.gold",
+ g_file_repeat => 1,
+ g_nof_data => c_nof_dut,
+ g_data_width => 1,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_val,
+ out_dat => ref_u_ovr_vec,
+ out_val => OPEN,
+ out_eof => open
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_round.vhd b/libraries/base/common/tb/vhdl/tb_round.vhd
index 59813adae6..72d30a9c7f 100644
--- a/libraries/base/common/tb/vhdl/tb_round.vhd
+++ b/libraries/base/common/tb/vhdl/tb_round.vhd
@@ -36,9 +36,9 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_round is
generic (
@@ -271,86 +271,86 @@ begin
-----------------------------------------------------------------------------
s_truncate : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => false,
- g_round_clip => false,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_truncate
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => false,
+ g_round_clip => false,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_truncate
+ );
s_round_half_away : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_round_half_away
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_round_half_away
+ );
s_round_half_away_clip : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_round_half_away_clip
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_round_half_away_clip
+ );
s_round_half_even : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_round_even => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_round_half_even
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_round_even => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_round_half_even
+ );
s_round_half_even_clip : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => true,
- g_round_even => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_round_half_even_clip
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_round_even => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_round_half_even_clip
+ );
-----------------------------------------------------------------------------
-- UNSIGNED DUTs
@@ -358,86 +358,86 @@ begin
-- DUT for truncate
u_truncate : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => false,
- g_round_clip => false,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_truncate
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => false,
+ g_round_clip => false,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_truncate
+ );
u_round_half_up : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_round_half_up
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_round_half_up
+ );
u_round_half_up_clip : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => true,
- g_round_clip => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_round_half_up_clip
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_round_half_up_clip
+ );
u_round_half_even : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => true,
- g_round_clip => false,
- g_round_even => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_round_half_even
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_round_even => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_round_half_even
+ );
u_round_half_even_clip : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => true,
- g_round_clip => true,
- g_round_even => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_round_half_even_clip
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_round_even => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_round_half_even_clip
+ );
-- Observe fixed point SLV values as REAL
-- . signed
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
index 7d7001e00c..c411a2debd 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_add_sub is
end tb_tb_common_add_sub;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd
index ac64038aab..f6ab79a108 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_adder_tree is
end tb_tb_common_adder_tree;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
index b24e0b6dac..02e39d8606 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
@@ -24,7 +24,7 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_create_strobes_from_valid is
end tb_tb_common_create_strobes_from_valid;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
index d76e0e916d..6c7afea6b9 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_fanout_tree is
end tb_tb_common_fanout_tree;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
index 64bfdbd9cc..944149548e 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_multiplexer is
end tb_tb_common_multiplexer;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
index 238655a6c4..25bd7e5d65 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_operation_tree is
end tb_tb_common_operation_tree;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
index 4a6aa138ca..de4876f686 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_paged_ram_ww_rr is
end tb_tb_common_paged_ram_ww_rr;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd
index a7ad45d86a..382fe2714a 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_reinterleave is
generic (
g_dat_w : natural
- );
+ );
end;
architecture rtl of tb_tb_common_reinterleave is
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
index 309b4f2b8c..c33d65fa4a 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_reorder_symbol is
end tb_tb_common_reorder_symbol;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
index 297df49506..1d9a41bb4b 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_rl is
end tb_tb_common_rl;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
index 77863f33c0..60783b83ee 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_rl_register is
end tb_tb_common_rl_register;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
index 3fd334e1a1..96f1800080 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
--- Purpose: Multi-test bench for common_transpose.vhd
--- Usage:
--- > as 3
--- > run -all
+ -- Purpose: Multi-test bench for common_transpose.vhd
+ -- Usage:
+ -- > as 3
+ -- > run -all
entity tb_tb_common_transpose is
end tb_tb_common_transpose;
@@ -33,13 +33,13 @@ end tb_tb_common_transpose;
architecture tb of tb_tb_common_transpose is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- g_pipeline_shiftreg : NATURAL := 0;
--- | g_pipeline_transpose : NATURAL := 0;
--- | | g_pipeline_hold : NATURAL := 0;
--- | | | g_pipeline_select : NATURAL := 1;
--- | | | | g_nof_data : NATURAL := 3;
--- | | | | | g_data_w : NATURAL := 12
--- | | | | | |
+ -- g_pipeline_shiftreg : NATURAL := 0;
+ -- | g_pipeline_transpose : NATURAL := 0;
+ -- | | g_pipeline_hold : NATURAL := 0;
+ -- | | | g_pipeline_select : NATURAL := 1;
+ -- | | | | g_nof_data : NATURAL := 3;
+ -- | | | | | g_data_w : NATURAL := 12
+ -- | | | | | |
u_4_4 : entity common_lib.tb_common_transpose generic map(0, 0, 0, 1, 4, 4);
u_4_8 : entity common_lib.tb_common_transpose generic map(0, 0, 0, 1, 4, 8);
diff --git a/libraries/base/common/tb/vhdl/tb_tb_resize.vhd b/libraries/base/common/tb/vhdl/tb_tb_resize.vhd
index af84a20edf..fd5ac65da3 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_resize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_resize.vhd
@@ -20,7 +20,7 @@
-- Purpose: Multi tb for common_resize.vhd and RESIZE_NUM() in common_pkg.vhd
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_resize is
end tb_tb_resize;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_round.vhd b/libraries/base/common/tb/vhdl/tb_tb_round.vhd
index d6d452e9d1..a437ca42b2 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_round.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_round.vhd
@@ -20,7 +20,7 @@
-- Purpose: Multi tb for common_round.vhd and s_round(), u_round() in common_pkg.vhd
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_round is
end tb_tb_round;
diff --git a/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd b/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
index 1d2064de81..4038a7d1a3 100644
--- a/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
entity common_complex_mult_add is
generic (
@@ -72,68 +72,68 @@ architecture str of common_complex_mult_add is
begin
-- u_complex_mult : entity work.common_complex_mult(stratix4) -- requires sum of g_pipeline >= 3
u_complex_mult : entity work.common_complex_mult -- suits sum of g_pipeline >= 0
- generic map (
- g_technology => g_technology,
- g_variant => "RTL",
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_out_p_w => c_prod_w,
- g_conjugate_b => c_conjugate,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- out_pr => out_pr,
- out_pi => out_pi
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "RTL",
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => c_prod_w,
+ g_conjugate_b => c_conjugate,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => in_bi,
+ out_pr => out_pr,
+ out_pi => out_pi
+ );
add_inr <= RESIZE_SVEC(out_pr, g_out_p_w); -- Connect the output of the multiplier to the adders input
add_ini <= RESIZE_SVEC(out_pi, g_out_p_w);
u_adder_real : entity common_lib.common_add_sub
- generic map (
- g_direction => c_direction,
- g_representation => "SIGNED",
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => g_out_p_w,
- g_out_dat_w => g_out_p_w
- )
- port map (
- clk => clk,
- clken => '1',
- sel_add => c_sel_add,
- in_a => in_chr,
- in_b => add_inr,
- result => out_sumr
- );
+ generic map (
+ g_direction => c_direction,
+ g_representation => "SIGNED",
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => g_out_p_w,
+ g_out_dat_w => g_out_p_w
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ sel_add => c_sel_add,
+ in_a => in_chr,
+ in_b => add_inr,
+ result => out_sumr
+ );
u_adder_imag : entity common_lib.common_add_sub
- generic map (
- g_direction => c_direction,
- g_representation => "SIGNED",
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => g_out_p_w,
- g_out_dat_w => g_out_p_w
- )
- port map (
- clk => clk,
- clken => '1',
- sel_add => c_sel_add,
- in_a => in_chi,
- in_b => add_ini,
- result => out_sumi
- );
+ generic map (
+ g_direction => c_direction,
+ g_representation => "SIGNED",
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => g_out_p_w,
+ g_out_dat_w => g_out_p_w
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ sel_add => c_sel_add,
+ in_a => in_chi,
+ in_b => add_ini,
+ result => out_sumi
+ );
end str;
-- The rtl architecture follows the syntax that is given as example by Altera for inferring the DSP blocks.
@@ -154,30 +154,30 @@ begin
process (clk, rst, clken)
begin
if(rst = '1') then -- asynchronous reset
- ar_reg <= (others => '0');
- ai_reg <= (others => '0');
- br_reg <= (others => '0');
- bi_reg <= (others => '0');
- chr_reg <= (others => '0');
- chi_reg <= (others => '0');
- pr <= (others => '0');
- pi <= (others => '0');
- sumr <= (others => '0');
- sumi <= (others => '0');
+ ar_reg <= (others => '0');
+ ai_reg <= (others => '0');
+ br_reg <= (others => '0');
+ bi_reg <= (others => '0');
+ chr_reg <= (others => '0');
+ chi_reg <= (others => '0');
+ pr <= (others => '0');
+ pi <= (others => '0');
+ sumr <= (others => '0');
+ sumi <= (others => '0');
elsif(rising_edge(clk) and clken = '1') then -- rising clock edge
- ar_reg <= signed(in_ar);
- ai_reg <= signed(in_ai);
- br_reg <= signed(in_br);
- bi_reg <= signed(in_bi);
- chr_reg <= signed(in_chr);
- chi_reg <= signed(in_chi);
+ ar_reg <= signed(in_ar);
+ ai_reg <= signed(in_ai);
+ br_reg <= signed(in_br);
+ bi_reg <= signed(in_bi);
+ chr_reg <= signed(in_chr);
+ chi_reg <= signed(in_chi);
- pr <= RESIZE_NUM((ar_reg * br_reg), c_prod_w) - RESIZE_NUM((ai_reg * bi_reg), c_prod_w); -- Calculate the real part
- pi <= RESIZE_NUM((ar_reg * bi_reg), c_prod_w) + RESIZE_NUM((ai_reg * br_reg), c_prod_w); -- Calculate the imaginary part
+ pr <= RESIZE_NUM((ar_reg * br_reg), c_prod_w) - RESIZE_NUM((ai_reg * bi_reg), c_prod_w); -- Calculate the real part
+ pi <= RESIZE_NUM((ar_reg * bi_reg), c_prod_w) + RESIZE_NUM((ai_reg * br_reg), c_prod_w); -- Calculate the imaginary part
- sumr <= RESIZE_NUM(pr, g_out_p_w) + RESIZE_NUM(signed(in_chr), g_out_p_w); -- Add the chain_in real part to the real product
- sumi <= RESIZE_NUM(pi, g_out_p_w) + RESIZE_NUM(signed(in_chi), g_out_p_w); -- Add the chain_in imaginary part to the imaginary product
+ sumr <= RESIZE_NUM(pr, g_out_p_w) + RESIZE_NUM(signed(in_chr), g_out_p_w); -- Add the chain_in real part to the real product
+ sumi <= RESIZE_NUM(pi, g_out_p_w) + RESIZE_NUM(signed(in_chi), g_out_p_w); -- Add the chain_in imaginary part to the imaginary product
end if;
end process;
diff --git a/libraries/base/common_mult/src/vhdl/common_mult.vhd b/libraries/base/common_mult/src/vhdl/common_mult.vhd
index e533209b2a..1f440e0d06 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult.vhd
@@ -20,24 +20,24 @@
-------------------------------------------------------------------------------
library ieee, common_lib, tech_mult_lib, technology_lib;
-use ieee.std_logic_1164.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
--- Function: Default one or more independent products dependent on g_nof_mult
---
--- If g_nof_mult = 2 then the input vectors are
--- a = a(1) & a(0) and b = b(1) & b(0)
--- and the independent products in the product vector will be:
--- p = a(1)*b(1) & a(0)*b(0)
---
--- Remarks:
--- . When g_out_p_w < g_in_a_w+g_in_b_w then the common_mult truncates the
--- MSbit of the product.
--- . For c_prod_w = g_in_a_w+g_in_b_w the full product range is preserved. Use
--- g_out_p_w = c_prod_w-1 to skip the double sign bit that is only needed
--- when the maximum positive product -2**(g_in_a_w-1) * -2**(g_in_b_w-1) has
--- to be represented, which is typically not needed in DSP.
+ -- Function: Default one or more independent products dependent on g_nof_mult
+ --
+ -- If g_nof_mult = 2 then the input vectors are
+ -- a = a(1) & a(0) and b = b(1) & b(0)
+ -- and the independent products in the product vector will be:
+ -- p = a(1)*b(1) & a(0)*b(0)
+ --
+ -- Remarks:
+ -- . When g_out_p_w < g_in_a_w+g_in_b_w then the common_mult truncates the
+ -- MSbit of the product.
+ -- . For c_prod_w = g_in_a_w+g_in_b_w the full product range is preserved. Use
+ -- g_out_p_w = c_prod_w-1 to skip the double sign bit that is only needed
+ -- when the maximum positive product -2**(g_in_a_w-1) * -2**(g_in_b_w-1) has
+ -- to be represented, which is typically not needed in DSP.
entity common_mult is
generic (
@@ -73,56 +73,56 @@ architecture str of common_mult is
signal result : std_logic_vector(out_p'range); -- stage dependent on g_pipeline_output being 0 or 1
begin
u_mult : entity tech_mult_lib.tech_mult
- generic map(
- g_technology => g_technology,
- g_variant => g_variant,
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_out_p_w => g_out_p_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => g_representation
- )
- port map(
- rst => rst,
- clk => clk,
- clken => clken,
- in_a => in_a,
- in_b => in_b,
- out_p => result
- );
+ generic map(
+ g_technology => g_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => g_representation
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ out_p => result
+ );
-- Propagate in_val with c_pipeline latency
u_out_val : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_dat => in_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => c_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_dat => in_val,
+ out_dat => out_val
+ );
------------------------------------------------------------------------------
-- Extra output pipelining
------------------------------------------------------------------------------
u_output_pipe : entity common_lib.common_pipeline -- pipeline output
- generic map (
- g_representation => g_representation,
- g_pipeline => c_pipeline_output,
- g_in_dat_w => result'LENGTH,
- g_out_dat_w => result'length
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_dat => std_logic_vector(result),
- out_dat => out_p
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => c_pipeline_output,
+ g_in_dat_w => result'LENGTH,
+ g_out_dat_w => result'length
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_dat => std_logic_vector(result),
+ out_dat => out_p
+ );
end str;
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add.vhd
index 9c70318d26..4fa12a0b8e 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add.vhd
@@ -34,9 +34,9 @@
--
library ieee, common_lib;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use common_lib.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use common_lib.common_pkg.all;
entity common_mult_add is
generic (
@@ -55,10 +55,10 @@ entity common_mult_add is
in_b1 : in std_logic_vector(g_in_b_w - 1 downto 0);
out_dat : out std_logic_vector(g_out_dat_w - 1 downto 0)
);
-begin
- -- ASSERT g_pipeline=3
+ begin
+ -- ASSERT g_pipeline=3
-- REPORT "pipeline value not supported"
- -- SEVERITY FAILURE;
+ -- SEVERITY FAILURE;
end common_mult_add;
architecture rtl of common_mult_add is
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
index 397a229a0b..3968b49029 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
@@ -20,24 +20,24 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib, tech_mult_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
--- Function: vector low part product + or - vector high part product
--- Call:
--- a = a(1) & a(0)
--- b = b(1) & b(0)
--- then:
--- result = a(0)*b(0) + a(1)*b(1) when g_add_sub = "ADD"
--- result = a(0)*b(0) - a(1)*b(1) when g_add_sub = "SUB"
--- and:
--- res = RESIZE_NUM(result)
---
--- Architectures:
--- . rtl : uses RTL to have all registers in one clocked process
---
+ -- Function: vector low part product + or - vector high part product
+ -- Call:
+ -- a = a(1) & a(0)
+ -- b = b(1) & b(0)
+ -- then:
+ -- result = a(0)*b(0) + a(1)*b(1) when g_add_sub = "ADD"
+ -- result = a(0)*b(0) - a(1)*b(1) when g_add_sub = "SUB"
+ -- and:
+ -- res = RESIZE_NUM(result)
+ --
+ -- Architectures:
+ -- . rtl : uses RTL to have all registers in one clocked process
+ --
entity common_mult_add2 is
generic (
@@ -70,44 +70,44 @@ architecture str of common_mult_add2 is
signal result : std_logic_vector(res'range);
begin
u_mult_add2 : entity tech_mult_lib.tech_mult_add2
- generic map(
- g_technology => g_technology,
- g_variant => g_variant,
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_res_w => g_res_w,
- g_force_dsp => g_force_dsp,
- g_add_sub => g_add_sub,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map(
- rst => rst,
- clk => clk,
- clken => clken,
- in_a => in_a,
- in_b => in_b,
- res => result
- );
+ generic map(
+ g_technology => g_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_res_w => g_res_w,
+ g_force_dsp => g_force_dsp,
+ g_add_sub => g_add_sub,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ res => result
+ );
------------------------------------------------------------------------------
-- Extra output pipelining
------------------------------------------------------------------------------
u_output_pipe : entity common_lib.common_pipeline -- pipeline output
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_output,
- g_in_dat_w => res'LENGTH,
- g_out_dat_w => res'length
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => result,
- out_dat => res
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_output,
+ g_in_dat_w => res'LENGTH,
+ g_out_dat_w => res'length
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => result,
+ out_dat => res
+ );
end str;
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
index 088c8ccc9d..8aa7556a0a 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
@@ -20,27 +20,27 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib, tech_mult_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
--- Function: vector low part product + or - vector high part product
--- Call:
--- a = a(3) & a(2) & a(1) & a(0)
--- b = b(3) & b(2) & b(1) & b(0)
--- then: first sum first sum second sum
--- g_add_sub0 g_add_sub1 g_add_sub
--- result = (a(0)*b(0) + a(1)*b(1)) + ((a(2)*b(2) + a(3)*b(3))) when "ADD" "ADD" "ADD"
--- result = (a(0)*b(0) - a(1)*b(1)) + ((a(2)*b(2) + a(3)*b(3))) when "SUB" "ADD" "ADD"
--- result = (a(0)*b(0) + a(1)*b(1)) + ((a(2)*b(2) - a(3)*b(3))) when "ADD" "SUB" "ADD"
--- result = (a(0)*b(0) + a(1)*b(1)) - ((a(2)*b(2) + a(3)*b(3))) when "ADD" "SUB" "SUB"
--- and:
--- res = RESIZE(result)
---
--- Architectures:
--- . rtl : uses RTL to have all registers in one clocked process
---
+ -- Function: vector low part product + or - vector high part product
+ -- Call:
+ -- a = a(3) & a(2) & a(1) & a(0)
+ -- b = b(3) & b(2) & b(1) & b(0)
+ -- then: first sum first sum second sum
+ -- g_add_sub0 g_add_sub1 g_add_sub
+ -- result = (a(0)*b(0) + a(1)*b(1)) + ((a(2)*b(2) + a(3)*b(3))) when "ADD" "ADD" "ADD"
+ -- result = (a(0)*b(0) - a(1)*b(1)) + ((a(2)*b(2) + a(3)*b(3))) when "SUB" "ADD" "ADD"
+ -- result = (a(0)*b(0) + a(1)*b(1)) + ((a(2)*b(2) - a(3)*b(3))) when "ADD" "SUB" "ADD"
+ -- result = (a(0)*b(0) + a(1)*b(1)) - ((a(2)*b(2) + a(3)*b(3))) when "ADD" "SUB" "SUB"
+ -- and:
+ -- res = RESIZE(result)
+ --
+ -- Architectures:
+ -- . rtl : uses RTL to have all registers in one clocked process
+ --
entity common_mult_add4 is
generic (
@@ -75,46 +75,46 @@ architecture str of common_mult_add4 is
signal result : std_logic_vector(res'range);
begin
u_mult_add4 : entity tech_mult_lib.tech_mult_add4
- generic map(
- g_technology => g_technology,
- g_variant => g_variant,
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_res_w => g_res_w,
- g_force_dsp => g_force_dsp,
- g_add_sub0 => g_add_sub0,
- g_add_sub1 => g_add_sub1,
- g_add_sub => g_add_sub,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map(
- rst => rst,
- clk => clk,
- clken => clken,
- in_a => in_a,
- in_b => in_b,
- res => result
- );
+ generic map(
+ g_technology => g_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_res_w => g_res_w,
+ g_force_dsp => g_force_dsp,
+ g_add_sub0 => g_add_sub0,
+ g_add_sub1 => g_add_sub1,
+ g_add_sub => g_add_sub,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ res => result
+ );
------------------------------------------------------------------------------
-- Extra output pipelining
------------------------------------------------------------------------------
u_output_pipe : entity common_lib.common_pipeline -- pipeline output
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_output,
- g_in_dat_w => res'LENGTH,
- g_out_dat_w => res'length
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => result,
- out_dat => res
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_output,
+ g_in_dat_w => res'LENGTH,
+ g_out_dat_w => res'length
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => result,
+ out_dat => res
+ );
end str;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
index bd0dec1fcb..ad65dc951e 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
@@ -27,13 +27,13 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE, common_lib, technology_lib, tech_mult_lib, ip_stratixiv_mult_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_common_complex_mult is
generic (
@@ -217,76 +217,76 @@ begin
ref_result_im <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "IM", c_out_dat_w);
u_result_re : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => c_out_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => ref_result_re,
- out_dat => result_re_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => c_out_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => ref_result_re,
+ out_dat => result_re_expected
+ );
u_result_im : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => c_out_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => ref_result_im,
- out_dat => result_im_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => c_out_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => ref_result_im,
+ out_dat => result_im_expected
+ );
u_result_val_expected : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline,
- g_reset_value => 0
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_val,
- out_dat => result_val_expected
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_reset_value => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_val,
+ out_dat => result_val_expected
+ );
u_dut : entity work.common_complex_mult
- generic map (
- g_technology => c_technology,
- g_variant => g_variant,
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => c_out_dat_w,
- g_conjugate_b => g_conjugate_b,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- in_val => in_val,
- out_pr => result_re_dut,
- out_pi => result_im_dut,
- out_val => result_val_dut
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => c_out_dat_w,
+ g_conjugate_b => g_conjugate_b,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => in_bi,
+ in_val => in_val,
+ out_pr => result_re_dut,
+ out_pi => result_im_dut,
+ out_val => result_val_dut
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
index 811b71ec89..c52a2a49d1 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
@@ -27,11 +27,11 @@
-- > run -all
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_common_mult is
generic (
@@ -161,36 +161,36 @@ begin
-- pipeline inputs to ease comparison in the Wave window
u_in_a_pipeline : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_in_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_a,
- out_dat => in_a_p
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_in_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_a,
+ out_dat => in_a_p
+ );
u_in_b_pipeline : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_in_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_b,
- out_dat => in_b_p
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_in_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_b,
+ out_dat => in_b_p
+ );
gen_wires : for I in 0 to g_nof_mult - 1 generate
-- use same input for all multipliers
@@ -211,124 +211,124 @@ begin
uresult_ip <= uresult_arr_ip(g_out_dat_w - 1 downto 0);
u_sresult : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => out_sresult,
- out_dat => sresult_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => out_sresult,
+ out_dat => sresult_expected
+ );
u_uresult : entity common_lib.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => out_uresult,
- out_dat => uresult_expected
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => out_uresult,
+ out_dat => uresult_expected
+ );
u_sdut_rtl : entity work.common_mult
- generic map (
- g_technology => c_technology,
- g_variant => "RTL",
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => "SIGNED"
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a_arr,
- in_b => in_b_arr,
- out_p => sresult_arr_rtl
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => "RTL",
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => "SIGNED"
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a_arr,
+ in_b => in_b_arr,
+ out_p => sresult_arr_rtl
+ );
u_udut_rtl : entity work.common_mult
- generic map (
- g_technology => c_technology,
- g_variant => "RTL",
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => "UNSIGNED"
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a_arr,
- in_b => in_b_arr,
- out_p => uresult_arr_rtl
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => "RTL",
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => "UNSIGNED"
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a_arr,
+ in_b => in_b_arr,
+ out_p => uresult_arr_rtl
+ );
u_sdut_ip : entity work.common_mult
- generic map (
- g_technology => c_technology,
- g_variant => "IP",
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => "SIGNED"
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a_arr,
- in_b => in_b_arr,
- out_p => sresult_arr_ip
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => "IP",
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => "SIGNED"
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a_arr,
+ in_b => in_b_arr,
+ out_p => sresult_arr_ip
+ );
u_udut_ip : entity work.common_mult
- generic map (
- g_technology => c_technology,
- g_variant => "IP",
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => "UNSIGNED"
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a_arr,
- in_b => in_b_arr,
- out_p => uresult_arr_ip
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => "IP",
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => "UNSIGNED"
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a_arr,
+ in_b => in_b_arr,
+ out_p => uresult_arr_ip
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
index b2e150e364..f098b4a78f 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
@@ -27,10 +27,10 @@
-- > run -all
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_common_mult_add2 is
generic (
@@ -175,42 +175,42 @@ begin
out_result <= func_result(in_a0, in_b0, in_a1, in_b1);
u_result : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => out_result,
- out_dat => result_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => out_result,
+ out_dat => result_expected
+ );
u_dut_rtl : entity work.common_mult_add2
- generic map (
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_res_w => g_out_dat_w, -- g_in_a_w + g_in_b_w + log2(2)
- g_force_dsp => g_force_dsp, -- not applicable for 'rtl'
- g_add_sub => g_add_sub,
- g_nof_mult => 2,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a,
- in_b => in_b,
- res => result_rtl
- );
+ generic map (
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_res_w => g_out_dat_w, -- g_in_a_w + g_in_b_w + log2(2)
+ g_force_dsp => g_force_dsp, -- not applicable for 'rtl'
+ g_add_sub => g_add_sub,
+ g_nof_mult => 2,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a,
+ in_b => in_b,
+ res => result_rtl
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
index a8b7dfd246..3c540b41a9 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
@@ -26,9 +26,9 @@
-- --------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_tb_common_complex_mult is
end tb_tb_common_complex_mult;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
index d08b846610..4728866d94 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
@@ -24,7 +24,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_mult is
end tb_tb_common_mult;
diff --git a/libraries/base/diag/src/vhdl/diag_block_gen.vhd b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
index 7163a9b310..6d820c74cd 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
@@ -73,11 +73,11 @@
-- . out_sosi.re(g_buf_dat_w/2-1: 0)
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity diag_block_gen is
generic (
@@ -124,175 +124,175 @@ architecture rtl of diag_block_gen is
signal out_sosi_i : t_dp_sosi := c_dp_sosi_rst; -- Signal used to assign reset values to output
signal xon_reg : std_logic := '0';
begin
- -- xon is not clk cycle timing critical, so can use register xon to ease timing closure
- xon_reg <= out_siso.xon when rising_edge(clk);
+ -- xon is not clk cycle timing critical, so can use register xon to ease timing closure
+ xon_reg <= out_siso.xon when rising_edge(clk);
- p_comb : process(r, rst, ctrl, en_sync, out_siso, xon_reg)
- variable v : reg_type;
- variable v_samples_per_packet : natural;
- variable v_gapsize : natural;
- variable v_blocks_per_sync : natural;
- variable v_mem_low_adrs : natural;
- variable v_mem_high_adrs : natural;
- begin
- v_samples_per_packet := TO_UINT(r.ctrl_hold.samples_per_packet);
- v_gapsize := TO_UINT(r.ctrl_hold.gapsize);
- v_blocks_per_sync := TO_UINT(r.ctrl_hold.blocks_per_sync);
- v_mem_low_adrs := TO_UINT(r.ctrl_hold.mem_low_adrs);
- v_mem_high_adrs := TO_UINT(r.ctrl_hold.mem_high_adrs);
+ p_comb : process(r, rst, ctrl, en_sync, out_siso, xon_reg)
+ variable v : reg_type;
+ variable v_samples_per_packet : natural;
+ variable v_gapsize : natural;
+ variable v_blocks_per_sync : natural;
+ variable v_mem_low_adrs : natural;
+ variable v_mem_high_adrs : natural;
+ begin
+ v_samples_per_packet := TO_UINT(r.ctrl_hold.samples_per_packet);
+ v_gapsize := TO_UINT(r.ctrl_hold.gapsize);
+ v_blocks_per_sync := TO_UINT(r.ctrl_hold.blocks_per_sync);
+ v_mem_low_adrs := TO_UINT(r.ctrl_hold.mem_low_adrs);
+ v_mem_high_adrs := TO_UINT(r.ctrl_hold.mem_high_adrs);
- v := r; -- default hold all r fields
- v.pls_sync := '0';
- v.valid := '0';
- v.sop := '0';
- v.eop := '0';
- v.rd_ena := '0';
+ v := r; -- default hold all r fields
+ v.pls_sync := '0';
+ v.valid := '0';
+ v.sop := '0';
+ v.eop := '0';
+ v.rd_ena := '0';
- -- Control block generator enable
- if ctrl.enable_sync = '0' then
- -- apply ctrl.enable immediately
+ -- Control block generator enable
+ if ctrl.enable_sync = '0' then
+ -- apply ctrl.enable immediately
+ v.blk_en := ctrl.enable;
+ else
+ -- keep blk_en and apply ctrl.enable (on or off) at input sync pulse
+ if en_sync = '1' then
v.blk_en := ctrl.enable;
- else
- -- keep blk_en and apply ctrl.enable (on or off) at input sync pulse
- if en_sync = '1' then
- v.blk_en := ctrl.enable;
- end if;
end if;
+ end if;
- -- The pulse sync is high at the sop of the first block, the block sync is high during the entire block until the eop
- if r.eop = '1' then
- v.blk_sync := '0';
- end if;
+ -- The pulse sync is high at the sop of the first block, the block sync is high during the entire block until the eop
+ if r.eop = '1' then
+ v.blk_sync := '0';
+ end if;
- -- Increment the block sequence number counter after each block
- if r.eop = '1' then
- v.bsn_cnt := incr_uvec(r.bsn_cnt, 1);
- end if;
+ -- Increment the block sequence number counter after each block
+ if r.eop = '1' then
+ v.bsn_cnt := incr_uvec(r.bsn_cnt, 1);
+ end if;
- case r.state is
- when s_idle =>
- v.blk_xon := xon_reg;
- v.blk_sync := '0';
- v.samples_cnt := 0;
- v.blocks_cnt := 0;
- v.mem_cnt := v_mem_low_adrs;
- if r.blk_en = '1' then -- Wait until enabled
- if xon_reg = '1' then -- Wait until XON is 1
- v.ctrl_hold := ctrl; -- hold new control settings while BG is enabled
- v.bsn_cnt := ctrl.bsn_init;
- v.rd_ena := '1';
- v.state := s_block;
- end if;
+ case r.state is
+ when s_idle =>
+ v.blk_xon := xon_reg;
+ v.blk_sync := '0';
+ v.samples_cnt := 0;
+ v.blocks_cnt := 0;
+ v.mem_cnt := v_mem_low_adrs;
+ if r.blk_en = '1' then -- Wait until enabled
+ if xon_reg = '1' then -- Wait until XON is 1
+ v.ctrl_hold := ctrl; -- hold new control settings while BG is enabled
+ v.bsn_cnt := ctrl.bsn_init;
+ v.rd_ena := '1';
+ v.state := s_block;
end if;
+ end if;
- when s_block =>
- if out_siso.ready = '1' then
-
- v.rd_ena := '1'; -- read next data
- if r.samples_cnt = 0 and r.blocks_cnt = 0 then
- v.pls_sync := '1'; -- Always start with a pulse sync
- v.blk_sync := '1';
- v.sop := '1';
- v.samples_cnt := v.samples_cnt + 1;
- elsif r.samples_cnt = 0 then
- v.sop := '1';
- v.samples_cnt := v.samples_cnt + 1;
- elsif r.samples_cnt >= v_samples_per_packet - 1 and v_gapsize = 0 and r.blocks_cnt >= v_blocks_per_sync - 1 then
- v.eop := '1';
- v.samples_cnt := 0;
- v.blocks_cnt := 0;
- elsif r.samples_cnt >= v_samples_per_packet - 1 and v_gapsize = 0 then
- v.eop := '1';
- v.samples_cnt := 0;
- v.blocks_cnt := r.blocks_cnt + 1;
- elsif r.samples_cnt >= v_samples_per_packet - 1 then
- v.eop := '1';
- v.samples_cnt := 0;
- v.rd_ena := '0';
- v.state := s_gap;
- else
- v.samples_cnt := r.samples_cnt + 1;
- end if;
- v.valid := '1'; -- output pending data
-
- if r.mem_cnt >= v_mem_high_adrs then
- v.mem_cnt := v_mem_low_adrs;
- else
- v.mem_cnt := r.mem_cnt + 1;
- end if;
+ when s_block =>
+ if out_siso.ready = '1' then
- if v.eop = '1' and r.blk_en = '0' then
- v.state := s_idle; -- accept disable after eop, not during block
- end if;
- end if; -- out_siso.ready='1'
- if r.eop = '1' then
- v.blk_xon := xon_reg; -- accept XOFF after eop, not during block
- end if;
-
- when s_gap =>
- if r.samples_cnt >= v_gapsize-1 and r.blocks_cnt >= v_blocks_per_sync - 1 then
+ v.rd_ena := '1'; -- read next data
+ if r.samples_cnt = 0 and r.blocks_cnt = 0 then
+ v.pls_sync := '1'; -- Always start with a pulse sync
+ v.blk_sync := '1';
+ v.sop := '1';
+ v.samples_cnt := v.samples_cnt + 1;
+ elsif r.samples_cnt = 0 then
+ v.sop := '1';
+ v.samples_cnt := v.samples_cnt + 1;
+ elsif r.samples_cnt >= v_samples_per_packet - 1 and v_gapsize = 0 and r.blocks_cnt >= v_blocks_per_sync - 1 then
+ v.eop := '1';
v.samples_cnt := 0;
v.blocks_cnt := 0;
- v.rd_ena := '1';
- v.state := s_block;
- elsif r.samples_cnt >= v_gapsize-1 then
+ elsif r.samples_cnt >= v_samples_per_packet - 1 and v_gapsize = 0 then
+ v.eop := '1';
v.samples_cnt := 0;
v.blocks_cnt := r.blocks_cnt + 1;
- v.rd_ena := '1';
- v.state := s_block;
+ elsif r.samples_cnt >= v_samples_per_packet - 1 then
+ v.eop := '1';
+ v.samples_cnt := 0;
+ v.rd_ena := '0';
+ v.state := s_gap;
else
v.samples_cnt := r.samples_cnt + 1;
end if;
+ v.valid := '1'; -- output pending data
+
+ if r.mem_cnt >= v_mem_high_adrs then
+ v.mem_cnt := v_mem_low_adrs;
+ else
+ v.mem_cnt := r.mem_cnt + 1;
+ end if;
- if r.blk_en = '0' then
- v.state := s_idle;
+ if v.eop = '1' and r.blk_en = '0' then
+ v.state := s_idle; -- accept disable after eop, not during block
end if;
- v.blk_xon := xon_reg;
+ end if; -- out_siso.ready='1'
+ if r.eop = '1' then
+ v.blk_xon := xon_reg; -- accept XOFF after eop, not during block
+ end if;
+
+ when s_gap =>
+ if r.samples_cnt >= v_gapsize-1 and r.blocks_cnt >= v_blocks_per_sync - 1 then
+ v.samples_cnt := 0;
+ v.blocks_cnt := 0;
+ v.rd_ena := '1';
+ v.state := s_block;
+ elsif r.samples_cnt >= v_gapsize-1 then
+ v.samples_cnt := 0;
+ v.blocks_cnt := r.blocks_cnt + 1;
+ v.rd_ena := '1';
+ v.state := s_block;
+ else
+ v.samples_cnt := r.samples_cnt + 1;
+ end if;
- when others =>
+ if r.blk_en = '0' then
v.state := s_idle;
- end case;
+ end if;
+ v.blk_xon := xon_reg;
- if rst = '1' then
- v.ctrl_hold := c_diag_block_gen_rst;
- v.blk_en := '0';
- v.blk_xon := '0';
- v.blk_sync := '0';
- v.pls_sync := '0';
- v.valid := '0';
- v.sop := '0';
- v.eop := '0';
- v.rd_ena := '0';
- v.samples_cnt := 0;
- v.blocks_cnt := 0;
- v.bsn_cnt := (others => '0');
- v.mem_cnt := 0;
- v.state := s_idle;
- end if;
+ when others =>
+ v.state := s_idle;
+ end case;
- rin <= v;
- end process;
+ if rst = '1' then
+ v.ctrl_hold := c_diag_block_gen_rst;
+ v.blk_en := '0';
+ v.blk_xon := '0';
+ v.blk_sync := '0';
+ v.pls_sync := '0';
+ v.valid := '0';
+ v.sop := '0';
+ v.eop := '0';
+ v.rd_ena := '0';
+ v.samples_cnt := 0;
+ v.blocks_cnt := 0;
+ v.bsn_cnt := (others => '0');
+ v.mem_cnt := 0;
+ v.state := s_idle;
+ end if;
- p_regs : process(rst, clk)
- begin
- if rising_edge(clk) then
- r <= rin;
- end if;
- end process;
+ rin <= v;
+ end process;
+
+ p_regs : process(rst, clk)
+ begin
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+ end process;
- -- Connect to the outside world
- out_sosi_i.sop <= r.sop and r.blk_xon;
- out_sosi_i.eop <= r.eop and r.blk_xon;
- out_sosi_i.sync <= r.pls_sync and r.blk_xon when g_blk_sync = false else r.blk_sync and r.blk_xon;
- out_sosi_i.valid <= r.valid and r.blk_xon;
- out_sosi_i.bsn <= r.bsn_cnt;
- out_sosi_i.re <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w / 2 - 1 downto 0)); -- treat as signed
- out_sosi_i.im <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w - 1 downto g_buf_dat_w / 2)); -- treat as signed
- out_sosi_i.data <= RESIZE_DP_DATA( buf_rddat(g_buf_dat_w - 1 downto 0)); -- treat as unsigned
+ -- Connect to the outside world
+ out_sosi_i.sop <= r.sop and r.blk_xon;
+ out_sosi_i.eop <= r.eop and r.blk_xon;
+ out_sosi_i.sync <= r.pls_sync and r.blk_xon when g_blk_sync = false else r.blk_sync and r.blk_xon;
+ out_sosi_i.valid <= r.valid and r.blk_xon;
+ out_sosi_i.bsn <= r.bsn_cnt;
+ out_sosi_i.re <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w / 2 - 1 downto 0)); -- treat as signed
+ out_sosi_i.im <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w - 1 downto g_buf_dat_w / 2)); -- treat as signed
+ out_sosi_i.data <= RESIZE_DP_DATA( buf_rddat(g_buf_dat_w - 1 downto 0)); -- treat as unsigned
- out_sosi <= out_sosi_i;
- buf_addr <= TO_UVEC(r.mem_cnt, g_buf_addr_w);
- buf_rden <= r.rd_ena;
+ out_sosi <= out_sosi_i;
+ buf_addr <= TO_UVEC(r.mem_cnt, g_buf_addr_w);
+ buf_rden <= r.rd_ena;
- ctrl_hold <= r.ctrl_hold;
+ ctrl_hold <= r.ctrl_hold;
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd b/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
index 018ca44aef..32f6755dd3 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
entity diag_block_gen_reg is
generic (
@@ -58,59 +58,59 @@ begin
p_mm_reg : process (mm_rst, mm_clk)
begin
if(mm_rst = '1') then
- mm_miso <= c_mem_miso_rst;
- mm_bg_ctrl <= g_diag_block_gen_rst;
+ mm_miso <= c_mem_miso_rst;
+ mm_bg_ctrl <= g_diag_block_gen_rst;
elsif(rising_edge(mm_clk)) then
- -- Read access defaults
- mm_miso.rdval <= '0';
- -- Write access: set register value
- if(mm_mosi.wr = '1') then
- case TO_UINT(mm_mosi.address(c_adrs_width - 1 downto 0)) is
- when 0 =>
- mm_bg_ctrl.enable <= mm_mosi.wrdata(0);
- mm_bg_ctrl.enable_sync <= mm_mosi.wrdata(1);
- when 1 =>
- mm_bg_ctrl.samples_per_packet <= mm_mosi.wrdata(c_diag_bg_samples_per_packet_w - 1 downto 0);
- when 2 =>
- mm_bg_ctrl.blocks_per_sync <= mm_mosi.wrdata(c_diag_bg_blocks_per_sync_w - 1 downto 0);
- when 3 =>
- mm_bg_ctrl.gapsize <= mm_mosi.wrdata(c_diag_bg_gapsize_w - 1 downto 0);
- when 4 =>
- mm_bg_ctrl.mem_low_adrs <= mm_mosi.wrdata(c_diag_bg_mem_low_adrs_w - 1 downto 0);
- when 5 =>
- mm_bg_ctrl.mem_high_adrs <= mm_mosi.wrdata(c_diag_bg_mem_high_adrs_w - 1 downto 0);
- when 6 =>
- mm_bg_ctrl.bsn_init(31 downto 0) <= mm_mosi.wrdata(31 downto 0);
- when 7 =>
- mm_bg_ctrl.bsn_init(63 downto 32) <= mm_mosi.wrdata(31 downto 0);
- when others => null; -- not used MM addresses
- end case;
- -- Read access: get register value
- elsif mm_mosi.rd = '1' then
- mm_miso <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- mm_miso.rdval <= '1';
- case TO_UINT(mm_mosi.address(c_adrs_width - 1 downto 0)) is
- -- Read Block Sync
- when 0 =>
- mm_miso.rddata(0) <= mm_bg_ctrl.enable;
- mm_miso.rddata(1) <= mm_bg_ctrl.enable_sync;
- when 1 =>
- mm_miso.rddata(c_diag_bg_samples_per_packet_w - 1 downto 0) <= mm_bg_ctrl.samples_per_packet;
- when 2 =>
- mm_miso.rddata(c_diag_bg_blocks_per_sync_w - 1 downto 0) <= mm_bg_ctrl.blocks_per_sync;
- when 3 =>
- mm_miso.rddata(c_diag_bg_gapsize_w - 1 downto 0) <= mm_bg_ctrl.gapsize;
- when 4 =>
- mm_miso.rddata(c_diag_bg_mem_low_adrs_w - 1 downto 0) <= mm_bg_ctrl.mem_low_adrs;
- when 5 =>
- mm_miso.rddata(c_diag_bg_mem_high_adrs_w - 1 downto 0) <= mm_bg_ctrl.mem_high_adrs;
- when 6 =>
- mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(31 downto 0);
- when 7 =>
- mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(63 downto 32);
- when others => null; -- not used MM addresses
- end case;
- end if;
+ -- Read access defaults
+ mm_miso.rdval <= '0';
+ -- Write access: set register value
+ if(mm_mosi.wr = '1') then
+ case TO_UINT(mm_mosi.address(c_adrs_width - 1 downto 0)) is
+ when 0 =>
+ mm_bg_ctrl.enable <= mm_mosi.wrdata(0);
+ mm_bg_ctrl.enable_sync <= mm_mosi.wrdata(1);
+ when 1 =>
+ mm_bg_ctrl.samples_per_packet <= mm_mosi.wrdata(c_diag_bg_samples_per_packet_w - 1 downto 0);
+ when 2 =>
+ mm_bg_ctrl.blocks_per_sync <= mm_mosi.wrdata(c_diag_bg_blocks_per_sync_w - 1 downto 0);
+ when 3 =>
+ mm_bg_ctrl.gapsize <= mm_mosi.wrdata(c_diag_bg_gapsize_w - 1 downto 0);
+ when 4 =>
+ mm_bg_ctrl.mem_low_adrs <= mm_mosi.wrdata(c_diag_bg_mem_low_adrs_w - 1 downto 0);
+ when 5 =>
+ mm_bg_ctrl.mem_high_adrs <= mm_mosi.wrdata(c_diag_bg_mem_high_adrs_w - 1 downto 0);
+ when 6 =>
+ mm_bg_ctrl.bsn_init(31 downto 0) <= mm_mosi.wrdata(31 downto 0);
+ when 7 =>
+ mm_bg_ctrl.bsn_init(63 downto 32) <= mm_mosi.wrdata(31 downto 0);
+ when others => null; -- not used MM addresses
+ end case;
+ -- Read access: get register value
+ elsif mm_mosi.rd = '1' then
+ mm_miso <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
+ mm_miso.rdval <= '1';
+ case TO_UINT(mm_mosi.address(c_adrs_width - 1 downto 0)) is
+ -- Read Block Sync
+ when 0 =>
+ mm_miso.rddata(0) <= mm_bg_ctrl.enable;
+ mm_miso.rddata(1) <= mm_bg_ctrl.enable_sync;
+ when 1 =>
+ mm_miso.rddata(c_diag_bg_samples_per_packet_w - 1 downto 0) <= mm_bg_ctrl.samples_per_packet;
+ when 2 =>
+ mm_miso.rddata(c_diag_bg_blocks_per_sync_w - 1 downto 0) <= mm_bg_ctrl.blocks_per_sync;
+ when 3 =>
+ mm_miso.rddata(c_diag_bg_gapsize_w - 1 downto 0) <= mm_bg_ctrl.gapsize;
+ when 4 =>
+ mm_miso.rddata(c_diag_bg_mem_low_adrs_w - 1 downto 0) <= mm_bg_ctrl.mem_low_adrs;
+ when 5 =>
+ mm_miso.rddata(c_diag_bg_mem_high_adrs_w - 1 downto 0) <= mm_bg_ctrl.mem_high_adrs;
+ when 6 =>
+ mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(31 downto 0);
+ when 7 =>
+ mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(63 downto 32);
+ when others => null; -- not used MM addresses
+ end case;
+ end if;
end if;
end process;
@@ -139,15 +139,15 @@ begin
-- Assume diag BG enable gets written last, so when diag BG enable is transfered properly to the dp_clk domain, then
-- the other diag BG control fields are stable as well
u_bg_enable : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- din => mm_bg_ctrl.enable,
- dout => dp_bg_ctrl.enable
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ din => mm_bg_ctrl.enable,
+ dout => dp_bg_ctrl.enable
+ );
dp_bg_ctrl.enable_sync <= mm_bg_ctrl.enable_sync;
dp_bg_ctrl.samples_per_packet <= mm_bg_ctrl.samples_per_packet;
dp_bg_ctrl.blocks_per_sync <= mm_bg_ctrl.blocks_per_sync;
diff --git a/libraries/base/diag/src/vhdl/diag_bypass.vhd b/libraries/base/diag/src/vhdl/diag_bypass.vhd
index 506398a3d5..dc8a7771cc 100644
--- a/libraries/base/diag/src/vhdl/diag_bypass.vhd
+++ b/libraries/base/diag/src/vhdl/diag_bypass.vhd
@@ -21,9 +21,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity diag_bypass is
generic (
@@ -84,7 +84,7 @@ begin
end process;
output_switch_proc : process (bypass_en, mod_out_dat_x, mod_out_val, mod_out_sync,
- in_dat_x, in_val, in_sync, mod_out_dat_y, in_dat_y)
+ in_dat_x, in_val, in_sync, mod_out_dat_y, in_dat_y)
begin
nxt_out_dat_x <= RESIZE_SVEC(mod_out_dat_x, out_dat_x'length);
nxt_out_dat_y <= RESIZE_SVEC(mod_out_dat_y, out_dat_y'length);
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
index f0211b988e..f0a53b7654 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
@@ -44,12 +44,12 @@
-- a c_word_w parts.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity diag_data_buffer is
generic (
@@ -85,23 +85,26 @@ architecture rtl of diag_data_buffer is
constant c_nof_data_mm : natural := g_nof_data * c_mm_factor;
constant g_data_mm_w : natural := g_data_w / c_mm_factor;
- constant c_buf_mm : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_data_mm),
- dat_w => g_data_mm_w,
- nof_dat => c_nof_data_mm,
- init_sl => '0');
-
- constant c_buf_st : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_data),
- dat_w => g_data_w,
- nof_dat => g_nof_data,
- init_sl => '0');
-
- constant c_reg : t_c_mem := (latency => 1,
- adr_w => c_diag_db_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_diag_db_reg_nof_dat, -- 1: word_cnt; 0:sync_cnt
- init_sl => '0');
+ constant c_buf_mm : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_data_mm),
+ dat_w => g_data_mm_w,
+ nof_dat => c_nof_data_mm,
+ init_sl => '0');
+
+ constant c_buf_st : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_data),
+ dat_w => g_data_w,
+ nof_dat => g_nof_data,
+ init_sl => '0');
+
+ constant c_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_diag_db_reg_adr_w,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_diag_db_reg_nof_dat, -- 1: word_cnt; 0:sync_cnt
+ init_sl => '0');
signal i_ram_mm_miso : t_mem_miso := c_mem_miso_rst; -- used to avoid vsim-8684 error "No drivers exist" for the unused fields
@@ -134,17 +137,17 @@ begin
-- Determine the write trigger
use_rd_last : if g_use_in_sync = false generate
u_wr_sync : entity common_lib.common_spulse
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => rd_last,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => wr_sync
- );
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => rd_last,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => wr_sync
+ );
end generate;
use_in_sync : if g_use_in_sync = true generate
@@ -188,73 +191,73 @@ begin
end process;
u_buf : entity common_lib.common_ram_crw_crw_ratio
- generic map (
- g_technology => g_technology,
- g_ram_a => c_buf_mm,
- g_ram_b => c_buf_st,
- g_init_file => "UNUSED"
- )
- port map (
- -- MM read/write port clock domain
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_mm_mosi.wr,
- wr_dat_a => ram_mm_mosi.wrdata(c_buf_mm.dat_w - 1 downto 0),
- adr_a => ram_mm_mosi.address(c_buf_mm.adr_w - 1 downto 0),
- rd_en_a => ram_mm_mosi.rd,
- rd_dat_a => i_ram_mm_miso.rddata(c_buf_mm.dat_w - 1 downto 0),
- rd_val_a => i_ram_mm_miso.rdval,
-
- -- ST write only port clock domain
- rst_b => st_rst,
- clk_b => st_clk,
- wr_en_b => wr_en,
- wr_dat_b => wr_data,
- adr_b => wr_addr,
- rd_en_b => '0',
- rd_dat_b => OPEN,
- rd_val_b => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram_a => c_buf_mm,
+ g_ram_b => c_buf_st,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ -- MM read/write port clock domain
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_mm_mosi.wr,
+ wr_dat_a => ram_mm_mosi.wrdata(c_buf_mm.dat_w - 1 downto 0),
+ adr_a => ram_mm_mosi.address(c_buf_mm.adr_w - 1 downto 0),
+ rd_en_a => ram_mm_mosi.rd,
+ rd_dat_a => i_ram_mm_miso.rddata(c_buf_mm.dat_w - 1 downto 0),
+ rd_val_a => i_ram_mm_miso.rdval,
+
+ -- ST write only port clock domain
+ rst_b => st_rst,
+ clk_b => st_clk,
+ wr_en_b => wr_en,
+ wr_dat_b => wr_data,
+ adr_b => wr_addr,
+ rd_en_b => '0',
+ rd_dat_b => OPEN,
+ rd_val_b => open
+ );
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_reg => c_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mm_mosi,
- sla_out => reg_mm_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => reg_rd_arr,
- in_reg => reg_slv,
- out_reg => open
- );
+ generic map (
+ g_reg => c_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mm_mosi,
+ sla_out => reg_mm_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => reg_rd_arr,
+ in_reg => reg_slv,
+ out_reg => open
+ );
reg_slv <= word_cnt & sync_cnt;
u_word_cnt : entity common_lib.common_counter
- port map (
- rst => st_rst,
- clk => st_clk,
- cnt_en => wr_en,
- cnt_clr => wr_sync,
- count => word_cnt
- );
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ cnt_en => wr_en,
+ cnt_clr => wr_sync,
+ count => word_cnt
+ );
u_sync_cnt : entity common_lib.common_counter
- port map (
- rst => st_rst,
- clk => st_clk,
- cnt_en => wr_sync,
- cnt_clr => sync_cnt_clr,
- count => sync_cnt
- );
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ cnt_en => wr_sync,
+ cnt_clr => sync_cnt_clr,
+ count => sync_cnt
+ );
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
index 278e607ea2..de5aad5966 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
@@ -65,12 +65,12 @@
-- a c_word_w parts.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity diag_data_buffer_dev is
generic (
@@ -108,23 +108,26 @@ architecture rtl of diag_data_buffer_dev is
constant c_nof_data_mm : natural := g_nof_data * c_mm_factor;
constant g_data_mm_w : natural := g_data_w / c_mm_factor;
- constant c_buf_mm : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_data_mm),
- dat_w => g_data_mm_w,
- nof_dat => c_nof_data_mm,
- init_sl => '0');
-
- constant c_buf_st : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_data),
- dat_w => g_data_w,
- nof_dat => g_nof_data,
- init_sl => '0');
-
- constant c_reg : t_c_mem := (latency => 1,
- adr_w => c_diag_db_dev_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_diag_db_dev_reg_nof_dat, -- 3: reg_sync_delay 2: valid_cnt 1: word_cnt; 0:sync_cnt
- init_sl => '0');
+ constant c_buf_mm : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_data_mm),
+ dat_w => g_data_mm_w,
+ nof_dat => c_nof_data_mm,
+ init_sl => '0');
+
+ constant c_buf_st : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_data),
+ dat_w => g_data_w,
+ nof_dat => g_nof_data,
+ init_sl => '0');
+
+ constant c_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_diag_db_dev_reg_adr_w,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_diag_db_dev_reg_nof_dat, -- 3: reg_sync_delay 2: valid_cnt 1: word_cnt; 0:sync_cnt
+ init_sl => '0');
signal i_ram_mm_miso : t_mem_miso := c_mem_miso_rst; -- used to avoid vsim-8684 error "No drivers exist" for the unused fields
@@ -172,17 +175,17 @@ begin
rd_last <= '1' when unsigned(ram_mm_mosi.address(c_buf_mm.adr_w - 1 downto 0)) = c_nof_data_mm - 1 and ram_mm_mosi.rd = '1' else '0';
u_rd_last_clock_cross : entity common_lib.common_spulse
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => rd_last,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => rd_last_st
- );
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => rd_last,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => rd_last_st
+ );
-- Determine the write trigger in NON-SYNC MODE
use_rd_last : if g_use_in_sync = false generate
@@ -284,55 +287,55 @@ begin
end process;
u_buf : entity common_lib.common_ram_crw_crw_ratio
- generic map (
- g_technology => g_technology,
- g_ram_a => c_buf_mm,
- g_ram_b => c_buf_st,
- g_init_file => "UNUSED"
- )
- port map (
- -- MM read/write port clock domain
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_mm_mosi.wr,
- wr_dat_a => ram_mm_mosi.wrdata(c_buf_mm.dat_w - 1 downto 0),
- adr_a => ram_mm_mosi.address(c_buf_mm.adr_w - 1 downto 0),
- rd_en_a => ram_mm_mosi.rd,
- rd_dat_a => i_ram_mm_miso.rddata(c_buf_mm.dat_w - 1 downto 0),
- rd_val_a => i_ram_mm_miso.rdval,
-
- -- ST write only port clock domain
- rst_b => st_rst,
- clk_b => st_clk,
- wr_en_b => wr_en,
- wr_dat_b => wr_data,
- adr_b => wr_addr,
- rd_en_b => '0',
- rd_dat_b => OPEN,
- rd_val_b => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram_a => c_buf_mm,
+ g_ram_b => c_buf_st,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ -- MM read/write port clock domain
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_mm_mosi.wr,
+ wr_dat_a => ram_mm_mosi.wrdata(c_buf_mm.dat_w - 1 downto 0),
+ adr_a => ram_mm_mosi.address(c_buf_mm.adr_w - 1 downto 0),
+ rd_en_a => ram_mm_mosi.rd,
+ rd_dat_a => i_ram_mm_miso.rddata(c_buf_mm.dat_w - 1 downto 0),
+ rd_val_a => i_ram_mm_miso.rdval,
+
+ -- ST write only port clock domain
+ rst_b => st_rst,
+ clk_b => st_clk,
+ wr_en_b => wr_en,
+ wr_dat_b => wr_data,
+ adr_b => wr_addr,
+ rd_en_b => '0',
+ rd_dat_b => OPEN,
+ rd_val_b => open
+ );
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_reg => c_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mm_mosi,
- sla_out => reg_mm_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => reg_wr_arr,
- reg_rd_arr => reg_rd_arr,
- in_reg => reg_slv_rd,
- out_reg => reg_slv_wr
- );
+ generic map (
+ g_reg => c_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mm_mosi,
+ sla_out => reg_mm_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => reg_wr_arr,
+ reg_rd_arr => reg_rd_arr,
+ in_reg => reg_slv_rd,
+ out_reg => reg_slv_wr
+ );
arm_enable <= reg_wr_arr(2);
reg_sync_delay <= reg_slv_wr(4 * c_word_w - 1 downto 3 * c_word_w);
@@ -340,29 +343,29 @@ begin
reg_sync_delay & valid_cnt & word_cnt & sync_cnt;
u_word_cnt : entity common_lib.common_counter
- port map (
- rst => st_rst,
- clk => st_clk,
- cnt_en => wr_en,
- cnt_clr => wr_sync,
- count => word_cnt
- );
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ cnt_en => wr_en,
+ cnt_clr => wr_sync,
+ count => word_cnt
+ );
u_sync_cnt : entity common_lib.common_counter
- port map (
- rst => st_rst,
- clk => st_clk,
- cnt_en => wr_sync,
- cnt_clr => sync_cnt_clr,
- count => sync_cnt
- );
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ cnt_en => wr_sync,
+ cnt_clr => sync_cnt_clr,
+ count => sync_cnt
+ );
u_valid_cnt : entity common_lib.common_counter
- port map (
- rst => st_rst,
- clk => st_clk,
- cnt_en => in_val,
- cnt_clr => in_sync,
- count => valid_cnt
- );
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ cnt_en => in_val,
+ cnt_clr => in_sync,
+ count => valid_cnt
+ );
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_frm_generator.vhd b/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
index cccb660269..8acd6ef277 100644
--- a/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
+++ b/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
@@ -21,27 +21,27 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-
--- Purpose: Generate a stream of frames with test sequence data.
--- Description:
--- Each frame has g_frame_len words of out_dat. The test data can be PRSG or
--- COUNTER dependent on diag_sel, or constant data when diag_dc='1'.
--- The frame generator is enabled by diag_en. The actual frame rate depends
--- on the g_sop_period and on out_ready.
--- The out_ready acts as a data request. During a frame the out_dat is valid
--- for every active out_ready, to support streaming flow control.
--- Remark:
--- . This component can be easily mapped to standard MM and ST interfaces.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+
+ -- Purpose: Generate a stream of frames with test sequence data.
+ -- Description:
+ -- Each frame has g_frame_len words of out_dat. The test data can be PRSG or
+ -- COUNTER dependent on diag_sel, or constant data when diag_dc='1'.
+ -- The frame generator is enabled by diag_en. The actual frame rate depends
+ -- on the g_sop_period and on out_ready.
+ -- The out_ready acts as a data request. During a frame the out_dat is valid
+ -- for every active out_ready, to support streaming flow control.
+ -- Remark:
+ -- . This component can be easily mapped to standard MM and ST interfaces.
entity diag_frm_generator is
generic (
g_sel : std_logic := '1'; -- '0' = PRSG, '1' = COUNTER
g_frame_len : natural := 2; -- >= 2, test frame length in nof dat words
g_sof_period : natural := 1; -- >= 1, nof cycles between sop that start a frame, typically >> g_frame_len
- -- to generate frames with idle in between
+ -- to generate frames with idle in between
g_frame_cnt_w : natural := 32;
g_dat_w : natural := 16; -- >= 1, test data width
g_symbol_w : natural := 16; -- >= 1, and nof_symbols_per_dat = g_dat_w/g_symbol_w, must be an integer
@@ -93,17 +93,17 @@ begin
-- Signal begin of diag_en
u_diag_en_revt : entity common_lib.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_sig => diag_en,
- out_evt => diag_en_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_sig => diag_en,
+ out_evt => diag_en_revt
+ );
p_clk : process (rst, clk)
begin
@@ -121,62 +121,62 @@ begin
nxt_diag_init <= TO_UVEC(c_init, g_dat_w) when diag_en = '0' else INCR_UVEC(diag_init, 1) when i_out_sop = '1';
u_pulse_sop : entity common_lib.common_pulser
- generic map (
- g_pulse_period => g_sof_period
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- pulse_period => diag_sof_period,
- pulse_en => diag_en,
- pulse_clr => diag_en_revt,
- pulse_out => diag_sop
- );
+ generic map (
+ g_pulse_period => g_sof_period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ pulse_period => diag_sof_period,
+ pulse_en => diag_en,
+ pulse_clr => diag_en_revt,
+ pulse_out => diag_sop
+ );
-- Hold last frame count also when the generator is disabled, clear when it is restarted
nxt_diag_frame_cnt <= (others => '0') when diag_en_revt = '1' else frame_cnt;
u_frm_cnt : entity common_lib.common_counter
- generic map (
- g_width => g_frame_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => diag_en_revt,
- cnt_en => i_out_eop,
- count => frame_cnt
- );
+ generic map (
+ g_width => g_frame_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_en_revt,
+ cnt_en => i_out_eop,
+ count => frame_cnt
+ );
u_tx_frm : entity work.diag_tx_frm
- generic map (
- g_sel => g_sel,
- g_init => c_init,
- g_frame_len => g_frame_len,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
-
- -- Static control input (connect via MM or leave open to use default)
- diag_sel => diag_sel,
- diag_dc => diag_dc,
- diag_frame_len => diag_frame_len,
-
- -- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
- diag_ready => diag_ready,
- diag_init => diag_init,
- diag_sop => diag_sop,
-
- -- ST output
- out_ready => out_ready,
- out_dat => out_dat,
- out_val => out_val,
- out_sop => i_out_sop,
- out_eop => i_out_eop
- );
+ generic map (
+ g_sel => g_sel,
+ g_init => c_init,
+ g_frame_len => g_frame_len,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+
+ -- Static control input (connect via MM or leave open to use default)
+ diag_sel => diag_sel,
+ diag_dc => diag_dc,
+ diag_frame_len => diag_frame_len,
+
+ -- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
+ diag_ready => diag_ready,
+ diag_init => diag_init,
+ diag_sop => diag_sop,
+
+ -- ST output
+ out_ready => out_ready,
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sop => i_out_sop,
+ out_eop => i_out_eop
+ );
end str;
diff --git a/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd b/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
index 1993a75098..8c646ac2a2 100644
--- a/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
+++ b/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
@@ -21,25 +21,25 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
--- Purpose: Monitor a stream of frames with test sequence data.
--- Description:
--- Each frame is marked by an active in_eop. The in_sop is not needed and the
--- in_dat test data in the frame is ignored. The monitor does not need to
--- explicitly check the frame data, because it relies on the PHY level frame
--- error detection by e.g. and CRC check that was already done before this
--- monitor. This PHY level frame error information needs to be passed on to
--- the monitor via the in_error input.
--- The frame monitor is enabled by diag_en. When enabled the monitor is
--- always ready to receive frames.
--- Based on the in_eop it counts the number of received frames. Based on the
--- in_error signal that is valid during the in_eop it counts the number of
--- frames that have an error.
--- Remark:
--- . This component can be easily mapped to standard MM and ST interfaces.
+ -- Purpose: Monitor a stream of frames with test sequence data.
+ -- Description:
+ -- Each frame is marked by an active in_eop. The in_sop is not needed and the
+ -- in_dat test data in the frame is ignored. The monitor does not need to
+ -- explicitly check the frame data, because it relies on the PHY level frame
+ -- error detection by e.g. and CRC check that was already done before this
+ -- monitor. This PHY level frame error information needs to be passed on to
+ -- the monitor via the in_error input.
+ -- The frame monitor is enabled by diag_en. When enabled the monitor is
+ -- always ready to receive frames.
+ -- Based on the in_eop it counts the number of received frames. Based on the
+ -- in_error signal that is valid during the in_eop it counts the number of
+ -- frames that have an error.
+ -- Remark:
+ -- . This component can be easily mapped to standard MM and ST interfaces.
entity diag_frm_monitor is
generic (
@@ -87,17 +87,17 @@ begin
-- Signal begin of diag_en
u_diag_en_revt : entity common_lib.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_sig => diag_en,
- out_evt => diag_en_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_sig => diag_en,
+ out_evt => diag_en_revt
+ );
-- Hold last frame and error counts also when the monitor is disabled, clear when it is restarted
nxt_diag_frame_cnt <= (others => '0') when diag_en_revt = '1' else frame_cnt;
@@ -105,31 +105,31 @@ begin
-- Count all received frames
u_frm_cnt : entity common_lib.common_counter
- generic map (
- g_width => g_frame_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => diag_en_revt,
- cnt_en => in_eop,
- count => frame_cnt
- );
+ generic map (
+ g_width => g_frame_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_en_revt,
+ cnt_en => in_eop,
+ count => frame_cnt
+ );
-- Count the received frames that had an error
frm_error <= in_eop and in_error;
u_err_cnt : entity common_lib.common_counter
- generic map (
- g_width => g_frame_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => diag_en_revt,
- cnt_en => frm_error,
- count => error_cnt
- );
+ generic map (
+ g_width => g_frame_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_en_revt,
+ cnt_en => frm_error,
+ count => error_cnt
+ );
end str;
diff --git a/libraries/base/diag/src/vhdl/diag_pkg.vhd b/libraries/base/diag/src/vhdl/diag_pkg.vhd
index 8f88945551..2321d82955 100644
--- a/libraries/base/diag/src/vhdl/diag_pkg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_pkg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
package diag_pkg is
-----------------------------------------------------------------------------
@@ -59,7 +59,7 @@ package diag_pkg is
constant c_diag_wg_phase_w : natural := 16; -- = c_diag_wg_nofsamples_w
constant c_diag_wg_freq_w : natural := 31; -- >> c_diag_wg_nofsamples_w, determines the minimum frequency = Fs / 2**c_diag_wg_freq_w
constant c_diag_wg_ampl_w : natural := 17; -- Typically fit DSP multiply 18x18 element so use <= 17, to fit unsigned in 18 bit signed,
- -- = waveform data width-1 (sign bit) to be able to make a 1 LSBit amplitude sinus
+ -- = waveform data width-1 (sign bit) to be able to make a 1 LSBit amplitude sinus
constant c_diag_wg_mode_off : natural := 0;
constant c_diag_wg_mode_calc : natural := 1;
@@ -75,23 +75,24 @@ package diag_pkg is
end record;
constant c_diag_wg_ampl_norm : real := 1.0; -- Use this default amplitude norm = 1.0 when WG data width = WG waveform buffer data width,
- -- else use extra amplitude unit scaling by (WG data max)/(WG data max + 1)
+ -- else use extra amplitude unit scaling by (WG data max)/(WG data max + 1)
constant c_diag_wg_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
- -- . use gain 2**0 = 1 to have fulle scale without clipping
- -- . use gain 2**g_calc_gain_w > 1 to cause clipping
- -- For c_diag_wg_gain_w = 1 there is clipping from [1 2> For normalized values >= 2**c_diag_wg_gain_w = 2
- -- the behaviour becomes more or less undefined. Due to wrapping it appears that normalized values [2 3>
- -- result in a sinus again. Therefore use normalized range [0 2**c_diag_wg_gain_w>.
+ -- . use gain 2**0 = 1 to have fulle scale without clipping
+ -- . use gain 2**g_calc_gain_w > 1 to cause clipping
+ -- For c_diag_wg_gain_w = 1 there is clipping from [1 2> For normalized values >= 2**c_diag_wg_gain_w = 2
+ -- the behaviour becomes more or less undefined. Due to wrapping it appears that normalized values [2 3>
+ -- result in a sinus again. Therefore use normalized range [0 2**c_diag_wg_gain_w>.
constant c_diag_wg_ampl_unit : real := 2**REAL(c_diag_wg_ampl_w - c_diag_wg_gain_w) * c_diag_wg_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
constant c_diag_wg_freq_unit : real := 2**REAL(c_diag_wg_freq_w); -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
constant c_diag_wg_phase_unit : real := 2**REAL(c_diag_wg_phase_w) / 360.0; -- ^= 1 degree
constant c_diag_wg_latency : natural := 10; -- WG starts 10 cycles after trigger
- constant c_diag_wg_rst : t_diag_wg := (TO_UVEC(c_diag_wg_mode_off, c_diag_wg_mode_w),
- TO_UVEC( 1024, c_diag_wg_nofsamples_w),
- TO_UVEC( 0, c_diag_wg_phase_w),
- TO_UVEC( 0, c_diag_wg_freq_w),
- TO_UVEC( 0, c_diag_wg_ampl_w));
+ constant c_diag_wg_rst : t_diag_wg := (
+ TO_UVEC(c_diag_wg_mode_off, c_diag_wg_mode_w),
+ TO_UVEC( 1024, c_diag_wg_nofsamples_w),
+ TO_UVEC( 0, c_diag_wg_phase_w),
+ TO_UVEC( 0, c_diag_wg_freq_w),
+ TO_UVEC( 0, c_diag_wg_ampl_w));
type t_diag_wg_arr is array (integer range <>) of t_diag_wg;
@@ -139,23 +140,25 @@ package diag_pkg is
bsn_init : natural;
end record;
- constant c_diag_block_gen_rst : t_diag_block_gen := ( '0',
- '0',
- TO_UVEC( 256, c_diag_bg_samples_per_packet_w),
- TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( 128, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( 1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
-
- constant c_diag_block_gen_enabled : t_diag_block_gen := ( '1',
- '0',
- TO_UVEC( 50, c_diag_bg_samples_per_packet_w),
- TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( 7, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( 15, c_diag_bg_mem_high_adrs_w), -- fits any BG buffer that has address width >= 4
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_diag_block_gen_rst : t_diag_block_gen := (
+ '0',
+ '0',
+ TO_UVEC( 256, c_diag_bg_samples_per_packet_w),
+ TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( 128, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( 1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
+
+ constant c_diag_block_gen_enabled : t_diag_block_gen := (
+ '1',
+ '0',
+ TO_UVEC( 50, c_diag_bg_samples_per_packet_w),
+ TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( 7, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( 15, c_diag_bg_mem_high_adrs_w), -- fits any BG buffer that has address width >= 4
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
type t_diag_block_gen_arr is array (integer range <>) of t_diag_block_gen;
type t_diag_block_gen_integer_arr is array (integer range <>) of t_diag_block_gen_integer;
@@ -235,25 +238,25 @@ package body diag_pkg is
function func_diag_bg_ctrl_integer_to_slv(bg_ctrl_int : t_diag_block_gen_integer) return t_diag_block_gen is
begin
return ( bg_ctrl_int.enable,
- bg_ctrl_int.enable_sync,
- TO_UVEC(bg_ctrl_int.samples_per_packet, c_diag_bg_samples_per_packet_w),
- TO_UVEC(bg_ctrl_int.blocks_per_sync , c_diag_bg_blocks_per_sync_w),
- TO_UVEC(bg_ctrl_int.gapsize , c_diag_bg_gapsize_w),
- TO_UVEC(bg_ctrl_int.mem_low_adrs , c_diag_bg_mem_low_adrs_w),
- TO_UVEC(bg_ctrl_int.mem_high_adrs , c_diag_bg_mem_high_adrs_w),
- TO_UVEC(bg_ctrl_int.bsn_init , c_diag_bg_bsn_init_w));
+ bg_ctrl_int.enable_sync,
+ TO_UVEC(bg_ctrl_int.samples_per_packet, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(bg_ctrl_int.blocks_per_sync , c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(bg_ctrl_int.gapsize , c_diag_bg_gapsize_w),
+ TO_UVEC(bg_ctrl_int.mem_low_adrs , c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(bg_ctrl_int.mem_high_adrs , c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(bg_ctrl_int.bsn_init , c_diag_bg_bsn_init_w));
end;
function func_diag_bg_ctrl_slv_to_integer(bg_ctrl_slv : t_diag_block_gen) return t_diag_block_gen_integer is
begin
return ( bg_ctrl_slv.enable,
- bg_ctrl_slv.enable_sync,
- TO_UINT(bg_ctrl_slv.samples_per_packet),
- TO_UINT(bg_ctrl_slv.blocks_per_sync),
- TO_UINT(bg_ctrl_slv.gapsize),
- TO_UINT(bg_ctrl_slv.mem_low_adrs),
- TO_UINT(bg_ctrl_slv.mem_high_adrs),
- TO_UINT(bg_ctrl_slv.bsn_init));
+ bg_ctrl_slv.enable_sync,
+ TO_UINT(bg_ctrl_slv.samples_per_packet),
+ TO_UINT(bg_ctrl_slv.blocks_per_sync),
+ TO_UINT(bg_ctrl_slv.gapsize),
+ TO_UINT(bg_ctrl_slv.mem_low_adrs),
+ TO_UINT(bg_ctrl_slv.mem_high_adrs),
+ TO_UINT(bg_ctrl_slv.bsn_init));
end;
end diag_pkg;
diff --git a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
index 4bf373e254..c5b797b9d7 100644
--- a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
@@ -90,11 +90,11 @@
-- in case they occur.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use work.diag_pkg.all;
entity diag_rx_seq is
generic (
@@ -212,19 +212,19 @@ begin
-- Use initialisation to set initial diag_res to invalid
diag_res <= diag_res_int; -- use initialisation of internal signal diag_res_int rather than initialisation of entity output diag_res
--- -- Use rst to set initial diag_res to invalid
--- p_rst_clk : PROCESS (rst, clk)
--- BEGIN
--- IF rst='1' THEN
--- diag_res <= c_diag_res_invalid;
--- ELSIF rising_edge(clk) THEN
--- IF clken='1' THEN
--- -- Internal.
--- diag_res <= nxt_diag_res;
--- -- Outputs.
--- END IF;
--- END IF;
--- END PROCESS;
+ -- -- Use rst to set initial diag_res to invalid
+ -- p_rst_clk : PROCESS (rst, clk)
+ -- BEGIN
+ -- IF rst='1' THEN
+ -- diag_res <= c_diag_res_invalid;
+ -- ELSIF rising_edge(clk) THEN
+ -- IF clken='1' THEN
+ -- -- Internal.
+ -- diag_res <= nxt_diag_res;
+ -- -- Outputs.
+ -- END IF;
+ -- END IF;
+ -- END PROCESS;
p_clk : process (clk)
begin
@@ -269,24 +269,24 @@ begin
------------------------------------------------------------------------------
u_in_val_1 : entity common_lib.common_switch
- port map(
- clk => clk,
- rst => rst,
- switch_high => in_val_reg,
- switch_low => diag_dis,
- out_level => in_val_1 -- first in_val has been detected, but this one was used as seed for common_lfsr_nxt_seq
- );
+ port map(
+ clk => clk,
+ rst => rst,
+ switch_high => in_val_reg,
+ switch_low => diag_dis,
+ out_level => in_val_1 -- first in_val has been detected, but this one was used as seed for common_lfsr_nxt_seq
+ );
in_val_act <= in_val_1 and in_val_reg; -- Signal the second valid in_dat after diag_en='1'
u_in_val_2 : entity common_lib.common_switch
- port map(
- clk => clk,
- rst => rst,
- switch_high => in_val_act,
- switch_low => diag_dis,
- out_level => in_val_2 -- second in_val has been detected, representing a true next sequence value
- );
+ port map(
+ clk => clk,
+ rst => rst,
+ switch_high => in_val_act,
+ switch_low => diag_dis,
+ out_level => in_val_2 -- second in_val has been detected, representing a true next sequence value
+ );
-- Use in_val_2_act instead of in_val_2 to have stable start in case diag_dis takes just a pulse and in_val is continue high
in_val_2_act <= vector_and(in_val_2 & in_val_2_dly);
@@ -300,14 +300,14 @@ begin
no_steps : if g_use_steps = false generate
-- Determine next reference dat based on current input dat
common_lfsr_nxt_seq(c_lfsr_nr, -- IN
- g_cnt_incr, -- IN
- ref_en, -- IN
- in_val_reg, -- IN, use in_val_reg to allow gaps in the input data valid stream
- in_dat_reg, -- IN, used only to init nxt_prsg and nxt_cntr when ref_en='0'
- prsg, -- IN
- cntr, -- IN
- nxt_prsg, -- OUT
- nxt_cntr); -- OUT
+ g_cnt_incr, -- IN
+ ref_en, -- IN
+ in_val_reg, -- IN, use in_val_reg to allow gaps in the input data valid stream
+ in_dat_reg, -- IN, used only to init nxt_prsg and nxt_cntr when ref_en='0'
+ prsg, -- IN
+ cntr, -- IN
+ nxt_prsg, -- OUT
+ nxt_cntr); -- OUT
nxt_ref_dat <= prsg when diag_sel = '0' else cntr;
@@ -335,13 +335,13 @@ begin
-- Hold any difference on the in_dat bus lines
u_dat : entity common_lib.common_switch
- port map(
- clk => clk,
- rst => rst,
- switch_high => diff_dat(I),
- switch_low => diff_dis,
- out_level => diff_res(I)
- );
+ port map(
+ clk => clk,
+ rst => rst,
+ switch_high => diff_dat(I),
+ switch_low => diff_dis,
+ out_level => diff_res(I)
+ );
end generate;
end generate;
@@ -385,13 +385,13 @@ begin
-- hold detected diff detect
u_dat : entity common_lib.common_switch
- port map(
- clk => clk,
- rst => rst,
- switch_high => diff_detect,
- switch_low => diff_dis,
- out_level => diff_hold
- );
+ port map(
+ clk => clk,
+ rst => rst,
+ switch_high => diff_detect,
+ switch_low => diff_dis,
+ out_level => diff_hold
+ );
diff_res <= (others => diff_hold); -- convert diff_hold to diff_res slv format as used for g_use_steps=FALSE
end generate;
@@ -417,16 +417,16 @@ begin
-- Count number of valid input data
------------------------------------------------------------------------------
u_common_counter : entity common_lib.common_counter
- generic map (
- g_latency => 1, -- default 1 for registered count output, use 0 for immediate combinatorial count output
- g_width => g_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
- cnt_en => in_val,
- count => in_cnt
- );
+ generic map (
+ g_latency => 1, -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ g_width => g_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
+ cnt_en => in_val,
+ count => in_cnt
+ );
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_tx_frm.vhd b/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
index 0f392a8179..d519d06ef2 100644
--- a/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
+++ b/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
@@ -21,27 +21,27 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-
--- Purpose: Transmit a frame with PRSG or COUNTER test sequence data.
--- Description:
--- The test data can be PRSG or COUNTER dependent on diag_sel.
--- A frame generation is enabled (started) by diag_sop. It does not need
--- diag_eop to end the frame generation, because the generator ends itself
--- when it has generated g_frame_len words of out_dat.
--- After a test frame has finished then diag_ready with RL=0 is active to
--- indicate that a new diag_sof can be handled. The next frame will then
--- immediatly follow the previous frame, so out_sop of new frame direct after
--- out_eop of previous frame, if allowed by out_ready from the sink.
--- It is allowed to keep diag_sop continue high or to make diag_sop =
--- diag_ready, both will result in maximum frame rate.
--- The out_ready acts as a data request. During a frame the out_dat is valid
--- for every active out_ready, to support streaming flow control.
--- Remark:
--- . This component can be easily mapped to standard MM and ST interfaces.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+
+ -- Purpose: Transmit a frame with PRSG or COUNTER test sequence data.
+ -- Description:
+ -- The test data can be PRSG or COUNTER dependent on diag_sel.
+ -- A frame generation is enabled (started) by diag_sop. It does not need
+ -- diag_eop to end the frame generation, because the generator ends itself
+ -- when it has generated g_frame_len words of out_dat.
+ -- After a test frame has finished then diag_ready with RL=0 is active to
+ -- indicate that a new diag_sof can be handled. The next frame will then
+ -- immediatly follow the previous frame, so out_sop of new frame direct after
+ -- out_eop of previous frame, if allowed by out_ready from the sink.
+ -- It is allowed to keep diag_sop continue high or to make diag_sop =
+ -- diag_ready, both will result in maximum frame rate.
+ -- The out_ready acts as a data request. During a frame the out_dat is valid
+ -- for every active out_ready, to support streaming flow control.
+ -- Remark:
+ -- . This component can be easily mapped to standard MM and ST interfaces.
entity diag_tx_frm is
generic (
@@ -137,32 +137,32 @@ begin
nxt_out_eop <= cnt_done;
u_cnt_len : entity common_lib.common_counter
- generic map (
- g_width => diag_frame_len'length
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => diag_frame_len'length
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
u_frame_dat : entity work.diag_tx_seq
- generic map (
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- diag_en => diag_en,
- diag_sel => diag_sel,
- diag_dc => diag_dc,
- diag_init => diag_init,
- diag_req => out_ready,
- out_dat => out_dat,
- out_val => open
- );
+ generic map (
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ diag_en => diag_en,
+ diag_sel => diag_sel,
+ diag_dc => diag_dc,
+ diag_init => diag_init,
+ diag_req => out_ready,
+ out_dat => out_dat,
+ out_val => open
+ );
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
index 6b00fcfb0d..d044d9b815 100644
--- a/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
@@ -21,24 +21,24 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
--- Purpose: Transmit continuous PRSG or COUNTER test sequence data.
--- Description:
--- The Tx test data can sequence data or constant value data dependent on
--- diag_dc.
--- The Tx test sequence data can be PRSG or COUNTER dependent on diag_sel.
--- The Tx is enabled by diag_en. When the Tx is disabled then the sequence
--- data gets initialised with diag_init.
--- The out_ready acts as a data request. When the generator is enabled then
--- output is valid for every active out_ready, to support streaming flow
--- control. With g_latency=1 the out_val is active one cycle after diag_req,
--- by using g_latency=0 outval is active in the same cycle as diag_req.
--- Use diag_mod=0 for default binary wrap at 2**g_dat_w. For diag_rx_seq
--- choose diag_step = 2**g_seq_dat_w - diag_mod + g_cnt_incr to verify ok.
+ -- Purpose: Transmit continuous PRSG or COUNTER test sequence data.
+ -- Description:
+ -- The Tx test data can sequence data or constant value data dependent on
+ -- diag_dc.
+ -- The Tx test sequence data can be PRSG or COUNTER dependent on diag_sel.
+ -- The Tx is enabled by diag_en. When the Tx is disabled then the sequence
+ -- data gets initialised with diag_init.
+ -- The out_ready acts as a data request. When the generator is enabled then
+ -- output is valid for every active out_ready, to support streaming flow
+ -- control. With g_latency=1 the out_val is active one cycle after diag_req,
+ -- by using g_latency=0 outval is active in the same cycle as diag_req.
+ -- Use diag_mod=0 for default binary wrap at 2**g_dat_w. For diag_rx_seq
+ -- choose diag_step = 2**g_seq_dat_w - diag_mod + g_cnt_incr to verify ok.
entity diag_tx_seq is
generic (
@@ -117,14 +117,14 @@ begin
end generate;
common_lfsr_nxt_seq(c_lfsr_nr, -- IN
- g_cnt_incr, -- IN
- diag_en, -- IN
- diag_req, -- IN
- diag_init, -- IN
- prsg, -- IN
- cntr, -- IN
- nxt_prsg, -- OUT
- next_cntr); -- OUT
+ g_cnt_incr, -- IN
+ diag_en, -- IN
+ diag_req, -- IN
+ diag_init, -- IN
+ prsg, -- IN
+ cntr, -- IN
+ nxt_prsg, -- OUT
+ next_cntr); -- OUT
nxt_cntr <= next_cntr when unsigned(next_cntr) < unsigned(diag_mod) else SUB_UVEC(next_cntr, diag_mod);
@@ -133,16 +133,16 @@ begin
-- Count number of valid output data
u_common_counter : entity common_lib.common_counter
- generic map (
- g_latency => g_latency, -- default 1 for registered count output, use 0 for immediate combinatorial count output
- g_width => g_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
- cnt_en => nxt_out_val,
- count => out_cnt
- );
+ generic map (
+ g_latency => g_latency, -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ g_width => g_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
+ cnt_en => nxt_out_val,
+ count => out_cnt
+ );
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_wg.vhd b/libraries/base/diag/src/vhdl/diag_wg.vhd
index 93592adee8..7af56d5834 100644
--- a/libraries/base/diag/src/vhdl/diag_wg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg.vhd
@@ -46,25 +46,25 @@
-- CW with fractional frequency is SNR ~= 56 dB, even if g_calc_dat_w > 9.
library IEEE, common_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity diag_wg is
generic (
g_technology : natural := c_tech_select_default;
g_buf_dat_w : natural := 18; -- Use >= g_calc_dat_w and typically <= DSP multiply 18x18 element
g_buf_addr_w : natural := 11; -- Waveform buffer size 2**g_buf_addr_w nof samples
- -- . in calc mode fill the entire buffer with one sinus wave, ctrl.phase and ctrl.freq will map on the entire range
- -- . in single or repeat mode fill the buffer with an arbitrary signal and define actual the period via ctrl.nof_samples
+ -- . in calc mode fill the entire buffer with one sinus wave, ctrl.phase and ctrl.freq will map on the entire range
+ -- . in single or repeat mode fill the buffer with an arbitrary signal and define actual the period via ctrl.nof_samples
g_rate_factor : natural := 1; -- Default 1 for unit frequency Fs, else g_rate_factor * Fs using g_rate_factor nof parallel outputs
g_rate_offset : natural := 0; -- Selects which of the parallel outputs [0:g_rate_factor-1] this WG should generate
g_calc_support : boolean := true; -- When FALSE then calc mode falls back to repeat mode to save logic.
g_calc_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
- -- . use gain 2**0 = 1 to have full scale without clipping
- -- . use gain 2**g_calc_gain_w > 1 to cause clipping
+ -- . use gain 2**0 = 1 to have full scale without clipping
+ -- . use gain 2**g_calc_gain_w > 1 to cause clipping
g_calc_dat_w : natural := 12 -- Effective range of the WG out_dat
);
port (
@@ -227,15 +227,15 @@ begin
when c_diag_wg_mode_single => if init_repeat_done = '1' then nxt_state <= s_single; nxt_init_sync <= '1'; end if;
when c_diag_wg_mode_repeat => if init_repeat_done = '1' then nxt_state <= s_repeat; nxt_init_sync <= '1'; end if;
when c_diag_wg_mode_calc => if g_calc_support = false and init_repeat_done = '1' then nxt_state <= s_repeat; nxt_init_sync <= '1'; end if;
- if g_calc_support = true and init_calc_done = '1' then nxt_state <= s_calc; nxt_init_sync <= '1'; end if;
+ if g_calc_support = true and init_calc_done = '1' then nxt_state <= s_calc; nxt_init_sync <= '1'; end if;
when others => nxt_state <= s_off;
end case;
- when s_single =>
+ when s_single =>
if sample_cnt + sample_step >= unsigned(nof_samples) then
nxt_state <= s_off;
end if;
- when others => null; -- continue in state
- end case;
+ when others => null; -- continue in state
+ end case;
end if;
end process;
@@ -346,98 +346,98 @@ begin
end process;
mult : entity common_mult_lib.common_mult
- generic map (
- g_technology => g_technology,
- g_variant => "RTL",
- g_in_a_w => g_buf_dat_w,
- g_in_b_w => c_ampl_w,
- g_out_p_w => c_mult_w,
- g_pipeline_input => c_mult_pipeline_input,
- g_pipeline_product => c_mult_pipeline_product,
- g_pipeline_output => c_mult_pipeline_output
- )
- port map (
- rst => rst,
- clk => clk,
- in_a => buf_rddat,
- in_b => ctrl_ampl,
- out_p => mult_dat
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "RTL",
+ g_in_a_w => g_buf_dat_w,
+ g_in_b_w => c_ampl_w,
+ g_out_p_w => c_mult_w,
+ g_pipeline_input => c_mult_pipeline_input,
+ g_pipeline_product => c_mult_pipeline_product,
+ g_pipeline_output => c_mult_pipeline_output
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_a => buf_rddat,
+ in_b => ctrl_ampl,
+ out_p => mult_dat
+ );
-- Skip the double-sign bit
prod_dat <= mult_dat(c_prod_w - 1 downto 0);
u_round : entity common_lib.common_round
- generic map(
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => true,
- g_pipeline_input => 0,
- g_pipeline_output => c_round_pipeline,
- g_in_dat_w => c_prod_w,
- g_out_dat_w => c_round_w
- )
- port map (
- clk => clk,
- in_dat => prod_dat,
- out_dat => round_dat
- );
+ generic map(
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_pipeline_input => 0,
+ g_pipeline_output => c_round_pipeline,
+ g_in_dat_w => c_prod_w,
+ g_out_dat_w => c_round_w
+ )
+ port map (
+ clk => clk,
+ in_dat => prod_dat,
+ out_dat => round_dat
+ );
u_clip : entity common_lib.common_clip
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_clip_pipeline,
- g_full_scale => to_unsigned(c_calc_full_scale, g_calc_dat_w)
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => round_dat,
- out_dat => clip_dat,
- out_ovr => clip_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_clip_pipeline,
+ g_full_scale => to_unsigned(c_calc_full_scale, g_calc_dat_w)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => round_dat,
+ out_dat => clip_dat,
+ out_ovr => clip_ovr
+ );
u_rdval_delay : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_calc_pipeline,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- in_clr => idle,
- in_dat => slv(buf_rdval),
- sl(out_dat) => buf_rdval_dly
- );
+ generic map (
+ g_pipeline => c_calc_pipeline,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_clr => idle,
+ in_dat => slv(buf_rdval),
+ sl(out_dat) => buf_rdval_dly
+ );
u_sync_default_delay : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_sync_dly,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- in_clr => idle,
- in_dat => slv(init_sync),
- sl(out_dat) => sync_dly_default
- );
+ generic map (
+ g_pipeline => c_sync_dly,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_clr => idle,
+ in_dat => slv(init_sync),
+ sl(out_dat) => sync_dly_default
+ );
u_sync_calc_delay : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_calc_pipeline,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- in_clr => idle,
- in_dat => slv(sync_dly_default),
- sl(out_dat) => sync_dly_calc
- );
+ generic map (
+ g_pipeline => c_calc_pipeline,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_clr => idle,
+ in_dat => slv(sync_dly_default),
+ sl(out_dat) => sync_dly_calc
+ );
output_proc : process(state, buf_rdval_dly, clip_dat, clip_ovr, buf_rdval, buf_rddat, sync_dly_default, sync_dly_calc)
begin
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
index bb2657dbd8..1980ccaf89 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
@@ -25,12 +25,12 @@
-- . For g_wideband_factor=1 this diag_wg_wideband defaults to diag_wg.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity diag_wg_wideband is
generic (
@@ -76,14 +76,16 @@ entity diag_wg_wideband is
end diag_wg_wideband;
architecture str of diag_wg_wideband is
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => g_buf_addr_w,
- dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
- nof_dat => 2**g_buf_addr_w, -- = 2**adr_w
- init_sl => '0');
- constant c_buf_file : string := sel_a_b(c_buf.adr_w = 11 and c_buf.dat_w = 18, g_buf_dir & "diag_sin_2048x18.hex",
- sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, g_buf_dir & "diag_sin_1024x18.hex",
- sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 8, g_buf_dir & "diag_sin_1024x8.hex", "UNUSED")));
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => g_buf_addr_w,
+ dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
+ nof_dat => 2**g_buf_addr_w, -- = 2**adr_w
+ init_sl => '0');
+ constant c_buf_file : string := sel_a_b(
+ c_buf.adr_w = 11 and c_buf.dat_w = 18, g_buf_dir & "diag_sin_2048x18.hex",
+ sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, g_buf_dir & "diag_sin_1024x18.hex",
+ sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 8, g_buf_dir & "diag_sin_1024x8.hex", "UNUSED")));
type t_buf_dat_arr is array (natural range <>) of std_logic_vector(g_buf_dat_w - 1 downto 0);
type t_buf_adr_arr is array (natural range <>) of std_logic_vector(g_buf_addr_w - 1 downto 0);
@@ -111,60 +113,60 @@ begin
gen_wg : for I in 0 to g_wideband_factor - 1 generate
-- Waveform buffer
u_buf : entity common_lib.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => c_buf,
- g_init_file => c_buf_file
- )
- port map (
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_dat_a => mm_wrdata,
- adr_a => mm_address,
- wr_en_a => mm_wr,
- rd_en_a => mm_rd,
- rd_val_a => buf_rdval(I),
- rd_dat_a => buf_rddata(I),
- rst_b => st_rst,
- clk_b => st_clk,
- wr_dat_b => (others => '0'),
- adr_b => st_address(I),
- wr_en_b => '0',
- rd_en_b => st_rd(I),
- rd_val_b => st_rdval(I),
- rd_dat_b => st_rddata(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_buf,
+ g_init_file => c_buf_file
+ )
+ port map (
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_dat_a => mm_wrdata,
+ adr_a => mm_address,
+ wr_en_a => mm_wr,
+ rd_en_a => mm_rd,
+ rd_val_a => buf_rdval(I),
+ rd_dat_a => buf_rddata(I),
+ rst_b => st_rst,
+ clk_b => st_clk,
+ wr_dat_b => (others => '0'),
+ adr_b => st_address(I),
+ wr_en_b => '0',
+ rd_en_b => st_rd(I),
+ rd_val_b => st_rdval(I),
+ rd_dat_b => st_rddata(I)
+ );
-- Waveform generator
u_wg : entity work.diag_wg
- generic map (
- g_technology => g_technology,
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w,
- g_rate_factor => g_wideband_factor,
- g_rate_offset => I,
- g_calc_support => g_calc_support,
- g_calc_gain_w => g_calc_gain_w,
- g_calc_dat_w => g_calc_dat_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- restart => st_restart,
-
- buf_rddat => st_rddata(I),
- buf_rdval => st_rdval(I),
- buf_addr => st_address(I),
- buf_rden => st_rd(I),
-
- ctrl => st_ctrl,
- mon_ctrl => st_mon_ctrl_arr(I),
-
- out_ovr => out_ovr( g_wideband_factor - I - 1),
- out_dat => out_dat((g_wideband_factor - I) * g_buf_dat_w - 1 downto (g_wideband_factor - I - 1) * g_buf_dat_w),
- out_val => out_val( g_wideband_factor - I - 1),
- out_sync => out_sync( g_wideband_factor - I - 1)
- );
+ generic map (
+ g_technology => g_technology,
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w,
+ g_rate_factor => g_wideband_factor,
+ g_rate_offset => I,
+ g_calc_support => g_calc_support,
+ g_calc_gain_w => g_calc_gain_w,
+ g_calc_dat_w => g_calc_dat_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ restart => st_restart,
+
+ buf_rddat => st_rddata(I),
+ buf_rdval => st_rdval(I),
+ buf_addr => st_address(I),
+ buf_rden => st_rd(I),
+
+ ctrl => st_ctrl,
+ mon_ctrl => st_mon_ctrl_arr(I),
+
+ out_ovr => out_ovr( g_wideband_factor - I - 1),
+ out_dat => out_dat((g_wideband_factor - I) * g_buf_dat_w - 1 downto (g_wideband_factor - I - 1) * g_buf_dat_w),
+ out_val => out_val( g_wideband_factor - I - 1),
+ out_sync => out_sync( g_wideband_factor - I - 1)
+ );
end generate;
end str;
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
index b0d7b45dc6..bfb5573380 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
@@ -41,10 +41,10 @@
-- diag_wg_reg.vhd.
library IEEE, common_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use diag_lib.diag_pkg.all;
entity diag_wg_wideband_reg is
generic (
@@ -69,11 +69,12 @@ end diag_wg_wideband_reg;
architecture rtl of diag_wg_wideband_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2**2,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 2,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2**2,
+ init_sl => '0');
-- Registers in mm_clk domain
signal mm_wg_ctrl : t_diag_wg;
@@ -122,7 +123,7 @@ begin
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -181,17 +182,17 @@ begin
-- Assume diag WG mode gets written last, so when diag WG mode is transfered properly to the st_clk domain, then
-- the other diag WG control fields are stable as well
u_mode : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_wg_ctrl_mode_wr, -- when '1' then new in_dat is available after g_in_new_latency
- in_dat => mm_wg_ctrl.mode,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_wg_ctrl.mode,
- out_new => open -- when '1' then the out_dat was updated with in_dat due to in_new
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_wg_ctrl_mode_wr, -- when '1' then new in_dat is available after g_in_new_latency
+ in_dat => mm_wg_ctrl.mode,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_wg_ctrl.mode,
+ out_new => open -- when '1' then the out_dat was updated with in_dat due to in_new
+ );
end generate;
-- The other wg_ctrl only take effect in diag_wg after the mode has been set
@@ -203,54 +204,54 @@ begin
-- Read: ST to MM clock domain
gen_cross_rd : if g_cross_clock_domain = true generate
u_mode : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.mode,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.mode
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.mode,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.mode
+ );
u_nof_samples : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.nof_samples,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.nof_samples
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.nof_samples,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.nof_samples
+ );
u_freq : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.freq,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.freq
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.freq,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.freq
+ );
u_phase : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.phase,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.phase
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.phase,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.phase
+ );
u_ampl : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.ampl,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.ampl
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.ampl,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.ampl
+ );
end generate;
end rtl;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
index 60095ffc8c..5cbb474e06 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
@@ -93,13 +93,13 @@
-- . A nice new feature would be to support a BG burst of N blocks.
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_block_gen is
generic (
@@ -148,11 +148,12 @@ entity mms_diag_block_gen is
end mms_diag_block_gen;
architecture rtl of mms_diag_block_gen is
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => g_buf_addr_w,
- dat_w => g_buf_dat_w,
- nof_dat => 2**g_buf_addr_w,
- init_sl => '0');
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => g_buf_addr_w,
+ dat_w => g_buf_dat_w,
+ nof_dat => 2**g_buf_addr_w,
+ init_sl => '0');
constant c_post_buf_file : string := ".hex";
@@ -201,32 +202,32 @@ begin
mux_ctrl <= 0 when bg_ctrl.enable = '0' else 1;
u_bg_ctrl : entity work.diag_block_gen_reg
- generic map(
- g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_diag_block_gen_rst => g_diag_block_gen_rst
- )
- port map (
- mm_rst => mm_rst, -- Clocks and reset
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_mosi => reg_bg_ctrl_mosi,
- mm_miso => reg_bg_ctrl_miso,
- bg_ctrl => bg_ctrl
- );
+ generic map(
+ g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_diag_block_gen_rst => g_diag_block_gen_rst
+ )
+ port map (
+ mm_rst => mm_rst, -- Clocks and reset
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_mosi => reg_bg_ctrl_mosi,
+ mm_miso => reg_bg_ctrl_miso,
+ bg_ctrl => bg_ctrl
+ );
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
u_mem_mux_bg_data : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => g_buf_addr_w
- )
- port map (
- mosi => ram_bg_data_mosi,
- miso => ram_bg_data_miso,
- mosi_arr => ram_bg_data_mosi_arr,
- miso_arr => ram_bg_data_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => g_buf_addr_w
+ )
+ port map (
+ mosi => ram_bg_data_mosi,
+ miso => ram_bg_data_miso,
+ mosi_arr => ram_bg_data_mosi_arr,
+ miso_arr => ram_bg_data_miso_arr
+ );
gen_streams : for I in 0 to g_nof_streams - 1 generate
no_buffer_ram : if g_use_bg_buffer_ram = false generate
@@ -239,53 +240,53 @@ begin
gen_buffer_ram : if g_use_bg_buffer_ram = true generate
u_buffer_ram : entity common_lib.common_ram_crw_crw
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_buf,
+ -- Sequence number and ".hex" extension are added to the relative path in case a ram file is provided.
+ g_init_file => sel_a_b(g_file_name_prefix = "UNUSED", g_file_name_prefix, g_file_name_prefix & "_" & natural'image(g_file_index_arr(I)) & c_post_buf_file)
+ )
+ port map (
+ -- MM side
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_bg_data_mosi_arr(I).wr,
+ wr_dat_a => ram_bg_data_mosi_arr(I).wrdata(c_buf.dat_w - 1 downto 0),
+ adr_a => ram_bg_data_mosi_arr(I).address(c_buf.adr_w - 1 downto 0),
+ rd_en_a => ram_bg_data_mosi_arr(I).rd,
+ rd_dat_a => ram_bg_data_miso_arr(I).rddata(c_buf.dat_w - 1 downto 0),
+ rd_val_a => ram_bg_data_miso_arr(I).rdval,
+ -- Waveform side
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ adr_b => st_addr_arr(I),
+ rd_en_b => st_rd_arr(I),
+ rd_dat_b => st_rddata_arr(I),
+ rd_val_b => st_rdval_arr(I)
+ );
+ end generate;
+
+ u_diag_block_gen : entity work.diag_block_gen
generic map (
- g_technology => g_technology,
- g_ram => c_buf,
- -- Sequence number and ".hex" extension are added to the relative path in case a ram file is provided.
- g_init_file => sel_a_b(g_file_name_prefix = "UNUSED", g_file_name_prefix, g_file_name_prefix & "_" & natural'image(g_file_index_arr(I)) & c_post_buf_file)
+ g_blk_sync => g_blk_sync,
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w
)
port map (
- -- MM side
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_bg_data_mosi_arr(I).wr,
- wr_dat_a => ram_bg_data_mosi_arr(I).wrdata(c_buf.dat_w - 1 downto 0),
- adr_a => ram_bg_data_mosi_arr(I).address(c_buf.adr_w - 1 downto 0),
- rd_en_a => ram_bg_data_mosi_arr(I).rd,
- rd_dat_a => ram_bg_data_miso_arr(I).rddata(c_buf.dat_w - 1 downto 0),
- rd_val_a => ram_bg_data_miso_arr(I).rdval,
- -- Waveform side
- rst_b => dp_rst,
- clk_b => dp_clk,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- adr_b => st_addr_arr(I),
- rd_en_b => st_rd_arr(I),
- rd_dat_b => st_rddata_arr(I),
- rd_val_b => st_rdval_arr(I)
+ rst => dp_rst,
+ clk => dp_clk,
+ buf_addr => st_addr_arr(I),
+ buf_rden => st_rd_arr(I),
+ buf_rddat => st_rddata_arr(I),
+ buf_rdval => st_rdval_arr(I),
+ ctrl => bg_ctrl, -- same BG control for all streams
+ ctrl_hold => bg_ctrl_hold_arr(I), -- active BG control can differ in time per stream
+ en_sync => en_sync,
+ out_siso => bg_src_in_arr(I),
+ out_sosi => bg_src_out_arr(I)
);
- end generate;
-
- u_diag_block_gen : entity work.diag_block_gen
- generic map (
- g_blk_sync => g_blk_sync,
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- buf_addr => st_addr_arr(I),
- buf_rden => st_rd_arr(I),
- buf_rddat => st_rddata_arr(I),
- buf_rdval => st_rdval_arr(I),
- ctrl => bg_ctrl, -- same BG control for all streams
- ctrl_hold => bg_ctrl_hold_arr(I), -- active BG control can differ in time per stream
- en_sync => en_sync,
- out_siso => bg_src_in_arr(I),
- out_sosi => bg_src_out_arr(I)
- );
end generate;
end generate;
@@ -300,7 +301,7 @@ begin
-- User input only, BG only or no input
mux_src_out_arr <= usr_sosi_arr when g_use_usr_input = true else
bg_src_out_arr when g_use_bg = true else
- (others => c_dp_sosi_rst);
+ (others => c_dp_sosi_rst);
end generate;
-----------------------------------------------------------------------------
@@ -311,19 +312,19 @@ begin
gen_streams : for I in 0 to g_nof_streams - 1 generate
-- Add user xon flow control if the user input does not already support it
u_dp_xonoff : entity dp_lib.dp_xonoff
- generic map (
- g_bypass => g_usr_bypass_xonoff -- if the user input already has xon flow control then bypass using g_usr_bypass_xonoff=TRUE
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- Frame in
- in_siso => usr_siso_arr(I),
- in_sosi => usr_sosi_arr(I),
- -- Frame out
- out_siso => usr_xflow_src_in_arr(I), -- flush control via out_siso.xon
- out_sosi => usr_xflow_src_out_arr(I)
- );
+ generic map (
+ g_bypass => g_usr_bypass_xonoff -- if the user input already has xon flow control then bypass using g_usr_bypass_xonoff=TRUE
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Frame in
+ in_siso => usr_siso_arr(I),
+ in_sosi => usr_sosi_arr(I),
+ -- Frame out
+ out_siso => usr_xflow_src_in_arr(I), -- flush control via out_siso.xon
+ out_sosi => usr_xflow_src_out_arr(I)
+ );
-- Multiplex the inputs:
-- . [0] = usr input
@@ -335,30 +336,30 @@ begin
mux_snk_in_2arr_2(I)(1) <= bg_src_out_arr(I);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_technology => g_technology,
- -- MUX
- g_mode => 4, -- g_mode=4 for framed input select via sel_ctrl
- g_nof_input => c_mux_nof_input, -- >= 1
- g_append_channel_lo => false,
- g_sel_ctrl_invert => true, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
- -- Input FIFO
- g_use_fifo => false,
- g_fifo_size => array_init(1024, c_mux_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, c_mux_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- Control
- sel_ctrl => mux_ctrl, -- 0 = usr, 1 = BG
- -- ST sinks
- snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
- snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
- -- ST source
- src_in => mux_src_in_arr(I),
- src_out => mux_src_out_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ -- MUX
+ g_mode => 4, -- g_mode=4 for framed input select via sel_ctrl
+ g_nof_input => c_mux_nof_input, -- >= 1
+ g_append_channel_lo => false,
+ g_sel_ctrl_invert => true, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ -- Input FIFO
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, c_mux_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, c_mux_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Control
+ sel_ctrl => mux_ctrl, -- 0 = usr, 1 = BG
+ -- ST sinks
+ snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
+ snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
+ -- ST source
+ src_in => mux_src_in_arr(I),
+ src_out => mux_src_out_arr(I)
+ );
end generate;
end generate;
@@ -371,29 +372,29 @@ begin
gen_tx_seq : if g_use_tx_seq = true generate
u_mms_diag_tx_seq : entity work.mms_diag_tx_seq
- generic map (
- g_use_usr_input => c_use_tx_seq_input,
- g_mm_broadcast => c_reg_tx_seq_broadcast,
- g_nof_streams => g_nof_streams,
- g_seq_dat_w => g_seq_dat_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- reg_mosi => reg_tx_seq_mosi,
- reg_miso => reg_tx_seq_miso,
-
- -- DP streaming interface
- usr_snk_out_arr => mux_src_in_arr, -- connect when g_use_usr_input=TRUE, else leave not connected
- usr_snk_in_arr => mux_src_out_arr,
- tx_src_out_arr => out_sosi_arr,
- tx_src_in_arr => out_siso_arr
- );
+ generic map (
+ g_use_usr_input => c_use_tx_seq_input,
+ g_mm_broadcast => c_reg_tx_seq_broadcast,
+ g_nof_streams => g_nof_streams,
+ g_seq_dat_w => g_seq_dat_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ reg_mosi => reg_tx_seq_mosi,
+ reg_miso => reg_tx_seq_miso,
+
+ -- DP streaming interface
+ usr_snk_out_arr => mux_src_in_arr, -- connect when g_use_usr_input=TRUE, else leave not connected
+ usr_snk_in_arr => mux_src_out_arr,
+ tx_src_out_arr => out_sosi_arr,
+ tx_src_in_arr => out_siso_arr
+ );
end generate;
end rtl;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd b/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
index 481104862a..12e00675d4 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
@@ -58,13 +58,13 @@
-- capture some data before and after the trigger event.
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_data_buffer is
generic (
@@ -131,28 +131,28 @@ begin
gen_db : if g_use_db = true generate
-- Combine the internal array of mm interfaces for the data_buf to one array that is connected to the port of the MM bus
u_mem_mux_data_buf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_buf_adr_w
- )
- port map (
- mosi => ram_data_buf_mosi,
- miso => ram_data_buf_miso,
- mosi_arr => ram_data_buf_mosi_arr,
- miso_arr => ram_data_buf_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_buf_adr_w
+ )
+ port map (
+ mosi => ram_data_buf_mosi,
+ miso => ram_data_buf_miso,
+ mosi_arr => ram_data_buf_mosi_arr,
+ miso_arr => ram_data_buf_miso_arr
+ );
u_mem_mux_reg : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_data_buf_mosi,
- miso => reg_data_buf_miso,
- mosi_arr => reg_data_buf_mosi_arr,
- miso_arr => reg_data_buf_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
+ )
+ port map (
+ mosi => reg_data_buf_mosi,
+ miso => reg_data_buf_miso,
+ mosi_arr => reg_data_buf_mosi_arr,
+ miso_arr => reg_data_buf_miso_arr
+ );
gen_stream : for I in 0 to g_nof_streams - 1 generate
in_data_arr(I) <= in_sosi_arr(I).im(g_data_w / 2 - 1 downto 0) & in_sosi_arr(I).re(g_data_w / 2 - 1 downto 0) when g_data_type = e_complex else
@@ -161,31 +161,31 @@ begin
in_sosi_arr(I).data(g_data_w - 1 downto 0); -- g_data_type=e_data is default
u_diag_data_buffer : entity work.diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_nof_data => g_buf_nof_data,
- g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_mm_mosi => ram_data_buf_mosi_arr(I),
- ram_mm_miso => ram_data_buf_miso_arr(I),
-
- reg_mm_mosi => reg_data_buf_mosi_arr(I),
- reg_mm_miso => reg_data_buf_miso_arr(I),
-
- -- Streaming clock domain
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- in_data => in_data_arr(I),
- in_sync => in_sync,
- in_val => in_sosi_arr(I).valid
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_nof_data => g_buf_nof_data,
+ g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_mm_mosi => ram_data_buf_mosi_arr(I),
+ ram_mm_miso => ram_data_buf_miso_arr(I),
+
+ reg_mm_mosi => reg_data_buf_mosi_arr(I),
+ reg_mm_miso => reg_data_buf_miso_arr(I),
+
+ -- Streaming clock domain
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ in_data => in_data_arr(I),
+ in_sync => in_sync,
+ in_val => in_sosi_arr(I).valid
+ );
end generate;
end generate;
@@ -195,27 +195,27 @@ begin
gen_rx_seq : if g_use_rx_seq = true generate
u_mms_diag_rx_seq : entity work.mms_diag_rx_seq
- generic map (
- g_nof_streams => g_nof_streams,
- g_use_steps => g_use_steps,
- g_nof_steps => g_nof_steps,
- g_seq_dat_w => g_seq_dat_w, -- >= 1, test sequence data width
- g_data_w => g_data_w -- >= g_seq_dat_w, user data width
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped Slave
- reg_mosi => reg_rx_seq_mosi, -- multiplexed port for g_nof_streams MM control/status registers
- reg_miso => reg_rx_seq_miso,
-
- -- Streaming interface
- rx_snk_in_arr => in_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_use_steps => g_use_steps,
+ g_nof_steps => g_nof_steps,
+ g_seq_dat_w => g_seq_dat_w, -- >= 1, test sequence data width
+ g_data_w => g_data_w -- >= g_seq_dat_w, user data width
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped Slave
+ reg_mosi => reg_rx_seq_mosi, -- multiplexed port for g_nof_streams MM control/status registers
+ reg_miso => reg_rx_seq_miso,
+
+ -- Streaming interface
+ rx_snk_in_arr => in_sosi_arr
+ );
end generate;
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd b/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
index 6bfbb0dab8..e328d9dc43 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
@@ -58,13 +58,13 @@
-- capture some data before and after the trigger event.
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_data_buffer_dev is
generic (
@@ -132,28 +132,28 @@ begin
gen_db : if g_use_db = true generate
-- Combine the internal array of mm interfaces for the data_buf to one array that is connected to the port of the MM bus
u_mem_mux_data_buf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_buf_adr_w
- )
- port map (
- mosi => ram_data_buf_mosi,
- miso => ram_data_buf_miso,
- mosi_arr => ram_data_buf_mosi_arr,
- miso_arr => ram_data_buf_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_buf_adr_w
+ )
+ port map (
+ mosi => ram_data_buf_mosi,
+ miso => ram_data_buf_miso,
+ mosi_arr => ram_data_buf_mosi_arr,
+ miso_arr => ram_data_buf_miso_arr
+ );
u_mem_mux_reg : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_data_buf_mosi,
- miso => reg_data_buf_miso,
- mosi_arr => reg_data_buf_mosi_arr,
- miso_arr => reg_data_buf_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
+ )
+ port map (
+ mosi => reg_data_buf_mosi,
+ miso => reg_data_buf_miso,
+ mosi_arr => reg_data_buf_mosi_arr,
+ miso_arr => reg_data_buf_miso_arr
+ );
gen_stream : for I in 0 to g_nof_streams - 1 generate
in_data_arr(I) <= in_sosi_arr(I).im(g_data_w / 2 - 1 downto 0) & in_sosi_arr(I).re(g_data_w / 2 - 1 downto 0) when g_data_type = e_complex else
@@ -162,32 +162,32 @@ begin
in_sosi_arr(I).data(g_data_w - 1 downto 0); -- g_data_type=e_data is default
u_diag_data_buffer : entity work.diag_data_buffer_dev
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_nof_data => g_buf_nof_data,
- g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_mm_mosi => ram_data_buf_mosi_arr(I),
- ram_mm_miso => ram_data_buf_miso_arr(I),
-
- reg_mm_mosi => reg_data_buf_mosi_arr(I),
- reg_mm_miso => reg_data_buf_miso_arr(I),
-
- -- Streaming clock domain
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- in_data => in_data_arr(I),
- in_sync => in_sync,
- in_val => in_sosi_arr(I).valid,
- out_wr_done => out_wr_done_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_nof_data => g_buf_nof_data,
+ g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_mm_mosi => ram_data_buf_mosi_arr(I),
+ ram_mm_miso => ram_data_buf_miso_arr(I),
+
+ reg_mm_mosi => reg_data_buf_mosi_arr(I),
+ reg_mm_miso => reg_data_buf_miso_arr(I),
+
+ -- Streaming clock domain
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ in_data => in_data_arr(I),
+ in_sync => in_sync,
+ in_val => in_sosi_arr(I).valid,
+ out_wr_done => out_wr_done_arr(I)
+ );
end generate;
end generate;
@@ -197,27 +197,27 @@ begin
gen_rx_seq : if g_use_rx_seq = true generate
u_mms_diag_rx_seq : entity work.mms_diag_rx_seq
- generic map (
- g_nof_streams => g_nof_streams,
- g_use_steps => g_use_steps,
- g_nof_steps => g_nof_steps,
- g_seq_dat_w => g_seq_dat_w, -- >= 1, test sequence data width
- g_data_w => g_data_w -- >= g_seq_dat_w, user data width
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped Slave
- reg_mosi => reg_rx_seq_mosi, -- multiplexed port for g_nof_streams MM control/status registers
- reg_miso => reg_rx_seq_miso,
-
- -- Streaming interface
- rx_snk_in_arr => in_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_use_steps => g_use_steps,
+ g_nof_steps => g_nof_steps,
+ g_seq_dat_w => g_seq_dat_w, -- >= 1, test sequence data width
+ g_data_w => g_data_w -- >= g_seq_dat_w, user data width
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped Slave
+ reg_mosi => reg_rx_seq_mosi, -- multiplexed port for g_nof_streams MM control/status registers
+ reg_miso => reg_rx_seq_miso,
+
+ -- Streaming interface
+ rx_snk_in_arr => in_sosi_arr
+ );
end generate;
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
index f3c7d79645..3fa51d4443 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
@@ -1,4 +1,4 @@
- -------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
@@ -95,13 +95,13 @@
-- COUNTER increment values.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
entity mms_diag_rx_seq is
generic (
@@ -129,21 +129,23 @@ end mms_diag_rx_seq;
architecture str of mms_diag_rx_seq is
-- Define MM slave register size
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => c_diag_seq_rx_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_diag_seq_rx_reg_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_diag_seq_rx_reg_adr_w,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_diag_seq_rx_reg_nof_dat,
+ init_sl => '0');
-- Define MM slave register fields for Python peripheral using pi_common.py (specify MM register access per word, not per individual bit because mm_fields assumes 1 field per MM word)
- constant c_mm_reg_field_arr : t_common_field_arr(c_mm_reg.nof_dat - 1 downto 0) := ( ( field_name_pad("step_3"), "RW", c_word_w, field_default(0) ), -- [7] = diag_steps_arr[3], c_diag_seq_rx_reg_nof_steps = 4
- ( field_name_pad("step_2"), "RW", c_word_w, field_default(0) ), -- [6] = diag_steps_arr[2]
- ( field_name_pad("step_1"), "RW", c_word_w, field_default(0) ), -- [5] = diag_steps_arr[1]
- ( field_name_pad("step_0"), "RW", c_word_w, field_default(0) ), -- [4] = diag_steps_arr[0]
- ( field_name_pad("rx_sample"), "RO", c_word_w, field_default(0) ), -- [3]
- ( field_name_pad("rx_cnt"), "RO", c_word_w, field_default(0) ), -- [2]
- ( field_name_pad("result"), "RO", 2, field_default(0) ), -- [1] = result[1:0] = res_val_n & res_ok_n
- ( field_name_pad("control"), "RW", 2, field_default(0) )); -- [0] = control[1:0] = diag_sel & diag_en
+ constant c_mm_reg_field_arr : t_common_field_arr(
+ c_mm_reg.nof_dat - 1 downto 0) := ( ( field_name_pad("step_3"), "RW", c_word_w, field_default(0) ), -- [7] = diag_steps_arr[3], c_diag_seq_rx_reg_nof_steps = 4
+ ( field_name_pad("step_2"), "RW", c_word_w, field_default(0) ), -- [6] = diag_steps_arr[2]
+ ( field_name_pad("step_1"), "RW", c_word_w, field_default(0) ), -- [5] = diag_steps_arr[1]
+ ( field_name_pad("step_0"), "RW", c_word_w, field_default(0) ), -- [4] = diag_steps_arr[0]
+ ( field_name_pad("rx_sample"), "RO", c_word_w, field_default(0) ), -- [3]
+ ( field_name_pad("rx_cnt"), "RO", c_word_w, field_default(0) ), -- [2]
+ ( field_name_pad("result"), "RO", 2, field_default(0) ), -- [1] = result[1:0] = res_val_n & res_ok_n
+ ( field_name_pad("control"), "RW", 2, field_default(0) )); -- [0] = control[1:0] = diag_sel & diag_en
constant c_reg_slv_w : natural := c_mm_reg.nof_dat * c_mm_reg.dat_w;
constant c_reg_dat_w : natural := smallest(c_word_w, g_seq_dat_w);
@@ -212,34 +214,34 @@ begin
-- detect rx sequence errors
u_diag_rx_seq: entity WORK.diag_rx_seq
- generic map (
- g_use_steps => g_use_steps,
- g_nof_steps => g_nof_steps,
- g_cnt_w => c_word_w,
- g_dat_w => g_seq_dat_w,
- g_diag_res_w => g_seq_dat_w -- do not use g_seq_dat_w+1 to include NOT diag_res_val in MSbit, instead use diag_res_val output
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_use_steps => g_use_steps,
+ g_nof_steps => g_nof_steps,
+ g_cnt_w => c_word_w,
+ g_dat_w => g_seq_dat_w,
+ g_diag_res_w => g_seq_dat_w -- do not use g_seq_dat_w+1 to include NOT diag_res_val in MSbit, instead use diag_res_val output
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- -- Write and read back registers:
- diag_en => diag_en_arr(I),
- diag_sel => diag_sel_arr(I),
- diag_steps_arr => diag_steps_2arr(I),
+ -- Write and read back registers:
+ diag_en => diag_en_arr(I),
+ diag_sel => diag_sel_arr(I),
+ diag_steps_arr => diag_steps_2arr(I),
- -- Read only registers:
- diag_res => diag_res_arr(I),
- diag_res_val => diag_res_val_arr(I),
- diag_sample => rx_sample_arr(I),
- diag_sample_diff => rx_sample_diff_arr(I),
- diag_sample_val => rx_sample_val_arr(I),
+ -- Read only registers:
+ diag_res => diag_res_arr(I),
+ diag_res_val => diag_res_val_arr(I),
+ diag_sample => rx_sample_arr(I),
+ diag_sample_diff => rx_sample_diff_arr(I),
+ diag_sample_val => rx_sample_val_arr(I),
- -- Streaming
- in_cnt => rx_cnt_arr(I),
- in_dat => rx_seq_arr(I),
- in_val => rx_seq_val_arr(I)
- );
+ -- Streaming
+ in_cnt => rx_cnt_arr(I),
+ in_dat => rx_seq_arr(I),
+ in_val => rx_seq_val_arr(I)
+ );
-- Map diag_res to single bit and register it to ease timing closure
stat_res_ok_n_arr(I) <= orv(diag_res_arr(I)) when rising_edge(dp_clk);
@@ -267,38 +269,38 @@ begin
end process;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(I),
- sla_out => reg_miso_arr(I),
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(I),
+ sla_out => reg_miso_arr(I),
- -- MM registers in dp_clk domain
- in_reg => stat_reg_arr(I),
- out_reg => ctrl_reg_arr(I)
- );
+ -- MM registers in dp_clk domain
+ in_reg => stat_reg_arr(I),
+ out_reg => ctrl_reg_arr(I)
+ );
end generate;
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
u_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_mm_reg.adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_mm_reg.adr_w
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
index 879b31e632..97a1c88d2d 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
@@ -1,4 +1,4 @@
- -------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
@@ -150,12 +150,12 @@
-- yields a different CNTR value than reading 2**(g_seq_dat_w+1).
library IEEE, common_lib, dp_lib; -- init value for out_dat when diag_en = '0'
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
entity mms_diag_tx_seq is
generic (
@@ -185,17 +185,19 @@ end mms_diag_tx_seq;
architecture str of mms_diag_tx_seq is
-- Define MM slave register size
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => c_diag_seq_tx_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_diag_seq_tx_reg_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_diag_seq_tx_reg_adr_w,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_diag_seq_tx_reg_nof_dat,
+ init_sl => '0');
-- Define MM slave register fields for Python peripheral using pi_common.py (specify MM register access per word, not per individual bit because mm_fields assumes 1 field per MM word)
- constant c_mm_reg_field_arr : t_common_field_arr(c_mm_reg.nof_dat - 1 downto 0) := ( ( field_name_pad("modulo"), "RW", c_word_w, field_default(0) ),
- ( field_name_pad("tx_cnt"), "RO", c_word_w, field_default(0) ),
- ( field_name_pad("init"), "RW", c_word_w, field_default(0) ),
- ( field_name_pad("control"), "RW", 3, field_default(0) )); -- control[2:0] = diag_dc & diag_sel & diag_en
+ constant c_mm_reg_field_arr : t_common_field_arr(
+ c_mm_reg.nof_dat - 1 downto 0) := ( ( field_name_pad("modulo"), "RW", c_word_w, field_default(0) ),
+ ( field_name_pad("tx_cnt"), "RO", c_word_w, field_default(0) ),
+ ( field_name_pad("init"), "RW", c_word_w, field_default(0) ),
+ ( field_name_pad("control"), "RW", 3, field_default(0) )); -- control[2:0] = diag_dc & diag_sel & diag_en
constant c_reg_slv_w : natural := c_mm_reg.nof_dat * c_mm_reg.dat_w;
@@ -240,28 +242,28 @@ begin
gen_nof_streams: for I in 0 to g_nof_streams - 1 generate
u_diag_tx_seq: entity WORK.diag_tx_seq
- generic map (
- g_latency => c_latency,
- g_cnt_w => c_word_w,
- g_dat_w => g_seq_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Write and read back registers:
- diag_en => diag_en_arr(I),
- diag_sel => diag_sel_arr(I),
- diag_dc => diag_dc_arr(I),
- diag_init => diag_init_arr(I),
- diag_mod => diag_mod_arr(I),
-
- -- Streaming
- diag_req => tx_req_arr(I),
- out_cnt => tx_cnt_arr(I),
- out_dat => tx_dat_arr(I),
- out_val => tx_val_arr(I)
- );
+ generic map (
+ g_latency => c_latency,
+ g_cnt_w => c_word_w,
+ g_dat_w => g_seq_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Write and read back registers:
+ diag_en => diag_en_arr(I),
+ diag_sel => diag_sel_arr(I),
+ diag_dc => diag_dc_arr(I),
+ diag_init => diag_init_arr(I),
+ diag_mod => diag_mod_arr(I),
+
+ -- Streaming
+ diag_req => tx_req_arr(I),
+ out_cnt => tx_cnt_arr(I),
+ out_dat => tx_dat_arr(I),
+ out_val => tx_val_arr(I)
+ );
tx_req_arr(I) <= tx_seq_src_in_arr(I).ready;
@@ -290,41 +292,41 @@ begin
end process;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(I),
- sla_out => reg_miso_arr(I),
-
- -- MM registers in dp_clk domain
- in_reg => stat_reg_arr(I), -- connect out_reg to in_reg for write and readback register
- out_reg => ctrl_reg_arr(I)
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(I),
+ sla_out => reg_miso_arr(I),
+
+ -- MM registers in dp_clk domain
+ in_reg => stat_reg_arr(I), -- connect out_reg to in_reg for write and readback register
+ out_reg => ctrl_reg_arr(I)
+ );
end generate;
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
u_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_broadcast => g_mm_broadcast,
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_mm_reg.adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_broadcast => g_mm_broadcast,
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_mm_reg.adr_w
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
ignore_usr_input : if g_use_usr_input = false generate
-- flow control
@@ -367,19 +369,19 @@ begin
-- Pipeline the streams by 1 to register the mux_seq_src_out_arr data to ease timing closure given that c_tx_seq_latency=0
u_dp_pipeline_arr : entity dp_lib.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out_arr => mux_seq_src_in_arr,
- snk_in_arr => mux_seq_src_out_arr,
- -- ST source
- src_in_arr => tx_src_in_arr,
- src_out_arr => tx_src_out_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out_arr => mux_seq_src_in_arr,
+ snk_in_arr => mux_seq_src_out_arr,
+ -- ST source
+ src_in_arr => tx_src_in_arr,
+ src_out_arr => tx_src_out_arr
+ );
end generate;
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
index f23fda685a..8840d62fb3 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
@@ -28,12 +28,12 @@
--
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_wg_wideband is
generic (
@@ -82,64 +82,64 @@ architecture str of mms_diag_wg_wideband is
signal st_mon_ctrl : t_diag_wg; -- read
begin
u_mm_reg : entity work.diag_wg_wideband_reg
- generic map (
- g_cross_clock_domain => g_cross_clock_domain
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- st_wg_ctrl => st_wg_ctrl,
- st_mon_ctrl => st_mon_ctrl
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ st_wg_ctrl => st_wg_ctrl,
+ st_mon_ctrl => st_mon_ctrl
+ );
u_wg_wideband : entity work.diag_wg_wideband
- generic map (
- g_technology => g_technology,
- -- Use g_buf_dir to be able to have different path to waveform file for sim and for synth
- g_buf_dir => g_buf_dir,
-
- -- Wideband parameters
- g_wideband_factor => g_wideband_factor,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w,
- g_calc_support => g_calc_support,
- g_calc_gain_w => g_calc_gain_w,
- g_calc_dat_w => g_calc_dat_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- mm_wrdata => buf_mosi.wrdata(g_buf_dat_w - 1 downto 0),
- mm_address => buf_mosi.address(g_buf_addr_w - 1 downto 0),
- mm_wr => buf_mosi.wr,
- mm_rd => buf_mosi.rd,
- mm_rdval => buf_miso.rdval,
- mm_rddata => buf_miso.rddata(g_buf_dat_w - 1 downto 0),
-
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
- st_restart => st_restart,
-
- st_ctrl => st_wg_ctrl,
- st_mon_ctrl => st_mon_ctrl,
-
- out_ovr => out_ovr,
- out_dat => out_dat,
- out_val => out_val,
- out_sync => out_sync
- );
+ generic map (
+ g_technology => g_technology,
+ -- Use g_buf_dir to be able to have different path to waveform file for sim and for synth
+ g_buf_dir => g_buf_dir,
+
+ -- Wideband parameters
+ g_wideband_factor => g_wideband_factor,
+
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w,
+ g_calc_support => g_calc_support,
+ g_calc_gain_w => g_calc_gain_w,
+ g_calc_dat_w => g_calc_dat_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ mm_wrdata => buf_mosi.wrdata(g_buf_dat_w - 1 downto 0),
+ mm_address => buf_mosi.address(g_buf_addr_w - 1 downto 0),
+ mm_wr => buf_mosi.wr,
+ mm_rd => buf_mosi.rd,
+ mm_rdval => buf_miso.rdval,
+ mm_rddata => buf_miso.rddata(g_buf_dat_w - 1 downto 0),
+
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_restart => st_restart,
+
+ st_ctrl => st_wg_ctrl,
+ st_mon_ctrl => st_mon_ctrl,
+
+ out_ovr => out_ovr,
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sync => out_sync
+ );
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
index aa5b1be2c4..70a80d8d11 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
@@ -27,13 +27,13 @@
-- no need to make a mms_diag_wg.vhd.
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_wg_wideband_arr is
generic (
@@ -89,63 +89,63 @@ architecture str of mms_diag_wg_wideband_arr is
signal wg_sync : std_logic_vector(g_nof_streams * g_wideband_factor - 1 downto 0);
begin
u_common_mem_mux_reg : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
u_common_mem_mux_buf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => g_buf_addr_w
- )
- port map (
- mosi => buf_mosi,
- miso => buf_miso,
- mosi_arr => buf_mosi_arr,
- miso_arr => buf_miso_arr
- );
-
- gen_wg : for I in 0 to g_nof_streams - 1 generate
- u_mms_diag_wg_wideband : entity work.mms_diag_wg_wideband
generic map (
- g_technology => g_technology,
- g_cross_clock_domain => g_cross_clock_domain,
- g_buf_dir => g_buf_dir,
- g_wideband_factor => g_wideband_factor,
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w,
- g_calc_support => g_calc_support,
- g_calc_gain_w => g_calc_gain_w,
- g_calc_dat_w => g_calc_dat_w
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => g_buf_addr_w
)
port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_mosi_arr(I),
- reg_miso => reg_miso_arr(I),
-
- buf_mosi => buf_mosi_arr(I),
- buf_miso => buf_miso_arr(I),
-
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
- st_restart => st_restart,
+ mosi => buf_mosi,
+ miso => buf_miso,
+ mosi_arr => buf_mosi_arr,
+ miso_arr => buf_miso_arr
+ );
- out_ovr => wg_ovr( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ),
- out_dat => wg_dat( (I + 1) * g_wideband_factor * g_buf_dat_w - 1 downto I * g_wideband_factor * g_buf_dat_w),
- out_val => wg_val( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ),
- out_sync => wg_sync((I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor )
- );
+ gen_wg : for I in 0 to g_nof_streams - 1 generate
+ u_mms_diag_wg_wideband : entity work.mms_diag_wg_wideband
+ generic map (
+ g_technology => g_technology,
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_buf_dir => g_buf_dir,
+ g_wideband_factor => g_wideband_factor,
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w,
+ g_calc_support => g_calc_support,
+ g_calc_gain_w => g_calc_gain_w,
+ g_calc_dat_w => g_calc_dat_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_mosi_arr(I),
+ reg_miso => reg_miso_arr(I),
+
+ buf_mosi => buf_mosi_arr(I),
+ buf_miso => buf_miso_arr(I),
+
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_restart => st_restart,
+
+ out_ovr => wg_ovr( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ),
+ out_dat => wg_dat( (I + 1) * g_wideband_factor * g_buf_dat_w - 1 downto I * g_wideband_factor * g_buf_dat_w),
+ out_val => wg_val( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ),
+ out_sync => wg_sync((I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor )
+ );
-- wire the wg signals to sosi outputs
-- This is done as per the method used in unb1_bn_capture_input (Apertif)
@@ -155,8 +155,8 @@ begin
out_sosi_arr(I).valid <= vector_or(wg_val( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ));
out_sosi_arr(I).sync <= vector_or(wg_sync((I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ));
out_sosi_arr(I).err <= TO_DP_ERROR(0) when
- vector_or(wg_ovr( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor )) = '0' else
- TO_DP_ERROR(2**7); -- pass ADC or WG overflow info on as an error signal
+ vector_or(wg_ovr( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor )) = '0' else
+ TO_DP_ERROR(2**7); -- pass ADC or WG overflow info on as an error signal
end generate;
end str;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
index 4ec82902c6..93f8369595 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
@@ -28,17 +28,17 @@
-- > run -all
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_math_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_math_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.diag_pkg.all;
entity tb_diag_block_gen is
generic (
@@ -51,7 +51,7 @@ entity tb_diag_block_gen is
g_buf_adr_w : natural := 7; -- Waveform buffer address width (requires corresponding c_buf_file)
g_buf_dat_w : natural := 32; -- Waveform buffer stored data width (requires corresponding c_buf_file)
g_try_phasor : boolean := false -- use TRUE to see BG phasor in wave window with out_sosi.re/im in radix
- -- decimal and analogue format, no self test
+ -- decimal and analogue format, no self test
);
end tb_diag_block_gen;
@@ -62,11 +62,12 @@ architecture tb of tb_diag_block_gen is
constant c_runtime : natural := 1500;
-- Default settings
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => g_buf_adr_w,
- dat_w => g_buf_dat_w,
- nof_dat => 2**g_buf_adr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => g_buf_adr_w,
+ dat_w => g_buf_dat_w,
+ nof_dat => 2**g_buf_adr_w, -- = 2**adr_w
+ init_sl => '0');
constant c_buf_file : string := sel_a_b(c_buf.adr_w = 7 and c_buf.dat_w = 32, "data/diag_block.hex", "UNUSED");
@@ -83,21 +84,23 @@ architecture tb of tb_diag_block_gen is
constant c_phasor_ampl : real := 1.0 * c_phasor_unit_ampl; -- use g_phasor_ampl <= 1.0 to avoid wrapping
constant c_phasor_freq : real := 2.0; -- in range -N/2 : N/2-1
constant c_phasor_phase : real := 0.0;
- constant c_phasor_exp_arr : t_slv_32_arr := common_math_create_look_up_table_phasor(c_phasor_nof_points,
- c_phasor_dat_w,
- c_phasor_ampl,
- c_phasor_freq,
- c_phasor_phase);
+ constant c_phasor_exp_arr : t_slv_32_arr := common_math_create_look_up_table_phasor(
+ c_phasor_nof_points,
+ c_phasor_dat_w,
+ c_phasor_ampl,
+ c_phasor_freq,
+ c_phasor_phase);
-- Default BG control
- constant c_bg_ctrl : t_diag_block_gen := ( '0',
- '0',
- TO_UVEC(g_nof_samples_per_packet, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC(g_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC(95, c_diag_bg_mem_high_adrs_w),
- TO_UVEC(42, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0',
+ '0',
+ TO_UVEC(g_nof_samples_per_packet, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(g_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(95, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(42, c_diag_bg_bsn_init_w));
constant c_bg_period : natural := TO_UINT(c_bg_ctrl.samples_per_packet) + TO_UINT(c_bg_ctrl.gapsize);
-- Some alternative BG control settings
@@ -106,14 +109,15 @@ architecture tb of tb_diag_block_gen is
constant c_alternative_data_gap : natural := 1 + c_alternative_mem_low_adrs;
-- Another BG control for verifying XON
- constant c_bg_ctrl2 : t_diag_block_gen := ( '0',
- '0',
- TO_UVEC(17, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( 0, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC(16, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl2 : t_diag_block_gen := (
+ '0',
+ '0',
+ TO_UVEC(17, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( 0, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(16, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
constant c_bg_period2 : natural := TO_UINT(c_bg_ctrl2.samples_per_packet) + TO_UINT(c_bg_ctrl2.gapsize);
@@ -226,46 +230,46 @@ begin
-- Waveform buffer
u_buf : entity common_lib.common_ram_crw_crw
- generic map (
- g_ram => c_buf,
- g_init_file => c_buf_file
- )
- port map (
- rst_a => '0',
- rst_b => '0',
- clk_a => clk,
- clk_b => clk,
- wr_en_a => mm_buf_mosi.wr,
- wr_en_b => '0',
- wr_dat_a => mm_buf_mosi.wrdata(c_buf.dat_w - 1 downto 0),
- wr_dat_b => (others => '0'),
- adr_a => mm_buf_mosi.address(c_buf.adr_w - 1 downto 0),
- adr_b => bg_buf_mosi.address(c_buf.adr_w - 1 downto 0),
- rd_en_a => mm_buf_mosi.rd,
- rd_en_b => bg_buf_mosi.rd,
- rd_dat_a => mm_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
- rd_dat_b => bg_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
- rd_val_a => mm_buf_miso.rdval,
- rd_val_b => bg_buf_miso.rdval
- );
+ generic map (
+ g_ram => c_buf,
+ g_init_file => c_buf_file
+ )
+ port map (
+ rst_a => '0',
+ rst_b => '0',
+ clk_a => clk,
+ clk_b => clk,
+ wr_en_a => mm_buf_mosi.wr,
+ wr_en_b => '0',
+ wr_dat_a => mm_buf_mosi.wrdata(c_buf.dat_w - 1 downto 0),
+ wr_dat_b => (others => '0'),
+ adr_a => mm_buf_mosi.address(c_buf.adr_w - 1 downto 0),
+ adr_b => bg_buf_mosi.address(c_buf.adr_w - 1 downto 0),
+ rd_en_a => mm_buf_mosi.rd,
+ rd_en_b => bg_buf_mosi.rd,
+ rd_dat_a => mm_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
+ rd_dat_b => bg_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
+ rd_val_a => mm_buf_miso.rdval,
+ rd_val_b => bg_buf_miso.rdval
+ );
u_dut : entity work.diag_block_gen
- generic map(
- g_buf_dat_w => c_buf.dat_w,
- g_buf_addr_w => c_buf.adr_w
- )
- port map (
- rst => rst,
- clk => clk,
- buf_addr => bg_buf_mosi.address(c_buf.adr_w - 1 downto 0),
- buf_rden => bg_buf_mosi.rd,
- buf_rddat => bg_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
- buf_rdval => bg_buf_miso.rdval,
- ctrl => bg_ctrl,
- ctrl_hold => bg_ctrl_hold,
- out_siso => out_siso_bg,
- out_sosi => out_sosi
- );
+ generic map(
+ g_buf_dat_w => c_buf.dat_w,
+ g_buf_addr_w => c_buf.adr_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ buf_addr => bg_buf_mosi.address(c_buf.adr_w - 1 downto 0),
+ buf_rden => bg_buf_mosi.rd,
+ buf_rddat => bg_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
+ buf_rdval => bg_buf_miso.rdval,
+ ctrl => bg_ctrl,
+ ctrl_hold => bg_ctrl_hold,
+ out_siso => out_siso_bg,
+ out_sosi => out_sosi
+ );
random <= func_common_random(random) when rising_edge(clk);
toggle <= not toggle when rising_edge(clk);
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd b/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
index 730f6e6fd0..e7f5e865f2 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
@@ -38,17 +38,17 @@
-- > Evalute the WAVE window.
library IEEE, common_lib, mm_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
entity tb_diag_data_buffer is
generic(
@@ -111,14 +111,15 @@ architecture tb of tb_diag_data_buffer is
constant c_bg_nof_blocks_per_sync : natural := 8;
constant c_bg_mem_high_addr : natural := g_nof_data - 1;
- constant c_bg_ctrl : t_diag_block_gen := ( '0', -- enable: On by default in simulation; MM enable required on hardware.
- '0', -- enable_sync
- TO_UVEC( c_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( c_bg_mem_high_addr, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable: On by default in simulation; MM enable required on hardware.
+ '0', -- enable_sync
+ TO_UVEC( c_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(c_bg_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( c_bg_mem_high_addr, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
-- Configuration of the databuffers:
constant c_db_nof_streams : positive := g_nof_streams;
@@ -151,7 +152,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -213,10 +214,10 @@ begin
end loop;
nof_valids <= 1;
--- WHILE nof_valids /= 0 LOOP
- proc_mem_mm_bus_rd( 2, mm_clk, reg_diag_data_buf_mosi);
- nof_valids <= TO_UINT(reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0));
--- END LOOP;
+ -- WHILE nof_valids /= 0 LOOP
+ proc_mem_mm_bus_rd( 2, mm_clk, reg_diag_data_buf_mosi);
+ nof_valids <= TO_UINT(reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0));
+ -- END LOOP;
proc_common_wait_some_cycles(mm_clk, 10);
-- Arm the databuffer
@@ -229,55 +230,55 @@ begin
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity work.mms_diag_block_gen
- generic map(
- g_nof_streams => c_bg_nof_output_streams,
- g_buf_dat_w => c_bg_buf_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w,
- g_file_index_arr => c_bg_data_file_index_arr,
- g_diag_block_gen_rst => c_bg_ctrl,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_diag_block_gen_rst => c_bg_ctrl,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut : entity work.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_re,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- -- ST interface
- in_sync => bg_sosi_arr(0).sync,
- in_sosi_arr => bg_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => bg_sosi_arr(0).sync,
+ in_sosi_arr => bg_sosi_arr
+ );
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd b/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
index 0156020ba1..e686868113 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
@@ -26,9 +26,9 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_diag_frm_generator is
end tb_diag_frm_generator;
@@ -72,7 +72,7 @@ begin
clk <= not clk or tb_end after c_period / 2;
stimuli: process
- -- run 200 us
+ -- run 200 us
begin
diag_sel <= c_sel;
diag_frame_len <= TO_UVEC(c_frame_len, c_frame_len_w);
@@ -124,35 +124,35 @@ begin
end process;
u_frm_gen : entity work.diag_frm_generator
- generic map (
- g_sel => c_sel,
- g_frame_len => c_frame_len,
- g_sof_period => c_sof_period,
- g_frame_cnt_w => c_frame_cnt_w,
- g_dat_w => c_dat_w,
- g_symbol_w => c_symbol_w,
- g_empty => c_empty
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
-
- -- Static control input (connect via MM or leave open to use default)
- diag_en => diag_en,
- diag_sel => diag_sel,
- diag_frame_len => diag_frame_len,
- diag_sof_period => diag_sof_period,
- diag_frame_cnt => diag_frame_cnt,
-
- -- ST output
- out_ready => seq_req,
- out_dat => seq_dat,
- out_val => seq_val,
- out_sop => seq_sop,
- out_eop => seq_eop,
- out_empty => seq_empty
- );
+ generic map (
+ g_sel => c_sel,
+ g_frame_len => c_frame_len,
+ g_sof_period => c_sof_period,
+ g_frame_cnt_w => c_frame_cnt_w,
+ g_dat_w => c_dat_w,
+ g_symbol_w => c_symbol_w,
+ g_empty => c_empty
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+
+ -- Static control input (connect via MM or leave open to use default)
+ diag_en => diag_en,
+ diag_sel => diag_sel,
+ diag_frame_len => diag_frame_len,
+ diag_sof_period => diag_sof_period,
+ diag_frame_cnt => diag_frame_cnt,
+
+ -- ST output
+ out_ready => seq_req,
+ out_dat => seq_dat,
+ out_val => seq_val,
+ out_sop => seq_sop,
+ out_eop => seq_eop,
+ out_empty => seq_empty
+ );
prev_seq_dat <= seq_dat when rising_edge(clk) and seq_val = '1';
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd b/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
index ef5aa9aa48..797720e3c5 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
@@ -26,9 +26,9 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_diag_frm_monitor is
end tb_diag_frm_monitor;
@@ -75,7 +75,7 @@ begin
clk <= not clk or tb_end after c_period / 2;
stimuli: process
- -- run 200 us
+ -- run 200 us
begin
gen_diag_sel <= c_sel;
gen_diag_frame_len <= TO_UVEC(c_frame_len, c_frame_len_w);
@@ -125,53 +125,53 @@ begin
end process;
u_frm_gen : entity work.diag_frm_generator
- generic map (
- g_sel => c_sel,
- g_frame_len => c_frame_len,
- g_sof_period => c_sof_period,
- g_frame_cnt_w => c_frame_cnt_w,
- g_dat_w => c_dat_w,
- g_symbol_w => c_dat_w,
- g_empty => 0
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
-
- -- Static control input (connect via MM or leave open to use default)
- diag_en => gen_diag_en,
- diag_sel => gen_diag_sel,
- diag_frame_len => gen_diag_frame_len,
- diag_sof_period => gen_diag_sof_period,
- diag_frame_cnt => gen_diag_frame_cnt,
-
- -- ST output
- out_ready => seq_req,
- out_dat => seq_dat,
- out_val => seq_val,
- out_sop => seq_sop,
- out_eop => seq_eop
- );
+ generic map (
+ g_sel => c_sel,
+ g_frame_len => c_frame_len,
+ g_sof_period => c_sof_period,
+ g_frame_cnt_w => c_frame_cnt_w,
+ g_dat_w => c_dat_w,
+ g_symbol_w => c_dat_w,
+ g_empty => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+
+ -- Static control input (connect via MM or leave open to use default)
+ diag_en => gen_diag_en,
+ diag_sel => gen_diag_sel,
+ diag_frame_len => gen_diag_frame_len,
+ diag_sof_period => gen_diag_sof_period,
+ diag_frame_cnt => gen_diag_frame_cnt,
+
+ -- ST output
+ out_ready => seq_req,
+ out_dat => seq_dat,
+ out_val => seq_val,
+ out_sop => seq_sop,
+ out_eop => seq_eop
+ );
u_frm_mon : entity work.diag_frm_monitor
- generic map (
- g_frame_cnt_w => c_frame_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
-
- -- Static control input (connect via MM)
- diag_en => mon_diag_en,
- diag_frame_cnt => mon_diag_frame_cnt,
- diag_error_cnt => mon_diag_error_cnt,
-
- -- ST input
- in_eop => seq_eop,
- in_error => seq_error
- );
+ generic map (
+ g_frame_cnt_w => c_frame_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+
+ -- Static control input (connect via MM)
+ diag_en => mon_diag_en,
+ diag_frame_cnt => mon_diag_frame_cnt,
+ diag_error_cnt => mon_diag_error_cnt,
+
+ -- ST input
+ in_eop => seq_eop,
+ in_error => seq_error
+ );
prev_seq_dat <= seq_dat when rising_edge(clk) and seq_val = '1';
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
index 9d1b394675..e22f6a339c 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
@@ -23,16 +23,16 @@
-- Purpose: Test bench package for diag library
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.diag_pkg.all;
package tb_diag_pkg is
-- Test modes for diag seq
@@ -43,161 +43,174 @@ package tb_diag_pkg is
s_expect_no_result
);
- procedure proc_diag_seq_read_all(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal tx_miso : in t_mem_miso;
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso;
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_tx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
- constant c_tx_init : in natural;
- constant c_tx_mod : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_rx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_tx_disable(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_rx_disable(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_rx_write_steps(constant c_stream : in natural;
- constant c_steps_arr : in t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0);
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_verify(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal tx_miso : in t_mem_miso;
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso;
- signal rx_mosi : out t_mem_mosi;
- signal tb_mode : inout t_tb_diag_seq_mode_enum;
- signal tb_verify : out std_logic;
- signal rd_reg : inout t_diag_seq_mm_reg); -- read all MM reg
+ procedure proc_diag_seq_read_all(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal tx_miso : in t_mem_miso;
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso;
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_tx_enable(
+ constant c_stream : in natural;
+ constant c_pattern : in string; -- "PSRG", "CNTR"
+ constant c_tx_init : in natural;
+ constant c_tx_mod : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_rx_enable(
+ constant c_stream : in natural;
+ constant c_pattern : in string; -- "PSRG", "CNTR"
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_tx_disable(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_rx_disable(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_rx_write_steps(
+ constant c_stream : in natural;
+ constant c_steps_arr : in t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0);
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_verify(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal tx_miso : in t_mem_miso;
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso;
+ signal rx_mosi : out t_mem_mosi;
+ signal tb_mode : inout t_tb_diag_seq_mode_enum;
+ signal tb_verify : out std_logic;
+ signal rd_reg : inout t_diag_seq_mm_reg); -- read all MM reg
-- Measure ADC/WG input power and determine effective sine amplitude
- procedure proc_diag_measure_cw_statistics(constant c_nof_samples : in natural; -- number of samples per in_start interval
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal track_max : inout real; -- store local tracker in signal
- signal track_min : inout real; -- store local tracker in signal
- signal accum_mean : inout real; -- store local accumulator in signal
- signal accum_power : inout real; -- store local accumulator in signal
- signal measured_max : out real; -- maximum sample value
- signal measured_min : out real; -- minimum sample value
- signal measured_mean : out real; -- average sample value (DC)
- signal measured_power : out real; -- average sample power
- signal measured_ampl : out real); -- corresponding sine amplitude
+ procedure proc_diag_measure_cw_statistics(
+ constant c_nof_samples : in natural; -- number of samples per in_start interval
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal track_max : inout real; -- store local tracker in signal
+ signal track_min : inout real; -- store local tracker in signal
+ signal accum_mean : inout real; -- store local accumulator in signal
+ signal accum_power : inout real; -- store local accumulator in signal
+ signal measured_max : out real; -- maximum sample value
+ signal measured_min : out real; -- minimum sample value
+ signal measured_mean : out real; -- average sample value (DC)
+ signal measured_power : out real; -- average sample power
+ signal measured_ampl : out real); -- corresponding sine amplitude
-- Measure ADC/WG amplitude and phase using local sin and cos
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_nof_samples : in natural; -- number of samples per in_start interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal ref_I : out real; -- output local I as signal for debugging in wave window
- signal ref_Q : out real; -- output local Q as signal for debugging in wave window
- signal accum_I : inout real; -- store local I accumulator in signal
- signal accum_Q : inout real; -- store local Q accumulator in signal
- signal measured_ampl : out real; -- measured CW amplitude
- signal measured_phase : out real; -- measured CW phase in radials
- signal measured_phase_Ts : out real); -- measured CW phase in sample periods
-
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
- constant c_sub : in real;
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic;
- signal in_val : in std_logic;
- signal in_cnt : in natural;
- signal ref_I : out real;
- signal ref_Q : out real;
- signal accum_I : inout real;
- signal accum_Q : inout real;
- signal measured_ampl : out real;
- signal measured_phase : out real;
- signal measured_phase_Ts : out real);
+ procedure proc_diag_measure_cw_ampl_and_phase(
+ constant c_nof_samples : in natural; -- number of samples per in_start interval
+ constant c_fft_size : in natural; -- number of points of FFT
+ constant c_sub : in real; -- subband index
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal in_cnt : in natural; -- sample index in c_fft_size
+ signal ref_I : out real; -- output local I as signal for debugging in wave window
+ signal ref_Q : out real; -- output local Q as signal for debugging in wave window
+ signal accum_I : inout real; -- store local I accumulator in signal
+ signal accum_Q : inout real; -- store local Q accumulator in signal
+ signal measured_ampl : out real; -- measured CW amplitude
+ signal measured_phase : out real; -- measured CW phase in radials
+ signal measured_phase_Ts : out real); -- measured CW phase in sample periods
+
+ procedure proc_diag_measure_cw_ampl_and_phase(
+ constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
+ constant c_sub : in real;
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic;
+ signal in_val : in std_logic;
+ signal in_cnt : in natural;
+ signal ref_I : out real;
+ signal ref_Q : out real;
+ signal accum_I : inout real;
+ signal accum_Q : inout real;
+ signal measured_ampl : out real;
+ signal measured_phase : out real;
+ signal measured_phase_Ts : out real);
-- Use estimated CW to determine noise power in input sine (e.g. WG sine)
- procedure proc_diag_measure_cw_noise_power(constant c_nof_samples : in natural; -- number of samples per integration interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal cw_ampl : in real; -- estimated CW amplitude of in_dat
- signal cw_phase : in real; -- estimated CW phase of in_dat
- signal cw_dat : out integer; -- estimated CW
- signal cw_noise : out real; -- estimated CW quantization noise
- signal accum_noise_power : inout real; -- store noise power accumulator in signal
- signal measured_noise_power : out real); -- measured noise power in in_dat
-
- procedure proc_diag_measure_cw_noise_power(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
- constant c_sub : in real;
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic;
- signal in_val : in std_logic;
- signal in_cnt : in natural;
- signal cw_ampl : in real;
- signal cw_phase : in real;
- signal cw_dat : out integer;
- signal cw_noise : out real;
- signal accum_noise_power : inout real;
- signal measured_noise_power : out real);
+ procedure proc_diag_measure_cw_noise_power(
+ constant c_nof_samples : in natural; -- number of samples per integration interval
+ constant c_fft_size : in natural; -- number of points of FFT
+ constant c_sub : in real; -- subband index
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal in_cnt : in natural; -- sample index in c_fft_size
+ signal cw_ampl : in real; -- estimated CW amplitude of in_dat
+ signal cw_phase : in real; -- estimated CW phase of in_dat
+ signal cw_dat : out integer; -- estimated CW
+ signal cw_noise : out real; -- estimated CW quantization noise
+ signal accum_noise_power : inout real; -- store noise power accumulator in signal
+ signal measured_noise_power : out real); -- measured noise power in in_dat
+
+ procedure proc_diag_measure_cw_noise_power(
+ constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
+ constant c_sub : in real;
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic;
+ signal in_val : in std_logic;
+ signal in_cnt : in natural;
+ signal cw_ampl : in real;
+ signal cw_phase : in real;
+ signal cw_dat : out integer;
+ signal cw_noise : out real;
+ signal accum_noise_power : inout real;
+ signal measured_noise_power : out real);
end tb_diag_pkg;
package body tb_diag_pkg is
- procedure proc_diag_seq_read_all(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal tx_miso : in t_mem_miso;
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso;
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ procedure proc_diag_seq_read_all(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal tx_miso : in t_mem_miso;
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso;
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
constant c_tx_offset : natural := c_stream * 2**c_diag_seq_tx_reg_adr_w;
constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
begin
@@ -251,17 +264,18 @@ package body tb_diag_pkg is
rd_reg.rx_sample <= rx_miso.rddata(c_word_w - 1 downto 0);
end proc_diag_seq_read_all;
- procedure proc_diag_seq_tx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
- constant c_tx_init : in natural;
- constant c_tx_mod : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ procedure proc_diag_seq_tx_enable(
+ constant c_stream : in natural;
+ constant c_pattern : in string; -- "PSRG", "CNTR"
+ constant c_tx_init : in natural;
+ constant c_tx_mod : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
constant c_tx_offset : natural := c_stream * 2**c_diag_seq_tx_reg_adr_w;
constant c_en : natural := 1;
variable v_sel : natural;
@@ -281,15 +295,16 @@ package body tb_diag_pkg is
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_tx_enable;
- procedure proc_diag_seq_rx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ procedure proc_diag_seq_rx_enable(
+ constant c_stream : in natural;
+ constant c_pattern : in string; -- "PSRG", "CNTR"
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
constant c_en : natural := 1;
variable v_sel : natural;
@@ -306,14 +321,15 @@ package body tb_diag_pkg is
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_rx_enable;
- procedure proc_diag_seq_tx_disable(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ procedure proc_diag_seq_tx_disable(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
constant c_tx_offset : natural := c_stream * 2**c_diag_seq_tx_reg_adr_w;
begin
proc_mem_mm_bus_wr(c_tx_offset + 0, 0, mm_clk, tx_miso, tx_mosi);
@@ -321,14 +337,15 @@ package body tb_diag_pkg is
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_tx_disable;
- procedure proc_diag_seq_rx_disable(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ procedure proc_diag_seq_rx_disable(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
begin
proc_mem_mm_bus_wr(c_rx_offset + 0, 0, mm_clk, rx_miso, rx_mosi);
@@ -336,15 +353,16 @@ package body tb_diag_pkg is
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_rx_disable;
- procedure proc_diag_seq_rx_write_steps(constant c_stream : in natural;
- constant c_steps_arr : in t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0);
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ procedure proc_diag_seq_rx_write_steps(
+ constant c_stream : in natural;
+ constant c_steps_arr : in t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0);
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
constant c_en : natural := 1;
variable v_sel : natural;
@@ -358,95 +376,96 @@ package body tb_diag_pkg is
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_rx_write_steps;
- procedure proc_diag_seq_verify(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal tx_miso : in t_mem_miso;
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso;
- signal rx_mosi : out t_mem_mosi;
- signal tb_mode : inout t_tb_diag_seq_mode_enum;
- signal tb_verify : out std_logic;
- signal rd_reg : inout t_diag_seq_mm_reg) is -- read all MM reg
- variable v_rx_stat : std_logic_vector(c_word_w - 1 downto 0);
- variable v_rx_sample : std_logic_vector(c_word_w - 1 downto 0);
- variable v_rx_cnt : natural;
- variable v_tx_cnt : natural;
+ procedure proc_diag_seq_verify(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal tx_miso : in t_mem_miso;
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso;
+ signal rx_mosi : out t_mem_mosi;
+ signal tb_mode : inout t_tb_diag_seq_mode_enum;
+ signal tb_verify : out std_logic;
+ signal rd_reg : inout t_diag_seq_mm_reg) is -- read all MM reg
+ variable v_rx_stat : std_logic_vector(c_word_w - 1 downto 0);
+ variable v_rx_sample : std_logic_vector(c_word_w - 1 downto 0);
+ variable v_rx_cnt : natural;
+ variable v_tx_cnt : natural;
begin
- -- Read all
- proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
- proc_common_wait_some_cycles(mm_clk, 1);
- v_rx_stat := rd_reg.rx_stat;
- v_rx_sample := rd_reg.rx_sample;
- v_rx_cnt := TO_UINT(rd_reg.rx_cnt);
- v_tx_cnt := TO_UINT(rd_reg.tx_cnt);
+ -- Read all
+ proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
+ proc_common_wait_some_cycles(mm_clk, 1);
+ v_rx_stat := rd_reg.rx_stat;
+ v_rx_sample := rd_reg.rx_sample;
+ v_rx_cnt := TO_UINT(rd_reg.rx_cnt);
+ v_tx_cnt := TO_UINT(rd_reg.tx_cnt);
+
+ -- Issue tb_verify pulse eg. to easy recognition in Wave window
+ tb_verify <= '1';
+ proc_common_wait_some_cycles(mm_clk, 1);
+ tb_verify <= '0';
+
+ -- Verify
+ if tb_mode = s_expect_ok then
+ if v_rx_stat(1) /= '0' then
+ report "Wrong diag result: no valid result." severity ERROR;
+ elsif v_rx_stat(0) /= '0' then
+ report "Wrong diag result: one or more data errors." severity ERROR;
+ end if;
- -- Issue tb_verify pulse eg. to easy recognition in Wave window
- tb_verify <= '1';
+ -- Read rx_cnt and tx_cnt again after some cycles
+ proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
proc_common_wait_some_cycles(mm_clk, 1);
- tb_verify <= '0';
-
- -- Verify
- if tb_mode = s_expect_ok then
- if v_rx_stat(1) /= '0' then
- report "Wrong diag result: no valid result." severity ERROR;
- elsif v_rx_stat(0) /= '0' then
- report "Wrong diag result: one or more data errors." severity ERROR;
- end if;
-
- -- Read rx_cnt and tx_cnt again after some cycles
- proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
- proc_common_wait_some_cycles(mm_clk, 1);
- if v_rx_cnt = 0 then
- report "Wrong diag result: rx_cnt = 0." severity ERROR;
- elsif v_rx_cnt >= TO_UINT(rd_reg.rx_cnt) then
- report "Wrong diag result: rx_cnt did not increase." severity ERROR;
- end if;
- if v_tx_cnt = 0 then
- report "Wrong diag result: tx_cnt = 0." severity ERROR;
- elsif v_tx_cnt >= TO_UINT(rd_reg.tx_cnt) then
- report "Wrong diag result: tx_cnt did not increase." severity ERROR;
- end if;
- -- Read rx_sample again after some cycles
- if unsigned(v_rx_sample) = 0 then
- report "Wrong diag sample: no valid sample." severity ERROR;
- elsif v_rx_sample = rd_reg.rx_sample then
- report "Wrong diag sample: sample did not change." severity ERROR;
- end if;
- elsif tb_mode = s_expect_error then
- if v_rx_stat(1) /= '0' then
- report "Wrong diag result: no valid result." severity ERROR;
- elsif v_rx_stat(0) /= '1' then
- report "Wrong diag result: must detect data errors." severity ERROR;
- end if;
- if v_rx_cnt = 0 then
- report "Wrong diag result: rx_cnt = 0." severity ERROR;
- end if;
- if v_tx_cnt = 0 then
- report "Wrong diag result: tx_cnt = 0." severity ERROR;
- end if;
- elsif tb_mode = s_expect_no_result then
- if v_rx_stat(1) /= '1' then
- report "Wrong diag result: must indicate no valid result." severity ERROR;
- end if;
- if v_rx_cnt /= 0 then
- report "Wrong diag result: rx_cnt /= 0." severity ERROR;
- end if;
- if unsigned(v_rx_sample) /= 0 then
- report "Wrong diag sample: rx_sample /= 0." severity ERROR;
- end if;
- elsif tb_mode = s_off then
- if v_rx_cnt /= 0 then
- report "Wrong diag result: rx_cnt /= 0." severity ERROR;
- end if;
- if v_tx_cnt /= 0 then
- report "Wrong diag result: tx_cnt /= 0." severity ERROR;
- end if;
- if unsigned(v_rx_sample) /= 0 then
- report "Wrong diag sample: rx_sample /= 0." severity ERROR;
- end if;
- else
- report "Unknown verify mode" severity FAILURE;
+ if v_rx_cnt = 0 then
+ report "Wrong diag result: rx_cnt = 0." severity ERROR;
+ elsif v_rx_cnt >= TO_UINT(rd_reg.rx_cnt) then
+ report "Wrong diag result: rx_cnt did not increase." severity ERROR;
+ end if;
+ if v_tx_cnt = 0 then
+ report "Wrong diag result: tx_cnt = 0." severity ERROR;
+ elsif v_tx_cnt >= TO_UINT(rd_reg.tx_cnt) then
+ report "Wrong diag result: tx_cnt did not increase." severity ERROR;
+ end if;
+ -- Read rx_sample again after some cycles
+ if unsigned(v_rx_sample) = 0 then
+ report "Wrong diag sample: no valid sample." severity ERROR;
+ elsif v_rx_sample = rd_reg.rx_sample then
+ report "Wrong diag sample: sample did not change." severity ERROR;
+ end if;
+ elsif tb_mode = s_expect_error then
+ if v_rx_stat(1) /= '0' then
+ report "Wrong diag result: no valid result." severity ERROR;
+ elsif v_rx_stat(0) /= '1' then
+ report "Wrong diag result: must detect data errors." severity ERROR;
+ end if;
+ if v_rx_cnt = 0 then
+ report "Wrong diag result: rx_cnt = 0." severity ERROR;
+ end if;
+ if v_tx_cnt = 0 then
+ report "Wrong diag result: tx_cnt = 0." severity ERROR;
+ end if;
+ elsif tb_mode = s_expect_no_result then
+ if v_rx_stat(1) /= '1' then
+ report "Wrong diag result: must indicate no valid result." severity ERROR;
+ end if;
+ if v_rx_cnt /= 0 then
+ report "Wrong diag result: rx_cnt /= 0." severity ERROR;
+ end if;
+ if unsigned(v_rx_sample) /= 0 then
+ report "Wrong diag sample: rx_sample /= 0." severity ERROR;
end if;
+ elsif tb_mode = s_off then
+ if v_rx_cnt /= 0 then
+ report "Wrong diag result: rx_cnt /= 0." severity ERROR;
+ end if;
+ if v_tx_cnt /= 0 then
+ report "Wrong diag result: tx_cnt /= 0." severity ERROR;
+ end if;
+ if unsigned(v_rx_sample) /= 0 then
+ report "Wrong diag sample: rx_sample /= 0." severity ERROR;
+ end if;
+ else
+ report "Unknown verify mode" severity FAILURE;
+ end if;
end proc_diag_seq_verify;
---------------------------------------------------------------------------
@@ -459,46 +478,47 @@ package body tb_diag_pkg is
-- measure DC.
-- . accumulate samples during interval and calculate effective amplitude.
---------------------------------------------------------------------------
- procedure proc_diag_measure_cw_statistics(constant c_nof_samples : in natural; -- number of samples per in_start interval
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal track_max : inout real; -- store local tracker in signal
- signal track_min : inout real; -- store local tracker in signal
- signal accum_mean : inout real; -- store local accumulator in signal
- signal accum_power : inout real; -- store local accumulator in signal
- signal measured_max : out real; -- maximum sample value
- signal measured_min : out real; -- minimum sample value
- signal measured_mean : out real; -- average sample value (DC)
- signal measured_power : out real; -- average sample power
- signal measured_ampl : out real) is -- corresponding sine amplitude
+ procedure proc_diag_measure_cw_statistics(
+ constant c_nof_samples : in natural; -- number of samples per in_start interval
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal track_max : inout real; -- store local tracker in signal
+ signal track_min : inout real; -- store local tracker in signal
+ signal accum_mean : inout real; -- store local accumulator in signal
+ signal accum_power : inout real; -- store local accumulator in signal
+ signal measured_max : out real; -- maximum sample value
+ signal measured_min : out real; -- minimum sample value
+ signal measured_mean : out real; -- average sample value (DC)
+ signal measured_power : out real; -- average sample power
+ signal measured_ampl : out real) is -- corresponding sine amplitude
constant c_Nsamples : real := real(c_nof_samples);
constant c_dat : real := real(TO_SINT(in_dat));
constant c_mean : real := accum_mean / c_Nsamples;
constant c_power : real := accum_power / c_Nsamples;
constant c_ampl : real := SQRT(c_power * 2.0);
begin
- if rising_edge(dp_clk) then
- if in_start = '1' then
- -- Hold last interval max, min and accumulation
- measured_max <= track_max;
- measured_min <= track_min;
- measured_power <= c_power;
- measured_ampl <= c_ampl;
- -- Start new interval accumulation
- track_max <= real'low;
- track_min <= real'high;
- accum_mean <= c_dat;
- accum_power <= (abs(c_dat))**2.0; -- Must use ABS() with ** of real, because (negative)**2.0 yields error and value 0.0, also must use brackets (ABS()) to avoid compile error
- elsif in_val = '1' then
- -- Detect and accumulate during interval
- track_max <= largest(track_max, c_dat);
- track_min <= smallest(track_min, c_dat);
- accum_mean <= accum_mean + c_dat;
- accum_power <= accum_power + (abs(c_dat))**2.0;
- end if;
+ if rising_edge(dp_clk) then
+ if in_start = '1' then
+ -- Hold last interval max, min and accumulation
+ measured_max <= track_max;
+ measured_min <= track_min;
+ measured_power <= c_power;
+ measured_ampl <= c_ampl;
+ -- Start new interval accumulation
+ track_max <= real'low;
+ track_min <= real'high;
+ accum_mean <= c_dat;
+ accum_power <= (abs(c_dat))**2.0; -- Must use ABS() with ** of real, because (negative)**2.0 yields error and value 0.0, also must use brackets (ABS()) to avoid compile error
+ elsif in_val = '1' then
+ -- Detect and accumulate during interval
+ track_max <= largest(track_max, c_dat);
+ track_min <= smallest(track_min, c_dat);
+ accum_mean <= accum_mean + c_dat;
+ accum_power <= accum_power + (abs(c_dat))**2.0;
end if;
+ end if;
end proc_diag_measure_cw_statistics;
---------------------------------------------------------------------------
@@ -539,21 +559,22 @@ package body tb_diag_pkg is
-- . the sine power of the perfect reference CW (carrier wave) is:
-- cwPower = (A**2)/2
---------------------------------------------------------------------------
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_nof_samples : in natural; -- number of samples per in_start interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal ref_I : out real; -- output local I as signal for debugging in wave window
- signal ref_Q : out real; -- output local Q as signal for debugging in wave window
- signal accum_I : inout real; -- store local I accumulator in signal
- signal accum_Q : inout real; -- store local Q accumulator in signal
- signal measured_ampl : out real; -- measured CW amplitude
- signal measured_phase : out real; -- measured CW phase in radials
- signal measured_phase_Ts : out real) is -- measured CW phase in sample periods
+ procedure proc_diag_measure_cw_ampl_and_phase(
+ constant c_nof_samples : in natural; -- number of samples per in_start interval
+ constant c_fft_size : in natural; -- number of points of FFT
+ constant c_sub : in real; -- subband index
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal in_cnt : in natural; -- sample index in c_fft_size
+ signal ref_I : out real; -- output local I as signal for debugging in wave window
+ signal ref_Q : out real; -- output local Q as signal for debugging in wave window
+ signal accum_I : inout real; -- store local I accumulator in signal
+ signal accum_Q : inout real; -- store local Q accumulator in signal
+ signal measured_ampl : out real; -- measured CW amplitude
+ signal measured_phase : out real; -- measured CW phase in radials
+ signal measured_phase_Ts : out real) is -- measured CW phase in sample periods
constant c_Nsamples : real := real(c_nof_samples);
constant c_Nfft : real := real(c_fft_size);
constant c_omega : real := MATH_2_PI * c_sub / c_Nfft;
@@ -588,25 +609,26 @@ package body tb_diag_pkg is
end if;
end proc_diag_measure_cw_ampl_and_phase;
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
- constant c_sub : in real;
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic;
- signal in_val : in std_logic;
- signal in_cnt : in natural;
- signal ref_I : out real;
- signal ref_Q : out real;
- signal accum_I : inout real;
- signal accum_Q : inout real;
- signal measured_ampl : out real;
- signal measured_phase : out real;
- signal measured_phase_Ts : out real) is
+ procedure proc_diag_measure_cw_ampl_and_phase(
+ constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
+ constant c_sub : in real;
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic;
+ signal in_val : in std_logic;
+ signal in_cnt : in natural;
+ signal ref_I : out real;
+ signal ref_Q : out real;
+ signal accum_I : inout real;
+ signal accum_Q : inout real;
+ signal measured_ampl : out real;
+ signal measured_phase : out real;
+ signal measured_phase_Ts : out real) is
begin
proc_diag_measure_cw_ampl_and_phase(c_fft_size, c_fft_size, c_sub, dp_clk,
- in_dat, in_start, in_val, in_cnt,
- ref_I, ref_Q, accum_I, accum_Q,
- measured_ampl, measured_phase, measured_phase_Ts);
+ in_dat, in_start, in_val, in_cnt,
+ ref_I, ref_Q, accum_I, accum_Q,
+ measured_ampl, measured_phase, measured_phase_Ts);
end proc_diag_measure_cw_ampl_and_phase;
---------------------------------------------------------------------------
@@ -629,20 +651,21 @@ package body tb_diag_pkg is
--
-- SNR = 10*log10(cwPower / noisePower) [dB]
---------------------------------------------------------------------------
- procedure proc_diag_measure_cw_noise_power(constant c_nof_samples : in natural; -- number of samples per integration interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal cw_ampl : in real; -- estimated CW amplitude of in_dat
- signal cw_phase : in real; -- estimated CW phase of in_dat
- signal cw_dat : out integer; -- estimated CW
- signal cw_noise : out real; -- estimated CW quantization noise
- signal accum_noise_power : inout real; -- store noise power accumulator in signal
- signal measured_noise_power : out real) is -- measured noise power in in_dat
+ procedure proc_diag_measure_cw_noise_power(
+ constant c_nof_samples : in natural; -- number of samples per integration interval
+ constant c_fft_size : in natural; -- number of points of FFT
+ constant c_sub : in real; -- subband index
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal in_cnt : in natural; -- sample index in c_fft_size
+ signal cw_ampl : in real; -- estimated CW amplitude of in_dat
+ signal cw_phase : in real; -- estimated CW phase of in_dat
+ signal cw_dat : out integer; -- estimated CW
+ signal cw_noise : out real; -- estimated CW quantization noise
+ signal accum_noise_power : inout real; -- store noise power accumulator in signal
+ signal measured_noise_power : out real) is -- measured noise power in in_dat
constant c_Nsamples : real := real(c_nof_samples);
constant c_Nfft : real := real(c_fft_size);
constant c_omega : real := MATH_2_PI * c_sub / c_Nfft;
@@ -671,24 +694,25 @@ package body tb_diag_pkg is
end if;
end proc_diag_measure_cw_noise_power;
- procedure proc_diag_measure_cw_noise_power(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
- constant c_sub : in real;
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic;
- signal in_val : in std_logic;
- signal in_cnt : in natural;
- signal cw_ampl : in real;
- signal cw_phase : in real;
- signal cw_dat : out integer;
- signal cw_noise : out real;
- signal accum_noise_power : inout real;
- signal measured_noise_power : out real) is
+ procedure proc_diag_measure_cw_noise_power(
+ constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
+ constant c_sub : in real;
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic;
+ signal in_val : in std_logic;
+ signal in_cnt : in natural;
+ signal cw_ampl : in real;
+ signal cw_phase : in real;
+ signal cw_dat : out integer;
+ signal cw_noise : out real;
+ signal accum_noise_power : inout real;
+ signal measured_noise_power : out real) is
begin
proc_diag_measure_cw_noise_power(c_fft_size, c_fft_size, c_sub, dp_clk,
- in_dat, in_start, in_val, in_cnt,
- cw_ampl, cw_phase, cw_dat, cw_noise,
- accum_noise_power, measured_noise_power);
+ in_dat, in_start, in_val, in_cnt,
+ cw_ampl, cw_phase, cw_dat, cw_noise,
+ accum_noise_power, measured_noise_power);
end proc_diag_measure_cw_noise_power;
end tb_diag_pkg;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd b/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd
index e34799d1dc..546d2f36b1 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd
@@ -29,7 +29,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_diag_regression is
end tb_diag_regression;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
index 35316f212a..e713af9c17 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
@@ -21,21 +21,21 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.diag_pkg.all;
--- Purpose: test bench for diag_rx_seq control
--- Usage:
--- > as 5
--- > run -all
--- . default should run OK i.e. no mismatches reported
--- . force errors by briefly using different tx sequence at the end of the
--- stimuli process, these mismatches are reported
--- Remarks:
--- . The tb can verify rx_steps other than +1 by using g_tx_cnt_incr, it can
--- only verify one of the c_diag_seq_rx_reg_nof_steps at a time.
+ -- Purpose: test bench for diag_rx_seq control
+ -- Usage:
+ -- > as 5
+ -- > run -all
+ -- . default should run OK i.e. no mismatches reported
+ -- . force errors by briefly using different tx sequence at the end of the
+ -- stimuli process, these mismatches are reported
+ -- Remarks:
+ -- . The tb can verify rx_steps other than +1 by using g_tx_cnt_incr, it can
+ -- only verify one of the c_diag_seq_rx_reg_nof_steps at a time.
entity tb_diag_rx_seq is
generic (
@@ -83,7 +83,7 @@ begin
clk <= not clk or tb_end after c_period / 2;
stimuli: process
- -- run 100 us
+ -- run 100 us
begin
tx_diag_en <= '0';
rx_diag_en <= '0';
@@ -254,39 +254,39 @@ begin
end process;
u_diag_tx_seq : entity work.diag_tx_seq
- generic map (
- g_cnt_incr => g_tx_cnt_incr,
- g_dat_w => g_seq_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- diag_en => tx_diag_en,
- diag_sel => tx_diag_sel,
- diag_mod => tx_diag_mod,
- diag_req => tx_diag_req,
- out_dat => seq_dat,
- out_val => seq_val
- );
+ generic map (
+ g_cnt_incr => g_tx_cnt_incr,
+ g_dat_w => g_seq_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ diag_en => tx_diag_en,
+ diag_sel => tx_diag_sel,
+ diag_mod => tx_diag_mod,
+ diag_req => tx_diag_req,
+ out_dat => seq_dat,
+ out_val => seq_val
+ );
u_diag_rx_seq : entity work.diag_rx_seq
- generic map (
- g_use_steps => g_rx_use_steps,
- g_nof_steps => c_rx_nof_steps,
- g_dat_w => g_seq_dat_w,
- g_diag_res_w => c_diag_res_w
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => seq_dat,
- in_val => seq_val,
- diag_en => rx_diag_en,
- diag_sel => rx_diag_sel,
- diag_steps_arr => rx_diag_steps_arr,
- diag_res => diag_res,
- diag_res_val => diag_res_val
- );
+ generic map (
+ g_use_steps => g_rx_use_steps,
+ g_nof_steps => c_rx_nof_steps,
+ g_dat_w => g_seq_dat_w,
+ g_diag_res_w => c_diag_res_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => seq_dat,
+ in_val => seq_val,
+ diag_en => rx_diag_en,
+ diag_sel => rx_diag_sel,
+ diag_steps_arr => rx_diag_steps_arr,
+ diag_res => diag_res,
+ diag_res_val => diag_res_val
+ );
p_report : process (clk)
begin
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd b/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
index d526a763f0..945144ec22 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
@@ -21,9 +21,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_diag_tx_frm is
end tb_diag_tx_frm;
@@ -58,7 +58,7 @@ begin
clk <= not clk after c_period / 2;
stimuli: process
- -- run 100 us
+ -- run 100 us
begin
diag_sel <= c_sel;
diag_init <= TO_UVEC(c_init, c_dat_w);
@@ -153,30 +153,30 @@ begin
end process;
u_diag_tx_frm : entity work.diag_tx_frm
- generic map (
- g_sel => c_sel,
- g_init => c_init,
- g_frame_len => c_frame_len,
- g_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- -- Static control input (connect via MM or leave open to use default)
- diag_sel => diag_sel,
- diag_frame_len => diag_frame_len,
- -- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
- diag_ready => diag_ready,
- diag_init => diag_init,
- diag_sop => diag_sop,
- -- ST output
- out_ready => seq_req,
- out_dat => seq_dat,
- out_val => seq_val,
- out_sop => seq_sop,
- out_eop => seq_eop
- );
+ generic map (
+ g_sel => c_sel,
+ g_init => c_init,
+ g_frame_len => c_frame_len,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ -- Static control input (connect via MM or leave open to use default)
+ diag_sel => diag_sel,
+ diag_frame_len => diag_frame_len,
+ -- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
+ diag_ready => diag_ready,
+ diag_init => diag_init,
+ diag_sop => diag_sop,
+ -- ST output
+ out_ready => seq_req,
+ out_dat => seq_dat,
+ out_val => seq_val,
+ out_sop => seq_sop,
+ out_eop => seq_eop
+ );
prev_seq_dat <= seq_dat when rising_edge(clk) and seq_val = '1';
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
index a172bb172d..f032802778 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
@@ -26,9 +26,9 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_diag_tx_seq is
end tb_diag_tx_seq;
@@ -104,16 +104,16 @@ begin
end process;
u_diag_tx_seq : entity work.diag_tx_seq
- generic map (
- g_dat_w => c_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- diag_en => diag_en,
- diag_sel => diag_sel,
- diag_req => diag_req,
- out_dat => seq_dat,
- out_val => seq_val
- );
+ generic map (
+ g_dat_w => c_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ diag_en => diag_en,
+ diag_sel => diag_sel,
+ diag_req => diag_req,
+ out_dat => seq_dat,
+ out_val => seq_val
+ );
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
index db0f7c42fe..ce0a62787e 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
@@ -21,20 +21,20 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-
--- Usage:
--- > do wave_diag_wg_wideband.do
--- > run -all
---
--- . Use select rigth mouse in wave window on wg_dat and choose 'format --> analogue (automatic)'
--- . run 10 us to see CALC mode waveform output at proper automatic scale
--- . run 100 us to see SINGLE and REPEAT mode waveform output at proper automatic scale
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+
+ -- Usage:
+ -- > do wave_diag_wg_wideband.do
+ -- > run -all
+ --
+ -- . Use select rigth mouse in wave window on wg_dat and choose 'format --> analogue (automatic)'
+ -- . run 10 us to see CALC mode waveform output at proper automatic scale
+ -- . run 100 us to see SINGLE and REPEAT mode waveform output at proper automatic scale
entity tb_diag_wg is
generic (
@@ -49,19 +49,21 @@ architecture tb of tb_diag_wg is
constant c_clk_period : time := (10**9 / c_clk_freq) * 1 ns;
-- Default settings
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => g_buf_adr_w,
- dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
- nof_dat => 2**g_buf_adr_w, -- = 2**adr_w
- init_sl => '0');
- constant c_buf_file : string := sel_a_b(c_buf.adr_w = 11 and c_buf.dat_w = 18, "data/diag_sin_2048x18.hex",
- sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, "data/diag_sin_1024x18.hex",
- sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 8, "data/diag_sin_1024x8.hex", "UNUSED")));
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => g_buf_adr_w,
+ dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
+ nof_dat => 2**g_buf_adr_w, -- = 2**adr_w
+ init_sl => '0');
+ constant c_buf_file : string := sel_a_b(
+ c_buf.adr_w = 11 and c_buf.dat_w = 18, "data/diag_sin_2048x18.hex",
+ sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, "data/diag_sin_1024x18.hex",
+ sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 8, "data/diag_sin_1024x8.hex", "UNUSED")));
constant c_wg_nof_samples : natural := c_buf.nof_dat; -- must be <= c_buf.nof_dat
constant c_wg_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
- -- . use gain 2**0 = 1 to have fulle scale without clipping
- -- . use gain 2**g_calc_gain_w > 1 to cause clipping
+ -- . use gain 2**0 = 1 to have fulle scale without clipping
+ -- . use gain 2**g_calc_gain_w > 1 to cause clipping
constant c_buf_full_scale : natural := 2**(g_buf_dat_w - 1) - 1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
constant c_wg_full_scale : natural := 2**(g_wg_dat_w - 1) - 1;
@@ -118,13 +120,13 @@ begin
-- >>> CALC mode
-- Cosinus with frequency Fs/2 (note sinus Fs/2 yields DC = 0)
--- wg_freq <= INTEGER(0.5 * c_freq_unit);
--- wg_phase <= INTEGER(90.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(0.5 * c_freq_unit);
+ -- wg_phase <= INTEGER(90.0 * c_phase_unit);
-- Choosing 1.0*Fs to select Fs which is equivalent to DC, hence the DC value is then determined by phase
-- this also applies to 2.0, 3.0, 4.0 etc
--- wg_freq <= INTEGER(1.0 * c_freq_unit);
--- wg_phase <= INTEGER(45.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(1.0 * c_freq_unit);
+ -- wg_phase <= INTEGER(45.0 * c_phase_unit);
-- Sinus Fs/16
wg_freq <= integer(0.0625 * c_freq_unit);
@@ -134,12 +136,12 @@ begin
wg_phase <= integer(0.0 * c_phase_unit);
-- Sinus Fs/17
--- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
--- wg_phase <= INTEGER(0.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
+ -- wg_phase <= INTEGER(0.0 * c_phase_unit);
wg_ampl <= integer(1.0 * c_ampl_unit); -- yields amplitude of c_wg_full_scale
--- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
--- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
+ -- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
+ -- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
wait until rising_edge(clk); -- align to rising edge
wait for c_clk_period * 200;
@@ -203,53 +205,53 @@ begin
-- Waveform buffer
u_buf : entity common_lib.common_ram_crw_crw
- generic map (
- g_ram => c_buf,
- g_init_file => c_buf_file
- )
- port map (
- rst_a => '0',
- rst_b => '0',
- clk_a => clk,
- clk_b => clk,
- wr_en_a => '0',
- wr_en_b => '0',
- wr_dat_a => (others => '0'),
- wr_dat_b => (others => '0'),
- adr_a => (others => '0'),
- adr_b => buf_addr,
- rd_en_a => '0',
- rd_en_b => buf_rden,
- rd_dat_a => OPEN,
- rd_dat_b => buf_rddat,
- rd_val_a => OPEN,
- rd_val_b => buf_rdval
- );
+ generic map (
+ g_ram => c_buf,
+ g_init_file => c_buf_file
+ )
+ port map (
+ rst_a => '0',
+ rst_b => '0',
+ clk_a => clk,
+ clk_b => clk,
+ wr_en_a => '0',
+ wr_en_b => '0',
+ wr_dat_a => (others => '0'),
+ wr_dat_b => (others => '0'),
+ adr_a => (others => '0'),
+ adr_b => buf_addr,
+ rd_en_a => '0',
+ rd_en_b => buf_rden,
+ rd_dat_a => OPEN,
+ rd_dat_b => buf_rddat,
+ rd_val_a => OPEN,
+ rd_val_b => buf_rdval
+ );
-- Waveform generator
u_wg : entity work.diag_wg
- generic map (
- g_buf_dat_w => c_buf.dat_w,
- g_buf_addr_w => c_buf.adr_w,
- g_calc_support => true,
- g_calc_gain_w => c_wg_gain_w,
- g_calc_dat_w => g_wg_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- restart => restart,
-
- buf_rddat => buf_rddat,
- buf_rdval => buf_rdval,
- buf_addr => buf_addr,
- buf_rden => buf_rden,
-
- ctrl => wg_ctrl,
-
- out_ovr => wg_ovr,
- out_dat => wg_dat,
- out_val => wg_val,
- out_sync => wg_sync
- );
+ generic map (
+ g_buf_dat_w => c_buf.dat_w,
+ g_buf_addr_w => c_buf.adr_w,
+ g_calc_support => true,
+ g_calc_gain_w => c_wg_gain_w,
+ g_calc_dat_w => g_wg_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ restart => restart,
+
+ buf_rddat => buf_rddat,
+ buf_rdval => buf_rdval,
+ buf_addr => buf_addr,
+ buf_rden => buf_rden,
+
+ ctrl => wg_ctrl,
+
+ out_ovr => wg_ovr,
+ out_dat => wg_dat,
+ out_val => wg_val,
+ out_sync => wg_sync
+ );
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
index 8521629f7d..17ca2becd7 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
@@ -29,17 +29,17 @@
-- . Observe state in diag_wg(0).
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use work.diag_pkg.all;
entity tb_diag_wg_wideband is
generic (
-- Wideband parameters
g_wideband_factor : natural := 4; -- Wideband rate factor >= 1 for unit frequency of g_wideband_factor * Fs
- -- Take care that the g_wideband_factor and c_clk_freq match the simulation time resolution of integer 1 ps
+ -- Take care that the g_wideband_factor and c_clk_freq match the simulation time resolution of integer 1 ps
-- Basic WG parameters, see diag_wg.vhd for their meaning
g_buf_addr_w : natural := 10;
g_buf_dat_w : natural := 8;
@@ -55,8 +55,8 @@ architecture tb of tb_diag_wg_wideband is
constant c_buf_nof_dat : natural := 2**g_buf_addr_w;
constant c_wg_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
- -- . use gain 2**0 = 1 to have fulle scale without clipping
- -- . use gain 2**g_calc_gain_w > 1 to cause clipping
+ -- . use gain 2**0 = 1 to have fulle scale without clipping
+ -- . use gain 2**g_calc_gain_w > 1 to cause clipping
constant c_buf_full_scale : natural := 2**(g_buf_dat_w - 1) - 1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
constant c_wg_full_scale : natural := 2**(g_wg_dat_w - 1) - 1;
@@ -130,13 +130,13 @@ begin
-- >>> CALC mode
-- Cosinus with frequency Fs/2 (note sinus Fs/2 yields DC = 0)
--- wg_freq <= INTEGER(0.5 * c_freq_unit);
--- wg_phase <= INTEGER(90.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(0.5 * c_freq_unit);
+ -- wg_phase <= INTEGER(90.0 * c_phase_unit);
-- Choosing 1.0*Fs to select Fs which is equivalent to DC, hence the DC value is then determined by phase
-- this also applies to 2.0, 3.0, 4.0 etc
--- wg_freq <= INTEGER(1.0 * c_freq_unit);
--- wg_phase <= INTEGER(45.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(1.0 * c_freq_unit);
+ -- wg_phase <= INTEGER(45.0 * c_phase_unit);
-- Sinus Fs/16
wg_freq <= integer(0.0625 * c_freq_unit);
@@ -146,12 +146,12 @@ begin
wg_phase <= integer(0.0 * c_phase_unit);
-- Sinus Fs/17
--- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
--- wg_phase <= INTEGER(0.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
+ -- wg_phase <= INTEGER(0.0 * c_phase_unit);
wg_ampl <= integer(1.0 * c_ampl_unit); -- yields amplitude of c_wg_full_scale
--- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
--- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
+ -- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
+ -- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
wait until rising_edge(clk); -- align to rising edge
cur_ctrl <= wg_ctrl;
@@ -261,41 +261,41 @@ begin
end process;
u_wideband_wg : entity work.diag_wg_wideband
- generic map (
- -- Wideband parameters
- g_wideband_factor => g_wideband_factor,
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w,
- g_calc_support => true,
- g_calc_gain_w => c_wg_gain_w,
- g_calc_dat_w => g_wg_dat_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => '0',
- mm_clk => '0',
-
- mm_wrdata => (others => '0'),
- mm_address => (others => '0'),
- mm_wr => '0',
- mm_rd => '0',
- mm_rdval => OPEN,
- mm_rddata => OPEN,
-
- -- Streaming clock domain
- st_rst => rst,
- st_clk => clk,
- st_restart => restart,
-
- st_ctrl => wg_ctrl,
- st_mon_ctrl => mon_ctrl,
-
- out_ovr => out_ovr,
- out_dat => out_dat,
- out_val => out_val,
- out_sync => out_sync
- );
+ generic map (
+ -- Wideband parameters
+ g_wideband_factor => g_wideband_factor,
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w,
+ g_calc_support => true,
+ g_calc_gain_w => c_wg_gain_w,
+ g_calc_dat_w => g_wg_dat_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => '0',
+ mm_clk => '0',
+
+ mm_wrdata => (others => '0'),
+ mm_address => (others => '0'),
+ mm_wr => '0',
+ mm_rd => '0',
+ mm_rdval => OPEN,
+ mm_rddata => OPEN,
+
+ -- Streaming clock domain
+ st_rst => rst,
+ st_clk => clk,
+ st_restart => restart,
+
+ st_ctrl => wg_ctrl,
+ st_mon_ctrl => mon_ctrl,
+
+ out_ovr => out_ovr,
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sync => out_sync
+ );
-- Map wideband WG out_* slv to wg_* arrays to ease interpretation in wave window
gen_wires : for I in 0 to g_wideband_factor - 1 generate
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
index f18f50f775..1fe5505bed 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
@@ -27,17 +27,17 @@
-- Observe tb_state and check the out_sosi_0 fields if data is OK.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use std.textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use std.textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.diag_pkg.all;
entity tb_mms_diag_block_gen is
generic (
@@ -212,24 +212,24 @@ begin
-- User input modelled by another BG
-------------------------------------------------
u_user : entity work.mms_diag_block_gen
- generic map (
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => c_buf_dat_w,
- g_buf_addr_w => c_buf_addr_w,
- g_file_name_prefix => c_file_name_prefix,
- g_diag_block_gen_rst => c_diag_block_gen_enabled -- user BG is default enabled
- )
- port map (
- -- System
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
- en_sync => '0',
- -- ST interface
- out_siso_arr => usr_src_in_arr,
- out_sosi_arr => usr_src_out_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => c_buf_dat_w,
+ g_buf_addr_w => c_buf_addr_w,
+ g_file_name_prefix => c_file_name_prefix,
+ g_diag_block_gen_rst => c_diag_block_gen_enabled -- user BG is default enabled
+ )
+ port map (
+ -- System
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+ en_sync => '0',
+ -- ST interface
+ out_siso_arr => usr_src_in_arr,
+ out_sosi_arr => usr_src_out_arr
+ );
-- Use sufficiently large FIFO to provide siso.ready flow control to the user input
no_user_fifo : if c_use_user_fifo = false generate
@@ -240,37 +240,37 @@ begin
gen_user_fifo : if c_use_user_fifo = true generate
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_user_fifo : entity dp_lib.dp_fifo_sc
- generic map (
- g_data_w => c_buf_dat_w,
- g_bsn_w => c_dp_stream_bsn_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_error => true,
- g_use_sync => true,
- g_use_ctrl => true,
- g_use_complex => false,
- g_fifo_size => c_usr_fifo_size,
- g_fifo_af_margin => 4,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor FIFO filling
- wr_ful => OPEN,
- usedw => OPEN,
- rd_emp => OPEN,
- -- ST sink
- snk_out => usr_src_in_arr(I),
- snk_in => usr_src_out_arr(I),
- -- ST source
- src_in => usr_fifo_src_in_arr(I),
- src_out => usr_fifo_src_out_arr(I)
- );
+ generic map (
+ g_data_w => c_buf_dat_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_error_w => c_dp_stream_error_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ g_use_ctrl => true,
+ g_use_complex => false,
+ g_fifo_size => c_usr_fifo_size,
+ g_fifo_af_margin => 4,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => OPEN,
+ usedw => OPEN,
+ rd_emp => OPEN,
+ -- ST sink
+ snk_out => usr_src_in_arr(I),
+ snk_in => usr_src_out_arr(I),
+ -- ST source
+ src_in => usr_fifo_src_in_arr(I),
+ src_out => usr_fifo_src_out_arr(I)
+ );
end generate;
end generate;
@@ -299,44 +299,44 @@ begin
-- Device under test
-------------------------------------------------
u_dut : entity work.mms_diag_block_gen
- generic map (
- -- Generate configurations
- g_use_usr_input => g_use_usr_input,
- g_use_bg => g_use_bg,
- g_use_tx_seq => g_use_tx_seq,
- -- General
- g_nof_streams => g_nof_streams,
- -- BG settings
- g_use_bg_buffer_ram => g_use_bg_buffer_ram,
- g_buf_dat_w => c_buf_dat_w,
- g_buf_addr_w => c_buf_addr_w,
- g_file_name_prefix => c_file_name_prefix,
- g_diag_block_gen_rst => c_diag_block_gen_rst, -- user BG is default disabled, MM controlled by p_dut_bg_ctrl
- -- User input multiplexer option
- g_usr_bypass_xonoff => g_usr_bypass_xonoff,
- -- Tx_seq
- g_seq_dat_w => c_buf_dat_w -- >= 1, test sequence data width. Choose g_seq_dat_w <= g_buf_dat_w
- )
- port map (
- -- System
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
- en_sync => en_sync,
- -- MM interface
- ram_bg_data_mosi => ram_bg_data_mosi,
- ram_bg_data_miso => ram_bg_data_miso,
- reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
- reg_bg_ctrl_miso => reg_bg_ctrl_miso,
- reg_tx_seq_mosi => reg_tx_seq_mosi,
- reg_tx_seq_miso => reg_tx_seq_miso,
- -- ST interface
- usr_siso_arr => usr_fifo_src_in_arr,
- usr_sosi_arr => usr_fifo_src_out_arr,
- out_siso_arr => out_siso_arr,
- out_sosi_arr => out_sosi_arr
- );
+ generic map (
+ -- Generate configurations
+ g_use_usr_input => g_use_usr_input,
+ g_use_bg => g_use_bg,
+ g_use_tx_seq => g_use_tx_seq,
+ -- General
+ g_nof_streams => g_nof_streams,
+ -- BG settings
+ g_use_bg_buffer_ram => g_use_bg_buffer_ram,
+ g_buf_dat_w => c_buf_dat_w,
+ g_buf_addr_w => c_buf_addr_w,
+ g_file_name_prefix => c_file_name_prefix,
+ g_diag_block_gen_rst => c_diag_block_gen_rst, -- user BG is default disabled, MM controlled by p_dut_bg_ctrl
+ -- User input multiplexer option
+ g_usr_bypass_xonoff => g_usr_bypass_xonoff,
+ -- Tx_seq
+ g_seq_dat_w => c_buf_dat_w -- >= 1, test sequence data width. Choose g_seq_dat_w <= g_buf_dat_w
+ )
+ port map (
+ -- System
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+ en_sync => en_sync,
+ -- MM interface
+ ram_bg_data_mosi => ram_bg_data_mosi,
+ ram_bg_data_miso => ram_bg_data_miso,
+ reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
+ reg_bg_ctrl_miso => reg_bg_ctrl_miso,
+ reg_tx_seq_mosi => reg_tx_seq_mosi,
+ reg_tx_seq_miso => reg_tx_seq_miso,
+ -- ST interface
+ usr_siso_arr => usr_fifo_src_in_arr,
+ usr_sosi_arr => usr_fifo_src_out_arr,
+ out_siso_arr => out_siso_arr,
+ out_sosi_arr => out_sosi_arr
+ );
-------------------------------------------------
-- Verification
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
index 57222de7e0..f174e0bd57 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
@@ -27,17 +27,17 @@
-- > run -all
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.diag_pkg.all;
-use work.tb_diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.diag_pkg.all;
+ use work.tb_diag_pkg.all;
entity tb_mms_diag_seq is
generic (
@@ -274,66 +274,66 @@ begin
for I in 1 to g_nof_streams - 1 loop
if v_snk_in /= rx_snk_in_arr(I) then
report "Wrong diag result: for g_mm_broadcast_tx=TRUE all streams should carry the same data." severity ERROR;
- exit;
+ exit;
+ end if;
+ end loop;
end if;
- end loop;
- end if;
- end process;
-
- u_mms_diag_tx_seq: entity WORK.mms_diag_tx_seq
- generic map(
- g_mm_broadcast => g_mm_broadcast_tx,
- g_nof_streams => g_nof_streams,
- g_seq_dat_w => g_seq_dat_w
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- reg_mosi => reg_tx_mosi,
- reg_miso => reg_tx_miso,
-
- -- DP streaming interface
- tx_src_out_arr => tx_src_out_arr,
- tx_src_in_arr => tx_src_in_arr
- );
-
- u_mms_diag_rx_seq: entity WORK.mms_diag_rx_seq
- generic map(
- g_nof_streams => g_nof_streams,
- g_use_steps => g_use_steps,
- g_seq_dat_w => g_seq_dat_w,
- g_data_w => g_data_w
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- reg_mosi => reg_rx_mosi,
- reg_miso => reg_rx_miso,
-
- -- DP streaming interface
- rx_snk_in_arr => rx_snk_in_arr
- );
-
- p_connect : process(tx_src_out_arr, force_low_error, force_replicate_error)
- begin
- -- Default lopoback all streams
- rx_snk_in_arr <= tx_src_out_arr;
- -- Optionally apply errors on stream 0
- if force_low_error = '1' then
- rx_snk_in_arr(0).data(0) <= not tx_src_out_arr(0).data(0);
- end if;
- if force_replicate_error = '1' then
- rx_snk_in_arr(0).data(g_seq_dat_w) <= not tx_src_out_arr(0).data(g_seq_dat_w);
- end if;
- end process;
-end architecture str;
+ end process;
+
+ u_mms_diag_tx_seq: entity WORK.mms_diag_tx_seq
+ generic map(
+ g_mm_broadcast => g_mm_broadcast_tx,
+ g_nof_streams => g_nof_streams,
+ g_seq_dat_w => g_seq_dat_w
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ reg_mosi => reg_tx_mosi,
+ reg_miso => reg_tx_miso,
+
+ -- DP streaming interface
+ tx_src_out_arr => tx_src_out_arr,
+ tx_src_in_arr => tx_src_in_arr
+ );
+
+ u_mms_diag_rx_seq: entity WORK.mms_diag_rx_seq
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_use_steps => g_use_steps,
+ g_seq_dat_w => g_seq_dat_w,
+ g_data_w => g_data_w
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ reg_mosi => reg_rx_mosi,
+ reg_miso => reg_rx_miso,
+
+ -- DP streaming interface
+ rx_snk_in_arr => rx_snk_in_arr
+ );
+
+ p_connect : process(tx_src_out_arr, force_low_error, force_replicate_error)
+ begin
+ -- Default lopoback all streams
+ rx_snk_in_arr <= tx_src_out_arr;
+ -- Optionally apply errors on stream 0
+ if force_low_error = '1' then
+ rx_snk_in_arr(0).data(0) <= not tx_src_out_arr(0).data(0);
+ end if;
+ if force_replicate_error = '1' then
+ rx_snk_in_arr(0).data(g_seq_dat_w) <= not tx_src_out_arr(0).data(g_seq_dat_w);
+ end if;
+ end process;
+ end architecture str;
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
index 6417e9d67f..529803a62c 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
@@ -29,8 +29,8 @@
-- > run -all
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_tb_diag_block_gen is
end tb_tb_diag_block_gen;
@@ -47,7 +47,7 @@ begin
-- g_buf_adr_w : NATURAL := 7; -- Waveform buffer address width (requires corresponding c_buf_file)
-- g_buf_dat_w : NATURAL := 32 -- Waveform buffer stored data width (requires corresponding c_buf_file)
-- g_try_phasor : BOOLEAN := FALSE -- use TRUE to see BG phasor in wave window with out_sosi.re/im in radix
- -- decimal and analogue format, no self test
+ -- decimal and analogue format, no self test
u_bg : entity work.tb_diag_block_gen generic map (e_active, 96, 10, 32, 7, 32, false);
u_bg_ready : entity work.tb_diag_block_gen generic map (e_random, 96, 10, 32, 7, 32, false);
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
index 09ecb0650a..b97341a951 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_tb_diag_rx_seq is
end tb_tb_diag_rx_seq;
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
index 812024f273..48ccad2ed5 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_tb_mms_diag_block_gen is
end tb_tb_mms_diag_block_gen;
@@ -39,15 +39,15 @@ architecture tb of tb_tb_mms_diag_block_gen is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- g_use_usr_input : BOOLEAN := TRUE;
--- g_use_bg : BOOLEAN := TRUE;
--- g_use_tx_seq : BOOLEAN := FALSE;
--- g_use_bg_buffer_ram : BOOLEAN := TRUE;
--- g_usr_bypass_xonoff : BOOLEAN := FALSE;
--- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
--- g_nof_repeat : NATURAL := 2;
--- g_nof_streams : NATURAL := 16;
--- g_gap_size : NATURAL := 160
+ -- g_use_usr_input : BOOLEAN := TRUE;
+ -- g_use_bg : BOOLEAN := TRUE;
+ -- g_use_tx_seq : BOOLEAN := FALSE;
+ -- g_use_bg_buffer_ram : BOOLEAN := TRUE;
+ -- g_usr_bypass_xonoff : BOOLEAN := FALSE;
+ -- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- g_nof_repeat : NATURAL := 2;
+ -- g_nof_streams : NATURAL := 16;
+ -- g_gap_size : NATURAL := 160
u_bg_one_stream : entity work.tb_mms_diag_block_gen generic map (false, true, false, true, false, e_active, 1, 1, 0);
u_bg_gap_0 : entity work.tb_mms_diag_block_gen generic map (false, true, false, true, false, e_active, 1, 3, 0);
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
index 416cb26dec..9324000d7f 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_tb_mms_diag_seq is
end tb_tb_mms_diag_seq;
diff --git a/libraries/base/diagnostics/src/vhdl/diagnostics.vhd b/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
index 2fceec4f1a..22054ea8d8 100644
--- a/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
+++ b/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
@@ -32,11 +32,11 @@
-- All control inputs and status outputs apply to an individual stream.
library IEEE, common_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity diagnostics is
generic (
@@ -46,7 +46,7 @@ entity diagnostics is
g_src_latency : natural := 1;
g_snk_latency : natural := 1;
g_separate_clk : boolean := false -- Use separate SRC and SNK clock domains
- );
+ );
port (
rst : in std_logic := '0';
clk : in std_logic := '0';
@@ -132,56 +132,56 @@ begin
snk_diag_res_val(i) <= andv(substream_snk_diag_res_val(i)); -- If all substream diag results are valid, the stream's diag_res is valid.
u_tx_latency_adpt: entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => g_src_latency
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => g_src_latency
)
- port map (
- rst => tx_rst(i),
- clk => tx_clk(i),
+ port map (
+ rst => tx_rst(i),
+ clk => tx_clk(i),
- snk_out => tx_dpmon_siso_arr(i),
- snk_in => tx_dpmon_sosi_arr(i),
+ snk_out => tx_dpmon_siso_arr(i),
+ snk_in => tx_dpmon_sosi_arr(i),
- src_out => src_out_arr(i),
- src_in => src_in_arr(i)
- );
+ src_out => src_out_arr(i),
+ src_in => src_in_arr(i)
+ );
u_rx_latency_adpt: entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => g_snk_latency,
- g_out_latency => 1
- )
- port map (
- rst => rx_rst(i),
- clk => rx_clk(i),
+ generic map (
+ g_in_latency => g_snk_latency,
+ g_out_latency => 1
+ )
+ port map (
+ rst => rx_rst(i),
+ clk => rx_clk(i),
- snk_out => snk_out_arr(i),
- snk_in => snk_in_arr(i),
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
- src_out => rx_dpmon_sosi_arr(i),
- src_in => rx_dpmon_siso_arr(i)
- );
+ src_out => rx_dpmon_sosi_arr(i),
+ src_in => rx_dpmon_siso_arr(i)
+ );
tx_diag_req(i) <= tx_siso_arr(i).ready and tx_siso_arr(i).xon;
gen_bg : if g_block_len > 0 generate
u_dp_block_gen: entity dp_lib.dp_block_gen
- generic map (
- g_nof_data => g_block_len,
- g_empty => 0,
- g_channel => 0,
- g_error => 0
- )
- port map (
- rst => tx_rst(i),
- clk => tx_clk(i),
+ generic map (
+ g_nof_data => g_block_len,
+ g_empty => 0,
+ g_channel => 0,
+ g_error => 0
+ )
+ port map (
+ rst => tx_rst(i),
+ clk => tx_clk(i),
- src_in => tx_bg_siso_arr(i),
- src_out => tx_bg_sosi_arr(i),
+ src_in => tx_bg_siso_arr(i),
+ src_out => tx_bg_sosi_arr(i),
- en => src_diag_en(i)
- );
+ en => src_diag_en(i)
+ );
tx_sosi_arr(i).sop <= tx_bg_sosi_arr(i).sop;
tx_sosi_arr(i).eop <= tx_bg_sosi_arr(i).eop;
@@ -194,41 +194,41 @@ begin
gen_nof_substreams : for j in c_nof_substreams - 1 downto 0 generate
u_diag_tx_seq: entity diag_lib.diag_tx_seq
- generic map (
- g_dat_w => c_sub_stream_dat_w
+ generic map (
+ g_dat_w => c_sub_stream_dat_w
)
- port map (
- rst => tx_rst(i),
- clk => tx_clk(i),
- clken => tb_clken(i),
+ port map (
+ rst => tx_rst(i),
+ clk => tx_clk(i),
+ clken => tb_clken(i),
- diag_en => src_diag_en(i),
- diag_sel => src_diag_md(i),
- diag_init => (others => '0'),
+ diag_en => src_diag_en(i),
+ diag_sel => src_diag_md(i),
+ diag_init => (others => '0'),
- diag_req => tx_diag_req(i),
- out_dat => tx_sosi_arr(i).data( (j + 1) * c_sub_stream_dat_w - 1 downto (j + 1) * c_sub_stream_dat_w - c_sub_stream_dat_w ),
- out_val => tx_seq_out_val(i)(j)
- );
+ diag_req => tx_diag_req(i),
+ out_dat => tx_sosi_arr(i).data( (j + 1) * c_sub_stream_dat_w - 1 downto (j + 1) * c_sub_stream_dat_w - c_sub_stream_dat_w ),
+ out_val => tx_seq_out_val(i)(j)
+ );
u_diag_rx_seq: entity diag_lib.diag_rx_seq
- generic map (
- g_dat_w => c_sub_stream_dat_w,
- g_diag_res_w => c_sub_stream_dat_w
+ generic map (
+ g_dat_w => c_sub_stream_dat_w,
+ g_diag_res_w => c_sub_stream_dat_w
)
- port map (
- rst => rx_rst(i),
- clk => rx_clk(i),
+ port map (
+ rst => rx_rst(i),
+ clk => rx_clk(i),
- diag_en => snk_diag_en(i),
- diag_sel => snk_diag_md(i),
+ diag_en => snk_diag_en(i),
+ diag_sel => snk_diag_md(i),
- orv(diag_res) => substream_snk_diag_res(i)(j), -- vector-wise OR to create a one-bit diag_result per substream
- diag_res_val => substream_snk_diag_res_val(i)(j),
+ orv(diag_res) => substream_snk_diag_res(i)(j), -- vector-wise OR to create a one-bit diag_result per substream
+ diag_res_val => substream_snk_diag_res_val(i)(j),
- in_dat => rx_sosi_arr(i).data( (j + 1) * c_sub_stream_dat_w - 1 downto (j + 1) * c_sub_stream_dat_w - c_sub_stream_dat_w),
- in_val => rx_sosi_arr(i).valid
- );
+ in_dat => rx_sosi_arr(i).data( (j + 1) * c_sub_stream_dat_w - 1 downto (j + 1) * c_sub_stream_dat_w - c_sub_stream_dat_w),
+ in_val => rx_sosi_arr(i).valid
+ );
end generate;
tx_sosi_arr(i).valid <= tx_seq_out_val(i)(0);
@@ -237,41 +237,41 @@ begin
rx_siso_arr(i).xon <= '1'; -- snk_diag_en(i);
u_tx_dpmon : entity dp_lib.dp_mon
- generic map (
- g_latency => 1
- )
- port map (
- rst => tx_rst(i),
- clk => tx_clk(i),
- en => src_diag_en(i),
+ generic map (
+ g_latency => 1
+ )
+ port map (
+ rst => tx_rst(i),
+ clk => tx_clk(i),
+ en => src_diag_en(i),
- snk_out => tx_siso_arr(i),
- snk_in => tx_sosi_arr(i),
+ snk_out => tx_siso_arr(i),
+ snk_in => tx_sosi_arr(i),
- src_in => tx_dpmon_siso_arr(i),
- src_out => tx_dpmon_sosi_arr(i),
+ src_in => tx_dpmon_siso_arr(i),
+ src_out => tx_dpmon_sosi_arr(i),
- clr => src_val_cnt_clr(i),
- word_cnt => src_val_cnt(i)
- );
+ clr => src_val_cnt_clr(i),
+ word_cnt => src_val_cnt(i)
+ );
u_rx_dpmon : entity dp_lib.dp_mon
- generic map (
- g_latency => 1
- )
- port map (
- rst => rx_rst(i),
- clk => rx_clk(i),
- en => snk_diag_en(i),
-
- snk_out => rx_dpmon_siso_arr(i),
- snk_in => rx_dpmon_sosi_arr(i),
-
- src_in => rx_siso_arr(i),
- src_out => rx_sosi_arr(i),
-
- clr => snk_val_cnt_clr(i),
- word_cnt => snk_val_cnt(i)
- );
+ generic map (
+ g_latency => 1
+ )
+ port map (
+ rst => rx_rst(i),
+ clk => rx_clk(i),
+ en => snk_diag_en(i),
+
+ snk_out => rx_dpmon_siso_arr(i),
+ snk_in => rx_dpmon_sosi_arr(i),
+
+ src_in => rx_siso_arr(i),
+ src_out => rx_sosi_arr(i),
+
+ clr => snk_val_cnt_clr(i),
+ word_cnt => snk_val_cnt(i)
+ );
end generate;
end str;
diff --git a/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd b/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
index 6fd9e3ac98..c1be681082 100644
--- a/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use diag_lib.diag_pkg.all;
entity diagnostics_reg is
generic (
g_nof_streams : natural;
g_separate_clk : boolean := false -- Use separate SRC and SNK clock domains
- );
+ );
port (
-- Clocks and reset
mm_rst : in std_logic; -- reset synchronous with mm_clk
@@ -60,17 +60,18 @@ entity diagnostics_reg is
st_snk_cnt_clr_evt : out std_logic_vector(g_nof_streams - 1 downto 0);
st_snk_diag_val : in std_logic_vector(g_nof_streams - 1 downto 0);
st_snk_diag_res : in std_logic_vector(g_nof_streams - 1 downto 0)
- );
+ );
end diagnostics_reg;
architecture rtl of diagnostics_reg is
constant c_nof_registers : natural := 40; -- src_cnt and snk_cnt registers should be variable in size....but the CASE process makes that difficult.
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_registers),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_registers,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_registers),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_registers,
+ init_sl => '0');
-- Registers in mm_clk domain
signal mm_src_en : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -156,7 +157,7 @@ begin
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -349,8 +350,8 @@ begin
-- Diag_res and related signals are polled after a certain nof words has been
-- received - data will be stable.
--- mm_snk_diag_val(i) <= st_snk_diag_val(i);
--- mm_snk_diag_res(i) <= st_snk_diag_res(i);
+ -- mm_snk_diag_val(i) <= st_snk_diag_val(i);
+ -- mm_snk_diag_res(i) <= st_snk_diag_res(i);
end generate;
u_cross_domain_snk_diag_val : entity common_lib.common_reg_cross_domain
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
index 3f93466da3..e7ef0a68c9 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
@@ -21,20 +21,20 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mm_rx_logger is
generic (
g_technology : natural := c_tech_select_default;
g_dat_w : natural;
g_fifo_wr_depth : natural := 128 -- Only put powers of 2 here.
- );
+ );
port (
rx_rst : in std_logic;
rx_clk : in std_logic;
@@ -92,7 +92,7 @@ architecture str of mm_rx_logger is
signal trig_log_en : std_logic;
signal log_en : std_logic;
signal mm_ovr : std_logic := '0'; -- Normal operation (mm_over='0') : trigger enable/disable inputs control log_en
- -- Overridden operation (mm_over='1'): MM master controls log_en
+ -- Overridden operation (mm_over='1'): MM master controls log_en
signal mm_trig_on : std_logic;
signal mm_trig_one_shot : std_logic;
@@ -118,17 +118,17 @@ begin
-- FSM to enable/disable logging based on trigger inputs
u_mm_rx_logger_trig : entity work.mm_rx_logger_trig
- port map (
- clk => rx_clk,
- rst => rx_rst,
- trig_on => mm_trig_on,
- one_shot => mm_trig_one_shot,
- log_en_evt => trig_en_evt,
- log_dis_evt => trig_dis_evt,
- log_nof_words => mm_trig_nof_words,
- log_cnt => mm_trig_nof_logged_words,
- log_en => trig_log_en
- );
+ port map (
+ clk => rx_clk,
+ rst => rx_rst,
+ trig_on => mm_trig_on,
+ one_shot => mm_trig_one_shot,
+ log_en_evt => trig_en_evt,
+ log_dis_evt => trig_dis_evt,
+ log_nof_words => mm_trig_nof_words,
+ log_cnt => mm_trig_nof_logged_words,
+ log_en => trig_log_en
+ );
log_en <= trig_log_en or sla_log_en; -- Allow slave input to enable logging
mst_log_en <= log_en; -- Forward log_en signal to master output
@@ -140,41 +140,41 @@ begin
-- The FIFO's almost_full will de-assert it's snk ready signal. We'll use
-- that to flush the FIFO on the src side.
u_data_log_fifo : entity dp_lib.dp_fifo_sc
- generic map (
- g_technology => g_technology,
- g_data_w => g_dat_w,
- g_use_ctrl => false,
- g_fifo_size => g_fifo_wr_depth
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
-
- snk_out => data_log_fifo_siso,
- snk_in => data_log_fifo_sosi,
-
- src_in => data_flusher_siso,
- src_out => data_flusher_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_dat_w,
+ g_use_ctrl => false,
+ g_fifo_size => g_fifo_wr_depth
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+
+ snk_out => data_log_fifo_siso,
+ snk_in => data_log_fifo_sosi,
+
+ src_in => data_flusher_siso,
+ src_out => data_flusher_sosi
+ );
-- dp_flush to flush data log FIFO when almost full.
u_data_flush: entity dp_lib.dp_flush
- generic map (
- g_framed_xon => false,
- g_framed_xoff => false
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
- -- ST sink
- snk_in => data_flusher_sosi,
- snk_out => data_flusher_siso,
- -- ST source
- src_in => ovr_data_dpmm_fifo_siso,
- src_out => data_dpmm_fifo_sosi,
- -- Enable flush
- flush_en => flush_en
- );
+ generic map (
+ g_framed_xon => false,
+ g_framed_xoff => false
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+ -- ST sink
+ snk_in => data_flusher_sosi,
+ snk_out => data_flusher_siso,
+ -- ST source
+ src_in => ovr_data_dpmm_fifo_siso,
+ src_out => data_dpmm_fifo_sosi,
+ -- Enable flush
+ flush_en => flush_en
+ );
flush_en <= not data_log_fifo_siso.ready; -- We'll flush when the data log fifo is almost full.
@@ -185,47 +185,47 @@ begin
ovr_data_dpmm_fifo_siso.xon <= data_dpmm_fifo_siso.xon; -- leave xon as it is
u_data_dpmm_fifo : entity dp_lib.dp_fifo_dc_mixed_widths
- generic map (
- g_technology => g_technology,
- g_wr_data_w => g_dat_w,
- g_rd_data_w => c_word_w,
- g_use_ctrl => false,
- g_wr_fifo_size => c_dpmm_fifo_wr_depth
- )
- port map (
- wr_rst => rx_rst,
- wr_clk => rx_clk,
- rd_rst => mm_rst,
- rd_clk => mm_clk,
-
- snk_out => data_dpmm_fifo_siso,
- snk_in => data_dpmm_fifo_sosi,
-
- wr_usedw => OPEN,
- rd_usedw => data_dpmm_fifo_rd_usedw,
- rd_emp => OPEN,
-
- src_in => data_mm_siso,
- src_out => data_mm_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_wr_data_w => g_dat_w,
+ g_rd_data_w => c_word_w,
+ g_use_ctrl => false,
+ g_wr_fifo_size => c_dpmm_fifo_wr_depth
+ )
+ port map (
+ wr_rst => rx_rst,
+ wr_clk => rx_clk,
+ rd_rst => mm_rst,
+ rd_clk => mm_clk,
+
+ snk_out => data_dpmm_fifo_siso,
+ snk_in => data_dpmm_fifo_sosi,
+
+ wr_usedw => OPEN,
+ rd_usedw => data_dpmm_fifo_rd_usedw,
+ rd_emp => OPEN,
+
+ src_in => data_mm_siso,
+ src_out => data_mm_sosi
+ );
u_data_fifo_to_mm : entity dp_lib.dp_fifo_to_mm
- generic map(
- g_fifo_size => c_data_dpmm_fifo_rd_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
-
- snk_out => data_mm_siso,
- snk_in => data_mm_sosi,
- usedw => data_dpmm_fifo_rd_usedw, -- used words from the clock crossing FIFO (NOT the logging FIFO)
-
- mm_rd => data_mm_rd,
- mm_rddata => data_mm_rd_data,
- mm_rdval => data_mm_rd_val,
- mm_usedw => data_mm_rd_usedw -- used words resized to 32 bits
- );
+ generic map(
+ g_fifo_size => c_data_dpmm_fifo_rd_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ snk_out => data_mm_siso,
+ snk_in => data_mm_sosi,
+ usedw => data_dpmm_fifo_rd_usedw, -- used words from the clock crossing FIFO (NOT the logging FIFO)
+
+ mm_rd => data_mm_rd,
+ mm_rddata => data_mm_rd_data,
+ mm_rdval => data_mm_rd_val,
+ mm_usedw => data_mm_rd_usedw -- used words resized to 32 bits
+ );
-- data read output to mm bus
data_miso.rddata(c_word_w - 1 downto 0) <= data_mm_rd_data;
@@ -235,22 +235,22 @@ begin
-- ============== MM control ========================================================================
u_ctrl_reg : entity work.mm_rx_logger_reg
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- rx_rst => rx_rst,
- rx_clk => rx_clk,
-
- sla_in => ctrl_mosi,
- sla_out => ctrl_miso,
-
- rx_trig_on => mm_trig_on,
- rx_trig_one_shot => mm_trig_one_shot,
- rx_mm_ovr => mm_ovr,
- rx_log_en_evt => mm_trig_en_evt,
- rx_log_dis_evt => mm_trig_dis_evt,
- rx_trig_nof_words => mm_trig_nof_words,
- rx_trig_nof_logged_words => mm_trig_nof_logged_words,
- mm_data_usedw => data_mm_rd_usedw
- );
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ rx_rst => rx_rst,
+ rx_clk => rx_clk,
+
+ sla_in => ctrl_mosi,
+ sla_out => ctrl_miso,
+
+ rx_trig_on => mm_trig_on,
+ rx_trig_one_shot => mm_trig_one_shot,
+ rx_mm_ovr => mm_ovr,
+ rx_log_en_evt => mm_trig_en_evt,
+ rx_log_dis_evt => mm_trig_dis_evt,
+ rx_trig_nof_words => mm_trig_nof_words,
+ rx_trig_nof_logged_words => mm_trig_nof_logged_words,
+ mm_data_usedw => data_mm_rd_usedw
+ );
end str;
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
index fb6107194a..5af04ea58d 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mm_rx_logger_reg is
port (
@@ -48,15 +48,16 @@ entity mm_rx_logger_reg is
-- MM registers
mm_data_usedw : in std_logic_vector(31 downto 0)
- );
+ );
end mm_rx_logger_reg;
architecture rtl of mm_rx_logger_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(8),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 8,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(8),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 8,
+ init_sl => '0');
-- Registers in mm_clk domain
signal mm_trig_on : std_logic;
signal mm_trig_one_shot : std_logic;
@@ -114,7 +115,7 @@ begin
when others => null; -- unused MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -124,7 +125,7 @@ begin
sla_out.rddata(c_word_w - 1 downto 0) <= mm_trig_nof_logged_words;
when 4 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_data_usedw;
- when others => null; -- unused MM addresses
+ when others => null; -- unused MM addresses
end case;
end if;
end if;
@@ -148,59 +149,59 @@ begin
------------------------------------------------------------------------------
u_spulse_log_en_evt : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_log_en_evt,
- in_busy => OPEN,
- out_rst => rx_rst,
- out_clk => rx_clk,
- out_pulse => rx_log_en_evt
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_log_en_evt,
+ in_busy => OPEN,
+ out_rst => rx_rst,
+ out_clk => rx_clk,
+ out_pulse => rx_log_en_evt
+ );
u_spulse_log_dis_evt : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_log_dis_evt,
- in_busy => OPEN,
- out_rst => rx_rst,
- out_clk => rx_clk,
- out_pulse => rx_log_dis_evt
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_log_dis_evt,
+ in_busy => OPEN,
+ out_rst => rx_rst,
+ out_clk => rx_clk,
+ out_pulse => rx_log_dis_evt
+ );
u_async_mm_ovr : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
- din => mm_ovr,
- dout => rx_mm_ovr
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+ din => mm_ovr,
+ dout => rx_mm_ovr
+ );
u_async_mm_trig_on : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
- din => mm_trig_on,
- dout => rx_trig_on
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+ din => mm_trig_on,
+ dout => rx_trig_on
+ );
u_async_mm_trig_one_shot : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
- din => mm_trig_one_shot,
- dout => rx_trig_one_shot
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+ din => mm_trig_one_shot,
+ dout => rx_trig_one_shot
+ );
rx_trig_nof_words <= mm_trig_nof_words;
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
index cfe4fe951f..386b309498 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
@@ -21,9 +21,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity mm_rx_logger_trig is
port (
@@ -36,7 +36,7 @@ entity mm_rx_logger_trig is
log_nof_words : in std_logic_vector(c_word_w - 1 downto 0); -- unlimited (as long as there's no dis_evt) when zero (log FIFO keeps flushing then)
log_cnt : out std_logic_vector(c_word_w - 1 downto 0);
log_en : out std_logic
- );
+ );
end mm_rx_logger_trig;
architecture str of mm_rx_logger_trig is
diff --git a/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd b/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
index 6f31fd34b9..c17fdfbd85 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
@@ -21,19 +21,19 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mm_tx_framer is
generic(
g_technology : natural := c_tech_select_default;
g_dat_out_w : natural;
g_rd_fifo_depth : natural := 128
- );
+ );
port (
mm_clk : in std_logic;
mm_rst : in std_logic;
@@ -52,8 +52,8 @@ entity mm_tx_framer is
master_release : out std_logic; -- If used this instance will provide master release control for other instance(s)
slave_release : in std_logic := '0' -- If this instance is slave of another instance, the an MM write to the master's MM release will
- -- also release the frames in the slave(s)
- );
+ -- also release the frames in the slave(s)
+ );
end mm_tx_framer;
architecture str of mm_tx_framer is
@@ -72,63 +72,63 @@ begin
master_release <= release;
u_data_dp_fifo_from_mm : entity dp_lib.dp_fifo_from_mm
- generic map (
- g_fifo_size => c_wr_fifo_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- ST soure connected to FIFO input
- src_out => mm_to_fifo_sosi,
- usedw => wr_usedw,
- -- Control for FIFO read access
- mm_wr => data_mosi.wr,
- mm_wrdata => data_mosi.wrdata(c_word_w - 1 downto 0),
- mm_usedw => OPEN,
- mm_availw => mm_availw
- );
+ generic map (
+ g_fifo_size => c_wr_fifo_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- ST soure connected to FIFO input
+ src_out => mm_to_fifo_sosi,
+ usedw => wr_usedw,
+ -- Control for FIFO read access
+ mm_wr => data_mosi.wr,
+ mm_wrdata => data_mosi.wrdata(c_word_w - 1 downto 0),
+ mm_usedw => OPEN,
+ mm_availw => mm_availw
+ );
u_mm_to_dp_fifo : entity dp_lib.dp_fifo_dc_mixed_widths
- generic map (
- g_technology => g_technology,
- g_wr_data_w => c_word_w,
- g_rd_data_w => g_dat_out_w,
- g_use_ctrl => false,
- g_wr_fifo_size => c_wr_fifo_depth
- )
- port map (
- wr_rst => mm_rst,
- wr_clk => mm_clk,
- rd_rst => tx_rst,
- rd_clk => tx_clk,
-
- snk_out => OPEN,
- snk_in => mm_to_fifo_sosi,
-
- wr_usedw => wr_usedw, -- Using wr_usedw because that side is in mm_clk domain
- rd_usedw => OPEN,
- rd_emp => OPEN,
-
- src_in => fifo_siso,
- src_out => fifo_out_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_wr_data_w => c_word_w,
+ g_rd_data_w => g_dat_out_w,
+ g_use_ctrl => false,
+ g_wr_fifo_size => c_wr_fifo_depth
+ )
+ port map (
+ wr_rst => mm_rst,
+ wr_clk => mm_clk,
+ rd_rst => tx_rst,
+ rd_clk => tx_clk,
+
+ snk_out => OPEN,
+ snk_in => mm_to_fifo_sosi,
+
+ wr_usedw => wr_usedw, -- Using wr_usedw because that side is in mm_clk domain
+ rd_usedw => OPEN,
+ rd_emp => OPEN,
+
+ src_in => fifo_siso,
+ src_out => fifo_out_sosi
+ );
data_out <= fifo_out_sosi.data(g_dat_out_w - 1 downto 0) when fifo_out_sosi.valid = '1' and (release = '1' or slave_release = '1') else data_out_default;
fifo_siso.ready <= release or slave_release;
u_reg : entity work.mm_tx_framer_reg
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- tx_clk => tx_clk,
- tx_rst => tx_rst,
+ tx_clk => tx_clk,
+ tx_rst => tx_rst,
- sla_in => ctrl_mosi,
- sla_out => ctrl_miso,
+ sla_in => ctrl_mosi,
+ sla_out => ctrl_miso,
- mm_availw => mm_availw,
- tx_release => release
+ mm_availw => mm_availw,
+ tx_release => release
- );
+ );
end str;
diff --git a/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd b/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
index 97ef6ed9f1..d4171a05c1 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mm_tx_framer_reg is
port (
@@ -42,15 +42,16 @@ entity mm_tx_framer_reg is
-- MM registers
mm_availw : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mm_tx_framer_reg;
architecture rtl of mm_tx_framer_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(2),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(2),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2,
+ init_sl => '0');
-- Registers in mm_clk domain
signal mm_release : std_logic;
begin
@@ -82,10 +83,10 @@ begin
-- Write Block Sync
when 1 =>
mm_release <= sla_in.wrdata(0);
- when others => null; -- unused MM addresses
+ when others => null; -- unused MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -93,7 +94,7 @@ begin
-- Read Block Sync
when 0 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_availw;
- when others => null; -- unused MM addresses
+ when others => null; -- unused MM addresses
end case;
end if;
end if;
@@ -117,13 +118,13 @@ begin
------------------------------------------------------------------------------
u_async_release : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => tx_rst,
- clk => tx_clk,
- din => mm_release,
- dout => tx_release
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => tx_rst,
+ clk => tx_clk,
+ din => mm_release,
+ dout => tx_release
+ );
end rtl;
diff --git a/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd b/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
index a1c02e2330..7b03bab114 100644
--- a/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_diagnostics is
generic (
@@ -85,72 +85,72 @@ begin
snk_en_out <= snk_diag_en;
u_diagnostics: entity work.diagnostics
- generic map (
- g_dat_w => g_data_w,
- g_block_len => g_block_len,
- g_nof_streams => g_nof_streams,
- g_src_latency => g_src_latency,
- g_snk_latency => g_snk_latency,
- g_separate_clk => g_separate_clk
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- src_rst => src_rst,
- src_clk => src_clk,
-
- snk_rst => snk_rst,
- snk_clk => snk_clk,
-
- snk_out_arr => snk_out_arr,
- snk_in_arr => snk_in_arr,
- snk_diag_en => snk_diag_en,
- snk_diag_md => snk_diag_md,
- snk_diag_res => snk_diag_res,
- snk_diag_res_val => snk_diag_res_val,
- snk_val_cnt => snk_val_cnt,
- snk_val_cnt_clr => snk_val_cnt_clr,
-
- src_out_arr => src_out_arr,
- src_in_arr => src_in_arr,
- src_diag_en => src_diag_en,
- src_diag_md => src_diag_md,
- src_val_cnt => src_val_cnt,
- src_val_cnt_clr => src_val_cnt_clr
- );
+ generic map (
+ g_dat_w => g_data_w,
+ g_block_len => g_block_len,
+ g_nof_streams => g_nof_streams,
+ g_src_latency => g_src_latency,
+ g_snk_latency => g_snk_latency,
+ g_separate_clk => g_separate_clk
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ src_rst => src_rst,
+ src_clk => src_clk,
+
+ snk_rst => snk_rst,
+ snk_clk => snk_clk,
+
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ snk_diag_en => snk_diag_en,
+ snk_diag_md => snk_diag_md,
+ snk_diag_res => snk_diag_res,
+ snk_diag_res_val => snk_diag_res_val,
+ snk_val_cnt => snk_val_cnt,
+ snk_val_cnt_clr => snk_val_cnt_clr,
+
+ src_out_arr => src_out_arr,
+ src_in_arr => src_in_arr,
+ src_diag_en => src_diag_en,
+ src_diag_md => src_diag_md,
+ src_val_cnt => src_val_cnt,
+ src_val_cnt_clr => src_val_cnt_clr
+ );
u_diagnostics_reg: entity work.diagnostics_reg
- generic map(
- g_nof_streams => g_nof_streams,
- g_separate_clk => g_separate_clk
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- src_rst => src_rst,
- src_clk => src_clk,
-
- snk_rst => snk_rst,
- snk_clk => snk_clk,
-
- sla_in => mm_mosi,
- sla_out => mm_miso,
-
- st_src_en => src_diag_en,
- st_src_md => src_diag_md,
- st_src_cnt => src_val_cnt,
- st_src_cnt_clr_evt => src_val_cnt_clr,
-
- st_snk_en => snk_diag_en,
- st_snk_md => snk_diag_md,
- st_snk_cnt => snk_val_cnt,
- st_snk_cnt_clr_evt => snk_val_cnt_clr,
- st_snk_diag_val => snk_diag_res_val,
- st_snk_diag_res => snk_diag_res
- );
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_separate_clk => g_separate_clk
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ src_rst => src_rst,
+ src_clk => src_clk,
+
+ snk_rst => snk_rst,
+ snk_clk => snk_clk,
+
+ sla_in => mm_mosi,
+ sla_out => mm_miso,
+
+ st_src_en => src_diag_en,
+ st_src_md => src_diag_md,
+ st_src_cnt => src_val_cnt,
+ st_src_cnt_clr_evt => src_val_cnt_clr,
+
+ st_snk_en => snk_diag_en,
+ st_snk_md => snk_diag_md,
+ st_snk_cnt => snk_val_cnt,
+ st_snk_cnt_clr_evt => snk_val_cnt_clr,
+ st_snk_diag_val => snk_diag_res_val,
+ st_snk_diag_res => snk_diag_res
+ );
end str;
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
index 4df9f42fa1..d4cd3ec4ad 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
@@ -27,12 +27,12 @@
-- > run -a
library IEEE, common_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_unsigned.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_diagnostics is
end entity tb_diagnostics;
@@ -58,7 +58,7 @@ architecture str of tb_diagnostics is
signal src_diag_en : std_logic_vector(c_nof_streams - 1 downto 0);
signal src_val_cnt : t_slv_32_arr(c_nof_streams - 1 downto 0);
- begin
+begin
-- Run for 1us
rst <= '0' after 100 ns;
@@ -104,7 +104,7 @@ architecture str of tb_diagnostics is
generic map (
g_dat_w => c_dat_w,
g_nof_streams => c_nof_streams
- )
+ )
port map (
rst => rst,
clk => clk,
@@ -123,4 +123,4 @@ architecture str of tb_diagnostics is
src_diag_md => (others => '1'),
src_val_cnt => src_val_cnt
);
-end architecture str;
+ end architecture str;
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
index 796aeba35b..ae12f48ec5 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
@@ -20,43 +20,48 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use STD.textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use STD.textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
package tb_diagnostics_trnb_pkg is
type t_e_diagnostics_trnb_mode is (e_prbs, e_counter);
-- Global procedures
- procedure proc_diagnostics_trnb_tx_set_mode_prbs( signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_diagnostics_trnb_rx_set_mode_prbs( signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_diagnostics_trnb_tx_set_mode_counter(constant c_nof_gx_mask : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_diagnostics_trnb_rx_set_mode_counter(constant c_nof_gx_mask : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_diagnostics_trnb_run_and_verify(constant c_chip_id : in natural;
- constant c_nof_gx : in natural;
- constant c_nof_gx_mask : in integer;
- constant c_link_delay : in real;
- constant c_diag_on_interval : in real;
- constant c_diag_off_interval : in real;
- constant c_mm_clk_1us : in real;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_diagnostics_trnb_tx_set_mode_prbs(
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_diagnostics_trnb_rx_set_mode_prbs(
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_diagnostics_trnb_tx_set_mode_counter(
+ constant c_nof_gx_mask : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_diagnostics_trnb_rx_set_mode_counter(
+ constant c_nof_gx_mask : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_diagnostics_trnb_run_and_verify(
+ constant c_chip_id : in natural;
+ constant c_nof_gx : in natural;
+ constant c_nof_gx_mask : in integer;
+ constant c_link_delay : in real;
+ constant c_diag_on_interval : in real;
+ constant c_diag_off_interval : in real;
+ constant c_mm_clk_1us : in real;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi);
-- Private procedures
end tb_diagnostics_trnb_pkg;
@@ -66,14 +71,16 @@ package body tb_diagnostics_trnb_pkg is
-- PROCEDURE: Set all gx to default mode PRBS
------------------------------------------------------------------------------
- procedure proc_diagnostics_trnb_tx_set_mode_prbs(signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_tx_set_mode_prbs(
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
proc_mem_mm_bus_wr( 1, 0, mm_clk, mm_mosi); -- set source mode 0 = PRBS, 1 = COUNTER
end procedure proc_diagnostics_trnb_tx_set_mode_prbs;
- procedure proc_diagnostics_trnb_rx_set_mode_prbs(signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_rx_set_mode_prbs(
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
proc_mem_mm_bus_wr(20, 0, mm_clk, mm_mosi); -- set sink mode 0 = PRBS, 1 = COUNTER
end procedure proc_diagnostics_trnb_rx_set_mode_prbs;
@@ -83,16 +90,18 @@ package body tb_diagnostics_trnb_pkg is
-- default mode PRBS
------------------------------------------------------------------------------
- procedure proc_diagnostics_trnb_tx_set_mode_counter(constant c_nof_gx_mask : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_tx_set_mode_counter(
+ constant c_nof_gx_mask : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
proc_mem_mm_bus_wr( 1, c_nof_gx_mask, mm_clk, mm_mosi); -- set source mode 0 = PRBS, 1 = COUNTER
end procedure proc_diagnostics_trnb_tx_set_mode_counter;
- procedure proc_diagnostics_trnb_rx_set_mode_counter(constant c_nof_gx_mask : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_rx_set_mode_counter(
+ constant c_nof_gx_mask : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
proc_mem_mm_bus_wr(20, c_nof_gx_mask, mm_clk, mm_mosi); -- set source mode 0 = PRBS, 1 = COUNTER
end procedure proc_diagnostics_trnb_rx_set_mode_counter;
@@ -101,47 +110,48 @@ package body tb_diagnostics_trnb_pkg is
-- PROCEDURE: Run a diagnostic measurement and verify the result
------------------------------------------------------------------------------
- procedure proc_diagnostics_trnb_run_and_verify(constant c_chip_id : in natural;
- constant c_nof_gx : in natural;
- constant c_nof_gx_mask : in integer;
- constant c_link_delay : in real;
- constant c_diag_on_interval : in real;
- constant c_diag_off_interval : in real;
- constant c_mm_clk_1us : in real;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_run_and_verify(
+ constant c_chip_id : in natural;
+ constant c_nof_gx : in natural;
+ constant c_nof_gx_mask : in integer;
+ constant c_link_delay : in real;
+ constant c_diag_on_interval : in real;
+ constant c_diag_off_interval : in real;
+ constant c_mm_clk_1us : in real;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi) is
constant c_nof_gx_mask_slv : std_logic_vector(c_nof_gx - 1 downto 0) := TO_UVEC(c_nof_gx_mask, c_nof_gx);
- variable v_diag_results_valid : std_logic_vector(c_nof_gx - 1 downto 0);
- variable v_diag_results : std_logic_vector(c_nof_gx - 1 downto 0);
+ variable v_diag_results_valid : std_logic_vector(c_nof_gx - 1 downto 0);
+ variable v_diag_results : std_logic_vector(c_nof_gx - 1 downto 0);
begin
- -- Enable diagnostics
- proc_mem_mm_bus_wr( 0, c_nof_gx_mask, mm_clk, mm_mosi); -- set source enable
- proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_link_delay); -- ensure source data has arrived before enabling the sink
- proc_mem_mm_bus_wr(19, c_nof_gx_mask, mm_clk, mm_mosi); -- set sink enable
-
- -- Measurement interval
- proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_diag_on_interval);
-
- -- Read results
- proc_mem_mm_bus_rd(38, mm_clk, mm_miso, mm_mosi); -- get sink diag result valid
- proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
- v_diag_results_valid := mm_miso.rddata(c_nof_gx - 1 downto 0) and c_nof_gx_mask_slv;
- proc_mem_mm_bus_rd(39, mm_clk, mm_miso, mm_mosi); -- get sink diag result
- proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
- v_diag_results := mm_miso.rddata(c_nof_gx - 1 downto 0) and c_nof_gx_mask_slv;
- proc_common_wait_some_cycles(mm_clk, 1);
-
- -- Verify results
- assert TO_UINT(v_diag_results_valid) = c_nof_gx_mask and TO_UINT(v_diag_results) = 0 report "proc_diagnostics_trnb_run_and_verify: TRNB diagnostics on went wrong on node " & natural'image(c_chip_id) severity ERROR;
-
- -- Disable diagnostics
- proc_mem_mm_bus_wr(19, 0, mm_clk, mm_mosi); -- set sink disable
- proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_link_delay); -- ensure disabling the sink before the source data has stopped arriving
- proc_mem_mm_bus_wr( 0, 0, mm_clk, mm_mosi); -- set source disable
-
- -- Idle interval
- proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_diag_off_interval);
+ -- Enable diagnostics
+ proc_mem_mm_bus_wr( 0, c_nof_gx_mask, mm_clk, mm_mosi); -- set source enable
+ proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_link_delay); -- ensure source data has arrived before enabling the sink
+ proc_mem_mm_bus_wr(19, c_nof_gx_mask, mm_clk, mm_mosi); -- set sink enable
+
+ -- Measurement interval
+ proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_diag_on_interval);
+
+ -- Read results
+ proc_mem_mm_bus_rd(38, mm_clk, mm_miso, mm_mosi); -- get sink diag result valid
+ proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
+ v_diag_results_valid := mm_miso.rddata(c_nof_gx - 1 downto 0) and c_nof_gx_mask_slv;
+ proc_mem_mm_bus_rd(39, mm_clk, mm_miso, mm_mosi); -- get sink diag result
+ proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
+ v_diag_results := mm_miso.rddata(c_nof_gx - 1 downto 0) and c_nof_gx_mask_slv;
+ proc_common_wait_some_cycles(mm_clk, 1);
+
+ -- Verify results
+ assert TO_UINT(v_diag_results_valid) = c_nof_gx_mask and TO_UINT(v_diag_results) = 0 report "proc_diagnostics_trnb_run_and_verify: TRNB diagnostics on went wrong on node " & natural'image(c_chip_id) severity ERROR;
+
+ -- Disable diagnostics
+ proc_mem_mm_bus_wr(19, 0, mm_clk, mm_mosi); -- set sink disable
+ proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_link_delay); -- ensure disabling the sink before the source data has stopped arriving
+ proc_mem_mm_bus_wr( 0, 0, mm_clk, mm_mosi); -- set source disable
+
+ -- Idle interval
+ proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_diag_off_interval);
end procedure proc_diagnostics_trnb_run_and_verify;
end tb_diagnostics_trnb_pkg;
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd b/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
index 9500074a59..335dc90e3e 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
@@ -20,14 +20,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_mm_tx_framer is
end tb_mm_tx_framer;
@@ -135,41 +135,41 @@ begin
-- simultaneously.
------------------------------------------------------------------------------
u_mm_tx_framer_mst: entity work.mm_tx_framer
- generic map(
- g_dat_out_w => 64
- )
- port map(
- tx_rst => tx_rst,
- tx_clk => tx_clk,
+ generic map(
+ g_dat_out_w => 64
+ )
+ port map(
+ tx_rst => tx_rst,
+ tx_clk => tx_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- ctrl_mosi => ctrl_mosi,
- ctrl_miso => ctrl_miso,
+ ctrl_mosi => ctrl_mosi,
+ ctrl_miso => ctrl_miso,
- data_mosi => mst_data_mosi,
- data_miso => mst_data_miso,
+ data_mosi => mst_data_mosi,
+ data_miso => mst_data_miso,
- data_out => mst_data_out,
- master_release => mst_release
- );
+ data_out => mst_data_out,
+ master_release => mst_release
+ );
u_mm_tx_framer_sla: entity work.mm_tx_framer
- generic map(
- g_dat_out_w => 32
- )
- port map(
- tx_rst => tx_rst,
- tx_clk => tx_clk,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- data_mosi => sla_data_mosi,
- data_miso => sla_data_miso,
-
- data_out => sla_data_out,
- slave_release => mst_release
- );
+ generic map(
+ g_dat_out_w => 32
+ )
+ port map(
+ tx_rst => tx_rst,
+ tx_clk => tx_clk,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ data_mosi => sla_data_mosi,
+ data_miso => sla_data_miso,
+
+ data_out => sla_data_out,
+ slave_release => mst_release
+ );
end tb;
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
index 8e84c4b54c..95ecdba40f 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
@@ -38,22 +38,22 @@
-- used to target hardware (--unb # --fn # --bn #)
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, tech_tse_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
-use common_lib.common_network_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
entity mmm_unb1_dp_offload is
generic (
@@ -185,41 +185,53 @@ begin
eth1g_ram_mosi <= c_mem_mosi_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
- port map(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
+ u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
+ port map(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
- u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
- port map(mm_rst, i_mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
+ u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
+ port map(mm_rst, i_mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
- u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+ u_mm_file_reg_bsn_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+ port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
- u_mm_file_ram_diag_data_buffer : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+ u_mm_file_ram_diag_data_buffer : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF")
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
- u_mm_file_reg_diag_data_buffer : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+ u_mm_file_reg_diag_data_buffer : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF")
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -243,10 +255,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_reg_mosi <= sim_eth1g_reg_mosi;
- else
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
- end if;
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ else
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -261,145 +273,145 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_dp_offload
- port map (
- clk_0 => xo_clk, -- 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- 125 MHz system clock
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
- dp_clk => i_dp_clk,
- cal_reconf_clk => OPEN,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_tech_tse_byte_addr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dp_offload_tx_hdr_dat
- coe_address_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
- coe_read_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
- coe_write_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dp_offload_rx_hdr_dat
- coe_address_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
- coe_read_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
- coe_write_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_reg_rsp_bsn_monitor_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_bsn_monitor => OPEN,
- coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_bsn_monitor => OPEN,
- coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buffer
- coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
- coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
- coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buffer
- coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
- coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
- coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ clk_0 => xo_clk, -- 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk, -- 125 MHz system clock
+ tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
+ dp_clk => i_dp_clk,
+ cal_reconf_clk => OPEN,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_tech_tse_byte_addr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dp_offload_tx_hdr_dat
+ coe_address_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
+ coe_read_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.rd,
+ coe_readdata_export_to_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
+ coe_write_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wr,
+ coe_writedata_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dp_offload_rx_hdr_dat
+ coe_address_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
+ coe_read_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.rd,
+ coe_readdata_export_to_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
+ coe_write_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wr,
+ coe_writedata_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_reg_rsp_bsn_monitor_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_bsn_monitor => OPEN,
+ coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_bsn_monitor => OPEN,
+ coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buffer
+ coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buffer
+ coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
index 52877cb035..b8e7955a09 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
@@ -27,19 +27,19 @@
-- instances via 1GbE (32b user interface)
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use diag_lib.diag_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use common_lib.common_field_pkg.all;
entity unb1_dp_offload is
generic (
@@ -52,7 +52,7 @@ entity unb1_dp_offload is
);
port (
-- GENERAL
--- CLK : IN STD_LOGIC; -- dp_clk is generated by SOPC altpll
+ -- CLK : IN STD_LOGIC; -- dp_clk is generated by SOPC altpll
PPS : in std_logic;
WDI : out std_logic;
INTA : inout std_logic;
@@ -83,46 +83,48 @@ architecture str of unb1_dp_offload is
constant c_bg_block_size : natural := 900;
constant c_bg_gapsize : natural := 100;
constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable
- '0', -- enable_sync
- TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable
+ '0', -- enable_sync
+ TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
-- dp_offload_tx
constant c_nof_hdr_fields : natural := 4 + 12 + 4 + 9; -- Total header bits = 512
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(x"002286080000") ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(128) ),
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(4000) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(4000) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(108) ),
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
- ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
- ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
- ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
- ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
- ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
- ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
- ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
+ constant c_hdr_field_arr : t_common_field_arr(
+ c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(x"002286080000") ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(128) ),
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(4000) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(4000) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(108) ),
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "1101" & "111111111100" & "1111" & "001111111";
@@ -206,28 +208,28 @@ begin
-- TX: Block generator
-----------------------------------------------------------------------------
u_mms_diag_block_gen : entity diag_lib.mms_diag_block_gen
- generic map (
- g_nof_streams => c_nof_streams,
- g_buf_dat_w => c_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_name_prefix => "hex/counter_data_" & natural'image(c_data_w),
- g_diag_block_gen_rst => c_bg_ctrl
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_buf_dat_w => c_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(c_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso
+ );
---------------------------------------------------------------------------------------
-- Use a FIFO when the source has no flow control
@@ -235,56 +237,56 @@ begin
---------------------------------------------------------------------------------------
gen_dp_fifo_sc : for i in 0 to c_nof_streams - 1 generate
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
- generic map (
- g_data_w => c_data_w,
- g_use_bsn => true,
- g_bsn_w => 64,
- g_use_sync => true,
- g_fifo_size => 100
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => block_gen_src_out_arr(i),
- snk_out => block_gen_src_in_arr(i),
-
- src_out => dp_offload_tx_snk_in_arr(i),
- src_in => dp_offload_tx_snk_out_arr(i)
- );
+ generic map (
+ g_data_w => c_data_w,
+ g_use_bsn => true,
+ g_bsn_w => 64,
+ g_use_sync => true,
+ g_fifo_size => 100
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => block_gen_src_out_arr(i),
+ snk_out => block_gen_src_in_arr(i),
+
+ src_out => dp_offload_tx_snk_in_arr(i),
+ src_in => dp_offload_tx_snk_out_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_use_complex => false,
- g_nof_words_per_block => c_nof_words_per_block,
- g_nof_blocks_per_packet => c_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_tx_snk_in_arr,
- snk_out_arr => dp_offload_tx_snk_out_arr,
-
- src_out_arr => dp_offload_tx_src_out_arr,
- src_in_arr => dp_offload_tx_src_in_arr,
-
- hdr_fields_in_arr => hdr_fields_in_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_use_complex => false,
+ g_nof_words_per_block => c_nof_words_per_block,
+ g_nof_blocks_per_packet => c_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_tx_snk_in_arr,
+ snk_out_arr => dp_offload_tx_snk_out_arr,
+
+ src_out_arr => dp_offload_tx_src_out_arr,
+ src_in_arr => dp_offload_tx_src_in_arr,
+
+ hdr_fields_in_arr => hdr_fields_in_arr
+ );
gen_hdr_in_fields : for i in 0 to c_nof_streams - 1 generate
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) downto field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000" & ID(7 downto 3) & RESIZE_UVEC(ID(2 downto 0), c_byte_w);
@@ -300,30 +302,30 @@ begin
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => true,
- g_crc_nof_words => 1
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
-
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
-
- hdr_fields_out_arr => hdr_fields_out_arr
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => true,
+ g_crc_nof_words => 1
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
);
gen_hdr_out_fields : for i in 0 to c_nof_streams - 1 generate
@@ -345,199 +347,199 @@ begin
end generate;
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => c_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => 2 * c_bg_blocks_per_sync * (c_bg_block_size + c_bg_gapsize),
- g_cnt_sop_w => ceil_log2(c_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(c_bg_blocks_per_sync * c_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => diag_data_buf_snk_out_arr,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => 2 * c_bg_blocks_per_sync * (c_bg_block_size + c_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(c_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(c_bg_blocks_per_sync * c_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => diag_data_buf_snk_out_arr,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_buf_nof_data => 1024,
- g_buf_use_sync => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sop,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sop,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl_unb1_board : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => c_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_udp_offload => true,
- g_udp_offload_nof_streams => c_nof_streams,
- g_dp_clk_use_pll => false
- )
- port map (
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => OPEN,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => dp_offload_tx_src_out_arr,
- udp_tx_siso_arr => dp_offload_tx_src_in_arr,
- udp_rx_sosi_arr => dp_offload_rx_snk_in_arr,
- udp_rx_siso_arr => dp_offload_rx_snk_out_arr,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- UniBoard FPGA pins
- CLK => '0',
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => c_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_udp_offload => true,
+ g_udp_offload_nof_streams => c_nof_streams,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => OPEN,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => dp_offload_tx_src_out_arr,
+ udp_tx_siso_arr => dp_offload_tx_src_in_arr,
+ udp_rx_sosi_arr => dp_offload_rx_snk_in_arr,
+ udp_rx_siso_arr => dp_offload_rx_snk_out_arr,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- UniBoard FPGA pins
+ CLK => '0',
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm_unb1_dp_offload : entity work.mmm_unb1_dp_offload
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_nof_streams => c_nof_streams,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- dp_clk => dp_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
-
- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_nof_streams => c_nof_streams,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ dp_clk => dp_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso
+ );
end str;
diff --git a/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
index 9faac986ed..c85e61e80c 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
@@ -38,11 +38,11 @@
-- . run -a
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_dp_offload is
end tb_unb1_dp_offload;
@@ -94,5 +94,5 @@ begin
ETH_clk => eth_clk,
ETH_SGIN => eth_lpbk,
ETH_SGOUT => eth_lpbk
- );
+ );
end tb;
diff --git a/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd b/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
index 2c46150622..52a9fd26e9 100644
--- a/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
+++ b/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
@@ -23,10 +23,10 @@
-- Description:
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_barrel_shift is
generic (
@@ -51,8 +51,9 @@ architecture str of dp_barrel_shift is
shift_out : std_logic_vector(ceil_log2(g_nof_streams) - 1 downto 0);
end record;
- constant c_reg_defaults : t_reg := ( (others => c_dp_sosi_rst),
- (others => '0') );
+ constant c_reg_defaults : t_reg := (
+ (others => c_dp_sosi_rst),
+ (others => '0') );
signal r, nxt_r : t_reg := c_reg_defaults;
begin
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
index 96e84bff32..b9c5425281 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
@@ -64,11 +64,11 @@
-- --------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_from_mm is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
index a5dbf8136b..1c36c28cff 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
@@ -40,11 +40,11 @@
-- --------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_from_mm_dc is
generic (
@@ -110,17 +110,17 @@ begin
-- if mm_start_pulse arrive one clock cycle early and mm_sync_hi arrives one
-- clock cycle late.
u_common_spulse_start_pulse : entity common_lib.common_spulse
- generic map (
- g_delay_len => c_meta_delay_len + 4
- )
- port map (
- in_rst => dp_rst,
- in_clk => dp_clk,
- in_pulse => start_pulse,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_pulse => mm_start_pulse
- );
+ generic map (
+ g_delay_len => c_meta_delay_len + 4
+ )
+ port map (
+ in_rst => dp_rst,
+ in_clk => dp_clk,
+ in_pulse => start_pulse,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_pulse => mm_start_pulse
+ );
-- The synchronous start_pulse and sync_in in the dp_clk domain cannot be
-- passed on via two separate common_spulse instances, because then they may
@@ -128,17 +128,17 @@ begin
-- dp_clk and mm_clk are asynchronous on HW. Therefore use mm_sync_level to
-- pass on sync_in.
u_common_spulse_sync : entity common_lib.common_spulse
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- in_rst => dp_rst,
- in_clk => dp_clk,
- in_pulse => sync_in,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_pulse => mm_sync_hi
- );
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ in_rst => dp_rst,
+ in_clk => dp_clk,
+ in_pulse => sync_in,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_pulse => mm_sync_hi
+ );
p_mm_sync : process(mm_clk)
begin
@@ -158,75 +158,75 @@ begin
mm_start_address <= TO_UINT(mm_start_address_slv);
u_common_async_slv_start_address : entity common_lib.common_async_slv
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => start_address_slv,
- dout => mm_start_address_slv
- );
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => start_address_slv,
+ dout => mm_start_address_slv
+ );
u_common_async_slv_bsn : entity common_lib.common_async_slv
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => bsn_at_sync,
- dout => mm_bsn_at_sync
- );
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => bsn_at_sync,
+ dout => mm_bsn_at_sync
+ );
u_dp_fifo_fill_eop : entity work.dp_fifo_fill_eop
- generic map (
- g_use_dual_clock => true,
- g_data_w => c_word_w,
- g_bsn_w => g_bsn_w,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_fill => c_fifo_fill,
- g_fifo_size => c_fifo_size
- )
- port map (
- wr_rst => mm_rst,
- wr_clk => mm_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
- -- ST sink
- snk_in => mm_fifo_sosi,
- snk_out => mm_fifo_siso,
- -- ST source
- src_out => dp_out_sosi,
- src_in => dp_out_siso
- );
+ generic map (
+ g_use_dual_clock => true,
+ g_data_w => c_word_w,
+ g_bsn_w => g_bsn_w,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_fill => c_fifo_fill,
+ g_fifo_size => c_fifo_size
+ )
+ port map (
+ wr_rst => mm_rst,
+ wr_clk => mm_clk,
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+ -- ST sink
+ snk_in => mm_fifo_sosi,
+ snk_out => mm_fifo_siso,
+ -- ST source
+ src_out => dp_out_sosi,
+ src_in => dp_out_siso
+ );
u_dp_block_from_mm : entity work.dp_block_from_mm
- generic map (
- g_user_size => g_user_size,
- g_data_size => g_data_size,
- g_step_size => g_step_size,
- g_nof_data => g_nof_data,
- g_word_w => g_word_w,
- g_reverse_word_order => g_reverse_word_order,
- g_bsn_w => g_bsn_w,
- g_bsn_incr_enable => g_bsn_incr_enable
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
-
- start_pulse => mm_start_pulse,
- sync_in => mm_sync,
- bsn_at_sync => mm_bsn_at_sync,
- start_address => mm_start_address,
- mm_done => mm_done, -- = mm_fifo_sosi.eop
- mm_mosi => mm_mosi,
- mm_miso => mm_miso,
- out_sosi => mm_fifo_sosi,
- out_siso => mm_fifo_siso
- );
+ generic map (
+ g_user_size => g_user_size,
+ g_data_size => g_data_size,
+ g_step_size => g_step_size,
+ g_nof_data => g_nof_data,
+ g_word_w => g_word_w,
+ g_reverse_word_order => g_reverse_word_order,
+ g_bsn_w => g_bsn_w,
+ g_bsn_incr_enable => g_bsn_incr_enable
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+
+ start_pulse => mm_start_pulse,
+ sync_in => mm_sync,
+ bsn_at_sync => mm_bsn_at_sync,
+ start_address => mm_start_address,
+ mm_done => mm_done, -- = mm_fifo_sosi.eop
+ mm_mosi => mm_mosi,
+ mm_miso => mm_miso,
+ out_sosi => mm_fifo_sosi,
+ out_siso => mm_fifo_siso
+ );
-- Wire output
out_sop <= dp_out_sosi.sop;
diff --git a/libraries/base/dp/src/vhdl/dp_block_gen.vhd b/libraries/base/dp/src/vhdl/dp_block_gen.vhd
index a9f997127f..8155470706 100644
--- a/libraries/base/dp/src/vhdl/dp_block_gen.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_gen.vhd
@@ -63,10 +63,10 @@
-- dp_block_reshape.vhd.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_gen is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd b/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
index 0abb80fa52..00eb68ad72 100644
--- a/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
@@ -140,10 +140,10 @@
-- allow for a fractional amount of blocks per sync period.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_gen_valid_arr is
generic (
@@ -226,17 +226,17 @@ begin
in_sync_wr_en <= (others => snk_in.sync);
u_paged_bsn : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_bsn_w,
- g_nof_pages => g_nof_pages_bsn
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => in_sync_wr_en,
- wr_dat => snk_in.bsn,
- out_dat => in_bsn_buffer
- );
+ generic map (
+ g_data_w => c_dp_stream_bsn_w,
+ g_nof_pages => g_nof_pages_bsn
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => in_sync_wr_en,
+ wr_dat => snk_in.bsn,
+ out_dat => in_bsn_buffer
+ );
p_snk_in : process(snk_in, in_bsn_buffer)
begin
@@ -332,18 +332,18 @@ begin
use_global_bsn : if g_restore_global_bsn = true generate
u_dp_bsn_restore_global : entity work.dp_bsn_restore_global
- generic map (
- g_bsn_w => c_dp_stream_bsn_w,
- g_pipeline => 0 -- pipeline registering is done via nxt_src_out_arr
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => nxt_r.reg_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_pipeline => 0 -- pipeline registering is done via nxt_src_out_arr
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => nxt_r.reg_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
end generate;
-- Combine input data with the same out_put info and output ctrl for all streams
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
index 5e1dce61c2..95025118d9 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
@@ -72,10 +72,10 @@
-- an input block stream.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_reshape is
generic (
@@ -99,9 +99,10 @@ end dp_block_reshape;
architecture str of dp_block_reshape is
constant c_nof_counters : natural := 2; -- counter [0] is used for block reshape and valid index,
- -- counter [1] is only used for sop_index
- constant c_nof_block_per_sync : natural := sel_a_b(g_input_nof_data_per_sync > g_reshape_nof_data_per_blk,
- g_input_nof_data_per_sync / g_reshape_nof_data_per_blk, 1);
+ -- counter [1] is only used for sop_index
+ constant c_nof_block_per_sync : natural := sel_a_b(
+ g_input_nof_data_per_sync > g_reshape_nof_data_per_blk,
+ g_input_nof_data_per_sync / g_reshape_nof_data_per_blk, 1);
constant c_range_start : t_nat_natural_arr(c_nof_counters - 1 downto 0) := (others => 0);
constant c_range_stop : t_nat_natural_arr(c_nof_counters - 1 downto 0) := (c_nof_block_per_sync, g_reshape_nof_data_per_blk);
@@ -111,26 +112,26 @@ architecture str of dp_block_reshape is
signal input_src_out : t_dp_sosi;
begin
u_dp_counter : entity work.dp_counter
- generic map (
- g_nof_counters => c_nof_counters,
- g_range_start => c_range_start,
- g_range_stop => c_range_stop,
- g_range_step => c_range_step,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
+ generic map (
+ g_nof_counters => c_nof_counters,
+ g_range_start => c_range_start,
+ g_range_stop => c_range_stop,
+ g_range_step => c_range_step,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
- snk_in => snk_in,
- snk_out => snk_out,
+ snk_in => snk_in,
+ snk_out => snk_out,
- src_out => input_src_out,
- src_in => src_in,
+ src_out => input_src_out,
+ src_in => src_in,
- count_src_out_arr => cnt_sosi_arr
- );
+ count_src_out_arr => cnt_sosi_arr
+ );
src_index_arr(1) <= TO_UINT(cnt_sosi_arr(1).data); -- sop index
src_index_arr(0) <= TO_UINT(cnt_sosi_arr(0).data); -- valid index
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
index d0d7039eca..9ba397219a 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
@@ -33,10 +33,10 @@
--
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_reshape_arr is
generic (
@@ -125,23 +125,23 @@ begin
-- Instantiate dp_block_reshape per stream
gen_streams : for I in 0 to g_nof_streams - 1 generate
u_block_reshape : entity work.dp_block_reshape
- generic map (
- g_input_nof_data_per_sync => g_input_nof_data_per_sync,
- g_reshape_nof_data_per_blk => g_reshape_nof_data_per_blk,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
+ generic map (
+ g_input_nof_data_per_sync => g_input_nof_data_per_sync,
+ g_reshape_nof_data_per_blk => g_reshape_nof_data_per_blk,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
- snk_in => in_sosi_arr(I),
- snk_out => in_siso_arr(I),
+ snk_in => in_sosi_arr(I),
+ snk_out => in_siso_arr(I),
- src_out => out_sosi_arr(I),
- src_in => out_siso_arr(I),
- src_index_arr => out_index_2arr_2(I)
- );
+ src_out => out_sosi_arr(I),
+ src_in => out_siso_arr(I),
+ src_index_arr => out_index_2arr_2(I)
+ );
end generate;
-- Wire index arr
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
index 2934cf719e..363e90bf04 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
@@ -65,10 +65,10 @@
-- dp_sync_insert.vhd.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_reshape_sync is
generic (
@@ -97,17 +97,19 @@ architecture str of dp_block_reshape_sync is
-- If g_input_nof_data_per_sync <= c_reshape_nof_data_per_sync then c_nof_output_sync_per_input_sync = 1, else the
-- assumption is that g_input_nof_data_per_sync is an integer multiple of c_reshape_nof_data_per_sync.
- constant c_nof_output_sync_per_input_sync : natural := sel_a_b(g_input_nof_data_per_sync > c_reshape_nof_data_per_sync,
- g_input_nof_data_per_sync / c_reshape_nof_data_per_sync, 1);
+ constant c_nof_output_sync_per_input_sync : natural := sel_a_b(
+ g_input_nof_data_per_sync > c_reshape_nof_data_per_sync,
+ g_input_nof_data_per_sync / c_reshape_nof_data_per_sync, 1);
-- counter [0] is use for block reshape,
-- counter [1] is used for sync reshape,
-- counter [2] is only used for sync_index if c_nof_output_sync_per_input_sync > 1
constant c_nof_counters : natural := sel_a_b(c_nof_output_sync_per_input_sync > 1, 3, 2);
constant c_range_start : t_nat_natural_arr(c_nof_counters - 1 downto 0) := (others => 0);
- constant c_range_stop : t_nat_natural_arr(c_nof_counters - 1 downto 0) := sel_a_b(c_nof_output_sync_per_input_sync > 1,
- (c_nof_output_sync_per_input_sync, g_reshape_nof_blk_per_sync, g_reshape_nof_data_per_blk),
- (g_reshape_nof_blk_per_sync, g_reshape_nof_data_per_blk));
+ constant c_range_stop : t_nat_natural_arr(
+ c_nof_counters - 1 downto 0) := sel_a_b(c_nof_output_sync_per_input_sync > 1,
+ (c_nof_output_sync_per_input_sync, g_reshape_nof_blk_per_sync, g_reshape_nof_data_per_blk),
+ (g_reshape_nof_blk_per_sync, g_reshape_nof_data_per_blk));
constant c_range_step : t_nat_natural_arr(c_nof_counters - 1 downto 0) := (others => 1);
signal cnt_sosi_arr : t_dp_sosi_arr(c_nof_counters - 1 downto 0);
@@ -131,26 +133,26 @@ architecture str of dp_block_reshape_sync is
signal reg_global_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
begin
u_dp_counter : entity work.dp_counter
- generic map (
- g_nof_counters => c_nof_counters,
- g_range_start => c_range_start,
- g_range_stop => c_range_stop,
- g_range_step => c_range_step,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => snk_in,
- snk_out => snk_out,
-
- src_out => input_sosi,
- src_in => input_siso,
-
- count_src_out_arr => cnt_sosi_arr
- );
+ generic map (
+ g_nof_counters => c_nof_counters,
+ g_range_start => c_range_start,
+ g_range_stop => c_range_stop,
+ g_range_step => c_range_step,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => snk_in,
+ snk_out => snk_out,
+
+ src_out => input_sosi,
+ src_in => input_siso,
+
+ count_src_out_arr => cnt_sosi_arr
+ );
gen_sync_index : if c_nof_output_sync_per_input_sync > 1 generate
sync_index <= TO_UINT(cnt_sosi_arr(2).data);
diff --git a/libraries/base/dp/src/vhdl/dp_block_resize.vhd b/libraries/base/dp/src/vhdl/dp_block_resize.vhd
index db89a82750..4c511fb58c 100644
--- a/libraries/base/dp/src/vhdl/dp_block_resize.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_resize.vhd
@@ -21,27 +21,27 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
--- Author: Eric Kooistra, 16 Mar 2018
--- Purpose:
--- Resize a block by moving the sop and or the eop of the block
--- Description:
--- The output sop and eop can be put at any index of the input block in range(g_input_block_size).
--- Any valid input data before the new sop index and after the new eop index is lost. This
--- component is useful to e.g. remove an unused head or tail of a block.
---
--- * The info at sop (sync, bsn, channel) is preserved by sop_sosi when g_out_sop_index >= 0
--- * The info at eop (empty, err) gets lost if g_out_eop_index < g_input_block_size-1, this is
--- often no issue. If it is an issue then use dp_split instead.
--- Remarks:
--- - This component supports flow control and was designed by keeping the functional
--- state registers and the pipeline registers seperate. Therefore the function is
--- implemented using combinatorial logic and local state registers to keep its
--- state. The combinatorial function output preserves the snk_in ready latency and
--- is pipelined using dp_pipeline to ease timing closure on the output.
--- A similar approach is also used with dp_counter.vhd.
+ -- Author: Eric Kooistra, 16 Mar 2018
+ -- Purpose:
+ -- Resize a block by moving the sop and or the eop of the block
+ -- Description:
+ -- The output sop and eop can be put at any index of the input block in range(g_input_block_size).
+ -- Any valid input data before the new sop index and after the new eop index is lost. This
+ -- component is useful to e.g. remove an unused head or tail of a block.
+ --
+ -- * The info at sop (sync, bsn, channel) is preserved by sop_sosi when g_out_sop_index >= 0
+ -- * The info at eop (empty, err) gets lost if g_out_eop_index < g_input_block_size-1, this is
+ -- often no issue. If it is an issue then use dp_split instead.
+ -- Remarks:
+ -- - This component supports flow control and was designed by keeping the functional
+ -- state registers and the pipeline registers seperate. Therefore the function is
+ -- implemented using combinatorial logic and local state registers to keep its
+ -- state. The combinatorial function output preserves the snk_in ready latency and
+ -- is pipelined using dp_pipeline to ease timing closure on the output.
+ -- A similar approach is also used with dp_counter.vhd.
entity dp_block_resize is
generic (
@@ -62,8 +62,8 @@ entity dp_block_resize is
end dp_block_resize;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture rtl of dp_block_resize is
signal cnt_reg : natural range 0 to g_input_block_size-1;
@@ -126,17 +126,17 @@ begin
-- Register block_sosi to easy timing closure
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => block_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => block_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_select.vhd b/libraries/base/dp/src/vhdl/dp_block_select.vhd
index 773adcfb0d..262eafb0a5 100644
--- a/libraries/base/dp/src/vhdl/dp_block_select.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_select.vhd
@@ -21,35 +21,35 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Author: Eric Kooistra, 14 Dec 2018
--- Purpose:
--- Pass on a range of blocks within a sync interval and drop the blocks
--- outside this range.
--- Description:
--- The blocks are counted from the sync using the eop. The blocks with index >= g_index_lo
--- and index <= g_index_hi are passed on. The blocks with index outside this range are
--- skipped by making there sosi control fields zero.
--- If g_index_lo > 0 then the sosi.sync and (global) sosi.bsn will be passed on via the
--- first output block. The sosi.bsn for the other blocks is not changed, so the (local)
--- sosi.bsn for the output is not restarted.
--- If g_index_hi >= g_nof_blocks_per_sync interval, then no trailing blocks are dropped.
--- The g_nof_blocks_per_sync is used to determine the size of the internal block counter.
---
--- Usage:
--- This component can be used to select a specific range of blocks within a sync interval
--- e.g. to capture one in a data buffer or to reduce the output data rate.
---
--- Remarks:
--- - This component supports flow control and was designed by keeping the functional
--- state registers and the pipeline registers seperate. Therefore the function is
--- implemented using combinatorial logic and local state registers to keep its
--- state. The combinatorial function output preserves the snk_in ready latency and
--- is pipelined using dp_pipeline to ease timing closure on the output.
--- A similar approach is also used with dp_block_resize.vhd.
+ -- Author: Eric Kooistra, 14 Dec 2018
+ -- Purpose:
+ -- Pass on a range of blocks within a sync interval and drop the blocks
+ -- outside this range.
+ -- Description:
+ -- The blocks are counted from the sync using the eop. The blocks with index >= g_index_lo
+ -- and index <= g_index_hi are passed on. The blocks with index outside this range are
+ -- skipped by making there sosi control fields zero.
+ -- If g_index_lo > 0 then the sosi.sync and (global) sosi.bsn will be passed on via the
+ -- first output block. The sosi.bsn for the other blocks is not changed, so the (local)
+ -- sosi.bsn for the output is not restarted.
+ -- If g_index_hi >= g_nof_blocks_per_sync interval, then no trailing blocks are dropped.
+ -- The g_nof_blocks_per_sync is used to determine the size of the internal block counter.
+ --
+ -- Usage:
+ -- This component can be used to select a specific range of blocks within a sync interval
+ -- e.g. to capture one in a data buffer or to reduce the output data rate.
+ --
+ -- Remarks:
+ -- - This component supports flow control and was designed by keeping the functional
+ -- state registers and the pipeline registers seperate. Therefore the function is
+ -- implemented using combinatorial logic and local state registers to keep its
+ -- state. The combinatorial function output preserves the snk_in ready latency and
+ -- is pipelined using dp_pipeline to ease timing closure on the output.
+ -- A similar approach is also used with dp_block_resize.vhd.
entity dp_block_select is
generic (
@@ -74,8 +74,8 @@ entity dp_block_select is
end dp_block_select;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture rtl of dp_block_select is
signal cnt_reg : natural range 0 to true_log_pow2(g_nof_blocks_per_sync);
@@ -140,17 +140,17 @@ begin
-- Register block_sosi to easy timing closure
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => block_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => g_pipeline -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => block_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
index 0c1cb30560..bb6f2cf947 100644
--- a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
@@ -26,11 +26,11 @@
-- --------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_to_mm is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
index a9a587e8e4..a4d39c6b39 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
@@ -61,11 +61,11 @@
-- =====================================================================
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_block_validate_bsn_at_sync is
generic (
@@ -93,11 +93,12 @@ architecture rtl of dp_block_validate_bsn_at_sync is
constant c_nof_regs : natural := 3;
constant c_clear_adr : natural := c_nof_regs - 1;
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs, -- total counter + discarded counter
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs, -- total counter + discarded counter
+ init_sl => '0');
-- Registers in st_clk domain
signal count_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
@@ -131,61 +132,61 @@ begin
-- discarded counter
u_discarded_counter : entity common_lib.common_counter
- generic map (
- g_width => c_word_w,
- g_clip => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_width => c_word_w,
+ g_clip => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_discarded_en,
- count => cnt_discarded
- );
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_discarded_en,
+ count => cnt_discarded
+ );
-- sync counter
u_blk_counter : entity common_lib.common_counter
- generic map (
- g_width => c_word_w,
- g_clip => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_width => c_word_w,
+ g_clip => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- cnt_clr => cnt_clr,
- cnt_en => in_sosi.sync,
- count => cnt_sync
- );
+ cnt_clr => cnt_clr,
+ cnt_en => in_sosi.sync,
+ count => cnt_sync
+ );
-- Register mapping
count_reg( c_word_w - 1 downto 0 ) <= cnt_discarded;
count_reg(2 * c_word_w - 1 downto c_word_w ) <= cnt_sync;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => count_reg, -- read only
- out_reg => open -- no write
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => count_reg, -- read only
+ out_reg => open -- no write
+ );
-- Process to check the bsn at sync. It captures the bsn at the sync of bs_sosi. Then compares that bsn to
-- the bsn at sync of in_sosi. If they are unequal all packets during that sync period with in_sosi.channel
@@ -254,15 +255,15 @@ begin
end process;
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => block_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => block_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
index 32c4a07830..8d21990ced 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
@@ -32,11 +32,11 @@
-- Remarks:
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_block_validate_channel is
generic (
@@ -64,16 +64,16 @@ architecture rtl of dp_block_validate_channel is
begin
assert g_mode = "=" or g_mode = "<" or g_mode = ">" report "g_mode must be one of three options: '=', '<' or '>'" severity ERROR;
gen_equal : if g_mode = "=" generate -- remove all blocks with ch = remove_channel
- remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
- '1' when unsigned(in_sosi.channel) = unsigned(remove_channel) else '0';
+ remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
+ '1' when unsigned(in_sosi.channel) = unsigned(remove_channel) else '0';
end generate;
gen_smaller : if g_mode = "<" generate -- remove all blocks with ch < remove_channel
- remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
- '1' when unsigned(in_sosi.channel) < unsigned(remove_channel) else '0';
+ remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
+ '1' when unsigned(in_sosi.channel) < unsigned(remove_channel) else '0';
end generate;
gen_larger : if g_mode = ">" generate -- remove all blocks with ch > remove_channel
- remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
- '1' when unsigned(in_sosi.channel) > unsigned(remove_channel) else '0';
+ remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
+ '1' when unsigned(in_sosi.channel) > unsigned(remove_channel) else '0';
end generate;
p_dp_clk : process(dp_rst, dp_clk)
@@ -102,28 +102,28 @@ begin
end process;
u_pipe_remove : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => remove_sosi,
- -- ST source
- src_out => out_remove_sosi
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => remove_sosi,
+ -- ST source
+ src_out => out_remove_sosi
+ );
u_pipe_keep : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => keep_sosi,
- -- ST source
- src_out => out_keep_sosi
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => keep_sosi,
+ -- ST source
+ src_out => out_keep_sosi
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
index 96b89286a1..227bcc2796 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
@@ -72,11 +72,11 @@
-- ====================================================================================
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_block_validate_err is
generic (
@@ -126,11 +126,12 @@ architecture rtl of dp_block_validate_err is
type t_cnt_err_arr is array (integer range <>) of std_logic_vector(g_cnt_w - 1 downto 0);
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0');
-- Registers in st_clk domain
signal ref_sync_reg : std_logic := '0';
@@ -188,39 +189,22 @@ begin
-- block counter
cnt_blk_en <= cnt_this_eop;
u_blk_counter : entity common_lib.common_counter
- generic map (
- g_width => g_blk_cnt_w,
- g_clip => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- cnt_clr => cnt_clr,
- cnt_en => cnt_blk_en,
- count => cnt_blk
- );
+ generic map (
+ g_width => g_blk_cnt_w,
+ g_clip => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_blk_en,
+ count => cnt_blk
+ );
-- discarded block counter
cnt_discarded_en <= cnt_this_eop when TO_UINT(snk_in.err(g_nof_err_counts - 1 downto 0)) > 0 else '0';
u_discarded_counter : entity common_lib.common_counter
- generic map (
- g_width => g_cnt_w,
- g_clip => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- cnt_clr => cnt_clr,
- cnt_en => cnt_discarded_en,
- count => cnt_discarded
- );
-
- -- error counters
- gen_err_counters : for I in 0 to g_nof_err_counts - 1 generate
- cnt_err_en_arr(I) <= cnt_this_eop and snk_in.err(I);
- u_blk_counter : entity common_lib.common_counter
generic map (
g_width => g_cnt_w,
g_clip => true
@@ -230,9 +214,26 @@ begin
clk => dp_clk,
cnt_clr => cnt_clr,
- cnt_en => cnt_err_en_arr(I),
- count => cnt_err_arr(I)
+ cnt_en => cnt_discarded_en,
+ count => cnt_discarded
);
+
+ -- error counters
+ gen_err_counters : for I in 0 to g_nof_err_counts - 1 generate
+ cnt_err_en_arr(I) <= cnt_this_eop and snk_in.err(I);
+ u_blk_counter : entity common_lib.common_counter
+ generic map (
+ g_width => g_cnt_w,
+ g_clip => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_err_en_arr(I),
+ count => cnt_err_arr(I)
+ );
end generate;
-- Hold counter values at ref_sync_reg to have stable values for MM read for comparision between nodes
@@ -269,71 +270,71 @@ begin
end generate;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => count_reg, -- read only
- out_reg => open -- no write
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => count_reg, -- read only
+ out_reg => open -- no write
+ );
u_fifo_fill_eop : entity work.dp_fifo_fill_eop
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_max_block_size,
- g_fifo_size => g_fifo_size
- )
- port map (
- wr_rst => dp_rst,
- wr_clk => dp_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
-
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => block_siso,
- src_out => block_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_max_block_size,
+ g_fifo_size => g_fifo_size
+ )
+ port map (
+ wr_rst => dp_rst,
+ wr_clk => dp_clk,
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => block_siso,
+ src_out => block_sosi
+ );
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out => block_siso,
- snk_in => block_sosi,
- -- ST source
- src_in => src_in,
- src_out => block_sosi_piped
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => block_siso,
+ snk_in => block_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => block_sosi_piped
+ );
p_dp_clk : process(dp_rst, dp_clk)
begin
@@ -349,19 +350,19 @@ begin
err_ok <= not vector_or(snk_in.err(g_nof_err_counts - 1 downto 0)) when snk_in.eop = '1' else err_ok_reg;
u_fifo_err_ok : entity common_lib.common_fifo_sc
- generic map (
- g_dat_w => 1,
- g_nof_words => c_nof_err_ok
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- wr_dat(0) => err_ok,
- wr_req => snk_in.eop,
- rd_req => block_sosi.sop,
- rd_dat(0) => fifo_err_ok,
- rd_val => fifo_err_ok_val
- );
+ generic map (
+ g_dat_w => 1,
+ g_nof_words => c_nof_err_ok
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ wr_dat(0) => err_ok,
+ wr_req => snk_in.eop,
+ rd_req => block_sosi.sop,
+ rd_dat(0) => fifo_err_ok,
+ rd_val => fifo_err_ok_val
+ );
out_valid <= fifo_err_ok when fifo_err_ok_val = '1' else out_valid_reg;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
index d523cc1506..321909ee59 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
@@ -43,8 +43,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
entity dp_block_validate_length is
generic (
@@ -111,17 +111,17 @@ begin
-- Register block_sosi to easy timing closure
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => block_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => block_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
index f8c6daeaf2..a587e74829 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
@@ -20,118 +20,118 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-
--- Future note:
--- The dp_bsn_align aligns at BSN level. In retrospect it is probably
--- sufficient and easier to align at sync level. This can be done in a new
--- component dp_sync_align. The dp_sync_align then waits for the sync in
--- all streams and then declares alignment. The sync interval is longer than
--- a BSN interval so sync alignment will take longer to achieve. However this
--- is no disadvantage, because typically the system remains aligned after the
--- initial alignment.
--- Per stream it or for all streams together it may be necessary to have
--- monitors to detect misalignment. These can be used to detect:
--- . corrupted blocks due to input FIFO overflow by means of valid cnt from
--- sop to eop = g_block_size and valid cnt from eop to sop = 0.
--- . missing blocks or out of order blocks by means of the incrementing BSN.
--- . sync timeout (similar to sop timeout in dp_bsn_align).
---
--- Purpose:
--- Align frames from multiple input streams
---
--- Description:
---
--- BSN alignment:
--- The frame alignment is based on the BSN of the enabled inputs. Initially
--- and when the BSN differ too much then the inputs get flushed via s_xoff.
--- The inputs are then flushed for g_xoff_timeout cycles. Using a preset
--- timeout is easier and more robust dynamically determining the flush time
--- based on monitoring the inputs states.
--- When the BSN differ less than g_bsn_latency, then the maximum of all BSN
--- is determined and the inputs that have not yet reached this BSN are read
--- until they have. When all inputs have the same BSN pending, then they are
--- output per frame. After every frame the BSN alignment is checked and the
--- frame output continues if the alignment is still OK, else the function
--- tries to recover the BSN aligmnent.
--- The assumption is that the data blocks arrive almost at the same time at
--- the inputs. The g_bsn_latency defines the maximum number of blocks that
--- their arrival may differ. Therefor each input stream needs an external
--- FIFO that can at least buffer g_bsn_latency number of blocks, so
--- c_input_fifo_size >= g_bsn_latency * g_block_size. Typically if all inputs
--- are transmitted at the same instant then they will arrive with at within
--- +-1 BSN difference, but it can be more dependent on the buffering and
--- multiplexing that occurs for each input from tx to rx. Default using +-3
--- seems a save marging so g_bsn_latency = 3. Choosing g_bsn_latency larger
--- than needed costs extra logic for the BSN comparison and extra RAM for
--- the input FIFO buffering.
--- The data blocks arrive with gaps in between them, the block size + average
--- gap size is equal to the g_block_period with which the data blocks were
--- generated. This g_block_period is e.g. 256 cycles and is used as a unit
--- for the g_xoff_timeout and the g_sop_timeout.
---
--- Input FIFO size and sop and xoff timeouts:
---
--- For example for:
--- g_bsn_latency = 3
--- g_block_size = 32
--- g_block_period = 256
--- use:
--- c_input_fifo_size >= (g_bsn_latency + 2) * g_block_size -- of external FIFO
--- g_sop_timeout = (g_bsn_latency + 1) * g_block_period
--- g_xoff_timeout = g_bsn_latency * 2 * g_block_period
---
--- The g_sop_timeout makes sure that an attempt to align the input stream is
--- ended if it does not succeed within g_sop_timeout clock cycles. The
--- worst case time to align is about g_block_period * g_bsn_latency, because
--- more time difference between the input streams can not occur during
--- normal operation. Choose g_sop_timeout +1 period larger.
--- The g_sop_timeout also avoids that the input FIFOs will get full.
--- Choosing g_sop_timeout too large may cause some input FIFOs to get full,
--- but that is probably no problem because the BSN aligner will then still
--- recover anyway. Therefore choose the input FIFO size a little larger
--- to fit all blocks that can arrive during a sop timeout, hence choose
--- c_input_fifo_size +2 blocks larger.
--- To recover from a failed alignment the xoff is used. The xoff makes sure
--- that the rx of new input frames is stopped and that the input FIFOs get
--- flushed. The g_xoff_timeout must be long enough to ensure that all input
--- FIFOs are empty. Hence typically g_xoff_timeout must be equal to the input
--- FIFO size, so about g_bsn_latency*g_block_size. However it is bad to flush
--- to short and fine to flush longer than needed. Therefor add a factor 2
--- extra to g_xoff_timeout and use g_block_period instead of g_block_size.
---
--- External input fill FIFO:
--- The BSN aligner can only cope with gaps in the snk_in_arr valid if they
--- occur the same for all inputs. Otherwise the inputs need to be put through
--- a dp_fifo_fill that fills >= 1 * g_block_period to ensure that after the
--- alignment at the sop the inputs deliver valid data for the whole frame,
--- so for every src_in ready there then is valid output.
---
--- Remark:
--- . Using g_nof_input=1 is transparent.
--- . The xoff is used for coarse flow control over blocks of data to recover
--- from start up mis alignment or an rx input that briefly misses a burst of
--- data. The ready is used for the fine flow per clock cycle to align on the
--- inputs at their sop's.
--- . The assumption is that data from the upstream inputs can be stopped via
--- xoff or have a dp_flush that can be enabled via xoff to empty all input
--- streams.
--- . The number of outputs is also g_nof_input. All outputs, including those
--- for the inputs that are not enabled, have the same sosi control signalling
--- (sync, valid, sop and eop). Therefore a downstream sink only needs to use
--- the control from one output, typically output 0. For the inputs that are
--- not enabled the sosi data fields are forced to 0.
--- . The input block sizes must match the g_block_size. Using g_block_size an
--- internally generated reference block is used to set the sosi control
--- during the frame output. The advantage of using this internal reference
--- block generator is that it does not depend on the in_en_arr settings.
--- . It was also considered to have a state machine per input, but later on it
--- was though easier to use only a single state machine and vectored input
--- control.
---
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+
+ -- Future note:
+ -- The dp_bsn_align aligns at BSN level. In retrospect it is probably
+ -- sufficient and easier to align at sync level. This can be done in a new
+ -- component dp_sync_align. The dp_sync_align then waits for the sync in
+ -- all streams and then declares alignment. The sync interval is longer than
+ -- a BSN interval so sync alignment will take longer to achieve. However this
+ -- is no disadvantage, because typically the system remains aligned after the
+ -- initial alignment.
+ -- Per stream it or for all streams together it may be necessary to have
+ -- monitors to detect misalignment. These can be used to detect:
+ -- . corrupted blocks due to input FIFO overflow by means of valid cnt from
+ -- sop to eop = g_block_size and valid cnt from eop to sop = 0.
+ -- . missing blocks or out of order blocks by means of the incrementing BSN.
+ -- . sync timeout (similar to sop timeout in dp_bsn_align).
+ --
+ -- Purpose:
+ -- Align frames from multiple input streams
+ --
+ -- Description:
+ --
+ -- BSN alignment:
+ -- The frame alignment is based on the BSN of the enabled inputs. Initially
+ -- and when the BSN differ too much then the inputs get flushed via s_xoff.
+ -- The inputs are then flushed for g_xoff_timeout cycles. Using a preset
+ -- timeout is easier and more robust dynamically determining the flush time
+ -- based on monitoring the inputs states.
+ -- When the BSN differ less than g_bsn_latency, then the maximum of all BSN
+ -- is determined and the inputs that have not yet reached this BSN are read
+ -- until they have. When all inputs have the same BSN pending, then they are
+ -- output per frame. After every frame the BSN alignment is checked and the
+ -- frame output continues if the alignment is still OK, else the function
+ -- tries to recover the BSN aligmnent.
+ -- The assumption is that the data blocks arrive almost at the same time at
+ -- the inputs. The g_bsn_latency defines the maximum number of blocks that
+ -- their arrival may differ. Therefor each input stream needs an external
+ -- FIFO that can at least buffer g_bsn_latency number of blocks, so
+ -- c_input_fifo_size >= g_bsn_latency * g_block_size. Typically if all inputs
+ -- are transmitted at the same instant then they will arrive with at within
+ -- +-1 BSN difference, but it can be more dependent on the buffering and
+ -- multiplexing that occurs for each input from tx to rx. Default using +-3
+ -- seems a save marging so g_bsn_latency = 3. Choosing g_bsn_latency larger
+ -- than needed costs extra logic for the BSN comparison and extra RAM for
+ -- the input FIFO buffering.
+ -- The data blocks arrive with gaps in between them, the block size + average
+ -- gap size is equal to the g_block_period with which the data blocks were
+ -- generated. This g_block_period is e.g. 256 cycles and is used as a unit
+ -- for the g_xoff_timeout and the g_sop_timeout.
+ --
+ -- Input FIFO size and sop and xoff timeouts:
+ --
+ -- For example for:
+ -- g_bsn_latency = 3
+ -- g_block_size = 32
+ -- g_block_period = 256
+ -- use:
+ -- c_input_fifo_size >= (g_bsn_latency + 2) * g_block_size -- of external FIFO
+ -- g_sop_timeout = (g_bsn_latency + 1) * g_block_period
+ -- g_xoff_timeout = g_bsn_latency * 2 * g_block_period
+ --
+ -- The g_sop_timeout makes sure that an attempt to align the input stream is
+ -- ended if it does not succeed within g_sop_timeout clock cycles. The
+ -- worst case time to align is about g_block_period * g_bsn_latency, because
+ -- more time difference between the input streams can not occur during
+ -- normal operation. Choose g_sop_timeout +1 period larger.
+ -- The g_sop_timeout also avoids that the input FIFOs will get full.
+ -- Choosing g_sop_timeout too large may cause some input FIFOs to get full,
+ -- but that is probably no problem because the BSN aligner will then still
+ -- recover anyway. Therefore choose the input FIFO size a little larger
+ -- to fit all blocks that can arrive during a sop timeout, hence choose
+ -- c_input_fifo_size +2 blocks larger.
+ -- To recover from a failed alignment the xoff is used. The xoff makes sure
+ -- that the rx of new input frames is stopped and that the input FIFOs get
+ -- flushed. The g_xoff_timeout must be long enough to ensure that all input
+ -- FIFOs are empty. Hence typically g_xoff_timeout must be equal to the input
+ -- FIFO size, so about g_bsn_latency*g_block_size. However it is bad to flush
+ -- to short and fine to flush longer than needed. Therefor add a factor 2
+ -- extra to g_xoff_timeout and use g_block_period instead of g_block_size.
+ --
+ -- External input fill FIFO:
+ -- The BSN aligner can only cope with gaps in the snk_in_arr valid if they
+ -- occur the same for all inputs. Otherwise the inputs need to be put through
+ -- a dp_fifo_fill that fills >= 1 * g_block_period to ensure that after the
+ -- alignment at the sop the inputs deliver valid data for the whole frame,
+ -- so for every src_in ready there then is valid output.
+ --
+ -- Remark:
+ -- . Using g_nof_input=1 is transparent.
+ -- . The xoff is used for coarse flow control over blocks of data to recover
+ -- from start up mis alignment or an rx input that briefly misses a burst of
+ -- data. The ready is used for the fine flow per clock cycle to align on the
+ -- inputs at their sop's.
+ -- . The assumption is that data from the upstream inputs can be stopped via
+ -- xoff or have a dp_flush that can be enabled via xoff to empty all input
+ -- streams.
+ -- . The number of outputs is also g_nof_input. All outputs, including those
+ -- for the inputs that are not enabled, have the same sosi control signalling
+ -- (sync, valid, sop and eop). Therefore a downstream sink only needs to use
+ -- the control from one output, typically output 0. For the inputs that are
+ -- not enabled the sosi data fields are forced to 0.
+ -- . The input block sizes must match the g_block_size. Using g_block_size an
+ -- internally generated reference block is used to set the sosi control
+ -- during the frame output. The advantage of using this internal reference
+ -- block generator is that it does not depend on the in_en_arr settings.
+ -- . It was also considered to have a state machine per input, but later on it
+ -- was though easier to use only a single state machine and vectored input
+ -- control.
+ --
entity dp_bsn_align is
generic (
@@ -233,67 +233,67 @@ begin
-- control user input enable updates to not occur during a block
u_in_en_new : entity common_lib.common_switch
- generic map (
- g_rst_level => '0',
- g_priority_lo => false,
- g_or_high => false,
- g_and_low => false
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => in_en_evt,
- switch_low => in_en_ack,
- out_level => in_en_new
- );
+ generic map (
+ g_rst_level => '0',
+ g_priority_lo => false,
+ g_or_high => false,
+ g_and_low => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => in_en_evt,
+ switch_low => in_en_ack,
+ out_level => in_en_new
+ );
-- block reference
u_block_gen : entity work.dp_block_gen
- generic map (
- g_nof_data => g_block_size,
- g_empty => 0,
- g_channel => 0,
- g_error => 0
- )
- port map (
- rst => rst,
- clk => clk,
- -- Streaming source
- src_in => blk_siso,
- src_out => blk_sosi,
- -- MM control
- en => blk_en
- );
+ generic map (
+ g_nof_data => g_block_size,
+ g_empty => 0,
+ g_channel => 0,
+ g_error => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Streaming source
+ src_in => blk_siso,
+ src_out => blk_sosi,
+ -- MM control
+ en => blk_en
+ );
-- Hold the sink input to be able to register the source output
u_block_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => blk_siso, -- wired blk_siso = hold_blk_in
- snk_in => blk_sosi,
- -- ST source
- src_in => hold_blk_in,
- next_src_out => next_blk_buf,
- pend_src_out => OPEN,
- src_out_reg => r.blk_buf
- );
-
- gen_inputs : for I in g_nof_input - 1 downto 0 generate
- u_hold : entity work.dp_hold_input
port map (
rst => rst,
clk => clk,
-- ST sink
- snk_out => OPEN,
- snk_in => snk_in_arr(I),
+ snk_out => blk_siso, -- wired blk_siso = hold_blk_in
+ snk_in => blk_sosi,
-- ST source
- src_in => hold_src_in_arr(I),
- next_src_out => next_src_buf_arr(I),
- pend_src_out => pend_src_buf_arr(I),
- src_out_reg => r.src_buf_arr(I)
+ src_in => hold_blk_in,
+ next_src_out => next_blk_buf,
+ pend_src_out => OPEN,
+ src_out_reg => r.blk_buf
);
+
+ gen_inputs : for I in g_nof_input - 1 downto 0 generate
+ u_hold : entity work.dp_hold_input
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => hold_src_in_arr(I),
+ next_src_out => next_src_buf_arr(I),
+ pend_src_out => pend_src_buf_arr(I),
+ src_out_reg => r.src_buf_arr(I)
+ );
end generate;
-- This is not Erlang or Haskell, but that does not mean that we can not do some functional programming in VHDL as well.
@@ -325,38 +325,38 @@ begin
-- Use tree instead of folding to ease timing closure:
-- pend_bsn_max <= func_dp_stream_arr_bsn_max(pend_src_buf_arr, r.in_en_arr, c_bsn_align_w);
u_pend_bsn_max : entity common_lib.common_operation_tree
- generic map (
- g_operation => "MAX",
- g_representation => "UNSIGNED",
- g_pipeline => c_bsn_stage_pipeline, -- amount of output pipelining per stage
- g_pipeline_mod => c_bsn_stage_pipeline_mod, -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
- g_nof_inputs => g_nof_input,
- g_dat_w => c_bsn_align_w
- )
- port map (
- clk => clk,
- in_data_vec => pend_bsn_vec,
- in_en_vec => r.in_en_arr,
- result => pend_bsn_max
- );
+ generic map (
+ g_operation => "MAX",
+ g_representation => "UNSIGNED",
+ g_pipeline => c_bsn_stage_pipeline, -- amount of output pipelining per stage
+ g_pipeline_mod => c_bsn_stage_pipeline_mod, -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
+ g_nof_inputs => g_nof_input,
+ g_dat_w => c_bsn_align_w
+ )
+ port map (
+ clk => clk,
+ in_data_vec => pend_bsn_vec,
+ in_en_vec => r.in_en_arr,
+ result => pend_bsn_max
+ );
-- Use tree instead of folding to ease timing closure:
-- pend_bsn_min <= func_dp_stream_arr_bsn_min(pend_src_buf_arr, r.in_en_arr, c_bsn_align_w);
u_pend_bsn_min : entity common_lib.common_operation_tree
- generic map (
- g_operation => "MIN",
- g_representation => "UNSIGNED",
- g_pipeline => c_bsn_stage_pipeline, -- amount of output pipelining per stage
- g_pipeline_mod => c_bsn_stage_pipeline_mod, -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
- g_nof_inputs => g_nof_input,
- g_dat_w => c_bsn_align_w
- )
- port map (
- clk => clk,
- in_data_vec => pend_bsn_vec,
- in_en_vec => r.in_en_arr,
- result => pend_bsn_min
- );
+ generic map (
+ g_operation => "MIN",
+ g_representation => "UNSIGNED",
+ g_pipeline => c_bsn_stage_pipeline, -- amount of output pipelining per stage
+ g_pipeline_mod => c_bsn_stage_pipeline_mod, -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
+ g_nof_inputs => g_nof_input,
+ g_dat_w => c_bsn_align_w
+ )
+ port map (
+ clk => clk,
+ in_data_vec => pend_bsn_vec,
+ in_en_vec => r.in_en_arr,
+ result => pend_bsn_min
+ );
-- Hold input registers
nxt_r.blk_buf <= next_blk_buf;
@@ -461,7 +461,7 @@ begin
nxt_r.timeout_cnt <= (others => '0');
nxt_r.state <= s_xoff;
end if;
- -- check user input enable control (must use 'ELSIF' and not 'END IF; IF', to properly handle case where both conditions are TRUE at same clock cycle)
+ -- check user input enable control (must use 'ELSIF' and not 'END IF; IF', to properly handle case where both conditions are TRUE at same clock cycle)
elsif in_en_new = '1' then
-- need to use updated user input enable settings, so flush all inputs and try to align again
nxt_r.timeout_cnt <= (others => '0');
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
index e2f93b3baf..7c549982c8 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
@@ -40,9 +40,9 @@
-- |-----------------------------------------------------------------------|
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_align_reg is
generic (
@@ -68,11 +68,12 @@ end dp_bsn_align_reg;
architecture str of dp_bsn_align_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_input),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => g_nof_input,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_input),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => g_nof_input,
+ init_sl => '0');
-- FUNCTION array_init(init : NATURAL; nof, width : NATURAL) RETURN STD_LOGIC_VECTOR; -- useful to init an unconstrained std_logic_vector with repetitive content
constant c_reg_init : std_logic_vector(g_nof_input * c_word_w - 1 downto 0) := array_init(1, g_nof_input, c_word_w);
@@ -82,32 +83,32 @@ architecture str of dp_bsn_align_reg is
signal reg_wr_arr : std_logic_vector(g_nof_input - 1 downto 0) := (others => '0');
begin
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1,
- g_readback => true,
- g_reg => c_mm_reg,
- g_init_reg => RESIZE_UVEC(c_reg_init, c_mem_reg_init_w) -- RESIZE_UVEC(TO_UVEC(1, c_word_w), c_mem_reg_init_w)
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1,
+ g_readback => true,
+ g_reg => c_mm_reg,
+ g_init_reg => RESIZE_UVEC(c_reg_init, c_mem_reg_init_w) -- RESIZE_UVEC(TO_UVEC(1, c_word_w), c_mem_reg_init_w)
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => sla_in,
- sla_out => sla_out,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => sla_in,
+ sla_out => sla_out,
- -- MM registers in st_clk domain
- reg_wr_arr => reg_wr_arr,
- reg_rd_arr => OPEN,
- in_new => OPEN,
- in_reg => out_en_arr_reg, -- read
- out_reg => out_en_arr_reg, -- write
- out_new => out_en_evt
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => reg_wr_arr,
+ reg_rd_arr => OPEN,
+ in_new => OPEN,
+ in_reg => out_en_arr_reg, -- read
+ out_reg => out_en_arr_reg, -- write
+ out_new => out_en_evt
+ );
gen_out_arr : for I in 0 to g_nof_input - 1 generate
out_en_arr(I) <= out_en_arr_reg(I * c_word_w);
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
index 9042f050f7..fa301bee27 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
@@ -48,11 +48,11 @@
-- robust.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_align_v2 is
generic (
@@ -96,11 +96,12 @@ architecture rtl of dp_bsn_align_v2 is
constant c_buffer_nof_blocks : natural := true_log_pow2(1 + g_nof_aligners_max * g_bsn_latency_max);
constant c_ram_size : natural := c_buffer_nof_blocks * g_block_size;
- constant c_ram_buf : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_ram_size),
- dat_w => g_data_w,
- nof_dat => c_ram_size,
- init_sl => '0');
+ constant c_ram_buf : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_ram_size),
+ dat_w => g_data_w,
+ nof_dat => c_ram_size,
+ init_sl => '0');
-- Use +1 to ensure that g_block_size that is power of 2 also fits in c_block_size_slv
constant c_block_size_w : natural := ceil_log2(g_block_size + 1);
@@ -155,27 +156,29 @@ architecture rtl of dp_bsn_align_v2 is
out_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
end record;
- constant c_reg_rst : t_reg := (0,
- (others => c_mem_copi_rst),
- (others => (others => '0')),
- (others => '0'),
- (others => '0'),
- (others => (others => '0')),
- c_dp_sosi_rst,
- c_dp_sosi_rst,
- 0,
- (others => '0'),
- c_mem_copi_rst,
- (others => c_mem_cipo_rst),
- (others => '0'),
- (others => (others => '0')),
- (others => '0'));
-
- constant c_comb_rst : t_comb := (c_dp_sosi_rst,
- (others => '0'),
- (others => '0'),
- (others => '0'),
- (others => c_dp_sosi_rst));
+ constant c_reg_rst : t_reg := (
+ 0,
+ (others => c_mem_copi_rst),
+ (others => (others => '0')),
+ (others => '0'),
+ (others => '0'),
+ (others => (others => '0')),
+ c_dp_sosi_rst,
+ c_dp_sosi_rst,
+ 0,
+ (others => '0'),
+ c_mem_copi_rst,
+ (others => c_mem_cipo_rst),
+ (others => '0'),
+ (others => (others => '0')),
+ (others => '0'));
+
+ constant c_comb_rst : t_comb := (
+ c_dp_sosi_rst,
+ (others => '0'),
+ (others => '0'),
+ (others => '0'),
+ (others => c_dp_sosi_rst));
-- State registers for p_comb
signal r : t_reg;
@@ -364,7 +367,7 @@ begin
-- . pass on input data from the buffer
w.out_sosi_arr := rd_sosi_arr; -- = v.fill_cipo_arr in streaming format, contains the
- -- input data from the buffer or replacement data
+ -- input data from the buffer or replacement data
if rd_sosi_arr(0).sop = '1' then
-- . at sop pass on input info from r.dp_sosi to all streams in out_sosi_arr
w.out_sosi_arr := func_dp_stream_arr_set(w.out_sosi_arr, r.dp_sosi.sync, "SYNC");
@@ -383,8 +386,8 @@ begin
-- . until next sop pass on BSN to all streams, to ease view in wave window
w.out_sosi_arr := func_dp_stream_arr_set(w.out_sosi_arr, r.out_bsn, "BSN");
for I in 0 to g_nof_streams - 1 loop
- -- . until next sop pass on channel bit 0 per stream, to ease view in wave window
- w.out_sosi_arr(I).channel := RESIZE_DP_CHANNEL(r.out_channel_arr(I));
+ -- . until next sop pass on channel bit 0 per stream, to ease view in wave window
+ w.out_sosi_arr(I).channel := RESIZE_DP_CHANNEL(r.out_channel_arr(I));
end loop;
end if;
@@ -410,20 +413,20 @@ begin
gen_data_buffer : for I in 0 to g_nof_streams - 1 generate
u_data_buffer : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram_buf
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- wr_en => r.wr_copi_arr(I).wr,
- wr_adr => r.wr_copi_arr(I).address(c_ram_buf.adr_w - 1 downto 0),
- wr_dat => r.wr_copi_arr(I).wrdata(c_ram_buf.dat_w - 1 downto 0),
- rd_en => rd_copi.rd,
- rd_adr => rd_copi.address(c_ram_buf.adr_w - 1 downto 0),
- rd_dat => rd_cipo_arr(I).rddata(c_ram_buf.dat_w - 1 downto 0),
- rd_val => rd_cipo_arr(I).rdval
- );
+ generic map (
+ g_ram => c_ram_buf
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ wr_en => r.wr_copi_arr(I).wr,
+ wr_adr => r.wr_copi_arr(I).address(c_ram_buf.adr_w - 1 downto 0),
+ wr_dat => r.wr_copi_arr(I).wrdata(c_ram_buf.dat_w - 1 downto 0),
+ rd_en => rd_copi.rd,
+ rd_adr => rd_copi.address(c_ram_buf.adr_w - 1 downto 0),
+ rd_dat => rd_cipo_arr(I).rddata(c_ram_buf.dat_w - 1 downto 0),
+ rd_val => rd_cipo_arr(I).rdval
+ );
end generate;
------------------------------------------------------------------------------
@@ -433,26 +436,26 @@ begin
gen_streaming_output : if not g_use_mm_output generate
gen_mm_to_dp : for I in 0 to g_nof_streams - 1 generate
u_mm_to_dp: entity work.dp_block_from_mm
- generic map (
- g_user_size => 1,
- g_data_size => 1,
- g_step_size => 1,
- g_nof_data => g_block_size,
- g_word_w => g_data_w,
- g_mm_rd_latency => g_rd_latency,
- g_reverse_word_order => false
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- start_pulse => r.mm_sosi.sop,
- start_address => 0,
- mm_done => dp_done_arr(I),
- mm_mosi => dp_copi_arr(I),
- mm_miso => nxt_r.fill_cipo_arr(I),
- out_sosi => rd_sosi_arr(I),
- out_siso => c_dp_siso_rdy
- );
+ generic map (
+ g_user_size => 1,
+ g_data_size => 1,
+ g_step_size => 1,
+ g_nof_data => g_block_size,
+ g_word_w => g_data_w,
+ g_mm_rd_latency => g_rd_latency,
+ g_reverse_word_order => false
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ start_pulse => r.mm_sosi.sop,
+ start_address => 0,
+ mm_done => dp_done_arr(I),
+ mm_mosi => dp_copi_arr(I),
+ mm_miso => nxt_r.fill_cipo_arr(I),
+ out_sosi => rd_sosi_arr(I),
+ out_siso => c_dp_siso_rdy
+ );
end generate;
-- Use dp_copi_arr(0) to read same addresses in parallel for all streams
@@ -465,16 +468,16 @@ begin
------------------------------------------------------------------------------
gen_cnt_replace : for I in 0 to g_nof_streams - 1 generate
u_cnt_replace : entity common_lib.common_counter
- generic map (
- g_width => c_word_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- cnt_clr => in_sosi_arr_p(0).sync,
- cnt_en => r.replace_cnt_en_arr(I),
- count => replace_cnt_arr(I)
- );
+ generic map (
+ g_width => c_word_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ cnt_clr => in_sosi_arr_p(0).sync,
+ cnt_en => r.replace_cnt_en_arr(I),
+ count => replace_cnt_arr(I)
+ );
end generate;
nxt_hold_replace_cnt_arr <= replace_cnt_arr when in_sosi_arr_p(0).sync = '1' else hold_replace_cnt_arr;
@@ -487,34 +490,34 @@ begin
-- . input streams
u_in_sosi_arr_p : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => g_pipeline_input -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_out_arr => in_sosi_arr_p
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => g_pipeline_input -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_out_arr => in_sosi_arr_p
+ );
-- . read RAM
rd_copi <= nxt_r.rd_copi when g_rd_latency = 1 else r.rd_copi;
-- . output streams
u_out_sosi_arr_p : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => g_pipeline_output
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => comb_out_sosi_arr,
- -- ST source
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => g_pipeline_output
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => comb_out_sosi_arr,
+ -- ST source
+ src_out_arr => out_sosi_arr
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd b/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
index fe7e368060..f13afbd2e3 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
@@ -20,49 +20,49 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose : Delay the input sync and BSN so they remain aligned to the data
--- path processing.
--- Description:
--- The out_release of the data path processing forms the release trigger for
--- the sync and the BSN. The delay is static (fixed) regarding the number of
--- blocks and can be 0 or more blocks and is set by g_nof_block_latency. The
--- delay is dynamic regarding the back pressure ready signal and can handle
--- any data processing logic latency >= 1 clock cycles.
--- Issues:
--- . The in_sync can occur during data invalid, so when in_eop = '0'. The
--- BSN timing must be robust for this.
--- . Connecting out_release to an early out_sop can cause that the out_sync
--- occurs during data invalid.
--- . Connecting out_release to out_eop ensures that the out_sync occurs during
--- valid but can cause the output sync and BSN to be 1 block early in case
--- the out_eop occurs before the in_eop (e.g. if the DP block outputs smaller
--- blocks than that it gets at its input).
--- ==> The dp_latency_adapter can now pass on a sync during data not valid. So
--- it is now possible to connect out_release to an early out_sop.
--- Remarks:
--- . The sync and BSN can not be delayed by a fixed latency, because the data
--- path processing may use dynamic back pressure using the ready signal.
--- Therefore this dp_bsn_delay uses out_release to release the sync and BSN.
--- . About dynamic block delay support.
--- - A data path function that can store and forward a dynamic number of
--- blocks can not use this dp_bsn_delay, because g_nof_block_latency is a
--- generic. Perhaps the block latency can be made dynamic by monitoring the
--- number of out_release that occured relative to the number of in_eop. The
--- g_nof_block_latency then sets the maximum that is supported.
--- - Alternatively, and probably better, the sync and BSN can be put through
--- a separate FIFO that is written by the in_eop and read by the
--- out_release. The FIFO can then have RL=0 so that the read sync becomes
--- out_sync directly and the read bsn then becomes out_bsn after a register
--- stage.
--- Putting the sync and BSN through the same FIFO as the data and sop, eop
--- consumes quite some RAM since the BSN is typically 48 bit wide and it
--- then needs to be pass through through the FIFO for every valid clock
--- cycle.
+ -- Purpose : Delay the input sync and BSN so they remain aligned to the data
+ -- path processing.
+ -- Description:
+ -- The out_release of the data path processing forms the release trigger for
+ -- the sync and the BSN. The delay is static (fixed) regarding the number of
+ -- blocks and can be 0 or more blocks and is set by g_nof_block_latency. The
+ -- delay is dynamic regarding the back pressure ready signal and can handle
+ -- any data processing logic latency >= 1 clock cycles.
+ -- Issues:
+ -- . The in_sync can occur during data invalid, so when in_eop = '0'. The
+ -- BSN timing must be robust for this.
+ -- . Connecting out_release to an early out_sop can cause that the out_sync
+ -- occurs during data invalid.
+ -- . Connecting out_release to out_eop ensures that the out_sync occurs during
+ -- valid but can cause the output sync and BSN to be 1 block early in case
+ -- the out_eop occurs before the in_eop (e.g. if the DP block outputs smaller
+ -- blocks than that it gets at its input).
+ -- ==> The dp_latency_adapter can now pass on a sync during data not valid. So
+ -- it is now possible to connect out_release to an early out_sop.
+ -- Remarks:
+ -- . The sync and BSN can not be delayed by a fixed latency, because the data
+ -- path processing may use dynamic back pressure using the ready signal.
+ -- Therefore this dp_bsn_delay uses out_release to release the sync and BSN.
+ -- . About dynamic block delay support.
+ -- - A data path function that can store and forward a dynamic number of
+ -- blocks can not use this dp_bsn_delay, because g_nof_block_latency is a
+ -- generic. Perhaps the block latency can be made dynamic by monitoring the
+ -- number of out_release that occured relative to the number of in_eop. The
+ -- g_nof_block_latency then sets the maximum that is supported.
+ -- - Alternatively, and probably better, the sync and BSN can be put through
+ -- a separate FIFO that is written by the in_eop and read by the
+ -- out_release. The FIFO can then have RL=0 so that the read sync becomes
+ -- out_sync directly and the read bsn then becomes out_bsn after a register
+ -- stage.
+ -- Putting the sync and BSN through the same FIFO as the data and sop, eop
+ -- consumes quite some RAM since the BSN is typically 48 bit wide and it
+ -- then needs to be pass through through the FIFO for every valid clock
+ -- cycle.
entity dp_bsn_delay is
generic (
@@ -109,18 +109,18 @@ begin
-- Hold the in_sync during the block until the in_eop
u_hold_sync : entity common_lib.common_switch
- generic map (
- g_priority_lo => false, -- in_sync has priority over in_eop, because they may occur simultaneously
- g_or_high => false, -- hold_sync goes high after in_sync
- g_and_low => false -- hold_sync goes low after in_eop
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => in_sync,
- switch_low => in_eop,
- out_level => hold_sync
- );
+ generic map (
+ g_priority_lo => false, -- in_sync has priority over in_eop, because they may occur simultaneously
+ g_or_high => false, -- hold_sync goes high after in_sync
+ g_and_low => false -- hold_sync goes low after in_eop
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => in_sync,
+ switch_low => in_eop,
+ out_level => hold_sync
+ );
-- Delay line for in_sync and in_bsn at block level
sync_dly(0) <= hold_sync;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
index e32360c208..b114d40b1d 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
@@ -41,10 +41,10 @@
-- valid remains active until an acknowledge by ready)
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_monitor is
generic (
@@ -162,33 +162,33 @@ begin
nof_valid <= INCR_UVEC(cnt_valid, 1); -- +1 because the valid at the sync also counts
u_sync_timeout_cnt : entity common_lib.common_counter
- generic map (
- g_width => c_sync_timeout_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => sync_timeout_n,
- count => sync_timeout_cnt
- );
+ generic map (
+ g_width => c_sync_timeout_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => sync_timeout_n,
+ count => sync_timeout_cnt
+ );
sync_timeout_n <= not nxt_sync_timeout;
nxt_sync_timeout <= '1' when unsigned(sync_timeout_cnt) >= g_sync_timeout else '0';
u_sync_timeout_revt : entity common_lib.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_invert => false,
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => sync_timeout,
- out_evt => sync_timeout_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_invert => false,
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => sync_timeout,
+ out_evt => sync_timeout_revt
+ );
p_clk : process(rst, clk)
begin
@@ -243,24 +243,24 @@ begin
nxt_xon <= in_siso.xon;
u_ready_stable : entity common_lib.common_stable_monitor
- port map (
- rst => rst,
- clk => clk,
- -- MM
- r_in => ready,
- r_stable => ready_stable,
- r_stable_ack => sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- MM
+ r_in => ready,
+ r_stable => ready_stable,
+ r_stable_ack => sync
+ );
u_xon_stable : entity common_lib.common_stable_monitor
- port map (
- rst => rst,
- clk => clk,
- -- MM
- r_in => xon,
- r_stable => xon_stable,
- r_stable_ack => sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- MM
+ r_in => xon,
+ r_stable => xon_stable,
+ r_stable_ack => sync
+ );
-- Sample the BSN, because BSN is only valid during sop.
nxt_current_bsn <= in_sosi.bsn(c_bsn_w - 1 downto 0) when in_sosi.sop = '1' else i_current_bsn;
@@ -287,50 +287,50 @@ begin
end generate;
u_cnt_sop : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_sop_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => sop,
- count => cnt_sop
- );
+ generic map (
+ g_width => c_cnt_sop_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => sop,
+ count => cnt_sop
+ );
u_nof_err : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_sop_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => err,
- count => cnt_err
- );
+ generic map (
+ g_width => c_cnt_sop_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => err,
+ count => cnt_err
+ );
u_cnt_valid : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_valid_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => valid,
- count => cnt_valid
- );
+ generic map (
+ g_width => c_cnt_valid_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => valid,
+ count => cnt_valid
+ );
u_cnt_cycle : entity common_lib.common_counter
- generic map (
- g_width => c_word_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => in_sosi.sop,
- cnt_en => '1',
- count => cnt_cycle
- );
+ generic map (
+ g_width => c_word_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => in_sosi.sop,
+ cnt_en => '1',
+ count => cnt_cycle
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
index 1eab6bd1e0..4bb60ba939 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
@@ -46,9 +46,9 @@
-- |-----------------------------------------------------------------------|
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_monitor_reg is
generic (
@@ -83,11 +83,12 @@ end dp_bsn_monitor_reg;
architecture str of dp_bsn_monitor_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 4,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 9,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 4,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 9,
+ init_sl => '0');
-- Registers in st_clk domain
signal mon_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
@@ -103,28 +104,28 @@ begin
mon_reg(9 * c_word_w - 1 downto 8 * c_word_w) <= RESIZE_UVEC(mon_bsn_first_cycle_cnt, c_word_w);
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1, -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1, -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => sla_in,
- sla_out => sla_out,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => sla_in,
+ sla_out => sla_out,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_new => mon_evt,
- in_reg => mon_reg, -- read only
- out_reg => open -- no write
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_new => mon_evt,
+ in_reg => mon_reg, -- read only
+ out_reg => open -- no write
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
index 6f01dc61b6..fb98bb09df 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
@@ -43,9 +43,9 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_monitor_reg_v2 is
generic (
@@ -79,11 +79,12 @@ end dp_bsn_monitor_reg_v2;
architecture str of dp_bsn_monitor_reg_v2 is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 3,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 7,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 3,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 7,
+ init_sl => '0');
-- Registers in st_clk domain
signal mon_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
@@ -98,28 +99,28 @@ begin
mon_reg(7 * c_word_w - 1 downto 6 * c_word_w) <= RESIZE_UVEC(mon_latency, c_word_w);
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1, -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1, -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => sla_in,
- sla_out => sla_out,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => sla_in,
+ sla_out => sla_out,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_new => mon_evt,
- in_reg => mon_reg, -- read only
- out_reg => open -- no write
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_new => mon_evt,
+ in_reg => mon_reg, -- read only
+ out_reg => open -- no write
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
index 339533f55e..f28745ed44 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
@@ -40,10 +40,10 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_monitor_v2 is
generic (
@@ -173,33 +173,33 @@ begin
ref_sync_reg <= ref_sync when rising_edge(clk);
u_sync_timeout_cnt : entity common_lib.common_counter
- generic map (
- g_width => c_sync_timeout_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => sync_timeout_n,
- count => sync_timeout_cnt
- );
+ generic map (
+ g_width => c_sync_timeout_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => sync_timeout_n,
+ count => sync_timeout_cnt
+ );
sync_timeout_n <= not nxt_sync_timeout;
nxt_sync_timeout <= '1' when unsigned(sync_timeout_cnt) >= g_sync_timeout else '0';
u_sync_timeout_revt : entity common_lib.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_invert => false,
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => sync_timeout,
- out_evt => sync_timeout_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_invert => false,
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => sync_timeout,
+ out_evt => sync_timeout_revt
+ );
p_clk : process(rst, clk)
begin
@@ -255,24 +255,24 @@ begin
nxt_xon <= in_siso.xon;
u_ready_stable : entity common_lib.common_stable_monitor
- port map (
- rst => rst,
- clk => clk,
- -- MM
- r_in => ready,
- r_stable => ready_stable,
- r_stable_ack => sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- MM
+ r_in => ready,
+ r_stable => ready_stable,
+ r_stable_ack => sync
+ );
u_xon_stable : entity common_lib.common_stable_monitor
- port map (
- rst => rst,
- clk => clk,
- -- MM
- r_in => xon,
- r_stable => xon_stable,
- r_stable_ack => sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- MM
+ r_in => xon,
+ r_stable => xon_stable,
+ r_stable_ack => sync
+ );
-- Sample the BSN, because BSN is only valid during sop.
nxt_current_bsn <= in_sosi.bsn(c_bsn_w - 1 downto 0) when in_sosi.sop = '1' else i_current_bsn;
@@ -287,52 +287,52 @@ begin
nxt_bsn <= in_sosi.bsn(c_bsn_w - 1 downto 0) when in_sosi.sop = '1' else bsn; -- keep bsn as defined at sop
u_cnt_sop : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_sop_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the sop at the sync counts too.
- cnt_en => sop,
- load => TO_SVEC(1, c_cnt_sop_w),
- count => cnt_sop
- );
+ generic map (
+ g_width => c_cnt_sop_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the sop at the sync counts too.
+ cnt_en => sop,
+ load => TO_SVEC(1, c_cnt_sop_w),
+ count => cnt_sop
+ );
u_nof_err : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_sop_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => err,
- count => cnt_err
- );
+ generic map (
+ g_width => c_cnt_sop_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => err,
+ count => cnt_err
+ );
u_cnt_valid : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_valid_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the valid at the sync counts too.
- cnt_en => valid,
- load => TO_SVEC(1, c_cnt_valid_w),
- count => cnt_valid
- );
+ generic map (
+ g_width => c_cnt_valid_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the valid at the sync counts too.
+ cnt_en => valid,
+ load => TO_SVEC(1, c_cnt_valid_w),
+ count => cnt_valid
+ );
u_cnt_latency : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_latency_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => ref_sync_reg,
- cnt_en => '1',
- count => cnt_latency
- );
+ generic map (
+ g_width => c_cnt_latency_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => ref_sync_reg,
+ cnt_en => '1',
+ count => cnt_latency
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd b/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
index b4c524a869..a0de81c540 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
@@ -21,24 +21,24 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Author: Eric Kooistra, 17 nov 2017
--- Purpose:
--- Restore global BSN.
--- Description:
--- The input global BSN is active at the sync. In between sync the other BSN
--- BSN at the sop may count a local BSN that restarted at 0 for every sync.
--- This dp_bsn_restore_global takes the BSN at the sync and starts counting
--- from there for every sop, so in this way it restores the global BSN count
--- for the blocks in between syncs.
--- The increment for each restored BSN is 1. The assumption is that the
--- number of blocks between syncs equals the difference in global BSN values
--- between syncs. In this way the restored BSN counts without gaps or
--- duplicates.
--- Remarks:
+ -- Author: Eric Kooistra, 17 nov 2017
+ -- Purpose:
+ -- Restore global BSN.
+ -- Description:
+ -- The input global BSN is active at the sync. In between sync the other BSN
+ -- BSN at the sop may count a local BSN that restarted at 0 for every sync.
+ -- This dp_bsn_restore_global takes the BSN at the sync and starts counting
+ -- from there for every sop, so in this way it restores the global BSN count
+ -- for the blocks in between syncs.
+ -- The increment for each restored BSN is 1. The assumption is that the
+ -- number of blocks between syncs equals the difference in global BSN values
+ -- between syncs. In this way the restored BSN counts without gaps or
+ -- duplicates.
+ -- Remarks:
entity dp_bsn_restore_global is
generic (
@@ -79,19 +79,19 @@ begin
-- Create block sync from snk_in.sync, this blk_sync is active during entire first sop-eop block of sync interval
u_common_switch : entity common_lib.common_switch
- generic map (
- g_rst_level => '0', -- Defines the output level at reset.
- g_priority_lo => false, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
- g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
- g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => snk_in.sync, -- A pulse on switch_high makes the out_level go high
- switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
- out_level => blk_sync
- );
+ generic map (
+ g_rst_level => '0', -- Defines the output level at reset.
+ g_priority_lo => false, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
+ g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
+ g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => snk_in.sync, -- A pulse on switch_high makes the out_level go high
+ switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
+ out_level => blk_sync
+ );
-- Use stored global BSN at sync and add local BSN to restore the global BSN for every next sop
bsn_restored <= snk_in.bsn when blk_sync = '1' else ADD_UVEC(bsn_at_sync, snk_in.bsn, g_bsn_w);
@@ -100,17 +100,17 @@ begin
-- Add pipeline to ensure timing closure for the restored BSN summation
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in_restored,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in_restored,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
index b095b03d52..5bde367984 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
@@ -20,22 +20,22 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose : Schedule an output trigger based on the Data Path BSN[]
--- Description:
--- When the snk_in.bsn matches the scheduled_bsn then trigger_out will pulse
--- at the block sync of that block.
--- Remark:
--- . The block sync is defined by the snk_in.eop. The trigger_out is in phase
--- with this block sync.
--- . If the scheduled_bsn is in the past then no trigger_out pulse will occur.
--- . A scheduled_bsn that has not yet occured can be canceled simply by applying
--- a new scheduled_bsn value.
--- . The bsn scheduler can only handle one scheduled_bsn at a time.
+ -- Purpose : Schedule an output trigger based on the Data Path BSN[]
+ -- Description:
+ -- When the snk_in.bsn matches the scheduled_bsn then trigger_out will pulse
+ -- at the block sync of that block.
+ -- Remark:
+ -- . The block sync is defined by the snk_in.eop. The trigger_out is in phase
+ -- with this block sync.
+ -- . If the scheduled_bsn is in the past then no trigger_out pulse will occur.
+ -- . A scheduled_bsn that has not yet occured can be canceled simply by applying
+ -- a new scheduled_bsn value.
+ -- . The bsn scheduler can only handle one scheduled_bsn at a time.
entity dp_bsn_scheduler is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
index 36d2d553ae..0509134e5a 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
@@ -32,9 +32,9 @@
-- |-----------------------------------------------------------------------|
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_scheduler_reg is
generic (
@@ -61,11 +61,12 @@ architecture rtl of dp_bsn_scheduler_reg is
constant c_bsn_w : natural := st_current_bsn'length;
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2,
+ init_sl => '0');
-- Registers in mm_clk domain
signal mm_current_bsn : std_logic_vector(c_longword_w - 1 downto 0) := (others => '0');
@@ -110,7 +111,7 @@ begin
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -163,31 +164,31 @@ begin
gen_cross : if g_cross_clock_domain = true generate
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_init_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_scheduled_bsn_wr, -- use wr of mm_scheduled_bsn high part for in_new to ensure proper transfer of double word
- in_dat => mm_scheduled_bsn(c_bsn_w - 1 downto 0),
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_scheduled_bsn,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_scheduled_bsn_wr, -- use wr of mm_scheduled_bsn high part for in_new to ensure proper transfer of double word
+ in_dat => mm_scheduled_bsn(c_bsn_w - 1 downto 0),
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_scheduled_bsn,
+ out_new => open
+ );
-- thanks to mm_current_bsn_hi the double word can be read reliably
u_current_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
- in_dat => st_current_bsn,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
- out_new => open
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ in_dat => st_current_bsn,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
+ out_new => open
+ );
end generate; -- gen_cross
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
index b190933263..a186032cb0 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
@@ -33,10 +33,10 @@
-- has to disable (dp_on='0') the data path before restarting it.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_source is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
index e6310abb8f..3e49f6cc94 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
@@ -39,9 +39,9 @@
-- ====================================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_source_reg is
generic (
@@ -73,11 +73,12 @@ architecture rtl of dp_bsn_source_reg is
constant c_bsn_w : natural := st_init_bsn'length;
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2**2,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 2,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2**2,
+ init_sl => '0');
-- Registers in mm_clk domain
signal mm_on : std_logic;
@@ -132,7 +133,7 @@ begin
when 1 =>
mm_nof_block_per_sync <= sla_in.wrdata(31 downto 0);
- -- Write init BSN
+ -- Write init BSN
when 2 =>
mm_init_bsn(31 downto 0) <= sla_in.wrdata(31 downto 0);
when 3 =>
@@ -142,7 +143,7 @@ begin
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -154,7 +155,7 @@ begin
when 1 =>
sla_out.rddata(31 downto 0) <= mm_nof_block_per_sync;
- -- Read current BSN
+ -- Read current BSN
when 2 =>
sla_out.rddata(31 downto 0) <= mm_current_bsn(31 downto 0);
mm_current_bsn_hi <= mm_current_bsn(63 downto 32); -- first read low part and preserve high part
@@ -207,16 +208,16 @@ begin
gen_cross : if g_cross_clock_domain = true generate
-- Block sync registers
u_dp_on_ctrl : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_on_ctrl,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_on_ctrl,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_on_ctrl,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_on_ctrl,
+ out_new => open
+ );
mm_on_ctrl(0) <= mm_on;
mm_on_ctrl(1) <= mm_on_pps;
@@ -225,56 +226,56 @@ begin
st_on_pps <= st_on_ctrl(1);
u_mm_on_status : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_on_status,
- dout => mm_on_status
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_on_status,
+ dout => mm_on_status
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_nof_block_per_sync : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_nof_block_per_sync,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_nof_block_per_sync,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_nof_block_per_sync,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_nof_block_per_sync,
+ out_new => open
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_init_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_init_bsn_wr, -- use wr of mm_init_bsn high part for in_new to ensure proper transfer of double word
- in_dat => mm_init_bsn(c_bsn_w - 1 downto 0),
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_init_bsn,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_init_bsn_wr, -- use wr of mm_init_bsn high part for in_new to ensure proper transfer of double word
+ in_dat => mm_init_bsn(c_bsn_w - 1 downto 0),
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_init_bsn,
+ out_new => open
+ );
-- thanks to mm_current_bsn_hi the double word can be read reliably
u_current_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
- in_dat => st_current_bsn,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
- out_new => open
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ in_dat => st_current_bsn,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
+ out_new => open
+ );
end generate; -- gen_cross
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
index 71eab87eda..63935abe3a 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
@@ -40,9 +40,9 @@
-- ====================================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_source_reg_v2 is
generic (
@@ -76,11 +76,12 @@ architecture rtl of dp_bsn_source_reg_v2 is
constant c_bsn_time_offset_w : natural := st_bsn_time_offset'length;
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 3,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2**3,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 3,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2**3,
+ init_sl => '0');
-- Registers in mm_clk domain
signal mm_on : std_logic;
@@ -141,14 +142,14 @@ begin
when 1 =>
mm_nof_clk_per_sync <= sla_in.wrdata(31 downto 0);
- -- Write init BSN
+ -- Write init BSN
when 2 =>
mm_bsn_init(31 downto 0) <= sla_in.wrdata(31 downto 0);
when 3 =>
mm_bsn_init(63 downto 32) <= sla_in.wrdata(31 downto 0);
mm_bsn_init_wr <= '1';
- -- write bsn_time_offset
+ -- write bsn_time_offset
when 4 =>
mm_bsn_time_offset <= sla_in.wrdata(c_bsn_time_offset_w - 1 downto 0);
mm_bsn_time_offset_wr <= '1';
@@ -156,7 +157,7 @@ begin
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -168,14 +169,14 @@ begin
when 1 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_nof_clk_per_sync;
- -- Read current BSN
+ -- Read current BSN
when 2 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_current_bsn(31 downto 0);
mm_current_bsn_hi <= mm_current_bsn(63 downto 32); -- first read low part and preserve high part
when 3 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_current_bsn_hi; -- then read preserved high part
- -- Read current bsn_time_offset
+ -- Read current bsn_time_offset
when 4 =>
sla_out.rddata(c_word_w - 1 downto 0) <= RESIZE_UVEC(mm_bsn_time_offset, c_word_w);
@@ -231,16 +232,16 @@ begin
gen_cross : if g_cross_clock_domain = true generate
-- Block sync registers
u_dp_on_ctrl : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_on_ctrl,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_on_ctrl,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_on_ctrl,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_on_ctrl,
+ out_new => open
+ );
mm_on_ctrl(0) <= mm_on;
mm_on_ctrl(1) <= mm_on_pps;
@@ -249,70 +250,70 @@ begin
st_on_pps <= st_on_ctrl(1);
u_mm_on_status : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_on_status,
- dout => mm_on_status
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_on_status,
+ dout => mm_on_status
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_nof_block_per_sync : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_nof_clk_per_sync,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_nof_clk_per_sync,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_nof_clk_per_sync,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_nof_clk_per_sync,
+ out_new => open
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_bsn_init : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_bsn_init_wr, -- use wr of mm_bsn_init high part for in_new to ensure proper transfer of double word
- in_dat => mm_bsn_init(c_bsn_w - 1 downto 0),
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_bsn_init,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_bsn_init_wr, -- use wr of mm_bsn_init high part for in_new to ensure proper transfer of double word
+ in_dat => mm_bsn_init(c_bsn_w - 1 downto 0),
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_bsn_init,
+ out_new => open
+ );
-- thanks to mm_current_bsn_hi the double word can be read reliably
u_current_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
- in_dat => st_current_bsn,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
- out_new => open
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ in_dat => st_current_bsn,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
+ out_new => open
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_bsn_time_offset : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_bsn_time_offset_wr,
- in_dat => mm_bsn_time_offset,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_bsn_time_offset,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_bsn_time_offset_wr,
+ in_dat => mm_bsn_time_offset,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_bsn_time_offset,
+ out_new => open
+ );
end generate; -- gen_cross
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
index 1d2ebf0fbb..6e0cc907b0 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
@@ -55,10 +55,10 @@
-- [1] https://support.astron.nl/confluence/display/L2M/L2+STAT+Decision%3A+Timing+in+Station
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_source_v2 is
generic (
@@ -125,8 +125,8 @@ begin
bs_new_interval <= i_bs_new_interval;
p_state : process(sync, sync_size_cnt, nof_clk_per_sync,
- state, i_src_out, block_size_cnt, bsn_time_offset_cnt,
- bsn_init, dp_on, dp_on_pps, pps, bsn_time_offset, prev_state)
+ state, i_src_out, block_size_cnt, bsn_time_offset_cnt,
+ bsn_init, dp_on, dp_on_pps, pps, bsn_time_offset, prev_state)
begin
-- Maintain sync_size_cnt for nof_clk_per_sync
-- . nof_clk_per_sync is the number of clk per pps interval and the
@@ -185,9 +185,9 @@ begin
nxt_bsn_time_offset_cnt <= INCR_UVEC(bsn_time_offset_cnt, 1);
end if;
- -- using separate states s_dp_on_sop and s_dp_on_eop instead of only
- -- s_dp_on state and block_size_cnt, cause that g_block_size must be
- -- >= 3, but that is fine.
+ -- using separate states s_dp_on_sop and s_dp_on_eop instead of only
+ -- s_dp_on state and block_size_cnt, cause that g_block_size must be
+ -- >= 3, but that is fine.
when s_dp_on_sop =>
-- Start of block
nxt_src_out.sop <= '1';
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
index f92809dc54..520a3ea35a 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
@@ -111,10 +111,10 @@
-- [1] https://support.astron.nl/confluence/display/L2M/L2+STAT+Decision%3A+Timing+in+Station
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_sync_scheduler is
generic (
@@ -424,17 +424,17 @@ begin
-- Pipeline output to avoid timing closure problems due to use of output_enable
-----------------------------------------------------------------------------
u_out_sosi : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => output_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => output_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
gen_pipe_out_start : if g_pipeline = 1 generate
out_start <= output_start when rising_edge(clk);
diff --git a/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd b/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
index 0326cf2138..b1f2d45617 100644
--- a/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
@@ -26,15 +26,15 @@
-- snk_in.eop of that block.
library IEEE, common_lib, easics_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-use easics_lib.PCK_CRC8_D8.all;
-use easics_lib.PCK_CRC16_D16.all;
-use easics_lib.PCK_CRC28_D28.all;
-use easics_lib.PCK_CRC32_D32.all;
-use easics_lib.PCK_CRC32_D64.all;
+ use easics_lib.PCK_CRC8_D8.all;
+ use easics_lib.PCK_CRC16_D16.all;
+ use easics_lib.PCK_CRC28_D28.all;
+ use easics_lib.PCK_CRC32_D32.all;
+ use easics_lib.PCK_CRC32_D64.all;
entity dp_calculate_crc is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_complex_add.vhd b/libraries/base/dp/src/vhdl/dp_complex_add.vhd
index 046cd7f80a..961308ed4a 100644
--- a/libraries/base/dp/src/vhdl/dp_complex_add.vhd
+++ b/libraries/base/dp/src/vhdl/dp_complex_add.vhd
@@ -20,24 +20,24 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-
--- Author:
--- . Daniel van der Schuur
--- Purpose:
--- . Provide a complex adder tree with streaming array I/O types
--- Description:
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+
+ -- Author:
+ -- . Daniel van der Schuur
+ -- Purpose:
+ -- . Provide a complex adder tree with streaming array I/O types
+ -- Description:
entity dp_complex_add is
generic (
g_technology : natural := c_tech_select_default;
g_nof_inputs : natural;
g_data_w : natural -- Complex input data width
- );
+ );
port (
rst : in std_logic;
clk : in std_logic;
@@ -74,33 +74,33 @@ begin
-- One adder tree for the real part
u_adder_tree_re : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_nof_inputs => g_nof_inputs,
- g_dat_w => g_data_w,
- g_sum_w => c_common_adder_tree_sum_w
- )
- port map (
- clk => clk,
- in_dat => common_adder_tree_re_in_dat,
- sum => common_adder_tree_re_sum
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_nof_inputs => g_nof_inputs,
+ g_dat_w => g_data_w,
+ g_sum_w => c_common_adder_tree_sum_w
+ )
+ port map (
+ clk => clk,
+ in_dat => common_adder_tree_re_in_dat,
+ sum => common_adder_tree_re_sum
+ );
-- One adder tree for the imaginary part
u_adder_tree_im : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_nof_inputs => g_nof_inputs,
- g_dat_w => g_data_w,
- g_sum_w => c_common_adder_tree_sum_w
- )
- port map (
- clk => clk,
- in_dat => common_adder_tree_im_in_dat,
- sum => common_adder_tree_im_sum
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_nof_inputs => g_nof_inputs,
+ g_dat_w => g_data_w,
+ g_sum_w => c_common_adder_tree_sum_w
+ )
+ port map (
+ clk => clk,
+ in_dat => common_adder_tree_im_in_dat,
+ sum => common_adder_tree_im_sum
+ );
p_src_out : process(snk_in_pipe, common_adder_tree_re_sum, common_adder_tree_im_sum)
begin
@@ -117,15 +117,15 @@ begin
snk_in <= snk_in_arr(0);
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline_adder_tree
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => snk_in,
- -- ST source
- src_out => snk_in_pipe
- );
+ generic map (
+ g_pipeline => c_pipeline_adder_tree
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => snk_in,
+ -- ST source
+ src_out => snk_in_pipe
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_complex_mult.vhd b/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
index b41f0cfdf0..4288471b78 100644
--- a/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
+++ b/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
@@ -20,21 +20,21 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
--- Author:
--- . Daniel van der Schuur
--- Purpose:
--- . Provide an array of complex multipliers with streaming array I/O types
--- Description:
--- . Multiplies snk_in_2arr_2[i][0] with snk_in_2arr_2[i][1] yielding
--- src_out_2arr[i] for i in 0..g_nof_multipliers-1.
--- . This DP wrapper does not allow selection of RTL implementation of
--- common_complex_mult; it uses the generated IP core for g_technology.
+ -- Author:
+ -- . Daniel van der Schuur
+ -- Purpose:
+ -- . Provide an array of complex multipliers with streaming array I/O types
+ -- Description:
+ -- . Multiplies snk_in_2arr_2[i][0] with snk_in_2arr_2[i][1] yielding
+ -- src_out_2arr[i] for i in 0..g_nof_multipliers-1.
+ -- . This DP wrapper does not allow selection of RTL implementation of
+ -- common_complex_mult; it uses the generated IP core for g_technology.
entity dp_complex_mult is
generic (
@@ -43,7 +43,7 @@ entity dp_complex_mult is
g_conjugate_b : boolean := false; -- Conjugate input 1 of snk_in_2arr2(i)(1 DOWNTO 0)
g_data_w : natural; -- Input data width. Output data width = 2*input data width.
g_variant : string := "IP"
- );
+ );
port (
rst : in std_logic;
clk : in std_logic;
@@ -65,27 +65,27 @@ begin
-----------------------------------------------------------------------------
gen_common_complex_mult : for i in 0 to g_nof_multipliers - 1 generate
u_common_complex_mult : entity common_mult_lib.common_complex_mult
- generic map (
- g_technology => g_technology,
- g_variant => g_variant,
- g_in_a_w => g_data_w,
- g_in_b_w => g_data_w,
- g_out_p_w => 2 * g_data_w, -- default use g_out_p_w = g_in_a_w+g_in_b_w
- g_conjugate_b => g_conjugate_b
- )
- port map (
- clk => clk,
- clken => '1',
- rst => '0',
- in_ar => snk_in_2arr_2(i)(0).re(g_data_w - 1 downto 0),
- in_ai => snk_in_2arr_2(i)(0).im(g_data_w - 1 downto 0),
- in_br => snk_in_2arr_2(i)(1).re(g_data_w - 1 downto 0),
- in_bi => snk_in_2arr_2(i)(1).im(g_data_w - 1 downto 0),
- in_val => snk_in_2arr_2(i)(0).valid,
- out_pr => common_complex_mult_src_out_arr(i).re(2 * g_data_w - 1 downto 0),
- out_pi => common_complex_mult_src_out_arr(i).im(2 * g_data_w - 1 downto 0),
- out_val => common_complex_mult_src_out_arr(i).valid
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_data_w,
+ g_in_b_w => g_data_w,
+ g_out_p_w => 2 * g_data_w, -- default use g_out_p_w = g_in_a_w+g_in_b_w
+ g_conjugate_b => g_conjugate_b
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ rst => '0',
+ in_ar => snk_in_2arr_2(i)(0).re(g_data_w - 1 downto 0),
+ in_ai => snk_in_2arr_2(i)(0).im(g_data_w - 1 downto 0),
+ in_br => snk_in_2arr_2(i)(1).re(g_data_w - 1 downto 0),
+ in_bi => snk_in_2arr_2(i)(1).im(g_data_w - 1 downto 0),
+ in_val => snk_in_2arr_2(i)(0).valid,
+ out_pr => common_complex_mult_src_out_arr(i).re(2 * g_data_w - 1 downto 0),
+ out_pi => common_complex_mult_src_out_arr(i).im(2 * g_data_w - 1 downto 0),
+ out_val => common_complex_mult_src_out_arr(i).valid
+ );
src_out_arr(i).re <= RESIZE_DP_DSP_DATA(common_complex_mult_src_out_arr(i).re(2 * g_data_w - 1 downto 0));
src_out_arr(i).im <= RESIZE_DP_DSP_DATA(common_complex_mult_src_out_arr(i).im(2 * g_data_w - 1 downto 0));
@@ -96,14 +96,14 @@ begin
-- Forward the input sync with the correct latency
-----------------------------------------------------------------------------
u_common_pipeline_sl : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline => c_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_dat => snk_in_2arr_2(0)(0).sync,
- out_dat => src_out_arr(0).sync
- );
+ in_dat => snk_in_2arr_2(0)(0).sync,
+ out_dat => src_out_arr(0).sync
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
index 2fafe0a210..dcba4de488 100644
--- a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
@@ -24,9 +24,9 @@
-- Description:
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_components_pkg is
constant c_dp_clk_MHz : natural := 200;
diff --git a/libraries/base/dp/src/vhdl/dp_concat.vhd b/libraries/base/dp/src/vhdl/dp_concat.vhd
index e2d6a58f0d..0e2077d651 100644
--- a/libraries/base/dp/src/vhdl/dp_concat.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat.vhd
@@ -20,51 +20,51 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-
--- Purpose:
--- Concat two frames into one frame.
--- Description:
--- When both frames are present at the snk_in_arr ports, then the output frame
--- starts with the head frame from sink port 0 and concatenates it with the
--- tail frame from sink port 1.
--- Remark:
--- . Both frames must have the same data width and symbol width.
--- . The concatenation is done at symbol level and the output frame will have
--- the aggregated empty.
--- . The concatenated frame gets the channel and error field of the tail frame
--- from sink port 1.
--- . The ready control can easily result in combinatorial loop errors (the loop
--- does not end in a stable state) or synthesis warning. To avoid that:
--- - when src_in.ready = '1' then use c_dp_siso_rdy instead of src_in for
--- flow control assignments to avoid combinatorial loop warning at
--- synthesis
--- - do not use next_src_out_arr in conditional statements but explicitely
--- use pend_src_out_arr AND src_in.ready
---
--- Design steps that were taken for dp_concat (took about 3 days):
--- 1 aim is a component that can add a header to a frame
--- 2 generalize to a streaming component that can concat two arbitrary frames
--- 3 support c_nof_symbols_per_data >= 1
--- 4 draft dp_concat that uses dp_hold_input and implements the p_state state machine, key aspects are:
--- . it is not necessary to use dp_shiftreg, using the combination of dp_hold_input and prev_tail is appropriate
--- . state s_sop introduces an idle output cycle, this is no limitation, but makes the state machine easier
--- . states s_head, s_tail and s_eop do not introduce extra output idle cycles, this ensures that the output frame remains
--- active if possible (dependent on snk_in_arr().valid and src_in.ready). It also makes the statemachine more complex and
--- makes it necessary to independently register the hold input streams in src_out_buf_arr in addition to i_src_out. Note that
--- this is different in dp_mux, because dp_mux uses i_src_out for all hold inputs, which causes an idle cycle between
--- dp_mux output frames.
--- . support head and or tail frame with only one symbol
--- 5 made proc_dp_gen_frame(), func_dp_data_init() and func_dp_data_incr() to generate frames with symbol data
--- 6 made test bench tb_dp_concat and test with ready and valid both active for various head and tail frame lengths
--- 7 made tb_dp_concat self checking for data for c_nof_symbols_per_data = 1
--- 8 test with ready sometimes active and sometimes inactive using random function from diag module
--- 9 test with input valid some times inactive when ready is active using random function from diag module
--- 10 made tb_dp_concat self checking for data for c_nof_symbols_per_data > 1
--- 11 iterate these steps until the dp_concat works OK
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+
+ -- Purpose:
+ -- Concat two frames into one frame.
+ -- Description:
+ -- When both frames are present at the snk_in_arr ports, then the output frame
+ -- starts with the head frame from sink port 0 and concatenates it with the
+ -- tail frame from sink port 1.
+ -- Remark:
+ -- . Both frames must have the same data width and symbol width.
+ -- . The concatenation is done at symbol level and the output frame will have
+ -- the aggregated empty.
+ -- . The concatenated frame gets the channel and error field of the tail frame
+ -- from sink port 1.
+ -- . The ready control can easily result in combinatorial loop errors (the loop
+ -- does not end in a stable state) or synthesis warning. To avoid that:
+ -- - when src_in.ready = '1' then use c_dp_siso_rdy instead of src_in for
+ -- flow control assignments to avoid combinatorial loop warning at
+ -- synthesis
+ -- - do not use next_src_out_arr in conditional statements but explicitely
+ -- use pend_src_out_arr AND src_in.ready
+ --
+ -- Design steps that were taken for dp_concat (took about 3 days):
+ -- 1 aim is a component that can add a header to a frame
+ -- 2 generalize to a streaming component that can concat two arbitrary frames
+ -- 3 support c_nof_symbols_per_data >= 1
+ -- 4 draft dp_concat that uses dp_hold_input and implements the p_state state machine, key aspects are:
+ -- . it is not necessary to use dp_shiftreg, using the combination of dp_hold_input and prev_tail is appropriate
+ -- . state s_sop introduces an idle output cycle, this is no limitation, but makes the state machine easier
+ -- . states s_head, s_tail and s_eop do not introduce extra output idle cycles, this ensures that the output frame remains
+ -- active if possible (dependent on snk_in_arr().valid and src_in.ready). It also makes the statemachine more complex and
+ -- makes it necessary to independently register the hold input streams in src_out_buf_arr in addition to i_src_out. Note that
+ -- this is different in dp_mux, because dp_mux uses i_src_out for all hold inputs, which causes an idle cycle between
+ -- dp_mux output frames.
+ -- . support head and or tail frame with only one symbol
+ -- 5 made proc_dp_gen_frame(), func_dp_data_init() and func_dp_data_incr() to generate frames with symbol data
+ -- 6 made test bench tb_dp_concat and test with ready and valid both active for various head and tail frame lengths
+ -- 7 made tb_dp_concat self checking for data for c_nof_symbols_per_data = 1
+ -- 8 test with ready sometimes active and sometimes inactive using random function from diag module
+ -- 9 test with input valid some times inactive when ready is active using random function from diag module
+ -- 10 made tb_dp_concat self checking for data for c_nof_symbols_per_data > 1
+ -- 11 iterate these steps until the dp_concat works OK
entity dp_concat is
generic (
@@ -153,18 +153,18 @@ begin
gen_input : for I in c_head to c_tail generate
-- Hold the sink input to be able to register the source output
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => hold_src_in_arr(I),
- next_src_out => next_src_out_arr(I),
- pend_src_out => pend_src_out_arr(I),
- src_out_reg => src_out_buf_arr(I)
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => hold_src_in_arr(I),
+ next_src_out => next_src_out_arr(I),
+ pend_src_out => pend_src_out_arr(I),
+ src_out_reg => src_out_buf_arr(I)
+ );
end generate;
-- default ready for hold input when ready for sink input or also ready for hold input when the eop is there
diff --git a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
index c115e41e88..8ca458ef56 100644
--- a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
@@ -36,13 +36,13 @@
-- the header and data are an integer number of g_data_w.
library IEEE, common_lib, technology_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_concat_field_blk is
generic (
@@ -122,31 +122,31 @@ begin
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : entity work.dp_field_blk
- generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
- g_field_sel => g_hdr_field_sel,
- g_snk_data_w => c_dp_field_blk_snk_data_w,
- g_src_data_w => c_dp_field_blk_src_data_w,
- g_in_symbol_w => g_symbol_w,
- g_out_symbol_w => g_symbol_w,
- g_pipeline_ready => g_pipeline_ready
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- snk_in => dp_field_blk_snk_in_arr(i),
- snk_out => dp_field_blk_snk_out_arr(i),
-
- src_out => dp_field_blk_src_out_arr(i),
- src_in => dp_field_blk_src_in_arr(i),
-
- reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
- reg_slv_miso => reg_hdr_dat_miso_arr(i)
- );
+ generic map (
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
+ g_field_sel => g_hdr_field_sel,
+ g_snk_data_w => c_dp_field_blk_snk_data_w,
+ g_src_data_w => c_dp_field_blk_src_data_w,
+ g_in_symbol_w => g_symbol_w,
+ g_out_symbol_w => g_symbol_w,
+ g_pipeline_ready => g_pipeline_ready
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ snk_in => dp_field_blk_snk_in_arr(i),
+ snk_out => dp_field_blk_snk_out_arr(i),
+
+ src_out => dp_field_blk_src_out_arr(i),
+ src_in => dp_field_blk_src_in_arr(i),
+
+ reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
+ reg_slv_miso => reg_hdr_dat_miso_arr(i)
+ );
dp_field_blk_src_in_arr(i) <= dp_concat_snk_out_2arr(i)(1);
end generate;
@@ -157,34 +157,34 @@ begin
dp_concat_snk_in_2arr(i)(1) <= dp_field_blk_src_out_arr(i);
u_dp_concat : entity work.dp_concat
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_concat_snk_out_2arr(i),
- snk_in_arr => dp_concat_snk_in_2arr(i),
-
- src_in => src_in_arr(i),
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_concat_snk_out_2arr(i),
+ snk_in_arr => dp_concat_snk_in_2arr(i),
+
+ src_in => src_in_arr(i),
+ src_out => src_out_arr(i)
+ );
end generate;
---------------------------------------------------------------------------------------
-- MM control & monitoring
---------------------------------------------------------------------------------------
u_common_mem_mux_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_counter.vhd b/libraries/base/dp/src/vhdl/dp_counter.vhd
index 9748348ee2..80f2fc35ce 100644
--- a/libraries/base/dp/src/vhdl/dp_counter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter.vhd
@@ -63,10 +63,10 @@
-- Any other useage will break counters >= stage i
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_counter is
generic (
@@ -108,55 +108,55 @@ begin
-- dp_counter_func
------------------------------------------------------------------------------
u_dp_counter_func : entity work.dp_counter_func
- generic map (
- g_nof_counters => g_nof_counters,
- g_range_start => c_range_start,
- g_range_stop => c_range_stop,
- g_range_step => c_range_step
- )
- port map (
- rst => rst,
- clk => clk,
-
- count_en => snk_in.valid,
-
- count_offset_in_arr => count_offset_in_arr,
- count_src_out_arr => dp_counter_func_src_out_arr
- );
-
- ------------------------------------------------------------------------------
- -- dp_pipeline
- ------------------------------------------------------------------------------
- gen_dp_pipeline : if c_use_dp_pipeline = true generate
- u_dp_pipeline_snk_in : entity work.dp_pipeline
generic map (
- g_pipeline => g_pipeline_src_out
+ g_nof_counters => g_nof_counters,
+ g_range_start => c_range_start,
+ g_range_stop => c_range_stop,
+ g_range_step => c_range_step
)
port map (
- clk => clk,
- rst => rst,
+ rst => rst,
+ clk => clk,
- snk_in => snk_in,
- snk_out => snk_out,
+ count_en => snk_in.valid,
- src_out => src_out,
- src_in => src_in
+ count_offset_in_arr => count_offset_in_arr,
+ count_src_out_arr => dp_counter_func_src_out_arr
);
- gen_dp_pipeline_count_src_out_arr : for i in 0 to g_nof_counters - 1 generate
- u_dp_pipeline_count_src_out_arr : entity work.dp_pipeline
+ ------------------------------------------------------------------------------
+ -- dp_pipeline
+ ------------------------------------------------------------------------------
+ gen_dp_pipeline : if c_use_dp_pipeline = true generate
+ u_dp_pipeline_snk_in : entity work.dp_pipeline
generic map (
g_pipeline => g_pipeline_src_out
)
port map (
- clk => clk,
- rst => rst,
+ clk => clk,
+ rst => rst,
- snk_in => dp_counter_func_src_out_arr(i),
+ snk_in => snk_in,
+ snk_out => snk_out,
- src_out => count_src_out_arr(i),
- src_in => src_in
+ src_out => src_out,
+ src_in => src_in
);
+
+ gen_dp_pipeline_count_src_out_arr : for i in 0 to g_nof_counters - 1 generate
+ u_dp_pipeline_count_src_out_arr : entity work.dp_pipeline
+ generic map (
+ g_pipeline => g_pipeline_src_out
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => dp_counter_func_src_out_arr(i),
+
+ src_out => count_src_out_arr(i),
+ src_in => src_in
+ );
end generate;
end generate;
@@ -165,34 +165,34 @@ begin
------------------------------------------------------------------------------
gen_dp_pipeline_ready : if c_use_dp_pipeline_ready = true generate
u_dp_pipeline_ready : entity work.dp_pipeline_ready
- generic map (
- g_in_latency => 1
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => snk_in,
- snk_out => snk_out,
-
- src_out => src_out,
- src_in => src_in
- );
-
- gen_dp_pipeline_ready_count_src_out_arr : for i in 0 to g_nof_counters - 1 generate
- u_dp_pipeline_ready_count_src_out_arr : entity work.dp_pipeline_ready
generic map (
- g_in_latency => 1
+ g_in_latency => 1
)
port map (
- clk => clk,
- rst => rst,
+ clk => clk,
+ rst => rst,
- snk_in => dp_counter_func_src_out_arr(i),
+ snk_in => snk_in,
+ snk_out => snk_out,
- src_out => count_src_out_arr(i),
- src_in => src_in
+ src_out => src_out,
+ src_in => src_in
);
+
+ gen_dp_pipeline_ready_count_src_out_arr : for i in 0 to g_nof_counters - 1 generate
+ u_dp_pipeline_ready_count_src_out_arr : entity work.dp_pipeline_ready
+ generic map (
+ g_in_latency => 1
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => dp_counter_func_src_out_arr(i),
+
+ src_out => count_src_out_arr(i),
+ src_in => src_in
+ );
end generate;
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_counter_func.vhd b/libraries/base/dp/src/vhdl/dp_counter_func.vhd
index 89431450dd..9383594c15 100644
--- a/libraries/base/dp/src/vhdl/dp_counter_func.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter_func.vhd
@@ -38,10 +38,10 @@
-- logic when minimum/maximum values per dimension are reached.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_counter_func is
generic (
@@ -88,8 +88,8 @@ begin
end generate;
gen_c1_upwards : if i > 0 generate
- count_en_arr(i) <= count_init_arr(i - 1) or count_min_arr(i - 1);
- check_max_arr(i) <= count_max_arr(i - 1);
+ count_en_arr(i) <= count_init_arr(i - 1) or count_min_arr(i - 1);
+ check_max_arr(i) <= count_max_arr(i - 1);
end generate;
end generate;
@@ -99,24 +99,24 @@ begin
-------------------------------------------------------------------------------
gen_dp_counter_func_single : for i in 0 to g_nof_counters - 1 generate
u_dp_counter_func_single : entity work.dp_counter_func_single
- generic map (
- g_range_start => c_range_start(i),
- g_range_stop => c_range_stop(i),
- g_range_step => c_range_step(i)
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_range_start => c_range_start(i),
+ g_range_stop => c_range_stop(i),
+ g_range_step => c_range_step(i)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- count_en => count_en_arr(i),
- check_max => check_max_arr(i),
- count_offset => count_offset_in_arr(i),
+ count_en => count_en_arr(i),
+ check_max => check_max_arr(i),
+ count_offset => count_offset_in_arr(i),
- count => count_arr(i),
- count_init => count_init_arr(i),
- count_min => count_min_arr(i),
- count_max => count_max_arr(i)
- );
+ count => count_arr(i),
+ count_init => count_init_arr(i),
+ count_min => count_min_arr(i),
+ count_max => count_max_arr(i)
+ );
end generate;
--------------------------------------------------------------------------------
@@ -124,7 +124,7 @@ begin
-------------------------------------------------------------------------------
gen_dp_counter_func_single_output : for i in 0 to g_nof_counters - 1 generate
count_src_out_arr(i).sync <= '0'; -- not used, force to '0' to avoid toggling between '0' and 'X' in Wave window
- -- when sync is passed on through other components
+ -- when sync is passed on through other components
count_src_out_arr(i).sop <= count_min_arr(i);
count_src_out_arr(i).eop <= count_max_arr(i);
count_src_out_arr(i).valid <= count_en;
diff --git a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
index 01c3d94c4a..cf45e5aa1b 100644
--- a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
@@ -29,10 +29,10 @@
-- . Not for standalone use; part of dp_counter_func.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_counter_func_single is -- FIXME move this to common
generic (
@@ -56,7 +56,7 @@ entity dp_counter_func_single is -- FIXME move this to common
end dp_counter_func_single;
architecture rtl of dp_counter_func_single is
- -- The user defines the counters like a Python range(start,stop,step) in which the stop value
+ -- The user defines the counters like a Python range(start,stop,step) in which the stop value
-- is never actually reached. Calculate the actual maximum values here.
-- . Example:
-- . range(0,4,2) = [0, 2]
@@ -98,7 +98,7 @@ begin
v.count := TO_UVEC(g_range_start + count_offset, c_count_w);
v.count_min := '1';
v.count_init := '1';
- -- keep counting
+ -- keep counting
else
v.count := INCR_UVEC(r.count, g_range_step);
if c_count_max > 0 and check_max = '1' and r.count = TO_UVEC(c_count_max - g_range_step, c_count_w) then -- count max almost reached
diff --git a/libraries/base/dp/src/vhdl/dp_deinterleave.vhd b/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
index e652bad0f3..c58de18468 100644
--- a/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
+++ b/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
@@ -20,24 +20,24 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-
--- Author:
--- . Daniel van der Schuur
--- Purpose:
--- . Deinterleave the input into g_nof_out outputs, outputting g_block_size_int words before switching to next output.
--- Description:
--- . DP wrapper for common_deinterleave
---
--- Status (erko):
--- . Obselete, do not use in new designs. Instead use:
--- - dp_deinterleave_one_to_n.vhd for 1 to N, preserves all sosi fields
--- - dp_unfolder.vhd for 1 to power of 2, but only preserves the valid
--- . The tb_tb_dp_deinterleave_interleave_to_one.vhd shows that dp_deinterleave.vhd fails if the
--- snk_in.valid is random.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+
+ -- Author:
+ -- . Daniel van der Schuur
+ -- Purpose:
+ -- . Deinterleave the input into g_nof_out outputs, outputting g_block_size_int words before switching to next output.
+ -- Description:
+ -- . DP wrapper for common_deinterleave
+ --
+ -- Status (erko):
+ -- . Obselete, do not use in new designs. Instead use:
+ -- - dp_deinterleave_one_to_n.vhd for 1 to N, preserves all sosi fields
+ -- - dp_unfolder.vhd for 1 to power of 2, but only preserves the valid
+ -- . The tb_tb_dp_deinterleave_interleave_to_one.vhd shows that dp_deinterleave.vhd fails if the
+ -- snk_in.valid is random.
entity dp_deinterleave is
generic (
@@ -84,22 +84,22 @@ begin
common_deinterleave_in_val <= snk_in.valid;
u_deinterleave : entity common_lib.common_deinterleave
- generic map (
- g_nof_out => g_nof_out,
- g_block_size => g_block_size_int,
- g_dat_w => g_dat_w,
- g_align_out => g_align_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => common_deinterleave_in_dat,
- in_val => common_deinterleave_in_val,
-
- out_dat => common_deinterleave_out_dat,
- out_val => common_deinterleave_out_val
- );
+ generic map (
+ g_nof_out => g_nof_out,
+ g_block_size => g_block_size_int,
+ g_dat_w => g_dat_w,
+ g_align_out => g_align_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => common_deinterleave_in_dat,
+ in_val => common_deinterleave_in_val,
+
+ out_dat => common_deinterleave_out_dat,
+ out_val => common_deinterleave_out_val
+ );
-----------------------------------------------------------------------------
-- Use complex fields if required
@@ -123,19 +123,19 @@ begin
gen_ctrl : if g_use_ctrl = true generate
gen_dp_block_gen : for i in 0 to g_nof_out - 1 generate
u_dp_block_gen : entity work.dp_block_gen
- generic map (
- g_use_src_in => false,
- g_nof_data => g_block_size_output,
- g_preserve_sync => true,
- g_preserve_bsn => true
- )
- port map(
- rst => rst,
- clk => clk,
-
- snk_in => common_deinterleave_src_out_arr(i),
- src_out => dp_block_gen_src_out_arr(i)
- );
+ generic map (
+ g_use_src_in => false,
+ g_nof_data => g_block_size_output,
+ g_preserve_sync => true,
+ g_preserve_bsn => true
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ snk_in => common_deinterleave_src_out_arr(i),
+ src_out => dp_block_gen_src_out_arr(i)
+ );
end generate;
end generate;
@@ -149,20 +149,20 @@ begin
align_out : if g_use_sync_bsn = true generate
gen_dp_fifo_info: for i in 0 to g_nof_out - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
- generic map (
- g_use_sync => true,
- g_use_bsn => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in, -- original snk_in info
-
- src_in => c_dp_siso_rdy,
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_use_sync => true,
+ g_use_bsn => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
+ info_snk_in => snk_in, -- original snk_in info
+
+ src_in => c_dp_siso_rdy,
+ src_out => src_out_arr(i)
+ );
end generate;
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd b/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
index aea3de86d7..6349ed97fa 100755
--- a/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
+++ b/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
@@ -20,32 +20,32 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Author:
--- . Eric Kooistra
--- Purpose:
--- . Deinterleave the input into g_nof_outputs parallel outputs, with one input
--- sample per output and all outputs valid at the same cycle.
--- Description:
--- . The snk_in blocks size should typically be an integer multiple of
--- g_nof_outputs. If the snk_in block size is an integer multiple of
--- g_nof_outputs, then the snk_in.eop occurs when cnt = g_nof_outputs-1, else
--- the snk_in.eop will break the deinterleaving and output immediately to
--- maintain output blocks with sop and eop.
--- . The snk_in.sop info (bsn, channel) and snk_in.eop info (empty, err) are
--- preserved and passed on to the src_out_arr outputs.
--- . The implementation supports siso flow control, thanks to that the
--- function is implemented combinatorially (so RL=0) using internal state
--- registers. The function only outputs when thereis valid input, therefore
--- it does not need to use src_in_arr().ready. The combinatorial output is
--- pipelined to ease timing closure.
--- Remark:
--- . This function is similar to dp_deinterleave by only supports m=1 to
--- g_nof_outputs and therefore the implementation is simpler.
+ -- Author:
+ -- . Eric Kooistra
+ -- Purpose:
+ -- . Deinterleave the input into g_nof_outputs parallel outputs, with one input
+ -- sample per output and all outputs valid at the same cycle.
+ -- Description:
+ -- . The snk_in blocks size should typically be an integer multiple of
+ -- g_nof_outputs. If the snk_in block size is an integer multiple of
+ -- g_nof_outputs, then the snk_in.eop occurs when cnt = g_nof_outputs-1, else
+ -- the snk_in.eop will break the deinterleaving and output immediately to
+ -- maintain output blocks with sop and eop.
+ -- . The snk_in.sop info (bsn, channel) and snk_in.eop info (empty, err) are
+ -- preserved and passed on to the src_out_arr outputs.
+ -- . The implementation supports siso flow control, thanks to that the
+ -- function is implemented combinatorially (so RL=0) using internal state
+ -- registers. The function only outputs when thereis valid input, therefore
+ -- it does not need to use src_in_arr().ready. The combinatorial output is
+ -- pipelined to ease timing closure.
+ -- Remark:
+ -- . This function is similar to dp_deinterleave by only supports m=1 to
+ -- g_nof_outputs and therefore the implementation is simpler.
entity dp_deinterleave_one_to_n is
generic (
@@ -149,18 +149,18 @@ begin
snk_out <= out_siso_arr(0); -- all out_siso_arr have the same siso, so wire output 0
u_pipeline_outputs : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_outputs,
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out_arr => out_siso_arr,
- snk_in_arr => out_sosi_arr,
- -- ST source
- src_in_arr => src_in_arr,
- src_out_arr => src_out_arr
- );
+ generic map (
+ g_nof_streams => g_nof_outputs,
+ g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out_arr => out_siso_arr,
+ snk_in_arr => out_sosi_arr,
+ -- ST source
+ src_in_arr => src_in_arr,
+ src_out_arr => src_out_arr
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_demux.vhd b/libraries/base/dp/src/vhdl/dp_demux.vhd
index f70721856d..6dee59f0bf 100644
--- a/libraries/base/dp/src/vhdl/dp_demux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_demux.vhd
@@ -20,42 +20,42 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose:
--- De-multiplex frames from one input stream with one or more channels onto
--- separate output streams.
--- Description:
--- If g_combined=TRUE then all outputs must be ready for the dp_demux to be
--- ready. This is because due to RL=1 the snk_in.channel and
--- src_in_arr().ready do not apply to the same clock cycle. The adavantage
--- of using g_combined=TRUE is that it takes minimal logic. The fact that it
--- works combinatorially may cause problems with achieving timing closure.
--- If g_combined=FALSE then only the output for the current channel needs to
--- be ready. This is possible because internally the dp_demux then operates
--- at RL=0 so it has a show-ahead on the valid snk_in.channel. The output is
--- again at RL=1 which has the additional benefit that the src_in_arr().ready
--- and the snk_out.ready SISO ready signals are connected via a register
--- stage. The RL adapter to get to RL=0 also registers the SOSI data signals.
--- The output selection scheme depends on g_mode:
--- 0: Use current channel to select the output port.
--- The snk_in.channel[log2(g_nof_output)-1:0] bits are used to select the
--- output port. The remaining snk_in.channel[high:log2(g_nof_output)]
--- bits are passed on to src_out_arr().channel (assuming typically
--- g_remove_channel_lo = TRUE).
--- 1: Use eop to select next output.
--- 2: Use external MM control input to select the output
--- Remark:
--- . For g_nof_output=1 the dp_demux collapses to wires, because ceil_log2(1)=1.
--- . The dp_mux adds true_log2(nof ports) low bits to src_out_arr.channel and
--- this dp_demux removes true_log2(nof ports) low bits from snk_in().channel.
--- . For demultiplexing time series frames or sample it can be applicable to
--- use g_remove_channel_lo=FALSE in combination with g_mode=1.
--- . Mode 0 and 2 two work for any sosi stream, mode 1 requires framed data i.e.
--- with eop.
+ -- Purpose:
+ -- De-multiplex frames from one input stream with one or more channels onto
+ -- separate output streams.
+ -- Description:
+ -- If g_combined=TRUE then all outputs must be ready for the dp_demux to be
+ -- ready. This is because due to RL=1 the snk_in.channel and
+ -- src_in_arr().ready do not apply to the same clock cycle. The adavantage
+ -- of using g_combined=TRUE is that it takes minimal logic. The fact that it
+ -- works combinatorially may cause problems with achieving timing closure.
+ -- If g_combined=FALSE then only the output for the current channel needs to
+ -- be ready. This is possible because internally the dp_demux then operates
+ -- at RL=0 so it has a show-ahead on the valid snk_in.channel. The output is
+ -- again at RL=1 which has the additional benefit that the src_in_arr().ready
+ -- and the snk_out.ready SISO ready signals are connected via a register
+ -- stage. The RL adapter to get to RL=0 also registers the SOSI data signals.
+ -- The output selection scheme depends on g_mode:
+ -- 0: Use current channel to select the output port.
+ -- The snk_in.channel[log2(g_nof_output)-1:0] bits are used to select the
+ -- output port. The remaining snk_in.channel[high:log2(g_nof_output)]
+ -- bits are passed on to src_out_arr().channel (assuming typically
+ -- g_remove_channel_lo = TRUE).
+ -- 1: Use eop to select next output.
+ -- 2: Use external MM control input to select the output
+ -- Remark:
+ -- . For g_nof_output=1 the dp_demux collapses to wires, because ceil_log2(1)=1.
+ -- . The dp_mux adds true_log2(nof ports) low bits to src_out_arr.channel and
+ -- this dp_demux removes true_log2(nof ports) low bits from snk_in().channel.
+ -- . For demultiplexing time series frames or sample it can be applicable to
+ -- use g_remove_channel_lo=FALSE in combination with g_mode=1.
+ -- . Mode 0 and 2 two work for any sosi stream, mode 1 requires framed data i.e.
+ -- with eop.
entity dp_demux is
generic (
@@ -165,8 +165,8 @@ begin
else
output_select <= g_nof_output - 1 - sel_ctrl;
end if;
- -- User might need this status port to indicate if/when the output has actually been switched
- sel_stat <= output_select;
+ -- User might need this status port to indicate if/when the output has actually been switched
+ sel_stat <= output_select;
end if;
end process;
@@ -182,16 +182,16 @@ begin
-- The dp_packet_detect component simply asserts its output from SOP to EOP
u_dp_packet_detect : entity work.dp_packet_detect
- generic map (
- g_latency => 0
- )
- port map (
- rst => rst,
- clk => clk,
- sosi => adapt_sosi,
- siso => adapt_siso, -- We're using the adapted sink_in with RL=0
- pkt_det => pkt_det
- );
+ generic map (
+ g_latency => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ sosi => adapt_sosi,
+ siso => adapt_siso, -- We're using the adapted sink_in with RL=0
+ pkt_det => pkt_det
+ );
end generate;
end generate;
@@ -235,20 +235,20 @@ begin
gen_individual : if g_combined = false and g_nof_output > 1 generate
-- Adapt input to RL = 0 to have show-ahead
u_rl_0 : entity work.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => adapt_siso,
- src_out => adapt_sosi
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => adapt_siso,
+ src_out => adapt_sosi
+ );
sel_channel <= adapt_sosi.channel;
sel_eop <= adapt_sosi.eop and adapt_siso.ready; -- RL = 0, so eop is only valid when the ready acknowledges it
@@ -282,20 +282,20 @@ begin
-- Back to output RL = 1
gen_rl_1 : for I in 0 to g_nof_output - 1 generate
u_incr : entity work.dp_latency_increase
- generic map (
- g_in_latency => 0,
- g_incr_latency => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => prev_src_in_arr(I),
- snk_in => pend_src_out_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
- );
+ generic map (
+ g_in_latency => 0,
+ g_incr_latency => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => prev_src_in_arr(I),
+ snk_in => pend_src_out_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
end generate;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_distribute.vhd b/libraries/base/dp/src/vhdl/dp_distribute.vhd
index 4165fd6370..20763f7c39 100644
--- a/libraries/base/dp/src/vhdl/dp_distribute.vhd
+++ b/libraries/base/dp/src/vhdl/dp_distribute.vhd
@@ -76,11 +76,11 @@
-- gets lost or an input is not used.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_distribute is
generic (
@@ -157,33 +157,33 @@ begin
gen_fifo : if g_use_fifo = true generate
gen_input : for I in 0 to g_nof_input - 1 generate
u_fifo : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => in_siso_arr(I),
- src_out => in_sosi_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => in_siso_arr(I),
+ src_out => in_sosi_arr(I)
+ );
end generate;
end generate;
@@ -195,20 +195,20 @@ begin
gen_dec : if g_decode_channel_lo = true generate
gen_i : for I in 0 to g_nof_input - 1 generate
u_dec : entity work.dp_packet_dec_channel_lo
- generic map (
- g_data_w => g_data_w,
- g_channel_lo => c_link_channel_lo
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => in_siso_arr(I),
- snk_in => in_sosi_arr(I),
- -- ST source
- src_in => rx_siso_arr(I),
- src_out => rx_sosi_arr(I)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_channel_lo => c_link_channel_lo
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => in_siso_arr(I),
+ snk_in => in_sosi_arr(I),
+ -- ST source
+ src_in => rx_siso_arr(I),
+ src_out => rx_sosi_arr(I)
+ );
end generate;
end generate;
@@ -220,22 +220,22 @@ begin
gen_transpose : if g_nof_input /= g_nof_output or g_transpose = true generate
gen_demux : for I in 0 to g_nof_input - 1 generate
u_demux : entity work.dp_demux
- generic map (
- g_mode => c_demux_mode,
- g_nof_output => g_nof_output,
- g_remove_channel_lo => c_demux_remove_channel_lo,
- g_combined => false
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => rx_siso_arr(I),
- snk_in => rx_sosi_arr(I),
- -- ST source
- src_in_arr => demux_siso_2arr(I),
- src_out_arr => demux_sosi_2arr(I)
- );
+ generic map (
+ g_mode => c_demux_mode,
+ g_nof_output => g_nof_output,
+ g_remove_channel_lo => c_demux_remove_channel_lo,
+ g_combined => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => rx_siso_arr(I),
+ snk_in => rx_sosi_arr(I),
+ -- ST source
+ src_in_arr => demux_siso_2arr(I),
+ src_out_arr => demux_sosi_2arr(I)
+ );
end generate;
-- Rewire to distribute
@@ -248,26 +248,26 @@ begin
gen_mux : for J in 0 to g_nof_output - 1 generate
u_mux : entity work.dp_mux
- generic map (
- -- MUX
- g_mode => c_mux_mode,
- g_nof_input => g_nof_input,
- g_append_channel_lo => c_mux_append_channel_lo,
- -- Input FIFO
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, g_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => mux_siso_2arr(J),
- snk_in_arr => mux_sosi_2arr(J),
- -- ST source
- src_in => tx_siso_arr(J),
- src_out => tx_sosi_arr(J)
- );
+ generic map (
+ -- MUX
+ g_mode => c_mux_mode,
+ g_nof_input => g_nof_input,
+ g_append_channel_lo => c_mux_append_channel_lo,
+ -- Input FIFO
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, g_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => mux_siso_2arr(J),
+ snk_in_arr => mux_sosi_2arr(J),
+ -- ST source
+ src_in => tx_siso_arr(J),
+ src_out => tx_sosi_arr(J)
+ );
end generate;
end generate;
@@ -279,18 +279,18 @@ begin
gen_enc : if g_encode_channel_lo = true generate
gen_j : for J in 0 to g_nof_output - 1 generate
u_enc : entity work.dp_packet_enc_channel_lo
- generic map (
- g_data_w => g_data_w,
- g_channel_lo => c_link_channel_lo
- )
- port map (
- -- ST sinks
- snk_out => tx_siso_arr(J),
- snk_in => tx_sosi_arr(J),
- -- ST source
- src_in => src_in_arr(J),
- src_out => src_out_arr(J)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_channel_lo => c_link_channel_lo
+ )
+ port map (
+ -- ST sinks
+ snk_out => tx_siso_arr(J),
+ snk_in => tx_sosi_arr(J),
+ -- ST source
+ src_in => src_in_arr(J),
+ src_out => src_out_arr(J)
+ );
end generate;
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_dummy_source.vhd b/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
index 33b96ad565..c8030b00b2 100644
--- a/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
@@ -23,10 +23,10 @@
-- Provide packetized dummy values when sink is ready
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_dummy_source is
generic (
@@ -38,7 +38,7 @@ entity dp_dummy_source is
g_dummy_empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0) := x"DD";
g_dummy_channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0) := x"DDDDDDDD";
g_dummy_err : std_logic_vector(c_dp_stream_error_w - 1 downto 0) := x"DDDDDDDD"
- );
+ );
port (
rst : in std_logic;
clk : in std_logic;
@@ -67,16 +67,16 @@ begin
src_out.err <= c_dp_sosi_dummy.err;
u_dp_block_gen: entity work.dp_block_gen
- generic map (
- g_nof_data => g_dummy_nof_data
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_nof_data => g_dummy_nof_data
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- src_in => src_in,
- src_out => block_sosi,
+ src_in => src_in,
+ src_out => block_sosi,
- en => '1'
- );
+ en => '1'
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_eop_extend.vhd b/libraries/base/dp/src/vhdl/dp_eop_extend.vhd
index c32b6480ea..5a9ddd3f88 100644
--- a/libraries/base/dp/src/vhdl/dp_eop_extend.vhd
+++ b/libraries/base/dp/src/vhdl/dp_eop_extend.vhd
@@ -21,15 +21,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
--- Purpose:
--- The extended eop output can be used to gate valid eop related stream info
--- like empty and error.
--- Description:
--- Extend the eop until the next sop.
+ -- Purpose:
+ -- The extended eop output can be used to gate valid eop related stream info
+ -- like empty and error.
+ -- Description:
+ -- Extend the eop until the next sop.
entity dp_eop_extend is
port (
@@ -45,13 +45,13 @@ architecture rtl of dp_eop_extend is
signal extend : std_logic;
begin
u_extend : entity common_lib.common_switch
- port map (
- rst => rst,
- clk => clk,
- switch_high => in_eop,
- switch_low => in_sop,
- out_level => extend
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => in_eop,
+ switch_low => in_sop,
+ out_level => extend
+ );
eop_extend <= (in_eop or extend) and not in_sop;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_example_dut.vhd b/libraries/base/dp/src/vhdl/dp_example_dut.vhd
index 5492efb386..2c3a31f3ab 100644
--- a/libraries/base/dp/src/vhdl/dp_example_dut.vhd
+++ b/libraries/base/dp/src/vhdl/dp_example_dut.vhd
@@ -163,9 +163,9 @@
-- the test bench.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_example_dut is
port (
diff --git a/libraries/base/dp/src/vhdl/dp_field_blk.vhd b/libraries/base/dp/src/vhdl/dp_field_blk.vhd
index abab971487..0f5b35c352 100644
--- a/libraries/base/dp/src/vhdl/dp_field_blk.vhd
+++ b/libraries/base/dp/src/vhdl/dp_field_blk.vhd
@@ -20,68 +20,68 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
-
--- Purpose:
--- . Source a DP data block of which the contents are read from snk_in.data when snk_in.valid = '1'
--- Description:
--- . The fields in snk_in.data are determined by g_field_arr;
--- . Each field can be overridden via MM when when its corresponding MM override bit is '1',
--- if override = '0' the field is taken from snk_in.data.
--- . The initial (default) values of the override bits are passed via g_field_sel(one bit per field);
--- . Both the SLV as the override (ovr) fields can be read back via MM;
--- . g_mode can be used to select in which mode dp_field_blk should work. Most of the time, the
--- default g_mode = 0 can be used. When using g_mode = 0, it is assumed that dp_field_blk must be
--- used in source mode when g_snk_data_w > g_src_data_w, else in sink mode. This is a typical
--- application as it is often the case that the total width of the field block is larger than the
--- serial data width as shown in the example below. There are cases where the width of the
--- field-block is smaller than the serial data words. Therefore it is possible to force either sink
--- or source mode.
--- . g_mode = 0: auto select mode based on g_snk_data_w and g_src_data_w.
--- . g_mode = 1: use dp_field_blk in source mode regardless of g_*_data_w.
--- . g_mode = 2: use dp_field_blk in sink mode regardless of g_*_data_w.
-
--- The diagrams below show dp_field_blk in source and sink configuration. For simplicity, the 5
--- fields are defined as follows (fields do not need to respect word boundaries):
--- . field_0 = 32b
--- . field_1 = 96b
--- . field_2 = 32b
--- --------------+
--- . Total =160b (*1 cycle)
---
--- ============================
--- dp_field_blk in source mode:
--- ============================
---
--- snk_in.data(160b) _
--- |f0| | \
--- |f1| =========> | \
--- |f2| | \
--- | \ field_slv(160b) _________ __________
--- | | |f0| |dp_repack| dp_repack_out_dat(5 cycles * 32b) |dp_fifo_sc|
--- | | =======> |f1| ======> | | =========> [f0,f1,f1,f1,f2] ==========> | | ==> src_out
--- | | |f2| |_________| |__________|
--- mm_fields_slv_out(160b)| /
--- |f0| | /
--- |f1| =========> | /|
--- |f2| |_/||
--- ||
--- ||
--- field_override_arr(3b)
---
--- ==========================
--- dp_field_blk in sink mode:
--- ==========================
--- _________ mm_fields_slv_in(160b)
--- snk_in.data(5 cycles * 32b) |dp_repack| |f0|
--- snk_in =========> [f0,f1,f1,f1,f2] =========> | | =====> |f1| ========> slv_out
--- |_________| |f2|
---
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
+
+ -- Purpose:
+ -- . Source a DP data block of which the contents are read from snk_in.data when snk_in.valid = '1'
+ -- Description:
+ -- . The fields in snk_in.data are determined by g_field_arr;
+ -- . Each field can be overridden via MM when when its corresponding MM override bit is '1',
+ -- if override = '0' the field is taken from snk_in.data.
+ -- . The initial (default) values of the override bits are passed via g_field_sel(one bit per field);
+ -- . Both the SLV as the override (ovr) fields can be read back via MM;
+ -- . g_mode can be used to select in which mode dp_field_blk should work. Most of the time, the
+ -- default g_mode = 0 can be used. When using g_mode = 0, it is assumed that dp_field_blk must be
+ -- used in source mode when g_snk_data_w > g_src_data_w, else in sink mode. This is a typical
+ -- application as it is often the case that the total width of the field block is larger than the
+ -- serial data width as shown in the example below. There are cases where the width of the
+ -- field-block is smaller than the serial data words. Therefore it is possible to force either sink
+ -- or source mode.
+ -- . g_mode = 0: auto select mode based on g_snk_data_w and g_src_data_w.
+ -- . g_mode = 1: use dp_field_blk in source mode regardless of g_*_data_w.
+ -- . g_mode = 2: use dp_field_blk in sink mode regardless of g_*_data_w.
+
+ -- The diagrams below show dp_field_blk in source and sink configuration. For simplicity, the 5
+ -- fields are defined as follows (fields do not need to respect word boundaries):
+ -- . field_0 = 32b
+ -- . field_1 = 96b
+ -- . field_2 = 32b
+ -- --------------+
+ -- . Total =160b (*1 cycle)
+ --
+ -- ============================
+ -- dp_field_blk in source mode:
+ -- ============================
+ --
+ -- snk_in.data(160b) _
+ -- |f0| | \
+ -- |f1| =========> | \
+ -- |f2| | \
+ -- | \ field_slv(160b) _________ __________
+ -- | | |f0| |dp_repack| dp_repack_out_dat(5 cycles * 32b) |dp_fifo_sc|
+ -- | | =======> |f1| ======> | | =========> [f0,f1,f1,f1,f2] ==========> | | ==> src_out
+ -- | | |f2| |_________| |__________|
+ -- mm_fields_slv_out(160b)| /
+ -- |f0| | /
+ -- |f1| =========> | /|
+ -- |f2| |_/||
+ -- ||
+ -- ||
+ -- field_override_arr(3b)
+ --
+ -- ==========================
+ -- dp_field_blk in sink mode:
+ -- ==========================
+ -- _________ mm_fields_slv_in(160b)
+ -- snk_in.data(5 cycles * 32b) |dp_repack| |f0|
+ -- snk_in =========> [f0,f1,f1,f1,f2] =========> | | =====> |f1| ========> slv_out
+ -- |_________| |f2|
+ --
entity dp_field_blk is
generic (
@@ -109,26 +109,26 @@ entity dp_field_blk is
-- Source mode
-- . Single cycle SLV input
--- slv_in : IN STD_LOGIC_VECTOR(g_snk_data_w-1 DOWNTO 0) := (OTHERS=> '0'); -- Input for the RW fields defined in g_field_arr
--- slv_in_val : IN STD_LOGIC := '0';
+ -- slv_in : IN STD_LOGIC_VECTOR(g_snk_data_w-1 DOWNTO 0) := (OTHERS=> '0'); -- Input for the RW fields defined in g_field_arr
+ -- slv_in_val : IN STD_LOGIC := '0';
-- . Multi cycle block output
-- Sink mode
-- . Multi cycle block input
-- . Single cycle SLV output
--- slv_out : OUT STD_LOGIC_VECTOR(g_src_data_w-1 DOWNTO 0); -- Output for the RO fields defined in g_field_arr
--- slv_out_val : OUT STD_LOGIC;
+ -- slv_out : OUT STD_LOGIC_VECTOR(g_src_data_w-1 DOWNTO 0); -- Output for the RO fields defined in g_field_arr
+ -- slv_out_val : OUT STD_LOGIC;
reg_slv_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_slv_miso : out t_mem_miso
--- reg_ovr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
--- reg_ovr_miso : OUT t_mem_miso
+ -- reg_ovr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ -- reg_ovr_miso : OUT t_mem_miso
);
end dp_field_blk;
architecture str of dp_field_blk is
--- CONSTANT c_ovr_field_arr : t_common_field_arr(g_field_arr'RANGE) := field_ovr_arr(g_field_arr, g_field_sel);
+ -- CONSTANT c_ovr_field_arr : t_common_field_arr(g_field_arr'RANGE) := field_ovr_arr(g_field_arr, g_field_sel);
-- Mode: fields to data block (c_field_to_block=True) or data block to fields (c_field_to_block=False)
-- a.k.a. wire to narrow or narrow to wide
@@ -191,65 +191,65 @@ begin
snk_out <= dp_repack_data_snk_out;
u_dp_repack_data : entity work.dp_repack_data
- generic map (
- g_in_dat_w => g_snk_data_w,
- g_in_nof_words => ceil_div(g_src_data_w, g_snk_data_w),
- g_out_dat_w => g_src_data_w,
- g_out_nof_words => ceil_div(g_snk_data_w, g_src_data_w),
- g_in_symbol_w => g_in_symbol_w,
- g_out_symbol_w => g_out_symbol_w,
- g_pipeline_ready => g_pipeline_ready
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => dp_repack_data_snk_out,
- snk_in => dp_repack_data_snk_in,
-
- src_in => dp_repack_data_src_in,
- src_out => dp_repack_data_src_out
- );
+ generic map (
+ g_in_dat_w => g_snk_data_w,
+ g_in_nof_words => ceil_div(g_src_data_w, g_snk_data_w),
+ g_out_dat_w => g_src_data_w,
+ g_out_nof_words => ceil_div(g_snk_data_w, g_src_data_w),
+ g_in_symbol_w => g_in_symbol_w,
+ g_out_symbol_w => g_out_symbol_w,
+ g_pipeline_ready => g_pipeline_ready
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => dp_repack_data_snk_out,
+ snk_in => dp_repack_data_snk_in,
+
+ src_in => dp_repack_data_src_in,
+ src_out => dp_repack_data_src_out
+ );
---------------------------------------------------------------------------------------
-- mm_fields for MM access to each field
---------------------------------------------------------------------------------------
u_mm_fields_slv: entity mm_lib.mm_fields
- generic map(
- g_field_arr => g_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_mosi => reg_slv_mosi,
- mm_miso => reg_slv_miso,
-
- slv_clk => dp_clk,
- slv_rst => dp_rst,
-
- slv_in => mm_fields_slv_in,
- slv_in_val => mm_fields_slv_in_val,
- slv_out => mm_fields_slv_out
- );
+ generic map(
+ g_field_arr => g_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_mosi => reg_slv_mosi,
+ mm_miso => reg_slv_miso,
+
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
+
+ slv_in => mm_fields_slv_in,
+ slv_in_val => mm_fields_slv_in_val,
+ slv_out => mm_fields_slv_out
+ );
---------------------------------------------------------------------------------------
-- mm_fields to set override bits
--- ---------------------------------------------------------------------------------------
--- u_mm_fields_ovr: ENTITY mm_lib.mm_fields
--- GENERIC MAP(
--- g_field_arr => field_arr_set_mode(c_ovr_field_arr, "RW") -- override fields are always RW
--- )
--- PORT MAP (
--- mm_clk => mm_clk,
--- mm_rst => mm_rst,
---
--- mm_mosi => reg_ovr_mosi,
--- mm_miso => reg_ovr_miso,
---
--- slv_clk => dp_clk,
--- slv_rst => dp_rst,
---
--- slv_out => field_override_arr
--- );
+ -- ---------------------------------------------------------------------------------------
+ -- u_mm_fields_ovr: ENTITY mm_lib.mm_fields
+ -- GENERIC MAP(
+ -- g_field_arr => field_arr_set_mode(c_ovr_field_arr, "RW") -- override fields are always RW
+ -- )
+ -- PORT MAP (
+ -- mm_clk => mm_clk,
+ -- mm_rst => mm_rst,
+ --
+ -- mm_mosi => reg_ovr_mosi,
+ -- mm_miso => reg_ovr_miso,
+ --
+ -- slv_clk => dp_clk,
+ -- slv_rst => dp_rst,
+ --
+ -- slv_out => field_override_arr
+ -- );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
index b611fd2797..f08abd26bb 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
@@ -40,11 +40,11 @@
-- ready signal.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_core is
generic (
@@ -97,8 +97,9 @@ architecture str of dp_fifo_core is
constant c_fifo_almost_full : natural := g_fifo_size - g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
constant c_fifo_almost_xon : natural := g_fifo_size - g_fifo_af_xon; -- FIFO almost full level for snk_out.xon
- constant c_fifo_dat_w : natural := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl,
- g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w); -- concat via FIFO
+ constant c_fifo_dat_w : natural := func_slv_concat_w(
+ c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl,
+ g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w); -- concat via FIFO
signal nxt_snk_out : t_dp_siso := c_dp_siso_rst;
@@ -153,13 +154,13 @@ begin
-- fifo wr wires
fifo_wr_req <= snk_in.valid;
fifo_wr_dat <= func_slv_concat(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl,
- wr_data,
- snk_in.bsn( g_bsn_w - 1 downto 0),
- snk_in.empty( g_empty_w - 1 downto 0),
- snk_in.channel(g_channel_w - 1 downto 0),
- snk_in.err( g_error_w - 1 downto 0),
- wr_sync,
- wr_ctrl);
+ wr_data,
+ snk_in.bsn( g_bsn_w - 1 downto 0),
+ snk_in.empty( g_empty_w - 1 downto 0),
+ snk_in.channel(g_channel_w - 1 downto 0),
+ snk_in.err( g_error_w - 1 downto 0),
+ wr_sync,
+ wr_ctrl);
-- pass on frame level flow control from src_in.xon to upstream snk_out.xon, and
-- add flow contol dependent on whether the fifo can fit another block
@@ -170,25 +171,25 @@ begin
gen_common_fifo_sc : if g_use_dual_clock = false generate
u_common_fifo_sc : entity common_lib.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_lut => g_use_lut_sc,
- g_dat_w => c_fifo_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- wr_dat => fifo_wr_dat,
- wr_req => fifo_wr_req,
- wr_ful => fifo_wr_ful,
- rd_dat => fifo_rd_dat,
- rd_req => fifo_rd_req,
- rd_emp => fifo_rd_emp,
- rd_val => fifo_rd_val,
- usedw => fifo_rd_usedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_lut => g_use_lut_sc,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rd_val => fifo_rd_val,
+ usedw => fifo_rd_usedw
+ );
wr_init <= '0'; -- to avoid no driver warning in synthesis
fifo_wr_usedw <= fifo_rd_usedw;
@@ -196,26 +197,26 @@ begin
gen_common_fifo_dc : if g_use_dual_clock = true generate
u_common_fifo_dc : entity common_lib.common_fifo_dc
- generic map (
- g_technology => g_technology,
- g_dat_w => c_fifo_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => arst,
- wr_clk => wr_clk,
- wr_dat => fifo_wr_dat,
- wr_req => fifo_wr_req,
- wr_init_out => wr_init,
- wr_ful => fifo_wr_ful,
- wrusedw => fifo_wr_usedw,
- rd_clk => rd_clk,
- rd_dat => fifo_rd_dat,
- rd_req => fifo_rd_req,
- rd_emp => fifo_rd_emp,
- rdusedw => fifo_rd_usedw,
- rd_val => fifo_rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => arst,
+ wr_clk => wr_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_init_out => wr_init,
+ wr_ful => fifo_wr_ful,
+ wrusedw => fifo_wr_usedw,
+ rd_clk => rd_clk,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rdusedw => fifo_rd_usedw,
+ rd_val => fifo_rd_val
+ );
arst <= wr_rst or rd_rst;
end generate;
@@ -244,18 +245,18 @@ begin
rd_sosi.eop <= fifo_rd_val and rd_ctrl(0);
u_ready_latency : entity work.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => g_fifo_rl
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- ST sink
- snk_out => rd_siso,
- snk_in => rd_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => g_fifo_rl
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso,
+ snk_in => rd_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
index b3a020284e..f8cc0e6120 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
@@ -44,11 +44,11 @@
-- . It is possible to add additonal signals to the fifo using in_aux/out_aux.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_core_arr is
generic (
@@ -107,8 +107,9 @@ architecture str of dp_fifo_core_arr is
constant c_fifo_almost_full : natural := g_fifo_size - g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
constant c_fifo_almost_xon : natural := g_fifo_size - g_fifo_af_xon; -- FIFO almost full level for snk_out.xon
- constant c_fifo_dat_w : natural := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
- c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w); -- concat via FIFO
+ constant c_fifo_dat_w : natural := func_slv_concat_w(
+ c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
+ c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w); -- concat via FIFO
signal nxt_snk_out : t_dp_siso := c_dp_siso_rst;
@@ -175,14 +176,14 @@ begin
-- fifo wr wires
fifo_wr_req <= snk_in_arr(0).valid;
fifo_wr_dat <= func_slv_concat(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
- wr_data,
- snk_in_arr(0).bsn( g_bsn_w - 1 downto 0),
- snk_in_arr(0).empty( g_empty_w - 1 downto 0),
- snk_in_arr(0).channel(g_channel_w - 1 downto 0),
- snk_in_arr(0).err( g_error_w - 1 downto 0),
- wr_sync,
- wr_ctrl,
- wr_aux);
+ wr_data,
+ snk_in_arr(0).bsn( g_bsn_w - 1 downto 0),
+ snk_in_arr(0).empty( g_empty_w - 1 downto 0),
+ snk_in_arr(0).channel(g_channel_w - 1 downto 0),
+ snk_in_arr(0).err( g_error_w - 1 downto 0),
+ wr_sync,
+ wr_ctrl,
+ wr_aux);
-- pass on frame level flow control from src_in.xon to upstream snk_out.xon, and
-- add flow contol dependent on whether the fifo can fit another block
@@ -193,58 +194,58 @@ begin
gen_common_fifo_sc : if g_use_dual_clock = false generate
u_common_fifo_sc : entity common_lib.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_lut => g_use_lut_sc,
- g_dat_w => c_fifo_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- wr_dat => fifo_wr_dat,
- wr_req => fifo_wr_req,
- wr_ful => fifo_wr_ful,
- rd_dat => fifo_rd_dat,
- rd_req => fifo_rd_req,
- rd_emp => fifo_rd_emp,
- rd_val => fifo_rd_val,
- usedw => fifo_rd_usedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_lut => g_use_lut_sc,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rd_val => fifo_rd_val,
+ usedw => fifo_rd_usedw
+ );
fifo_wr_usedw <= fifo_rd_usedw;
end generate;
gen_common_fifo_dc : if g_use_dual_clock = true generate
u_common_fifo_dc : entity common_lib.common_fifo_dc
- generic map (
- g_technology => g_technology,
- g_dat_w => c_fifo_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => arst,
- wr_clk => wr_clk,
- wr_dat => fifo_wr_dat,
- wr_req => fifo_wr_req,
- wr_ful => fifo_wr_ful,
- wrusedw => fifo_wr_usedw,
- rd_clk => rd_clk,
- rd_dat => fifo_rd_dat,
- rd_req => fifo_rd_req,
- rd_emp => fifo_rd_emp,
- rdusedw => fifo_rd_usedw,
- rd_val => fifo_rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => arst,
+ wr_clk => wr_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ wrusedw => fifo_wr_usedw,
+ rd_clk => rd_clk,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rdusedw => fifo_rd_usedw,
+ rd_val => fifo_rd_val
+ );
arst <= wr_rst or rd_rst;
end generate;
-- Extract the data from the wide FIFO output SLV. rd_data will be assigned to rd_sosi.data or rd_sosi.im & rd_sosi.re depending on g_use_complex.
rd_data <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
- c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w,
- fifo_rd_dat, 0);
+ c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w,
+ fifo_rd_dat, 0);
-- fifo rd wires
-- SISO
@@ -273,6 +274,24 @@ begin
rd_sosi_arr(I).eop <= fifo_rd_val and rd_ctrl(0);
u_ready_latency : entity work.dp_latency_adapter
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => g_fifo_rl
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso_arr(I),
+ snk_in => rd_sosi_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
+ end generate;
+
+ -- Using extra dp_latency_adapter for aux signal
+ u_ready_latency_aux : entity work.dp_latency_adapter
generic map (
g_in_latency => 1,
g_out_latency => g_fifo_rl
@@ -281,27 +300,9 @@ begin
rst => rd_rst,
clk => rd_clk,
-- ST sink
- snk_out => rd_siso_arr(I),
- snk_in => rd_sosi_arr(I),
+ snk_in => in_aux_sosi,
-- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
+ src_in => src_in_arr(0),
+ src_out => out_aux_sosi
);
- end generate;
-
- -- Using extra dp_latency_adapter for aux signal
- u_ready_latency_aux : entity work.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => g_fifo_rl
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- ST sink
- snk_in => in_aux_sosi,
- -- ST source
- src_in => src_in_arr(0),
- src_out => out_aux_sosi
- );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
index 3ec0c419a8..b4b3561e22 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
@@ -23,11 +23,11 @@
-- Description: See dp_fifo_core.vhd.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_dc is
generic (
@@ -72,42 +72,42 @@ end dp_fifo_dc;
architecture str of dp_fifo_dc is
begin
u_dp_fifo_core : entity work.dp_fifo_core
- generic map (
- g_technology => g_technology,
- g_use_dual_clock => true,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => g_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_usedw,
- rd_usedw => rd_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_use_dual_clock => true,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => g_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
index 5bc9dffb7f..8c897f8424 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
@@ -25,11 +25,11 @@
-- Description: See dp_fifo_core_arr.vhd.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_dc_arr is
generic (
@@ -79,47 +79,47 @@ end dp_fifo_dc_arr;
architecture str of dp_fifo_dc_arr is
begin
u_dp_fifo_core_arr : entity work.dp_fifo_core_arr
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_use_dual_clock => true,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_aux_w => g_aux_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_aux => g_use_aux,
- g_use_ctrl => g_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_usedw,
- rd_usedw => rd_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out_arr => snk_out_arr,
- snk_in_arr => snk_in_arr,
- in_aux => in_aux,
- -- ST source
- src_in_arr => src_in_arr,
- src_out_arr => src_out_arr,
- out_aux => out_aux
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_use_dual_clock => true,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_aux_w => g_aux_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_aux => g_use_aux,
+ g_use_ctrl => g_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ in_aux => in_aux,
+ -- ST source
+ src_in_arr => src_in_arr,
+ src_out_arr => src_out_arr,
+ out_aux => out_aux
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
index 2162fd4be1..59ebc922cd 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
@@ -101,11 +101,11 @@
-- . add this multi tb-tb test bench to tb_tb_tb_dp_backpressure.vhd
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_dc_mixed_widths is
generic (
@@ -197,37 +197,37 @@ begin
gen_equal : if c_nof_narrow = 1 generate -- fall back to equal width FIFO
u_dp_fifo_dc : entity work.dp_fifo_dc
- generic map (
- g_technology => g_technology,
- g_data_w => g_wr_data_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_ctrl => g_use_ctrl,
- g_fifo_size => g_wr_fifo_size,
- g_fifo_af_margin => g_wr_fifo_af_margin,
- g_fifo_rl => g_rd_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- ST sink
- snk_out => i_snk_out,
- snk_in => snk_in,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_usedw,
- rd_usedw => rd_usedw,
- rd_emp => rd_emp,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_wr_data_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_ctrl => g_use_ctrl,
+ g_fifo_size => g_wr_fifo_size,
+ g_fifo_af_margin => g_wr_fifo_af_margin,
+ g_fifo_rl => g_rd_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- ST sink
+ snk_out => i_snk_out,
+ snk_in => snk_in,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate; -- gen_equal
gen_mixed : if c_nof_narrow > 1 generate -- mixed width FIFO
@@ -266,26 +266,26 @@ begin
fifo_rd_req <= rd_siso.ready;
u_fifo_mw : entity common_lib.common_fifo_dc_mixed_widths
- generic map (
- g_technology => g_technology,
- g_nof_words => g_wr_fifo_size, -- FIFO size in nof wr_dat words
- g_wr_dat_w => c_fifo_wr_dat_w,
- g_rd_dat_w => c_fifo_rd_dat_w
- )
- port map (
- rst => arst,
- wr_clk => wr_clk,
- wr_dat => fifo_wr_dat,
- wr_req => fifo_wr_req,
- wr_ful => fifo_wr_ful,
- wrusedw => i_wr_usedw,
- rd_clk => rd_clk,
- rd_dat => fifo_rd_dat,
- rd_req => fifo_rd_req,
- rd_emp => rd_emp,
- rdusedw => rd_usedw,
- rd_val => fifo_rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_words => g_wr_fifo_size, -- FIFO size in nof wr_dat words
+ g_wr_dat_w => c_fifo_wr_dat_w,
+ g_rd_dat_w => c_fifo_rd_dat_w
+ )
+ port map (
+ rst => arst,
+ wr_clk => wr_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ wrusedw => i_wr_usedw,
+ rd_clk => rd_clk,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => rd_emp,
+ rdusedw => rd_usedw,
+ rd_val => fifo_rd_val
+ );
-- FIFO write multiple parallel --> read one serial
gen_wr_wide : if c_wr_wide = true generate
@@ -445,19 +445,19 @@ begin
-- Support show ahead FIFO with ready latency = 0 at read output
u_rl : entity work.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => g_rd_fifo_rl
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- ST sink
- snk_out => rd_siso,
- snk_in => rd_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => g_rd_fifo_rl
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso,
+ snk_in => rd_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate; -- gen_mixed
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
index 5ba44fca04..2ad8caf373 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
@@ -26,11 +26,11 @@
-- for new designs.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill is
generic (
@@ -78,44 +78,44 @@ end dp_fifo_fill;
architecture str of dp_fifo_fill is
begin
u_dp_fifo_fill_sc : entity work.dp_fifo_fill_sc
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- usedw => usedw,
- rd_emp => rd_emp,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ usedw => usedw,
+ rd_emp => rd_emp,
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b => wr_usedw_32b,
- rd_usedw_32b => rd_usedw_32b,
- rd_fill_32b => rd_fill_32b,
+ -- MM control FIFO filling (assume 32 bit MM interface)
+ wr_usedw_32b => wr_usedw_32b,
+ rd_usedw_32b => rd_usedw_32b,
+ rd_fill_32b => rd_fill_32b,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
index f7c848b155..707c2ccbb6 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
@@ -57,11 +57,11 @@
-- directly.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_core is
generic (
@@ -156,83 +156,83 @@ begin
gen_dp_fifo_sc : if g_use_dual_clock = false generate
u_dp_fifo_sc : entity work.dp_fifo_sc
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => c_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => c_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => c_fifo_rl
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- usedw => rd_fifo_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, for RL = 1 rd_siso.ready acts as read request
- src_out => rd_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => c_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => c_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => c_fifo_rl
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ usedw => rd_fifo_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, for RL = 1 rd_siso.ready acts as read request
+ src_out => rd_sosi
+ );
wr_fifo_usedw <= rd_fifo_usedw;
end generate;
gen_dp_fifo_dc : if g_use_dual_clock = true generate
u_dp_fifo_dc : entity work.dp_fifo_dc
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => c_use_ctrl,
- --g_use_complex => g_use_complex,
- g_fifo_size => c_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => c_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_fifo_usedw,
- rd_usedw => rd_fifo_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
- src_out => rd_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => c_use_ctrl,
+ --g_use_complex => g_use_complex,
+ g_fifo_size => c_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => c_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_fifo_usedw,
+ rd_usedw => rd_fifo_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
+ src_out => rd_sosi
+ );
end generate;
no_fill : if g_fifo_fill = 0 generate
@@ -326,18 +326,18 @@ begin
-- Hold the sink input for source output
u_snk : entity work.dp_hold_input
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- ST sink
- snk_out => rd_siso, -- SISO ready
- snk_in => rd_sosi, -- SOSI
- -- ST source
- src_in => hold_src_in, -- SISO ready
- next_src_out => OPEN, -- SOSI
- pend_src_out => pend_src_out,
- src_out_reg => i_src_out
- );
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso, -- SISO ready
+ snk_in => rd_sosi, -- SOSI
+ -- ST source
+ src_in => hold_src_in, -- SISO ready
+ next_src_out => OPEN, -- SOSI
+ pend_src_out => pend_src_out,
+ src_out_reg => i_src_out
+ );
p_state : process(state, src_in, xon_reg, pend_src_out, rd_fifo_usedw, rd_fill_ctrl)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
index e766edd8f6..f75621af44 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
@@ -24,11 +24,11 @@
-- Description: See dp_fifo_fill_core.vhd.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_dc is
generic (
@@ -76,45 +76,45 @@ end dp_fifo_fill_dc;
architecture str of dp_fifo_fill_dc is
begin
u_dp_fifo_fill_core : entity work.dp_fifo_fill_core
- generic map (
- g_technology => g_technology,
- g_use_dual_clock => true,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_usedw,
- rd_usedw => rd_usedw,
- rd_emp => rd_emp,
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b => wr_usedw_32b,
- rd_usedw_32b => rd_usedw_32b,
- rd_fill_32b => rd_fill_32b,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_use_dual_clock => true,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- MM control FIFO filling (assume 32 bit MM interface)
+ wr_usedw_32b => wr_usedw_32b,
+ rd_usedw_32b => rd_usedw_32b,
+ rd_fill_32b => rd_fill_32b,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index c7b793d0b5..b55f932a9d 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -53,11 +53,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_eop is
generic (
@@ -166,61 +166,61 @@ begin
rd_fill_ctrl <= rd_fill_32b(c_fifo_size_w - 1 downto 0);
u_dp_fifo_core : entity work.dp_fifo_core
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_dual_clock => g_use_dual_clock,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => c_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => c_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => c_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_fifo_usedw,
- rd_usedw => rd_fifo_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
- src_out => rd_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_dual_clock => g_use_dual_clock,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => c_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => c_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => c_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_fifo_usedw,
+ rd_usedw => rd_fifo_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
+ src_out => rd_sosi
+ );
-- Transfer eop counter across clock domains for dual clock
gen_rd_eop_cnt_dc : if g_use_dual_clock = true generate
reg_wr_eop_cnt <= TO_UVEC(wr_eop_cnt, c_word_w);
u_common_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => wr_rst,
- in_clk => wr_clk,
- in_dat => reg_wr_eop_cnt,
- in_new => wr_eop_new,
- in_done => wr_eop_done,
- out_rst => rd_rst,
- out_clk => rd_clk,
- out_dat => reg_rd_eop_cnt,
- out_new => rd_eop_new
- );
+ port map (
+ in_rst => wr_rst,
+ in_clk => wr_clk,
+ in_dat => reg_wr_eop_cnt,
+ in_new => wr_eop_new,
+ in_done => wr_eop_done,
+ out_rst => rd_rst,
+ out_clk => rd_clk,
+ out_dat => reg_rd_eop_cnt,
+ out_new => rd_eop_new
+ );
end generate;
-- No need to transfer eop counter across clock domains for single clock
@@ -329,18 +329,18 @@ begin
-- Hold the sink input for source output
u_snk : entity work.dp_hold_input
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- ST sink
- snk_out => rd_siso, -- SISO ready
- snk_in => rd_sosi, -- SOSI
- -- ST source
- src_in => hold_src_in, -- SISO ready
- next_src_out => OPEN, -- SOSI
- pend_src_out => pend_src_out,
- src_out_reg => i_src_out
- );
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso, -- SISO ready
+ snk_in => rd_sosi, -- SOSI
+ -- ST source
+ src_in => hold_src_in, -- SISO ready
+ next_src_out => OPEN, -- SOSI
+ pend_src_out => pend_src_out,
+ src_out_reg => i_src_out
+ );
end generate;
gen_rl_0 : if g_fifo_rl = 0 generate
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
index f7d22ea5bd..5c66adbb43 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
@@ -25,11 +25,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_eop_sc is
generic (
@@ -76,47 +76,47 @@ end dp_fifo_fill_eop_sc;
architecture wrap of dp_fifo_fill_eop_sc is
begin
u_dp_fifo_fill_eop : entity work.dp_fifo_fill_eop
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_dual_clock => false, -- single clock
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => rst,
- wr_clk => clk,
- rd_rst => rst,
- rd_clk => clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => OPEN,
- rd_usedw => usedw, -- use rd_usedw, similar as in dp_fifo_sc, dp_fifo_fill_sc
- rd_emp => rd_emp,
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b => wr_usedw_32b,
- rd_usedw_32b => rd_usedw_32b,
- rd_fill_32b => rd_fill_32b,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_dual_clock => false, -- single clock
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => clk,
+ rd_rst => rst,
+ rd_clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => OPEN,
+ rd_usedw => usedw, -- use rd_usedw, similar as in dp_fifo_sc, dp_fifo_fill_sc
+ rd_emp => rd_emp,
+ -- MM control FIFO filling (assume 32 bit MM interface)
+ wr_usedw_32b => wr_usedw_32b,
+ rd_usedw_32b => rd_usedw_32b,
+ rd_fill_32b => rd_fill_32b,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end wrap;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
index d5dabeee58..bcf95a5415 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
@@ -50,9 +50,9 @@
-- |-----------------------------------------------------------------------|
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_fifo_fill_reg is
generic (
@@ -82,11 +82,12 @@ architecture str of dp_fifo_fill_reg is
constant c_nof_regs_per_stream : natural := 4; -- Must always be a power of 2 in order to meet the python register definition.
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_streams * c_nof_regs_per_stream),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => g_nof_streams * c_nof_regs_per_stream,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_streams * c_nof_regs_per_stream),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => g_nof_streams * c_nof_regs_per_stream,
+ init_sl => '0');
-- Registers in st_clk domain
signal in_arr_reg : std_logic_vector(g_nof_streams * c_nof_regs_per_stream * c_word_w - 1 downto 0) := (others => '0');
@@ -101,47 +102,47 @@ begin
end generate;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1,
- g_readback => true,
- g_reg => c_mm_reg,
- g_init_reg => (others => '1')
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1,
+ g_readback => true,
+ g_reg => c_mm_reg,
+ g_init_reg => (others => '1')
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => sla_in,
- sla_out => sla_out,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => sla_in,
+ sla_out => sla_out,
- -- MM registers in st_clk domain
- reg_wr_arr => reg_wr_arr,
- reg_rd_arr => reg_rd_arr,
- in_new => OPEN,
- in_reg => in_arr_reg, -- read
- out_reg => OPEN, -- write
- out_new => open
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => reg_wr_arr,
+ reg_rd_arr => reg_rd_arr,
+ in_new => OPEN,
+ in_reg => in_arr_reg, -- read
+ out_reg => OPEN, -- write
+ out_new => open
+ );
gen_peak_meters : for I in 0 to g_nof_streams - 1 generate
u_peak_meter : entity common_lib.common_peak
- generic map(
- g_dat_w => c_word_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- in_dat => used_w((I + 1) * c_word_w - 1 downto I * c_word_w),
- in_val => '1',
- in_clear => reg_rd_arr(I * c_nof_regs_per_stream + c_reg_max_used_words_offset),
- out_dat => peak_used_w((I + 1) * c_word_w - 1 downto I * c_word_w),
- out_val => open
- );
+ generic map(
+ g_dat_w => c_word_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ in_dat => used_w((I + 1) * c_word_w - 1 downto I * c_word_w),
+ in_val => '1',
+ in_clear => reg_rd_arr(I * c_nof_regs_per_stream + c_reg_max_used_words_offset),
+ out_dat => peak_used_w((I + 1) * c_word_w - 1 downto I * c_word_w),
+ out_val => open
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
index 2fc428f432..0c0da0fd41 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
@@ -24,11 +24,11 @@
-- Description: See dp_fifo_fill_core.vhd.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_sc is
generic (
@@ -77,46 +77,46 @@ end dp_fifo_fill_sc;
architecture str of dp_fifo_fill_sc is
begin
u_dp_fifo_fill_core : entity work.dp_fifo_fill_core
- generic map (
- g_technology => g_technology,
- g_use_dual_clock => false,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => rst,
- wr_clk => clk,
- rd_rst => rst,
- rd_clk => clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => OPEN,
- rd_usedw => usedw,
- rd_emp => rd_emp,
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b => wr_usedw_32b,
- rd_usedw_32b => rd_usedw_32b,
- rd_fill_32b => rd_fill_32b,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_use_dual_clock => false,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => clk,
+ rd_rst => rst,
+ rd_clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => OPEN,
+ rd_usedw => usedw,
+ rd_emp => rd_emp,
+ -- MM control FIFO filling (assume 32 bit MM interface)
+ wr_usedw_32b => wr_usedw_32b,
+ rd_usedw_32b => rd_usedw_32b,
+ rd_fill_32b => rd_fill_32b,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
index 0ee926636d..bce1fc2193 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
@@ -20,30 +20,30 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose:
--- Provide MM access to the ST input of a FIFO.
--- Description:
--- An MM master can directly write the FIFO, provided that the MM data width
--- (g_mm_word_w) fits within the ST data width.
--- The MM master can read the mm_usedw[] value to know how many valid data
--- words are in the FIFO.
--- The MM master can read the mm_availw[] value to know how many valid data
--- it can write to the FIFO in a loop, until it needs to check mm_availw[]
--- again. The mm_availw[] is defined as g_fifo_size - g_fifo_af_margin -
--- mm_usedw[].
--- When mm_availw[] > 0 then the MM master can be sure that the mm_wrdata
--- will fit in the FIFO. Therefore it is not needed to use src_out.ready and
--- in this way the MM master does not need to check whether the FIFO has free
--- space left for every write FIFO data access.
--- Remark:
--- . This dp_fifo_from_mm connects to the MM clock domain side of the FIFO,
--- hence is operates entirely in the MM clock domain.
--- . The ST sop, eop, empty, channel and error fields are not supported.
+ -- Purpose:
+ -- Provide MM access to the ST input of a FIFO.
+ -- Description:
+ -- An MM master can directly write the FIFO, provided that the MM data width
+ -- (g_mm_word_w) fits within the ST data width.
+ -- The MM master can read the mm_usedw[] value to know how many valid data
+ -- words are in the FIFO.
+ -- The MM master can read the mm_availw[] value to know how many valid data
+ -- it can write to the FIFO in a loop, until it needs to check mm_availw[]
+ -- again. The mm_availw[] is defined as g_fifo_size - g_fifo_af_margin -
+ -- mm_usedw[].
+ -- When mm_availw[] > 0 then the MM master can be sure that the mm_wrdata
+ -- will fit in the FIFO. Therefore it is not needed to use src_out.ready and
+ -- in this way the MM master does not need to check whether the FIFO has free
+ -- space left for every write FIFO data access.
+ -- Remark:
+ -- . This dp_fifo_from_mm connects to the MM clock domain side of the FIFO,
+ -- hence is operates entirely in the MM clock domain.
+ -- . The ST sop, eop, empty, channel and error fields are not supported.
entity dp_fifo_from_mm is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
index 56aa690919..8123f5ae64 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_fifo_from_mm_reg is
port (
@@ -37,15 +37,16 @@ entity dp_fifo_from_mm_reg is
-- MM registers
mm_wr_usedw : in std_logic_vector(c_word_w - 1 downto 0);
mm_wr_availw : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end dp_fifo_from_mm_reg;
architecture rtl of dp_fifo_from_mm_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(2),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(2),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2,
+ init_sl => '0');
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_info.vhd b/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
index 05cdd07ee2..c4c80d5fad 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
@@ -71,11 +71,11 @@
-- - dp_block_gen_valid_arr
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_info is
generic (
@@ -155,19 +155,19 @@ begin
-- Data pipeline register to compensate for the fifo rd_req to rd_val latency of 1
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => data_snk_out,
- snk_in => data_snk_in,
- -- ST source
- src_in => dp_pipeline_data_src_in,
- src_out => dp_pipeline_data_src_out
- );
+ generic map (
+ g_pipeline => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => data_snk_out,
+ snk_in => data_snk_in,
+ -- ST source
+ src_in => dp_pipeline_data_src_in,
+ src_out => dp_pipeline_data_src_out
+ );
-- Buffer sop info
gen_info_sop : if c_fifo_sop_dat_w > 0 generate
@@ -177,30 +177,30 @@ begin
-- concatenate the sop data to use a single FIFO
wr_sync(0) <= info_snk_in.sync;
fifo_sop_wr_dat <= func_slv_concat(g_use_sync, g_use_bsn, g_use_channel,
- wr_sync,
- info_snk_in.bsn(g_bsn_w - 1 downto 0),
- info_snk_in.channel(g_channel_w - 1 downto 0));
+ wr_sync,
+ info_snk_in.bsn(g_bsn_w - 1 downto 0),
+ info_snk_in.channel(g_channel_w - 1 downto 0));
u_common_fifo_sc : entity common_lib.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => false, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_use_lut => true, -- when TRUE then force using LUTs via Altera eab="OFF",
- g_dat_w => c_fifo_sop_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => fifo_sop_wr_dat,
- wr_req => fifo_sop_wr_req,
- wr_ful => fifo_sop_wr_ful,
- rd_dat => fifo_sop_rd_dat,
- rd_req => fifo_sop_rd_req,
- rd_emp => fifo_sop_rd_emp,
- rd_val => fifo_sop_rd_val,
- usedw => fifo_sop_usedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => false, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_use_lut => true, -- when TRUE then force using LUTs via Altera eab="OFF",
+ g_dat_w => c_fifo_sop_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => fifo_sop_wr_dat,
+ wr_req => fifo_sop_wr_req,
+ wr_ful => fifo_sop_wr_ful,
+ rd_dat => fifo_sop_rd_dat,
+ rd_req => fifo_sop_rd_req,
+ rd_emp => fifo_sop_rd_emp,
+ rd_val => fifo_sop_rd_val,
+ usedw => fifo_sop_usedw
+ );
-- Extract the sop data from the FIFO output SLV
info_src_out.sync <= rd_sync(0);
@@ -216,29 +216,29 @@ begin
-- concatenate the eop data to use a single FIFO
fifo_eop_wr_dat <= func_slv_concat(g_use_empty, g_use_error,
- info_snk_in.empty(g_empty_w - 1 downto 0),
- info_snk_in.err(g_error_w - 1 downto 0));
+ info_snk_in.empty(g_empty_w - 1 downto 0),
+ info_snk_in.err(g_error_w - 1 downto 0));
u_common_fifo_sc : entity common_lib.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => false, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_use_lut => true, -- when TRUE then force using LUTs via Altera eab="OFF",
- g_dat_w => c_fifo_eop_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => fifo_eop_wr_dat,
- wr_req => fifo_eop_wr_req,
- wr_ful => fifo_eop_wr_ful,
- rd_dat => fifo_eop_rd_dat,
- rd_req => fifo_eop_rd_req,
- rd_emp => fifo_eop_rd_emp,
- rd_val => fifo_eop_rd_val,
- usedw => fifo_eop_usedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => false, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_use_lut => true, -- when TRUE then force using LUTs via Altera eab="OFF",
+ g_dat_w => c_fifo_eop_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => fifo_eop_wr_dat,
+ wr_req => fifo_eop_wr_req,
+ wr_ful => fifo_eop_wr_ful,
+ rd_dat => fifo_eop_rd_dat,
+ rd_req => fifo_eop_rd_req,
+ rd_emp => fifo_eop_rd_emp,
+ rd_val => fifo_eop_rd_val,
+ usedw => fifo_eop_usedw
+ );
-- Extract the eop data from the FIFO output SLV
info_src_out.empty(g_empty_w - 1 downto 0) <= func_slv_extract(g_use_empty, g_use_error, g_empty_w, g_error_w, fifo_eop_rd_dat, 0);
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd b/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
index fd0011ecac..ce56ea6977 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
@@ -28,12 +28,12 @@
-- desired monitoring inputs and control outputs.
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_fifo_monitor is
port (
@@ -56,11 +56,12 @@ entity dp_fifo_monitor is
end dp_fifo_monitor;
architecture str of dp_fifo_monitor is
- constant c_field_arr : t_common_field_arr(4 downto 0) := ( (field_name_pad("rd_usedw"), "RO", 32, field_default(0) ),
- (field_name_pad("wr_usedw"), "RO", 32, field_default(0) ),
- (field_name_pad("rd_empty"), "RO", 1, field_default(0) ),
- (field_name_pad("wr_full" ), "RO", 1, field_default(0) ),
- (field_name_pad("rd_fill" ), "RW", 32, field_default(0) ));
+ constant c_field_arr : t_common_field_arr(
+ 4 downto 0) := ( (field_name_pad("rd_usedw"), "RO", 32, field_default(0) ),
+ (field_name_pad("wr_usedw"), "RO", 32, field_default(0) ),
+ (field_name_pad("rd_empty"), "RO", 1, field_default(0) ),
+ (field_name_pad("wr_full" ), "RO", 1, field_default(0) ),
+ (field_name_pad("rd_fill" ), "RW", 32, field_default(0) ));
signal mm_fields_in : std_logic_vector(field_slv_in_len(c_field_arr) - 1 downto 0);
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_field_arr) - 1 downto 0);
@@ -71,25 +72,25 @@ begin
mm_fields_in(field_hi(c_field_arr, "wr_full") downto field_lo(c_field_arr, "wr_full")) <= slv(wr_full);
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi,
- mm_miso => reg_miso,
+ mm_mosi => reg_mosi,
+ mm_miso => reg_miso,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_in => mm_fields_in,
- slv_in_val => '1',
+ slv_in => mm_fields_in,
+ slv_in_val => '1',
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
rd_fill_32b <= mm_fields_out(field_hi(c_field_arr, "rd_fill") downto field_lo(c_field_arr, "rd_fill"));
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
index 4ec10842d1..49ead3e746 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
@@ -27,12 +27,12 @@
-- . see dp_fifo_monitor.vhd
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_fifo_monitor_arr is
generic (
@@ -64,35 +64,35 @@ architecture str of dp_fifo_monitor_arr is
signal reg_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(c_nof_regs)
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(c_nof_regs)
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
gen_dp_fifo_monitor : for i in 0 to g_nof_streams - 1 generate
u_dp_fifo_monitor: entity work.dp_fifo_monitor
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_mosi_arr(i),
- reg_miso => reg_miso_arr(i),
+ reg_mosi => reg_mosi_arr(i),
+ reg_miso => reg_miso_arr(i),
- rd_usedw_32b => rd_usedw_32b_arr(i),
- wr_usedw_32b => wr_usedw_32b_arr(i),
- rd_emp => rd_emp_arr(i),
- wr_full => wr_full_arr(i),
- rd_fill_32b => rd_fill_32b_arr(i)
- );
+ rd_usedw_32b => rd_usedw_32b_arr(i),
+ wr_usedw_32b => wr_usedw_32b_arr(i),
+ rd_emp => rd_emp_arr(i),
+ wr_full => wr_full_arr(i),
+ rd_fill_32b => rd_fill_32b_arr(i)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
index 1ff22a1a71..1bfd4a083b 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
@@ -23,11 +23,11 @@
-- Description: See dp_fifo_core.vhd.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_sc is
generic (
@@ -71,44 +71,44 @@ end dp_fifo_sc;
architecture str of dp_fifo_sc is
begin
u_dp_fifo_core : entity work.dp_fifo_core
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_dual_clock => false,
- g_use_lut_sc => g_use_lut,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => g_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => rst,
- wr_clk => clk,
- rd_rst => rst,
- rd_clk => clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => OPEN,
- rd_usedw => usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_dual_clock => false,
+ g_use_lut_sc => g_use_lut,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => g_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => clk,
+ rd_rst => rst,
+ rd_clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => OPEN,
+ rd_usedw => usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
index 2c5adb850c..b27be03060 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
@@ -20,29 +20,29 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose:
--- Provide MM access to the ST output of a FIFO.
--- Description:
--- An MM master can directly read the FIFO, provided that the ST data width
--- fits within the MM data width (g_mm_word_w) and that both have the same
--- latency (read latency = ready latency = 1).
--- The MM master can read the mm_usedw[] value to know how many valid data
--- words it can read in a loop, until it needs to check mm_usedw[] again.
--- When mm_usedw[] > 0 then the MM master can be sure that the read
--- mm_rddata will be valid. Therefore it is not needed to pass on
--- snk_in.valid and in this way the MM master does not need to check whether
--- there is valid data in the FIFO for every read fifo data access.
--- Remark:
--- . Assume the FIFO will never go completely full, so usedw[] only needs to
--- fit values <= g_fifo_size-1
--- . This dp_fifo_to_mm connects to the MM clock domain side of the FIFO, hence
--- is operates entirely in the MM clock domain.
--- . The ST sop, eop, empty, channel and error fields are not supported.
+ -- Purpose:
+ -- Provide MM access to the ST output of a FIFO.
+ -- Description:
+ -- An MM master can directly read the FIFO, provided that the ST data width
+ -- fits within the MM data width (g_mm_word_w) and that both have the same
+ -- latency (read latency = ready latency = 1).
+ -- The MM master can read the mm_usedw[] value to know how many valid data
+ -- words it can read in a loop, until it needs to check mm_usedw[] again.
+ -- When mm_usedw[] > 0 then the MM master can be sure that the read
+ -- mm_rddata will be valid. Therefore it is not needed to pass on
+ -- snk_in.valid and in this way the MM master does not need to check whether
+ -- there is valid data in the FIFO for every read fifo data access.
+ -- Remark:
+ -- . Assume the FIFO will never go completely full, so usedw[] only needs to
+ -- fit values <= g_fifo_size-1
+ -- . This dp_fifo_to_mm connects to the MM clock domain side of the FIFO, hence
+ -- is operates entirely in the MM clock domain.
+ -- . The ST sop, eop, empty, channel and error fields are not supported.
entity dp_fifo_to_mm is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
index 364603eeae..ab07867666 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_fifo_to_mm_reg is
port (
@@ -37,15 +37,16 @@ entity dp_fifo_to_mm_reg is
-- MM registers
mm_rd_usedw : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end dp_fifo_to_mm_reg;
architecture rtl of dp_fifo_to_mm_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_flush.vhd b/libraries/base/dp/src/vhdl/dp_flush.vhd
index c800903a5b..043c1fa6f7 100644
--- a/libraries/base/dp/src/vhdl/dp_flush.vhd
+++ b/libraries/base/dp/src/vhdl/dp_flush.vhd
@@ -21,45 +21,45 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose: Flush snk_in when src_in will be not ready for a long time.
--- Description:
--- Provide a stream with an alternative sink when its normal end sink may
--- be not ready for such a long time that it affects the stream (e.g. fifo's
--- fill up too much, gaps occur). This component, when enabled, keeps the
--- input stream streaming by simply being always ready and discarding the
--- data (not forwarding the stream to its source output). When disabled, it
--- does not interfere with the stream in any way.
---
--- Four flush modes:
--- * Streaming mode (both g_framed_xon and g_framed_xoff are FALSE)
--- When flush_en goes low the output is disabled immediately, but when
--- flush_en goes high the output is enabled only after taking account of
--- the g_ready_latency to avoid that flushed data gets output as valid
--- data too early.
--- * Framed mode (both g_framed_xon and g_framed_xoff are TRUE)
--- When flush_en goes low then the output is disabled at the next
--- snk_in.sop, to ensure that an ongoing frame does not loose its tail.
--- When flush_en goes high then the output is enabled at the next
--- snk_in.sop to ensure that an ongoig frame is not passed on without its
--- head.
--- * Only g_framed_xon=TRUE
--- The output is disabled immediately, but enabled only at a snk_in.sop.
--- * Only g_framed_xoff=TRUE
--- The output is disabled at a snk_in.sop, but enabled based on the RL.
--- Remark:
--- . This dp_flush supports XON/XOFF control via MM flush_en as well as via the
--- downstream src_in.xon.
--- . The snk_out.xon is always '1' so the upsteam components can be always on,
--- because if necessary this component does flush
--- . If g_use_framed_channel = TRUE then the framed xon or xoff also requires
--- that the channel matches g_framed_channel. Otherwise the g_framed_channel
--- number is ignored and any sop will affect framed xon or xoff. Use the
--- actual needed width for g_framed_channel_w to ease timing closure.
+ -- Purpose: Flush snk_in when src_in will be not ready for a long time.
+ -- Description:
+ -- Provide a stream with an alternative sink when its normal end sink may
+ -- be not ready for such a long time that it affects the stream (e.g. fifo's
+ -- fill up too much, gaps occur). This component, when enabled, keeps the
+ -- input stream streaming by simply being always ready and discarding the
+ -- data (not forwarding the stream to its source output). When disabled, it
+ -- does not interfere with the stream in any way.
+ --
+ -- Four flush modes:
+ -- * Streaming mode (both g_framed_xon and g_framed_xoff are FALSE)
+ -- When flush_en goes low the output is disabled immediately, but when
+ -- flush_en goes high the output is enabled only after taking account of
+ -- the g_ready_latency to avoid that flushed data gets output as valid
+ -- data too early.
+ -- * Framed mode (both g_framed_xon and g_framed_xoff are TRUE)
+ -- When flush_en goes low then the output is disabled at the next
+ -- snk_in.sop, to ensure that an ongoing frame does not loose its tail.
+ -- When flush_en goes high then the output is enabled at the next
+ -- snk_in.sop to ensure that an ongoig frame is not passed on without its
+ -- head.
+ -- * Only g_framed_xon=TRUE
+ -- The output is disabled immediately, but enabled only at a snk_in.sop.
+ -- * Only g_framed_xoff=TRUE
+ -- The output is disabled at a snk_in.sop, but enabled based on the RL.
+ -- Remark:
+ -- . This dp_flush supports XON/XOFF control via MM flush_en as well as via the
+ -- downstream src_in.xon.
+ -- . The snk_out.xon is always '1' so the upsteam components can be always on,
+ -- because if necessary this component does flush
+ -- . If g_use_framed_channel = TRUE then the framed xon or xoff also requires
+ -- that the channel matches g_framed_channel. Otherwise the g_framed_channel
+ -- number is ignored and any sop will affect framed xon or xoff. Use the
+ -- actual needed width for g_framed_channel_w to ease timing closure.
entity dp_flush is
generic (
@@ -146,19 +146,19 @@ begin
end process;
u_src_en : entity common_lib.common_switch
- generic map (
- g_rst_level => '1',
- g_priority_lo => true,
- g_or_high => true,
- g_and_low => true
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => src_en_hi,
- switch_low => src_en_lo,
- out_level => src_en
- );
+ generic map (
+ g_rst_level => '1',
+ g_priority_lo => true,
+ g_or_high => true,
+ g_and_low => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => src_en_hi,
+ switch_low => src_en_lo,
+ out_level => src_en
+ );
p_snk_flush : process(snk_in, flush_dly)
variable v_hi : std_logic;
@@ -191,17 +191,17 @@ begin
end process;
u_snk_flush : entity common_lib.common_switch
- generic map (
- g_rst_level => '1',
- g_priority_lo => true, -- priority does not matter
- g_or_high => true,
- g_and_low => true
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => snk_flush_hi,
- switch_low => snk_flush_lo,
- out_level => snk_flush
- );
+ generic map (
+ g_rst_level => '1',
+ g_priority_lo => true, -- priority does not matter
+ g_or_high => true,
+ g_and_low => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => snk_flush_hi,
+ switch_low => snk_flush_lo,
+ out_level => snk_flush
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_folder.vhd b/libraries/base/dp/src/vhdl/dp_folder.vhd
index 7b49530966..f2335c5ed6 100644
--- a/libraries/base/dp/src/vhdl/dp_folder.vhd
+++ b/libraries/base/dp/src/vhdl/dp_folder.vhd
@@ -20,35 +20,35 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-
--- Status:
--- . Active (recommended for new designs)
--- Author:
--- . Daniel van der Schuur
--- Purpose:
--- . Fold n input streams into n/2, n/2/2, n/2/2/2, .. output streams
--- Description:
--- . This component assumes the user has scheduled the input streams properly.
--- . Input data that is to be folded onto one stream must not be valid at the same clock cycle
--- . nof_outputs = ceil_div(g_nof_inputs, 2^(g_nof_folds)) for g_nof_folds>=0
--- . Examples:
--- . g_nof_inputs=10, g_nof_folds=0 -> nof_outputs=10
--- . g_nof_inputs=10, g_nof_folds=1 -> nof_outputs= 5
--- . g_nof_inputs=10, g_nof_folds=2 -> nof_outputs= 3
--- . g_nof_inputs=10, g_nof_folds=3 -> nof_outputs= 2
--- . g_nof_inputs=10, g_nof_folds=4 -> nof_outputs= 1
--- . g_nof_inputs=10, g_nof_folds<0 -> nof_outputs= 1
--- . This entity recursively instantiates (registered) stages of itself when folding streams multiple times.
---
--- Remark:
--- . Use dp_deinterleave_n_to_one.vhd when:
--- - for 1 to N, so any N >= 1 (so not only powers of 2)
--- - when all sosi fields need to be preserved (so not only the valid)
--- - if flow control is needed
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+
+ -- Status:
+ -- . Active (recommended for new designs)
+ -- Author:
+ -- . Daniel van der Schuur
+ -- Purpose:
+ -- . Fold n input streams into n/2, n/2/2, n/2/2/2, .. output streams
+ -- Description:
+ -- . This component assumes the user has scheduled the input streams properly.
+ -- . Input data that is to be folded onto one stream must not be valid at the same clock cycle
+ -- . nof_outputs = ceil_div(g_nof_inputs, 2^(g_nof_folds)) for g_nof_folds>=0
+ -- . Examples:
+ -- . g_nof_inputs=10, g_nof_folds=0 -> nof_outputs=10
+ -- . g_nof_inputs=10, g_nof_folds=1 -> nof_outputs= 5
+ -- . g_nof_inputs=10, g_nof_folds=2 -> nof_outputs= 3
+ -- . g_nof_inputs=10, g_nof_folds=3 -> nof_outputs= 2
+ -- . g_nof_inputs=10, g_nof_folds=4 -> nof_outputs= 1
+ -- . g_nof_inputs=10, g_nof_folds<0 -> nof_outputs= 1
+ -- . This entity recursively instantiates (registered) stages of itself when folding streams multiple times.
+ --
+ -- Remark:
+ -- . Use dp_deinterleave_n_to_one.vhd when:
+ -- - for 1 to N, so any N >= 1 (so not only powers of 2)
+ -- - when all sosi fields need to be preserved (so not only the valid)
+ -- - if flow control is needed
entity dp_folder is
generic (
@@ -191,20 +191,20 @@ begin
gen_ctrl : if g_output_block_size > 0 generate
gen_dp_block_gen : for i in 0 to c_nof_muxes - 1 generate
u_dp_block_gen : entity work.dp_block_gen
- generic map (
- g_use_src_in => false,
- g_nof_data => g_output_block_size,
- g_preserve_sync => true,
- g_preserve_bsn => true,
- g_preserve_channel => g_use_channel
- )
- port map(
- rst => rst,
- clk => clk,
-
- snk_in => dp_block_gen_snk_in_arr(i),
- src_out => dp_block_gen_src_out_arr(i)
- );
+ generic map (
+ g_use_src_in => false,
+ g_nof_data => g_output_block_size,
+ g_preserve_sync => true,
+ g_preserve_bsn => true,
+ g_preserve_channel => g_use_channel
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ snk_in => dp_block_gen_snk_in_arr(i),
+ src_out => dp_block_gen_src_out_arr(i)
+ );
end generate;
end generate;
@@ -218,20 +218,20 @@ begin
gen_sync_bsn : if g_fwd_sync_bsn = true generate
gen_dp_fifo_info: for i in 0 to c_nof_muxes - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
- generic map (
- g_use_sync => true,
- g_use_bsn => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in_arr(0), -- original snk_in info
-
- src_in => c_dp_siso_rdy,
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_use_sync => true,
+ g_use_bsn => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
+ info_snk_in => snk_in_arr(0), -- original snk_in info
+
+ src_in => c_dp_siso_rdy,
+ src_out => src_out_arr(i)
+ );
end generate;
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd b/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
index 7de5defbca..df591c619d 100644
--- a/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
+++ b/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
@@ -61,10 +61,10 @@
-- then the force_data is void.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_force_data_parallel is
generic (
@@ -100,8 +100,8 @@ entity dp_force_data_parallel is
end dp_force_data_parallel;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture str of dp_force_data_parallel is
signal data_in : t_dp_sosi;
@@ -146,19 +146,19 @@ begin
end process;
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => data_in,
- -- ST source
- src_in => src_in,
- src_out => data_out
- );
+ generic map (
+ g_pipeline => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => data_in,
+ -- ST source
+ src_in => src_in,
+ src_out => data_out
+ );
src_out <= data_out;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd b/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
index 85b4568abd..491dcdc0ac 100644
--- a/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
+++ b/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
@@ -76,10 +76,10 @@
-- then the force_data is void.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_force_data_serial is
generic (
@@ -123,18 +123,18 @@ begin
force_zero <= not force_zero_n;
u_common_counter : entity common_lib.common_counter
- generic map (
- g_latency => 0, -- default 1 for registered count output, use 0 for immediate combinatorial count output
- g_width => c_cnt_w,
- g_max => g_index_period
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_latency => 0, -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ g_width => c_cnt_w,
+ g_max => g_index_period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
p_comb : process(snk_in, cnt, force_en, force_index, force_value, force_zero, force_data, force_re, force_im)
begin
@@ -161,17 +161,17 @@ begin
end process;
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => data_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => data_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame.vhd b/libraries/base/dp/src/vhdl/dp_frame.vhd
index c60355be35..37efbd926e 100644
--- a/libraries/base/dp/src/vhdl/dp_frame.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame.vhd
@@ -20,43 +20,43 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_packetizing_pkg.all;
-
--- Reuse from LOFAR rad_frame.vhd and rad_frame(rtl).vhd
-
--- Purpose:
--- Puts the input data path signals:
--- . val
--- . dat[]
--- . sof
--- . eof
--- . fsn[]
--- into the internal data path (dp) frame data format:
---
--- -----------------------
--- | fsn | dat ... | brc |
--- -----------------------
--- sof eof
--- val val ... val
---
--- To make an external frame with sfd and crc instead of brc use dp_frame_tx.
---
--- Description:
--- The input sof and eof mark the first respectively the last valid word of a
--- block of input data. The output sof indicates the fsn word. After that
--- follows the block of input data. At the end a brc is appended indicated by
--- the output eof. If necessary invalid data is inserted between frames.
--- The brc is a boolean redundancy check and will be 0 indicating OK when
--- in_err='0', else 1. The in_err is valid during the active in_eof. The brc
--- can act as a place holder for a true crc to be inserted when the frame
--- is sent outside the FPGA using dp_frame_tx and dp_frame_rx. Alternatively
--- the brc can be kept in the dp frame in addition to a PHY level CRC.
--- The width of the fsn and brc is set by the dat width. The fsn is sign
--- extended to g_dat_w, in this way all bits g_dat_w:g_fsn_w-1 indicate
--- fsync, so a signed resize suits for every g_dat_w >= g_fsn_w.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_packetizing_pkg.all;
+
+ -- Reuse from LOFAR rad_frame.vhd and rad_frame(rtl).vhd
+
+ -- Purpose:
+ -- Puts the input data path signals:
+ -- . val
+ -- . dat[]
+ -- . sof
+ -- . eof
+ -- . fsn[]
+ -- into the internal data path (dp) frame data format:
+ --
+ -- -----------------------
+ -- | fsn | dat ... | brc |
+ -- -----------------------
+ -- sof eof
+ -- val val ... val
+ --
+ -- To make an external frame with sfd and crc instead of brc use dp_frame_tx.
+ --
+ -- Description:
+ -- The input sof and eof mark the first respectively the last valid word of a
+ -- block of input data. The output sof indicates the fsn word. After that
+ -- follows the block of input data. At the end a brc is appended indicated by
+ -- the output eof. If necessary invalid data is inserted between frames.
+ -- The brc is a boolean redundancy check and will be 0 indicating OK when
+ -- in_err='0', else 1. The in_err is valid during the active in_eof. The brc
+ -- can act as a place holder for a true crc to be inserted when the frame
+ -- is sent outside the FPGA using dp_frame_tx and dp_frame_rx. Alternatively
+ -- the brc can be kept in the dp frame in addition to a PHY level CRC.
+ -- The width of the fsn and brc is set by the dat width. The fsn is sign
+ -- extended to g_dat_w, in this way all bits g_dat_w:g_fsn_w-1 indicate
+ -- fsync, so a signed resize suits for every g_dat_w >= g_fsn_w.
entity dp_frame is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_frame_busy.vhd b/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
index 96e79e56f2..7acd3af0bb 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
@@ -27,9 +27,9 @@
-- Use g_pipeline > 0 to register snk_in_busy to ease timing closure.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_frame_busy is
generic (
@@ -47,30 +47,30 @@ architecture str of dp_frame_busy is
signal busy : std_logic;
begin
u_common_switch : entity common_lib.common_switch
- generic map (
- g_rst_level => '0', -- Defines the output level at reset.
- g_priority_lo => true, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
- g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
- g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => snk_in.sop, -- A pulse on switch_high makes the out_level go high
- switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
- out_level => busy
- );
+ generic map (
+ g_rst_level => '0', -- Defines the output level at reset.
+ g_priority_lo => true, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
+ g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
+ g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => snk_in.sop, -- A pulse on switch_high makes the out_level go high
+ switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
+ out_level => busy
+ );
u_common_pipeline_sl : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline, -- 0 for wires, > 0 for registers,
- g_reset_value => 0, -- 0 or 1, bit reset value,
- g_out_invert => false
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => busy,
- out_dat => snk_in_busy
- );
+ generic map (
+ g_pipeline => g_pipeline, -- 0 for wires, > 0 for registers,
+ g_reset_value => 0, -- 0 or 1, bit reset value,
+ g_out_invert => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => busy,
+ out_dat => snk_in_busy
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd b/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd
index 8b2e689ec4..bc14eb4bb6 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd
@@ -24,8 +24,8 @@
-- See dp_frame_busy.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
entity dp_frame_busy_arr is
generic (
@@ -44,15 +44,15 @@ architecture str of dp_frame_busy_arr is
begin
gen_nof_inputs : for I in 0 to g_nof_inputs - 1 generate
u_dp_frame_busy : entity work.dp_frame_busy
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- snk_in => snk_in_arr(I),
- snk_in_busy => snk_in_busy_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_in => snk_in_arr(I),
+ snk_in_busy => snk_in_busy_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd b/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
index 76ab9717de..ef48d04103 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
@@ -20,54 +20,54 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-
--- Reuse from LOFAR rad_frame_hdr.vhd and rad_frame_hdr(rtl).vhd
-
--- Purpose:
--- Determine start and end of data blocks and introduce the data path (dp)
--- frame sequence number (fsn) with sync and sequence number information.
--- Description:
--- The input data are the data path signals:
--- . sync
--- . val
--- . dat[]
--- The output data are the data paths signals:
--- . val
--- . dat[]
--- . sof
--- . eof
--- . fsn[]
--- The blocks have size g_block_size. There must be gaps between data blocks
--- to allow space for dp_frame and dp_frame_tx which insert >= 1 idle, sfd,
--- fsn and brc/crc into the stream. Therefore in_val must go low for at
--- least 4 cycles between data blocks. The sof marks the start of block and
--- the eof marks the end of the data block.
--- For the first block after a sync the msbit of the fsn is '1' and the frame
--- sequence number is forced to restart at 0. The fsn increments for the
--- subsequent data blocks. The fsn may wrap several times during a sync
--- interval. The fsn word is valid at the sof and during the frame. The new
--- fsn becomes valid directly after the eof or after an in_sync, that
--- restarts the fsn. The in_sync may be high for an entire data block. The
--- falling edge of in_sync is used internally and therefor the first cycle
--- after the last active in_sync must have in_val low (i.e. fall in the gap
--- between data blocks).
--- If g_use_sync is FALSE then the periodic in_sync is not used and the
--- function starts packetizing the data at the first valid input and will
--- remain in state s_data forever.
--- The function verifies that subsequent in_sync occur on a block boundary,
--- if not then the output flushes the rest of the block and then disables and
--- tries to recover at the next in_sync. In practise such an block error can
--- not occur, because the input signals come from internal circuitry in the
--- FPGA so if that goes wrong, then the entire FPGA logic state is undefined.
--- If the input data can be reset independent of this function then a
--- fractional data block can occur, so then the flush capability becomes
--- useful. Furthermore flush capability ensures that only full blocks are
--- output or nothing, similar as for dp_frame_rx. The error is output via
--- out_err which is valid in the cycle directly after out_eof. The g_fsn_w
--- must be <= g_dat_w.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+
+ -- Reuse from LOFAR rad_frame_hdr.vhd and rad_frame_hdr(rtl).vhd
+
+ -- Purpose:
+ -- Determine start and end of data blocks and introduce the data path (dp)
+ -- frame sequence number (fsn) with sync and sequence number information.
+ -- Description:
+ -- The input data are the data path signals:
+ -- . sync
+ -- . val
+ -- . dat[]
+ -- The output data are the data paths signals:
+ -- . val
+ -- . dat[]
+ -- . sof
+ -- . eof
+ -- . fsn[]
+ -- The blocks have size g_block_size. There must be gaps between data blocks
+ -- to allow space for dp_frame and dp_frame_tx which insert >= 1 idle, sfd,
+ -- fsn and brc/crc into the stream. Therefore in_val must go low for at
+ -- least 4 cycles between data blocks. The sof marks the start of block and
+ -- the eof marks the end of the data block.
+ -- For the first block after a sync the msbit of the fsn is '1' and the frame
+ -- sequence number is forced to restart at 0. The fsn increments for the
+ -- subsequent data blocks. The fsn may wrap several times during a sync
+ -- interval. The fsn word is valid at the sof and during the frame. The new
+ -- fsn becomes valid directly after the eof or after an in_sync, that
+ -- restarts the fsn. The in_sync may be high for an entire data block. The
+ -- falling edge of in_sync is used internally and therefor the first cycle
+ -- after the last active in_sync must have in_val low (i.e. fall in the gap
+ -- between data blocks).
+ -- If g_use_sync is FALSE then the periodic in_sync is not used and the
+ -- function starts packetizing the data at the first valid input and will
+ -- remain in state s_data forever.
+ -- The function verifies that subsequent in_sync occur on a block boundary,
+ -- if not then the output flushes the rest of the block and then disables and
+ -- tries to recover at the next in_sync. In practise such an block error can
+ -- not occur, because the input signals come from internal circuitry in the
+ -- FPGA so if that goes wrong, then the entire FPGA logic state is undefined.
+ -- If the input data can be reset independent of this function then a
+ -- fractional data block can occur, so then the flush capability becomes
+ -- useful. Furthermore flush capability ensures that only full blocks are
+ -- output or nothing, similar as for dp_frame_rx. The error is output via
+ -- out_err which is valid in the cycle directly after out_eof. The g_fsn_w
+ -- must be <= g_dat_w.
entity dp_frame_fsn is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_frame_rd.vhd b/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
index 0a1b077acf..70196f3915 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
@@ -23,42 +23,42 @@
-- Reuse from LOFAR rad_rdframe.vhd and rad_rdframe(rtl).vhd
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
--- Purpose:
--- Read or flush one frame from a FIFO.
--- Description:
--- The frame in the FIFO must be marked by sof and eof. If frm_req is high
--- then a new frame will be read form the FIFO and the frm_ack output gives
--- a pulse to indicate that frm_req can be released. A subsequent frm_req
--- will be acknowledged after the current frame has been read.
--- If frm_flush is high at frm_req then the frame will be read, but the output
--- val, sof, and eof remain low. When the frame has been read then the
--- frm_done output gives a pulse.
--- If the FIFO is empty then frm_ack output gives a pulse but then frm_busy
--- remains low.
--- With g_throttle_num / g_throttle_den the read output rate is set,
--- g_throttle_den=1 yields full speed.
--- A frame that does not start with a sof gets flushed too and is reported
--- via output frm_err. Typically output frm_err can be left OPEN.
--- Remarks:
--- . This sink ready latency = 1, applies to rd_req and rd_val
--- . This source ready latency is not used, because there is no out_req.
--- Hence this source assumes the downstream sink is always ready and pushes
--- a frame of throttled data out after a frm_req.
--- . To make use of frm_cnt connect frm_req to the eop of the FIFO input,
--- because then there is a frame pending in the FIFO. If frm_req='1' always
--- then frm_cnt is void.
--- . If the FIFO runs empty while reading a frame, then the throttling will
--- not output data when it can. To avoid this e.g. connect eof to frm_req.
--- . If the FIFO contains more than 2 frames then more frm_req requests are
--- needed to to read them all out. This is facilitated by frm_cnt>0.
--- If running the FIFO empty is no issue, then keeping frm_req high is also
--- suitable.
--- . Throttling after sof may not be needed if the sof data contains e.g. a
--- frame sequence number (then use g_throttle_eof=FALSE).
--- . The output throttle after the eof to avoid a new sof to follow the
--- previous eof too soon may not be needed (then use g_throttle_eof=FALSE).
+ -- Purpose:
+ -- Read or flush one frame from a FIFO.
+ -- Description:
+ -- The frame in the FIFO must be marked by sof and eof. If frm_req is high
+ -- then a new frame will be read form the FIFO and the frm_ack output gives
+ -- a pulse to indicate that frm_req can be released. A subsequent frm_req
+ -- will be acknowledged after the current frame has been read.
+ -- If frm_flush is high at frm_req then the frame will be read, but the output
+ -- val, sof, and eof remain low. When the frame has been read then the
+ -- frm_done output gives a pulse.
+ -- If the FIFO is empty then frm_ack output gives a pulse but then frm_busy
+ -- remains low.
+ -- With g_throttle_num / g_throttle_den the read output rate is set,
+ -- g_throttle_den=1 yields full speed.
+ -- A frame that does not start with a sof gets flushed too and is reported
+ -- via output frm_err. Typically output frm_err can be left OPEN.
+ -- Remarks:
+ -- . This sink ready latency = 1, applies to rd_req and rd_val
+ -- . This source ready latency is not used, because there is no out_req.
+ -- Hence this source assumes the downstream sink is always ready and pushes
+ -- a frame of throttled data out after a frm_req.
+ -- . To make use of frm_cnt connect frm_req to the eop of the FIFO input,
+ -- because then there is a frame pending in the FIFO. If frm_req='1' always
+ -- then frm_cnt is void.
+ -- . If the FIFO runs empty while reading a frame, then the throttling will
+ -- not output data when it can. To avoid this e.g. connect eof to frm_req.
+ -- . If the FIFO contains more than 2 frames then more frm_req requests are
+ -- needed to to read them all out. This is facilitated by frm_cnt>0.
+ -- If running the FIFO empty is no issue, then keeping frm_req high is also
+ -- suitable.
+ -- . Throttling after sof may not be needed if the sof data contains e.g. a
+ -- frame sequence number (then use g_throttle_eof=FALSE).
+ -- . The output throttle after the eof to avoid a new sof to follow the
+ -- previous eof too soon may not be needed (then use g_throttle_eof=FALSE).
entity dp_frame_rd is
generic (
@@ -212,7 +212,7 @@ begin
end process;
next_out_throttle <= nxt_out_throttle; -- note next_out_throttle high in is same cycle as out_throttle when g_throttle_den=1
- -- else next_out_throttle is high one cycle before out_throttle when g_throttle_den>1
+ -- else next_out_throttle is high one cycle before out_throttle when g_throttle_den>1
p_frm_cnt : process(frm_cnt, frm_req, nxt_frm_done)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_frame_remove.vhd b/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
index 41dbe3e5e8..f5f51d390c 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_frame_remove is
generic (
@@ -63,60 +63,60 @@ architecture str of dp_frame_remove is
begin
no_bypass : if g_internal_bypass = false generate
u_dp_latency_adpapter: entity work.dp_latency_adapter
- generic map (
- g_in_latency => g_snk_latency,
- g_out_latency => 1
- )
- port map (
- rst => st_rst,
- clk => st_clk,
+ generic map (
+ g_in_latency => g_snk_latency,
+ g_out_latency => 1
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
- snk_out => snk_out,
- snk_in => snk_in,
+ snk_out => snk_out,
+ snk_in => snk_in,
- src_out => snk_in_rl_1,
- src_in => snk_out_rl_1
- );
+ src_out => snk_in_rl_1,
+ src_in => snk_out_rl_1
+ );
u_dp_hdr_remove : entity work.dp_hdr_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_hdr_nof_words => g_hdr_nof_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_hdr_nof_words => g_hdr_nof_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- snk_out => snk_out_rl_1,
- snk_in => snk_in_rl_1,
+ snk_out => snk_out_rl_1,
+ snk_in => snk_in_rl_1,
- sla_in => sla_in,
- sla_out => sla_out,
+ sla_in => sla_in,
+ sla_out => sla_out,
- src_in => hdr_rem_siso,
- src_out => hdr_rem_sosi
- );
+ src_in => hdr_rem_siso,
+ src_out => hdr_rem_sosi
+ );
u_dp_tail_remove : entity work.dp_tail_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => c_tail_nof_symbols
- )
- port map (
- st_rst => st_rst,
- st_clk => st_clk,
-
- snk_out => hdr_rem_siso,
- snk_in => hdr_rem_sosi,
-
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => c_tail_nof_symbols
+ )
+ port map (
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ snk_out => hdr_rem_siso,
+ snk_in => hdr_rem_sosi,
+
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
gen_bypass : if g_internal_bypass = true generate
diff --git a/libraries/base/dp/src/vhdl/dp_frame_repack.vhd b/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
index 7bda823b12..bcfb3ab91b 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
@@ -22,8 +22,8 @@
-- Reuse from LOFAR rad_frame_repack.vhd and rad_frame_repack(rtl).vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity dp_frame_repack is
generic (
@@ -62,7 +62,7 @@ architecture str of dp_frame_repack is
begin
no_pack : if g_in_nof_words = g_out_nof_words generate
out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack at the other end,
- -- typically g_out_dat_w=g_in_dat_w
+ -- typically g_out_dat_w=g_in_dat_w
out_val <= in_val;
out_sof <= in_sof;
out_eof <= in_eof;
@@ -70,67 +70,67 @@ begin
gen_pack : if g_in_nof_words /= g_out_nof_words generate
unframe : entity work.dp_unframe
- generic map (
- g_dat_w => g_in_dat_w,
- g_fsn_w => g_in_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_dat,
- in_val => in_val,
- in_sof => in_sof,
- in_eof => in_eof,
- out_fsn => pack_fsn,
- out_sync => OPEN,
- out_dat => pack_dat,
- out_val => pack_val,
- out_sof => pack_sof,
- out_eof => pack_eof,
- out_err => pack_err
- );
+ generic map (
+ g_dat_w => g_in_dat_w,
+ g_fsn_w => g_in_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_dat,
+ in_val => in_val,
+ in_sof => in_sof,
+ in_eof => in_eof,
+ out_fsn => pack_fsn,
+ out_sync => OPEN,
+ out_dat => pack_dat,
+ out_val => pack_val,
+ out_sof => pack_sof,
+ out_eof => pack_eof,
+ out_err => pack_err
+ );
repack : entity work.dp_repack_legacy
- generic map (
- g_in_dat_w => g_in_dat_w,
- g_in_nof_words => g_in_nof_words,
- g_out_dat_w => g_out_dat_w,
- g_out_nof_words => g_out_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => pack_dat,
- in_val => pack_val,
- in_sof => pack_sof,
- in_eof => pack_eof,
- out_dat => repack_dat,
- out_val => repack_val,
- out_sof => repack_sof,
- out_eof => repack_eof
- );
+ generic map (
+ g_in_dat_w => g_in_dat_w,
+ g_in_nof_words => g_in_nof_words,
+ g_out_dat_w => g_out_dat_w,
+ g_out_nof_words => g_out_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => pack_dat,
+ in_val => pack_val,
+ in_sof => pack_sof,
+ in_eof => pack_eof,
+ out_dat => repack_dat,
+ out_val => repack_val,
+ out_sof => repack_sof,
+ out_eof => repack_eof
+ );
repack_fsn <= RESIZE_SVEC(pack_fsn,repack_fsn'length); -- pack_fsn remains valid
frame : entity work.dp_frame
- generic map (
- g_dat_w => g_out_dat_w,
- g_fsn_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_fsn => repack_fsn,
- in_dat => repack_dat,
- in_val => repack_val,
- in_sof => repack_sof,
- in_eof => repack_eof,
- in_err => pack_err, -- pack_err remains valid
- out_dat => out_dat,
- out_val => out_val,
- out_sof => out_sof,
- out_eof => out_eof
- );
+ generic map (
+ g_dat_w => g_out_dat_w,
+ g_fsn_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_fsn => repack_fsn,
+ in_dat => repack_dat,
+ in_val => repack_val,
+ in_sof => repack_sof,
+ in_eof => repack_eof,
+ in_err => pack_err, -- pack_err remains valid
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sof => out_sof,
+ out_eof => out_eof
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_rx.vhd b/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
index 6a5304e97b..1f5b58fac9 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
@@ -20,61 +20,61 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_packetizing_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_packetizing_pkg.all;
--- Reuse from LOFAR rad_frame_rx.vhd and rad_frame_rx(rtl).vhd
+ -- Reuse from LOFAR rad_frame_rx.vhd and rad_frame_rx(rtl).vhd
--- Purpose:
--- From the input dp frame PHY stream:
---
--- -----------------------------
--- idle | sfd | fsn | dat ... | crc | idle ...
--- -----------------------------
---
--- detect and output the dp frames for g_sfd:
---
--- -----------------------
--- | fsn | dat ... | brc |
--- -----------------------
--- sof eof
--- val val ... val
---
--- Mark the sof and eof of each frame and check the received CRC
--- Description:
--- A dp PHY frame consists of g_sfd, fsn, data and crc. The dp PHY frames
--- are seperated by at least one c_dp_idle word. The received crc is passed
--- on as boolean crc called bcr, where '0' indicates OK and '1' indicates
--- that an crc error.
--- The sof is detected based on a c_dp_idle to g_sfd word transition and the
--- eof is then determined by counting g_block_size data words. The g_sfd word
--- is not passed on, because we have the sof signal. Therefore the internal
--- frame consists of fsn, dat, bcr fields and seperate sof and eof signals.
--- The sof signal is active during the fsn and the eof is active during the
--- brc.
--- While counting valid data words the module is insensitive to c_dp_idle/
--- g_sfd. Hence the output is always a full frame, if for some reason the
--- input framing got corrupted, then this will reflect in the crc so the brc
--- will note error. Perhaps even a frame may get lost, but the frame
--- reception will recover on a next sof detection. Idle words between
--- internal frames are simply passed on, which is fine since out_val is
--- inactive.
--- Remark:
--- . Frame output is flow controlled on frame level only, by the out_xon input.
--- . Typically choose the rx timeout g_timeout_w=0 if a link is fixed after
--- power up (e.g. for RSP RI). If the link can stop and start asynchronously
--- (e.g. changing cables, transmitter restart) then choose g_timeout_w
--- sufficient to fit the frame period (e.g. for RSP Serdes).
--- . In p_state the rx timeout restart after every active in_val_reg, this in
--- principle allows using a smaller timeout that is sufficient to span the
--- inactive gaps of in_val_reg, so then g_timeout_w <= c_rsp_slice_size is
--- suficient. An alternative implementation for the timeout would be to let
--- the timeout run from the sop, the timeout must then at least span the
--- frame period. The frame period can vary a somewhat due to mutliplexing
--- so with c_rsp_slice_size the g_timeout_w would then have to be set to
--- c_rsp_slice_size+1
+ -- Purpose:
+ -- From the input dp frame PHY stream:
+ --
+ -- -----------------------------
+ -- idle | sfd | fsn | dat ... | crc | idle ...
+ -- -----------------------------
+ --
+ -- detect and output the dp frames for g_sfd:
+ --
+ -- -----------------------
+ -- | fsn | dat ... | brc |
+ -- -----------------------
+ -- sof eof
+ -- val val ... val
+ --
+ -- Mark the sof and eof of each frame and check the received CRC
+ -- Description:
+ -- A dp PHY frame consists of g_sfd, fsn, data and crc. The dp PHY frames
+ -- are seperated by at least one c_dp_idle word. The received crc is passed
+ -- on as boolean crc called bcr, where '0' indicates OK and '1' indicates
+ -- that an crc error.
+ -- The sof is detected based on a c_dp_idle to g_sfd word transition and the
+ -- eof is then determined by counting g_block_size data words. The g_sfd word
+ -- is not passed on, because we have the sof signal. Therefore the internal
+ -- frame consists of fsn, dat, bcr fields and seperate sof and eof signals.
+ -- The sof signal is active during the fsn and the eof is active during the
+ -- brc.
+ -- While counting valid data words the module is insensitive to c_dp_idle/
+ -- g_sfd. Hence the output is always a full frame, if for some reason the
+ -- input framing got corrupted, then this will reflect in the crc so the brc
+ -- will note error. Perhaps even a frame may get lost, but the frame
+ -- reception will recover on a next sof detection. Idle words between
+ -- internal frames are simply passed on, which is fine since out_val is
+ -- inactive.
+ -- Remark:
+ -- . Frame output is flow controlled on frame level only, by the out_xon input.
+ -- . Typically choose the rx timeout g_timeout_w=0 if a link is fixed after
+ -- power up (e.g. for RSP RI). If the link can stop and start asynchronously
+ -- (e.g. changing cables, transmitter restart) then choose g_timeout_w
+ -- sufficient to fit the frame period (e.g. for RSP Serdes).
+ -- . In p_state the rx timeout restart after every active in_val_reg, this in
+ -- principle allows using a smaller timeout that is sufficient to span the
+ -- inactive gaps of in_val_reg, so then g_timeout_w <= c_rsp_slice_size is
+ -- suficient. An alternative implementation for the timeout would be to let
+ -- the timeout run from the sop, the timeout must then at least span the
+ -- frame period. The frame period can vary a somewhat due to mutliplexing
+ -- so with c_rsp_slice_size the g_timeout_w would then have to be set to
+ -- c_rsp_slice_size+1
entity dp_frame_rx is
generic (
@@ -140,10 +140,11 @@ architecture rtl of dp_frame_rx is
signal nxt_flush_en : std_logic;
signal flush_val : std_logic;
- procedure proc_handle_rx_timeout(signal valid : in std_logic;
- signal timeout_evt : in std_logic;
- signal clr : out std_logic;
- variable v_state : inout t_state) is -- use variable v_state instead of signal to avoid getting latches
+ procedure proc_handle_rx_timeout(
+ signal valid : in std_logic;
+ signal timeout_evt : in std_logic;
+ signal clr : out std_logic;
+ variable v_state : inout t_state) is -- use variable v_state instead of signal to avoid getting latches
begin
if valid = '1' then
clr <= '1'; -- restart timeout_cnt during frame rx and remain in current state
@@ -212,15 +213,15 @@ begin
gen_timeout : if g_timeout_w > 0 generate
u_timeout_cnt : entity common_lib.common_counter
- generic map (
- g_width => c_timeout_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => timeout_cnt_clr,
- count => timeout_cnt
- );
+ generic map (
+ g_width => c_timeout_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => timeout_cnt_clr,
+ count => timeout_cnt
+ );
timeout_evt <= timeout_cnt(g_timeout_w); -- check MSbit for timeout of 2**g_timeout_w clk cycles
diff --git a/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
index 6d587242c7..14b93d400f 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
@@ -41,11 +41,11 @@
-- they are written into the input FIFO.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_frame_scheduler is
generic (
@@ -158,16 +158,16 @@ begin
wr_siso(I).xon <= not in_dis(I);
u_xonoff : entity work.dp_xonoff
- port map (
- rst => rst,
- clk => clk,
- -- Frame in
- in_siso => OPEN,
- in_sosi => snk_in(I),
- -- Frame out
- out_siso => wr_siso(I), -- flush control via xon, ready is not used and only passed on
- out_sosi => wr_sosi(I)
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Frame in
+ in_siso => OPEN,
+ in_sosi => snk_in(I),
+ -- Frame out
+ out_siso => wr_siso(I), -- flush control via xon, ready is not used and only passed on
+ out_sosi => wr_sosi(I)
+ );
-- Input FIFO
rd_siso(I).ready <= rd_req(I);
@@ -178,31 +178,31 @@ begin
rd_eof(I) <= rd_sosi(I).eop;
u_fill : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_data_w => g_dat_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_fifo_fill => c_fifo_fill(I),
- g_fifo_size => c_fifo_size(I),
- g_fifo_rl => g_fifo_rl
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN, -- OUT = request to upstream ST source
- snk_in => wr_sosi(I),
- -- ST source
- src_in => rd_siso(I), -- IN = request from downstream ST sink
- src_out => rd_sosi(I),
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_dat_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_fifo_fill => c_fifo_fill(I),
+ g_fifo_size => c_fifo_size(I),
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN, -- OUT = request to upstream ST source
+ snk_in => wr_sosi(I),
+ -- ST source
+ src_in => rd_siso(I), -- IN = request from downstream ST sink
+ src_out => rd_sosi(I),
- wr_ful => gp_out(I)
- );
+ wr_ful => gp_out(I)
+ );
end generate;
-- Output select
diff --git a/libraries/base/dp/src/vhdl/dp_frame_status.vhd b/libraries/base/dp/src/vhdl/dp_frame_status.vhd
index abff3ccbce..240ea9487d 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_status.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_status.vhd
@@ -30,9 +30,9 @@
-- status applies to the interval before the previous sync interval, due to the data processing latency.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity dp_frame_status is
generic (
@@ -126,33 +126,33 @@ begin
-- frame sync detection
u_fsync_det : entity common_lib.common_switch
- port map (
- clk => clk,
- rst => rst,
- switch_high => fsync, -- frame sync
- switch_low => sync_dly, -- system sync
- out_level => fsync_det
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => fsync, -- frame sync
+ switch_low => sync_dly, -- system sync
+ out_level => fsync_det
+ );
-- any frame brc over fsync interval
u_brc_det : entity common_lib.common_switch
- port map (
- clk => clk,
- rst => rst,
- switch_high => brc, -- frame brc
- switch_low => fsync, -- frame sync
- out_level => brc_det
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => brc, -- frame brc
+ switch_low => fsync, -- frame sync
+ out_level => brc_det
+ );
-- any frame discarded over fsync interval
u_dis_det : entity common_lib.common_switch
- port map (
- clk => clk,
- rst => rst,
- switch_high => in_dis, -- frame discarded
- switch_low => fsync, -- frame sync
- out_level => dis_det
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => in_dis, -- frame discarded
+ switch_low => fsync, -- frame sync
+ out_level => dis_det
+ );
-- frame count over fsync interval
p_frame_cnt : process(cnt, fsync, in_eof)
@@ -164,4 +164,4 @@ begin
nxt_cnt <= std_logic_vector(unsigned(cnt) + 1);
end if;
end process;
-end architecture;
+ end architecture;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_tx.vhd b/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
index 01dbbf256a..5a611b3d9f 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
@@ -20,48 +20,48 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_packetizing_pkg.all;
-
--- Reuse from LOFAR rad_frame_tx.vhd and rad_frame_tx(rtl).vhd
-
--- Purpose:
--- Pass on the input data path frame:
---
--- -----------------------
--- | fsn | dat ... | brc |
--- -----------------------
--- sof eof
--- val val ... val
---
--- into an output data path PHY frame:
---
--- ----------------------------------
--- idle |idle| sfd | fsn | dat ... | crc | idle ...
--- ----------------------------------
--- sof eof
--- val val val val ... val
---
--- Description:
--- An input internal frame consists of fsn, data and brc. The in_sof marks
--- fsn and the in_eof marks the brc. When in_val is '0' then c_dp_idle data
--- is output.
--- The dp PHY output frame suits point it point links only. A valid CRC is
--- inserted when the brc is OK else insert NOT crc to propagate the brc error
--- at dp PHY level. For dat'LENGTH < c_dp_crc_w the transmitted crc word gets
--- extended. For dat'LENGTH > c_dp_crc_w the transmitted crc word gets
--- truncated.
--- The dp PHY frame is prepended with at least 1 idle word and a start of
--- frame delimiter (sfd) word. Different sfd words can be used to have
--- multiple independent dp frame streams via one dp PHY link. The dat block
--- size is fixed per dp frame stream.
--- More idle words are sent between frames if necessary. The out_val, out_sof
--- and out_eof signals are available to ease subsequent tx frame scheduling,
--- but they are not used on the actual dp PHY link. The idle word just before
--- the sfd is also marked valid and indicated by the out_sof to ensure that
--- there is at least one idle word between frames.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_packetizing_pkg.all;
+
+ -- Reuse from LOFAR rad_frame_tx.vhd and rad_frame_tx(rtl).vhd
+
+ -- Purpose:
+ -- Pass on the input data path frame:
+ --
+ -- -----------------------
+ -- | fsn | dat ... | brc |
+ -- -----------------------
+ -- sof eof
+ -- val val ... val
+ --
+ -- into an output data path PHY frame:
+ --
+ -- ----------------------------------
+ -- idle |idle| sfd | fsn | dat ... | crc | idle ...
+ -- ----------------------------------
+ -- sof eof
+ -- val val val val ... val
+ --
+ -- Description:
+ -- An input internal frame consists of fsn, data and brc. The in_sof marks
+ -- fsn and the in_eof marks the brc. When in_val is '0' then c_dp_idle data
+ -- is output.
+ -- The dp PHY output frame suits point it point links only. A valid CRC is
+ -- inserted when the brc is OK else insert NOT crc to propagate the brc error
+ -- at dp PHY level. For dat'LENGTH < c_dp_crc_w the transmitted crc word gets
+ -- extended. For dat'LENGTH > c_dp_crc_w the transmitted crc word gets
+ -- truncated.
+ -- The dp PHY frame is prepended with at least 1 idle word and a start of
+ -- frame delimiter (sfd) word. Different sfd words can be used to have
+ -- multiple independent dp frame streams via one dp PHY link. The dat block
+ -- size is fixed per dp frame stream.
+ -- More idle words are sent between frames if necessary. The out_val, out_sof
+ -- and out_eof signals are available to ease subsequent tx frame scheduling,
+ -- but they are not used on the actual dp PHY link. The idle word just before
+ -- the sfd is also marked valid and indicated by the out_sof to ensure that
+ -- there is at least one idle word between frames.
entity dp_frame_tx is
generic (
@@ -211,8 +211,8 @@ begin
elsif in_val_dly2 = '0' then
if frame_busy = '0' then
nxt_out_dat <= c_idle; -- insert idle word when out_val is inactive between frames
- --ELSE
- -- do not transmit idle when out_val is inactive during a frame to reduce potential false sync at receiver
+ --ELSE
+ -- do not transmit idle when out_val is inactive during a frame to reduce potential false sync at receiver
end if;
end if;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_gap.vhd b/libraries/base/dp/src/vhdl/dp_gap.vhd
index 9f487ec1c7..ab00fdade6 100644
--- a/libraries/base/dp/src/vhdl/dp_gap.vhd
+++ b/libraries/base/dp/src/vhdl/dp_gap.vhd
@@ -34,17 +34,17 @@
-- valid data work comes in.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
entity dp_gap is
generic (
g_dat_len : natural := 1000000;
g_gap_len : natural := 5;
g_gap_extend : boolean := false -- if TRUE, the first valid='0' cycle is extended to g_gap_len by de-assertion of snk_out.ready.
- ); -- This results in all gaps having a minimum length of g_gap_len.
+ ); -- This results in all gaps having a minimum length of g_gap_len.
port (
clk : in std_logic;
rst : in std_logic;
@@ -97,45 +97,45 @@ begin
case state is
- when s_wait_for_val => -- Wait for valid data to come in
- if snk_in.valid = '1' then
- nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w);
- nxt_gap_cnt <= (others => '0');
- nxt_state <= s_counting;
- end if;
-
- when s_counting => -- Start counting cycles
- nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
- if clk_cnt = TO_UVEC(g_dat_len - 1, c_dat_len_w) then -- time to force a gap
- nxt_state <= s_force_not_rdy;
- snk_out.ready <= '0';
- nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w); -- we already have 1 clk cycle with ready='0' here
- end if;
- if snk_in.valid = '0' then -- Also start counting any invalid cycles
- if g_gap_extend = true then
- snk_out.ready <= '0'; -- Keep ready de-asserted. Gap_cnt will increment so it will be released again after g_gap_len.
+ when s_wait_for_val => -- Wait for valid data to come in
+ if snk_in.valid = '1' then
+ nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w);
+ nxt_gap_cnt <= (others => '0');
+ nxt_state <= s_counting;
+ end if;
+
+ when s_counting => -- Start counting cycles
+ nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
+ if clk_cnt = TO_UVEC(g_dat_len - 1, c_dat_len_w) then -- time to force a gap
+ nxt_state <= s_force_not_rdy;
+ snk_out.ready <= '0';
+ nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w); -- we already have 1 clk cycle with ready='0' here
+ end if;
+ if snk_in.valid = '0' then -- Also start counting any invalid cycles
+ if g_gap_extend = true then
+ snk_out.ready <= '0'; -- Keep ready de-asserted. Gap_cnt will increment so it will be released again after g_gap_len.
+ end if;
+ nxt_gap_cnt <= INCR_UVEC(gap_cnt, 1);
+ else
+ nxt_gap_cnt <= (others => '0');
end if;
- nxt_gap_cnt <= INCR_UVEC(gap_cnt, 1);
- else
- nxt_gap_cnt <= (others => '0');
- end if;
- if gap_cnt = TO_UVEC(g_gap_len - 1, c_gap_len_w) and snk_in.valid = '0' then -- A gap of sufficient length occured by itself (or valid='0' was extended); no need to force gap
- -- We've counted g_gap_len-1, plus the current gap cycle = g_gap_len
- nxt_gap_cnt <= (others => '0');
- nxt_clk_cnt <= (others => '0');
- nxt_state <= s_wait_for_val;
- if g_gap_extend = true then
- snk_out.ready <= src_in.ready; -- Release the ready signal again if it was forced down because of gap extension
+ if gap_cnt = TO_UVEC(g_gap_len - 1, c_gap_len_w) and snk_in.valid = '0' then -- A gap of sufficient length occured by itself (or valid='0' was extended); no need to force gap
+ -- We've counted g_gap_len-1, plus the current gap cycle = g_gap_len
+ nxt_gap_cnt <= (others => '0');
+ nxt_clk_cnt <= (others => '0');
+ nxt_state <= s_wait_for_val;
+ if g_gap_extend = true then
+ snk_out.ready <= src_in.ready; -- Release the ready signal again if it was forced down because of gap extension
+ end if;
+ end if;
+
+ when s_force_not_rdy => -- Force snk_out.ready to '0' for g_gap_len clk cycles
+ snk_out.ready <= '0';
+ nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
+ if clk_cnt = TO_UVEC(g_gap_len - 1, c_dat_len_w) then
+ nxt_state <= s_wait_for_val;
+ nxt_clk_cnt <= (others => '0');
end if;
- end if;
-
- when s_force_not_rdy => -- Force snk_out.ready to '0' for g_gap_len clk cycles
- snk_out.ready <= '0';
- nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
- if clk_cnt = TO_UVEC(g_gap_len - 1, c_dat_len_w) then
- nxt_state <= s_wait_for_val;
- nxt_clk_cnt <= (others => '0');
- end if;
end case;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd b/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
index 4de9166883..b7535b99bb 100644
--- a/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
@@ -25,10 +25,10 @@
-- and g_symbol_w.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_hdr_insert is
generic (
@@ -67,25 +67,25 @@ architecture str of dp_hdr_insert is
begin
no_bypass: if g_internal_bypass = false generate
u_dp_ram_from_mm : entity work.mms_dp_ram_from_mm
- generic map (
- g_ram_wr_nof_words => g_hdr_nof_words * (g_data_w / c_word_w),
- g_ram_rd_dat_w => g_data_w,
- g_init_file => g_init_hdr,
- g_dp_on_at_init => g_dp_on_at_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- reg_mosi => reg_mosi,
- ram_mosi => ram_mosi,
-
- src_in => hdr_siso,
- src_out => hdr_sosi
- );
+ generic map (
+ g_ram_wr_nof_words => g_hdr_nof_words * (g_data_w / c_word_w),
+ g_ram_rd_dat_w => g_data_w,
+ g_init_file => g_init_hdr,
+ g_dp_on_at_init => g_dp_on_at_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ reg_mosi => reg_mosi,
+ ram_mosi => ram_mosi,
+
+ src_in => hdr_siso,
+ src_out => hdr_sosi
+ );
hdr_siso <= concat_siso_arr(0);
snk_out <= concat_siso_arr(1);
@@ -93,20 +93,20 @@ begin
concat_sosi_arr(1) <= snk_in;
u_dp_concat : entity work.dp_concat -- RL = 1
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- -- ST sinks
- snk_out_arr => concat_siso_arr,
- snk_in_arr => concat_sosi_arr,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- ST sinks
+ snk_out_arr => concat_siso_arr,
+ snk_in_arr => concat_sosi_arr,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
gen_bypass : if g_internal_bypass = true generate
diff --git a/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd b/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
index c924c29515..5ba1d3185e 100644
--- a/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_hdr_remove is
generic (
@@ -57,41 +57,41 @@ architecture str of dp_hdr_remove is
signal split_sosi_arr : t_dp_sosi_arr(0 to 1);
begin
u_dp_ram_to_mm : entity work.dp_ram_to_mm
- generic map (
- g_ram_rd_nof_words => g_hdr_nof_words * (g_data_w / c_word_w),
- g_ram_wr_dat_w => g_data_w
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_ram_rd_nof_words => g_hdr_nof_words * (g_data_w / c_word_w),
+ g_ram_wr_dat_w => g_data_w
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- sla_out => sla_out,
- sla_in => sla_in,
+ sla_out => sla_out,
+ sla_in => sla_in,
- snk_in => split_sosi_arr(0),
- snk_out => split_siso_arr(0)
- );
+ snk_in => split_sosi_arr(0),
+ snk_out => split_siso_arr(0)
+ );
split_siso_arr(1) <= src_in;
src_out <= split_sosi_arr(1);
u_split : entity work.dp_split -- RL = 1
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => c_nof_symbols
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- -- ST sinks
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in_arr => split_siso_arr,
- src_out_arr => split_sosi_arr
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => c_nof_symbols
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- ST sinks
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in_arr => split_siso_arr,
+ src_out_arr => split_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd b/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
index 18f45d4172..7eb3b171b9 100644
--- a/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
@@ -21,21 +21,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
--- Purpose:
--- Hold hld_ctrl active until next ready high when in_ctrl is active while
--- ready went low
--- Description:
--- When ready goes low there may still arrive one new valid data. The control
--- information for this data can then be held with this component. When ready
--- goes high again the held data can then be output and the hld_ctrl is
--- released. After that the subsequent data output can come directly from the
--- up stream source, until ready goes low again.
--- Remarks:
--- . Ready latency RL = 1
--- . The in_ctrl is typically in_valid, in_sop or in_eop
--- . Typically used together with dp_hold_data
+ -- Purpose:
+ -- Hold hld_ctrl active until next ready high when in_ctrl is active while
+ -- ready went low
+ -- Description:
+ -- When ready goes low there may still arrive one new valid data. The control
+ -- information for this data can then be held with this component. When ready
+ -- goes high again the held data can then be output and the hld_ctrl is
+ -- released. After that the subsequent data output can come directly from the
+ -- up stream source, until ready goes low again.
+ -- Remarks:
+ -- . Ready latency RL = 1
+ -- . The in_ctrl is typically in_valid, in_sop or in_eop
+ -- . Typically used together with dp_hold_data
entity dp_hold_ctrl is
port (
@@ -55,11 +55,11 @@ begin
lo_ctrl <= not in_ctrl and ready; -- release
u_hld_ctrl : entity common_lib.common_switch
- port map (
- rst => rst,
- clk => clk,
- switch_high => hi_ctrl,
- switch_low => lo_ctrl,
- out_level => hld_ctrl
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => hi_ctrl,
+ switch_low => lo_ctrl,
+ out_level => hld_ctrl
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_hold_data.vhd b/libraries/base/dp/src/vhdl/dp_hold_data.vhd
index 73323f54a6..31ff57d080 100644
--- a/libraries/base/dp/src/vhdl/dp_hold_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hold_data.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
--- Purpose:
--- Hold the in_data value when in_en is inactive. The held data can then be
--- output when the downstream sink is ready again.
--- Description:
--- Hold last in_data value when not valid else register the new in_data.
--- Remarks:
--- . The rst can be left not connected, because typically the data value at
--- reset is don't care (because the data valid will then be low)
--- . The in_en is typically in_valid or ready
--- . The in_data is typically in_data, in_empty, in_error or in_channel
--- . Typically used together with dp_hold_ctrl
+ -- Purpose:
+ -- Hold the in_data value when in_en is inactive. The held data can then be
+ -- output when the downstream sink is ready again.
+ -- Description:
+ -- Hold last in_data value when not valid else register the new in_data.
+ -- Remarks:
+ -- . The rst can be left not connected, because typically the data value at
+ -- reset is don't care (because the data valid will then be low)
+ -- . The in_en is typically in_valid or ready
+ -- . The in_data is typically in_data, in_empty, in_error or in_channel
+ -- . Typically used together with dp_hold_ctrl
entity dp_hold_data is
port (
diff --git a/libraries/base/dp/src/vhdl/dp_hold_input.vhd b/libraries/base/dp/src/vhdl/dp_hold_input.vhd
index f5e5dd4572..9d5a5bfe82 100644
--- a/libraries/base/dp/src/vhdl/dp_hold_input.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hold_input.vhd
@@ -21,38 +21,38 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
--- Purpose:
--- Hold the sink input
--- Description:
--- This dp_hold_input provides the necessary input logic to hold the input
--- data and control to easily register the source output. Compared to
--- dp_pipeling the dp_hold_input is the same except for the output register
--- stage. In this way dp_hold_input can be used in a more complicated stream
--- component where the output is not always the same as the input.
--- The snk_in.valid and hold_in.valid are never high at the same time.
--- If src_in.ready goes low while snk_in.valid is high then this snk_in.valid
--- is held in hold_in.valid and the corresponding snk_in.data will get held
--- in the external src_out_reg.data. When src_in.ready goes high again then
--- the held data becomes valid via src_out_reg.valid and hold_in.valid goes
--- low. Due to the RL=1 the next cycle the snk_in.valid from the sink may go
--- high. The next_src_out control signals are equal to pend_src_out AND
--- src_in.ready, so they can directly be assigned to src_out_reg.data if the
--- snk_in.data needs to be passed on.
--- The internal pend_src_out control signals are available outside, in
--- addition to the next_src_out control signals, to support external control
--- independent of src_in.ready. Use pend_scr_out instead of next_src_out
--- to avoid combinatorial loop when src_in.ready depends on next_src_out.
--- The pend_src_out signals are used to implement show ahead behaviour like
--- with RL=0, but for RL=1. The input can then be stopped based on the snk_in
--- data and later on continued again without losing this snk_in data, because
--- it was held as described above.
--- Remarks:
--- . Ready latency = 1
--- . Without flow control so when src_in.ready = '1' fixed, then dp_hold_input
--- becomes void because the dp_hold_ctrl output then remains '0'.
+ -- Purpose:
+ -- Hold the sink input
+ -- Description:
+ -- This dp_hold_input provides the necessary input logic to hold the input
+ -- data and control to easily register the source output. Compared to
+ -- dp_pipeling the dp_hold_input is the same except for the output register
+ -- stage. In this way dp_hold_input can be used in a more complicated stream
+ -- component where the output is not always the same as the input.
+ -- The snk_in.valid and hold_in.valid are never high at the same time.
+ -- If src_in.ready goes low while snk_in.valid is high then this snk_in.valid
+ -- is held in hold_in.valid and the corresponding snk_in.data will get held
+ -- in the external src_out_reg.data. When src_in.ready goes high again then
+ -- the held data becomes valid via src_out_reg.valid and hold_in.valid goes
+ -- low. Due to the RL=1 the next cycle the snk_in.valid from the sink may go
+ -- high. The next_src_out control signals are equal to pend_src_out AND
+ -- src_in.ready, so they can directly be assigned to src_out_reg.data if the
+ -- snk_in.data needs to be passed on.
+ -- The internal pend_src_out control signals are available outside, in
+ -- addition to the next_src_out control signals, to support external control
+ -- independent of src_in.ready. Use pend_scr_out instead of next_src_out
+ -- to avoid combinatorial loop when src_in.ready depends on next_src_out.
+ -- The pend_src_out signals are used to implement show ahead behaviour like
+ -- with RL=0, but for RL=1. The input can then be stopped based on the snk_in
+ -- data and later on continued again without losing this snk_in data, because
+ -- it was held as described above.
+ -- Remarks:
+ -- . Ready latency = 1
+ -- . Without flow control so when src_in.ready = '1' fixed, then dp_hold_input
+ -- becomes void because the dp_hold_ctrl output then remains '0'.
entity dp_hold_input is
port (
@@ -90,40 +90,40 @@ begin
-- of a next packet to get pushed out.
u_hold_val : entity work.dp_hold_ctrl
- port map (
- rst => rst,
- clk => clk,
- ready => src_in.ready,
- in_ctrl => snk_in.valid,
- hld_ctrl => hold_in.valid
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ ready => src_in.ready,
+ in_ctrl => snk_in.valid,
+ hld_ctrl => hold_in.valid
+ );
u_hold_sync : entity work.dp_hold_ctrl
- port map (
- rst => rst,
- clk => clk,
- ready => src_in.ready,
- in_ctrl => snk_in.sync,
- hld_ctrl => hold_in.sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ ready => src_in.ready,
+ in_ctrl => snk_in.sync,
+ hld_ctrl => hold_in.sync
+ );
u_hold_sop : entity work.dp_hold_ctrl
- port map (
- rst => rst,
- clk => clk,
- ready => src_in.ready,
- in_ctrl => snk_in.sop,
- hld_ctrl => hold_in.sop
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ ready => src_in.ready,
+ in_ctrl => snk_in.sop,
+ hld_ctrl => hold_in.sop
+ );
u_hold_eop : entity work.dp_hold_ctrl
- port map (
- rst => rst,
- clk => clk,
- ready => src_in.ready,
- in_ctrl => snk_in.eop,
- hld_ctrl => hold_in.eop
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ ready => src_in.ready,
+ in_ctrl => snk_in.eop,
+ hld_ctrl => hold_in.eop
+ );
p_pend_src_out : process(snk_in, src_out_reg, hold_in)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd b/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
index 5335ee16ed..a6214c528a 100755
--- a/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
+++ b/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
@@ -20,51 +20,51 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-
--- Author:
--- . Eric Kooistra
--- Purpose:
--- . Interleave g_nof_inputs parallel inputs into one serial output. This
--- functions is the inverse of dp_deinterleave_one_to_n.
--- Description:
--- . The src_out blocks size will be an integer multiple of g_nof_inputs, so
--- all snk_in_arr info and control fields have the same information.
--- Therefore the sosi info and control fields are take from snk_in_arr(0).
--- . The snk_in_arr data must arrive with >= g_nof_inputs-1 idle cycles
--- to allow the output to be serialized. The function does support siso
--- flow control.
--- . The snk_in_arr(0) can be output immediately, because if the input can
--- be valid (because ready was '1' in the previous clk cylce, RL=1) then
--- the output is allowed to be valid too (because the implementation is
--- combinatorial, any pipelining to ease timing closure is done separately
--- at the output). The timing diagram explains the flow control in relation
--- to snk_in_arr().valid and src_in.ready.
---
--- clk 0 1 2 3 4 5 6 7 8
--- src_in.ready 1 1 0 1 1 1 1 1 1
--- r.ready 1 1 0 1 1 1 1 1
--- snk_in_arr [2] [2]
--- [1] [1]
--- snk_in_arr [0] [0]
--- snk_in_arr.valid 1 0 0 0 0 1 0 0
--- src_out cnt [0][1][2][2][0][0][1][2]
--- src_out.valid 1 1 0 1 0 1 1 1
--- shift_ready 0 0 0 1 1 0 0 1
--- ^ ^
--- not ready in clk 2 --/ |
--- ready in clk 4 but no new data --/
---
--- Remark:
--- . The function needs r.ready because it also outputs when there is no valid
--- input. The r.ready is the previous src_in.ready, so this assumes RL = 1.
--- . The pair of dp_interleave_n_to_one.vhd and dp_deinterleave_one_to_n.vhd
--- is simpler than dp_interleave because it goes to and from 1. The dp_folder
--- only supports n that is power of 2.
---
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+
+ -- Author:
+ -- . Eric Kooistra
+ -- Purpose:
+ -- . Interleave g_nof_inputs parallel inputs into one serial output. This
+ -- functions is the inverse of dp_deinterleave_one_to_n.
+ -- Description:
+ -- . The src_out blocks size will be an integer multiple of g_nof_inputs, so
+ -- all snk_in_arr info and control fields have the same information.
+ -- Therefore the sosi info and control fields are take from snk_in_arr(0).
+ -- . The snk_in_arr data must arrive with >= g_nof_inputs-1 idle cycles
+ -- to allow the output to be serialized. The function does support siso
+ -- flow control.
+ -- . The snk_in_arr(0) can be output immediately, because if the input can
+ -- be valid (because ready was '1' in the previous clk cylce, RL=1) then
+ -- the output is allowed to be valid too (because the implementation is
+ -- combinatorial, any pipelining to ease timing closure is done separately
+ -- at the output). The timing diagram explains the flow control in relation
+ -- to snk_in_arr().valid and src_in.ready.
+ --
+ -- clk 0 1 2 3 4 5 6 7 8
+ -- src_in.ready 1 1 0 1 1 1 1 1 1
+ -- r.ready 1 1 0 1 1 1 1 1
+ -- snk_in_arr [2] [2]
+ -- [1] [1]
+ -- snk_in_arr [0] [0]
+ -- snk_in_arr.valid 1 0 0 0 0 1 0 0
+ -- src_out cnt [0][1][2][2][0][0][1][2]
+ -- src_out.valid 1 1 0 1 0 1 1 1
+ -- shift_ready 0 0 0 1 1 0 0 1
+ -- ^ ^
+ -- not ready in clk 2 --/ |
+ -- ready in clk 4 but no new data --/
+ --
+ -- Remark:
+ -- . The function needs r.ready because it also outputs when there is no valid
+ -- input. The r.ready is the previous src_in.ready, so this assumes RL = 1.
+ -- . The pair of dp_interleave_n_to_one.vhd and dp_deinterleave_one_to_n.vhd
+ -- is simpler than dp_interleave because it goes to and from 1. The dp_folder
+ -- only supports n that is power of 2.
+ --
entity dp_interleave_n_to_one is
generic (
g_pipeline : natural := 1; -- 0 for combinatorial, > 0 for registers
@@ -189,17 +189,17 @@ begin
-- Pipeline output to easy timing closure
u_pipeline_output : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => out_siso,
- snk_in => out_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => out_siso,
+ snk_in => out_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd b/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
index 237ba315c2..1700ffdde0 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
@@ -21,30 +21,30 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-
--- Purpose:
--- Adapt the g_in_latency input ready to the g_out_latency output latency.
--- A typical application is to use this latency adapter to provide a read
--- ahead interface to a default FIFO with e.g. read latency 1 or 2.
--- Description:
--- If g_in_latency > g_out_latency then the input latency is first adapted
--- to zero latency by means of a latency FIFO. After that a delay line for
--- src_in.ready yields the g_out_latency output latency.
--- If g_in_latency < g_out_latency, then a delay line for src_in.ready yields
--- the g_out_latency output latency.
--- The sync input is also passed on, only if it occurs during valid. The
--- constant c_pass_sync_during_not_valid is defined to preserve the
--- corresponding section of code for passing the sync also during not valid.
--- Remark:
--- . The snk_out.ready is derived combinatorially from the src_in.ready. If for
--- timing performance it is needed to register snk_out.ready, then this can
--- be done by first increasing the ready latency using this adapter with
--- g_in_latency = g_out_latency + 1, followed by a second adapter to reach
--- the required output ready latency latency.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+
+ -- Purpose:
+ -- Adapt the g_in_latency input ready to the g_out_latency output latency.
+ -- A typical application is to use this latency adapter to provide a read
+ -- ahead interface to a default FIFO with e.g. read latency 1 or 2.
+ -- Description:
+ -- If g_in_latency > g_out_latency then the input latency is first adapted
+ -- to zero latency by means of a latency FIFO. After that a delay line for
+ -- src_in.ready yields the g_out_latency output latency.
+ -- If g_in_latency < g_out_latency, then a delay line for src_in.ready yields
+ -- the g_out_latency output latency.
+ -- The sync input is also passed on, only if it occurs during valid. The
+ -- constant c_pass_sync_during_not_valid is defined to preserve the
+ -- corresponding section of code for passing the sync also during not valid.
+ -- Remark:
+ -- . The snk_out.ready is derived combinatorially from the src_in.ready. If for
+ -- timing performance it is needed to register snk_out.ready, then this can
+ -- be done by first increasing the ready latency using this adapter with
+ -- g_in_latency = g_out_latency + 1, followed by a second adapter to reach
+ -- the required output ready latency latency.
entity dp_latency_adapter is
generic (
@@ -103,20 +103,20 @@ begin
no_fifo : if c_diff_latency > 0 generate -- g_out_latency > g_in_latency
-- Go from g_in_latency to required larger g_out_latency
u_latency : entity work.dp_latency_increase
- generic map (
- g_in_latency => g_in_latency,
- g_incr_latency => c_diff_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => i_snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => g_in_latency,
+ g_incr_latency => c_diff_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => i_snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate no_fifo;
gen_fifo : if c_diff_latency < 0 generate -- g_out_latency < g_in_latency
@@ -235,19 +235,19 @@ begin
-- Go from 0 FIFO latency to required g_out_latency (only wires when g_out_latency=0)
u_latency : entity work.dp_latency_increase
- generic map (
- g_in_latency => 0,
- g_incr_latency => g_out_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => ff_siso,
- snk_in => ff_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => 0,
+ g_incr_latency => g_out_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => ff_siso,
+ snk_in => ff_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate gen_fifo;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd b/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
index 77c10e03b9..a927ba0a5c 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
@@ -20,22 +20,22 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose: Simple DP fifo in registers.
--- Description:
--- The fifo can store up to g_fifo_size words. When the FIFO is full then
--- the snk_out.ready is '0', so wr_ful is equivalent and equal to NOT
--- snk_out.ready.
---
--- Remark:
--- . Uses a dp_latency_adapter as FIFO.
--- . Choose g_fifo_size > g_output_rl - g_input_rl to ensure that
--- c_adapter_input_rl > c_adapter_output_rl, because only then the FIFO
--- logic will be instantiated inside the dp_latency_adapter
+ -- Purpose: Simple DP fifo in registers.
+ -- Description:
+ -- The fifo can store up to g_fifo_size words. When the FIFO is full then
+ -- the snk_out.ready is '0', so wr_ful is equivalent and equal to NOT
+ -- snk_out.ready.
+ --
+ -- Remark:
+ -- . Uses a dp_latency_adapter as FIFO.
+ -- . Choose g_fifo_size > g_output_rl - g_input_rl to ensure that
+ -- c_adapter_input_rl > c_adapter_output_rl, because only then the FIFO
+ -- logic will be instantiated inside the dp_latency_adapter
entity dp_latency_fifo is
generic (
@@ -101,24 +101,24 @@ begin
wr_ful <= not i_snk_out.ready;
u_dp_latency_adapter : entity work.dp_latency_adapter
- generic map (
- g_in_latency => c_adapter_input_rl,
- g_out_latency => c_adapter_output_rl
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor internal FIFO filling
- fifo_usedw => i_usedw,
- fifo_ful => OPEN,
- fifo_emp => rd_emp,
- -- ST sink
- snk_out => fifo_snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => c_adapter_input_rl,
+ g_out_latency => c_adapter_output_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor internal FIFO filling
+ fifo_usedw => i_usedw,
+ fifo_ful => OPEN,
+ fifo_emp => rd_emp,
+ -- ST sink
+ snk_out => fifo_snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_latency_increase.vhd b/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
index 4ac0f42465..95105ba309 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
@@ -21,27 +21,27 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose:
--- Typically used in dp_latency_adapter.
--- Description:
--- Increase the output ready latency by g_incr_latency compared to the input
--- ready latency g_in_latency. Hence the output latency becomes g_in_latency
--- + g_incr_latency.
--- Remark:
--- . The SOSI data stream signals (i.e. data, empty, channel, err) are passed
--- on as wires.
--- . The out_sync, out_val, out_sop and out_eop are internally AND with the
--- delayed src_in.ready, this is only truely necessary if the input ready
--- latency is 0, but it does not harm to do it also when the input ready
--- latency > 0. However to easy achieving P&R timing it is better to not have
--- unnessary logic in the combinatorial path of out_sync, out_val, out_sop
--- and out_eop, therefore the AND with reg_val is only generated when
--- g_in_latency=0.
+ -- Purpose:
+ -- Typically used in dp_latency_adapter.
+ -- Description:
+ -- Increase the output ready latency by g_incr_latency compared to the input
+ -- ready latency g_in_latency. Hence the output latency becomes g_in_latency
+ -- + g_incr_latency.
+ -- Remark:
+ -- . The SOSI data stream signals (i.e. data, empty, channel, err) are passed
+ -- on as wires.
+ -- . The out_sync, out_val, out_sop and out_eop are internally AND with the
+ -- delayed src_in.ready, this is only truely necessary if the input ready
+ -- latency is 0, but it does not harm to do it also when the input ready
+ -- latency > 0. However to easy achieving P&R timing it is better to not have
+ -- unnessary logic in the combinatorial path of out_sync, out_val, out_sop
+ -- and out_eop, therefore the AND with reg_val is only generated when
+ -- g_in_latency=0.
entity dp_latency_increase is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_loopback.vhd b/libraries/base/dp/src/vhdl/dp_loopback.vhd
index c28f0223b3..2f57803437 100644
--- a/libraries/base/dp/src/vhdl/dp_loopback.vhd
+++ b/libraries/base/dp/src/vhdl/dp_loopback.vhd
@@ -19,33 +19,33 @@
--
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-
--- General function:
--- =================
--- ________________
--- | |
--- 0 -----> | snk(0)->src(0) | -----> 0
--- | || /\ |
--- | \/ || |
--- 1 <----- | src(1)<-snk(1) | <----- 1
--- |________________|
-
--- 00 = Loop back neither
--- connects snk(0) to src(0)
--- connects snk(1) to src(1)
--- 01 = Loop back (0) to (1)
--- connects snk(0) to src(1)
--- connects snk(1) to dp_flush or c_siso_hold depending on g_flush_not_hold
--- 10 = Loop back (1) to (0)
--- connects snk(1) to src(0)
--- connects snk(0) to dp_flush or c_siso_hold depending on g_flush_not_hold
--- 11 = Loop back both
--- connects snk(0) to src(1)
--- connects snk(1) to src(0)
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+
+ -- General function:
+ -- =================
+ -- ________________
+ -- | |
+ -- 0 -----> | snk(0)->src(0) | -----> 0
+ -- | || /\ |
+ -- | \/ || |
+ -- 1 <----- | src(1)<-snk(1) | <----- 1
+ -- |________________|
+
+ -- 00 = Loop back neither
+ -- connects snk(0) to src(0)
+ -- connects snk(1) to src(1)
+ -- 01 = Loop back (0) to (1)
+ -- connects snk(0) to src(1)
+ -- connects snk(1) to dp_flush or c_siso_hold depending on g_flush_not_hold
+ -- 10 = Loop back (1) to (0)
+ -- connects snk(1) to src(0)
+ -- connects snk(0) to dp_flush or c_siso_hold depending on g_flush_not_hold
+ -- 11 = Loop back both
+ -- connects snk(0) to src(1)
+ -- connects snk(1) to src(0)
entity dp_loopback is
generic (
@@ -141,82 +141,82 @@ begin
demux_1_siso_arr(2) <= c_dp_siso_flush;
u_dp_demux_0: entity work.dp_demux
- generic map (
- g_mode => 2,
- g_nof_output => c_nof_demux_out,
- g_combined => false,
- g_sel_ctrl_invert => true,
- g_sel_ctrl_pkt => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => snk_out_arr(0),
- snk_in => snk_in_arr(0),
-
- src_in_arr => demux_0_siso_arr,
- src_out_arr => demux_0_sosi_arr,
-
- sel_ctrl => demux_0_sel_ctrl,
- sel_stat => demux_0_sel_stat
- );
+ generic map (
+ g_mode => 2,
+ g_nof_output => c_nof_demux_out,
+ g_combined => false,
+ g_sel_ctrl_invert => true,
+ g_sel_ctrl_pkt => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => snk_out_arr(0),
+ snk_in => snk_in_arr(0),
+
+ src_in_arr => demux_0_siso_arr,
+ src_out_arr => demux_0_sosi_arr,
+
+ sel_ctrl => demux_0_sel_ctrl,
+ sel_stat => demux_0_sel_stat
+ );
u_dp_demux_1: entity work.dp_demux
- generic map (
- g_mode => 2,
- g_nof_output => c_nof_demux_out,
- g_combined => false,
- g_sel_ctrl_invert => true,
- g_sel_ctrl_pkt => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => snk_out_arr(1),
- snk_in => snk_in_arr(1),
-
- src_in_arr => demux_1_siso_arr,
- src_out_arr => demux_1_sosi_arr,
-
- sel_ctrl => demux_1_sel_ctrl,
- sel_stat => demux_1_sel_stat
- );
+ generic map (
+ g_mode => 2,
+ g_nof_output => c_nof_demux_out,
+ g_combined => false,
+ g_sel_ctrl_invert => true,
+ g_sel_ctrl_pkt => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => snk_out_arr(1),
+ snk_in => snk_in_arr(1),
+
+ src_in_arr => demux_1_siso_arr,
+ src_out_arr => demux_1_sosi_arr,
+
+ sel_ctrl => demux_1_sel_ctrl,
+ sel_stat => demux_1_sel_stat
+ );
u_dp_mux_0 : entity work.dp_mux
- generic map (
- g_mode => 2,
- g_sel_ctrl_invert => true
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_mode => 2,
+ g_sel_ctrl_invert => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out_arr => mux_0_siso_arr,
- snk_in_arr => mux_0_sosi_arr,
+ snk_out_arr => mux_0_siso_arr,
+ snk_in_arr => mux_0_sosi_arr,
- src_in => src_in_arr(0),
- src_out => src_out_arr(0),
+ src_in => src_in_arr(0),
+ src_out => src_out_arr(0),
- sel_ctrl => mux_0_sel_ctrl
- );
+ sel_ctrl => mux_0_sel_ctrl
+ );
u_dp_mux_1 : entity work.dp_mux
- generic map (
- g_mode => 2,
- g_sel_ctrl_invert => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out_arr => mux_1_siso_arr,
- snk_in_arr => mux_1_sosi_arr,
-
- src_in => src_in_arr(1),
- src_out => src_out_arr(1),
-
- sel_ctrl => mux_1_sel_ctrl
- );
+ generic map (
+ g_mode => 2,
+ g_sel_ctrl_invert => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out_arr => mux_1_siso_arr,
+ snk_in_arr => mux_1_sosi_arr,
+
+ src_in => src_in_arr(1),
+ src_out => src_out_arr(1),
+
+ sel_ctrl => mux_1_sel_ctrl
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_mon.vhd b/libraries/base/dp/src/vhdl/dp_mon.vhd
index e1d72e7654..19ba3df61b 100644
--- a/libraries/base/dp/src/vhdl/dp_mon.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mon.vhd
@@ -23,10 +23,10 @@
-- passing stream in any way - it monitors the stream and keeps useful stats.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_mon is
generic (
@@ -59,16 +59,16 @@ begin
snk_accept <= snk_in.valid when g_latency > 0 else snk_in.valid and src_in.ready;
u_word_cntr : entity common_lib.common_counter
- generic map (
- g_width => 32,
- g_step_size => 1,
- g_latency => 0
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => clr,
- cnt_en => snk_accept,
- count => word_cnt
- );
+ generic map (
+ g_width => 32,
+ g_step_size => 1,
+ g_latency => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => clr,
+ cnt_en => snk_accept,
+ count => word_cnt
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_mux.vhd b/libraries/base/dp/src/vhdl/dp_mux.vhd
index 9e15141bf0..154eda67f2 100644
--- a/libraries/base/dp/src/vhdl/dp_mux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mux.vhd
@@ -79,11 +79,11 @@
-- use g_append_channel_lo=FALSE in combination with g_mode=2.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_mux is
generic (
@@ -211,34 +211,34 @@ begin
gen_input : for I in 0 to g_nof_input - 1 generate
gen_fifo : if g_use_fifo = true generate
u_fill : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_in_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_in_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_fifo_fill => c_fifo_fill(I),
- g_fifo_size => c_fifo_size(I),
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => i_snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => rd_siso_arr(I),
- src_out => rd_sosi_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_in_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_in_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_fifo_fill => c_fifo_fill(I),
+ g_fifo_size => c_fifo_size(I),
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => i_snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => rd_siso_arr(I),
+ src_out => rd_sosi_arr(I)
+ );
end generate;
no_fifo : if g_use_fifo = false generate
@@ -248,18 +248,18 @@ begin
-- Hold the sink input to be able to register the source output
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN, -- SISO ready
- snk_in => rd_sosi_arr(I), -- SOSI
- -- ST source
- src_in => hold_src_in_arr(I), -- SISO ready
- next_src_out => next_src_out_arr(I), -- SOSI
- pend_src_out => pend_src_out_arr(I),
- src_out_reg => src_out_hi
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN, -- SISO ready
+ snk_in => rd_sosi_arr(I), -- SOSI
+ -- ST source
+ src_in => hold_src_in_arr(I), -- SISO ready
+ next_src_out => next_src_out_arr(I), -- SOSI
+ pend_src_out => pend_src_out_arr(I),
+ src_out_reg => src_out_hi
+ );
end generate;
-- Register and adjust external MM sel_ctrl for g_sel_ctrl_invert
@@ -289,16 +289,16 @@ begin
gen_sel_ctrl_framed : if g_mode = 4 generate
u_dp_frame_busy_arr : entity work.dp_frame_busy_arr
- generic map (
- g_nof_inputs => g_nof_input,
- g_pipeline => 1 -- register snk_in_busy to ease timing closure
- )
- port map (
- rst => rst,
- clk => clk,
- snk_in_arr => rd_sosi_arr,
- snk_in_busy_arr => rd_sosi_busy_arr
- );
+ generic map (
+ g_nof_inputs => g_nof_input,
+ g_pipeline => 1 -- register snk_in_busy to ease timing closure
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_in_arr => rd_sosi_arr,
+ snk_in_busy_arr => rd_sosi_busy_arr
+ );
hold_src_in_arr <= (others => c_dp_siso_rdy); -- effectively bypass the dp_hold_input
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
index 374201d300..983a796812 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
@@ -40,12 +40,12 @@
-- control the snk_out_arr empty field.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
entity dp_offload_rx is
generic (
@@ -109,21 +109,21 @@ begin
---------------------------------------------------------------------------------------
gen_nof_streams: for i in 0 to g_nof_streams - 1 generate
u_dp_split : entity work.dp_split
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => c_symbol_w,
- g_nof_symbols => c_nof_header_symbols
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => snk_out_arr(i),
- snk_in => snk_in_arr(i),
-
- src_in_arr => dp_split_src_in_2arr(i),
- src_out_arr => dp_split_src_out_2arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => c_symbol_w,
+ g_nof_symbols => c_nof_header_symbols
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
+
+ src_in_arr => dp_split_src_in_2arr(i),
+ src_out_arr => dp_split_src_out_2arr(i)
+ );
-- In dp_split index 0 is head and index 1 is tail, but dp_split uses 0 TO
-- 1 range and dp_split_src_in_2arr()() uses 1 DOWNTO 0 range, so:
@@ -138,32 +138,32 @@ begin
---------------------------------------------------------------------------------------
gen_dp_field_blk : for i in 0 to g_nof_streams - 1 generate
u_dp_field_blk : entity work.dp_field_blk
- generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RO"),
- g_field_sel => c_field_sel,
- g_snk_data_w => c_dp_field_blk_snk_data_w, -- g_data_w,
- g_src_data_w => c_dp_field_blk_src_data_w, -- field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"))
- g_in_symbol_w => c_symbol_w,
- g_out_symbol_w => c_symbol_w,
- g_mode => 2 -- sink mode
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RO"),
+ g_field_sel => c_field_sel,
+ g_snk_data_w => c_dp_field_blk_snk_data_w, -- g_data_w,
+ g_src_data_w => c_dp_field_blk_src_data_w, -- field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"))
+ g_in_symbol_w => c_symbol_w,
+ g_out_symbol_w => c_symbol_w,
+ g_mode => 2 -- sink mode
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- snk_in => dp_split_src_out_2arr(i)(1),
+ snk_in => dp_split_src_out_2arr(i)(1),
- src_out => dp_field_blk_src_out_arr(i),
+ src_out => dp_field_blk_src_out_arr(i),
--- slv_out => dp_field_blk_slv_out(i)(field_slv_len(g_hdr_field_arr)-1 DOWNTO 0),
--- slv_out_val => dp_field_blk_slv_out_val(i),
+ -- slv_out => dp_field_blk_slv_out(i)(field_slv_len(g_hdr_field_arr)-1 DOWNTO 0),
+ -- slv_out_val => dp_field_blk_slv_out_val(i),
- reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
- reg_slv_miso => reg_hdr_dat_miso_arr(i)
- );
+ reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
+ reg_slv_miso => reg_hdr_dat_miso_arr(i)
+ );
dp_field_blk_slv_out(i)(c_dp_field_blk_src_data_w - 1 downto 0) <= dp_field_blk_src_out_arr(i).data(c_dp_field_blk_src_data_w - 1 downto 0);
dp_field_blk_slv_out_val(i) <= dp_field_blk_src_out_arr(i).valid;
@@ -174,21 +174,21 @@ begin
---------------------------------------------------------------------------------------
gen_dp_tail_remove : for i in 0 to g_nof_streams - 1 generate
u_dp_tail_remove : entity work.dp_tail_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => c_symbol_w,
- g_nof_symbols => sel_a_b(g_remove_crc, g_crc_nof_words, 0)
- )
- port map (
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- snk_out => dp_split_src_in_2arr(i)(0),
- snk_in => dp_split_src_out_2arr(i)(0), -- tail part
-
- src_in => dp_tail_remove_src_in_arr(i),
- src_out => dp_tail_remove_src_out_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => c_symbol_w,
+ g_nof_symbols => sel_a_b(g_remove_crc, g_crc_nof_words, 0)
+ )
+ port map (
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ snk_out => dp_split_src_in_2arr(i)(0),
+ snk_in => dp_split_src_out_2arr(i)(0), -- tail part
+
+ src_in => dp_tail_remove_src_in_arr(i),
+ src_out => dp_tail_remove_src_out_arr(i)
+ );
end generate;
src_out_arr <= dp_tail_remove_src_out_arr;
@@ -224,14 +224,14 @@ begin
-- MM control & monitoring
---------------------------------------------------------------------------------------
u_common_mem_mux_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
index fe450e22c1..d6f03b0ca0 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
entity dp_offload_rx_filter is
generic (
- g_bypass : boolean := false;
+ g_bypass : boolean := false;
g_nof_streams : positive := 1;
g_data_w : natural;
g_hdr_field_arr : t_common_field_arr;
@@ -109,8 +109,8 @@ begin
end loop check;
if(dp_rst = '1') then
- v.src_out_arr := (others => c_dp_sosi_rst);
- v.valid := (others => '0');
+ v.src_out_arr := (others => c_dp_sosi_rst);
+ v.valid := (others => '0');
end if;
rin <= v;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
index d091171e52..46fefb2641 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
entity dp_offload_rx_filter_mm is
generic (
@@ -141,8 +141,8 @@ begin
end loop check;
if(dp_rst = '1') then
- v.src_out_arr := (others => c_dp_sosi_rst);
- v.valid := (others => '0');
+ v.src_out_arr := (others => c_dp_sosi_rst);
+ v.valid := (others => '0');
end if;
rin <= v;
@@ -165,81 +165,81 @@ begin
end if;
end process;
- -------------------------------------------
- -- mm_fields for MM access to each field --
- -------------------------------------------
+ -------------------------------------------
+ -- mm_fields for MM access to each field --
+ -------------------------------------------
u_mult_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w)) + 1
- )
- port map (
- mosi => reg_dp_offload_rx_filter_hdr_fields_mosi,
- miso => reg_dp_offload_rx_filter_hdr_fields_miso,
- mosi_arr => mult_streams_mosi_arr,
- miso_arr => mult_streams_miso_arr
- );
-
- gen_mm_fields : for i in 0 to g_nof_streams - 1 generate
- u_common_mem_mux : entity common_lib.common_mem_mux
generic map (
- g_nof_mosi => 2,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w)) + 1
)
port map (
- mosi => mult_streams_mosi_arr(i),
- miso => mult_streams_miso_arr(i),
- mosi_arr => common_mosi_arr,
- miso_arr => common_miso_arr
+ mosi => reg_dp_offload_rx_filter_hdr_fields_mosi,
+ miso => reg_dp_offload_rx_filter_hdr_fields_miso,
+ mosi_arr => mult_streams_mosi_arr,
+ miso_arr => mult_streams_miso_arr
);
+ gen_mm_fields : for i in 0 to g_nof_streams - 1 generate
+ u_common_mem_mux : entity common_lib.common_mem_mux
+ generic map (
+ g_nof_mosi => 2,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => mult_streams_mosi_arr(i),
+ miso => mult_streams_miso_arr(i),
+ mosi_arr => common_mosi_arr,
+ miso_arr => common_miso_arr
+ );
+
eth_dst_mac_ena(i) <= is_true(reg_ena_sig(i)(0));
- ip_dst_addr_ena(i) <= is_true(reg_ena_sig(i)(32));
- ip_total_length_ena(i) <= is_true(reg_ena_sig(i)(64));
- udp_dst_port_ena(i) <= is_true(reg_ena_sig(i)(96));
+ ip_dst_addr_ena(i) <= is_true(reg_ena_sig(i)(32));
+ ip_total_length_ena(i) <= is_true(reg_ena_sig(i)(64));
+ udp_dst_port_ena(i) <= is_true(reg_ena_sig(i)(96));
cr : entity common_lib.common_reg_r_w_dc
- generic map(
- g_reg => c_ena_reg
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
- st_rst => dp_rst, -- reset synchronous with st_clk
- st_clk => dp_clk, -- other clock domain clock
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => common_mosi_arr(1), -- IN t_mem_mosi; -- actual ranges defined by g_reg
- sla_out => common_miso_arr(1), -- OUT t_mem_miso; -- actual ranges defined by g_reg
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_new => OPEN,
- in_reg => reg_ena_sig(i),
- out_reg => reg_ena_sig(i),
- out_new => open
- );
+ generic map(
+ g_reg => c_ena_reg
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
+ st_rst => dp_rst, -- reset synchronous with st_clk
+ st_clk => dp_clk, -- other clock domain clock
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => common_mosi_arr(1), -- IN t_mem_mosi; -- actual ranges defined by g_reg
+ sla_out => common_miso_arr(1), -- OUT t_mem_miso; -- actual ranges defined by g_reg
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_new => OPEN,
+ in_reg => reg_ena_sig(i),
+ out_reg => reg_ena_sig(i),
+ out_new => open
+ );
u_mm_fields_slv: entity mm_lib.mm_fields
- generic map(
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW")
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_mosi => common_mosi_arr(0),
- mm_miso => common_miso_arr(0),
-
- slv_clk => dp_clk,
- slv_rst => dp_rst,
-
- slv_in => mm_fields_slv_in_arr(i),
- slv_in_val => hdr_fields_val,
- slv_out => mm_fields_slv_out_arr(i)
- );
+ generic map(
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW")
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_mosi => common_mosi_arr(0),
+ mm_miso => common_miso_arr(0),
+
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
+
+ slv_in => mm_fields_slv_in_arr(i),
+ slv_in_val => hdr_fields_val,
+ slv_out => mm_fields_slv_out_arr(i)
+ );
end generate;
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd
index cbe97b4e0f..b82b7e8299 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_offload_rx_legacy is
generic (
@@ -63,63 +63,63 @@ architecture str of dp_offload_rx_legacy is
signal ram_hdr_remove_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
begin
u_common_mem_mux_hdr_ram : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_hdr_remove_ram_addr_w
- )
- port map (
- mosi => ram_hdr_remove_mosi,
- miso => ram_hdr_remove_miso,
- mosi_arr => ram_hdr_remove_mosi_arr,
- miso_arr => ram_hdr_remove_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_hdr_remove_ram_addr_w
+ )
+ port map (
+ mosi => ram_hdr_remove_mosi,
+ miso => ram_hdr_remove_miso,
+ mosi_arr => ram_hdr_remove_mosi_arr,
+ miso_arr => ram_hdr_remove_miso_arr
+ );
gen_nof_streams: for i in 0 to g_nof_streams - 1 generate
---------------------------------------------------------------------------------------
-- RX: Unframe: remove header (and CRC if phy link is used) from DP packets
---------------------------------------------------------------------------------------
u_frame_remove : entity dp_lib.dp_frame_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => c_byte_w,
- g_hdr_nof_words => g_hdr_nof_words,
- g_tail_nof_words => sel_a_b(g_remove_crc, g_crc_nof_words, 0)
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- snk_out => rx_siso_arr(i),
- snk_in => rx_sosi_arr(i),
-
- -- dp_frame_remove uses hdr_remove internally
- sla_in => ram_hdr_remove_mosi_arr(i),
- sla_out => ram_hdr_remove_miso_arr(i),
-
- src_in => rx_pkt_siso_arr(i),
- src_out => rx_pkt_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_nof_words => g_hdr_nof_words,
+ g_tail_nof_words => sel_a_b(g_remove_crc, g_crc_nof_words, 0)
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ snk_out => rx_siso_arr(i),
+ snk_in => rx_sosi_arr(i),
+
+ -- dp_frame_remove uses hdr_remove internally
+ sla_in => ram_hdr_remove_mosi_arr(i),
+ sla_out => ram_hdr_remove_miso_arr(i),
+
+ src_in => rx_pkt_siso_arr(i),
+ src_out => rx_pkt_sosi_arr(i)
+ );
---------------------------------------------------------------------------------------
-- RX: Convert DP packets to DP stream
---------------------------------------------------------------------------------------
u_dp_packet_dec : entity dp_lib.dp_packet_dec
- generic map (
- g_data_w => g_data_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- snk_out => rx_pkt_siso_arr(i),
- snk_in => rx_pkt_sosi_arr(i),
-
- src_in => dp_siso_arr(i),
- src_out => dp_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => rx_pkt_siso_arr(i),
+ snk_in => rx_pkt_sosi_arr(i),
+
+ src_in => dp_siso_arr(i),
+ src_out => dp_sosi_arr(i)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
index e88d96a678..ba35abf70c 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
@@ -41,13 +41,13 @@
-- Remarks:
library IEEE, common_lib, technology_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_offload_tx is
generic (
@@ -157,79 +157,79 @@ begin
snk_out_arr(i).xon <= src_in_arr(i).xon; -- Pass on XON from source side
u_dp_split : entity work.dp_split
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_data_w,
- g_nof_symbols => g_nof_words_per_block
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => dp_split_snk_out_arr(i),
- snk_in => dp_split_snk_in_arr(i),
-
- src_in_arr => dp_split_src_in_2arr(i),
- src_out_arr => dp_split_src_out_2arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_data_w,
+ g_nof_symbols => g_nof_words_per_block
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => dp_split_snk_out_arr(i),
+ snk_in => dp_split_snk_in_arr(i),
+
+ src_in_arr => dp_split_src_in_2arr(i),
+ src_out_arr => dp_split_src_out_2arr(i)
+ );
dp_split_src_in_2arr(i)(0) <= c_dp_siso_rdy; -- Always ready to throw away the tail
end generate;
-- Introduce the same delay (as dp_plit) on the corresponding header fields
u_dp_pipeline_arr_dp_split : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_dp_split_val_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in_arr => dp_split_hdr_fields_snk_in_arr,
- snk_out_arr => OPEN, -- Flow control is already taken care of by dp_split
-
- src_out_arr => dp_split_hdr_fields_src_out_arr,
- src_in_arr => dp_split_hdr_fields_src_in_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_dp_split_val_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in_arr => dp_split_hdr_fields_snk_in_arr,
+ snk_out_arr => OPEN, -- Flow control is already taken care of by dp_split
+
+ src_out_arr => dp_split_hdr_fields_src_out_arr,
+ src_in_arr => dp_split_hdr_fields_src_in_arr
+ );
---------------------------------------------------------------------------------------
-- Merge nof_blocks_per_packet
---------------------------------------------------------------------------------------
gen_dp_packet_merge : for i in 0 to g_nof_streams - 1 generate
u_dp_packet_merge : entity work.dp_packet_merge
+ generic map (
+ g_nof_pkt => g_nof_blocks_per_packet,
+ g_align_at_sync => g_pkt_merge_align_at_sync
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => dp_split_src_in_2arr(i)(1),
+ snk_in => dp_split_src_out_2arr(i)(1),
+
+ src_in => dp_packet_merge_src_in_arr(i),
+ src_out => dp_packet_merge_src_out_arr(i)
+ );
+ end generate;
+
+ -- Introduce the same delay (as dp_packet_merge) on the corresponding header fields
+ u_dp_pipeline_arr_dp_packet_merge : entity work.dp_pipeline_arr
generic map (
- g_nof_pkt => g_nof_blocks_per_packet,
- g_align_at_sync => g_pkt_merge_align_at_sync
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_dp_packet_merge_val_latency
)
port map (
rst => dp_rst,
clk => dp_clk,
- snk_out => dp_split_src_in_2arr(i)(1),
- snk_in => dp_split_src_out_2arr(i)(1),
+ snk_in_arr => dp_split_hdr_fields_src_out_arr,
+ snk_out_arr => dp_split_hdr_fields_src_in_arr,
- src_in => dp_packet_merge_src_in_arr(i),
- src_out => dp_packet_merge_src_out_arr(i)
+ src_out_arr => dp_packet_merge_hdr_fields_src_out_arr,
+ src_in_arr => dp_packet_merge_hdr_fields_src_in_arr
);
- end generate;
-
- -- Introduce the same delay (as dp_packet_merge) on the corresponding header fields
- u_dp_pipeline_arr_dp_packet_merge : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_dp_packet_merge_val_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in_arr => dp_split_hdr_fields_src_out_arr,
- snk_out_arr => dp_split_hdr_fields_src_in_arr,
-
- src_out_arr => dp_packet_merge_hdr_fields_src_out_arr,
- src_in_arr => dp_packet_merge_hdr_fields_src_in_arr
- );
-- dp_packet_merge_hdr_fields_src_out_arr contains a valid header for each block that was merged
-- into one packet. We want only the first valid header per merged block to be forwarded to
@@ -259,22 +259,22 @@ begin
---------------------------------------------------------------------------------------
gen_dp_fifo_fill : for i in 0 to sel_a_b(g_use_post_split_fifo, g_nof_streams, 0) - 1 generate
u_dp_fifo_fill : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_fifo_fill => c_dp_fifo_fill,
- g_fifo_size => c_dp_fifo_size
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_packet_merge_src_out_arr(i),
- snk_out => dp_packet_merge_src_in_arr(i),
-
- src_out => dp_fifo_fill_src_out_arr(i),
- src_in => dp_fifo_fill_src_in_arr(i)
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_fifo_fill => c_dp_fifo_fill,
+ g_fifo_size => c_dp_fifo_size
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => dp_packet_merge_src_out_arr(i),
+ snk_out => dp_packet_merge_src_in_arr(i),
+
+ src_out => dp_fifo_fill_src_out_arr(i),
+ src_in => dp_fifo_fill_src_in_arr(i)
+ );
dp_fifo_fill_src_in_arr(i).ready <= dp_concat_snk_out_2arr(i)(0).ready;
dp_fifo_fill_src_in_arr(i).xon <= '1'; -- Prevents flushing of frames
@@ -293,60 +293,60 @@ begin
gen_dp_field_blk : for i in 0 to g_nof_streams - 1 generate
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : entity work.dp_field_blk
- generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
- g_field_sel => g_hdr_field_sel,
- g_snk_data_w => c_dp_field_blk_snk_data_w,
- g_src_data_w => c_dp_field_blk_src_data_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- snk_in => dp_field_blk_snk_in_arr(i),
- snk_out => dp_field_blk_snk_out_arr(i),
-
- src_in => dp_concat_snk_out_2arr(i)(1),
- src_out => dp_concat_snk_in_2arr(i)(1),
-
- reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
- reg_slv_miso => reg_hdr_dat_miso_arr(i)
- );
+ generic map (
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
+ g_field_sel => g_hdr_field_sel,
+ g_snk_data_w => c_dp_field_blk_snk_data_w,
+ g_src_data_w => c_dp_field_blk_src_data_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ snk_in => dp_field_blk_snk_in_arr(i),
+ snk_out => dp_field_blk_snk_out_arr(i),
+
+ src_in => dp_concat_snk_out_2arr(i)(1),
+ src_out => dp_concat_snk_in_2arr(i)(1),
+
+ reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
+ reg_slv_miso => reg_hdr_dat_miso_arr(i)
+ );
end generate;
gen_dp_concat : for i in 0 to g_nof_streams - 1 generate
u_dp_concat : entity work.dp_concat
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_concat_snk_out_2arr(i),
- snk_in_arr => dp_concat_snk_in_2arr(i),
-
- src_in => src_in_arr(i),
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_concat_snk_out_2arr(i),
+ snk_in_arr => dp_concat_snk_in_2arr(i),
+
+ src_in => src_in_arr(i),
+ src_out => src_out_arr(i)
+ );
end generate;
---------------------------------------------------------------------------------------
-- MM control & monitoring
---------------------------------------------------------------------------------------
u_common_mem_mux_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
index b3101b542d..e7c68a8289 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, work;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_offload_tx_legacy is
generic (
@@ -113,24 +113,24 @@ architecture str of dp_offload_tx_legacy is
signal ram_hdr_insert_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
begin
u_common_mem_mux_hdr_reg : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_hdr_insert_reg_addr_w
- )
- port map (
- mosi => reg_hdr_insert_mosi,
- mosi_arr => reg_hdr_insert_mosi_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_hdr_insert_reg_addr_w
+ )
+ port map (
+ mosi => reg_hdr_insert_mosi,
+ mosi_arr => reg_hdr_insert_mosi_arr
+ );
u_common_mem_mux_hdr_ram : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_hdr_insert_ram_addr_w
- )
- port map (
- mosi => ram_hdr_insert_mosi,
- mosi_arr => ram_hdr_insert_mosi_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_hdr_insert_ram_addr_w
+ )
+ port map (
+ mosi => ram_hdr_insert_mosi,
+ mosi_arr => ram_hdr_insert_mosi_arr
+ );
gen_nof_streams0: for i in 0 to g_nof_streams - 1 generate
---------------------------------------------------------------------------------------
@@ -154,30 +154,30 @@ begin
---------------------------------------------------------------------------------------
gen_input_buffer : if g_use_input_fifo = true generate
u_buf : entity work.dp_fifo_sc
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => g_input_fifo_bsn_w,
- g_empty_w => g_input_fifo_empty_w,
- g_channel_w => g_input_fifo_channel_w,
- g_error_w => g_input_fifo_error_w,
- g_use_bsn => g_input_fifo_use_bsn,
- g_use_empty => g_input_fifo_use_empty,
- g_use_channel => g_input_fifo_use_channel,
- g_use_error => g_input_fifo_use_error,
- g_use_sync => g_input_fifo_use_sync,
- g_use_ctrl => true,
- g_fifo_size => 10 -- Use 10 as there's a FIFO margin
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- snk_out => dp_siso_arr(i),
- snk_in => dp_sel_sosi_arr(i),
-
- src_in => dp_to_split_siso_arr(i),
- src_out => dp_to_split_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => g_input_fifo_bsn_w,
+ g_empty_w => g_input_fifo_empty_w,
+ g_channel_w => g_input_fifo_channel_w,
+ g_error_w => g_input_fifo_error_w,
+ g_use_bsn => g_input_fifo_use_bsn,
+ g_use_empty => g_input_fifo_use_empty,
+ g_use_channel => g_input_fifo_use_channel,
+ g_use_error => g_input_fifo_use_error,
+ g_use_sync => g_input_fifo_use_sync,
+ g_use_ctrl => true,
+ g_fifo_size => 10 -- Use 10 as there's a FIFO margin
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => dp_siso_arr(i),
+ snk_in => dp_sel_sosi_arr(i),
+
+ src_in => dp_to_split_siso_arr(i),
+ src_out => dp_to_split_sosi_arr(i)
+ );
end generate;
end generate;
@@ -186,28 +186,28 @@ begin
-- Throw away words 0..g_block_nof_sel_words-1 of block (0..g_block_size-1)
---------------------------------------------------------------------------------------
u_mms_dp_split : entity work.mms_dp_split
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_symbol_w => g_data_w,
- g_nof_symbols_max => g_block_nof_sel_words * (g_data_w / c_byte_w)
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- snk_out_arr => dp_to_split_siso_arr,
- snk_in_arr => dp_to_split_sosi_arr,
-
- src_in_2arr => dp_from_split_siso_2arr,
- src_out_2arr => dp_from_split_sosi_2arr,
-
- reg_mosi => reg_dp_split_mosi,
- reg_miso => reg_dp_split_miso
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_symbol_w => g_data_w,
+ g_nof_symbols_max => g_block_nof_sel_words * (g_data_w / c_byte_w)
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ snk_out_arr => dp_to_split_siso_arr,
+ snk_in_arr => dp_to_split_sosi_arr,
+
+ src_in_2arr => dp_from_split_siso_2arr,
+ src_out_2arr => dp_from_split_sosi_2arr,
+
+ reg_mosi => reg_dp_split_mosi,
+ reg_miso => reg_dp_split_miso
+ );
gen_nof_streams1: for i in 0 to g_nof_streams - 1 generate
dp_from_split_siso_2arr(i)(0) <= c_dp_siso_rdy;
@@ -220,30 +220,30 @@ begin
---------------------------------------------------------------------------------------
gen_input_fifo : if g_use_input_fifo = true generate
u_input_fifo : entity work.dp_fifo_sc
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => g_input_fifo_bsn_w,
- g_empty_w => g_input_fifo_empty_w,
- g_channel_w => g_input_fifo_channel_w,
- g_error_w => g_input_fifo_error_w,
- g_use_bsn => g_input_fifo_use_bsn,
- g_use_empty => g_input_fifo_use_empty,
- g_use_channel => g_input_fifo_use_channel,
- g_use_error => g_input_fifo_use_error,
- g_use_sync => g_input_fifo_use_sync,
- g_use_ctrl => true,
- g_fifo_size => c_input_fifo_size
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- snk_out => dp_from_split_siso_2arr(i)(1),
- snk_in => dp_from_split_sosi_2arr(i)(1),
-
- src_in => dp_to_pkt_merge_siso_arr(i),
- src_out => dp_to_pkt_merge_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => g_input_fifo_bsn_w,
+ g_empty_w => g_input_fifo_empty_w,
+ g_channel_w => g_input_fifo_channel_w,
+ g_error_w => g_input_fifo_error_w,
+ g_use_bsn => g_input_fifo_use_bsn,
+ g_use_empty => g_input_fifo_use_empty,
+ g_use_channel => g_input_fifo_use_channel,
+ g_use_error => g_input_fifo_use_error,
+ g_use_sync => g_input_fifo_use_sync,
+ g_use_ctrl => true,
+ g_fifo_size => c_input_fifo_size
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => dp_from_split_siso_2arr(i)(1),
+ snk_in => dp_from_split_sosi_2arr(i)(1),
+
+ src_in => dp_to_pkt_merge_siso_arr(i),
+ src_out => dp_to_pkt_merge_sosi_arr(i)
+ );
end generate;
no_input_fifo : if g_use_input_fifo = false generate
@@ -259,102 +259,102 @@ begin
-- G_nof_pkt packets are merged into 1.
---------------------------------------------------------------------------------------
u_dp_packet_merge : entity work.mms_dp_packet_merge
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_pkt => g_nof_words_per_pkt -- Support merging 360*1 word
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_pkt => g_nof_words_per_pkt -- Support merging 360*1 word
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- dp_rst => st_rst,
- dp_clk => st_clk,
+ dp_rst => st_rst,
+ dp_clk => st_clk,
- snk_out_arr => dp_to_pkt_merge_siso_arr,
- snk_in_arr => dp_to_pkt_merge_sosi_arr,
+ snk_out_arr => dp_to_pkt_merge_siso_arr,
+ snk_in_arr => dp_to_pkt_merge_sosi_arr,
- src_in_arr => dp_merged_siso_arr,
- src_out_arr => dp_merged_sosi_arr,
+ src_in_arr => dp_merged_siso_arr,
+ src_out_arr => dp_merged_sosi_arr,
- reg_mosi => reg_dp_pkt_merge_mosi,
- reg_miso => reg_dp_pkt_merge_miso
- );
+ reg_mosi => reg_dp_pkt_merge_mosi,
+ reg_miso => reg_dp_pkt_merge_miso
+ );
gen_nof_streams3: for i in 0 to g_nof_streams - 1 generate
---------------------------------------------------------------------------------------
-- Convert DP to packetized DP
---------------------------------------------------------------------------------------
u_dp_packet_enc : entity work.dp_packet_enc
- generic map (
- g_data_w => g_data_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
+ generic map (
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
- snk_out => dp_merged_siso_arr(i),
- snk_in => dp_merged_sosi_arr(i),
+ snk_out => dp_merged_siso_arr(i),
+ snk_in => dp_merged_sosi_arr(i),
- src_in => udp_tx_pkt_siso_arr(i),
- src_out => udp_tx_pkt_sosi_arr(i)
- );
+ src_in => udp_tx_pkt_siso_arr(i),
+ src_out => udp_tx_pkt_sosi_arr(i)
+ );
---------------------------------------------------------------------------------------
-- Add header to DP packet
---------------------------------------------------------------------------------------
u_hdr_insert : entity work.dp_hdr_insert
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => c_byte_w,
- g_hdr_nof_words => g_hdr_nof_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_nof_words => g_hdr_nof_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- reg_mosi => reg_hdr_insert_mosi_arr(i),
- ram_mosi => ram_hdr_insert_mosi_arr(i),
+ reg_mosi => reg_hdr_insert_mosi_arr(i),
+ ram_mosi => ram_hdr_insert_mosi_arr(i),
- snk_out => udp_tx_pkt_siso_arr(i),
- snk_in => udp_tx_pkt_sosi_arr(i),
+ snk_out => udp_tx_pkt_siso_arr(i),
+ snk_in => udp_tx_pkt_sosi_arr(i),
- src_in => udp_tx_hdr_pkt_siso_arr(i),
- src_out => udp_tx_hdr_pkt_sosi_arr(i)
- );
+ src_in => udp_tx_hdr_pkt_siso_arr(i),
+ src_out => udp_tx_hdr_pkt_sosi_arr(i)
+ );
---------------------------------------------------------------------------------------
-- FIFO so we can deliver packets to the ETH module fast enough
---------------------------------------------------------------------------------------
gen_output_fifo: if g_use_output_fifo = true generate
u_dp_fifo_fill : entity work.dp_fifo_fill
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => 0,
- g_empty_w => 0,
- g_channel_w => 0,
- g_error_w => 0,
- g_use_bsn => false, -- Don't forward these as all have been encoded by dp_packet_enc
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_sync => false,
- g_fifo_fill => c_output_fifo_fill, -- Release packet only when available
- g_fifo_size => c_output_fifo_size,
- g_fifo_rl => 1
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- snk_out => udp_tx_hdr_pkt_siso_arr(i),
- snk_in => udp_tx_hdr_pkt_sosi_arr(i),
-
- src_in => udp_tx_hdr_pkt_fifo_siso_arr(i),
- src_out => udp_tx_hdr_pkt_fifo_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => 0,
+ g_empty_w => 0,
+ g_channel_w => 0,
+ g_error_w => 0,
+ g_use_bsn => false, -- Don't forward these as all have been encoded by dp_packet_enc
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_sync => false,
+ g_fifo_fill => c_output_fifo_fill, -- Release packet only when available
+ g_fifo_size => c_output_fifo_size,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => udp_tx_hdr_pkt_siso_arr(i),
+ snk_in => udp_tx_hdr_pkt_sosi_arr(i),
+
+ src_in => udp_tx_hdr_pkt_fifo_siso_arr(i),
+ src_out => udp_tx_hdr_pkt_fifo_sosi_arr(i)
+ );
udp_tx_hdr_pkt_fifo_siso_arr(i) <= tx_siso_arr(i);
tx_sosi_arr(i) <= udp_tx_hdr_pkt_fifo_sosi_arr(i);
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
index e95ac25810..80f8fdbdc0 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
@@ -20,22 +20,22 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
-
--- Purpose:
--- . Calculate UDP total length and IP total length fields
--- Description:
--- . The length fields are calculated based on the status outputs
--- of dp_split and dp_packet_merge:
--- . udp_total_length = c_udp_header_len + nof_data_bytes + c_user_hdr_len
--- . c_udp_header_len = 8 (fixed) bytes
--- . nof_data_bytes = nof_words_per_block * nof_blocks_per_packet * 4 bytes
--- . c_user_hdr_len = nof bytes in remaining header
--- . ip_total_length = udp_total_length - c_ip_header_len
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
+
+ -- Purpose:
+ -- . Calculate UDP total length and IP total length fields
+ -- Description:
+ -- . The length fields are calculated based on the status outputs
+ -- of dp_split and dp_packet_merge:
+ -- . udp_total_length = c_udp_header_len + nof_data_bytes + c_user_hdr_len
+ -- . c_udp_header_len = 8 (fixed) bytes
+ -- . nof_data_bytes = nof_words_per_block * nof_blocks_per_packet * 4 bytes
+ -- . c_user_hdr_len = nof bytes in remaining header
+ -- . ip_total_length = udp_total_length - c_ip_header_len
entity dp_offload_tx_len_calc is
generic (
@@ -82,25 +82,25 @@ begin
-- Calculate number of payload words
---------------------------------------------------------------------------------------
u_common_mult: entity common_mult_lib.common_mult
- generic map (
- g_technology => g_technology,
- g_variant => "RTL",
- g_in_a_w => nof_words_per_block'LENGTH,
- g_in_b_w => nof_blocks_per_packet'LENGTH,
- g_out_p_w => c_product_w,
- g_pipeline_input => 0,
- g_pipeline_product => 0,
- g_pipeline_output => 0,
- g_representation => "UNSIGNED"
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_a => nof_words_per_block,
- in_b => nof_blocks_per_packet,
- out_p => nof_data_words
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "RTL",
+ g_in_a_w => nof_words_per_block'LENGTH,
+ g_in_b_w => nof_blocks_per_packet'LENGTH,
+ g_out_p_w => c_product_w,
+ g_pipeline_input => 0,
+ g_pipeline_product => 0,
+ g_pipeline_output => 0,
+ g_representation => "UNSIGNED"
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_a => nof_words_per_block,
+ in_b => nof_blocks_per_packet,
+ out_p => nof_data_words
+ );
---------------------------------------------------------------------------------------
-- Calculate number of payload bytes by bit shifting to the left
@@ -113,18 +113,18 @@ begin
udp_adder_in <= RESIZE_UVEC(nof_data_bytes, c_adder_in_w) & TO_UVEC(c_udp_header_len, c_adder_in_w) & TO_UVEC(c_user_hdr_len, c_adder_in_w);
u_common_adder_tree_udp : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => 0,
- g_nof_inputs => 3,
- g_dat_w => c_adder_in_w,
- g_sum_w => c_adder_in_w + 2
- )
- port map (
- clk => clk,
- in_dat => udp_adder_in,
- sum => udp_adder_out
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => 0,
+ g_nof_inputs => 3,
+ g_dat_w => c_adder_in_w,
+ g_sum_w => c_adder_in_w + 2
+ )
+ port map (
+ clk => clk,
+ in_dat => udp_adder_in,
+ sum => udp_adder_out
+ );
udp_total_length <= udp_adder_out(c_adder_in_w - 1 downto 0);
@@ -134,18 +134,18 @@ begin
ip_adder_in <= RESIZE_UVEC(udp_adder_out, c_adder_in_w) & TO_UVEC(c_ip_header_len, c_adder_in_w);
u_common_adder_tree_ip : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => 0,
- g_nof_inputs => 2,
- g_dat_w => c_adder_in_w,
- g_sum_w => c_adder_in_w + 1
- )
- port map (
- clk => clk,
- in_dat => ip_adder_in,
- sum => ip_adder_out
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => 0,
+ g_nof_inputs => 2,
+ g_dat_w => c_adder_in_w,
+ g_sum_w => c_adder_in_w + 1
+ )
+ port map (
+ clk => clk,
+ in_dat => ip_adder_in,
+ sum => ip_adder_out
+ );
ip_total_length <= ip_adder_out(c_adder_in_w - 1 downto 0);
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
index 9382254dc5..161d7bb3f5 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
@@ -40,13 +40,13 @@
-- bits in the header and data are an integer number of g_data_w.
library IEEE, common_lib, technology_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_offload_tx_v3 is
generic (
@@ -151,50 +151,50 @@ begin
-- mm_fields for MM access to each field
---------------------------------------------------------------------------------------
u_mm_fields_slv: entity mm_lib.mm_fields
- generic map(
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW")
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW")
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_hdr_dat_mosi_arr(i),
- mm_miso => OPEN, -- Not used
+ mm_mosi => reg_hdr_dat_mosi_arr(i),
+ mm_miso => OPEN, -- Not used
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_slv_out_arr(i)(field_slv_len(g_hdr_field_arr) - 1 downto 0)
- );
+ slv_out => mm_fields_slv_out_arr(i)(field_slv_len(g_hdr_field_arr) - 1 downto 0)
+ );
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : entity work.dp_field_blk
- generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
- g_field_sel => g_hdr_field_sel,
- g_snk_data_w => c_dp_field_blk_snk_data_w,
- g_src_data_w => c_dp_field_blk_src_data_w,
- g_in_symbol_w => g_symbol_w,
- g_out_symbol_w => g_symbol_w,
- g_pipeline_ready => g_pipeline_ready,
- g_mode => 1 -- source mode
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- snk_in => dp_field_blk_snk_in_arr(i),
- snk_out => dp_field_blk_snk_out_arr(i),
-
- src_out => dp_field_blk_src_out_arr(i),
- src_in => dp_field_blk_src_in_arr(i),
-
- reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
- reg_slv_miso => reg_hdr_dat_miso_arr(i)
- );
+ generic map (
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
+ g_field_sel => g_hdr_field_sel,
+ g_snk_data_w => c_dp_field_blk_snk_data_w,
+ g_src_data_w => c_dp_field_blk_src_data_w,
+ g_in_symbol_w => g_symbol_w,
+ g_out_symbol_w => g_symbol_w,
+ g_pipeline_ready => g_pipeline_ready,
+ g_mode => 1 -- source mode
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ snk_in => dp_field_blk_snk_in_arr(i),
+ snk_out => dp_field_blk_snk_out_arr(i),
+
+ src_out => dp_field_blk_src_out_arr(i),
+ src_in => dp_field_blk_src_in_arr(i),
+
+ reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
+ reg_slv_miso => reg_hdr_dat_miso_arr(i)
+ );
dp_field_blk_src_in_arr(i) <= dp_concat_snk_out_2arr(i)(1);
end generate;
@@ -205,34 +205,34 @@ begin
dp_concat_snk_in_2arr(i)(1) <= dp_field_blk_src_out_arr(i);
u_dp_concat : entity work.dp_concat
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_concat_snk_out_2arr(i),
- snk_in_arr => dp_concat_snk_in_2arr(i),
-
- src_in => src_in_arr(i),
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_concat_snk_out_2arr(i),
+ snk_in_arr => dp_concat_snk_in_2arr(i),
+
+ src_in => src_in_arr(i),
+ src_out => src_out_arr(i)
+ );
end generate;
---------------------------------------------------------------------------------------
-- MM control & monitoring
---------------------------------------------------------------------------------------
u_common_mem_mux_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_dec.vhd b/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
index 6839ff8a6e..981b3fdb77 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
@@ -20,60 +20,60 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_packet_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_packet_pkg.all;
--- Purpose: Decode DP packet to DP sosi.
--- Description:
---
--- From an input DP packet:
---
--- ----------------------------------------------
--- |chan| bsn | data ... |err|
--- ----------------------------------------------
--- sop eop
--- val val val val ... val
--- err, when g_use_phy_err = TRUE
---
--- extract the block of output SOSI data:
---
--- -----------------------
--- | data ... |
--- -----------------------
--- sop eop
--- val val ... val
--- sync
--- bsn
--- channel
--- empty
--- err
---
--- The data length (eop) and empty do not show as fields in the packet
--- because they are implitely known per channel.
---
--- The dp_packet_enc does the reverse.
---
--- The g_channel_lo parameter allows using the LSbit channel fields to be
--- used for defining different groups of DP packet streams. This is e.g. used
--- to map these groups to corresponding 'tlen' types in case of transport
--- went by using UTH packets over a transceiver link.
---
--- Remark:
--- . This dp_packet_dec has a similar structure as uth_rx(rtl_hold) for the
--- flow control and as dp_packet_enc for the states. However dp_packet_dec
--- uses the sop and eop so it does not (need to) know the DP packet nof
--- data. Therefor it uses dp_shiftreg to adjust the output eop to the last
--- payload data instead of at the last err-field data.
--- . When the DP packet comes from a PHY link then it may have gotten corrupted
--- contents so then it is useful to set g_use_phy_err to TRUE. The PHY
--- error status is based on the received CRC and fits in 1 bit. The
--- g_phy_err_bi defines where the PHY error bit is put in src_out.err in
--- case g_use_phy_err = TRUE.
--- . The output SOSI sync is defined such that it can only be active at sop, so
--- not during entire frame or even until the next sop.
+ -- Purpose: Decode DP packet to DP sosi.
+ -- Description:
+ --
+ -- From an input DP packet:
+ --
+ -- ----------------------------------------------
+ -- |chan| bsn | data ... |err|
+ -- ----------------------------------------------
+ -- sop eop
+ -- val val val val ... val
+ -- err, when g_use_phy_err = TRUE
+ --
+ -- extract the block of output SOSI data:
+ --
+ -- -----------------------
+ -- | data ... |
+ -- -----------------------
+ -- sop eop
+ -- val val ... val
+ -- sync
+ -- bsn
+ -- channel
+ -- empty
+ -- err
+ --
+ -- The data length (eop) and empty do not show as fields in the packet
+ -- because they are implitely known per channel.
+ --
+ -- The dp_packet_enc does the reverse.
+ --
+ -- The g_channel_lo parameter allows using the LSbit channel fields to be
+ -- used for defining different groups of DP packet streams. This is e.g. used
+ -- to map these groups to corresponding 'tlen' types in case of transport
+ -- went by using UTH packets over a transceiver link.
+ --
+ -- Remark:
+ -- . This dp_packet_dec has a similar structure as uth_rx(rtl_hold) for the
+ -- flow control and as dp_packet_enc for the states. However dp_packet_dec
+ -- uses the sop and eop so it does not (need to) know the DP packet nof
+ -- data. Therefor it uses dp_shiftreg to adjust the output eop to the last
+ -- payload data instead of at the last err-field data.
+ -- . When the DP packet comes from a PHY link then it may have gotten corrupted
+ -- contents so then it is useful to set g_use_phy_err to TRUE. The PHY
+ -- error status is based on the received CRC and fits in 1 bit. The
+ -- g_phy_err_bi defines where the PHY error bit is put in src_out.err in
+ -- case g_use_phy_err = TRUE.
+ -- . The output SOSI sync is defined such that it can only be active at sop, so
+ -- not during entire frame or even until the next sop.
entity dp_packet_dec is
generic (
@@ -176,18 +176,18 @@ begin
nxt_src_buf <= next_src_buf;
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in,
- -- ST source
- src_in => hold_src_in,
- next_src_out => next_src_buf,
- pend_src_out => OPEN,
- src_out_reg => src_buf
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in,
+ -- ST source
+ src_in => hold_src_in,
+ next_src_out => next_src_buf,
+ pend_src_out => OPEN,
+ src_out_reg => src_buf
+ );
-- State machine
p_state : process(state, src_in, channel, bsn, cnt, blk_sosi, next_src_buf)
@@ -282,25 +282,25 @@ begin
-- Handle output error field and eop
u_src_shift : entity work.dp_shiftreg
- generic map (
- g_output_reg => c_output_reg,
- g_flush_eop => true,
- g_modify_support => true,
- g_nof_words => c_shiftreg_len
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => blk_sosi,
- -- Control shift register contents
- cur_shiftreg_inputs => cur_src_out_inputs,
- new_shiftreg_inputs => new_src_out_inputs,
- -- ST source
- src_in => src_in,
- src_out => i_src_out
- );
+ generic map (
+ g_output_reg => c_output_reg,
+ g_flush_eop => true,
+ g_modify_support => true,
+ g_nof_words => c_shiftreg_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => blk_sosi,
+ -- Control shift register contents
+ cur_shiftreg_inputs => cur_src_out_inputs,
+ new_shiftreg_inputs => new_src_out_inputs,
+ -- ST source
+ src_in => src_in,
+ src_out => i_src_out
+ );
p_src_err : process(cur_src_out_inputs)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd b/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
index 2fe927abf4..3717d1fd2b 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
@@ -20,22 +20,22 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose: Decode sosi.channel low bits from the high part of the CHAN field
--- of a DP packet.
--- Description:
--- The snk_in data must be DP packet data. The [high-1:high-g_channel_lo]
--- bits of the CHAN field get set to 0 and placed into the [g_channel_lo-1:0]
--- bits of the sosi.channel field. The [high] bit of the CHAN field is not
--- changed because it is reserved for future use.
--- Remark:
--- . See also dp_packet_enc_channel_lo.
--- . The dp_packet_dec_channel_lo.vhd is verified in tb_dp_distribute.vhd.
--- . The sosi.channel field must be valid during the entire frame, so not only
--- at the sop. Therefore it is necessary to use channel_lo_hold.
+ -- Purpose: Decode sosi.channel low bits from the high part of the CHAN field
+ -- of a DP packet.
+ -- Description:
+ -- The snk_in data must be DP packet data. The [high-1:high-g_channel_lo]
+ -- bits of the CHAN field get set to 0 and placed into the [g_channel_lo-1:0]
+ -- bits of the sosi.channel field. The [high] bit of the CHAN field is not
+ -- changed because it is reserved for future use.
+ -- Remark:
+ -- . See also dp_packet_enc_channel_lo.
+ -- . The dp_packet_dec_channel_lo.vhd is verified in tb_dp_distribute.vhd.
+ -- . The sosi.channel field must be valid during the entire frame, so not only
+ -- at the sop. Therefore it is necessary to use channel_lo_hold.
entity dp_packet_dec_channel_lo is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_packet_detect.vhd b/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
index 0801177252..b9d5c55160 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
@@ -20,23 +20,23 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose:
--- Assert output during a packet on the input:
---
--- ___ _________ ___
--- val ______| |___| |___| |____
--- ___
--- sop ______| |__________________________
--- ___
--- eop ____________________________| |____
---
--- _________________________
--- pkt_det ______| |____
+ -- Purpose:
+ -- Assert output during a packet on the input:
+ --
+ -- ___ _________ ___
+ -- val ______| |___| |___| |____
+ -- ___
+ -- sop ______| |__________________________
+ -- ___
+ -- eop ____________________________| |____
+ --
+ -- _________________________
+ -- pkt_det ______| |____
entity dp_packet_detect is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_packet_enc.vhd b/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
index 489bdc80ec..7a702aa12f 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
@@ -20,56 +20,56 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_packet_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_packet_pkg.all;
--- Purpose: Encode DP sosi to DP packet.
--- Description:
---
--- Pass on the block of input SOSI data:
---
--- -----------------------
--- | data ... |
--- -----------------------
--- sop eop
--- val val ... val
--- sync sync ... sync
--- bsn
--- channel
--- empty
--- err
---
--- into an output DP packet:
---
--- ----------------------------------------------
--- |chan| bsn | data ... |err|
--- ----------------------------------------------
--- sop eop
--- val val val val ... val
--- channel_lo
--- sync
---
--- The data length (eop) and empty do not show as fields in the packet
--- because they are implitely known per channel.
---
--- The dp_packet_dec does the reverse.
---
--- The g_channel_lo parameter allows using the LSbit channel fields to be
--- used for defining different groups of DP packet streams. This is e.g. used
--- to map these groups to corresponding 'tlen' types in case of further
--- transport using UTH packets over a transceiver link.
---
--- Remark:
--- . This dp_packet_enc has a similar structure as uth_tx(rtl_hold).
--- . The snk_in.sync is encoded into the frame BSN field but also always passed
--- on via the src_out.sync field. The g_blk_sync determines how the sync is
--- passed on. Use the default g_blk_sync is FALSE for DP style, because then
--- the src_out.sync does not need to be AND-ed with the src_out.sop when it
--- is used to trigger an event. When g_blk_sync is TRUE then the sync is kept
--- until the sop of the next input frame. This is useful to mimic the LOFAR
--- style sync whereby the sync preceeds the sop.
+ -- Purpose: Encode DP sosi to DP packet.
+ -- Description:
+ --
+ -- Pass on the block of input SOSI data:
+ --
+ -- -----------------------
+ -- | data ... |
+ -- -----------------------
+ -- sop eop
+ -- val val ... val
+ -- sync sync ... sync
+ -- bsn
+ -- channel
+ -- empty
+ -- err
+ --
+ -- into an output DP packet:
+ --
+ -- ----------------------------------------------
+ -- |chan| bsn | data ... |err|
+ -- ----------------------------------------------
+ -- sop eop
+ -- val val val val ... val
+ -- channel_lo
+ -- sync
+ --
+ -- The data length (eop) and empty do not show as fields in the packet
+ -- because they are implitely known per channel.
+ --
+ -- The dp_packet_dec does the reverse.
+ --
+ -- The g_channel_lo parameter allows using the LSbit channel fields to be
+ -- used for defining different groups of DP packet streams. This is e.g. used
+ -- to map these groups to corresponding 'tlen' types in case of further
+ -- transport using UTH packets over a transceiver link.
+ --
+ -- Remark:
+ -- . This dp_packet_enc has a similar structure as uth_tx(rtl_hold).
+ -- . The snk_in.sync is encoded into the frame BSN field but also always passed
+ -- on via the src_out.sync field. The g_blk_sync determines how the sync is
+ -- passed on. Use the default g_blk_sync is FALSE for DP style, because then
+ -- the src_out.sync does not need to be AND-ed with the src_out.sop when it
+ -- is used to trigger an event. When g_blk_sync is TRUE then the sync is kept
+ -- until the sop of the next input frame. This is useful to mimic the LOFAR
+ -- style sync whereby the sync preceeds the sop.
entity dp_packet_enc is
generic (
@@ -151,18 +151,18 @@ begin
nxt_src_buf <= next_src_buf;
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in,
- -- ST source
- src_in => hold_src_in,
- next_src_out => next_src_buf,
- pend_src_out => pend_src_buf,
- src_out_reg => src_buf
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in,
+ -- ST source
+ src_in => hold_src_in,
+ next_src_out => next_src_buf,
+ pend_src_out => pend_src_buf,
+ src_out_reg => src_buf
+ );
-- State machine
p_state : process(state, cnt, src_in, pend_src_buf, i_src_out, in_err)
diff --git a/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd b/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
index 9ce09443d7..f739d05aeb 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
@@ -20,33 +20,33 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose: Encode sosi.channel low bit into the high part of the CHAN field of
--- a DP packet.
--- Description:
--- The snk_in data must be DP packet data. The [g_channel_lo-1:0] bits of the
--- sosi.channel field get placed into the [high-1:high-g_channel_lo] bits
--- of the CHAN field. The [high] bit of the CHAN field is not used because it
--- is reserved for future use.
--- Remark:
--- . The dp_packet_enc_channel_lo.vhd is verified in tb_dp_distribute.vhd.
--- . The DP packet CHAN field occurs at the sop. By placing the channel_lo bits
--- in the high part of the CHAN field this dp_packet_enc_channel_lo can
--- combinatorially modifiy the CHAN data at the sop. For small g_data_w the
--- CHAN field can cover multiple data words, therefore using the low part of
--- the CHAN field would imply shifting in the g_channel_lo bits and would
--- require more logic including registers to modify the entire CHAN field.
--- . The snk_in channel is passed on unmodified to the src_out.channel, because
--- DP packets typically do not use the channel field, so the g_channel_lo
--- bits are the only valid bits in the channel field and therefore they may
--- as wel remain, rather then being shifted out.
--- . Pre-conditions:
--- - g_channel_lo+1 <= g_data_w
--- - g_channel_lo+1 <= c_dp_packet_channel_w = 16
--- - g_channel_lo+1 <= c_dp_packet_channel_w - currently used CHAN width
+ -- Purpose: Encode sosi.channel low bit into the high part of the CHAN field of
+ -- a DP packet.
+ -- Description:
+ -- The snk_in data must be DP packet data. The [g_channel_lo-1:0] bits of the
+ -- sosi.channel field get placed into the [high-1:high-g_channel_lo] bits
+ -- of the CHAN field. The [high] bit of the CHAN field is not used because it
+ -- is reserved for future use.
+ -- Remark:
+ -- . The dp_packet_enc_channel_lo.vhd is verified in tb_dp_distribute.vhd.
+ -- . The DP packet CHAN field occurs at the sop. By placing the channel_lo bits
+ -- in the high part of the CHAN field this dp_packet_enc_channel_lo can
+ -- combinatorially modifiy the CHAN data at the sop. For small g_data_w the
+ -- CHAN field can cover multiple data words, therefore using the low part of
+ -- the CHAN field would imply shifting in the g_channel_lo bits and would
+ -- require more logic including registers to modify the entire CHAN field.
+ -- . The snk_in channel is passed on unmodified to the src_out.channel, because
+ -- DP packets typically do not use the channel field, so the g_channel_lo
+ -- bits are the only valid bits in the channel field and therefore they may
+ -- as wel remain, rather then being shifted out.
+ -- . Pre-conditions:
+ -- - g_channel_lo+1 <= g_data_w
+ -- - g_channel_lo+1 <= c_dp_packet_channel_w = 16
+ -- - g_channel_lo+1 <= c_dp_packet_channel_w - currently used CHAN width
entity dp_packet_enc_channel_lo is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
index 78269fecf9..942485bedd 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
@@ -178,10 +178,10 @@
-- through dp_pipeline to register it and to add the flow control.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_packet_merge is
generic (
@@ -241,20 +241,20 @@ begin
dp_latency_adapter_snk_in <= r.src_out;
u_dp_latency_adapter : entity work.dp_latency_adapter
- generic map (
- g_in_latency => 2,
- g_out_latency => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => dp_latency_adapter_snk_out,
- snk_in => dp_latency_adapter_snk_in,
- -- ST source
- src_in => dp_latency_adapter_src_in,
- src_out => dp_latency_adapter_src_out
- );
+ generic map (
+ g_in_latency => 2,
+ g_out_latency => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => dp_latency_adapter_snk_out,
+ snk_in => dp_latency_adapter_snk_in,
+ -- ST source
+ src_in => dp_latency_adapter_src_in,
+ src_out => dp_latency_adapter_src_out
+ );
dp_latency_adapter_src_in <= src_in;
src_out <= dp_latency_adapter_src_out;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd b/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
index 76c65b3a90..fddb364b95 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
@@ -20,8 +20,8 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package dp_packet_pkg is
------------------------------------------------------------------------------
@@ -60,8 +60,8 @@ package body dp_packet_pkg is
begin
-- Calculate the total DP PACKET overhead length of header (channel and bsn words) + lenght of tail (error words).
return ceil_div(c_dp_packet_channel_w, c_data_w) +
- ceil_div(c_dp_packet_bsn_w, c_data_w) +
- ceil_div(c_dp_packet_error_w, c_data_w);
+ ceil_div(c_dp_packet_bsn_w, c_data_w) +
+ ceil_div(c_dp_packet_error_w, c_data_w);
end;
end dp_packet_pkg;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd b/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
index 1fe7ebd08f..729b6ea5a3 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
@@ -32,10 +32,10 @@
-- src_out.eop _____________|0|_______|1|_______|2|_______|0|_______|1|_______|2|___
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_packet_unmerge is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd b/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
index cbc94af722..9600780376 100644
--- a/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
@@ -20,38 +20,38 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, easics_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-
-use easics_lib.RAD_CRC16_D16.all;
-use easics_lib.RAD_CRC18_D18.all;
-use easics_lib.RAD_CRC20_D20.all;
-
-use easics_lib.PCK_CRC16_D4.all;
-use easics_lib.PCK_CRC16_D8.all;
-use easics_lib.PCK_CRC16_D9.all;
-use easics_lib.PCK_CRC16_D10.all;
-use easics_lib.PCK_CRC16_D16.all;
-use easics_lib.PCK_CRC16_D18.all;
-use easics_lib.PCK_CRC16_D20.all;
-use easics_lib.PCK_CRC16_D32.all;
-use easics_lib.PCK_CRC16_D36.all;
-use easics_lib.PCK_CRC16_D48.all;
-use easics_lib.PCK_CRC16_D64.all;
-use easics_lib.PCK_CRC16_D72.all;
-
-use easics_lib.PCK_CRC32_D4.all;
-use easics_lib.PCK_CRC32_D8.all;
-use easics_lib.PCK_CRC32_D9.all;
-use easics_lib.PCK_CRC32_D10.all;
-use easics_lib.PCK_CRC32_D16.all;
-use easics_lib.PCK_CRC32_D18.all;
-use easics_lib.PCK_CRC32_D20.all;
-use easics_lib.PCK_CRC32_D32.all;
-use easics_lib.PCK_CRC32_D36.all;
-use easics_lib.PCK_CRC32_D48.all;
-use easics_lib.PCK_CRC32_D64.all;
-use easics_lib.PCK_CRC32_D72.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+
+ use easics_lib.RAD_CRC16_D16.all;
+ use easics_lib.RAD_CRC18_D18.all;
+ use easics_lib.RAD_CRC20_D20.all;
+
+ use easics_lib.PCK_CRC16_D4.all;
+ use easics_lib.PCK_CRC16_D8.all;
+ use easics_lib.PCK_CRC16_D9.all;
+ use easics_lib.PCK_CRC16_D10.all;
+ use easics_lib.PCK_CRC16_D16.all;
+ use easics_lib.PCK_CRC16_D18.all;
+ use easics_lib.PCK_CRC16_D20.all;
+ use easics_lib.PCK_CRC16_D32.all;
+ use easics_lib.PCK_CRC16_D36.all;
+ use easics_lib.PCK_CRC16_D48.all;
+ use easics_lib.PCK_CRC16_D64.all;
+ use easics_lib.PCK_CRC16_D72.all;
+
+ use easics_lib.PCK_CRC32_D4.all;
+ use easics_lib.PCK_CRC32_D8.all;
+ use easics_lib.PCK_CRC32_D9.all;
+ use easics_lib.PCK_CRC32_D10.all;
+ use easics_lib.PCK_CRC32_D16.all;
+ use easics_lib.PCK_CRC32_D18.all;
+ use easics_lib.PCK_CRC32_D20.all;
+ use easics_lib.PCK_CRC32_D32.all;
+ use easics_lib.PCK_CRC32_D36.all;
+ use easics_lib.PCK_CRC32_D48.all;
+ use easics_lib.PCK_CRC32_D64.all;
+ use easics_lib.PCK_CRC32_D72.all;
package dp_packetizing_pkg is
--<types>--
diff --git a/libraries/base/dp/src/vhdl/dp_pad_insert.vhd b/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
index 7a0fe1975a..92b576baa1 100644
--- a/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
@@ -20,25 +20,25 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose:
--- Prepend one word with empty symbols at the head of a frame
--- Description:
--- This function is typically used to change the word boundary in a frame by
--- inserting g_nof_padding symbols at the head of the frame.
--- E.g. the total ethernet header is 42 octets and then followed by the
--- payload. This dp_pad_insert can insert 2 or 6 octets in front of the
--- header to make it 48 octets and hence make the payload start at a 32 or
--- 64 bit word boundary respectively.
--- Remark:
--- . Ready latency (RL) = 1
--- . The padding preserves the sync and BSN from the snk_in.
--- . Reverse operation is dp_pad_remove, which is merely dp_split.
--- . This dp_pad_insert now can only insert 1 word at the head, this could be
--- extended to allow also g_nof_padding > g_data_w/g_symbol_w
+ -- Purpose:
+ -- Prepend one word with empty symbols at the head of a frame
+ -- Description:
+ -- This function is typically used to change the word boundary in a frame by
+ -- inserting g_nof_padding symbols at the head of the frame.
+ -- E.g. the total ethernet header is 42 octets and then followed by the
+ -- payload. This dp_pad_insert can insert 2 or 6 octets in front of the
+ -- header to make it 48 octets and hence make the payload start at a 32 or
+ -- 64 bit word boundary respectively.
+ -- Remark:
+ -- . Ready latency (RL) = 1
+ -- . The padding preserves the sync and BSN from the snk_in.
+ -- . Reverse operation is dp_pad_remove, which is merely dp_split.
+ -- . This dp_pad_insert now can only insert 1 word at the head, this could be
+ -- extended to allow also g_nof_padding > g_data_w/g_symbol_w
entity dp_pad_insert is
generic (
@@ -105,18 +105,18 @@ begin
end process;
u_hold_snk_in : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => in_siso,
- next_src_out => next_in_sosi,
- pend_src_out => pend_in_sosi,
- src_out_reg => in_sosi
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => in_siso,
+ next_src_out => next_in_sosi,
+ pend_src_out => pend_in_sosi,
+ src_out_reg => in_sosi
+ );
-- Prepend the padding octets to snk_in
pad_siso <= concat_siso_arr(0);
@@ -125,20 +125,20 @@ begin
concat_sosi_arr(1) <= in_sosi; -- = tail frame with in_sosi eop info
u_concat : entity work.dp_concat -- RL = 1
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => concat_siso_arr,
- snk_in_arr => concat_sosi_arr,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => concat_siso_arr,
+ snk_in_arr => concat_sosi_arr,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
gen_bypass : if g_internal_bypass = true generate
diff --git a/libraries/base/dp/src/vhdl/dp_pad_remove.vhd b/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
index 134fc740ef..ef4c16be91 100644
--- a/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
@@ -20,18 +20,18 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose:
--- Remove padding octects from the head of a padded frame
--- Description:
--- This dp_pad_remove merely uses dp_split. It throws away the head and it
--- passes on the tail.
--- Remark:
--- . Ready latency (RL) = 1
--- . Reverse operation is dp_pad_insert
+ -- Purpose:
+ -- Remove padding octects from the head of a padded frame
+ -- Description:
+ -- This dp_pad_remove merely uses dp_split. It throws away the head and it
+ -- passes on the tail.
+ -- Remark:
+ -- . Ready latency (RL) = 1
+ -- . Reverse operation is dp_pad_insert
entity dp_pad_remove is
generic (
@@ -65,21 +65,21 @@ begin
src_out <= split_sosi_arr(1);
u_split : entity work.dp_split -- RL = 1
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => g_nof_padding
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in_arr => split_siso_arr,
- src_out_arr => split_sosi_arr
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => g_nof_padding
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in_arr => split_siso_arr,
+ src_out_arr => split_sosi_arr
+ );
end generate;
gen_bypass : if g_internal_bypass = true generate
diff --git a/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd b/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
index a2b024710c..2dde43ee21 100644
--- a/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
@@ -40,10 +40,10 @@
-- - dp_block_gen_valid_arr
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_paged_sop_eop_reg is
generic (
@@ -71,68 +71,68 @@ begin
src_out.sync <= src_out_sync(0); -- convert slv to sl
u_paged_sync : entity common_lib.common_paged_reg
- generic map (
- g_data_w => 1,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => sop_wr_en,
- wr_dat => snk_in_sync,
- out_dat => src_out_sync
- );
+ generic map (
+ g_data_w => 1,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => sop_wr_en,
+ wr_dat => snk_in_sync,
+ out_dat => src_out_sync
+ );
u_paged_bsn : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_bsn_w,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => sop_wr_en,
- wr_dat => snk_in.bsn,
- out_dat => src_out.bsn
- );
+ generic map (
+ g_data_w => c_dp_stream_bsn_w,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => sop_wr_en,
+ wr_dat => snk_in.bsn,
+ out_dat => src_out.bsn
+ );
u_paged_channel : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_channel_w,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => sop_wr_en,
- wr_dat => snk_in.channel,
- out_dat => src_out.channel
- );
+ generic map (
+ g_data_w => c_dp_stream_channel_w,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => sop_wr_en,
+ wr_dat => snk_in.channel,
+ out_dat => src_out.channel
+ );
-- Sosi info at eop
u_paged_empty : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_empty_w,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => eop_wr_en,
- wr_dat => snk_in.empty,
- out_dat => src_out.empty
- );
+ generic map (
+ g_data_w => c_dp_stream_empty_w,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => eop_wr_en,
+ wr_dat => snk_in.empty,
+ out_dat => src_out.empty
+ );
u_paged_err : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_error_w,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => eop_wr_en,
- wr_dat => snk_in.err,
- out_dat => src_out.err
- );
+ generic map (
+ g_data_w => c_dp_stream_error_w,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => eop_wr_en,
+ wr_dat => snk_in.err,
+ out_dat => src_out.err
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline.vhd b/libraries/base/dp/src/vhdl/dp_pipeline.vhd
index 63f860246c..1e029a9912 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline.vhd
@@ -21,28 +21,28 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
--- Purpose:
--- Pipeline the source output by one cycle or by g_pipeline cycles.
--- Description:
--- The dp_pipeline instantiates 0:g_pipeline stages of dp_pipeline_one.
--- The dp_pipeline_one provides a single clock cycle delay of the source
--- output (i.e. sosi). The dp_pipeline_one holds valid sink input in case
--- src_in.ready goes low and makes src_out.valid high again when
--- src_in.ready goes high again, without the need for a valid sink input to
--- push this held data out.
--- The dp_pipeline delays the data, sop, eop by one cycle relative to the
--- valid. However the src_out.valid still has the same phase as the
--- snk_in.valid, because both valids depends on the same src_in.ready.
--- Therefore dp_pipeline cannot be used to delay the valid phase by one
--- cycle. Hence the may purpose of dp_pipeline is to register the sosi.
--- Remarks:
--- . Ready latency = 1
--- . Without flow control so when src_in.ready = '1' fixed, then the hold
--- logic in dp_pipeline becomes void and dp_pipeline then just pipelines the
--- snk_in sosi.
+ -- Purpose:
+ -- Pipeline the source output by one cycle or by g_pipeline cycles.
+ -- Description:
+ -- The dp_pipeline instantiates 0:g_pipeline stages of dp_pipeline_one.
+ -- The dp_pipeline_one provides a single clock cycle delay of the source
+ -- output (i.e. sosi). The dp_pipeline_one holds valid sink input in case
+ -- src_in.ready goes low and makes src_out.valid high again when
+ -- src_in.ready goes high again, without the need for a valid sink input to
+ -- push this held data out.
+ -- The dp_pipeline delays the data, sop, eop by one cycle relative to the
+ -- valid. However the src_out.valid still has the same phase as the
+ -- snk_in.valid, because both valids depends on the same src_in.ready.
+ -- Therefore dp_pipeline cannot be used to delay the valid phase by one
+ -- cycle. Hence the may purpose of dp_pipeline is to register the sosi.
+ -- Remarks:
+ -- . Ready latency = 1
+ -- . Without flow control so when src_in.ready = '1' fixed, then the hold
+ -- logic in dp_pipeline becomes void and dp_pipeline then just pipelines the
+ -- snk_in sosi.
entity dp_pipeline is
generic (
@@ -61,8 +61,8 @@ entity dp_pipeline is
end dp_pipeline;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
entity dp_pipeline_one is
port (
@@ -78,8 +78,8 @@ entity dp_pipeline_one is
end dp_pipeline_one;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture str of dp_pipeline is
signal snk_out_arr : t_dp_siso_arr(0 to g_pipeline);
@@ -95,23 +95,23 @@ begin
gen_p : for I in 1 to g_pipeline generate
u_p : entity work.dp_pipeline_one
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out_arr(I - 1),
- snk_in => snk_in_arr(I - 1),
- -- ST source
- src_in => snk_out_arr(I),
- src_out => snk_in_arr(I)
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out_arr(I - 1),
+ snk_in => snk_in_arr(I - 1),
+ -- ST source
+ src_in => snk_out_arr(I),
+ src_out => snk_in_arr(I)
+ );
end generate;
end str;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture str of dp_pipeline_one is
signal nxt_src_out : t_dp_sosi;
@@ -131,16 +131,16 @@ begin
-- Input control
u_hold_input : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- next_src_out => nxt_src_out,
- pend_src_out => OPEN,
- src_out_reg => i_src_out
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ next_src_out => nxt_src_out,
+ pend_src_out => OPEN,
+ src_out_reg => i_src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd b/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
index 57e45e045e..9172f05398 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
--- Purpose:
--- Pipeline array of g_nof_streams by g_pipeline cycles.
--- Description:
--- See dp_pipeline.
+ -- Purpose:
+ -- Pipeline array of g_nof_streams by g_pipeline cycles.
+ -- Description:
+ -- See dp_pipeline.
entity dp_pipeline_arr is
generic (
@@ -50,19 +50,19 @@ architecture str of dp_pipeline_arr is
begin
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_p : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd b/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
index b4dcc11aac..bb291d2b70 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
@@ -21,22 +21,22 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
--- Purpose:
--- Pipeline the source input
--- Description:
--- This dp_pipeline_ready provides a single clock cycle delay of the source
--- input (i.e. siso). It does this by first going from RL = g_in_latency -->
--- 0 and then to RL = g_out_latency.
--- Data flow:
--- . out RL > in RL : incr(out RL - in RL)
--- . out RL <= in RL AND out RL = 0 : incr(1) --> adapt(out RL)
--- . out RL <= in RL AND out RL > 0 : adapt(0) --> incr(out RL)
--- Remark:
--- . The g_in_latency may be 0, but for g_in_latency=0 the sosi.ready acts
--- as an acknowledge and that could simply also be registered by the user.
+ -- Purpose:
+ -- Pipeline the source input
+ -- Description:
+ -- This dp_pipeline_ready provides a single clock cycle delay of the source
+ -- input (i.e. siso). It does this by first going from RL = g_in_latency -->
+ -- 0 and then to RL = g_out_latency.
+ -- Data flow:
+ -- . out RL > in RL : incr(out RL - in RL)
+ -- . out RL <= in RL AND out RL = 0 : incr(1) --> adapt(out RL)
+ -- . out RL <= in RL AND out RL > 0 : adapt(0) --> incr(out RL)
+ -- Remark:
+ -- . The g_in_latency may be 0, but for g_in_latency=0 the sosi.ready acts
+ -- as an acknowledge and that could simply also be registered by the user.
entity dp_pipeline_ready is
generic (
@@ -62,92 +62,92 @@ begin
gen_out_incr_rl : if g_out_latency > g_in_latency generate
-- Register siso by incrementing the input RL first
u_incr : entity work.dp_latency_increase
- generic map (
- g_in_latency => g_in_latency,
- g_incr_latency => g_out_latency - g_in_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => g_in_latency,
+ g_incr_latency => g_out_latency - g_in_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
gen_out_rl_0 : if g_out_latency <= g_in_latency and g_out_latency = 0 generate
-- Register siso by incrementing the input RL first
u_incr : entity work.dp_latency_increase
- generic map (
- g_in_latency => g_in_latency,
- g_incr_latency => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => internal_siso,
- src_out => internal_sosi
- );
+ generic map (
+ g_in_latency => g_in_latency,
+ g_incr_latency => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => internal_siso,
+ src_out => internal_sosi
+ );
-- Input RL --> 0
u_adapt : entity work.dp_latency_adapter
- generic map (
- g_in_latency => g_in_latency + 1,
- g_out_latency => g_out_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => internal_siso,
- snk_in => internal_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => g_in_latency + 1,
+ g_out_latency => g_out_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => internal_siso,
+ snk_in => internal_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
gen_out_rl : if g_out_latency <= g_in_latency and g_out_latency > 0 generate
-- First adapt the input RL --> 0
u_adapt : entity work.dp_latency_adapter
- generic map (
- g_in_latency => g_in_latency,
- g_out_latency => 0
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => internal_siso,
- src_out => internal_sosi
- );
+ generic map (
+ g_in_latency => g_in_latency,
+ g_out_latency => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => internal_siso,
+ src_out => internal_sosi
+ );
-- Register siso by incrementing the internal RL = 0 --> the output RL
u_incr : entity work.dp_latency_increase
- generic map (
- g_in_latency => 0,
- g_incr_latency => g_out_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => internal_siso,
- snk_in => internal_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => 0,
+ g_incr_latency => g_out_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => internal_siso,
+ snk_in => internal_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
index bc4a05d652..0f45599d19 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
@@ -20,12 +20,12 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_ram_from_mm is
generic (
@@ -53,19 +53,21 @@ entity dp_ram_from_mm is
end dp_ram_from_mm;
architecture rtl of dp_ram_from_mm is
- constant c_mm_ram_wr : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_ram_wr_nof_words),
- dat_w => c_word_w,
- nof_dat => g_ram_wr_nof_words,
- init_sl => '0');
+ constant c_mm_ram_wr : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_ram_wr_nof_words),
+ dat_w => c_word_w,
+ nof_dat => g_ram_wr_nof_words,
+ init_sl => '0');
constant c_ram_rd_nof_words : natural := (c_word_w * g_ram_wr_nof_words) / g_ram_rd_dat_w;
- constant c_mm_ram_rd : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_ram_rd_nof_words),
- dat_w => g_ram_rd_dat_w,
- nof_dat => c_ram_rd_nof_words,
- init_sl => '0');
+ constant c_mm_ram_rd : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_ram_rd_nof_words),
+ dat_w => g_ram_rd_dat_w,
+ nof_dat => c_ram_rd_nof_words,
+ init_sl => '0');
type t_state_enum is (s_init, s_wait_for_rdy, s_read);
@@ -150,25 +152,25 @@ begin
end process;
u_ram : entity common_lib.common_ram_cr_cw_ratio
- generic map (
- g_technology => g_technology,
- g_ram_wr => c_mm_ram_wr,
- g_ram_rd => c_mm_ram_rd,
- g_init_file => g_init_file
- )
- port map (
- -- Write port clock domain
- wr_rst => mm_rst,
- wr_clk => mm_clk,
- wr_en => mm_wr,
- wr_adr => mm_addr(c_mm_ram_wr.adr_w - 1 downto 0),
- wr_dat => mm_wrdata(c_mm_ram_wr.dat_w - 1 downto 0),
- -- Read port clock domain
- rd_rst => st_rst,
- rd_clk => st_clk,
- rd_en => rd_en,
- rd_adr => rd_addr,
- rd_dat => rd_data,
- rd_val => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram_wr => c_mm_ram_wr,
+ g_ram_rd => c_mm_ram_rd,
+ g_init_file => g_init_file
+ )
+ port map (
+ -- Write port clock domain
+ wr_rst => mm_rst,
+ wr_clk => mm_clk,
+ wr_en => mm_wr,
+ wr_adr => mm_addr(c_mm_ram_wr.adr_w - 1 downto 0),
+ wr_dat => mm_wrdata(c_mm_ram_wr.dat_w - 1 downto 0),
+ -- Read port clock domain
+ rd_rst => st_rst,
+ rd_clk => st_clk,
+ rd_en => rd_en,
+ rd_adr => rd_addr,
+ rd_dat => rd_data,
+ rd_val => open
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
index 25446267ea..35f6535dd4 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_ram_from_mm_reg is
generic (
@@ -38,15 +38,16 @@ entity dp_ram_from_mm_reg is
sla_in : in t_mem_mosi;
dp_on : out std_logic
- );
+ );
end dp_ram_from_mm_reg;
architecture rtl of dp_ram_from_mm_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0');
signal mm_dp_on : std_logic;
begin
@@ -68,13 +69,13 @@ begin
end process;
u_async_dp_on : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- din => mm_dp_on,
- dout => dp_on
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ din => mm_dp_on,
+ dout => dp_on
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
index eab525722a..a389ac1b20 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
@@ -20,12 +20,12 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_ram_to_mm is
generic (
@@ -49,19 +49,21 @@ entity dp_ram_to_mm is
end dp_ram_to_mm;
architecture rtl of dp_ram_to_mm is
- constant c_mm_ram_rd : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_ram_rd_nof_words),
- dat_w => c_word_w,
- nof_dat => g_ram_rd_nof_words,
- init_sl => '0');
+ constant c_mm_ram_rd : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_ram_rd_nof_words),
+ dat_w => c_word_w,
+ nof_dat => g_ram_rd_nof_words,
+ init_sl => '0');
constant c_ram_wr_nof_words : natural := (c_word_w * g_ram_rd_nof_words) / g_ram_wr_dat_w;
- constant c_mm_ram_wr : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_ram_wr_nof_words),
- dat_w => g_ram_wr_dat_w,
- nof_dat => c_ram_wr_nof_words,
- init_sl => '0');
+ constant c_mm_ram_wr : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_ram_wr_nof_words),
+ dat_w => g_ram_wr_dat_w,
+ nof_dat => c_ram_wr_nof_words,
+ init_sl => '0');
type t_state_enum is (s_init, s_wait_for_sop, s_write);
@@ -128,25 +130,25 @@ begin
end process;
u_ram : entity common_lib.common_ram_cr_cw_ratio
- generic map (
- g_technology => g_technology,
- g_ram_wr => c_mm_ram_wr,
- g_ram_rd => c_mm_ram_rd,
- g_init_file => "UNUSED"
- )
- port map (
- -- Write port clock domain
- wr_rst => st_rst,
- wr_clk => st_clk,
- wr_en => snk_in.valid,
- wr_adr => wr_addr,
- wr_dat => snk_in.data(c_mm_ram_wr.dat_w - 1 downto 0),
- -- Read port clock domain
- rd_rst => mm_rst,
- rd_clk => mm_clk,
- rd_en => sla_in.rd,
- rd_adr => sla_in.address(c_mm_ram_rd.adr_w - 1 downto 0),
- rd_dat => sla_out.rddata(c_mm_ram_rd.dat_w - 1 downto 0),
- rd_val => sla_out.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram_wr => c_mm_ram_wr,
+ g_ram_rd => c_mm_ram_rd,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ -- Write port clock domain
+ wr_rst => st_rst,
+ wr_clk => st_clk,
+ wr_en => snk_in.valid,
+ wr_adr => wr_addr,
+ wr_dat => snk_in.data(c_mm_ram_wr.dat_w - 1 downto 0),
+ -- Read port clock domain
+ rd_rst => mm_rst,
+ rd_clk => mm_clk,
+ rd_en => sla_in.rd,
+ rd_adr => sla_in.address(c_mm_ram_rd.adr_w - 1 downto 0),
+ rd_dat => sla_out.rddata(c_mm_ram_rd.dat_w - 1 downto 0),
+ rd_val => sla_out.rdval
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_ready.vhd b/libraries/base/dp/src/vhdl/dp_ready.vhd
index f1f8532c37..a5f9be7cb2 100644
--- a/libraries/base/dp/src/vhdl/dp_ready.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ready.vhd
@@ -21,16 +21,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose:
--- =======
--- This component can be added to an uninterruptible source to provide the
--- stream with some flow control based on the ready signal of the
--- connected sink.
+ -- Purpose:
+ -- =======
+ -- This component can be added to an uninterruptible source to provide the
+ -- stream with some flow control based on the ready signal of the
+ -- connected sink.
entity dp_ready is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
index d0f65d7299..0e928ece0e 100644
--- a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
@@ -20,37 +20,37 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-
--- Author:
--- . Daniel van der Schuur
--- Purpose:
--- . DP wrapper for common_reinterleave
--- Description:
--- . The reinterleaver is an array of deinterleavers that feed an array of interleavers.
--- _
--- _ | \
--- / |----------| |----
--- ----| |---\ /--|_/
--- \_|--\ \ / _
--- \ X----| \
--- X | |----
--- _ / X----|_/
--- / |--/ / \ _
--- ----| |---/ \--| \
--- \_|----------| |----
--- |_/
--- Remarks:
--- . Requirements:
--- * All input streams must be synchronous;
--- * g_inter_block_size >= g_deint_block_size;
--- . g_deint_block_size = g_block_size out
--- . Input block length (!= g_deint_block_size) / nof_out / g_block_size_x = integer.
--- If it is not an integer number, the input blocks cannot be evenly distributed over
--- the outputs with the chosen block_size_x.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+
+ -- Author:
+ -- . Daniel van der Schuur
+ -- Purpose:
+ -- . DP wrapper for common_reinterleave
+ -- Description:
+ -- . The reinterleaver is an array of deinterleavers that feed an array of interleavers.
+ -- _
+ -- _ | \
+ -- / |----------| |----
+ -- ----| |---\ /--|_/
+ -- \_|--\ \ / _
+ -- \ X----| \
+ -- X | |----
+ -- _ / X----|_/
+ -- / |--/ / \ _
+ -- ----| |---/ \--| \
+ -- \_|----------| |----
+ -- |_/
+ -- Remarks:
+ -- . Requirements:
+ -- * All input streams must be synchronous;
+ -- * g_inter_block_size >= g_deint_block_size;
+ -- . g_deint_block_size = g_block_size out
+ -- . Input block length (!= g_deint_block_size) / nof_out / g_block_size_x = integer.
+ -- If it is not an integer number, the input blocks cannot be evenly distributed over
+ -- the outputs with the chosen block_size_x.
entity dp_reinterleave is
generic (
@@ -107,24 +107,24 @@ begin
common_reinterleave_in_val <= snk_in_arr(0).valid;
u_common_reinterleave : entity common_lib.common_reinterleave
- generic map (
- g_nof_in => g_nof_in,
- g_deint_block_size => g_deint_block_size,
- g_nof_out => g_nof_out,
- g_inter_block_size => g_inter_block_size,
- g_dat_w => g_dat_w,
- g_align_out => g_align_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => common_reinterleave_in_dat,
- in_val => common_reinterleave_in_val,
-
- out_dat => common_reinterleave_out_dat,
- out_val => common_reinterleave_out_val
- );
+ generic map (
+ g_nof_in => g_nof_in,
+ g_deint_block_size => g_deint_block_size,
+ g_nof_out => g_nof_out,
+ g_inter_block_size => g_inter_block_size,
+ g_dat_w => g_dat_w,
+ g_align_out => g_align_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => common_reinterleave_in_dat,
+ in_val => common_reinterleave_in_val,
+
+ out_dat => common_reinterleave_out_dat,
+ out_val => common_reinterleave_out_val
+ );
-----------------------------------------------------------------------------
-- Map output SLV to sosi_arr
@@ -154,19 +154,19 @@ begin
gen_ctrl : if g_use_ctrl = true generate
gen_dp_block_gen : for i in 0 to g_nof_out - 1 generate
u_dp_block_gen : entity work.dp_block_gen
- generic map (
- g_use_src_in => false,
- g_nof_data => g_block_size_output,
- g_preserve_sync => true,
- g_preserve_bsn => true
- )
- port map(
- rst => rst,
- clk => clk,
-
- snk_in => common_reinterleave_src_out_arr(i),
- src_out => dp_block_gen_src_out_arr(i)
- );
+ generic map (
+ g_use_src_in => false,
+ g_nof_data => g_block_size_output,
+ g_preserve_sync => true,
+ g_preserve_bsn => true
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ snk_in => common_reinterleave_src_out_arr(i),
+ src_out => dp_block_gen_src_out_arr(i)
+ );
end generate;
end generate;
@@ -180,20 +180,20 @@ begin
align_out : if g_use_sync_bsn = true generate
gen_dp_fifo_info: for i in 0 to g_nof_out - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
- generic map (
- g_use_sync => true,
- g_use_bsn => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in_arr(0), -- original snk_in info
-
- src_in => c_dp_siso_rdy,
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_use_sync => true,
+ g_use_bsn => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
+ info_snk_in => snk_in_arr(0), -- original snk_in info
+
+ src_in => c_dp_siso_rdy,
+ src_out => src_out_arr(i)
+ );
end generate;
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_repack.vhd b/libraries/base/dp/src/vhdl/dp_repack.vhd
index ebc3dd4c1b..6eabb8c9d1 100644
--- a/libraries/base/dp/src/vhdl/dp_repack.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack.vhd
@@ -20,22 +20,22 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-
--- Reuse from LOFAR rad_repack.vhd and rad_repack(rtl).vhd
-
--- Purpose:
--- Repack g_in_nof_words of width g_in_dat_w into g_out_nof_words of width
--- g_out_dat_w.
--- Description:
--- The dp_repack works both as packer and as unpacker.
--- If g_in_nof_words=g_out_nof_words then in_dat is simply passed on directly
--- to out_dat via wires.
--- The nof input words indicated by in_sof and in_eof must be a multiple of
--- g_in_nof_words, i.e. padding is not supported.
--- The in_val active duty-cycle must be <= g_in_nof_words/g_out_nof_words.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+
+ -- Reuse from LOFAR rad_repack.vhd and rad_repack(rtl).vhd
+
+ -- Purpose:
+ -- Repack g_in_nof_words of width g_in_dat_w into g_out_nof_words of width
+ -- g_out_dat_w.
+ -- Description:
+ -- The dp_repack works both as packer and as unpacker.
+ -- If g_in_nof_words=g_out_nof_words then in_dat is simply passed on directly
+ -- to out_dat via wires.
+ -- The nof input words indicated by in_sof and in_eof must be a multiple of
+ -- g_in_nof_words, i.e. padding is not supported.
+ -- The in_val active duty-cycle must be <= g_in_nof_words/g_out_nof_words.
entity dp_repack is
generic (
@@ -96,7 +96,7 @@ architecture rtl of dp_repack is
begin
no_pack : if g_in_nof_words = g_out_nof_words generate
out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack at the other end,
- -- typically g_out_dat_w=g_in_dat_w
+ -- typically g_out_dat_w=g_in_dat_w
out_val <= in_val;
out_sof <= in_sof;
out_eof <= in_eof;
@@ -149,11 +149,11 @@ begin
out_eof <= out_eof_vec(0);
buf_load <= '1' when signed(in_val_vec) = -1 else '0';
- -- in_val_vec=-1: input set complete, ready to be repacked
+ -- in_val_vec=-1: input set complete, ready to be repacked
buf_flush <= '1' when (unsigned(out_val_vec) = 1 or unsigned(out_val_vec) = 0) and buf_val = '1' else '0';
- -- out_val_vec=0: ready to repack first input set
- -- out_val_vec=1: ready to repack next input set
- -- buf_val: new input set available
+ -- out_val_vec=0: ready to repack first input set
+ -- out_val_vec=1: ready to repack next input set
+ -- buf_val: new input set available
p_in: process(in_sof, buf_load, in_val, in_val_vec, in_dat, in_dat_vec)
begin
@@ -217,11 +217,11 @@ begin
if g_ls_to_ms = true then
-- Push SLV to the right so new word appears at LS position
nxt_out_dat_vec <= std_logic_vector(to_unsigned(0,out_dat'length)) &
- out_dat_vec(out_dat_vec'high downto out_dat'length);
+ out_dat_vec(out_dat_vec'high downto out_dat'length);
else
-- Push SLV to the left so new word appears at MS position
nxt_out_dat_vec <= out_dat_vec(out_dat_vec'high - out_dat'length downto 0) &
- std_logic_vector(to_unsigned(0,out_dat'length));
+ std_logic_vector(to_unsigned(0,out_dat'length));
end if;
nxt_out_val_vec <= '0' & out_val_vec(out_val_vec'high downto 1);
diff --git a/libraries/base/dp/src/vhdl/dp_repack_data.vhd b/libraries/base/dp/src/vhdl/dp_repack_data.vhd
index fbc1849f6a..c595be9762 100644
--- a/libraries/base/dp/src/vhdl/dp_repack_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack_data.vhd
@@ -175,9 +175,9 @@
-- useful to be able to isolate a component for debugging.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_repack_in is
generic (
@@ -386,9 +386,9 @@ begin
end rtl;
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_repack_out is
generic (
@@ -626,9 +626,9 @@ begin
end rtl;
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_repack_data is
generic (
@@ -675,16 +675,16 @@ architecture str of dp_repack_data is
begin
gen_dp_pipeline_ready: if g_pipeline_ready = true generate
u_dp_pipeline_ready : entity dp_lib.dp_pipeline_ready
- port map (
- rst => rst,
- clk => clk,
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out => snk_out,
- snk_in => snk_in,
+ snk_out => snk_out,
+ snk_in => snk_in,
- src_in => i_snk_out,
- src_out => i_snk_in
- );
+ src_in => i_snk_out,
+ src_out => i_snk_in
+ );
end generate;
gen_no_dp_pipeline_ready: if g_pipeline_ready = false generate
@@ -705,23 +705,23 @@ begin
gen_dp_repack_in : if g_enable_repack_in = true generate
u_dp_repack_in : entity work.dp_repack_in
- generic map (
- g_bypass => g_in_bypass,
- g_in_dat_w => g_in_dat_w,
- g_in_nof_words => g_in_nof_words,
- g_in_symbol_w => g_in_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => i_snk_out,
- snk_in => i_snk_in,
-
- src_in => pack_siso,
- src_out => pack_sosi,
- src_out_data => pack_sosi_data
- );
+ generic map (
+ g_bypass => g_in_bypass,
+ g_in_dat_w => g_in_dat_w,
+ g_in_nof_words => g_in_nof_words,
+ g_in_symbol_w => g_in_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => i_snk_out,
+ snk_in => i_snk_in,
+
+ src_in => pack_siso,
+ src_out => pack_sosi,
+ src_out_data => pack_sosi_data
+ );
end generate;
no_dp_repack_out : if g_enable_repack_out = false generate
@@ -731,24 +731,24 @@ begin
gen_dp_repack_out : if g_enable_repack_out = true generate
u_dp_repack_out : entity work.dp_repack_out
- generic map (
- g_bypass => g_out_bypass,
- g_in_buf_dat_w => c_in_buf_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_out_nof_words => g_out_nof_words,
- g_out_symbol_w => g_out_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => pack_siso,
- snk_in => pack_sosi,
- snk_in_data => pack_sosi_data,
-
- src_in => src_in,
- src_out => i_src_out
- );
+ generic map (
+ g_bypass => g_out_bypass,
+ g_in_buf_dat_w => c_in_buf_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_out_nof_words => g_out_nof_words,
+ g_out_symbol_w => g_out_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => pack_siso,
+ snk_in => pack_sosi,
+ snk_in_data => pack_sosi_data,
+
+ src_in => src_in,
+ src_out => i_src_out
+ );
end generate;
-- Simulation only: internal stream RL verification
diff --git a/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd b/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
index 5149b5f2aa..4a7f2d1898 100644
--- a/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
@@ -20,22 +20,22 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-
--- Reuse from LOFAR rad_repack.vhd and rad_repack(rtl).vhd
-
--- Purpose:
--- Repack g_in_nof_words of width g_in_dat_w into g_out_nof_words of width
--- g_out_dat_w.
--- Description:
--- The dp_repack_legacy works both as packer and as unpacker.
--- If g_in_nof_words=g_out_nof_words then in_dat is simply passed on directly
--- to out_dat via wires.
--- The nof input words indicated by in_sof and in_eof must be a multiple of
--- g_in_nof_words, i.e. padding is not supported.
--- The in_val active duty-cycle must be <= g_in_nof_words/g_out_nof_words.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+
+ -- Reuse from LOFAR rad_repack.vhd and rad_repack(rtl).vhd
+
+ -- Purpose:
+ -- Repack g_in_nof_words of width g_in_dat_w into g_out_nof_words of width
+ -- g_out_dat_w.
+ -- Description:
+ -- The dp_repack_legacy works both as packer and as unpacker.
+ -- If g_in_nof_words=g_out_nof_words then in_dat is simply passed on directly
+ -- to out_dat via wires.
+ -- The nof input words indicated by in_sof and in_eof must be a multiple of
+ -- g_in_nof_words, i.e. padding is not supported.
+ -- The in_val active duty-cycle must be <= g_in_nof_words/g_out_nof_words.
entity dp_repack_legacy is
generic (
@@ -96,7 +96,7 @@ architecture rtl of dp_repack_legacy is
begin
no_pack : if g_in_nof_words = g_out_nof_words generate
out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack_legacy at the other end,
- -- typically g_out_dat_w=g_in_dat_w
+ -- typically g_out_dat_w=g_in_dat_w
out_val <= in_val;
out_sof <= in_sof;
out_eof <= in_eof;
@@ -149,11 +149,11 @@ begin
out_eof <= out_eof_vec(0);
buf_load <= '1' when signed(in_val_vec) = -1 else '0';
- -- in_val_vec=-1: input set complete, ready to be repacked
+ -- in_val_vec=-1: input set complete, ready to be repacked
buf_flush <= '1' when (unsigned(out_val_vec) = 1 or unsigned(out_val_vec) = 0) and buf_val = '1' else '0';
- -- out_val_vec=0: ready to repack first input set
- -- out_val_vec=1: ready to repack next input set
- -- buf_val: new input set available
+ -- out_val_vec=0: ready to repack first input set
+ -- out_val_vec=1: ready to repack next input set
+ -- buf_val: new input set available
p_in: process(in_sof, buf_load, in_val, in_val_vec, in_dat, in_dat_vec)
begin
@@ -217,11 +217,11 @@ begin
if g_ls_to_ms = true then
-- Push SLV to the right so new word appears at LS position
nxt_out_dat_vec <= std_logic_vector(to_unsigned(0,out_dat'length)) &
- out_dat_vec(out_dat_vec'high downto out_dat'length);
+ out_dat_vec(out_dat_vec'high downto out_dat'length);
else
-- Push SLV to the left so new word appears at MS position
nxt_out_dat_vec <= out_dat_vec(out_dat_vec'high - out_dat'length downto 0) &
- std_logic_vector(to_unsigned(0,out_dat'length));
+ std_logic_vector(to_unsigned(0,out_dat'length));
end if;
nxt_out_val_vec <= '0' & out_val_vec(out_val_vec'high downto 1);
diff --git a/libraries/base/dp/src/vhdl/dp_requantize.vhd b/libraries/base/dp/src/vhdl/dp_requantize.vhd
index c063da2ad8..1b4ec29cbb 100644
--- a/libraries/base/dp/src/vhdl/dp_requantize.vhd
+++ b/libraries/base/dp/src/vhdl/dp_requantize.vhd
@@ -21,30 +21,30 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
-use common_lib.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.all;
+ use common_lib.common_pkg.all;
--- Purpose: Requantize the data in the re, im or data field of the sosi record.
--- Description:
--- See common_requantize.vhd
--- Remarks:
--- . It does not take into account the ready signal from the siso record.
+ -- Purpose: Requantize the data in the re, im or data field of the sosi record.
+ -- Description:
+ -- See common_requantize.vhd
+ -- Remarks:
+ -- . It does not take into account the ready signal from the siso record.
entity dp_requantize is
generic (
g_complex : boolean := true; -- when TRUE, the re and im field are processed, when false, the data field is processed
g_representation : string := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
g_lsb_w : integer := 4; -- when > 0, number of LSbits to remove from in_dat
- -- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
- -- when 0 then no effect
+ -- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
+ -- when 0 then no effect
g_lsb_round : boolean := true; -- when TRUE round else truncate the input LSbits
g_lsb_round_clip : boolean := false; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
g_lsb_round_even : boolean := true; -- when TRUE round half to even, else round half away from zero
g_msb_clip : boolean := true; -- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric : boolean := false; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
- -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
+ -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
g_gain_w : natural := 0; -- do not use, must be 0, use negative g_lsb_w instead
g_pipeline_remove_lsb : natural := 0; -- >= 0
g_pipeline_remove_msb : natural := 0; -- >= 0, use g_pipeline_remove_lsb=0 and g_pipeline_remove_msb=0 for combinatorial output
@@ -81,25 +81,25 @@ begin
---------------------------------------------------------------
gen_requantize_data : if g_complex = false generate
u_requantize_data : entity common_lib.common_requantize
- generic map (
- g_representation => g_representation,
- g_lsb_w => g_lsb_w,
- g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
- g_lsb_round_even => g_lsb_round_even,
- g_msb_clip => g_msb_clip,
- g_msb_clip_symmetric => g_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => snk_in.data,
- out_dat => quantized_data,
- out_ovr => out_ovr
- );
+ generic map (
+ g_representation => g_representation,
+ g_lsb_w => g_lsb_w,
+ g_lsb_round => g_lsb_round,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_even => g_lsb_round_even,
+ g_msb_clip => g_msb_clip,
+ g_msb_clip_symmetric => g_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => snk_in.data,
+ out_dat => quantized_data,
+ out_ovr => out_ovr
+ );
end generate;
---------------------------------------------------------------
@@ -107,46 +107,46 @@ begin
---------------------------------------------------------------
gen_requantize_complex : if g_complex = true generate
u_requantize_re: entity common_lib.common_requantize
- generic map (
- g_representation => g_representation,
- g_lsb_w => g_lsb_w,
- g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
- g_lsb_round_even => g_lsb_round_even,
- g_msb_clip => g_msb_clip,
- g_msb_clip_symmetric => g_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => snk_in.re,
- out_dat => quantized_re,
- out_ovr => out_ovr_re
- );
+ generic map (
+ g_representation => g_representation,
+ g_lsb_w => g_lsb_w,
+ g_lsb_round => g_lsb_round,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_even => g_lsb_round_even,
+ g_msb_clip => g_msb_clip,
+ g_msb_clip_symmetric => g_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => snk_in.re,
+ out_dat => quantized_re,
+ out_ovr => out_ovr_re
+ );
u_requantize_im: entity common_lib.common_requantize
- generic map (
- g_representation => g_representation,
- g_lsb_w => g_lsb_w,
- g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
- g_lsb_round_even => g_lsb_round_even,
- g_msb_clip => g_msb_clip,
- g_msb_clip_symmetric => g_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => snk_in.im,
- out_dat => quantized_im,
- out_ovr => out_ovr_im
- );
+ generic map (
+ g_representation => g_representation,
+ g_lsb_w => g_lsb_w,
+ g_lsb_round => g_lsb_round,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_even => g_lsb_round_even,
+ g_msb_clip => g_msb_clip,
+ g_msb_clip_symmetric => g_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => snk_in.im,
+ out_dat => quantized_im,
+ out_ovr => out_ovr_im
+ );
out_ovr <= out_ovr_re or out_ovr_im;
end generate;
@@ -155,17 +155,17 @@ begin
-- Pipeline to align the other sosi fields
--------------------------------------------------------------
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => snk_in,
- -- ST source
- src_out => snk_in_piped
- );
+ generic map (
+ g_pipeline => c_pipeline -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => snk_in,
+ -- ST source
+ src_out => snk_in_piped
+ );
process(snk_in_piped, quantized_data, quantized_re, quantized_im)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd b/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
index 7e76bc93ba..d45433baea 100644
--- a/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
@@ -19,29 +19,29 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Author:
--- . Eric Kooistra, 14 Feb 2023
--- Purpose:
--- . Reverse the order of multiplexed data per every g_reverse_len values in
--- time.
--- Description:
--- . The snk_in blocks size must be an integer multiple of g_reverse_len.
--- . For example with g_reverse_len = 3, then snk_in input data 012_345_678
--- becomes 210_543_876 at src_out output.
--- . See common_reverse_n_data.vhd for more detailed description.
--- Remark:
--- . The dp_reverse_n_data.vhd and dp_reverse_n_data_fc.vhd are functionally
--- equivalent. Use dp_reverse_n_data_fc.vhd flow control (fc) is needed.
--- A difference is that dp_reverse_n_data_fc causes extra gaps in the data
--- valid after each g_reverse_len. Therefore use dp_reverse_n_data when no
--- flow control is needed.
--- . Typically g_reverse_len should not be too large (~< 4), because then the
--- implementation takes relatively too much logic.
+ -- Author:
+ -- . Eric Kooistra, 14 Feb 2023
+ -- Purpose:
+ -- . Reverse the order of multiplexed data per every g_reverse_len values in
+ -- time.
+ -- Description:
+ -- . The snk_in blocks size must be an integer multiple of g_reverse_len.
+ -- . For example with g_reverse_len = 3, then snk_in input data 012_345_678
+ -- becomes 210_543_876 at src_out output.
+ -- . See common_reverse_n_data.vhd for more detailed description.
+ -- Remark:
+ -- . The dp_reverse_n_data.vhd and dp_reverse_n_data_fc.vhd are functionally
+ -- equivalent. Use dp_reverse_n_data_fc.vhd flow control (fc) is needed.
+ -- A difference is that dp_reverse_n_data_fc causes extra gaps in the data
+ -- valid after each g_reverse_len. Therefore use dp_reverse_n_data when no
+ -- flow control is needed.
+ -- . Typically g_reverse_len should not be too large (~< 4), because then the
+ -- implementation takes relatively too much logic.
entity dp_reverse_n_data is
generic (
@@ -66,16 +66,16 @@ end dp_reverse_n_data;
architecture str of dp_reverse_n_data is
constant c_pipeline_total : natural := g_pipeline_demux_in + g_pipeline_demux_out +
- g_reverse_len - 1 +
- g_pipeline_mux_in + g_pipeline_mux_out;
- constant c_complex_w : natural := g_data_w / 2;
+ g_reverse_len - 1 +
+ g_pipeline_mux_in + g_pipeline_mux_out;
+ constant c_complex_w : natural := g_data_w / 2;
- signal in_data : std_logic_vector(g_data_w - 1 downto 0);
+ signal in_data : std_logic_vector(g_data_w - 1 downto 0);
- signal reversed_data : std_logic_vector(g_data_w - 1 downto 0);
- signal reversed_val : std_logic;
+ signal reversed_data : std_logic_vector(g_data_w - 1 downto 0);
+ signal reversed_val : std_logic;
- signal snk_in_delayed : t_dp_sosi;
+ signal snk_in_delayed : t_dp_sosi;
begin
p_in_data : process(snk_in)
begin
@@ -87,39 +87,39 @@ begin
end process;
u_common_reverse_n : entity common_lib.common_reverse_n_data
- generic map (
- -- Pipeline: 0 for combinatorial, > 0 for registers
- g_pipeline_demux_in => g_pipeline_demux_in, -- serial to parallel demux
- g_pipeline_demux_out => g_pipeline_demux_out,
- g_pipeline_mux_in => g_pipeline_mux_in, -- parallel to serial mux
- g_pipeline_mux_out => g_pipeline_mux_out,
- g_reverse_len => g_reverse_len,
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ -- Pipeline: 0 for combinatorial, > 0 for registers
+ g_pipeline_demux_in => g_pipeline_demux_in, -- serial to parallel demux
+ g_pipeline_demux_out => g_pipeline_demux_out,
+ g_pipeline_mux_in => g_pipeline_mux_in, -- parallel to serial mux
+ g_pipeline_mux_out => g_pipeline_mux_out,
+ g_reverse_len => g_reverse_len,
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_data => in_data,
- in_val => snk_in.valid,
- in_eop => snk_in.eop,
- out_data => reversed_data,
- out_val => reversed_val -- = snk_in_delayed.valid
- );
+ in_data => in_data,
+ in_val => snk_in.valid,
+ in_eop => snk_in.eop,
+ out_data => reversed_data,
+ out_val => reversed_val -- = snk_in_delayed.valid
+ );
-- Pipeline other sosi fields
u_pipe_input : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline_total
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => snk_in,
- -- ST source
- src_out => snk_in_delayed
- );
+ generic map (
+ g_pipeline => c_pipeline_total
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => snk_in,
+ -- ST source
+ src_out => snk_in_delayed
+ );
p_src_out : process(snk_in_delayed, reversed_data)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd b/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
index 77741d7694..9d84ee07fd 100644
--- a/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
@@ -19,28 +19,28 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Author:
--- . Eric Kooistra, 14 Feb 2023
--- Purpose:
--- . Reverse the order of multiplexed data per every g_reverse_len values in
--- time.
--- Description:
--- . The snk_in blocks size must be an integer multiple of g_reverse_len.
--- . For example with g_reverse_len = 3, then snk_in input data 012_345_678
--- becomes 210_543_876 at src_out output.
--- Remark:
--- . The dp_reverse_n_data.vhd and dp_reverse_n_data_fc.vhd are functionally
--- equivalent. Use dp_reverse_n_data_fc.vhd flow control (fc) is needed.
--- A difference is that dp_reverse_n_data_fc causes extra gaps in the data
--- valid after each g_reverse_len. Therefore use dp_reverse_n_data when no
--- flow control is needed.
--- . Typically g_reverse_len should not be too large (~< 4), because then the
--- implementation takes relatively too much logic.
+ -- Author:
+ -- . Eric Kooistra, 14 Feb 2023
+ -- Purpose:
+ -- . Reverse the order of multiplexed data per every g_reverse_len values in
+ -- time.
+ -- Description:
+ -- . The snk_in blocks size must be an integer multiple of g_reverse_len.
+ -- . For example with g_reverse_len = 3, then snk_in input data 012_345_678
+ -- becomes 210_543_876 at src_out output.
+ -- Remark:
+ -- . The dp_reverse_n_data.vhd and dp_reverse_n_data_fc.vhd are functionally
+ -- equivalent. Use dp_reverse_n_data_fc.vhd flow control (fc) is needed.
+ -- A difference is that dp_reverse_n_data_fc causes extra gaps in the data
+ -- valid after each g_reverse_len. Therefore use dp_reverse_n_data when no
+ -- flow control is needed.
+ -- . Typically g_reverse_len should not be too large (~< 4), because then the
+ -- implementation takes relatively too much logic.
entity dp_reverse_n_data_fc is
generic (
@@ -67,19 +67,19 @@ architecture str of dp_reverse_n_data_fc is
signal reverse_sosi_arr : t_dp_sosi_arr(g_reverse_len - 1 downto 0);
begin
u_demux_one_to_n : entity work.dp_deinterleave_one_to_n
- generic map (
- g_pipeline => g_pipeline_in,
- g_nof_outputs => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline => g_pipeline_in,
+ g_nof_outputs => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out => snk_out,
- snk_in => snk_in,
- src_in_arr => demux_siso_arr,
- src_out_arr => demux_sosi_arr
- );
+ snk_out => snk_out,
+ snk_in => snk_in,
+ src_in_arr => demux_siso_arr,
+ src_out_arr => demux_sosi_arr
+ );
gen_reverse : for I in 0 to g_reverse_len - 1 generate
demux_siso_arr(g_reverse_len - 1 - I) <= reverse_siso_arr(I);
@@ -87,17 +87,17 @@ begin
end generate;
u_mux_n_to_one : entity work.dp_interleave_n_to_one
- generic map (
- g_pipeline => g_pipeline_out,
- g_nof_inputs => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline => g_pipeline_out,
+ g_nof_inputs => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out_arr => reverse_siso_arr,
- snk_in_arr => reverse_sosi_arr,
- src_in => src_in,
- src_out => src_out
- );
+ snk_out_arr => reverse_siso_arr,
+ snk_in_arr => reverse_sosi_arr,
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_rsn_source.vhd b/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
index db1c351234..42e1cc9a1b 100644
--- a/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
@@ -62,10 +62,10 @@
-- [1] https://support.astron.nl/confluence/display/L2M/L2+STAT+Decision%3A+Timing+in+Station
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_rsn_source is
generic (
@@ -125,8 +125,8 @@ begin
rsn <= MULT_UVEC(bs_sosi.bsn(g_bsn_w - 1 downto 0), TO_UVEC(g_bs_block_size, c_bs_block_size_cnt_w));
p_state : process(bs_sosi, nxt_sync, sync, sync_size_cnt, nof_clk_per_sync,
- state, prev_state,
- i_rs_sosi, rs_block_size_cnt, rsn)
+ state, prev_state,
+ i_rs_sosi, rs_block_size_cnt, rsn)
begin
-- Maintain sync_size_cnt for nof_clk_per_sync
-- . nof_clk_per_sync is the number of clk per sync interval and the
@@ -169,9 +169,9 @@ begin
nxt_state <= s_on;
end if;
- -- using separate states s_on_sop and s_on_eop instead of only
- -- s_on state and rs_block_size_cnt, cause that g_rs_block_size must be
- -- >= 3, but that is fine.
+ -- using separate states s_on_sop and s_on_eop instead of only
+ -- s_on state and rs_block_size_cnt, cause that g_rs_block_size must be
+ -- >= 3, but that is fine.
when s_on_sop =>
-- Start of block
nxt_rs_sosi.sop <= '1';
diff --git a/libraries/base/dp/src/vhdl/dp_selector.vhd b/libraries/base/dp/src/vhdl/dp_selector.vhd
index 79aea56993..673baae8cb 100644
--- a/libraries/base/dp/src/vhdl/dp_selector.vhd
+++ b/libraries/base/dp/src/vhdl/dp_selector.vhd
@@ -28,12 +28,12 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib, common_mult_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_selector is
generic (
@@ -60,23 +60,23 @@ end dp_selector;
architecture str of dp_selector is
begin
u_dp_selector_arr : entity work.dp_selector_arr
- generic map (
- g_nof_arr => 1,
- g_pipeline => g_pipeline
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_nof_arr => 1,
+ g_pipeline => g_pipeline
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- reg_selector_mosi => reg_selector_mosi,
- reg_selector_miso => reg_selector_miso,
+ reg_selector_mosi => reg_selector_mosi,
+ reg_selector_miso => reg_selector_miso,
- pipe_sosi_arr(0) => pipe_sosi,
- ref_sosi_arr(0) => ref_sosi,
- out_sosi_arr(0) => out_sosi,
+ pipe_sosi_arr(0) => pipe_sosi,
+ ref_sosi_arr(0) => ref_sosi,
+ out_sosi_arr(0) => out_sosi,
- selector_en => selector_en
- );
+ selector_en => selector_en
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_selector_arr.vhd b/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
index 33b96c99a3..5b1ed899fb 100644
--- a/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
@@ -31,12 +31,12 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib, common_mult_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_selector_arr is
generic (
@@ -74,21 +74,21 @@ begin
selector_en <= reg_selector_en(0);
u_mms_common_reg : entity common_lib.mms_common_reg
- generic map (
- g_mm_reg => c_selector_mem_reg
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- reg_mosi => reg_selector_mosi,
- reg_miso => reg_selector_miso,
-
- in_reg => reg_selector_en,
- out_reg => reg_selector_en
- );
+ generic map (
+ g_mm_reg => c_selector_mem_reg
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ reg_mosi => reg_selector_mosi,
+ reg_miso => reg_selector_miso,
+
+ in_reg => reg_selector_en,
+ out_reg => reg_selector_en
+ );
n_en <= not reg_selector_en(0);
@@ -100,31 +100,31 @@ begin
switch_high => reg_selector_en(0),
switch_low => n_en,
out_level => switch_select
- );
+ );
u_pipeline_arr : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_arr,
- g_pipeline => g_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in_arr => pipe_sosi_arr,
- src_out_arr => pipelined_pipe_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_arr,
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in_arr => pipe_sosi_arr,
+ src_out_arr => pipelined_pipe_sosi_arr
+ );
select_sosi_arr <= pipelined_pipe_sosi_arr when switch_select = '1' else ref_sosi_arr;
u_pipeline_arr_out : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_arr,
- g_pipeline => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in_arr => select_sosi_arr,
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_arr,
+ g_pipeline => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in_arr => select_sosi_arr,
+ src_out_arr => out_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_shiftram.vhd b/libraries/base/dp/src/vhdl/dp_shiftram.vhd
index f63fd0c4d9..ecedb2e62a 100644
--- a/libraries/base/dp/src/vhdl/dp_shiftram.vhd
+++ b/libraries/base/dp/src/vhdl/dp_shiftram.vhd
@@ -23,13 +23,13 @@
-- Description:
library IEEE, common_lib, technology_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_shiftram is
generic (
@@ -76,57 +76,57 @@ begin
-----------------------------------------------------------------------------
gen_common_shiftram : for i in 0 to g_nof_streams - 1 generate
u_common_shiftram : entity common_lib.common_shiftram
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_nof_words => g_nof_words
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- data_in => snk_in_arr(i).data(g_data_w - 1 downto 0),
- data_in_val => snk_in_arr(i).valid,
- data_in_shift => common_shiftram_shift_in_arr(i),
-
- data_out => src_out_arr(i).data(g_data_w - 1 downto 0),
- data_out_val => src_out_arr(i).valid,
- data_out_shift => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_nof_words => g_nof_words
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ data_in => snk_in_arr(i).data(g_data_w - 1 downto 0),
+ data_in_val => snk_in_arr(i).valid,
+ data_in_shift => common_shiftram_shift_in_arr(i),
+
+ data_out => src_out_arr(i).data(g_data_w - 1 downto 0),
+ data_out_val => src_out_arr(i).valid,
+ data_out_shift => open
+ );
end generate;
-----------------------------------------------------------------------------
-- MM control
-----------------------------------------------------------------------------
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(c_field_arr, c_word_w))
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(c_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
gen_stream : for i in 0 to g_nof_streams - 1 generate
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi_arr(i),
- mm_miso => reg_miso_arr(i),
+ mm_mosi => reg_mosi_arr(i),
+ mm_miso => reg_miso_arr(i),
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_out_arr(i)
- );
+ slv_out => mm_fields_out_arr(i)
+ );
gen_no_sync : if g_use_sync_in = false generate
common_shiftram_shift_in_arr(i) <= mm_fields_out_arr(i)(field_hi(c_field_arr, "shift") downto field_lo(c_field_arr, "shift"));
@@ -139,8 +139,8 @@ begin
common_shiftram_shift_in_arr(i) <= (others => '0');
elsif rising_edge(dp_clk) then
if(sync_in = '1') then
- common_shiftram_shift_in_arr(i) <= mm_fields_out_arr(i)(field_hi(c_field_arr, "shift") downto field_lo(c_field_arr, "shift"));
- end if;
+ common_shiftram_shift_in_arr(i) <= mm_fields_out_arr(i)(field_hi(c_field_arr, "shift") downto field_lo(c_field_arr, "shift"));
+ end if;
end if;
end process;
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_shiftreg.vhd b/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
index 0a6c63afa8..9d3917ec9c 100644
--- a/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
@@ -21,32 +21,32 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-
--- Purpose:
--- Move the valid input data through a shift register to have access to
--- g_nof_words, before outputing them.
--- Description:
--- This dp_shiftreg puts the valid input data through a shift register. When
--- the shift register is full then every new valid input also causes a valid
--- output.
--- When g_flush_eop is TRUE then shift register gets flushed if it contains
--- an eop, provided that the output is ready.
--- Note that for g_nof_words = 1 the dp_shiftreg still differs from
--- dp_pipeline, because dp_pipeline outputs valid data when the
--- src_in.ready='1', while dp_shiftreg outputs valid data when it gets
--- pushed out by valid input data or by flush eop.
--- Via cur_shiftreg_inputs for all words of the current shift register is
--- available externally for monitoring. When g_modify_support is TRUE then
--- the input for all the words in de shift register can be modified via
--- new_shiftreg_inputs register. Note that cur_shiftreg_inputs(0) = snk_in.
--- Use g_output_reg=TRUE to register the src_out SOSI control signals,
--- because they have a combinatorial AND-delay if g_output_reg=FALSE.
--- Remarks:
--- . Ready latency = 1
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+
+ -- Purpose:
+ -- Move the valid input data through a shift register to have access to
+ -- g_nof_words, before outputing them.
+ -- Description:
+ -- This dp_shiftreg puts the valid input data through a shift register. When
+ -- the shift register is full then every new valid input also causes a valid
+ -- output.
+ -- When g_flush_eop is TRUE then shift register gets flushed if it contains
+ -- an eop, provided that the output is ready.
+ -- Note that for g_nof_words = 1 the dp_shiftreg still differs from
+ -- dp_pipeline, because dp_pipeline outputs valid data when the
+ -- src_in.ready='1', while dp_shiftreg outputs valid data when it gets
+ -- pushed out by valid input data or by flush eop.
+ -- Via cur_shiftreg_inputs for all words of the current shift register is
+ -- available externally for monitoring. When g_modify_support is TRUE then
+ -- the input for all the words in de shift register can be modified via
+ -- new_shiftreg_inputs register. Note that cur_shiftreg_inputs(0) = snk_in.
+ -- Use g_output_reg=TRUE to register the src_out SOSI control signals,
+ -- because they have a combinatorial AND-delay if g_output_reg=FALSE.
+ -- Remarks:
+ -- . Ready latency = 1
entity dp_shiftreg is
generic (
@@ -177,16 +177,16 @@ begin
gen_output_reg : if g_output_reg = true generate
u_output : entity work.dp_pipeline
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => shiftreg_out,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => shiftreg_out,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_split.vhd b/libraries/base/dp/src/vhdl/dp_split.vhd
index 19ac1fb2b5..37c4dcc055 100644
--- a/libraries/base/dp/src/vhdl/dp_split.vhd
+++ b/libraries/base/dp/src/vhdl/dp_split.vhd
@@ -20,57 +20,57 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-
--- Purpose:
--- Split one frame into two frames.
--- Description:
--- Split an input frame into a head and a tail output frame, so the reverse
--- of dp_concat. The g_nof_symbols determines how many symbols are used for
--- the head output frame via source port 0. The rest of the symbols are
--- passed on to tail output frame via source port 1.
--- Remark:
--- . Both frames will have the same data width and symbol width.
--- . The split is done at symbol level and the output frame will have the
--- aggregated empty.
--- . The split head frame gets the current channel and error field value. The
--- error field may be undefined because the true error information is not
--- known yet as it is only available at the snk_in.eop. The split tail frame
--- gets channel and error field from the input frame.
--- . If the dynamic nof_symbols input is used, then g_nof_symbols must be set
--- to fit the largest head frame and input nof_symbols. Otherwise if
--- nof_symbols is fixed, then g_nof_symbols can be set to that value and the
--- dynamic input can be left not connected.
--- . If nof_symbols=0, then the input frame is passed on entirely to the tail
--- frame output. If nof_symbols > nof input symbols then the input frame
--- is passed on entirely to the head frame output.
--- . Allow an idle cycle between head and tail frame if the split is not at a
--- word boundary. Otherwise the statemachine would become more complicated
--- and require the use of prev_src_in to check that the src_in_arr(c_tail) was
--- ready.
--- . Allow an idle cycle between tail and next head frame to ease the state
--- machine. Hence the input data must have at least one cycle gap between
--- input frames. The state machine is complicated due to that dp_split
--- support dynamic MM control of nof_symbols over a range of 0 to max.
--- . nof_symbols_out is valid at the SOP of the head frame and gives the nof
--- symbols in this head frame. Is based on nof_symbols. Therefore
--- nof_symbols_out is only correct if the input frame has >= nof_symbols.
---
--- Design steps that were taken for dp_split (took about 3 days):
--- 1 aim is a component that does the opposite of dp_concat
--- 2 same steps were taken as for dp_concat
--- 3 verify with tb_dp_split:
--- . always ready and input available
--- . nof_symbols = 0, 1, 2, ..., 10
--- . nof_symbols_per_data = 1, 2, 3, 4
--- . random ready
--- . random input availble
--- 4 combinatorial zero-delay loops and truncation warnings wer debugged by
--- restart -f, then run x ns to just before the when the error occurs and
--- then single step until the error occurs.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+
+ -- Purpose:
+ -- Split one frame into two frames.
+ -- Description:
+ -- Split an input frame into a head and a tail output frame, so the reverse
+ -- of dp_concat. The g_nof_symbols determines how many symbols are used for
+ -- the head output frame via source port 0. The rest of the symbols are
+ -- passed on to tail output frame via source port 1.
+ -- Remark:
+ -- . Both frames will have the same data width and symbol width.
+ -- . The split is done at symbol level and the output frame will have the
+ -- aggregated empty.
+ -- . The split head frame gets the current channel and error field value. The
+ -- error field may be undefined because the true error information is not
+ -- known yet as it is only available at the snk_in.eop. The split tail frame
+ -- gets channel and error field from the input frame.
+ -- . If the dynamic nof_symbols input is used, then g_nof_symbols must be set
+ -- to fit the largest head frame and input nof_symbols. Otherwise if
+ -- nof_symbols is fixed, then g_nof_symbols can be set to that value and the
+ -- dynamic input can be left not connected.
+ -- . If nof_symbols=0, then the input frame is passed on entirely to the tail
+ -- frame output. If nof_symbols > nof input symbols then the input frame
+ -- is passed on entirely to the head frame output.
+ -- . Allow an idle cycle between head and tail frame if the split is not at a
+ -- word boundary. Otherwise the statemachine would become more complicated
+ -- and require the use of prev_src_in to check that the src_in_arr(c_tail) was
+ -- ready.
+ -- . Allow an idle cycle between tail and next head frame to ease the state
+ -- machine. Hence the input data must have at least one cycle gap between
+ -- input frames. The state machine is complicated due to that dp_split
+ -- support dynamic MM control of nof_symbols over a range of 0 to max.
+ -- . nof_symbols_out is valid at the SOP of the head frame and gives the nof
+ -- symbols in this head frame. Is based on nof_symbols. Therefore
+ -- nof_symbols_out is only correct if the input frame has >= nof_symbols.
+ --
+ -- Design steps that were taken for dp_split (took about 3 days):
+ -- 1 aim is a component that does the opposite of dp_concat
+ -- 2 same steps were taken as for dp_concat
+ -- 3 verify with tb_dp_split:
+ -- . always ready and input available
+ -- . nof_symbols = 0, 1, 2, ..., 10
+ -- . nof_symbols_per_data = 1, 2, 3, 4
+ -- . random ready
+ -- . random input availble
+ -- 4 combinatorial zero-delay loops and truncation warnings wer debugged by
+ -- restart -f, then run x ns to just before the when the error occurs and
+ -- then single step until the error occurs.
entity dp_split is
generic (
@@ -189,18 +189,18 @@ begin
-- Hold the sink input to be able to register the source output
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in,
- -- ST source
- src_in => hold_src_in,
- next_src_out => next_src_buf,
- pend_src_out => OPEN,
- src_out_reg => src_buf
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in,
+ -- ST source
+ src_in => hold_src_in,
+ next_src_out => next_src_buf,
+ pend_src_out => OPEN,
+ src_out_reg => src_buf
+ );
-- Hold input register
nxt_src_buf <= next_src_buf;
@@ -275,7 +275,7 @@ begin
-- preserve tail data information for next state
nxt_tail <= tail; -- keep the tail data part in case the split is at symbol boundary and not at word boundary,
- -- keep the sop of the tail output, the valid and eop of tail are not used.
+ -- keep the sop of the tail output, the valid and eop of tail are not used.
-- pass on output
nxt_state <= state;
@@ -362,7 +362,7 @@ begin
if next_src_buf.eop = '1' then
i_snk_out <= c_dp_siso_rst; -- no input request for at least one clock cycle, to allow change in nof_symbols_reg and/or for state s_eop
if TO_UINT(v_input_empty) >= TO_UINT(head_empty_reg) then
- -- this is the last tail output, the input eop marks the tail output eop
+ -- this is the last tail output, the input eop marks the tail output eop
nxt_src_out_arr(c_tail).empty <= RESIZE_DP_EMPTY(func_dp_empty_split(v_input_empty, head_empty_reg, c_nof_symbols_per_data));
nxt_state <= s_head;
else -- need one more tail word to output the last tail part
diff --git a/libraries/base/dp/src/vhdl/dp_split_reg.vhd b/libraries/base/dp/src/vhdl/dp_split_reg.vhd
index dc7a67f30e..e38771dc82 100644
--- a/libraries/base/dp/src/vhdl/dp_split_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_split_reg.vhd
@@ -30,9 +30,9 @@
-- |-----------------------------------------------------------------------|
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_split_reg is
generic (
@@ -55,11 +55,12 @@ entity dp_split_reg is
end dp_split_reg;
architecture str of dp_split_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0');
signal mm_nof_symbols : std_logic_vector(ceil_log2(g_nof_symbols + 1) - 1 downto 0);
begin
@@ -81,12 +82,12 @@ begin
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
when 0 =>
- mm_nof_symbols <= sla_in.wrdata(ceil_log2(g_nof_symbols + 1) - 1 downto 0);
+ mm_nof_symbols <= sla_in.wrdata(ceil_log2(g_nof_symbols + 1) - 1 downto 0);
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -102,15 +103,15 @@ begin
end process;
u_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
- in_dat => mm_nof_symbols,
+ in_dat => mm_nof_symbols,
- out_rst => st_rst,
- out_clk => st_clk,
+ out_rst => st_rst,
+ out_clk => st_clk,
- out_dat => nof_symbols
- );
+ out_dat => nof_symbols
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd b/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
index e47aa13cbc..64c0df310c 100644
--- a/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
+++ b/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
@@ -20,21 +20,21 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-
--- Purpose:
--- . Control a source's output rate by toggling its ready input.
--- Description:
--- . The following diagram shows how src_out depends on the generics (only
--- two src_out samples shown):
--- |<--g_block_period-->|
--- src_out) |<-----g_init_valid_delay----->[0] [1]
--- ^
--- |
--- init_valid_delay_ref='1'
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+
+ -- Purpose:
+ -- . Control a source's output rate by toggling its ready input.
+ -- Description:
+ -- . The following diagram shows how src_out depends on the generics (only
+ -- two src_out samples shown):
+ -- |<--g_block_period-->|
+ -- src_out) |<-----g_init_valid_delay----->[0] [1]
+ -- ^
+ -- |
+ -- init_valid_delay_ref='1'
entity dp_src_out_timer is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
index 22b5cc127b..dcda4bb6d0 100644
--- a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
------------------------------------------------------------------------------
@@ -120,15 +120,16 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(1, c_dp_stream_bsn_w),
+ to_unsigned(1, c_dp_stream_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ '1', '1', '1',
+ to_unsigned(1, c_dp_stream_empty_w),
+ to_unsigned(1, c_dp_stream_channel_w),
+ to_unsigned(1, c_dp_stream_error_w));
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -207,30 +208,34 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Reset only the control fields of the DP sosi record
function RESET_DP_SOSI_CTRL(sosi : t_dp_sosi) return t_dp_sosi;
@@ -364,11 +369,11 @@ package dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
@@ -411,11 +416,12 @@ end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -430,20 +436,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -461,10 +469,11 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
@@ -921,7 +930,7 @@ package body dp_stream_pkg is
elsif str = "SOP" then v_dp(I).sop := v_slv(I);
elsif str = "EOP" then v_dp(I).eop := v_slv(I);
elsif str = "SYNC" then v_dp(I).sync := v_slv(I);
- -- use slv to set individual slv field
+ -- use slv to set individual slv field
elsif str = "BSN" then v_dp(I).bsn := RESIZE_DP_BSN(slv);
elsif str = "CHANNEL" then v_dp(I).channel := RESIZE_DP_CHANNEL(slv);
elsif str = "EMPTY" then v_dp(I).empty := RESIZE_DP_EMPTY(slv);
@@ -1296,16 +1305,16 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
@@ -1329,7 +1338,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
@@ -1481,11 +1490,11 @@ package body dp_stream_pkg is
if data_order_im_re = true then
-- data = im&re
v_out_data := RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w) &
- RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
+ RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
else
-- data = re&im
v_out_data := RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w) &
- RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
+ RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
end if;
end if;
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
index 82eb03aa00..6726d96eed 100644
--- a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
+++ b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
@@ -74,11 +74,11 @@
-- ref_sync stopped already.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_components_pkg.all;
entity dp_strobe_total_count is
generic (
@@ -110,11 +110,12 @@ architecture rtl of dp_strobe_total_count is
constant c_flush_adr : natural := c_dp_strobe_total_count_reg_flush_adr;
-- Define the size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => c_dp_strobe_total_count_reg_adr_w,
- dat_w => g_mm_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_dp_strobe_total_count_reg_nof_words,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_dp_strobe_total_count_reg_adr_w,
+ dat_w => g_mm_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_dp_strobe_total_count_reg_nof_words,
+ init_sl => '0');
type t_cnt_arr is array (integer range <>) of std_logic_vector(g_count_w - 1 downto 0);
@@ -142,28 +143,28 @@ begin
mm_cnt_flush <= reg_mosi.wr when TO_UINT(reg_mosi.address(c_mm_reg.adr_w - 1 downto 0)) = c_flush_adr else '0';
u_common_spulse_clear : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_cnt_clear,
- out_rst => dp_rst,
- out_clk => dp_clk,
- out_pulse => dp_cnt_clear
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_cnt_clear,
+ out_rst => dp_rst,
+ out_clk => dp_clk,
+ out_pulse => dp_cnt_clear
+ );
-- Support cnt clear via either MM or via an input strobe, use register
-- to ease timing closure
cnt_clr <= dp_cnt_clear or in_clr when rising_edge(dp_clk);
u_common_spulse_flush : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_cnt_flush,
- out_rst => dp_rst,
- out_clk => dp_clk,
- out_pulse => dp_cnt_flush
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_cnt_flush,
+ out_rst => dp_rst,
+ out_clk => dp_clk,
+ out_pulse => dp_cnt_flush
+ );
-- Register inputs to ease timing closure
-- . register ref_sync to ease timing closure for ref_sync fanout
@@ -199,18 +200,18 @@ begin
cnt_en_arr(I) <= cnt_en and in_strobe_reg2_arr(I);
u_counter : entity common_lib.common_counter
- generic map (
- g_width => g_count_w,
- g_clip => g_clip
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_width => g_count_w,
+ g_clip => g_clip
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en_arr(I),
- count => cnt_arr(I)
- );
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en_arr(I),
+ count => cnt_arr(I)
+ );
end generate;
-- Hold counter values at ref_sync_reg2 to have stable values for MM read
@@ -241,26 +242,26 @@ begin
end generate;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => rd_reg, -- read only
- out_reg => open -- no write
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => rd_reg, -- read only
+ out_reg => open -- no write
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_switch.vhd b/libraries/base/dp/src/vhdl/dp_switch.vhd
index e116310383..9118a87444 100644
--- a/libraries/base/dp/src/vhdl/dp_switch.vhd
+++ b/libraries/base/dp/src/vhdl/dp_switch.vhd
@@ -33,11 +33,11 @@
-- . So this does not work for continuous streams!
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_switch is
generic (
@@ -93,37 +93,37 @@ begin
-- A single MM register contains input to select
------------------------------------------------------------------------------
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi,
- mm_miso => reg_miso,
+ mm_mosi => reg_mosi,
+ mm_miso => reg_miso,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
------------------------------------------------------------------------------
-- put dp_xonoff block inbetween data path to control data flow.
------------------------------------------------------------------------------
gen_dp_xonoff_arr : for i in 0 to g_nof_inputs - 1 generate
u_dp_xonoff: entity work.dp_xonoff
- port map (
- clk => dp_clk,
- rst => dp_rst,
- -- Frame in
- in_sosi => snk_in_arr(i),
- in_siso => snk_out_arr(i),
- -- Frame out
- out_siso => xonoff_src_in_arr(i), -- flush control done by dp_mux.snk_out_arr
- out_sosi => xonoff_src_out_arr(i)
- );
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+ -- Frame in
+ in_sosi => snk_in_arr(i),
+ in_siso => snk_out_arr(i),
+ -- Frame out
+ out_siso => xonoff_src_in_arr(i), -- flush control done by dp_mux.snk_out_arr
+ out_sosi => xonoff_src_out_arr(i)
+ );
end generate;
------------------------------------------------------------------------------
@@ -145,35 +145,35 @@ begin
-- DP mux forwards input based on dp_mux_sel_ctrl
------------------------------------------------------------------------------
u_dp_mux : entity work.dp_mux
- generic map (
- g_mode => 4, -- Use sel_ctrl
- g_sel_ctrl_invert => false, -- Dont invert, data is already reverse mapped from DOWNTO >> TO arrays.
- g_nof_input => g_nof_inputs,
- g_use_fifo => g_use_fifo,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_empty_w => g_empty_w,
- g_in_channel_w => g_in_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_in_channel => g_use_in_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_size => array_init(g_fifo_size, g_nof_inputs),
- g_fifo_fill => array_init(g_fifo_fill, g_nof_inputs)
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
-
- sel_ctrl => dp_mux_sel_ctrl,
-
- snk_in_arr => inverted_snk_in_arr,
- snk_out_arr => inverted_snk_out_arr,
-
- src_out => src_out,
- src_in => src_in
- );
+ generic map (
+ g_mode => 4, -- Use sel_ctrl
+ g_sel_ctrl_invert => false, -- Dont invert, data is already reverse mapped from DOWNTO >> TO arrays.
+ g_nof_input => g_nof_inputs,
+ g_use_fifo => g_use_fifo,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_empty_w => g_empty_w,
+ g_in_channel_w => g_in_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_in_channel => g_use_in_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_size => array_init(g_fifo_size, g_nof_inputs),
+ g_fifo_fill => array_init(g_fifo_fill, g_nof_inputs)
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ sel_ctrl => dp_mux_sel_ctrl,
+
+ snk_in_arr => inverted_snk_in_arr,
+ snk_out_arr => inverted_snk_out_arr,
+
+ src_out => src_out,
+ src_in => src_in
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_sync_checker.vhd b/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
index e17d04d777..7e9ba9fde7 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
@@ -48,11 +48,11 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_sync_checker is
generic(
@@ -102,26 +102,26 @@ begin
v.snk_in := snk_in;
if(snk_in.sync = '1') then
- v.wait_for_next_sync := '0';
- v.sync_too_early := '0';
+ v.wait_for_next_sync := '0';
+ v.sync_too_early := '0';
end if;
-- Check on incoming SOP if things are OK
if (snk_in.sop = '1') then
if(r.wait_for_next_sync = '0') then
- v.cnt_sop := r.cnt_sop + 1;
- end if;
- if(r.cnt_sop = c_nof_blk_per_sync) then
- v.cnt_sop := 0;
- if(r.sync_too_early = '1') then
- -- Too early
- v.wait_for_next_sync := '1';
- elsif(snk_in.sync = '0') then
- -- Too late
- v.wait_for_next_sync := '1';
- v.nof_late_syncs := r.nof_late_syncs + 1;
- end if;
- end if;
+ v.cnt_sop := r.cnt_sop + 1;
+ end if;
+ if(r.cnt_sop = c_nof_blk_per_sync) then
+ v.cnt_sop := 0;
+ if(r.sync_too_early = '1') then
+ -- Too early
+ v.wait_for_next_sync := '1';
+ elsif(snk_in.sync = '0') then
+ -- Too late
+ v.wait_for_next_sync := '1';
+ v.nof_late_syncs := r.nof_late_syncs + 1;
+ end if;
+ end if;
end if;
-- Detect SYNC that is too early
@@ -133,28 +133,28 @@ begin
-- Only pass input to output when not waiting for valid SYNC.
if(r.wait_for_next_sync = '0') then
- v.src_out := r.snk_in;
+ v.src_out := r.snk_in;
else
- v.src_out := c_dp_sosi_rst;
+ v.src_out := c_dp_sosi_rst;
end if;
-- Reset the early and late sync counter
if(clear_nof_early_syncs = '1') then
- v.nof_early_syncs := 0;
+ v.nof_early_syncs := 0;
end if;
if(clear_nof_late_syncs = '1') then
- v.nof_late_syncs := 0;
+ v.nof_late_syncs := 0;
end if;
if(dp_rst = '1') then
- v.snk_in := c_dp_sosi_rst;
- v.src_out := c_dp_sosi_rst;
- v.cnt_sop := 0;
- v.sync_too_early := '0';
- v.wait_for_next_sync := '1';
- v.nof_early_syncs := 0;
- v.nof_late_syncs := 0;
+ v.snk_in := c_dp_sosi_rst;
+ v.src_out := c_dp_sosi_rst;
+ v.cnt_sop := 0;
+ v.sync_too_early := '0';
+ v.wait_for_next_sync := '1';
+ v.nof_early_syncs := 0;
+ v.nof_late_syncs := 0;
end if;
rin <= v;
diff --git a/libraries/base/dp/src/vhdl/dp_sync_insert.vhd b/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
index d1da545d1a..9a8439dc64 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
@@ -35,10 +35,10 @@
-- incoming data is perfectly aligned. Use a dp_sync_checker to assure the incoming data is perfect.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_sync_insert is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd b/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
index d5d54d2a23..1ca272d041 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
@@ -33,11 +33,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_sync_insert_v2 is
generic (
@@ -120,27 +120,27 @@ begin
end process;
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_nof_blk_per_sync_mm_reg,
- g_init_reg => c_init_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => reg_nof_blk_per_sync,
- out_reg => reg_nof_blk_per_sync
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_nof_blk_per_sync_mm_reg,
+ g_init_reg => c_init_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => reg_nof_blk_per_sync,
+ out_reg => reg_nof_blk_per_sync
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
index 60fee25c8b..2f0620bbd8 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
@@ -38,11 +38,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_sync_recover is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_tail_remove.vhd b/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
index d27a5f1743..0f9395c665 100644
--- a/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
@@ -29,18 +29,18 @@
-- remove 0 or more head data and 0 or more tail data from the input block.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_tail_remove is
generic (
g_data_w : natural;
g_symbol_w : natural;
g_nof_symbols : natural -- Nof symbols to be stripped from end of the packet,
- -- and accounting for the nof empty symbols.
+ -- and accounting for the nof empty symbols.
);
port (
st_rst : in std_logic;
@@ -68,25 +68,25 @@ begin
snk_out <= src_in;
u_src_shift : entity work.dp_shiftreg
- generic map (
- g_output_reg => c_output_reg,
- g_flush_eop => true,
- g_modify_support => true,
- g_nof_words => c_nof_shiftreg_words
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in,
- -- Control shift register contents
- cur_shiftreg_inputs => rd_sosi_arr,
- new_shiftreg_inputs => wr_sosi_arr,
- -- ST source
- src_in => src_in, -- We correct the stream via new_shiftreg_inputs, so
- src_out => src_out -- the shiftreg sources everything but the tail.
- );
+ generic map (
+ g_output_reg => c_output_reg,
+ g_flush_eop => true,
+ g_modify_support => true,
+ g_nof_words => c_nof_shiftreg_words
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in,
+ -- Control shift register contents
+ cur_shiftreg_inputs => rd_sosi_arr,
+ new_shiftreg_inputs => wr_sosi_arr,
+ -- ST source
+ src_in => src_in, -- We correct the stream via new_shiftreg_inputs, so
+ src_out => src_out -- the shiftreg sources everything but the tail.
+ );
p_shift: process(rd_sosi_arr)
variable v_wr_sosi_arr : t_dp_sosi_arr(0 to c_nof_shiftreg_words - 1);
diff --git a/libraries/base/dp/src/vhdl/dp_throttle.vhd b/libraries/base/dp/src/vhdl/dp_throttle.vhd
index 0c1ab51619..1bc951f435 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_throttle is
generic (
g_dc_period : natural := 100; -- provides a resolution of 1% (1/100..100/100)
g_throttle_valid : boolean := false -- FALSE: Stream passes through, snk_out.ready is AND'ed with pulse
- -- TRUE : Throttles src_out.valid instead of snk_out.ready; Onther entity I/O unused.
+ -- TRUE : Throttles src_out.valid instead of snk_out.ready; Onther entity I/O unused.
);
port (
rst : in std_logic;
@@ -60,20 +60,20 @@ begin
end generate;
u_common_duty_cycle : entity common_lib.common_duty_cycle
- generic map (
- g_rst_lvl => '0', -- Start with '0' on the output so our connected sink is not maxed out after reset
- g_dis_lvl => '0', -- Don't care - dc_out_en is not used.
- g_act_lvl => '1',
- g_per_cnt => g_dc_period,
- g_act_cnt => 0 -- After init, stay in idle state until we write a new DC value
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_rst_lvl => '0', -- Start with '0' on the output so our connected sink is not maxed out after reset
+ g_dis_lvl => '0', -- Don't care - dc_out_en is not used.
+ g_act_lvl => '1',
+ g_per_cnt => g_dc_period,
+ g_act_cnt => 0 -- After init, stay in idle state until we write a new DC value
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- dc_act_cnt => throttle,
+ dc_act_cnt => throttle,
- dc_out_en => '1', -- We can also disable the output by writing zero to dc_act_cnt.
- dc_out => dc_out
- );
+ dc_out_en => '1', -- We can also disable the output by writing zero to dc_act_cnt.
+ dc_out => dc_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd b/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
index 3d755e41ee..8a59c48e35 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_throttle_reg is
generic (
@@ -46,11 +46,12 @@ end dp_throttle_reg;
architecture rtl of dp_throttle_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 2,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
signal mm_throttle : std_logic_vector(ceil_log2(g_dc_period + 1) - 1 downto 0);
begin
@@ -59,7 +60,7 @@ begin
if mm_rst = '1' then
-- Access event, register values
mm_throttle <= (others => '0');
- elsif rising_edge(mm_clk) then
+ elsif rising_edge(mm_clk) then
-- Read access defaults
sla_out.rdval <= '0';
@@ -78,14 +79,14 @@ begin
end process;
u_common_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_throttle,
- in_done => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => throttle,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_throttle,
+ in_done => OPEN,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => throttle,
+ out_new => open
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd b/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
index f90a6ffc44..8820fc24b7 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
@@ -26,9 +26,9 @@
-- . g_period is
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_throttle_sop is
generic (
@@ -57,34 +57,34 @@ begin
snk_out.xon <= '1';
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cycle_cnt
- );
+ generic map (
+ g_width => c_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cycle_cnt
+ );
cnt_en <= '1' when TO_UINT(cycle_cnt) < g_period - 2 else '0';
cnt_clr <= snk_in.sop;
u_common_switch : entity common_lib.common_switch
- generic map (
- g_rst_level => '1',
- g_priority_lo => false,
- g_or_high => true,
- g_and_low => true
- )
- port map (
- clk => clk,
- rst => rst,
- switch_high => switch_high,
- switch_low => switch_low,
- out_level => switch_out
- );
+ generic map (
+ g_rst_level => '1',
+ g_priority_lo => false,
+ g_or_high => true,
+ g_and_low => true
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => switch_high,
+ switch_low => switch_low,
+ out_level => switch_out
+ );
switch_high <= not cnt_en;
switch_low <= snk_in.eop;
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd b/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
index dc6307419b..b3cff3e0c4 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
@@ -29,9 +29,9 @@
-- * (1/'data valid duty_cycle').
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_throttle_xon is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_unfolder.vhd b/libraries/base/dp/src/vhdl/dp_unfolder.vhd
index 3df7cc4c18..3c355e118e 100644
--- a/libraries/base/dp/src/vhdl/dp_unfolder.vhd
+++ b/libraries/base/dp/src/vhdl/dp_unfolder.vhd
@@ -20,22 +20,22 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-
--- Author:
--- . Daniel van der Schuur
--- Purpose:
--- . Unfold n input streams into n*2, n*2*2, n*2*2*2, .. output streams
--- Description:
--- . Reversed operation of dp_folder.
--- Remark:
--- . Use dp_deinterleave_one_to_n.vhd when:
--- - for 1 to N, so any N >= 1 (so not only powers of 2)
--- - when all sosi fields need to be preserved (so not only the valid)
--- - if flow control is needed
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+
+ -- Author:
+ -- . Daniel van der Schuur
+ -- Purpose:
+ -- . Unfold n input streams into n*2, n*2*2, n*2*2*2, .. output streams
+ -- Description:
+ -- . Reversed operation of dp_folder.
+ -- Remark:
+ -- . Use dp_deinterleave_one_to_n.vhd when:
+ -- - for 1 to N, so any N >= 1 (so not only powers of 2)
+ -- - when all sosi fields need to be preserved (so not only the valid)
+ -- - if flow control is needed
entity dp_unfolder is
generic (
@@ -142,8 +142,8 @@ begin
-- Wire the 2D demux output array to 1D array to match entity I/O type
-----------------------------------------------------------------------------
gen_demux_inputs_0: for i in 0 to c_nof_demuxes - 1 generate
- demux_src_out_arr(2 * i) <= demux_src_out_2arr_2(i)(0);
- demux_src_out_arr(2 * i + 1) <= demux_src_out_2arr_2(i)(1);
+ demux_src_out_arr(2 * i) <= demux_src_out_2arr_2(i)(0);
+ demux_src_out_arr(2 * i + 1) <= demux_src_out_2arr_2(i)(1);
end generate;
-----------------------------------------------------------------------------
@@ -180,16 +180,16 @@ begin
-----------------------------------------------------------------------------
gen_dp_pipeline : for i in 0 to c_nof_outputs - 1 generate
u_dp_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => 0 + (pow2(g_nof_unfolds) - i rem pow2(g_nof_unfolds) - 1)
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => dp_pipeline_snk_in_arr(i),
- src_out => dp_block_gen_snk_in_arr(i)
- );
+ generic map (
+ g_pipeline => 0 + (pow2(g_nof_unfolds) - i rem pow2(g_nof_unfolds) - 1)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => dp_pipeline_snk_in_arr(i),
+ src_out => dp_block_gen_snk_in_arr(i)
+ );
end generate;
end generate;
@@ -203,20 +203,20 @@ begin
gen_ctrl : if g_output_block_size > 0 generate
gen_dp_block_gen : for i in 0 to c_nof_outputs - 1 generate
u_dp_block_gen : entity work.dp_block_gen
- generic map (
- g_use_src_in => false,
- g_nof_data => g_output_block_size,
- g_preserve_sync => true,
- g_preserve_bsn => true,
- g_preserve_channel => g_use_channel
- )
- port map(
- rst => rst,
- clk => clk,
-
- snk_in => dp_block_gen_snk_in_arr(i),
- src_out => dp_block_gen_src_out_arr(i)
- );
+ generic map (
+ g_use_src_in => false,
+ g_nof_data => g_output_block_size,
+ g_preserve_sync => true,
+ g_preserve_bsn => true,
+ g_preserve_channel => g_use_channel
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ snk_in => dp_block_gen_snk_in_arr(i),
+ src_out => dp_block_gen_src_out_arr(i)
+ );
end generate;
end generate;
@@ -230,20 +230,20 @@ begin
gen_sync_bsn : if g_fwd_sync_bsn = true generate
gen_dp_fifo_info: for i in 0 to c_nof_outputs - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
- generic map (
- g_use_sync => true,
- g_use_bsn => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in_arr(0), -- original snk_in info
-
- src_in => c_dp_siso_rdy,
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_use_sync => true,
+ g_use_bsn => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
+ info_snk_in => snk_in_arr(0), -- original snk_in info
+
+ src_in => c_dp_siso_rdy,
+ src_out => src_out_arr(i)
+ );
end generate;
end generate;
@@ -251,8 +251,8 @@ begin
src_out_arr <= dp_block_gen_src_out_arr;
end generate;
- end generate;
- end generate;
+ end generate;
+ end generate;
-----------------------------------------------------------------------------
-- Wire output to input if g_nof_unfolds=0
diff --git a/libraries/base/dp/src/vhdl/dp_unframe.vhd b/libraries/base/dp/src/vhdl/dp_unframe.vhd
index 2e9d0f5b21..66082294d4 100644
--- a/libraries/base/dp/src/vhdl/dp_unframe.vhd
+++ b/libraries/base/dp/src/vhdl/dp_unframe.vhd
@@ -20,35 +20,35 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_packetizing_pkg.all;
-
--- Reuse from LOFAR rad_unframe.vhd and rad_unframe(rtl).vhd
-
--- Purpose:
--- Extract the payload data from a frame:
--- -----------------------
--- | fsn | dat ... | brc |
--- -----------------------
--- sof eof
--- val val ... val
--- and output the frame fsn and brc information as signals:
--- . dat[]
--- . fsn[]
--- . sync
--- . val
--- . sof
--- . eof
--- . sof_sync
---
--- Description:
--- The dp_unframe is the reverse of dp_frame. The output sof and eof mark the
--- start and end of the output dat. The output fsn signal is valid at the
--- output sof and remains valid. The output sync is a pulse and is valid one
--- cycle before output sof. The output err signal reflects the brc value and
--- is valid at the output eof and set to 0 at the next input sof.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_packetizing_pkg.all;
+
+ -- Reuse from LOFAR rad_unframe.vhd and rad_unframe(rtl).vhd
+
+ -- Purpose:
+ -- Extract the payload data from a frame:
+ -- -----------------------
+ -- | fsn | dat ... | brc |
+ -- -----------------------
+ -- sof eof
+ -- val val ... val
+ -- and output the frame fsn and brc information as signals:
+ -- . dat[]
+ -- . fsn[]
+ -- . sync
+ -- . val
+ -- . sof
+ -- . eof
+ -- . sof_sync
+ --
+ -- Description:
+ -- The dp_unframe is the reverse of dp_frame. The output sof and eof mark the
+ -- start and end of the output dat. The output fsn signal is valid at the
+ -- output sof and remains valid. The output sync is a pulse and is valid one
+ -- cycle before output sof. The output err signal reflects the brc value and
+ -- is valid at the output eof and set to 0 at the next input sof.
entity dp_unframe is
generic (
@@ -73,12 +73,12 @@ entity dp_unframe is
out_eof : out std_logic;
out_err : out std_logic
);
-begin
--- synthesis translate_off
+ begin
+ -- synthesis translate_off
assert g_fsn_w <= g_dat_w
- report "g_fsn_w must be smaller than or equal to g_dat_w"
- severity ERROR;
--- synthesis translate_on
+ report "g_fsn_w must be smaller than or equal to g_dat_w"
+ severity ERROR;
+ -- synthesis translate_on
end dp_unframe;
architecture rtl of dp_unframe is
diff --git a/libraries/base/dp/src/vhdl/dp_validate.vhd b/libraries/base/dp/src/vhdl/dp_validate.vhd
index 763676ec42..255558f13a 100644
--- a/libraries/base/dp/src/vhdl/dp_validate.vhd
+++ b/libraries/base/dp/src/vhdl/dp_validate.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
--- Purpose:
--- Assert valid, sop and eop only when they are valid.
--- Description:
--- . Assert valid regarding the ready latency
--- . Assert sop and eop only when valid is active
--- . Pass the SOSI data signals on as wires
--- . If g_boolean_error=TRUE then vector-OR the snk_in.err into a bit 0 of
--- src_out.err, where '0' = OK and '1' = error.
--- Remark:
--- . All assignments are combinatorial, so no clock latency
+ -- Purpose:
+ -- Assert valid, sop and eop only when they are valid.
+ -- Description:
+ -- . Assert valid regarding the ready latency
+ -- . Assert sop and eop only when valid is active
+ -- . Pass the SOSI data signals on as wires
+ -- . If g_boolean_error=TRUE then vector-OR the snk_in.err into a bit 0 of
+ -- src_out.err, where '0' = OK and '1' = error.
+ -- Remark:
+ -- . All assignments are combinatorial, so no clock latency
entity dp_validate is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
index a12132a9ea..43ef19d586 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
@@ -47,10 +47,10 @@
-- data is carried via the sosi array dimension.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_wideband_sp_arr_scope is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
index fcedf58750..588f416cf5 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
@@ -40,9 +40,9 @@
-- field or in the (re, im) fields.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_wideband_wb_arr_scope is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff.vhd b/libraries/base/dp/src/vhdl/dp_xonoff.vhd
index e9768eda7a..5773a11c83 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff.vhd
@@ -92,8 +92,8 @@
-- . Originally based on rad_frame_onoff from LOFAR RSP firmware
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
entity dp_xonoff is
generic (
@@ -184,4 +184,4 @@ begin
out_sosi.eop <= in_sosi.eop and i_out_en;
end process;
end generate;
-end architecture;
+ end architecture;
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd b/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
index 7690cbfe3f..04b83b9989 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
@@ -33,9 +33,9 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_xonoff_reg is
generic (
@@ -58,11 +58,12 @@ entity dp_xonoff_reg is
end dp_xonoff_reg;
architecture str of dp_xonoff_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => g_default_value);
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => g_default_value);
signal mm_xonoff_reg : std_logic_vector(0 downto 0);
begin
@@ -84,12 +85,12 @@ begin
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
when 0 =>
- mm_xonoff_reg(0) <= sla_in.wrdata(0);
+ mm_xonoff_reg(0) <= sla_in.wrdata(0);
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -105,15 +106,15 @@ begin
end process;
u_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
- in_dat => mm_xonoff_reg,
+ in_dat => mm_xonoff_reg,
- out_rst => st_rst,
- out_clk => st_clk,
+ out_rst => st_rst,
+ out_clk => st_clk,
- out_dat => xonoff_reg
- );
+ out_dat => xonoff_reg
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd b/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
index 4fd64c8f6e..caed1a1287 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
@@ -33,9 +33,9 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_xonoff_reg_timeout is
generic (
@@ -60,11 +60,12 @@ entity dp_xonoff_reg_timeout is
end dp_xonoff_reg_timeout;
architecture str of dp_xonoff_reg_timeout is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => g_default_value);
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => g_default_value);
constant c_mm_max_counter : natural := sel_a_b(g_sim, g_mm_timeout * 50, g_mm_timeout * (50 * 10**6)); -- @50MHz
signal mm_xonoff_reg : std_logic_vector(0 downto 0);
@@ -99,14 +100,14 @@ begin
when 0 =>
mm_xonoff_reg(0) <= sla_in.wrdata(0);
if sla_in.wrdata(0) = '1' then
- cnt_clr <= '1';
- cnt_en <= '1';
+ cnt_clr <= '1';
+ cnt_en <= '1';
end if;
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -122,27 +123,27 @@ begin
end process;
u_counter : entity common_lib.common_counter
- generic map (
- g_latency => 0
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => counter
- );
+ generic map (
+ g_latency => 0
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => counter
+ );
u_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
- in_dat => mm_xonoff_reg_out,
+ in_dat => mm_xonoff_reg_out,
- out_rst => st_rst,
- out_clk => st_clk,
+ out_rst => st_rst,
+ out_clk => st_clk,
- out_dat => xonoff_reg
- );
+ out_dat => xonoff_reg
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
index 20456ab387..08dfd7964c 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
@@ -35,11 +35,11 @@
-- https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+BSN+aligner+v2
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mmp_dp_bsn_align_v2 is
generic (
@@ -116,29 +116,29 @@ architecture str of mmp_dp_bsn_align_v2 is
begin
-- MM control of BSN aligner
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => (others => '1') -- Default all g_nof_streams are enabled.
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_bsn_align_copi,
- sla_out => reg_bsn_align_cipo,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- out_reg => reg_wr, -- readback via ST clock domain
- in_reg => reg_rd
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => (others => '1') -- Default all g_nof_streams are enabled.
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_bsn_align_copi,
+ sla_out => reg_bsn_align_cipo,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ out_reg => reg_wr, -- readback via ST clock domain
+ in_reg => reg_rd
+ );
gen_reg : for I in 0 to g_nof_streams - 1 generate
stream_en_arr(I) <= sl(reg_wr(2 * I * c_word_w downto 2 * I * c_word_w));
@@ -155,58 +155,58 @@ begin
-- . all input streams (g_nof_input_bsn_monitors = g_nof_streams).
gen_bsn_mon_input : if g_nof_input_bsn_monitors > 0 generate
u_bsn_mon_input : entity work.mms_dp_bsn_monitor_v2
- generic map (
- g_nof_streams => g_nof_input_bsn_monitors,
- g_cross_clock_domain => true,
- g_sync_timeout => g_nof_clk_per_sync,
- g_bsn_w => g_bsn_w,
- g_error_bi => 0,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_cnt_latency_w => c_word_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_input_monitor_copi,
- reg_miso => reg_input_monitor_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ref_sync => ref_sync,
-
- in_sosi_arr => in_sosi_arr(g_nof_input_bsn_monitors - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_input_bsn_monitors,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_nof_clk_per_sync,
+ g_bsn_w => g_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_input_monitor_copi,
+ reg_miso => reg_input_monitor_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => ref_sync,
+
+ in_sosi_arr => in_sosi_arr(g_nof_input_bsn_monitors - 1 downto 0)
+ );
end generate;
gen_bsn_mon_output : if g_use_bsn_output_monitor generate
u_bsn_mon_output : entity work.mms_dp_bsn_monitor_v2
- generic map (
- g_nof_streams => 1, -- all outputs have same BSN monitor information
- g_cross_clock_domain => true,
- g_sync_timeout => g_nof_clk_per_sync,
- g_bsn_w => g_bsn_w,
- g_error_bi => 0,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_cnt_latency_w => c_word_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_output_monitor_copi,
- reg_miso => reg_output_monitor_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ref_sync => ref_sync,
-
- in_sosi_arr => mon_out_sosi_arr
- );
+ generic map (
+ g_nof_streams => 1, -- all outputs have same BSN monitor information
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_nof_clk_per_sync,
+ g_bsn_w => g_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_output_monitor_copi,
+ reg_miso => reg_output_monitor_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => ref_sync,
+
+ in_sosi_arr => mon_out_sosi_arr
+ );
end generate;
-- Use mm_sosi or out_sosi_arr(0) from BSN aligner for output BSN monitor
@@ -217,33 +217,33 @@ begin
out_sosi_arr <= i_out_sosi_arr;
u_bsn_align : entity work.dp_bsn_align_v2
- generic map (
- g_nof_streams => g_nof_streams,
- g_bsn_latency_max => g_bsn_latency_max,
- g_nof_aligners_max => g_nof_aligners_max,
- g_block_size => g_block_size,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_data_replacement_value => g_data_replacement_value,
- g_use_mm_output => g_use_mm_output,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_rd_latency => g_rd_latency
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- node_index => node_index,
- -- MM control
- stream_en_arr => stream_en_arr,
- stream_replaced_cnt_arr => stream_replaced_cnt_arr,
- -- Streaming input
- in_sosi_arr => in_sosi_arr,
- -- Output via local MM in dp_clk domain
- mm_sosi => i_mm_sosi,
- mm_copi => mm_copi,
- mm_cipo_arr => mm_cipo_arr,
- -- Output via streaming DP interface, when g_use_mm_output = TRUE.
- out_sosi_arr => i_out_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_bsn_latency_max => g_bsn_latency_max,
+ g_nof_aligners_max => g_nof_aligners_max,
+ g_block_size => g_block_size,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_data_replacement_value => g_data_replacement_value,
+ g_use_mm_output => g_use_mm_output,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_rd_latency => g_rd_latency
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ node_index => node_index,
+ -- MM control
+ stream_en_arr => stream_en_arr,
+ stream_replaced_cnt_arr => stream_replaced_cnt_arr,
+ -- Streaming input
+ in_sosi_arr => in_sosi_arr,
+ -- Output via local MM in dp_clk domain
+ mm_sosi => i_mm_sosi,
+ mm_copi => mm_copi,
+ mm_cipo_arr => mm_cipo_arr,
+ -- Output via streaming DP interface, when g_use_mm_output = TRUE.
+ out_sosi_arr => i_out_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
index 4cab59e25a..64db6aaafc 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
@@ -55,10 +55,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mmp_dp_bsn_sync_scheduler is
generic (
@@ -127,23 +127,23 @@ begin
-- . Write
wr_ctrl_enable <= reg_wr( 0);
ctrl_interval_size <= TO_UINT(reg_wr( 2 * c_word_w - 1 downto 1 * c_word_w)) when
- g_ctrl_interval_size_min < TO_UINT(reg_wr( 2 * c_word_w - 1 downto 1 * c_word_w)) else g_ctrl_interval_size_min;
+ g_ctrl_interval_size_min < TO_UINT(reg_wr( 2 * c_word_w - 1 downto 1 * c_word_w)) else g_ctrl_interval_size_min;
wr_start_bsn_64( c_word_w - 1 downto 0) <= reg_wr( 3 * c_word_w - 1 downto 2 * c_word_w); -- low word
wr_start_bsn_64(2 * c_word_w - 1 downto 1 * c_word_w) <= reg_wr( 4 * c_word_w - 1 downto 3 * c_word_w); -- high word
-- Derive ctrl_enable_evt from change in wr_ctrl_enable, instead of using
-- reg_wr_arr(0), see description
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_sig => wr_ctrl_enable,
- out_evt => wr_ctrl_enable_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_sig => wr_ctrl_enable,
+ out_evt => wr_ctrl_enable_evt
+ );
ctrl_enable <= wr_ctrl_enable when rising_edge(dp_clk) and wr_ctrl_enable_evt = '1';
ctrl_enable_evt <= wr_ctrl_enable_evt when rising_edge(dp_clk);
@@ -163,56 +163,56 @@ begin
reg_rd(12 * c_word_w - 1 downto 11 * c_word_w) <= TO_UVEC(g_block_size, c_word_w);
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => reg_wr_arr,
- reg_rd_arr => OPEN,
- out_reg => reg_wr, -- readback via ST clock domain
- in_reg => reg_rd
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => reg_wr_arr,
+ reg_rd_arr => OPEN,
+ out_reg => reg_wr, -- readback via ST clock domain
+ in_reg => reg_rd
+ );
u_dp_bsn_sync_scheduler : entity work.dp_bsn_sync_scheduler
- generic map (
- g_bsn_w => g_bsn_w,
- g_block_size => g_block_size,
- g_ctrl_interval_size_min => g_ctrl_interval_size_min,
- g_pipeline => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- M&C
- ctrl_enable => ctrl_enable,
- ctrl_enable_evt => ctrl_enable_evt,
- ctrl_interval_size => ctrl_interval_size,
- ctrl_start_bsn => ctrl_start_bsn,
- mon_current_input_bsn => mon_current_input_bsn,
- mon_input_bsn_at_sync => mon_input_bsn_at_sync,
- mon_output_enable => mon_output_enable,
- mon_output_interval_size => mon_output_interval_size,
- mon_output_sync_bsn => mon_output_sync_bsn,
-
- -- Streaming
- in_sosi => in_sosi,
- out_sosi => out_sosi,
- out_start => out_start,
- out_start_interval => out_start_interval,
- out_enable => out_enable
- );
+ generic map (
+ g_bsn_w => g_bsn_w,
+ g_block_size => g_block_size,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min,
+ g_pipeline => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- M&C
+ ctrl_enable => ctrl_enable,
+ ctrl_enable_evt => ctrl_enable_evt,
+ ctrl_interval_size => ctrl_interval_size,
+ ctrl_start_bsn => ctrl_start_bsn,
+ mon_current_input_bsn => mon_current_input_bsn,
+ mon_input_bsn_at_sync => mon_input_bsn_at_sync,
+ mon_output_enable => mon_output_enable,
+ mon_output_interval_size => mon_output_interval_size,
+ mon_output_sync_bsn => mon_output_sync_bsn,
+
+ -- Streaming
+ in_sosi => in_sosi,
+ out_sosi => out_sosi,
+ out_start => out_start,
+ out_start_interval => out_start_interval,
+ out_enable => out_enable
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
index 85a154fa94..176e80286a 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
@@ -25,10 +25,10 @@
-- Remarks: See mmp_dp_bsn_sync_scheduler.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mmp_dp_bsn_sync_scheduler_arr is
generic (
@@ -66,42 +66,42 @@ architecture str of mmp_dp_bsn_sync_scheduler_arr is
begin
-- dp_bsn_sync_scheduler
u_mmp_dp_bsn_sync_scheduler : entity work.mmp_dp_bsn_sync_scheduler
- generic map (
- g_bsn_w => g_bsn_w,
- g_block_size => g_block_size,
- g_ctrl_interval_size_min => g_ctrl_interval_size_min
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_bsn_w => g_bsn_w,
+ g_block_size => g_block_size,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
- in_sosi => in_sosi_arr(0),
- out_sosi => single_src_out,
+ in_sosi => in_sosi_arr(0),
+ out_sosi => single_src_out,
- out_start => out_start,
- out_start_interval => out_start_interval,
- out_enable => out_enable
- );
+ out_start => out_start,
+ out_start_interval => out_start_interval,
+ out_enable => out_enable
+ );
-- Pipeline in_sosi_arr to compensate for the latency in mmp_dp_bsn_sync_scheduler
u_dp_pipeline_arr : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_out_arr => in_sosi_arr_piped
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_out_arr => in_sosi_arr_piped
+ );
p_streams : process(in_sosi_arr_piped, single_src_out)
begin
diff --git a/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd b/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
index 336f7e5565..93950da499 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
@@ -30,12 +30,12 @@
-- The index_lo and index_hi can be read and set via the MM interface.
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_block_select is
generic (
@@ -62,8 +62,9 @@ entity mms_dp_block_select is
end mms_dp_block_select;
architecture str of mms_dp_block_select is
- constant c_field_arr : t_common_field_arr(1 downto 0) := ( (field_name_pad("index_hi"), "RW", 32, field_default(g_index_hi) ),
- (field_name_pad("index_lo"), "RW", 32, field_default(g_index_lo) ));
+ constant c_field_arr : t_common_field_arr(
+ 1 downto 0) := ( (field_name_pad("index_hi"), "RW", 32, field_default(g_index_hi) ),
+ (field_name_pad("index_lo"), "RW", 32, field_default(g_index_lo) ));
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_field_arr) - 1 downto 0);
@@ -72,46 +73,46 @@ architecture str of mms_dp_block_select is
begin
-- Use same control for all streams
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi,
- mm_miso => reg_miso,
+ mm_mosi => reg_mosi,
+ mm_miso => reg_miso,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
index_lo <= TO_UINT(mm_fields_out(field_hi(c_field_arr, "index_lo") downto field_lo(c_field_arr, "index_lo")));
index_hi <= TO_UINT(mm_fields_out(field_hi(c_field_arr, "index_hi") downto field_lo(c_field_arr, "index_hi")));
gen_dp_block_select : for I in 0 to g_nof_streams - 1 generate
u_dp_block_select : entity work.dp_block_select
- generic map (
- g_nof_blocks_per_sync => g_nof_blocks_per_sync,
- g_index_lo => g_index_lo,
- g_index_hi => g_index_hi
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- Control
- index_lo => index_lo,
- index_hi => index_hi,
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
- );
+ generic map (
+ g_nof_blocks_per_sync => g_nof_blocks_per_sync,
+ g_index_lo => g_index_lo,
+ g_index_hi => g_index_hi
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Control
+ index_lo => index_lo,
+ index_hi => index_hi,
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
index fd265dbd40..896da17a1c 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
@@ -20,14 +20,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose : MMS for dp_bsn_aligner
--- Description: See dp_bsn_aligner.vhd
+ -- Purpose : MMS for dp_bsn_aligner
+ -- Description: See dp_bsn_aligner.vhd
entity mms_dp_bsn_align is
generic (
@@ -64,47 +64,47 @@ architecture str of mms_dp_bsn_align is
signal en_arr : std_logic_vector(g_nof_input - 1 downto 0);
begin
u_align : entity work.dp_bsn_align
- generic map(
- g_block_size => g_block_size,
- g_block_period => g_block_period,
- g_nof_input => g_nof_input,
- g_xoff_timeout => g_xoff_timeout,
- g_sop_timeout => g_sop_timeout,
- g_bsn_latency => g_bsn_latency,
- g_bsn_request_pipeline => g_bsn_request_pipeline
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- -- ST sinks
- snk_out_arr => snk_out_arr,
- snk_in_arr => snk_in_arr,
- -- ST source
- src_in_arr => src_in_arr,
- src_out_arr => src_out_arr,
- -- MM
- in_en_evt => en_evt,
- in_en_arr => en_arr
- );
+ generic map(
+ g_block_size => g_block_size,
+ g_block_period => g_block_period,
+ g_nof_input => g_nof_input,
+ g_xoff_timeout => g_xoff_timeout,
+ g_sop_timeout => g_sop_timeout,
+ g_bsn_latency => g_bsn_latency,
+ g_bsn_request_pipeline => g_bsn_request_pipeline
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sinks
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ -- ST source
+ src_in_arr => src_in_arr,
+ src_out_arr => src_out_arr,
+ -- MM
+ in_en_evt => en_evt,
+ in_en_arr => en_arr
+ );
u_reg : entity work.dp_bsn_align_reg
- generic map (
- g_nof_input => g_nof_input,
- g_cross_clock_domain => g_cross_clock_domain
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_nof_input => g_nof_input,
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- out_en_evt => en_evt,
- out_en_arr => en_arr
- );
+ -- MM registers in st_clk domain
+ out_en_evt => en_evt,
+ out_en_arr => en_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
index 645f43333f..d093f3376a 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
@@ -20,14 +20,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose : MMS for dp_bsn_monitor
--- Description: See dp_bsn_monitor.vhd
+ -- Purpose : MMS for dp_bsn_monitor
+ -- Description: See dp_bsn_monitor.vhd
entity mms_dp_bsn_monitor is
generic (
@@ -81,82 +81,82 @@ architecture str of mms_dp_bsn_monitor is
signal reg_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
-
- gen_stream : for i in 0 to g_nof_streams - 1 generate
- u_reg : entity work.dp_bsn_monitor_reg
generic map (
- g_cross_clock_domain => g_cross_clock_domain
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
)
port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
-
- -- MM registers in dp_clk domain
- -- . control
- mon_evt => mon_evt_arr(i),
- mon_sync_timeout => mon_sync_timeout_arr(i),
- -- . siso
- mon_ready_stable => mon_ready_stable_arr(i),
- mon_xon_stable => mon_xon_stable_arr(i),
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
- mon_nof_sop => mon_nof_sop_arr(i),
- mon_nof_err => mon_nof_err_arr(i),
- mon_nof_valid => mon_nof_valid_arr(i),
-
- mon_bsn_first => mon_bsn_first_arr(i),
- mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt_arr(i)
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
);
+ gen_stream : for i in 0 to g_nof_streams - 1 generate
+ u_reg : entity work.dp_bsn_monitor_reg
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ mon_evt => mon_evt_arr(i),
+ mon_sync_timeout => mon_sync_timeout_arr(i),
+ -- . siso
+ mon_ready_stable => mon_ready_stable_arr(i),
+ mon_xon_stable => mon_xon_stable_arr(i),
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
+ mon_nof_sop => mon_nof_sop_arr(i),
+ mon_nof_err => mon_nof_err_arr(i),
+ mon_nof_valid => mon_nof_valid_arr(i),
+
+ mon_bsn_first => mon_bsn_first_arr(i),
+ mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt_arr(i)
+ );
+
u_mon : entity work.dp_bsn_monitor
- generic map (
- g_sync_timeout => g_sync_timeout,
- g_error_bi => g_error_bi,
- g_log_first_bsn => g_log_first_bsn
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- ST interface
- in_siso => in_siso_arr(i),
- in_sosi => in_sosi_arr(i),
- sync_in => sync_in,
-
- -- MM interface
- -- . control
- mon_evt => mon_evt_arr(i), -- pulses when new monitor data is available regarding the previous sync interval
- mon_sync => OPEN,
- mon_sync_timeout => mon_sync_timeout_arr(i),
- -- . siso
- mon_ready_stable => mon_ready_stable_arr(i),
- mon_xon_stable => mon_xon_stable_arr(i),
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
- mon_nof_sop => mon_nof_sop_arr(i),
- mon_nof_err => mon_nof_err_arr(i),
- mon_nof_valid => mon_nof_valid_arr(i),
-
- mon_bsn_first => mon_bsn_first_arr(i),
- mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt_arr(i)
- );
+ generic map (
+ g_sync_timeout => g_sync_timeout,
+ g_error_bi => g_error_bi,
+ g_log_first_bsn => g_log_first_bsn
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- ST interface
+ in_siso => in_siso_arr(i),
+ in_sosi => in_sosi_arr(i),
+ sync_in => sync_in,
+
+ -- MM interface
+ -- . control
+ mon_evt => mon_evt_arr(i), -- pulses when new monitor data is available regarding the previous sync interval
+ mon_sync => OPEN,
+ mon_sync_timeout => mon_sync_timeout_arr(i),
+ -- . siso
+ mon_ready_stable => mon_ready_stable_arr(i),
+ mon_xon_stable => mon_xon_stable_arr(i),
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
+ mon_nof_sop => mon_nof_sop_arr(i),
+ mon_nof_err => mon_nof_err_arr(i),
+ mon_nof_valid => mon_nof_valid_arr(i),
+
+ mon_bsn_first => mon_bsn_first_arr(i),
+ mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt_arr(i)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
index 5ba8560094..98b483f78d 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
@@ -24,12 +24,12 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_components_pkg.all;
entity mms_dp_bsn_monitor_v2 is
generic (
@@ -83,77 +83,77 @@ architecture str of mms_dp_bsn_monitor_v2 is
signal reg_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
-
- gen_stream : for i in 0 to g_nof_streams - 1 generate
- u_reg : entity work.dp_bsn_monitor_reg_v2
generic map (
- g_cross_clock_domain => g_cross_clock_domain
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
)
port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
-
- -- MM registers in dp_clk domain
- -- . control
- mon_evt => mon_evt_arr(i),
- mon_sync_timeout => mon_sync_timeout_arr(i),
- -- . siso
- mon_ready_stable => mon_ready_stable_arr(i),
- mon_xon_stable => mon_xon_stable_arr(i),
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
- mon_nof_sop => mon_nof_sop_arr(i),
- mon_nof_err => mon_nof_err_arr(i),
- mon_nof_valid => mon_nof_valid_arr(i),
- mon_latency => mon_latency_arr(i)
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
);
+ gen_stream : for i in 0 to g_nof_streams - 1 generate
+ u_reg : entity work.dp_bsn_monitor_reg_v2
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ mon_evt => mon_evt_arr(i),
+ mon_sync_timeout => mon_sync_timeout_arr(i),
+ -- . siso
+ mon_ready_stable => mon_ready_stable_arr(i),
+ mon_xon_stable => mon_xon_stable_arr(i),
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
+ mon_nof_sop => mon_nof_sop_arr(i),
+ mon_nof_err => mon_nof_err_arr(i),
+ mon_nof_valid => mon_nof_valid_arr(i),
+ mon_latency => mon_latency_arr(i)
+ );
+
u_mon : entity work.dp_bsn_monitor_v2
- generic map (
- g_sync_timeout => g_sync_timeout,
- g_error_bi => g_error_bi
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- ST interface
- in_siso => in_siso_arr(i),
- in_sosi => in_sosi_arr(i),
- ref_sync => ref_sync,
-
- -- MM interface
- -- . control
- mon_evt => mon_evt_arr(i), -- pulses when new monitor data is available regarding the previous sync interval
- mon_sync => OPEN,
- mon_sync_timeout => mon_sync_timeout_arr(i),
- -- . siso
- mon_ready_stable => mon_ready_stable_arr(i),
- mon_xon_stable => mon_xon_stable_arr(i),
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
- mon_nof_sop => mon_nof_sop_arr(i),
- mon_nof_err => mon_nof_err_arr(i),
- mon_nof_valid => mon_nof_valid_arr(i),
- mon_latency => mon_latency_arr(i)
- );
+ generic map (
+ g_sync_timeout => g_sync_timeout,
+ g_error_bi => g_error_bi
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- ST interface
+ in_siso => in_siso_arr(i),
+ in_sosi => in_sosi_arr(i),
+ ref_sync => ref_sync,
+
+ -- MM interface
+ -- . control
+ mon_evt => mon_evt_arr(i), -- pulses when new monitor data is available regarding the previous sync interval
+ mon_sync => OPEN,
+ mon_sync_timeout => mon_sync_timeout_arr(i),
+ -- . siso
+ mon_ready_stable => mon_ready_stable_arr(i),
+ mon_xon_stable => mon_xon_stable_arr(i),
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
+ mon_nof_sop => mon_nof_sop_arr(i),
+ mon_nof_err => mon_nof_err_arr(i),
+ mon_nof_valid => mon_nof_valid_arr(i),
+ mon_latency => mon_latency_arr(i)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
index bf03acd736..c176bc0419 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
@@ -20,14 +20,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose : MMS for dp_bsn_scheduler
--- Description: See dp_bsn_scheduler.vhd
+ -- Purpose : MMS for dp_bsn_scheduler
+ -- Description: See dp_bsn_scheduler.vhd
entity mms_dp_bsn_scheduler is
generic (
@@ -55,36 +55,36 @@ architecture str of mms_dp_bsn_scheduler is
signal scheduled_bsn : std_logic_vector(g_bsn_w - 1 downto 0) := (others => '0');
begin
u_mm_reg : entity work.dp_bsn_scheduler_reg
- generic map (
- g_cross_clock_domain => g_cross_clock_domain
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in dp_clk domain
- st_current_bsn => snk_in.bsn,
- st_scheduled_bsn => scheduled_bsn
- );
+ -- MM registers in dp_clk domain
+ st_current_bsn => snk_in.bsn,
+ st_scheduled_bsn => scheduled_bsn
+ );
u_bsn_scheduler : entity work.dp_bsn_scheduler
- generic map (
- g_bsn_w => g_bsn_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- MM control
- scheduled_bsn => scheduled_bsn,
- -- Streaming
- snk_in => snk_in,
- trigger_out => trigger_out
- );
+ generic map (
+ g_bsn_w => g_bsn_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- MM control
+ scheduled_bsn => scheduled_bsn,
+ -- Streaming
+ snk_in => snk_in,
+ trigger_out => trigger_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
index 9b7f13a519..caea7b8ac4 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
@@ -23,10 +23,10 @@
-- Description: See dp_bsn_source.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_bsn_source is
generic (
@@ -67,49 +67,49 @@ begin
bs_sosi <= i_bs_sosi;
u_mm_reg : entity work.dp_bsn_source_reg
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_nof_block_per_sync => g_nof_block_per_sync
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_nof_block_per_sync => g_nof_block_per_sync
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- st_on => dp_on,
- st_on_pps => dp_on_pps,
- st_on_status => dp_on_status,
- st_nof_block_per_sync => nof_block_per_sync,
- st_init_bsn => init_bsn,
- st_current_bsn => capture_bsn
- );
+ -- MM registers in st_clk domain
+ st_on => dp_on,
+ st_on_pps => dp_on_pps,
+ st_on_status => dp_on_status,
+ st_nof_block_per_sync => nof_block_per_sync,
+ st_init_bsn => init_bsn,
+ st_current_bsn => capture_bsn
+ );
u_bsn_source : entity work.dp_bsn_source
- generic map (
- g_block_size => g_block_size,
- g_nof_block_per_sync => g_nof_block_per_sync,
- g_bsn_w => g_bsn_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- pps => dp_pps,
- -- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
- dp_on_status => dp_on_status,
- init_bsn => init_bsn,
- nof_block_per_sync => nof_block_per_sync,
- -- Streaming
- src_out => i_bs_sosi
- );
+ generic map (
+ g_block_size => g_block_size,
+ g_nof_block_per_sync => g_nof_block_per_sync,
+ g_bsn_w => g_bsn_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ pps => dp_pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+ dp_on_status => dp_on_status,
+ init_bsn => init_bsn,
+ nof_block_per_sync => nof_block_per_sync,
+ -- Streaming
+ src_out => i_bs_sosi
+ );
--capture_bsn <= i_bs_sosi.bsn; -- capture current BSN
--capture_bsn <= i_bs_sosi.bsn WHEN rising_edge(dp_clk) AND dp_pps='1'; -- capture BSN at external PPS
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
index 92388ecf1e..d88e0fdfcb 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
@@ -23,10 +23,10 @@
-- Description: See dp_bsn_source.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_bsn_source_v2 is
generic (
@@ -74,53 +74,53 @@ begin
bs_nof_clk_per_sync <= nof_clk_per_sync;
u_mm_reg : entity work.dp_bsn_source_reg_v2
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_nof_clk_per_sync => g_nof_clk_per_sync
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_nof_clk_per_sync => g_nof_clk_per_sync
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- st_on => dp_on,
- st_on_pps => dp_on_pps,
- st_on_status => dp_on_status,
- st_nof_clk_per_sync => nof_clk_per_sync,
- st_bsn_init => bsn_init,
- st_current_bsn => capture_bsn,
- st_bsn_time_offset => bsn_time_offset
- );
+ -- MM registers in st_clk domain
+ st_on => dp_on,
+ st_on_pps => dp_on_pps,
+ st_on_status => dp_on_status,
+ st_nof_clk_per_sync => nof_clk_per_sync,
+ st_bsn_init => bsn_init,
+ st_current_bsn => capture_bsn,
+ st_bsn_time_offset => bsn_time_offset
+ );
u_bsn_source : entity work.dp_bsn_source_v2
- generic map (
- g_block_size => g_block_size,
- g_nof_clk_per_sync => g_nof_clk_per_sync,
- g_bsn_w => g_bsn_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- pps => dp_pps,
- -- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
- dp_on_status => dp_on_status,
- bs_restart => bs_restart,
- bs_new_interval => bs_new_interval,
- bsn_init => bsn_init,
- nof_clk_per_sync => nof_clk_per_sync,
- bsn_time_offset => bsn_time_offset,
- -- Streaming
- src_out => i_bs_sosi
- );
+ generic map (
+ g_block_size => g_block_size,
+ g_nof_clk_per_sync => g_nof_clk_per_sync,
+ g_bsn_w => g_bsn_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ pps => dp_pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+ dp_on_status => dp_on_status,
+ bs_restart => bs_restart,
+ bs_new_interval => bs_new_interval,
+ bsn_init => bsn_init,
+ nof_clk_per_sync => nof_clk_per_sync,
+ bsn_time_offset => bsn_time_offset,
+ -- Streaming
+ src_out => i_bs_sosi
+ );
capture_bsn <= i_bs_sosi.bsn when rising_edge(dp_clk) and i_bs_sosi.sync = '1'; -- capture BSN at internal sync
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
index 4cc0b97ba5..a1d9af3b57 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
@@ -27,12 +27,12 @@
-- Remarks:
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_dp_fifo_fill is
generic (
@@ -67,9 +67,9 @@ entity mms_dp_fifo_fill is
dp_clk : in std_logic;
-- Monitor FIFO filling
--- wr_ful : OUT STD_LOGIC;
--- usedw : OUT STD_LOGIC_VECTOR(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2))-1 DOWNTO 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
--- rd_emp : OUT STD_LOGIC;
+ -- wr_ful : OUT STD_LOGIC;
+ -- usedw : OUT STD_LOGIC_VECTOR(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2))-1 DOWNTO 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ -- rd_emp : OUT STD_LOGIC;
-- ST sink
snk_out_arr : out t_dp_siso_arr(g_nof_streams - 1 downto 0);
@@ -89,59 +89,59 @@ architecture str of mms_dp_fifo_fill is
begin
gen_fifos : for I in 0 to g_nof_streams - 1 generate
dp_fifo_sc : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful_reg(I),
- usedw => fifo_usedw_reg(I * c_word_w + c_usedw_w - 1 downto I * c_word_w),
- rd_emp => rd_emp_reg(I),
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful_reg(I),
+ usedw => fifo_usedw_reg(I * c_word_w + c_usedw_w - 1 downto I * c_word_w),
+ rd_emp => rd_emp_reg(I),
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
u_reg : entity work.dp_fifo_fill_reg
- generic map(
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => g_cross_clock_domain
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- used_w => fifo_usedw_reg,
- rd_emp => rd_emp_reg,
- wr_ful => wr_ful_reg
- );
+ -- MM registers in st_clk domain
+ used_w => fifo_usedw_reg,
+ rd_emp => rd_emp_reg,
+ wr_ful => wr_ful_reg
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
index 8298bcacd5..ee93f70e8a 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity mms_dp_fifo_from_mm is
generic (
@@ -54,33 +54,33 @@ architecture str of mms_dp_fifo_from_mm is
signal mm_wr : std_logic;
begin
u_dp_fifo_from_mm : entity dp_lib.dp_fifo_from_mm
- generic map(
- g_fifo_size => g_wr_fifo_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
+ generic map(
+ g_fifo_size => g_wr_fifo_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
- src_out => wr_sosi,
- usedw => wr_usedw, -- used words from rd FIFO
+ src_out => wr_sosi,
+ usedw => wr_usedw, -- used words from rd FIFO
- mm_wr => mm_wr,
- mm_wrdata => mm_wr_data,
- mm_usedw => mm_wr_usedw, -- resized to 32 bits
- mm_availw => mm_wr_availw -- resized to 32 bits
- );
+ mm_wr => mm_wr,
+ mm_wrdata => mm_wr_data,
+ mm_usedw => mm_wr_usedw, -- resized to 32 bits
+ mm_availw => mm_wr_availw -- resized to 32 bits
+ );
u_dp_fifo_from_mm_reg: entity work.dp_fifo_from_mm_reg
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- sla_in => ctrl_mosi,
- sla_out => ctrl_miso,
+ sla_in => ctrl_mosi,
+ sla_out => ctrl_miso,
- mm_wr_usedw => mm_wr_usedw,
- mm_wr_availw => mm_wr_availw
- );
+ mm_wr_usedw => mm_wr_usedw,
+ mm_wr_availw => mm_wr_availw
+ );
mm_wr_data <= data_mosi.wrdata(c_word_w - 1 downto 0);
mm_wr <= data_mosi.wr;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
index 982363aafe..2112db2629 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity mms_dp_fifo_to_mm is
generic (
@@ -56,33 +56,33 @@ architecture str of mms_dp_fifo_to_mm is
signal mm_rd : std_logic;
begin
u_dp_fifo_to_mm : entity dp_lib.dp_fifo_to_mm
- generic map(
- g_fifo_size => g_rd_fifo_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
+ generic map(
+ g_fifo_size => g_rd_fifo_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
- snk_out => rd_siso,
- snk_in => rd_sosi,
- usedw => rd_usedw, -- used words from rd FIFO
+ snk_out => rd_siso,
+ snk_in => rd_sosi,
+ usedw => rd_usedw, -- used words from rd FIFO
- mm_rd => mm_rd,
- mm_rddata => mm_rd_data,
- mm_rdval => mm_rd_val,
- mm_usedw => mm_rd_usedw -- resized to 32 bits
- );
+ mm_rd => mm_rd,
+ mm_rddata => mm_rd_data,
+ mm_rdval => mm_rd_val,
+ mm_usedw => mm_rd_usedw -- resized to 32 bits
+ );
u_dp_fifo_to_mm_reg: entity work.dp_fifo_to_mm_reg
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- sla_in => ctrl_mosi,
- sla_out => ctrl_miso,
+ sla_in => ctrl_mosi,
+ sla_out => ctrl_miso,
- mm_rd_usedw => mm_rd_usedw
- );
+ mm_rd_usedw => mm_rd_usedw
+ );
data_miso.rddata(c_word_w - 1 downto 0) <= mm_rd_data;
data_miso.rdval <= mm_rd_val;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
index 78ef7e85f0..b53b22ac4a 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
@@ -33,10 +33,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_force_data_parallel is
generic (
@@ -102,59 +102,59 @@ begin
reg_force_data_rd(4 * c_mm_reg.dat_w - 1 downto 3 * c_mm_reg.dat_w) <= reg_force_data_wr(4 * c_mm_reg.dat_w - 1 downto 3 * c_mm_reg.dat_w);
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => c_mm_reg_init
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => c_mm_reg_init
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_force_data_mosi,
- sla_out => reg_force_data_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_force_data_mosi,
+ sla_out => reg_force_data_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- out_reg => reg_force_data_wr, -- readback via ST clock domain
- in_reg => reg_force_data_rd
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ out_reg => reg_force_data_wr, -- readback via ST clock domain
+ in_reg => reg_force_data_rd
+ );
u_dp_force_data_parallel : entity work.dp_force_data_parallel
- generic map (
- g_dat_w => g_dat_w,
- g_increment_data => g_increment_data,
- g_increment_re => g_increment_re,
- g_increment_im => g_increment_im,
- g_increment_data_on_sop => g_increment_data_on_sop,
- g_increment_re_on_sop => g_increment_re_on_sop,
- g_increment_im_on_sop => g_increment_im_on_sop,
- g_restart_data_on_sync => g_restart_data_on_sync,
- g_restart_re_on_sync => g_restart_re_on_sync,
- g_restart_im_on_sync => g_restart_im_on_sync,
- g_restart_data_on_sop => g_restart_data_on_sop,
- g_restart_re_on_sop => g_restart_re_on_sop,
- g_restart_im_on_sop => g_restart_im_on_sop
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- MM control
- force_en => force_en,
- force_data => force_data,
- force_re => force_re,
- force_im => force_im,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_dat_w => g_dat_w,
+ g_increment_data => g_increment_data,
+ g_increment_re => g_increment_re,
+ g_increment_im => g_increment_im,
+ g_increment_data_on_sop => g_increment_data_on_sop,
+ g_increment_re_on_sop => g_increment_re_on_sop,
+ g_increment_im_on_sop => g_increment_im_on_sop,
+ g_restart_data_on_sync => g_restart_data_on_sync,
+ g_restart_re_on_sync => g_restart_re_on_sync,
+ g_restart_im_on_sync => g_restart_im_on_sync,
+ g_restart_data_on_sop => g_restart_data_on_sop,
+ g_restart_re_on_sop => g_restart_re_on_sop,
+ g_restart_im_on_sop => g_restart_im_on_sop
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- MM control
+ force_en => force_en,
+ force_data => force_data,
+ force_re => force_re,
+ force_im => force_im,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
index 405a23ba8e..53add18b98 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
@@ -34,10 +34,10 @@
-- etc.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_force_data_parallel_arr is
generic (
@@ -81,48 +81,48 @@ architecture str of mms_dp_force_data_parallel_arr is
signal reg_force_data_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
begin
u_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_mm_reg_adr_w
- )
- port map (
- mosi => reg_force_data_mosi,
- miso => reg_force_data_miso,
- mosi_arr => reg_force_data_mosi_arr,
- miso_arr => reg_force_data_miso_arr
- );
-
- gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
- u_mms_dp_force_data_parallel : entity work.mms_dp_force_data_parallel
generic map (
- g_dat_w => g_dat_w,
- g_increment_data => g_increment_data,
- g_increment_re => g_increment_re,
- g_increment_im => g_increment_im,
- g_increment_data_on_sop => g_increment_data_on_sop,
- g_increment_re_on_sop => g_increment_re_on_sop,
- g_increment_im_on_sop => g_increment_im_on_sop,
- g_restart_data_on_sync => g_restart_data_on_sync,
- g_restart_re_on_sync => g_restart_re_on_sync,
- g_restart_im_on_sync => g_restart_im_on_sync,
- g_restart_data_on_sop => g_restart_data_on_sop,
- g_restart_re_on_sop => g_restart_re_on_sop,
- g_restart_im_on_sop => g_restart_im_on_sop
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_mm_reg_adr_w
)
port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM control
- reg_force_data_mosi => reg_force_data_mosi_arr(I),
- reg_force_data_miso => reg_force_data_miso_arr(I),
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
+ mosi => reg_force_data_mosi,
+ miso => reg_force_data_miso,
+ mosi_arr => reg_force_data_mosi_arr,
+ miso_arr => reg_force_data_miso_arr
);
+
+ gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
+ u_mms_dp_force_data_parallel : entity work.mms_dp_force_data_parallel
+ generic map (
+ g_dat_w => g_dat_w,
+ g_increment_data => g_increment_data,
+ g_increment_re => g_increment_re,
+ g_increment_im => g_increment_im,
+ g_increment_data_on_sop => g_increment_data_on_sop,
+ g_increment_re_on_sop => g_increment_re_on_sop,
+ g_increment_im_on_sop => g_increment_im_on_sop,
+ g_restart_data_on_sync => g_restart_data_on_sync,
+ g_restart_re_on_sync => g_restart_re_on_sync,
+ g_restart_im_on_sync => g_restart_im_on_sync,
+ g_restart_data_on_sop => g_restart_data_on_sop,
+ g_restart_re_on_sop => g_restart_re_on_sop,
+ g_restart_im_on_sop => g_restart_im_on_sop
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM control
+ reg_force_data_mosi => reg_force_data_mosi_arr(I),
+ reg_force_data_miso => reg_force_data_miso_arr(I),
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
index 63de286f7c..a2bf721227 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
@@ -37,10 +37,10 @@
-- See description of dp_force_data_serial.vhd.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_force_data_serial is
generic (
@@ -107,62 +107,62 @@ begin
-- read unused bits as '0' to save logic
reg_force_data_rd(1 * c_mm_reg.dat_w - 1 downto 2 + 0 * c_mm_reg.dat_w) <= (others => '0');
if c_index_w < c_mm_reg.dat_w then
- reg_force_data_rd(2 * c_mm_reg.dat_w - 1 downto c_index_w + 1 * c_mm_reg.dat_w) <= (others => '0');
+ reg_force_data_rd(2 * c_mm_reg.dat_w - 1 downto c_index_w + 1 * c_mm_reg.dat_w) <= (others => '0');
end if;
if g_dat_w < c_mm_reg.dat_w then
- reg_force_data_rd(3 * c_mm_reg.dat_w - 1 downto g_dat_w + 2 * c_mm_reg.dat_w) <= (others => '0');
- reg_force_data_rd(4 * c_mm_reg.dat_w - 1 downto g_dat_w + 3 * c_mm_reg.dat_w) <= (others => '0');
- reg_force_data_rd(5 * c_mm_reg.dat_w - 1 downto g_dat_w + 4 * c_mm_reg.dat_w) <= (others => '0');
+ reg_force_data_rd(3 * c_mm_reg.dat_w - 1 downto g_dat_w + 2 * c_mm_reg.dat_w) <= (others => '0');
+ reg_force_data_rd(4 * c_mm_reg.dat_w - 1 downto g_dat_w + 3 * c_mm_reg.dat_w) <= (others => '0');
+ reg_force_data_rd(5 * c_mm_reg.dat_w - 1 downto g_dat_w + 4 * c_mm_reg.dat_w) <= (others => '0');
end if;
end process;
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => c_mm_reg_init
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => c_mm_reg_init
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_force_data_mosi,
- sla_out => reg_force_data_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_force_data_mosi,
+ sla_out => reg_force_data_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- out_reg => reg_force_data_wr, -- readback via ST clock domain
- in_reg => reg_force_data_rd
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ out_reg => reg_force_data_wr, -- readback via ST clock domain
+ in_reg => reg_force_data_rd
+ );
u_dp_force_data_serial : entity work.dp_force_data_serial
- generic map (
- g_dat_w => g_dat_w,
- g_index_period => g_index_period,
- g_index_sample_block_n => g_index_sample_block_n
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- MM control
- force_en => force_en,
- force_value => force_value,
- force_zero_n => force_zero_n,
- force_data => force_data ,
- force_re => force_re,
- force_im => force_im,
- force_index => force_index,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_dat_w => g_dat_w,
+ g_index_period => g_index_period,
+ g_index_sample_block_n => g_index_sample_block_n
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- MM control
+ force_en => force_en,
+ force_value => force_value,
+ force_zero_n => force_zero_n,
+ force_data => force_data ,
+ force_re => force_re,
+ force_im => force_im,
+ force_index => force_index,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
index 38e1ad0980..0062ec699c 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
@@ -34,10 +34,10 @@
-- See description of mms_dp_force_data_serial.vhd.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_force_data_serial_arr is
generic (
@@ -71,39 +71,39 @@ architecture str of mms_dp_force_data_serial_arr is
signal reg_force_data_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
begin
u_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_mm_reg_adr_w
- )
- port map (
- mosi => reg_force_data_mosi,
- miso => reg_force_data_miso,
- mosi_arr => reg_force_data_mosi_arr,
- miso_arr => reg_force_data_miso_arr
- );
-
- gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
- u_mms_dp_force_data_serial : entity work.mms_dp_force_data_serial
generic map (
- g_dat_w => g_dat_w,
- g_index_period => g_index_period,
- g_index_sample_block_n => g_index_sample_block_n
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_mm_reg_adr_w
)
port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM control
- reg_force_data_mosi => reg_force_data_mosi_arr(I),
- reg_force_data_miso => reg_force_data_miso_arr(I),
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
+ mosi => reg_force_data_mosi,
+ miso => reg_force_data_miso,
+ mosi_arr => reg_force_data_mosi_arr,
+ miso_arr => reg_force_data_miso_arr
);
+
+ gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
+ u_mms_dp_force_data_serial : entity work.mms_dp_force_data_serial
+ generic map (
+ g_dat_w => g_dat_w,
+ g_index_period => g_index_period,
+ g_index_sample_block_n => g_index_sample_block_n
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM control
+ reg_force_data_mosi => reg_force_data_mosi_arr(I),
+ reg_force_data_miso => reg_force_data_miso_arr(I),
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
index cfb48e8937..914a300f3a 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
@@ -27,11 +27,11 @@
-- . See tb_mms_dp_gain_arr which also tests this mms_dp_gain
library IEEE, common_lib, common_mult_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_dp_gain is
generic (
@@ -86,45 +86,45 @@ begin
out_sosi <= out_sosi_arr(0);
u_one : entity work.mms_dp_gain_arr
- generic map (
- g_technology => g_technology,
- -- functional
- g_nof_streams => 1,
- g_complex_data => g_complex_data,
- g_complex_gain => g_complex_gain,
- g_gain_init_re => g_gain_init_re,
- g_gain_init_im => g_gain_init_im,
- g_gain_w => g_gain_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- -- pipelining (typically use defaults)
- -- . real multiplier
- g_pipeline_real_mult_input => g_pipeline_real_mult_input,
- g_pipeline_real_mult_product => g_pipeline_real_mult_product,
- g_pipeline_real_mult_output => g_pipeline_real_mult_output,
- -- . complex multiplier
- g_pipeline_complex_mult_input => g_pipeline_complex_mult_input,
- g_pipeline_complex_mult_product => g_pipeline_complex_mult_product,
- g_pipeline_complex_mult_adder => g_pipeline_complex_mult_adder,
- g_pipeline_complex_mult_output => g_pipeline_complex_mult_output
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_technology => g_technology,
+ -- functional
+ g_nof_streams => 1,
+ g_complex_data => g_complex_data,
+ g_complex_gain => g_complex_gain,
+ g_gain_init_re => g_gain_init_re,
+ g_gain_init_im => g_gain_init_im,
+ g_gain_w => g_gain_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ -- pipelining (typically use defaults)
+ -- . real multiplier
+ g_pipeline_real_mult_input => g_pipeline_real_mult_input,
+ g_pipeline_real_mult_product => g_pipeline_real_mult_product,
+ g_pipeline_real_mult_output => g_pipeline_real_mult_output,
+ -- . complex multiplier
+ g_pipeline_complex_mult_input => g_pipeline_complex_mult_input,
+ g_pipeline_complex_mult_product => g_pipeline_complex_mult_product,
+ g_pipeline_complex_mult_adder => g_pipeline_complex_mult_adder,
+ g_pipeline_complex_mult_output => g_pipeline_complex_mult_output
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- MM access to gain
- reg_gain_re_mosi => reg_gain_re_mosi,
- reg_gain_re_miso => reg_gain_re_miso,
- reg_gain_im_mosi => reg_gain_im_mosi,
- reg_gain_im_miso => reg_gain_im_miso,
+ -- MM access to gain
+ reg_gain_re_mosi => reg_gain_re_mosi,
+ reg_gain_re_miso => reg_gain_re_miso,
+ reg_gain_im_mosi => reg_gain_im_mosi,
+ reg_gain_im_miso => reg_gain_im_miso,
- reg_gain_re => reg_gain_re,
- reg_gain_im => reg_gain_im,
- -- ST
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => out_sosi_arr
- );
+ reg_gain_re => reg_gain_re,
+ reg_gain_im => reg_gain_im,
+ -- ST
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => out_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
index f6915b5ef6..eac2cb0631 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
@@ -52,11 +52,11 @@
-- . A dp_pipeline is used to pass through the dp_control_fields.
library IEEE, common_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_dp_gain_arr is
generic (
@@ -133,65 +133,65 @@ begin
reg_gain_im <= i_reg_gain_im;
u_common_reg_r_w_dc_re : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => c_mm_reg_init_re
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => c_mm_reg_init_re
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_gain_re_mosi,
- sla_out => reg_gain_re_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_gain_re_mosi,
+ sla_out => reg_gain_re_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => i_reg_gain_re,
- out_reg => i_reg_gain_re -- readback via ST clock domain
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => i_reg_gain_re,
+ out_reg => i_reg_gain_re -- readback via ST clock domain
+ );
gen_real_multiply : if c_real_multiply = true generate
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_common_mult : entity common_mult_lib.common_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => g_gain_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
- g_nof_mult => 1,
- g_pipeline_input => g_pipeline_real_mult_input,
- g_pipeline_product => g_pipeline_real_mult_product,
- g_pipeline_output => g_pipeline_real_mult_output,
- g_representation => "SIGNED" -- or "UNSIGNED"
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_a => i_reg_gain_re((I + 1) * g_gain_w - 1 downto I * g_gain_w),
- in_b => in_sosi_arr(I).data(g_in_dat_w - 1 downto 0),
- in_val => in_sosi_arr(I).valid,
- out_p => mult_sosi_arr(I).data(g_out_dat_w - 1 downto 0),
- out_val => mult_sosi_arr(I).valid
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => g_gain_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ g_nof_mult => 1,
+ g_pipeline_input => g_pipeline_real_mult_input,
+ g_pipeline_product => g_pipeline_real_mult_product,
+ g_pipeline_output => g_pipeline_real_mult_output,
+ g_representation => "SIGNED" -- or "UNSIGNED"
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_a => i_reg_gain_re((I + 1) * g_gain_w - 1 downto I * g_gain_w),
+ in_b => in_sosi_arr(I).data(g_in_dat_w - 1 downto 0),
+ in_val => in_sosi_arr(I).valid,
+ out_p => mult_sosi_arr(I).data(g_out_dat_w - 1 downto 0),
+ out_val => mult_sosi_arr(I).valid
+ );
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_real_multiply_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => in_sosi_arr(I),
- src_out => pipelined_in_sosi_arr(I)
- );
+ generic map (
+ g_pipeline => c_real_multiply_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => in_sosi_arr(I),
+ src_out => pipelined_in_sosi_arr(I)
+ );
p_out_sosi_arr : process(mult_sosi_arr, pipelined_in_sosi_arr)
begin
@@ -206,70 +206,70 @@ begin
gen_complex_multiply : if c_real_multiply = false generate
gen_complex_gain : if g_complex_gain = true generate
u_common_reg_r_w_dc_im : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => c_mm_reg_init_im
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => c_mm_reg_init_im
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_gain_im_mosi,
- sla_out => reg_gain_im_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_gain_im_mosi,
+ sla_out => reg_gain_im_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => i_reg_gain_im,
- out_reg => i_reg_gain_im -- readback via ST clock domain
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => i_reg_gain_im,
+ out_reg => i_reg_gain_im -- readback via ST clock domain
+ );
end generate gen_complex_gain;
-- ELSE: if g_complex_gain=FALSE then use default i_reg_gain_im, which is then typically g_gain_init_im=0 for all streams.
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_common_complex_mult : entity common_mult_lib.common_complex_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => g_gain_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
- g_conjugate_b => false,
- g_pipeline_input => g_pipeline_complex_mult_input,
- g_pipeline_product => g_pipeline_complex_mult_product,
- g_pipeline_adder => g_pipeline_complex_mult_adder,
- g_pipeline_output => g_pipeline_complex_mult_output
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_ar => i_reg_gain_re((I + 1) * g_gain_w - 1 downto I * g_gain_w),
- in_ai => i_reg_gain_im((I + 1) * g_gain_w - 1 downto I * g_gain_w),
- in_br => in_sosi_arr(I).re(g_in_dat_w - 1 downto 0),
- in_bi => in_sosi_arr(I).im(g_in_dat_w - 1 downto 0),
- in_val => in_sosi_arr(I).valid, -- only propagate valid, not used internally
- out_pr => mult_sosi_arr(I).re(g_out_dat_w - 1 downto 0),
- out_pi => mult_sosi_arr(I).im(g_out_dat_w - 1 downto 0),
- out_val => mult_sosi_arr(I).valid
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => g_gain_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ g_conjugate_b => false,
+ g_pipeline_input => g_pipeline_complex_mult_input,
+ g_pipeline_product => g_pipeline_complex_mult_product,
+ g_pipeline_adder => g_pipeline_complex_mult_adder,
+ g_pipeline_output => g_pipeline_complex_mult_output
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_ar => i_reg_gain_re((I + 1) * g_gain_w - 1 downto I * g_gain_w),
+ in_ai => i_reg_gain_im((I + 1) * g_gain_w - 1 downto I * g_gain_w),
+ in_br => in_sosi_arr(I).re(g_in_dat_w - 1 downto 0),
+ in_bi => in_sosi_arr(I).im(g_in_dat_w - 1 downto 0),
+ in_val => in_sosi_arr(I).valid, -- only propagate valid, not used internally
+ out_pr => mult_sosi_arr(I).re(g_out_dat_w - 1 downto 0),
+ out_pi => mult_sosi_arr(I).im(g_out_dat_w - 1 downto 0),
+ out_val => mult_sosi_arr(I).valid
+ );
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_complex_multiply_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => in_sosi_arr(I),
- src_out => pipelined_in_sosi_arr(I)
- );
+ generic map (
+ g_pipeline => c_complex_multiply_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => in_sosi_arr(I),
+ src_out => pipelined_in_sosi_arr(I)
+ );
p_out_sosi_arr : process(mult_sosi_arr, pipelined_in_sosi_arr)
begin
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
index f84253d771..f4de621422 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
@@ -27,11 +27,11 @@
-- . See tb_mms_dp_gain_serial_arr which also tests this mms_dp_gain_serial
library IEEE, common_lib, common_mult_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_dp_gain_serial is
generic (
@@ -84,44 +84,44 @@ begin
out_sosi <= out_sosi_arr(0);
u_one : entity work.mms_dp_gain_serial_arr
- generic map (
- g_technology => g_technology,
- g_nof_streams => 1,
- g_nof_gains => g_nof_gains,
- g_complex_data => g_complex_data,
- g_complex_gain => g_complex_gain,
- g_gain_w => g_gain_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_gains_file_name => g_gains_file_name,
- g_gains_write_only => g_gains_write_only,
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => 1,
+ g_nof_gains => g_nof_gains,
+ g_complex_data => g_complex_data,
+ g_complex_gain => g_complex_gain,
+ g_gain_w => g_gain_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_gains_file_name => g_gains_file_name,
+ g_gains_write_only => g_gains_write_only,
- -- pipelining (typically use defaults)
- -- . real multiplier
- g_pipeline_real_mult_input => g_pipeline_real_mult_input,
- g_pipeline_real_mult_product => g_pipeline_real_mult_product,
- g_pipeline_real_mult_output => g_pipeline_real_mult_output,
- -- . complex multiplier
- g_pipeline_complex_mult_input => g_pipeline_complex_mult_input,
- g_pipeline_complex_mult_product => g_pipeline_complex_mult_product,
- g_pipeline_complex_mult_adder => g_pipeline_complex_mult_adder,
- g_pipeline_complex_mult_output => g_pipeline_complex_mult_output
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ -- pipelining (typically use defaults)
+ -- . real multiplier
+ g_pipeline_real_mult_input => g_pipeline_real_mult_input,
+ g_pipeline_real_mult_product => g_pipeline_real_mult_product,
+ g_pipeline_real_mult_output => g_pipeline_real_mult_output,
+ -- . complex multiplier
+ g_pipeline_complex_mult_input => g_pipeline_complex_mult_input,
+ g_pipeline_complex_mult_product => g_pipeline_complex_mult_product,
+ g_pipeline_complex_mult_adder => g_pipeline_complex_mult_adder,
+ g_pipeline_complex_mult_output => g_pipeline_complex_mult_output
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- MM interface
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso,
+ -- MM interface
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
- -- ST interface
- gains_rd_address => gains_rd_address,
+ -- ST interface
+ gains_rd_address => gains_rd_address,
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => out_sosi_arr
- );
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => out_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
index e81bb5a6d0..717f27d0c7 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
@@ -40,13 +40,13 @@
-- choose the correct avs_common_mm_readlatency2 when creating the qsys system.
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib, common_mult_lib, technology_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_gain_serial_arr is
generic (
@@ -101,115 +101,116 @@ architecture str of mms_dp_gain_serial_arr is
-- dat_w : NATURAL;
-- nof_dat : NATURAL; -- optional, nof dat words <= 2**adr_w
-- init_sl : STD_LOGIC; -- optional, init all dat words to std_logic '0', '1' or 'X'
- constant c_mm_ram : t_c_mem := (latency => 2, -- set latency to 2 to ease timing
- adr_w => ceil_log2(g_nof_gains),
- dat_w => sel_a_b(g_complex_gain, c_nof_complex, 1) * g_gain_w,
- nof_dat => g_nof_gains,
- init_sl => '0');
+ constant c_mm_ram : t_c_mem := (
+ latency => 2, -- set latency to 2 to ease timing
+ adr_w => ceil_log2(g_nof_gains),
+ dat_w => sel_a_b(g_complex_gain, c_nof_complex, 1) * g_gain_w,
+ nof_dat => g_nof_gains,
+ init_sl => '0');
constant c_pipeline_real_latency : natural := g_pipeline_real_mult_input
- + g_pipeline_real_mult_product
- + g_pipeline_real_mult_output
- + c_mm_ram.latency;
+ + g_pipeline_real_mult_product
+ + g_pipeline_real_mult_output
+ + c_mm_ram.latency;
- constant c_pipeline_complex_latency : natural := g_pipeline_complex_mult_input
- + g_pipeline_complex_mult_product
- + g_pipeline_complex_mult_adder
- + g_pipeline_complex_mult_output
- + c_mm_ram.latency;
+ constant c_pipeline_complex_latency : natural := g_pipeline_complex_mult_input
+ + g_pipeline_complex_mult_product
+ + g_pipeline_complex_mult_adder
+ + g_pipeline_complex_mult_output
+ + c_mm_ram.latency;
- constant c_pipeline_latency : natural := sel_a_b(c_real_multiply, c_pipeline_real_latency, c_pipeline_complex_latency);
+ constant c_pipeline_latency : natural := sel_a_b(c_real_multiply, c_pipeline_real_latency, c_pipeline_complex_latency);
- type t_slv_rddata_arr is array (integer range <>) of std_logic_vector(c_mm_ram.dat_w - 1 downto 0);
- type t_slv_gains_arr is array (integer range <>) of std_logic_vector(g_gain_w - 1 downto 0);
- type t_slv_in_dat_arr is array (integer range <>) of std_logic_vector(g_in_dat_w - 1 downto 0);
- type t_slv_out_dat_arr is array (integer range <>) of std_logic_vector(g_out_dat_w - 1 downto 0);
+ type t_slv_rddata_arr is array (integer range <>) of std_logic_vector(c_mm_ram.dat_w - 1 downto 0);
+ type t_slv_gains_arr is array (integer range <>) of std_logic_vector(g_gain_w - 1 downto 0);
+ type t_slv_in_dat_arr is array (integer range <>) of std_logic_vector(g_in_dat_w - 1 downto 0);
+ type t_slv_out_dat_arr is array (integer range <>) of std_logic_vector(g_out_dat_w - 1 downto 0);
- signal mm_gains_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
- signal mm_gains_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0) := (others => c_mem_miso_rst);
+ signal mm_gains_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
+ signal mm_gains_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0) := (others => c_mem_miso_rst);
- signal gains_rd_data_arr : t_slv_rddata_arr(g_nof_streams - 1 downto 0);
- signal gains_re_arr : t_slv_gains_arr(g_nof_streams - 1 downto 0);
- signal gains_im_arr : t_slv_gains_arr(g_nof_streams - 1 downto 0);
+ signal gains_rd_data_arr : t_slv_rddata_arr(g_nof_streams - 1 downto 0);
+ signal gains_re_arr : t_slv_gains_arr(g_nof_streams - 1 downto 0);
+ signal gains_im_arr : t_slv_gains_arr(g_nof_streams - 1 downto 0);
- signal in_sosi_arr_pipe : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal in_sosi_arr_pipe_ctrl : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal in_dat_re_arr : t_slv_in_dat_arr(g_nof_streams - 1 downto 0);
- signal in_dat_im_arr : t_slv_in_dat_arr(g_nof_streams - 1 downto 0);
- signal in_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal in_sosi_arr_pipe : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal in_sosi_arr_pipe_ctrl : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal in_dat_re_arr : t_slv_in_dat_arr(g_nof_streams - 1 downto 0);
+ signal in_dat_im_arr : t_slv_in_dat_arr(g_nof_streams - 1 downto 0);
+ signal in_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal out_dat_re_arr : t_slv_out_dat_arr(g_nof_streams - 1 downto 0);
- signal out_dat_im_arr : t_slv_out_dat_arr(g_nof_streams - 1 downto 0);
- signal out_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal out_dat_re_arr : t_slv_out_dat_arr(g_nof_streams - 1 downto 0);
+ signal out_dat_im_arr : t_slv_out_dat_arr(g_nof_streams - 1 downto 0);
+ signal out_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
begin
-- pipeline in_sosi_arr to align it with gains_rd_data_arr
u_pipeline_arr : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_mm_ram.latency -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in_arr => in_sosi_arr,
- src_out_arr => in_sosi_arr_pipe
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_mm_ram.latency -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in_arr => in_sosi_arr,
+ src_out_arr => in_sosi_arr_pipe
+ );
-- pipeline in_sosi_arr to add sop, eop and sync back in out_sosi_arr
u_pipeline_arr_ctrl : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_pipeline_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in_arr => in_sosi_arr,
- src_out_arr => in_sosi_arr_pipe_ctrl
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_pipeline_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in_arr => in_sosi_arr,
+ src_out_arr => in_sosi_arr_pipe_ctrl
+ );
u_mem_mux_gains : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(g_nof_gains)
- )
- port map (
- mosi => ram_gains_mosi,
- miso => ram_gains_miso,
- mosi_arr => mm_gains_mosi_arr,
- miso_arr => mm_gains_miso_arr
- );
-
- gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
- -- Instantiate a gains memory for each input stream:
- u_common_ram_crw_crw : entity common_lib.common_ram_crw_crw
generic map (
- g_technology => g_technology,
- g_ram => c_mm_ram,
- g_init_file => sel_a_b(g_gains_file_name = "UNUSED", g_gains_file_name, g_gains_file_name & "_" & natural'image(I) & ".hex"),
- g_true_dual_port => not(g_gains_write_only)
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(g_nof_gains)
)
port map (
- -- MM side
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => mm_gains_mosi_arr(I).wr,
- wr_dat_a => mm_gains_mosi_arr(I).wrdata(c_mm_ram.dat_w - 1 downto 0),
- adr_a => mm_gains_mosi_arr(I).address(c_mm_ram.adr_w - 1 downto 0),
- rd_en_a => mm_gains_mosi_arr(I).rd,
- rd_dat_a => mm_gains_miso_arr(I).rddata(c_mm_ram.dat_w - 1 downto 0),
- rd_val_a => mm_gains_miso_arr(I).rdval,
- -- ST side
- rst_b => dp_rst,
- clk_b => dp_clk,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- adr_b => gains_rd_address,
- rd_en_b => '1',
- rd_dat_b => gains_rd_data_arr(I)(c_mm_ram.dat_w - 1 downto 0),
- rd_val_b => open
+ mosi => ram_gains_mosi,
+ miso => ram_gains_miso,
+ mosi_arr => mm_gains_mosi_arr,
+ miso_arr => mm_gains_miso_arr
);
+ gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
+ -- Instantiate a gains memory for each input stream:
+ u_common_ram_crw_crw : entity common_lib.common_ram_crw_crw
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_ram,
+ g_init_file => sel_a_b(g_gains_file_name = "UNUSED", g_gains_file_name, g_gains_file_name & "_" & natural'image(I) & ".hex"),
+ g_true_dual_port => not(g_gains_write_only)
+ )
+ port map (
+ -- MM side
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => mm_gains_mosi_arr(I).wr,
+ wr_dat_a => mm_gains_mosi_arr(I).wrdata(c_mm_ram.dat_w - 1 downto 0),
+ adr_a => mm_gains_mosi_arr(I).address(c_mm_ram.adr_w - 1 downto 0),
+ rd_en_a => mm_gains_mosi_arr(I).rd,
+ rd_dat_a => mm_gains_miso_arr(I).rddata(c_mm_ram.dat_w - 1 downto 0),
+ rd_val_a => mm_gains_miso_arr(I).rdval,
+ -- ST side
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ adr_b => gains_rd_address,
+ rd_en_b => '1',
+ rd_dat_b => gains_rd_data_arr(I)(c_mm_ram.dat_w - 1 downto 0),
+ rd_val_b => open
+ );
+
gen_real_multiply : if c_real_multiply = true generate
gains_re_arr(I) <= gains_rd_data_arr(I)(g_gain_w - 1 downto 0);
@@ -217,27 +218,27 @@ begin
in_val_arr(I) <= in_sosi_arr_pipe(I).valid;
u_common_mult : entity common_mult_lib.common_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => g_gain_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
- g_nof_mult => 1,
- g_pipeline_input => g_pipeline_real_mult_input,
- g_pipeline_product => g_pipeline_real_mult_product,
- g_pipeline_output => g_pipeline_real_mult_output,
- g_representation => "SIGNED" -- or "UNSIGNED"
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_a => gains_re_arr(I),
- in_b => in_dat_re_arr(I),
- in_val => in_val_arr(I),
- out_p => out_dat_re_arr(I),
- out_val => out_val_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => g_gain_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ g_nof_mult => 1,
+ g_pipeline_input => g_pipeline_real_mult_input,
+ g_pipeline_product => g_pipeline_real_mult_product,
+ g_pipeline_output => g_pipeline_real_mult_output,
+ g_representation => "SIGNED" -- or "UNSIGNED"
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_a => gains_re_arr(I),
+ in_b => in_dat_re_arr(I),
+ in_val => in_val_arr(I),
+ out_p => out_dat_re_arr(I),
+ out_val => out_val_arr(I)
+ );
p_out_sosi_arr : process(out_val_arr, out_dat_re_arr, in_sosi_arr_pipe_ctrl)
begin
@@ -267,30 +268,30 @@ begin
in_val_arr(I) <= in_sosi_arr_pipe(I).valid;
u_common_complex_mult : entity common_mult_lib.common_complex_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => g_gain_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_conjugate_b => c_conjugate,
- g_pipeline_input => g_pipeline_complex_mult_input,
- g_pipeline_product => g_pipeline_complex_mult_product,
- g_pipeline_adder => g_pipeline_complex_mult_adder,
- g_pipeline_output => g_pipeline_complex_mult_output
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_ar => gains_re_arr(I),
- in_ai => gains_im_arr(I),
- in_br => in_dat_re_arr(I),
- in_bi => in_dat_im_arr(I),
- in_val => in_val_arr(I),
- out_pr => out_dat_re_arr(I),
- out_pi => out_dat_im_arr(I),
- out_val => out_val_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => g_gain_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_conjugate_b => c_conjugate,
+ g_pipeline_input => g_pipeline_complex_mult_input,
+ g_pipeline_product => g_pipeline_complex_mult_product,
+ g_pipeline_adder => g_pipeline_complex_mult_adder,
+ g_pipeline_output => g_pipeline_complex_mult_output
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_ar => gains_re_arr(I),
+ in_ai => gains_im_arr(I),
+ in_br => in_dat_re_arr(I),
+ in_bi => in_dat_im_arr(I),
+ in_val => in_val_arr(I),
+ out_pr => out_dat_re_arr(I),
+ out_pi => out_dat_im_arr(I),
+ out_val => out_val_arr(I)
+ );
p_out_sosi_arr : process(out_val_arr, out_dat_re_arr, out_dat_im_arr, in_sosi_arr_pipe_ctrl)
begin
diff --git a/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd b/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
index 5191eef130..6e8a89840e 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
@@ -24,12 +24,12 @@
-- Remarks:
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_packet_merge is
generic (
@@ -70,50 +70,50 @@ architecture str of mms_dp_packet_merge is
signal nof_pkt : t_nof_pkt_arr;
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(c_field_arr, c_word_w))
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(c_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
gen_stream : for i in 0 to g_nof_streams - 1 generate
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi_arr(i),
- mm_miso => reg_miso_arr(i),
+ mm_mosi => reg_mosi_arr(i),
+ mm_miso => reg_miso_arr(i),
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_out_arr(i)
- );
+ slv_out => mm_fields_out_arr(i)
+ );
nof_pkt(i) <= mm_fields_out_arr(i)(field_hi(c_field_arr, "nof_pkt") downto field_lo(c_field_arr, "nof_pkt"));
u_dp_merge : entity work.dp_packet_merge
- generic map (
- g_nof_pkt => g_nof_pkt
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- nof_pkt => nof_pkt(i),
- snk_out => snk_out_arr(i),
- snk_in => snk_in_arr(i),
- src_in => src_in_arr(i),
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_nof_pkt => g_nof_pkt
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ nof_pkt => nof_pkt(i),
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
+ src_in => src_in_arr(i),
+ src_out => src_out_arr(i)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
index 47d9371bc9..d663f4355b 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity mms_dp_ram_from_mm is
generic (
@@ -48,44 +48,44 @@ entity mms_dp_ram_from_mm is
end mms_dp_ram_from_mm;
architecture str of mms_dp_ram_from_mm is
- signal dp_on : std_logic;
+ signal dp_on : std_logic;
begin
- u_dp_ram_from_mm : entity dp_lib.dp_ram_from_mm
- generic map(
- g_ram_wr_nof_words => g_ram_wr_nof_words,
- g_ram_rd_dat_w => g_ram_rd_dat_w,
- g_init_file => g_init_file
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ u_dp_ram_from_mm : entity dp_lib.dp_ram_from_mm
+ generic map(
+ g_ram_wr_nof_words => g_ram_wr_nof_words,
+ g_ram_rd_dat_w => g_ram_rd_dat_w,
+ g_init_file => g_init_file
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- mm_addr => ram_mosi.address,
- mm_wr => ram_mosi.wr,
- mm_wrdata => ram_mosi.wrdata,
+ mm_addr => ram_mosi.address,
+ mm_wr => ram_mosi.wr,
+ mm_wrdata => ram_mosi.wrdata,
- dp_on => dp_on,
+ dp_on => dp_on,
- src_in => src_in,
- src_out => src_out
- );
+ src_in => src_in,
+ src_out => src_out
+ );
u_dp_ram_from_mm_reg: entity work.dp_ram_from_mm_reg
- generic map(
- g_dp_on_at_init => g_dp_on_at_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map(
+ g_dp_on_at_init => g_dp_on_at_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- sla_in => reg_mosi,
+ sla_in => reg_mosi,
- dp_on => dp_on
- );
+ dp_on => dp_on
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_scale.vhd b/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
index 37b2b5a73d..ac25743d82 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
@@ -29,10 +29,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_scale is
generic (
@@ -51,7 +51,7 @@ entity mms_dp_scale is
g_lsb_round_clip : boolean := false; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
g_msb_clip : boolean := true; -- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric : boolean := false -- when TRUE CLIP signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
- -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
+ -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
);
port (
-- System
@@ -85,56 +85,56 @@ begin
-- Gain
---------------------------------------------------------------
u_mms_dp_gain : entity work.mms_dp_gain
- generic map (
- g_complex_data => g_complex_data,
- g_complex_gain => g_complex_gain,
- g_gain_init_re => g_gain_init_re,
- g_gain_init_im => g_gain_init_im,
- g_gain_w => g_gain_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_gain_out_dat_w
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_complex_data => g_complex_data,
+ g_complex_gain => g_complex_gain,
+ g_gain_init_re => g_gain_init_re,
+ g_gain_init_im => g_gain_init_im,
+ g_gain_w => g_gain_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_gain_out_dat_w
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- MM interface
- reg_gain_re_mosi => reg_gain_re_mosi,
- reg_gain_re_miso => reg_gain_re_miso,
- reg_gain_im_mosi => reg_gain_im_mosi,
- reg_gain_im_miso => reg_gain_im_miso,
+ -- MM interface
+ reg_gain_re_mosi => reg_gain_re_mosi,
+ reg_gain_re_miso => reg_gain_re_miso,
+ reg_gain_im_mosi => reg_gain_im_mosi,
+ reg_gain_im_miso => reg_gain_im_miso,
- reg_gain_re => reg_gain_re,
- reg_gain_im => reg_gain_im,
+ reg_gain_re => reg_gain_re,
+ reg_gain_im => reg_gain_im,
- in_sosi => in_sosi,
- out_sosi => dp_gain_out_sosi
- );
+ in_sosi => in_sosi,
+ out_sosi => dp_gain_out_sosi
+ );
---------------------------------------------------------------
-- Requantize
---------------------------------------------------------------
u_dp_requantize : entity work.dp_requantize
- generic map (
- g_complex => c_dp_requantize_complex,
- g_representation => "SIGNED",
- g_lsb_w => g_lsb_w,
- g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
- g_msb_clip => g_msb_clip,
- g_msb_clip_symmetric => g_msb_clip_symmetric,
- g_in_dat_w => c_gain_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => dp_gain_out_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_complex => c_dp_requantize_complex,
+ g_representation => "SIGNED",
+ g_lsb_w => g_lsb_w,
+ g_lsb_round => g_lsb_round,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_msb_clip => g_msb_clip,
+ g_msb_clip_symmetric => g_msb_clip_symmetric,
+ g_in_dat_w => c_gain_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => dp_gain_out_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_split.vhd b/libraries/base/dp/src/vhdl/mms_dp_split.vhd
index ee7ade081f..adb173263a 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_split.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_split.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_split is
generic (
@@ -67,55 +67,55 @@ architecture str of mms_dp_split is
signal nof_symbols : t_nof_symbols_arr;
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
gen_stream : for i in 0 to g_nof_streams - 1 generate
out_nof_symbols(i) <= TO_UINT(nof_symbols(i));
u_reg : entity work.dp_split_reg
- generic map (
- g_nof_symbols => g_nof_symbols_max
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
-
- -- MM registers in dp_clk domain
- -- . control
- nof_symbols => nof_symbols(i)
- );
+ generic map (
+ g_nof_symbols => g_nof_symbols_max
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ nof_symbols => nof_symbols(i)
+ );
u_dp_split : entity work.dp_split
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => g_nof_symbols_max
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- nof_symbols => nof_symbols(i),
- snk_out => snk_out_arr(i),
- snk_in => snk_in_arr(i),
- src_in_arr => src_in_2arr(i),
- src_out_arr => src_out_2arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => g_nof_symbols_max
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ nof_symbols => nof_symbols(i),
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
+ src_in_arr => src_in_2arr(i),
+ src_out_arr => src_out_2arr(i)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd b/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
index ad8d312d44..fdad36f150 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
@@ -48,11 +48,11 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_sync_checker is
generic(
@@ -83,11 +83,12 @@ end mms_dp_sync_checker;
architecture str of mms_dp_sync_checker is
-- Define the actual size of the MM slave register
constant c_nof_regs : positive := 2;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w,
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w,
+ nof_dat => c_nof_regs,
+ init_sl => '0');
signal read_register : std_logic_vector(c_nof_regs * c_word_w - 1 downto 0);
signal nof_early_syncs : std_logic_vector(c_word_w - 1 downto 0);
@@ -95,48 +96,48 @@ architecture str of mms_dp_sync_checker is
signal reg_rd_arr : std_logic_vector(c_nof_regs - 1 downto 0);
begin
u_dp_sync_checker : entity work.dp_sync_checker
- generic map(
- g_nof_blk_per_sync => g_nof_blk_per_sync
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
- snk_out => snk_out,
- snk_in => snk_in,
- src_in => src_in,
- src_out => src_out,
- nof_early_syncs => nof_early_syncs,
- nof_late_syncs => nof_late_syncs,
- clear_nof_early_syncs => reg_rd_arr(0),
- clear_nof_late_syncs => reg_rd_arr(1)
- );
+ generic map(
+ g_nof_blk_per_sync => g_nof_blk_per_sync
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ snk_out => snk_out,
+ snk_in => snk_in,
+ src_in => src_in,
+ src_out => src_out,
+ nof_early_syncs => nof_early_syncs,
+ nof_late_syncs => nof_late_syncs,
+ clear_nof_early_syncs => reg_rd_arr(0),
+ clear_nof_late_syncs => reg_rd_arr(1)
+ );
read_register <= nof_late_syncs & nof_early_syncs;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1,
- g_readback => true,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1,
+ g_readback => true,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_dp_sync_checker_mosi,
- sla_out => reg_dp_sync_checker_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_dp_sync_checker_mosi,
+ sla_out => reg_dp_sync_checker_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => reg_rd_arr,
- in_new => OPEN,
- in_reg => read_register,
- out_reg => OPEN,
- out_new => open
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => reg_rd_arr,
+ in_new => OPEN,
+ in_reg => read_register,
+ out_reg => OPEN,
+ out_new => open
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
index 1d6a6bbdef..713c40105f 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
@@ -28,9 +28,9 @@
-- share the same sync as input 0, as is the case e.g. after a dp_bsn_aligner.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_sync_checker_arr is
generic(
@@ -70,43 +70,43 @@ begin
-- Check sync on input stream 0
u_mms_dp_sync_checker : entity work.mms_dp_sync_checker
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_nof_blk_per_sync => g_nof_blk_per_sync
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_nof_blk_per_sync => g_nof_blk_per_sync
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- -- ST sinks
- snk_out => sync_checker_snk_out,
- snk_in => snk_in_arr(0),
- -- ST source
- src_in => src_in_arr(0),
- src_out => sync_checker_src_out,
+ -- ST sinks
+ snk_out => sync_checker_snk_out,
+ snk_in => snk_in_arr(0),
+ -- ST source
+ src_in => src_in_arr(0),
+ src_out => sync_checker_src_out,
- -- Memory Mapped
- reg_dp_sync_checker_mosi => reg_dp_sync_checker_mosi,
- reg_dp_sync_checker_miso => reg_dp_sync_checker_miso
- );
+ -- Memory Mapped
+ reg_dp_sync_checker_mosi => reg_dp_sync_checker_mosi,
+ reg_dp_sync_checker_miso => reg_dp_sync_checker_miso
+ );
-- Pipeline all input streams with same latency as mms_dp_sync_checker
u_dp_pipeline_arr : entity dp_lib.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => snk_in_arr,
- -- ST source
- src_out_arr => pipeline_src_out_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => snk_in_arr,
+ -- ST source
+ src_out_arr => pipeline_src_out_arr
+ );
-- copy sync_checker control to all output streams, pass on the pipelined data
p_copy_sync_checker_controls : process(sync_checker_src_out, pipeline_src_out_arr)
diff --git a/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd b/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
index 8194cddac1..1a343432bd 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_throttle is
generic (
@@ -52,38 +52,38 @@ architecture str of mms_dp_throttle is
signal throttle : std_logic_vector(ceil_log2(g_dc_period + 1) - 1 downto 0);
begin
u_dp_throttle_reg : entity work.dp_throttle_reg
- generic map (
- g_dc_period => g_dc_period
- )
- port map (
+ generic map (
+ g_dc_period => g_dc_period
+ )
+ port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- throttle => throttle
- );
+ throttle => throttle
+ );
u_dp_throttle : entity work.dp_throttle
- generic map (
- g_dc_period => g_dc_period,
- g_throttle_valid => g_throttle_valid
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_dc_period => g_dc_period,
+ g_throttle_valid => g_throttle_valid
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- snk_out => snk_out,
- snk_in => snk_in,
+ snk_out => snk_out,
+ snk_in => snk_in,
- src_in => src_in,
- src_out => src_out,
+ src_in => src_in,
+ src_out => src_out,
- throttle => throttle
- );
+ throttle => throttle
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd b/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
index ac9ddc3c2c..adc5d3af6e 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_xonoff is
generic (
@@ -71,62 +71,62 @@ architecture str of mms_dp_xonoff is
signal src_in_arr_i : t_dp_siso_arr(g_nof_streams - 1 downto 0);
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_ctrl_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_ctrl_streams,
+ g_mult_addr_w => c_reg_adr_w
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
gen_reg : for i in 0 to c_nof_ctrl_streams - 1 generate
gen_no_timeout : if g_timeout_time = 0 generate
u_reg : entity work.dp_xonoff_reg
- generic map(
- g_default_value => g_default_value
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
-
- -- MM registers in dp_clk domain
- -- . control
- xonoff_reg => xonoff_reg(i downto i)
- );
+ generic map(
+ g_default_value => g_default_value
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ xonoff_reg => xonoff_reg(i downto i)
+ );
end generate;
gen_with_timeout : if g_timeout_time > 0 generate
u_reg : entity work.dp_xonoff_reg_timeout
- generic map(
- g_default_value => g_default_value,
- g_mm_timeout => g_timeout_time,
- g_sim => g_sim
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
-
- -- MM registers in dp_clk domain
- -- . control
- xonoff_reg => xonoff_reg(i downto i)
- );
+ generic map(
+ g_default_value => g_default_value,
+ g_mm_timeout => g_timeout_time,
+ g_sim => g_sim
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ xonoff_reg => xonoff_reg(i downto i)
+ );
end generate;
end generate;
@@ -138,20 +138,20 @@ begin
src_in_arr_i(i).xon <= src_in_arr(i).xon and xonoff_reg_i(i);
u_dp_xonoff : entity work.dp_xonoff
- generic map (
- g_bypass => g_bypass
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_bypass => g_bypass
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- in_siso => snk_out_arr(i),
- in_sosi => snk_in_arr(i),
- out_siso => src_in_arr_i(i),
- out_sosi => src_out_arr(i),
+ in_siso => snk_out_arr(i),
+ in_sosi => snk_in_arr(i),
+ out_siso => src_in_arr_i(i),
+ out_sosi => src_out_arr(i),
- force_xoff => force_xoff_arr(i)
- );
+ force_xoff => force_xoff_arr(i)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/tb/vhdl/dp_phy_link.vhd b/libraries/base/dp/tb/vhdl/dp_phy_link.vhd
index bf481437ec..8bed6e4a91 100644
--- a/libraries/base/dp/tb/vhdl/dp_phy_link.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_phy_link.vhd
@@ -21,18 +21,18 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-
--- Purpose:
--- Model a transceiver link.
--- Description:
--- The latency of the link is modeled by delay g_latency.
--- If the real link has e.g. 8b/10b coding, then it can transmit fill words.
--- This is modeled by g_valid_support = TRUE. When in_val is low then a fill
--- word is transmitted that can not occur in the user data. At the receiver
--- the fill words can be passed on through out_val low. If the real link has
--- no coding, then this is modeled by g_valid_support = FALSE and out_val
--- will be high always.
+ use IEEE.std_logic_1164.all;
+
+ -- Purpose:
+ -- Model a transceiver link.
+ -- Description:
+ -- The latency of the link is modeled by delay g_latency.
+ -- If the real link has e.g. 8b/10b coding, then it can transmit fill words.
+ -- This is modeled by g_valid_support = TRUE. When in_val is low then a fill
+ -- word is transmitted that can not occur in the user data. At the receiver
+ -- the fill words can be passed on through out_val low. If the real link has
+ -- no coding, then this is modeled by g_valid_support = FALSE and out_val
+ -- will be high always.
entity dp_phy_link is
generic (
diff --git a/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd b/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
index 2df830e950..8c87bfc496 100644
--- a/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
@@ -21,16 +21,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use std.textio.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use std.textio.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_str_pkg.all;
--- Purpose:
--- . Like dp_sosi_recorder.vhd, but records an array to a file.
+ -- Purpose:
+ -- . Like dp_sosi_recorder.vhd, but records an array to a file.
entity dp_sosi_arr_recorder is
generic (
diff --git a/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd b/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
index 4fa5cf10e3..f243d92e4a 100644
--- a/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
@@ -21,33 +21,33 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use std.textio.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use std.textio.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_str_pkg.all;
--- Purpose:
--- . Record the DP record fields to a file for later playback by
--- dp_stream_player.
--- Description:
--- . The DP record fields are appended to a file each cycle. Recording starts
--- at the first cycle at which valid=1.
--- . The record fields are written to one line each cycle, in the order (left
--- to right) as defined in t_dp_sosi, separated by spaces:
--- [sync] [bsn] [data] [re] [im] [valid] [sop] [eop] [empty] [channel] [err]
--- . The STD_LOCIC record fields are written as binary, the STD_LOGIC_VECTORS
--- are written as hexadecimal values.
--- Usage:
--- . dp_sosi_recorder and dp_stream_player (or dp_stream_rec_play for both)
--- can be used to record a DP stream into a file for later playback. This
--- can dramatically reduce simulation time of systems that use components
--- with a high I/O delay, such as components with long integration or
--- buffering times.
--- . Record using g_record_invalid=TRUE to maintain the valid/invalid ratio
--- (gap size) of the recorded stream during playback.
+ -- Purpose:
+ -- . Record the DP record fields to a file for later playback by
+ -- dp_stream_player.
+ -- Description:
+ -- . The DP record fields are appended to a file each cycle. Recording starts
+ -- at the first cycle at which valid=1.
+ -- . The record fields are written to one line each cycle, in the order (left
+ -- to right) as defined in t_dp_sosi, separated by spaces:
+ -- [sync] [bsn] [data] [re] [im] [valid] [sop] [eop] [empty] [channel] [err]
+ -- . The STD_LOCIC record fields are written as binary, the STD_LOGIC_VECTORS
+ -- are written as hexadecimal values.
+ -- Usage:
+ -- . dp_sosi_recorder and dp_stream_player (or dp_stream_rec_play for both)
+ -- can be used to record a DP stream into a file for later playback. This
+ -- can dramatically reduce simulation time of systems that use components
+ -- with a high I/O delay, such as components with long integration or
+ -- buffering times.
+ -- . Record using g_record_invalid=TRUE to maintain the valid/invalid ratio
+ -- (gap size) of the recorded stream during playback.
entity dp_sosi_recorder is
generic (
diff --git a/libraries/base/dp/tb/vhdl/dp_statistics.vhd b/libraries/base/dp/tb/vhdl/dp_statistics.vhd
index 90c09b5f24..45433a2980 100644
--- a/libraries/base/dp/tb/vhdl/dp_statistics.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_statistics.vhd
@@ -36,13 +36,13 @@
--
library IEEE, common_lib, work, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_statistics is
generic (
@@ -51,7 +51,7 @@ entity dp_statistics is
g_check_nof_valid : boolean := false; -- True enables valid count checking at dp_done. Reports Failure in case of mismatch.
g_check_nof_valid_ref : natural := 0; -- Reference (= expected) valid count
g_dp_word_w : natural := 32 -- Used to calculate data rate
- );
+ );
port (
dp_clk : in std_logic := '0';
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_player.vhd b/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
index 2591a2fa72..1ae44f88fd 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use std.textio.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use std.textio.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_str_pkg.all;
--- Purpose:
--- . Play back a stream recorded by dp_stream_recorder.
--- Description:
--- . Playback starts as soon as the connected sink indicates to be ready by
--- asserting both XON and READY.
--- . See dp_stream_recorder.vhd
+ -- Purpose:
+ -- . Play back a stream recorded by dp_stream_recorder.
+ -- Description:
+ -- . Playback starts as soon as the connected sink indicates to be ready by
+ -- asserting both XON and READY.
+ -- . See dp_stream_recorder.vhd
entity dp_stream_player is
generic (
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd b/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd
index fe65542bf2..92efcd0e50 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
--- Purpose:
--- . Combine dp_stream_recorder and dp_stream_player.
--- Description:
--- . g_pass_through=TRUE : Forward SOSI/SISO without touching them. Recording
--- is possible, playback is not.
--- . g_rec_not_play=TRUE : Record stream
--- . g_rec_not_play=FALSE: Play back stream
--- . See dp_stream_recorder.vhd and dp_stream_player.vhd
+ -- Purpose:
+ -- . Combine dp_stream_recorder and dp_stream_player.
+ -- Description:
+ -- . g_pass_through=TRUE : Forward SOSI/SISO without touching them. Recording
+ -- is possible, playback is not.
+ -- . g_rec_not_play=TRUE : Record stream
+ -- . g_rec_not_play=FALSE: Play back stream
+ -- . See dp_stream_recorder.vhd and dp_stream_player.vhd
entity dp_stream_rec_play is
generic (
@@ -42,7 +42,7 @@ entity dp_stream_rec_play is
g_rec_not_play : boolean := true;
g_rec_play_file : string := "dp_stream_recorder.rec";
g_record_invalid : boolean := true
- );
+ );
port (
dp_clk : in std_logic;
snk_in : in t_dp_sosi;
@@ -61,26 +61,26 @@ begin
gen_dp_sosi_recorder : if g_sim = true and g_rec_not_play = true generate
u_dp_sosi_recorder : entity work.dp_sosi_recorder
- generic map (
- g_record_file => g_rec_play_file,
- g_record_invalid => g_record_invalid
- )
- port map (
- dp_clk => dp_clk,
- snk_in => snk_in
- );
+ generic map (
+ g_record_file => g_rec_play_file,
+ g_record_invalid => g_record_invalid
+ )
+ port map (
+ dp_clk => dp_clk,
+ snk_in => snk_in
+ );
end generate;
gen_dp_stream_player : if g_sim = true and g_pass_through = false and g_rec_not_play = false generate
u_dp_stream_player : entity work.dp_stream_player
- generic map (
- g_playback_file => g_rec_play_file
- )
- port map (
- dp_clk => dp_clk,
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_playback_file => g_rec_play_file
+ )
+ port map (
+ dp_clk => dp_clk,
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
end str;
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd b/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
index 6b507231b2..3f9f2924bf 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
@@ -32,13 +32,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity dp_stream_stimuli is
generic (
@@ -150,12 +150,12 @@ begin
-- Send packet
if g_use_complex = false then
proc_dp_gen_block_data(g_in_dat_w, TO_UINT(v_sosi.data),
- g_pkt_len, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn,
- clk, stimuli_en, src_in, i_src_out);
+ g_pkt_len, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn,
+ clk, stimuli_en, src_in, i_src_out);
else
proc_dp_gen_block_complex(g_in_dat_w, TO_UINT(v_sosi.re), TO_UINT(v_sosi.im),
- g_pkt_len, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn,
- clk, stimuli_en, src_in, i_src_out);
+ g_pkt_len, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn,
+ clk, stimuli_en, src_in, i_src_out);
end if;
-- Insert optional gap between the packets
proc_common_wait_some_cycles(clk, g_pkt_gap);
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd b/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
index 374ccc129d..63d44df6c8 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
@@ -39,13 +39,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity dp_stream_verify is
generic (
diff --git a/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
index a66fd6e302..01bbf94ff7 100644
--- a/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
@@ -45,13 +45,13 @@
-- . Observe out_* signals in Wave Window
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb2_dp_demux is
generic (
@@ -192,55 +192,55 @@ begin
------------------------------------------------------------------------------
dut : entity work.dp_demux
- generic map (
- g_mode => g_mode_demux,
- g_nof_output => g_nof_streams,
- g_remove_channel_lo => g_use_channel_lo,
- g_combined => g_combined_demux
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- sel_ctrl => g_in_channel,
- -- ST sinks
- snk_out => in_siso,
- snk_in => in_sosi,
- -- ST source
- src_in_arr => demux_siso_arr,
- src_out_arr => demux_sosi_arr
- );
+ generic map (
+ g_mode => g_mode_demux,
+ g_nof_output => g_nof_streams,
+ g_remove_channel_lo => g_use_channel_lo,
+ g_combined => g_combined_demux
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ sel_ctrl => g_in_channel,
+ -- ST sinks
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- ST source
+ src_in_arr => demux_siso_arr,
+ src_out_arr => demux_sosi_arr
+ );
------------------------------------------------------------------------------
-- DUT dp_mux
------------------------------------------------------------------------------
mux : entity work.dp_mux
- generic map (
- g_data_w => c_dp_data_w,
- g_empty_w => c_dp_empty_w,
- g_in_channel_w => c_dp_data_w,
- g_error_w => 1,
- g_use_empty => true,
- g_use_in_channel => true,
- g_use_error => false,
- g_mode => g_mode_mux,
- g_nof_input => g_nof_streams,
- g_append_channel_lo => g_use_channel_lo,
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_streams), -- FIFO is not used, but generic must match g_nof_input
- g_fifo_fill => array_init( 0, g_nof_streams) -- FIFO is not used, but generic must match g_nof_input
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- sel_ctrl => g_in_channel,
- -- ST sinks
- snk_out_arr => demux_siso_arr,
- snk_in_arr => demux_sosi_arr,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_empty_w => c_dp_empty_w,
+ g_in_channel_w => c_dp_data_w,
+ g_error_w => 1,
+ g_use_empty => true,
+ g_use_in_channel => true,
+ g_use_error => false,
+ g_mode => g_mode_mux,
+ g_nof_input => g_nof_streams,
+ g_append_channel_lo => g_use_channel_lo,
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_nof_streams), -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_fill => array_init( 0, g_nof_streams) -- FIFO is not used, but generic must match g_nof_input
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ sel_ctrl => g_in_channel,
+ -- ST sinks
+ snk_out_arr => demux_siso_arr,
+ snk_in_arr => demux_sosi_arr,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
index de5f5139e0..9dc507fdb2 100644
--- a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
@@ -50,13 +50,13 @@
-- . Observe out_* signals in Wave Window
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb2_dp_mux is
generic (
@@ -250,60 +250,60 @@ begin
-- Input level multiplexing
gen_mux : for I in 0 to c_nof_type-1 generate
u_input_mux : entity dp_lib.dp_mux
+ generic map (
+ -- MUX
+ g_mode => g_mode_mux,
+ g_nof_input => c_nof_input,
+ g_append_channel_lo => c_use_channel_lo,
+ -- Input FIFO
+ g_use_fifo => g_mux_use_fifo,
+ g_bsn_w => c_data_w,
+ g_data_w => c_data_w,
+ g_use_bsn => c_use_bsn,
+ g_use_sync => c_use_sync,
+ g_fifo_size => array_init( 1024, c_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso_2arr(I),
+ snk_in_arr => in_sosi_2arr(I),
+ -- ST source
+ src_in => mux_siso_arr(I),
+ src_out => mux_sosi_arr(I)
+ );
+ end generate;
+
+ -- Second level multiplexing
+ u_type_mux : entity dp_lib.dp_mux
generic map (
-- MUX
g_mode => g_mode_mux,
- g_nof_input => c_nof_input,
+ g_nof_input => c_nof_type,
g_append_channel_lo => c_use_channel_lo,
-- Input FIFO
g_use_fifo => g_mux_use_fifo,
g_bsn_w => c_data_w,
g_data_w => c_data_w,
+ g_in_channel_w => c_channel_input_w, -- pass channel due to u_input_mux
+ g_use_in_channel => g_mux_use_fifo,
g_use_bsn => c_use_bsn,
g_use_sync => c_use_sync,
- g_fifo_size => array_init( 1024, c_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_size => array_init( 1024, c_nof_type), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_type) -- must match g_nof_input, even when g_use_fifo=FALSE
)
port map (
rst => rst,
clk => clk,
-- ST sinks
- snk_out_arr => in_siso_2arr(I),
- snk_in_arr => in_sosi_2arr(I),
+ snk_out_arr => mux_siso_arr,
+ snk_in_arr => mux_sosi_arr,
-- ST source
- src_in => mux_siso_arr(I),
- src_out => mux_sosi_arr(I)
+ src_in => mux_siso,
+ src_out => mux_sosi
);
- end generate;
-
- -- Second level multiplexing
- u_type_mux : entity dp_lib.dp_mux
- generic map (
- -- MUX
- g_mode => g_mode_mux,
- g_nof_input => c_nof_type,
- g_append_channel_lo => c_use_channel_lo,
- -- Input FIFO
- g_use_fifo => g_mux_use_fifo,
- g_bsn_w => c_data_w,
- g_data_w => c_data_w,
- g_in_channel_w => c_channel_input_w, -- pass channel due to u_input_mux
- g_use_in_channel => g_mux_use_fifo,
- g_use_bsn => c_use_bsn,
- g_use_sync => c_use_sync,
- g_fifo_size => array_init( 1024, c_nof_type), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_type) -- must match g_nof_input, even when g_use_fifo=FALSE
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => mux_siso_arr,
- snk_in_arr => mux_sosi_arr,
- -- ST source
- src_in => mux_siso,
- src_out => mux_sosi
- );
-- Map to slv to ease monitoring in wave window
mux_data <= mux_sosi.data(c_data_w - 1 downto 0);
@@ -319,28 +319,9 @@ begin
------------------------------------------------------------------------------
u_type_demux: entity dp_lib.dp_demux
- generic map (
- g_mode => c_mode_demux,
- g_nof_output => c_nof_type,
- g_remove_channel_lo => c_use_channel_lo,
- g_combined => g_combined_demux
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => mux_siso,
- snk_in => mux_sosi,
- -- ST source
- src_in_arr => demux_siso_arr,
- src_out_arr => demux_sosi_arr
- );
-
- gen_demux : for I in 0 to c_nof_type-1 generate
- u_output_demux : entity dp_lib.dp_demux
generic map (
g_mode => c_mode_demux,
- g_nof_output => c_nof_input,
+ g_nof_output => c_nof_type,
g_remove_channel_lo => c_use_channel_lo,
g_combined => g_combined_demux
)
@@ -348,13 +329,32 @@ begin
rst => rst,
clk => clk,
-- ST sinks
- snk_out => demux_siso_arr(I),
- snk_in => demux_sosi_arr(I),
+ snk_out => mux_siso,
+ snk_in => mux_sosi,
-- ST source
- src_in_arr => out_siso_2arr(I),
- src_out_arr => out_sosi_2arr(I)
+ src_in_arr => demux_siso_arr,
+ src_out_arr => demux_sosi_arr
);
+ gen_demux : for I in 0 to c_nof_type-1 generate
+ u_output_demux : entity dp_lib.dp_demux
+ generic map (
+ g_mode => c_mode_demux,
+ g_nof_output => c_nof_input,
+ g_remove_channel_lo => c_use_channel_lo,
+ g_combined => g_combined_demux
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => demux_siso_arr(I),
+ snk_in => demux_sosi_arr(I),
+ -- ST source
+ src_in_arr => out_siso_2arr(I),
+ src_out_arr => out_sosi_2arr(I)
+ );
+
gen_output : for J in 0 to c_nof_input - 1 generate
out_data(I, J) <= out_sosi_2arr(I)(J).data(c_data_w - 1 downto 0);
out_bsn( I, J) <= out_sosi_2arr(I)(J).bsn(c_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
index 47b21dc98e..b93cc29b37 100644
--- a/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
@@ -36,13 +36,13 @@
-- . interrupted.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb3_dp_demux is
generic (
@@ -186,25 +186,25 @@ begin
------------------------------------------------------------------------------
dut : entity work.dp_demux
- generic map (
- g_mode => c_mode_demux,
- g_nof_output => g_nof_outputs,
- g_remove_channel_lo => c_use_channel_lo,
- g_combined => c_combined_demux,
- g_sel_ctrl_pkt => c_sel_ctrl_pkt
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- sel_ctrl => sel_ctrl,
- -- ST sinks
- snk_out => in_siso,
- snk_in => in_sosi,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ g_mode => c_mode_demux,
+ g_nof_output => g_nof_outputs,
+ g_remove_channel_lo => c_use_channel_lo,
+ g_combined => c_combined_demux,
+ g_sel_ctrl_pkt => c_sel_ctrl_pkt
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ sel_ctrl => sel_ctrl,
+ -- ST sinks
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr
+ );
-- Use same ready stimuli for all outputs to ease verification
out_siso_arr <= (others => out_siso);
diff --git a/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
index 535656ce91..542f625ee9 100644
--- a/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
@@ -33,13 +33,13 @@
-- . The verify procedures check the correct output
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb3_dp_mux is
generic (
@@ -189,26 +189,26 @@ begin
------------------------------------------------------------------------------
mux : entity work.dp_mux
- generic map (
- -- MUX
- g_mode => c_mode_mux,
- g_nof_input => g_nof_inputs,
- g_append_channel_lo => c_use_channel_lo,
- -- Input FIFO
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_inputs), -- FIFO is not used, but generic must match g_nof_input
- g_fifo_fill => array_init( 0, g_nof_inputs) -- FIFO is not used, but generic must match g_nof_input
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- sel_ctrl => sel_ctrl,
- -- ST sinks
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ -- MUX
+ g_mode => c_mode_mux,
+ g_nof_input => g_nof_inputs,
+ g_append_channel_lo => c_use_channel_lo,
+ -- Input FIFO
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_nof_inputs), -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_fill => array_init( 0, g_nof_inputs) -- FIFO is not used, but generic must match g_nof_input
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ sel_ctrl => sel_ctrl,
+ -- ST sinks
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
index b8030bfb66..b0c66f5600 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
@@ -42,13 +42,13 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_block_from_mm is
generic (
@@ -203,70 +203,70 @@ begin
------------------------------------------------------------------------------
-- RAM with test data
u_ram_rd: entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => ram_wr_en,
- wr_adr => ram_wr_adr,
- wr_dat => ram_wr_dat,
- rd_en => rd_mosi.rd,
- rd_adr => rd_mosi.address(c_ram.adr_w - 1 downto 0),
- rd_dat => rd_miso.rddata(c_ram.dat_w - 1 downto 0),
- rd_val => rd_miso.rdval
- );
+ generic map (
+ g_ram => c_ram
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => ram_wr_en,
+ wr_adr => ram_wr_adr,
+ wr_dat => ram_wr_dat,
+ rd_en => rd_mosi.rd,
+ rd_adr => rd_mosi.address(c_ram.adr_w - 1 downto 0),
+ rd_dat => rd_miso.rddata(c_ram.dat_w - 1 downto 0),
+ rd_val => rd_miso.rdval
+ );
-- DUT, dp_block_from_mm
u_dp_block_from_mm: entity work.dp_block_from_mm
- generic map (
- g_user_size => g_data_size,
- g_data_size => g_data_size,
- g_step_size => g_step_size,
- g_nof_data => g_nof_data
- )
- port map (
- rst => rst,
- clk => clk,
- start_pulse => start_pulse,
- start_address => start_address,
- mm_done => block_done,
- mm_mosi => rd_mosi,
- mm_miso => rd_miso,
- out_sosi => blk_sosi,
- out_siso => blk_siso
- );
+ generic map (
+ g_user_size => g_data_size,
+ g_data_size => g_data_size,
+ g_step_size => g_step_size,
+ g_nof_data => g_nof_data
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ start_pulse => start_pulse,
+ start_address => start_address,
+ mm_done => block_done,
+ mm_mosi => rd_mosi,
+ mm_miso => rd_miso,
+ out_sosi => blk_sosi,
+ out_siso => blk_siso
+ );
-- DUT, dp_block_to_mm
u_dp_block_to_mm: entity work.dp_block_to_mm
- generic map (
- g_data_size => g_data_size,
- g_step_size => g_step_size,
- g_nof_data => g_nof_data
- )
- port map (
- rst => rst,
- clk => clk,
- start_address => start_address_dly,
- mm_mosi => wr_mosi,
- in_sosi => blk_sosi
- );
+ generic map (
+ g_data_size => g_data_size,
+ g_step_size => g_step_size,
+ g_nof_data => g_nof_data
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ start_address => start_address_dly,
+ mm_mosi => wr_mosi,
+ in_sosi => blk_sosi
+ );
-- RAM with transferred data
u_ram_wr: entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => wr_mosi.wr,
- wr_adr => wr_mosi.address(c_ram.adr_w - 1 downto 0),
- wr_dat => wr_mosi.wrdata(c_ram.dat_w - 1 downto 0),
- rd_en => ram_rd_en,
- rd_adr => ram_rd_adr,
- rd_dat => ram_rd_dat,
- rd_val => ram_rd_val
- );
+ generic map (
+ g_ram => c_ram
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => wr_mosi.wr,
+ wr_adr => wr_mosi.address(c_ram.adr_w - 1 downto 0),
+ wr_dat => wr_mosi.wrdata(c_ram.dat_w - 1 downto 0),
+ rd_en => ram_rd_en,
+ rd_adr => ram_rd_adr,
+ rd_dat => ram_rd_dat,
+ rd_val => ram_rd_val
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
index 0e4fc37681..b0bd54786d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
@@ -27,13 +27,13 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_block_gen is
generic (
@@ -177,26 +177,26 @@ begin
------------------------------------------------------------------------------
u_dut: entity work.dp_block_gen
- generic map (
- g_use_src_in => g_use_src_in,
- g_nof_data => g_nof_data_per_block,
- g_nof_blk_per_sync => g_nof_blk_per_sync,
- g_empty => 1,
- g_channel => 2,
- g_error => 3,
- g_bsn => c_bsn_init,
- g_preserve_sync => false,
- g_preserve_bsn => false
- )
- port map (
- rst => rst,
- clk => clk,
- -- Streaming sink
- snk_in => ref_sosi,
- -- Streaming source
- src_in => out_siso,
- src_out => out_sosi,
- -- MM control
- en => enable
- );
+ generic map (
+ g_use_src_in => g_use_src_in,
+ g_nof_data => g_nof_data_per_block,
+ g_nof_blk_per_sync => g_nof_blk_per_sync,
+ g_empty => 1,
+ g_channel => 2,
+ g_error => 3,
+ g_bsn => c_bsn_init,
+ g_preserve_sync => false,
+ g_preserve_bsn => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Streaming sink
+ snk_in => ref_sosi,
+ -- Streaming source
+ src_in => out_siso,
+ src_out => out_sosi,
+ -- MM control
+ en => enable
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
index 52b11dd5ce..2f6e5d699c 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
@@ -28,13 +28,13 @@
-- Observe out_sosi in wave window
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_block_gen_valid_arr is
generic (
@@ -135,49 +135,49 @@ begin
-- input data
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_flow_control => g_flow_control, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => g_nof_blk_per_sync,
- g_sync_offset => c_sync_offset,
- g_data_init => 0,
- g_bsn_init => TO_DP_BSN(c_bsn_init),
- g_err_init => c_err_init,
- g_err_incr => 0,
- g_channel_init => c_channel_init,
- g_channel_incr => 0,
- -- specific
- g_in_dat_w => 32,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_nof_data_per_block,
- g_pkt_gap => 0
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_out => stimuli_sosi,
-
- -- End of stimuli
- last_snk_in => OPEN, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => OPEN, -- trigger verify to verify the last_snk_in
- tb_end => tb_input_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_flow_control => g_flow_control, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => g_nof_blk_per_sync,
+ g_sync_offset => c_sync_offset,
+ g_data_init => 0,
+ g_bsn_init => TO_DP_BSN(c_bsn_init),
+ g_err_init => c_err_init,
+ g_err_incr => 0,
+ g_channel_init => c_channel_init,
+ g_channel_incr => 0,
+ -- specific
+ g_in_dat_w => 32,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_nof_data_per_block,
+ g_pkt_gap => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ last_snk_in => OPEN, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => OPEN, -- trigger verify to verify the last_snk_in
+ tb_end => tb_input_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
-- Use dp_pipeline to model the latency introduced by upstream DSP components
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dsp_latency -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => stimuli_sosi,
- -- ST source
- src_out => dsp_sosi
- );
+ generic map (
+ g_pipeline => c_dsp_latency -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_out => dsp_sosi
+ );
p_in_sosi : process(dsp_sosi, stimuli_sosi)
begin
@@ -265,23 +265,23 @@ begin
------------------------------------------------------------------------------
u_dut: entity work.dp_block_gen_valid_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_data_per_block => g_nof_data_per_block,
- g_nof_blk_per_sync => g_nof_blk_per_sync,
- g_check_input_sync => g_check_input_sync,
- g_nof_pages_bsn => g_nof_pages_bsn,
- g_restore_global_bsn => g_restore_global_bsn
- )
- port map (
- rst => rst,
- clk => clk,
- -- Streaming sink
- snk_in => in_sosi,
- snk_in_arr => in_sosi_arr,
- -- Streaming source
- src_out_arr => out_sosi_arr,
- -- MM control
- enable => enable
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_data_per_block => g_nof_data_per_block,
+ g_nof_blk_per_sync => g_nof_blk_per_sync,
+ g_check_input_sync => g_check_input_sync,
+ g_nof_pages_bsn => g_nof_pages_bsn,
+ g_restore_global_bsn => g_restore_global_bsn
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Streaming sink
+ snk_in => in_sosi,
+ snk_in_arr => in_sosi_arr,
+ -- Streaming source
+ src_out_arr => out_sosi_arr,
+ -- MM control
+ enable => enable
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
index 91d7db7738..3bb29ac41d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
@@ -42,14 +42,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_reshape is
generic (
@@ -98,83 +98,83 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => c_input_nof_blk_per_sync,
- g_nof_repeat => c_input_nof_blk_per_sync * c_nof_sync,
- g_pkt_len => c_input_nof_data_per_blk,
- g_pkt_gap => c_gap_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => c_input_nof_blk_per_sync,
+ g_nof_repeat => c_input_nof_blk_per_sync * c_nof_sync,
+ g_pkt_len => c_input_nof_data_per_blk,
+ g_pkt_gap => c_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_reshape : entity work.dp_block_reshape
- generic map (
- g_input_nof_data_per_sync => c_input_nof_data_per_sync, -- nof data per input sync interval, used only for sop_index
- g_reshape_nof_data_per_blk => c_reshape_nof_data_per_blk,
- g_pipeline_src_out => g_pipeline,
- g_pipeline_src_in => 0
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => stimuli_sosi,
- snk_out => stimuli_siso,
-
- src_out => reshape_sosi,
- src_in => reshape_siso,
- src_index_arr => reshape_index_arr -- [1] sop index, [0] valid index
- );
+ generic map (
+ g_input_nof_data_per_sync => c_input_nof_data_per_sync, -- nof data per input sync interval, used only for sop_index
+ g_reshape_nof_data_per_blk => c_reshape_nof_data_per_blk,
+ g_pipeline_src_out => g_pipeline,
+ g_pipeline_src_in => 0
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => stimuli_sosi,
+ snk_out => stimuli_siso,
+
+ src_out => reshape_sosi,
+ src_in => reshape_siso,
+ src_index_arr => reshape_index_arr -- [1] sop index, [0] valid index
+ );
u_reshape_back : entity work.dp_block_reshape
- generic map (
- g_input_nof_data_per_sync => c_input_nof_data_per_sync, -- nof data per input sync interval, used only for sop_index
- g_reshape_nof_data_per_blk => c_input_nof_data_per_blk,
- g_pipeline_src_out => 0,
- g_pipeline_src_in => g_pipeline
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => reshape_sosi,
- snk_out => reshape_siso,
-
- src_out => verify_sosi,
- src_in => verify_siso,
- src_index_arr => verify_index_arr -- [1] sop index, [0] valid index
- );
+ generic map (
+ g_input_nof_data_per_sync => c_input_nof_data_per_sync, -- nof data per input sync interval, used only for sop_index
+ g_reshape_nof_data_per_blk => c_input_nof_data_per_blk,
+ g_pipeline_src_out => 0,
+ g_pipeline_src_in => g_pipeline
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => reshape_sosi,
+ snk_out => reshape_siso,
+
+ src_out => verify_sosi,
+ src_in => verify_siso,
+ src_index_arr => verify_index_arr -- [1] sop index, [0] valid index
+ );
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline * 2
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => pipeline_siso,
- src_out => pipeline_sosi
- );
+ generic map (
+ g_pipeline => g_pipeline * 2
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => pipeline_siso,
+ src_out => pipeline_sosi
+ );
p_verify : process(clk)
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
index d03c07a6ad..0460b585b6 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
@@ -38,14 +38,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_reshape_sync is
generic (
@@ -100,98 +100,98 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_input_nof_blk_per_sync,
- g_nof_repeat => g_input_nof_blk_per_sync * c_nof_sync,
- g_pkt_len => g_input_nof_data_per_blk,
- g_pkt_gap => c_gap_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_input_nof_blk_per_sync,
+ g_nof_repeat => g_input_nof_blk_per_sync * c_nof_sync,
+ g_pkt_len => g_input_nof_data_per_blk,
+ g_pkt_gap => c_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_reshape_dut : entity work.dp_block_reshape_sync
- generic map (
- g_reshape_nof_data_per_blk => g_reshape_nof_data_per_blk,
- g_reshape_nof_blk_per_sync => g_reshape_nof_blk_per_sync,
- g_reshape_bsn => g_reshape_bsn,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => stimuli_sosi,
- snk_out => stimuli_siso,
-
- src_out => reshape_sosi,
- src_in => reshape_siso
- );
+ generic map (
+ g_reshape_nof_data_per_blk => g_reshape_nof_data_per_blk,
+ g_reshape_nof_blk_per_sync => g_reshape_nof_blk_per_sync,
+ g_reshape_bsn => g_reshape_bsn,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => stimuli_sosi,
+ snk_out => stimuli_siso,
+
+ src_out => reshape_sosi,
+ src_in => reshape_siso
+ );
u_reshape_back : entity work.dp_block_reshape_sync
- generic map (
- g_reshape_nof_data_per_blk => g_input_nof_data_per_blk,
- g_reshape_nof_blk_per_sync => g_input_nof_blk_per_sync,
- g_reshape_bsn => g_reshape_bsn,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => reshape_sosi,
- snk_out => reshape_siso,
-
- src_out => verify_sosi,
- src_in => verify_siso
- );
+ generic map (
+ g_reshape_nof_data_per_blk => g_input_nof_data_per_blk,
+ g_reshape_nof_blk_per_sync => g_input_nof_blk_per_sync,
+ g_reshape_bsn => g_reshape_bsn,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => reshape_sosi,
+ snk_out => reshape_siso,
+
+ src_out => verify_sosi,
+ src_in => verify_siso
+ );
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
u_pipeline_dut : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline -- = c_pipeline in u_reshape_dut
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => pipeline_dut_siso,
- src_out => pipeline_dut_sosi
- );
+ generic map (
+ g_pipeline => c_pipeline -- = c_pipeline in u_reshape_dut
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => pipeline_dut_siso,
+ src_out => pipeline_dut_sosi
+ );
u_pipeline_total : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline * 2 -- = c_pipeline in u_reshape_dut + c_pipeline in u_reshape_back
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => pipeline_total_siso,
- src_out => pipeline_total_sosi
- );
+ generic map (
+ g_pipeline => c_pipeline * 2 -- = c_pipeline in u_reshape_dut + c_pipeline in u_reshape_back
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => pipeline_total_siso,
+ src_out => pipeline_total_sosi
+ );
prev_reshape_sosi <= reshape_sosi when rising_edge(clk);
prev_verify_sosi <= verify_sosi when rising_edge(clk);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
index 1162980ee8..58f136731b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
@@ -37,14 +37,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_select is
generic (
@@ -93,66 +93,66 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
- g_pkt_len => c_nof_data_per_blk,
- g_pkt_gap => c_gap_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
+ g_pkt_len => c_nof_data_per_blk,
+ g_pkt_gap => c_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_select : entity work.dp_block_select
- generic map (
- g_pipeline => g_dut_pipeline,
- g_nof_blocks_per_sync => g_nof_blocks_per_sync,
- g_index_lo => g_index_lo,
- g_index_hi => g_index_hi
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- index_lo => g_index_lo,
- index_hi => g_index_hi,
- -- ST sink
- snk_out => stimuli_siso,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => verify_siso,
- src_out => verify_sosi
- );
+ generic map (
+ g_pipeline => g_dut_pipeline,
+ g_nof_blocks_per_sync => g_nof_blocks_per_sync,
+ g_index_lo => g_index_lo,
+ g_index_hi => g_index_hi
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ index_lo => g_index_lo,
+ index_hi => g_index_hi,
+ -- ST sink
+ snk_out => stimuli_siso,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => verify_siso,
+ src_out => verify_sosi
+ );
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_dut_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => g_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
stimuli_blk_cnt_reg <= stimuli_blk_cnt when rising_edge(clk);
stimuli_blk_cnt <= 0 when stimuli_sosi.sync = '1' else
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
index 9ec17af29e..a78ee0cc5c 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
@@ -31,16 +31,16 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_validate_bsn_at_sync is
generic (
@@ -102,94 +102,94 @@ begin
-- Generate in_sosi with data frames
u_stimuli_in : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => c_nof_blk,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => c_gap_size,
- g_channel_init => 0,
- g_bsn_init => TO_DP_BSN(0)
- )
- port map (
- rst => rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => c_nof_blk,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => c_gap_size,
+ g_channel_init => 0,
+ g_bsn_init => TO_DP_BSN(0)
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
-- Generate bs_sosi with data frames
u_stimuli_bs : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => c_nof_blk,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => c_gap_size,
- g_channel_init => 0,
- g_bsn_init => TO_DP_BSN(g_bsn_init)
- )
- port map (
- rst => rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => bs_siso,
- src_out => bs_sosi,
-
- -- End of stimuli
- tb_end => open
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => c_nof_blk,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => c_gap_size,
+ g_channel_init => 0,
+ g_bsn_init => TO_DP_BSN(g_bsn_init)
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => bs_siso,
+ src_out => bs_sosi,
+
+ -- End of stimuli
+ tb_end => open
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_dut : entity work.dp_block_validate_bsn_at_sync
- generic map (
- g_check_channel => c_check_channel
- )
- port map (
- dp_rst => rst,
- dp_clk => dp_clk,
-
- mm_rst => rst,
- mm_clk => mm_clk,
- -- ST sink
- in_sosi => stimuli_sosi,
- bs_sosi => bs_sosi,
- -- ST source
- out_sosi => verify_sosi,
-
- reg_mosi => reg_mosi,
- reg_miso => reg_miso
- );
+ generic map (
+ g_check_channel => c_check_channel
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ mm_rst => rst,
+ mm_clk => mm_clk,
+ -- ST sink
+ in_sosi => stimuli_sosi,
+ bs_sosi => bs_sosi,
+ -- ST source
+ out_sosi => verify_sosi,
+
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso
+ );
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dut_pipeline
- )
- port map (
- rst => rst,
- clk => dp_clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => c_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
reference_cnt_reg <= reference_cnt when rising_edge(dp_clk);
reference_cnt <= reference_cnt_reg + 1 when reference_sosi.sync = '1' else reference_cnt_reg;
p_verify : process(dp_clk)
- variable v_valid_blk : boolean := true;
+ variable v_valid_blk : boolean := true;
begin
if rising_edge(dp_clk) then
if reference_sosi.sop = '1' then -- Decide for each block if it should be valid.
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
index d6ba2d4592..cdf345c557 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
@@ -30,16 +30,16 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_validate_channel is
generic (
@@ -86,62 +86,62 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => g_gap_size
- )
- port map (
- rst => rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => g_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_dut : entity work.dp_block_validate_channel
- generic map (
- g_mode => g_mode
- )
- port map (
- dp_rst => rst,
- dp_clk => dp_clk,
-
- -- ST sink
- in_sosi => stimuli_sosi,
- -- ST source
- out_keep_sosi => keep_sosi,
- out_remove_sosi => remove_sosi,
-
- remove_channel => TO_UVEC(g_remove_channel, 32)
- );
+ generic map (
+ g_mode => g_mode
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ -- ST sink
+ in_sosi => stimuli_sosi,
+ -- ST source
+ out_keep_sosi => keep_sosi,
+ out_remove_sosi => remove_sosi,
+
+ remove_channel => TO_UVEC(g_remove_channel, 32)
+ );
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dut_pipeline
- )
- port map (
- rst => rst,
- clk => dp_clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => c_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
p_verify : process(dp_clk)
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
index fd24928a06..093dfbe111 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
@@ -34,16 +34,16 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_validate_err is
generic (
@@ -114,87 +114,87 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => g_gap_size,
- g_err_init => 0,
- g_err_incr => 1
- )
- port map (
- rst => stimuli_rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => g_gap_size,
+ g_err_init => 0,
+ g_err_incr => 1
+ )
+ port map (
+ rst => stimuli_rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_dut : entity work.dp_block_validate_err
- generic map (
- g_cnt_w => g_cnt_w,
- g_blk_cnt_w => g_cnt_w,
- g_max_block_size => g_max_block_size,
- g_nof_err_counts => g_nof_err_counts,
- g_data_w => c_word_w,
- g_bsn_w => c_dp_stream_bsn_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_sync => true
- )
- port map (
- dp_rst => rst,
- dp_clk => dp_clk,
-
- ref_sync => stimuli_sosi.sync,
-
- -- ST sink
- snk_out => stimuli_siso,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => verify_siso,
- src_out => verify_sosi,
-
- mm_rst => rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_mosi,
- reg_miso => reg_miso
- );
+ generic map (
+ g_cnt_w => g_cnt_w,
+ g_blk_cnt_w => g_cnt_w,
+ g_max_block_size => g_max_block_size,
+ g_nof_err_counts => g_nof_err_counts,
+ g_data_w => c_word_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_sync => true
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ ref_sync => stimuli_sosi.sync,
+
+ -- ST sink
+ snk_out => stimuli_siso,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => verify_siso,
+ src_out => verify_sosi,
+
+ mm_rst => rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso
+ );
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dut_pipeline
- )
- port map (
- rst => rst,
- clk => dp_clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => c_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
reference_cnt_reg <= reference_cnt when rising_edge(dp_clk);
reference_cnt <= 0 when reference_sosi.eop = '1' and ((reference_cnt_reg + 1) mod 2**g_nof_err_counts) = 0 else
- reference_cnt_reg + 1 when reference_sosi.eop = '1' else
- reference_cnt_reg;
+ reference_cnt_reg + 1 when reference_sosi.eop = '1' else
+ reference_cnt_reg;
p_verify : process(dp_clk)
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
index 2ecc70415e..0ac5c0e4d2 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
@@ -29,14 +29,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_validate_length is
generic (
@@ -85,68 +85,68 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => c_gap_size,
- g_err_init => 0,
- g_err_incr => 0
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => c_gap_size,
+ g_err_init => 0,
+ g_err_incr => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_dut : entity work.dp_block_validate_length
- generic map (
- g_err_bi => g_err_bi,
- g_expected_length => g_expected_length
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => stimuli_siso,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => verify_siso,
- src_out => verify_sosi
- );
+ generic map (
+ g_err_bi => g_err_bi,
+ g_expected_length => g_expected_length
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => stimuli_siso,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => verify_siso,
+ src_out => verify_sosi
+ );
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dut_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => c_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
stimuli_cnt_reg <= stimuli_cnt when rising_edge(clk);
stimuli_cnt <= 0 when stimuli_sosi.sop = '1' else
- stimuli_cnt_reg + 1 when stimuli_sosi.valid = '1' else
- stimuli_cnt_reg;
+ stimuli_cnt_reg + 1 when stimuli_sosi.valid = '1' else
+ stimuli_cnt_reg;
reference_cnt <= stimuli_cnt when rising_edge(clk);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
index 5b799b6b68..d6e9299511 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
@@ -33,13 +33,13 @@
-- automatically.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_align is
generic (
@@ -285,7 +285,7 @@ begin
verify_dis_arr <= (others => '0');
proc_common_wait_some_cycles(clk, 1000);
--- verify_dis_arr <= (OTHERS=>'1');
+ -- verify_dis_arr <= (OTHERS=>'1');
-- . enforce large BSN misalignment
tb_state <= s_large_bsn_diff;
@@ -294,8 +294,8 @@ begin
proc_common_wait_until_high(clk, bsn_event_ack);
bsn_event <= '0';
-- expect no output, because difference remains too large, so do not restart verify_en here and leave it commented:
--- proc_common_wait_some_cycles(clk, 100);
--- verify_dis_arr <= (OTHERS=>'0');
+ -- proc_common_wait_some_cycles(clk, 100);
+ -- verify_dis_arr <= (OTHERS=>'0');
proc_common_wait_some_cycles(clk, 1000);
verify_dis_arr <= (others => '1');
@@ -405,25 +405,25 @@ begin
------------------------------------------------------------------------------
u_bsn_align : entity work.dp_bsn_align
- generic map (
- g_block_size => g_block_size,
- g_nof_input => g_nof_input,
- g_xoff_timeout => c_xoff_timeout,
- g_sop_timeout => c_sop_timeout,
- g_bsn_latency => g_bsn_latency,
- g_bsn_request_pipeline => g_bsn_request_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr,
- -- MM
- in_en_evt => in_en_event,
- in_en_arr => in_en_arr
- );
+ generic map (
+ g_block_size => g_block_size,
+ g_nof_input => g_nof_input,
+ g_xoff_timeout => c_xoff_timeout,
+ g_sop_timeout => c_sop_timeout,
+ g_bsn_latency => g_bsn_latency,
+ g_bsn_request_pipeline => g_bsn_request_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr,
+ -- MM
+ in_en_evt => in_en_event,
+ in_en_arr => in_en_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
index 2003d4327f..e4fb86ceb4 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
@@ -28,13 +28,13 @@
-- . The verify procedures check the correct input and monitor results
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_monitor is
generic (
@@ -305,34 +305,34 @@ begin
-- Tap the stream to the monitor
dut : entity work.dp_bsn_monitor
- generic map (
- g_log_first_bsn => false,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- ST interface
- in_siso => out_siso,
- in_sosi => in_sosi,
- sync_in => sync_in,
-
- -- MM interface
- -- . control
- mon_evt => mon_evt,
- mon_sync => mon_sync,
- mon_sync_timeout => mon_sync_timeout,
- -- . siso
- mon_ready_stable => mon_ready_stable,
- mon_xon_stable => mon_xon_stable,
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync,
- mon_nof_sop => mon_nof_sop,
- mon_nof_err => mon_nof_err,
- mon_nof_valid => mon_nof_valid,
-
- mon_bsn_first => mon_bsn_first,
- mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt
- );
+ generic map (
+ g_log_first_bsn => false,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- ST interface
+ in_siso => out_siso,
+ in_sosi => in_sosi,
+ sync_in => sync_in,
+
+ -- MM interface
+ -- . control
+ mon_evt => mon_evt,
+ mon_sync => mon_sync,
+ mon_sync_timeout => mon_sync_timeout,
+ -- . siso
+ mon_ready_stable => mon_ready_stable,
+ mon_xon_stable => mon_xon_stable,
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync,
+ mon_nof_sop => mon_nof_sop,
+ mon_nof_err => mon_nof_err,
+ mon_nof_valid => mon_nof_valid,
+
+ mon_bsn_first => mon_bsn_first,
+ mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
index 8f76b0058e..62f23aa343 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
@@ -28,13 +28,13 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_monitor_v2 is
generic (
@@ -305,31 +305,31 @@ begin
-- Tap the stream to the monitor
dut : entity work.dp_bsn_monitor_v2
- generic map (
- g_sync_timeout => c_sync_timeout
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- ST interface
- in_siso => out_siso,
- in_sosi => in_sosi,
- ref_sync => ref_sync,
-
- -- MM interface
- -- . control
- mon_evt => mon_evt,
- mon_sync => mon_sync,
- mon_sync_timeout => mon_sync_timeout,
- -- . siso
- mon_ready_stable => mon_ready_stable,
- mon_xon_stable => mon_xon_stable,
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync,
- mon_nof_sop => mon_nof_sop,
- mon_nof_err => mon_nof_err,
- mon_nof_valid => mon_nof_valid,
- mon_latency => mon_latency
- );
+ generic map (
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- ST interface
+ in_siso => out_siso,
+ in_sosi => in_sosi,
+ ref_sync => ref_sync,
+
+ -- MM interface
+ -- . control
+ mon_evt => mon_evt,
+ mon_sync => mon_sync,
+ mon_sync_timeout => mon_sync_timeout,
+ -- . siso
+ mon_ready_stable => mon_ready_stable,
+ mon_xon_stable => mon_xon_stable,
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync,
+ mon_nof_sop => mon_nof_sop,
+ mon_nof_err => mon_nof_err,
+ mon_nof_valid => mon_nof_valid,
+ mon_latency => mon_latency
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
index 77429b4b4f..ff14aa970a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
@@ -27,12 +27,12 @@
-- and then manually verify on/off in Wave window
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_source is
end tb_dp_bsn_source;
@@ -155,20 +155,20 @@ begin
-----------------------------------------------------------------------------
dut : entity work.dp_bsn_source
- generic map (
- g_block_size => c_block_size,
- g_nof_block_per_sync => c_sync_period,
- g_bsn_w => c_bsn_w
- )
- port map (
- rst => rst,
- clk => clk,
- pps => pps,
- -- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
- init_bsn => init_bsn,
- -- Streaming
- src_out => bs_sosi
- );
+ generic map (
+ g_block_size => c_block_size,
+ g_nof_block_per_sync => c_sync_period,
+ g_bsn_w => c_bsn_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pps => pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+ init_bsn => init_bsn,
+ -- Streaming
+ src_out => bs_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
index d8de93d613..b71a6b5b2e 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
@@ -43,12 +43,12 @@
-- . sync and bsn are verified automatically using the ref_grid
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_source_v2 is
generic (
@@ -259,16 +259,16 @@ begin
-- Verify sync at sop and at expected_sync
proc_dp_verify_sync(0, -- start bsn of PPS grid and BSN grid is 0, see [1]
- g_pps_interval,
- g_block_size,
- clk,
- verify_en,
- bs_sosi.sync,
- bs_sosi.sop,
- bs_sosi.bsn,
- dbg_nof_blk,
- dbg_accumulate,
- dbg_expected_bsn);
+ g_pps_interval,
+ g_block_size,
+ clk,
+ verify_en,
+ bs_sosi.sync,
+ bs_sosi.sop,
+ bs_sosi.bsn,
+ dbg_nof_blk,
+ dbg_accumulate,
+ dbg_expected_bsn);
-- Verify bs_sosi by comparing with exp_grid, this again verifies bs_sosi.sync, sop and bsn
p_verify_bs_sosi_grid : process(clk)
@@ -324,28 +324,28 @@ begin
-----------------------------------------------------------------------------
dut : entity work.dp_bsn_source_v2
- generic map (
- g_block_size => g_block_size,
- g_nof_clk_per_sync => g_pps_interval,
- g_bsn_w => c_bsn_w,
- g_bsn_time_offset_w => c_bsn_time_offset_w
- )
- port map (
- rst => rst,
- clk => clk,
- pps => ref_grid.pps,
- -- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
-
- dp_on_status => dp_on_status, -- = src_out.valid
- bs_restart => bs_restart, -- = src_out.sync for first sync after dp_on went high
- bs_new_interval => bs_new_interval, -- active during first src_out.sync interval
-
- bsn_init => bsn_init,
- bsn_time_offset => bsn_time_offset,
-
- -- Streaming
- src_out => bs_sosi
- );
+ generic map (
+ g_block_size => g_block_size,
+ g_nof_clk_per_sync => g_pps_interval,
+ g_bsn_w => c_bsn_w,
+ g_bsn_time_offset_w => c_bsn_time_offset_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pps => ref_grid.pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+
+ dp_on_status => dp_on_status, -- = src_out.valid
+ bs_restart => bs_restart, -- = src_out.sync for first sync after dp_on went high
+ bs_new_interval => bs_new_interval, -- active during first src_out.sync interval
+
+ bsn_init => bsn_init,
+ bsn_time_offset => bsn_time_offset,
+
+ -- Streaming
+ src_out => bs_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
index 9506ca762c..088dab377b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
@@ -31,14 +31,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_calculate_crc is
generic (
@@ -85,22 +85,22 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => c_nof_blk_per_sync,
- g_nof_repeat => c_nof_blk_per_sync * c_nof_sync,
- g_pkt_len => c_nof_data_per_blk,
- g_pkt_gap => g_gap_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => c_nof_blk_per_sync,
+ g_nof_repeat => c_nof_blk_per_sync * c_nof_sync,
+ g_pkt_len => c_nof_data_per_blk,
+ g_pkt_gap => g_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
-- Use same dat for every block to verify restart of CRC calculation
p_snk_in : process(stimuli_sosi)
@@ -113,17 +113,17 @@ begin
-- DUT
------------------------------------------------------------------------------
u_crc : entity work.dp_calculate_crc
- generic map (
- g_data_w => g_data_w,
- g_crc_w => g_crc_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => snk_in,
- blk_crc => blk_crc
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_crc_w => g_crc_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => snk_in,
+ blk_crc => blk_crc
+ );
------------------------------------------------------------------------------
-- Verifycation
@@ -135,11 +135,11 @@ begin
if rising_edge(clk) then
if new_crc = '1' then
--IF g_data_w = 28 AND g_crc_w = 28 AND c_nof_data_per_blk = 9 THEN
- if blk_crc = exp_crc_28 then
- report "OK CRC value." severity NOTE;
- else
- report "Wrong CRC value." severity ERROR;
- end if;
+ if blk_crc = exp_crc_28 then
+ report "OK CRC value." severity NOTE;
+ else
+ report "Wrong CRC value." severity ERROR;
+ end if;
--END IF;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd b/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
index e4ceabe74d..362d018ed3 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_concat is
generic (
@@ -148,18 +148,18 @@ begin
end process;
dut : entity work.dp_concat
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
- snk_in_arr => in_sosi_arr,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
+ snk_in_arr => in_sosi_arr,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
-- Input data
in_data_0 <= in_sosi_arr(0).data(g_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd b/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
index aea02918e9..d3fc68642b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
@@ -36,15 +36,15 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_concat_field_blk is
generic (
@@ -93,29 +93,30 @@ architecture tb of tb_dp_concat_field_blk is
-- Notes:
-- . pre-calculated ip_header_checksum is valid only for UNB0, FN0 targeting IP 10.10.10.10
-- . udp_total_length = 176 beamlets * 64b / 8b = 1408B + 14 DP bytes + 8 UDP bytes = 1430B
- constant c_udp_offload_hdr_field_arr : t_common_field_arr(c_udp_offload_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ),
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ),
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(29928) ),
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ),
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ),
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("dp_reserved" ), "RW", 47, field_default(0) ),
- ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
- ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) ) );
+ constant c_udp_offload_hdr_field_arr : t_common_field_arr(
+ c_udp_offload_nof_hdr_fields - 1 downto 0) := (
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ),
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ),
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(29928) ),
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ),
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ),
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ),
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("dp_reserved" ), "RW", 47, field_default(0) ),
+ ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) ) );
-- From apertif_unb1_fn_beamformer_udp_offload.vhd:
-- Override ('1') only the Ethernet fields so we can use MM defaults there.
@@ -194,36 +195,36 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- -- specific
- g_in_dat_w => g_data_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_wait_last_evt
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ -- specific
+ g_in_dat_w => g_data_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_wait_last_evt
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -257,37 +258,37 @@ begin
verify_last_snk_in_evt.err <= '0';
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => g_data_w,
- g_pkt_len => c_expected_pkt_len
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => g_data_w,
+ g_pkt_len => c_expected_pkt_len
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT offload Tx
@@ -297,23 +298,23 @@ begin
-- Use FIFO to mimic apertif_unb1_fn_beamformer_udp_offload.vhd, without FIFO dp_stream_stimuli
-- would handle the back pressure
u_dp_fifo_sc : entity work.dp_fifo_sc
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => 64,
- g_use_sync => true,
- g_use_bsn => true,
- g_fifo_size => 1024
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => OPEN, -- stimuli_src_in
- snk_in => stimuli_src_out,
-
- src_in => dp_fifo_sc_src_in,
- src_out => dp_fifo_sc_src_out
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => 64,
+ g_use_sync => true,
+ g_use_bsn => true,
+ g_fifo_size => 1024
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => OPEN, -- stimuli_src_in
+ snk_in => stimuli_src_out,
+
+ src_in => dp_fifo_sc_src_in,
+ src_out => dp_fifo_sc_src_out
+ );
dp_offload_tx_snk_in_arr(0) <= dp_fifo_sc_src_out;
dp_fifo_sc_src_in <= dp_offload_tx_snk_out_arr(0);
@@ -332,31 +333,31 @@ begin
tx_hdr_fields_in_arr(0)(field_hi(c_udp_offload_hdr_field_arr, "dp_bsn" ) downto field_lo(c_udp_offload_hdr_field_arr, "dp_bsn" )) <= dp_offload_tx_snk_in_arr(0).bsn(63 downto 0);
u_tx : entity work.dp_concat_field_blk
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_symbol_w => g_data_w,
- g_hdr_field_arr => c_udp_offload_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_tx_snk_in_arr,
- snk_out_arr => dp_offload_tx_snk_out_arr,
-
- src_out_arr => tx_offload_sosi_arr,
- src_in_arr => tx_offload_siso_arr,
-
- hdr_fields_in_arr => tx_hdr_fields_in_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_symbol_w => g_data_w,
+ g_hdr_field_arr => c_udp_offload_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_tx_snk_in_arr,
+ snk_out_arr => dp_offload_tx_snk_out_arr,
+
+ src_out_arr => tx_offload_sosi_arr,
+ src_in_arr => tx_offload_siso_arr,
+
+ hdr_fields_in_arr => tx_hdr_fields_in_arr
+ );
------------------------------------------------------------------------------
-- Link
@@ -380,32 +381,32 @@ begin
------------------------------------------------------------------------------
u_rx : entity work.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_udp_offload_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- snk_in_arr => link_offload_sosi_arr,
- snk_out_arr => link_offload_siso_arr,
-
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
-
- hdr_fields_out_arr => rx_hdr_fields_out_arr,
- hdr_fields_raw_arr => rx_hdr_fields_raw_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_udp_offload_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ snk_in_arr => link_offload_sosi_arr,
+ snk_out_arr => link_offload_siso_arr,
+
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => rx_hdr_fields_out_arr,
+ hdr_fields_raw_arr => rx_hdr_fields_raw_arr
+ );
p_restore_sync_bsn : process(dp_offload_rx_src_out_arr, rx_hdr_fields_out_arr)
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
index 50c0401ffe..d18b5d6471 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
@@ -32,14 +32,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_counter is
generic (
@@ -145,13 +145,13 @@ begin
-- Generate snk_in incrementing data with valid
proc_dp_gen_data(c_rl,
- c_data_w,
- c_data_init,
- rst,
- clk,
- in_en,
- snk_out,
- snk_in);
+ c_data_w,
+ c_data_init,
+ rst,
+ clk,
+ in_en,
+ snk_out,
+ snk_in);
p_stimuli : process
begin
@@ -168,26 +168,26 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dp_counter : entity work.dp_counter
- generic map (
- g_nof_counters => g_nof_counters,
- g_range_start => g_range_start,
- g_range_stop => g_range_stop,
- g_range_step => g_range_step,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => snk_in,
- snk_out => snk_out,
-
- src_out => src_out,
- src_in => src_in,
-
- count_src_out_arr => count_src_out_arr
- );
+ generic map (
+ g_nof_counters => g_nof_counters,
+ g_range_start => g_range_start,
+ g_range_stop => g_range_stop,
+ g_range_step => g_range_step,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => snk_in,
+ snk_out => snk_out,
+
+ src_out => src_out,
+ src_in => src_in,
+
+ count_src_out_arr => count_src_out_arr
+ );
------------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
index 0d79d8e8f6..a8e81de150 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
@@ -32,14 +32,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_counter_offset is
generic (
@@ -148,13 +148,13 @@ begin
-- Generate snk_in incrementing data with valid
proc_dp_gen_data(c_rl,
- c_data_w,
- c_data_init,
- rst,
- clk,
- in_en,
- snk_out,
- snk_in);
+ c_data_w,
+ c_data_init,
+ rst,
+ clk,
+ in_en,
+ snk_out,
+ snk_in);
p_stimuli : process
begin
@@ -172,27 +172,27 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dp_counter : entity work.dp_counter
- generic map (
- g_nof_counters => g_nof_counters,
- g_range_start => g_range_start,
- g_range_stop => g_range_stop,
- g_range_step => g_range_step,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => snk_in,
- snk_out => snk_out,
-
- src_out => src_out,
- src_in => src_in,
-
- count_offset_in_arr => count_offset_in_arr,
- count_src_out_arr => count_src_out_arr
- );
+ generic map (
+ g_nof_counters => g_nof_counters,
+ g_range_start => g_range_start,
+ g_range_stop => g_range_stop,
+ g_range_step => g_range_step,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => snk_in,
+ snk_out => snk_out,
+
+ src_out => src_out,
+ src_in => src_in,
+
+ count_offset_in_arr => count_offset_in_arr,
+ count_src_out_arr => count_src_out_arr
+ );
------------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd
index 033d1fe079..640c537ce2 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd
@@ -20,20 +20,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.tb_dp_pkg.all;
-
--- Purpose: Test bench to check deinterleave function on DP level
--- Usage:
--- > as 6
--- > run -all
--- Remark:
--- This TB is only used to visually inspect the wave window to see
--- if all functions well on DP level. The actual deinterleaving itself
--- is verified more thoroughly in tb_common_reinterleave.
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.tb_dp_pkg.all;
+
+ -- Purpose: Test bench to check deinterleave function on DP level
+ -- Usage:
+ -- > as 6
+ -- > run -all
+ -- Remark:
+ -- This TB is only used to visually inspect the wave window to see
+ -- if all functions well on DP level. The actual deinterleaving itself
+ -- is verified more thoroughly in tb_common_reinterleave.
entity tb_dp_deinterleave is
generic (
@@ -41,7 +41,7 @@ entity tb_dp_deinterleave is
g_nof_out : natural := 2;
g_block_size : natural := 3;
g_use_complex : boolean := true
- );
+ );
end;
architecture tb of tb_dp_deinterleave is
@@ -108,26 +108,26 @@ begin
proc_common_wait_some_cycles(clk, c_input_inval);
v_bsn := INCR_UVEC(v_bsn, 1);
end loop;
- end process;
+ end process;
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
u_deinterleave : entity work.dp_deinterleave
- generic map (
- g_nof_out => g_nof_out,
- g_block_size_int => g_block_size,
- g_block_size_output => g_block_size,
- g_dat_w => g_dat_w,
- g_use_complex => g_use_complex
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => snk_in,
- src_out_arr => src_out_arr
- );
+ generic map (
+ g_nof_out => g_nof_out,
+ g_block_size_int => g_block_size,
+ g_block_size_output => g_block_size,
+ g_dat_w => g_dat_w,
+ g_use_complex => g_use_complex
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => snk_in,
+ src_out_arr => src_out_arr
+ );
-----------------------------------------------------------------------------
-- Wave window monitor
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
index 9d28335701..461d7421cc 100755
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
@@ -43,14 +43,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_deinterleave_interleave_to_one is
generic (
@@ -97,9 +97,10 @@ architecture tb of tb_dp_deinterleave_interleave_to_one is
constant c_flow_control_latency_pls : natural := g_nof_repeat * g_pkt_len * (c_verify_pulse_period * c_stimuli_pulse_period) / (c_stimuli_pulse_active * c_verify_pulse_active);
constant c_flow_control_latency_rnd : natural := g_nof_repeat * g_pkt_len;
- constant c_flow_control_latency : natural := sel_a_b(g_flow_control_stimuli = e_pulse or c_flow_control_verify = e_pulse,
- c_flow_control_latency_pls,
- c_flow_control_latency_rnd); -- worst case value
+ constant c_flow_control_latency : natural := sel_a_b(
+ g_flow_control_stimuli = e_pulse or c_flow_control_verify = e_pulse,
+ c_flow_control_latency_pls,
+ c_flow_control_latency_rnd); -- worst case value
constant c_data_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
constant c_dsp_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
@@ -142,43 +143,43 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_use_complex => g_use_complex,
- g_data_init => c_data_init,
- g_re_init => c_re_init,
- g_im_init => c_im_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => c_data_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_use_complex => g_use_complex,
+ g_data_init => c_data_init,
+ g_re_init => c_re_init,
+ g_im_init => c_im_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
-- Throttle stimuli to ensure active = 1, period = 3, level '1'
--proc_common_gen_pulse(1, 3, '1', rst, clk, stimuli_src_in.ready);
@@ -215,108 +216,108 @@ begin
verify_last_snk_in_evt.err <= '0';
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => c_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => c_data_w,
- g_pkt_len => c_out_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => c_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_pkt_len => c_out_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT: 1 to N
------------------------------------------------------------------------------
u_dp_deinterleave : entity work.dp_deinterleave
- generic map (
- g_dat_w => c_data_w,
- g_nof_out => g_nof_streams,
- g_block_size_int => 1,
- g_block_size_output => c_par_pkt_len, -- Output block size: The number of samles in the blocks at the output
- g_use_ctrl => true, -- Requires: [input block size (sop:eop)] / [g_nof_out]/ [g_block_size_output] = integer number!
- g_use_sync_bsn => true, -- forwards (stored) input Sync+BSN to all output streams
- g_use_complex => g_use_complex,
- g_align_out => true -- Aligns the output streams
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => stimuli_src_out,
- src_out_arr => parallel_snk_in_arr
- );
-
- -- Use FIFO to break flow control between one to N and N to one, so that stimuli see ready = '1'
- gen_fifos : for I in 0 to g_nof_streams - 1 generate
- u_dp_fifo_sc : entity work.dp_fifo_sc
generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_dp_stream_dsp_data_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_error => true,
- g_use_sync => true,
- g_use_ctrl => true, -- sop & eop
- g_use_complex => g_use_complex, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size => c_fifo_size -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_dat_w => c_data_w,
+ g_nof_out => g_nof_streams,
+ g_block_size_int => 1,
+ g_block_size_output => c_par_pkt_len, -- Output block size: The number of samles in the blocks at the output
+ g_use_ctrl => true, -- Requires: [input block size (sop:eop)] / [g_nof_out]/ [g_block_size_output] = integer number!
+ g_use_sync_bsn => true, -- forwards (stored) input Sync+BSN to all output streams
+ g_use_complex => g_use_complex,
+ g_align_out => true -- Aligns the output streams
)
port map (
rst => rst,
clk => clk,
- -- Monitor FIFO filling
- -- ST sink
- snk_out => parallel_snk_out_arr(I),
- snk_in => parallel_snk_in_arr(I),
- -- ST source
- src_in => parallel_src_in_arr(I),
- src_out => parallel_src_out_arr(I)
+
+ snk_in => stimuli_src_out,
+ src_out_arr => parallel_snk_in_arr
);
+
+ -- Use FIFO to break flow control between one to N and N to one, so that stimuli see ready = '1'
+ gen_fifos : for I in 0 to g_nof_streams - 1 generate
+ u_dp_fifo_sc : entity work.dp_fifo_sc
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_dp_stream_dsp_data_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_error_w => c_dp_stream_error_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ g_use_ctrl => true, -- sop & eop
+ g_use_complex => g_use_complex, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_size => c_fifo_size -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ -- ST sink
+ snk_out => parallel_snk_out_arr(I),
+ snk_in => parallel_snk_in_arr(I),
+ -- ST source
+ src_in => parallel_src_in_arr(I),
+ src_out => parallel_src_out_arr(I)
+ );
end generate;
------------------------------------------------------------------------------
-- DUT: N to 1
------------------------------------------------------------------------------
u_n_to_one: entity work.dp_interleave_n_to_one
- generic map (
- g_pipeline => c_pipeline,
- g_nof_inputs => g_nof_streams
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out_arr => parallel_src_in_arr,
- snk_in_arr => parallel_src_out_arr,
- src_in => verify_snk_out,
- src_out => verify_snk_in
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_nof_inputs => g_nof_streams
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out_arr => parallel_src_in_arr,
+ snk_in_arr => parallel_src_out_arr,
+ src_in => verify_snk_out,
+ src_out => verify_snk_in
+ );
------------------------------------------------------------------------------
-- Auxiliary
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
index 85bdf4243f..16d8fc3da8 100755
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
@@ -37,14 +37,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_deinterleave_one_to_n_to_one is
generic (
@@ -89,9 +89,10 @@ architecture tb of tb_dp_deinterleave_one_to_n_to_one is
constant c_flow_control_latency_pls : natural := g_nof_repeat * g_pkt_len * (c_verify_pulse_period * c_stimuli_pulse_period) / (c_stimuli_pulse_active * c_verify_pulse_active);
constant c_flow_control_latency_rnd : natural := g_nof_repeat * g_pkt_len;
- constant c_flow_control_latency : natural := sel_a_b(g_flow_control_stimuli = e_pulse or g_flow_control_verify = e_pulse,
- c_flow_control_latency_pls,
- c_flow_control_latency_rnd); -- worst case value
+ constant c_flow_control_latency : natural := sel_a_b(
+ g_flow_control_stimuli = e_pulse or g_flow_control_verify = e_pulse,
+ c_flow_control_latency_pls,
+ c_flow_control_latency_rnd); -- worst case value
constant c_data_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
constant c_dsp_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
@@ -134,43 +135,43 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_use_complex => g_use_complex,
- g_data_init => c_data_init,
- g_re_init => c_re_init,
- g_im_init => c_im_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => c_data_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_use_complex => g_use_complex,
+ g_data_init => c_data_init,
+ g_re_init => c_re_init,
+ g_im_init => c_im_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -204,55 +205,55 @@ begin
verify_last_snk_in_evt.err <= last_snk_in_evt;
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => c_data_w,
- g_pkt_len => c_out_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_pkt_len => c_out_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT: 1 to N
------------------------------------------------------------------------------
u_one_to_n : entity work.dp_deinterleave_one_to_n
- generic map (
- g_pipeline => g_pipeline,
- g_nof_outputs => g_nof_streams
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => stimuli_src_in,
- snk_in => stimuli_src_out,
- src_in_arr => parallel_snk_out_arr,
- src_out_arr => parallel_snk_in_arr
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_nof_outputs => g_nof_streams
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => stimuli_src_in,
+ snk_in => stimuli_src_out,
+ src_in_arr => parallel_snk_out_arr,
+ src_out_arr => parallel_snk_in_arr
+ );
no_fifo : if g_use_fifo = false generate
parallel_snk_out_arr <= parallel_src_in_arr;
@@ -263,32 +264,32 @@ begin
use_fifo : if g_use_fifo = true generate
gen_fifos : for I in 0 to g_nof_streams - 1 generate
u_dp_fifo_sc : entity work.dp_fifo_sc
- generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_dp_stream_dsp_data_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_error => true,
- g_use_sync => true,
- g_use_ctrl => true, -- sop & eop
- g_use_complex => g_use_complex, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size => c_fifo_size -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor FIFO filling
- -- ST sink
- snk_out => parallel_snk_out_arr(I),
- snk_in => parallel_snk_in_arr(I),
- -- ST source
- src_in => parallel_src_in_arr(I),
- src_out => parallel_src_out_arr(I)
- );
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_dp_stream_dsp_data_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_error_w => c_dp_stream_error_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ g_use_ctrl => true, -- sop & eop
+ g_use_complex => g_use_complex, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_size => c_fifo_size -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ -- ST sink
+ snk_out => parallel_snk_out_arr(I),
+ snk_in => parallel_snk_in_arr(I),
+ -- ST source
+ src_in => parallel_src_in_arr(I),
+ src_out => parallel_src_out_arr(I)
+ );
end generate;
end generate;
@@ -296,19 +297,19 @@ begin
-- DUT: N to 1
------------------------------------------------------------------------------
u_n_to_one: entity work.dp_interleave_n_to_one
- generic map (
- g_pipeline => g_pipeline,
- g_nof_inputs => g_nof_streams
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out_arr => parallel_src_in_arr,
- snk_in_arr => parallel_src_out_arr,
- src_in => verify_snk_out,
- src_out => verify_snk_in
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_nof_inputs => g_nof_streams
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out_arr => parallel_src_in_arr,
+ snk_in_arr => parallel_src_out_arr,
+ src_in => verify_snk_out,
+ src_out => verify_snk_in
+ );
------------------------------------------------------------------------------
-- Auxiliary
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
index 16b878e544..fe163083f5 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_demux is
generic (
@@ -161,8 +161,8 @@ begin
in_channel_vec((I + 1) * c_dp_data_w - 1 downto I * c_dp_data_w) <= in_channel(I);
-- Stimuli control
--- proc_dp_count_en(rst, clk, sync, lfsr1(I)(c_random_w-1 DOWNTO 0), state(I), verify_done(I), tb_end_vec(I), cnt_en(I)); -- all cnt_en behave the same
--- proc_dp_out_ready(rst, clk, sync, lfsr2(I)(c_random_w DOWNTO 0), out_ready(I)); -- all out_ready behave the same
+ -- proc_dp_count_en(rst, clk, sync, lfsr1(I)(c_random_w-1 DOWNTO 0), state(I), verify_done(I), tb_end_vec(I), cnt_en(I)); -- all cnt_en behave the same
+ -- proc_dp_out_ready(rst, clk, sync, lfsr2(I)(c_random_w DOWNTO 0), out_ready(I)); -- all out_ready behave the same
proc_dp_count_en(rst, clk, sync_dly(I), lfsr1(I)(c_random_w - 1 downto 0), state(I), verify_done(I), tb_end_vec(I), cnt_en(I)); -- all cnt_en are relatively delayed
proc_dp_out_ready(rst, clk, sync_dly(I), lfsr2(I)(c_random_w downto 0), out_ready(I)); -- all out_ready are relatively delayed
@@ -220,47 +220,47 @@ begin
end process;
mux : entity work.dp_mux
- generic map (
- g_data_w => c_dp_data_w,
- g_empty_w => c_dp_empty_w,
- g_in_channel_w => c_dp_data_w,
- g_error_w => 1,
- g_use_empty => true,
- g_use_in_channel => true,
- g_use_error => false,
- g_nof_input => g_dut_nof_output,
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_dut_nof_output), -- FIFO is not used, but generic must match g_nof_input
- g_fifo_fill => array_init( 0, g_dut_nof_output) -- FIFO is not used, but generic must match g_nof_input
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => in_siso, -- OUT = request to upstream ST source
- snk_in_arr => in_sosi,
- -- ST source
- src_in => mux_siso, -- IN = request from downstream ST sink
- src_out => mux_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_empty_w => c_dp_empty_w,
+ g_in_channel_w => c_dp_data_w,
+ g_error_w => 1,
+ g_use_empty => true,
+ g_use_in_channel => true,
+ g_use_error => false,
+ g_nof_input => g_dut_nof_output,
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_dut_nof_output), -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_fill => array_init( 0, g_dut_nof_output) -- FIFO is not used, but generic must match g_nof_input
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso, -- OUT = request to upstream ST source
+ snk_in_arr => in_sosi,
+ -- ST source
+ src_in => mux_siso, -- IN = request from downstream ST sink
+ src_out => mux_sosi
+ );
------------------------------------------------------------------------------
-- DUT dp_demux
------------------------------------------------------------------------------
dut : entity work.dp_demux
- generic map (
- g_nof_output => g_dut_nof_output,
- g_combined => g_combined
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => mux_siso, -- OUT = request to upstream ST source
- snk_in => mux_sosi,
- -- ST source
- src_in_arr => demux_siso, -- IN = request from downstream ST sink
- src_out_arr => demux_sosi
- );
+ generic map (
+ g_nof_output => g_dut_nof_output,
+ g_combined => g_combined
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => mux_siso, -- OUT = request to upstream ST source
+ snk_in => mux_sosi,
+ -- ST source
+ src_in_arr => demux_siso, -- IN = request from downstream ST sink
+ src_out_arr => demux_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd b/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
index 6fe69179da..dbde8415b3 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
@@ -39,13 +39,13 @@
-- would need to use DP packet encoder and decoders.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_distribute is
generic (
@@ -239,71 +239,71 @@ begin
-- n --> m
tx : entity work.dp_distribute
- generic map (
- -- Distribution IO
- g_tx => true,
- g_nof_input => g_nof_input,
- g_nof_output => g_nof_serial,
- g_transpose => g_transpose,
- g_code_channel_lo => g_code_channel_lo,
- g_data_w => c_data_w,
- -- Input FIFO
- g_use_fifo => g_tx_use_fifo,
- g_bsn_w => c_data_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_bsn => g_tx_use_fifo,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_sync => g_tx_use_fifo,
- g_fifo_fill => g_tx_fifo_fill,
- g_fifo_size => c_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_in_arr => serial_siso_arr,
- src_out_arr => serial_sosi_arr
- );
+ generic map (
+ -- Distribution IO
+ g_tx => true,
+ g_nof_input => g_nof_input,
+ g_nof_output => g_nof_serial,
+ g_transpose => g_transpose,
+ g_code_channel_lo => g_code_channel_lo,
+ g_data_w => c_data_w,
+ -- Input FIFO
+ g_use_fifo => g_tx_use_fifo,
+ g_bsn_w => c_data_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_bsn => g_tx_use_fifo,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_sync => g_tx_use_fifo,
+ g_fifo_fill => g_tx_fifo_fill,
+ g_fifo_size => c_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_in_arr => serial_siso_arr,
+ src_out_arr => serial_sosi_arr
+ );
-- m --> n
rx : entity work.dp_distribute
- generic map (
- -- Distribution IO
- g_tx => false,
- g_nof_input => g_nof_serial,
- g_nof_output => g_nof_input,
- g_transpose => g_transpose,
- g_code_channel_lo => g_code_channel_lo,
- g_data_w => c_data_w,
- -- Input FIFO
- g_use_fifo => g_rx_use_fifo,
- g_bsn_w => c_data_w,
- g_empty_w => 1,
- g_channel_w => c_link_channel_lo, -- c_link_channel_lo-1 DOWNTO 0
- g_error_w => 1,
- g_use_bsn => g_rx_use_fifo,
- g_use_empty => false,
- g_use_channel => c_rx_use_fifo_link_channel_lo,
- g_use_error => false,
- g_use_sync => g_rx_use_fifo,
- g_fifo_fill => g_rx_fifo_fill,
- g_fifo_size => c_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => serial_siso_arr,
- snk_in_arr => serial_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ -- Distribution IO
+ g_tx => false,
+ g_nof_input => g_nof_serial,
+ g_nof_output => g_nof_input,
+ g_transpose => g_transpose,
+ g_code_channel_lo => g_code_channel_lo,
+ g_data_w => c_data_w,
+ -- Input FIFO
+ g_use_fifo => g_rx_use_fifo,
+ g_bsn_w => c_data_w,
+ g_empty_w => 1,
+ g_channel_w => c_link_channel_lo, -- c_link_channel_lo-1 DOWNTO 0
+ g_error_w => 1,
+ g_use_bsn => g_rx_use_fifo,
+ g_use_empty => false,
+ g_use_channel => c_rx_use_fifo_link_channel_lo,
+ g_use_error => false,
+ g_use_sync => g_rx_use_fifo,
+ g_fifo_fill => g_rx_fifo_fill,
+ g_fifo_size => c_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => serial_siso_arr,
+ snk_in_arr => serial_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd b/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
index 464fd24ca5..2cf406bac1 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
@@ -120,13 +120,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_example_dut is
generic (
@@ -198,39 +198,39 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_data_init => c_data_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => g_dat_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_data_init => c_data_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => g_dat_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -264,37 +264,37 @@ begin
verify_last_snk_in_evt.err <= last_snk_in_evt;
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => g_dat_w,
- g_pkt_len => g_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => g_dat_w,
+ g_pkt_len => g_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT
@@ -312,16 +312,16 @@ begin
-- DUT function
gen_dut : if g_no_dut = false generate
u_dut : entity work.dp_example_dut
- port map (
- rst => rst,
- clk => clk,
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out => dut_snk_out,
- snk_in => dut_snk_in,
+ snk_out => dut_snk_out,
+ snk_in => dut_snk_in,
- src_in => dut_src_in,
- src_out => dut_src_out
- );
+ src_in => dut_src_in,
+ src_out => dut_src_out
+ );
end generate;
-- Connect DUT source output stream to verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd b/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
index 7cf8b884b2..7ccd099b73 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
@@ -111,13 +111,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_example_no_dut is
generic (
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
index 2c5c009486..41660443ab 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_dc is
generic (
@@ -196,31 +196,31 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_fifo_dc
- generic map (
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_use_ctrl => g_dut_use_ctrl,
- g_fifo_size => c_dut_fifo_size,
- g_fifo_rl => g_dut_out_latency
- )
- port map (
- wr_rst => rst,
- wr_clk => wr_clk,
- rd_rst => rst,
- rd_clk => rd_clk,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- wr_usedw => usedw,
- rd_usedw => OPEN,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_use_ctrl => g_dut_use_ctrl,
+ g_fifo_size => c_dut_fifo_size,
+ g_fifo_rl => g_dut_out_latency
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => wr_clk,
+ rd_rst => rst,
+ rd_clk => rd_clk,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ wr_usedw => usedw,
+ rd_usedw => OPEN,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
index 5c75f0d420..6829d6a1c9 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
@@ -26,11 +26,11 @@
-- Verifies output data and ctrl signals of DUT. This is configurable using generics.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_dc_arr is
generic (
@@ -213,36 +213,36 @@ begin
out_eop <= out_sosi_arr(0).eop;
dut : entity work.dp_fifo_dc_arr
- generic map (
- g_nof_streams => g_dut_nof_streams,
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_aux_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_use_aux => g_dut_use_aux,
- g_use_ctrl => g_dut_use_ctrl,
- g_fifo_size => c_dut_fifo_size,
- g_fifo_rl => g_dut_out_latency
- )
- port map (
- wr_rst => rst,
- wr_clk => wr_clk,
- rd_rst => rst,
- rd_clk => rd_clk,
- snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
- snk_in_arr => in_sosi_arr,
- in_aux(0) => in_aux,
- wr_usedw => usedw,
- rd_usedw => OPEN,
- src_in_arr => out_siso_arr, -- IN = request from downstream ST sink
- src_out_arr => out_sosi_arr,
- out_aux(0) => out_aux
- );
+ generic map (
+ g_nof_streams => g_dut_nof_streams,
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_aux_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_use_aux => g_dut_use_aux,
+ g_use_ctrl => g_dut_use_ctrl,
+ g_fifo_size => c_dut_fifo_size,
+ g_fifo_rl => g_dut_out_latency
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => wr_clk,
+ rd_rst => rst,
+ rd_clk => rd_clk,
+ snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
+ snk_in_arr => in_sosi_arr,
+ in_aux(0) => in_aux,
+ wr_usedw => usedw,
+ rd_usedw => OPEN,
+ src_in_arr => out_siso_arr, -- IN = request from downstream ST sink
+ src_out_arr => out_sosi_arr,
+ out_aux(0) => out_aux
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
index 58dfd08b6b..91893ee2a1 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
--- run 50 us
+ -- run 50 us
entity tb_dp_fifo_dc_mixed_widths is
generic (
@@ -193,72 +193,72 @@ begin
-- Narrow to wide FIFO
u_dut_n2w : entity work.dp_fifo_dc_mixed_widths
- generic map (
- g_wr_data_w => g_narrow_w,
- g_rd_data_w => c_wide_w,
- g_use_ctrl => g_use_ctrl,
- g_wr_fifo_size => c_wr_fifo_size,
- g_rd_fifo_rl => g_read_rl
- )
- port map (
- wr_rst => narrow_rst,
- wr_clk => narrow_clk,
- rd_rst => wide_rst,
- rd_clk => wide_clk,
- -- ST sink
- snk_out => in_siso,
- snk_in => in_sosi,
- -- Monitor FIFO filling
- wr_usedw => fifo_n2w_wr_usedw,
- rd_usedw => fifo_n2w_rd_usedw,
- rd_emp => fifo_n2w_rd_emp,
- -- ST source
- src_in => wide_siso,
- src_out => wide_sosi
- );
+ generic map (
+ g_wr_data_w => g_narrow_w,
+ g_rd_data_w => c_wide_w,
+ g_use_ctrl => g_use_ctrl,
+ g_wr_fifo_size => c_wr_fifo_size,
+ g_rd_fifo_rl => g_read_rl
+ )
+ port map (
+ wr_rst => narrow_rst,
+ wr_clk => narrow_clk,
+ rd_rst => wide_rst,
+ rd_clk => wide_clk,
+ -- ST sink
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- Monitor FIFO filling
+ wr_usedw => fifo_n2w_wr_usedw,
+ rd_usedw => fifo_n2w_rd_usedw,
+ rd_emp => fifo_n2w_rd_emp,
+ -- ST source
+ src_in => wide_siso,
+ src_out => wide_sosi
+ );
-- Adapt for wide to narrow FIFO input RL=1 in case g_read_rl=0
u_rl : entity work.dp_latency_adapter
- generic map (
- g_in_latency => g_read_rl,
- g_out_latency => c_rl
- )
- port map (
- rst => wide_rst,
- clk => wide_clk,
- -- ST sink
- snk_out => wide_siso,
- snk_in => wide_sosi,
- -- ST source
- src_in => wide_siso_rl1,
- src_out => wide_sosi_rl1
- );
+ generic map (
+ g_in_latency => g_read_rl,
+ g_out_latency => c_rl
+ )
+ port map (
+ rst => wide_rst,
+ clk => wide_clk,
+ -- ST sink
+ snk_out => wide_siso,
+ snk_in => wide_sosi,
+ -- ST source
+ src_in => wide_siso_rl1,
+ src_out => wide_sosi_rl1
+ );
-- Wide to narrow FIFO
u_dut_w2n : entity work.dp_fifo_dc_mixed_widths
- generic map (
- g_wr_data_w => c_wide_w,
- g_rd_data_w => g_narrow_w,
- g_use_ctrl => g_use_ctrl,
- g_wr_fifo_size => c_wr_fifo_size,
- g_rd_fifo_rl => g_read_rl
- )
- port map (
- wr_rst => wide_rst,
- wr_clk => wide_clk,
- rd_rst => narrow_rst,
- rd_clk => narrow_clk,
- -- ST sink
- snk_out => wide_siso_rl1,
- snk_in => wide_sosi_rl1,
- -- Monitor FIFO filling
- wr_usedw => fifo_w2n_wr_usedw,
- rd_usedw => fifo_w2n_rd_usedw,
- rd_emp => fifo_w2n_rd_emp,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ g_wr_data_w => c_wide_w,
+ g_rd_data_w => g_narrow_w,
+ g_use_ctrl => g_use_ctrl,
+ g_wr_fifo_size => c_wr_fifo_size,
+ g_rd_fifo_rl => g_read_rl
+ )
+ port map (
+ wr_rst => wide_rst,
+ wr_clk => wide_clk,
+ rd_rst => narrow_rst,
+ rd_clk => narrow_clk,
+ -- ST sink
+ snk_out => wide_siso_rl1,
+ snk_in => wide_sosi_rl1,
+ -- Monitor FIFO filling
+ wr_usedw => fifo_w2n_wr_usedw,
+ rd_usedw => fifo_w2n_rd_usedw,
+ rd_emp => fifo_w2n_rd_emp,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
-- 1) Verify intermediate wide data
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
index d6ad771c2a..5c79fd0b15 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
@@ -35,11 +35,11 @@
-- . the tb is self checking
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_fill is
generic (
@@ -211,28 +211,28 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_fifo_fill
- generic map (
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_fifo_fill => g_dut_fifo_fill,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_rl => g_dut_fifo_rl
- )
- port map (
- rst => rst,
- clk => clk,
- wr_ful => wr_ful,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_fifo_fill => g_dut_fifo_fill,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_rl => g_dut_fifo_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_ful => wr_ful,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
index aeceefb25f..8fca288a0f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
@@ -37,12 +37,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_fill_eop is
generic (
@@ -187,7 +187,7 @@ begin
in_channel <= INCR_UVEC(in_data, c_channel_offset);
-- Stimuli control
- proc_dp_count_en(rst, clk, sync, lfsr1, state, verify_done, tb_done, cnt_en);
+ proc_dp_count_en(rst, clk, sync, lfsr1, state, verify_done, tb_done, cnt_en);
gen_random_ctrl : if g_dut_use_random_ctrl generate
proc_dp_out_ready(rst, clk, sync, lfsr2, out_ready);
@@ -267,33 +267,33 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_fifo_fill_eop
- generic map (
- g_use_dual_clock => g_dut_use_dual_clock,
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_fifo_fill => g_dut_fifo_fill,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_rl => g_dut_fifo_rl
- )
- port map (
- rd_rst => rst,
- rd_clk => clk,
- wr_rst => rst,
- wr_clk => clk,
- wr_ful => wr_ful,
- rd_usedw => rd_usedw,
- rd_fill_32b => rd_fill_32b,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_use_dual_clock => g_dut_use_dual_clock,
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_fifo_fill => g_dut_fifo_fill,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_rl => g_dut_fifo_rl
+ )
+ port map (
+ rd_rst => rst,
+ rd_clk => clk,
+ wr_rst => rst,
+ wr_clk => clk,
+ wr_ful => wr_ful,
+ rd_usedw => rd_usedw,
+ rd_fill_32b => rd_fill_32b,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
index bd1ccdaaa0..c39f7b639f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
@@ -35,12 +35,12 @@
-- . the tb is self checking
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_fill_sc is
generic (
@@ -241,30 +241,30 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_fifo_fill_sc
- generic map (
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_fifo_fill => g_dut_fifo_fill,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_rl => g_dut_fifo_rl
- )
- port map (
- rst => rst,
- clk => clk,
- wr_ful => wr_ful,
- usedw => rd_usedw,
- rd_fill_32b => rd_fill_32b,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_fifo_fill => g_dut_fifo_fill,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_rl => g_dut_fifo_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_ful => wr_ful,
+ usedw => rd_usedw,
+ rd_fill_32b => rd_fill_32b,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
index aea359818b..0d08c0422a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
@@ -32,13 +32,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_info is
generic (
@@ -188,51 +188,51 @@ begin
-- Stimuli data delay
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_data_delay
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => stimuli_src_in,
- snk_in => stimuli_src_out,
- -- ST source
- src_in => dp_pipeline_src_in,
- src_out => dp_pipeline_src_out
- );
+ generic map (
+ g_pipeline => g_data_delay
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => stimuli_src_in,
+ snk_in => stimuli_src_out,
+ -- ST source
+ src_in => dp_pipeline_src_in,
+ src_out => dp_pipeline_src_out
+ );
------------------------------------------------------------------------------
-- DUT dp_fifo_info
------------------------------------------------------------------------------
dut : entity work.dp_fifo_info
- generic map (
- g_use_sync => g_info_use_sync,
- g_use_bsn => g_info_use_bsn,
- g_use_channel => g_info_use_channel,
- g_use_empty => g_info_use_empty,
- g_use_error => g_info_use_error,
- g_bsn_w => c_dp_stream_bsn_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_fifo_size => g_info_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor info FIFO filling
- fifo_wr_ful => fifo_wr_ful,
- fifo_usedw => fifo_usedw,
- fifo_rd_emp => fifo_rd_emp,
- -- ST sink
- data_snk_out => dp_pipeline_src_in,
- data_snk_in => dp_pipeline_src_out, -- delayed snk_in data
- info_snk_in => stimuli_src_out, -- original snk_in info
- -- ST source
- src_in => verify_snk_out,
- src_out => verify_snk_in
- );
+ generic map (
+ g_use_sync => g_info_use_sync,
+ g_use_bsn => g_info_use_bsn,
+ g_use_channel => g_info_use_channel,
+ g_use_empty => g_info_use_empty,
+ g_use_error => g_info_use_error,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_error_w => c_dp_stream_error_w,
+ g_fifo_size => g_info_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor info FIFO filling
+ fifo_wr_ful => fifo_wr_ful,
+ fifo_usedw => fifo_usedw,
+ fifo_rd_emp => fifo_rd_emp,
+ -- ST sink
+ data_snk_out => dp_pipeline_src_in,
+ data_snk_in => dp_pipeline_src_out, -- delayed snk_in data
+ info_snk_in => stimuli_src_out, -- original snk_in info
+ -- ST source
+ src_in => verify_snk_out,
+ src_out => verify_snk_in
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
index 0597d8e0dc..75c5064394 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_sc is
generic (
@@ -194,30 +194,30 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_fifo_sc
- generic map (
- g_use_lut => g_dut_use_lut,
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_use_ctrl => g_dut_use_ctrl,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_af_margin => g_dut_fifo_af_margin,
- g_fifo_rl => g_dut_out_latency
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- usedw => usedw,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_use_lut => g_dut_use_lut,
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_use_ctrl => g_dut_use_ctrl,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_af_margin => g_dut_fifo_af_margin,
+ g_fifo_rl => g_dut_out_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ usedw => usedw,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
index 141127e58c..18bedb4753 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
@@ -21,33 +21,33 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
-
--- Purpose: This test bench verifies both dp_fifo_from_mm and dp_fifo_to_mm.
--- Usage:
--- > as 10
--- > run -all (run > c_run_time / 100 us and c_run_time >>> c_fifo_size)
---
--- Description:
--- The test bench structure is:
---
--- p_wr_stimuli -> dp_fifo_from_mm -> FIFO -> dp_fifo_to_mm -> p_rd_stimuli
---
--- The verify code at the end verifies that the data goes through correctly
--- and that sufficient data values have been applied.
---
--- Remark:
--- . The stimuli are applied via mm_wr and mm_rd, which are controlled in a
--- random manner.
--- . To ensure that all relevant conditions have been covered it is necessary
--- to run as long as necessary so that wr_availw_is_0='1' and
--- rd_usedw_is_0='1' have occurred.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
+
+ -- Purpose: This test bench verifies both dp_fifo_from_mm and dp_fifo_to_mm.
+ -- Usage:
+ -- > as 10
+ -- > run -all (run > c_run_time / 100 us and c_run_time >>> c_fifo_size)
+ --
+ -- Description:
+ -- The test bench structure is:
+ --
+ -- p_wr_stimuli -> dp_fifo_from_mm -> FIFO -> dp_fifo_to_mm -> p_rd_stimuli
+ --
+ -- The verify code at the end verifies that the data goes through correctly
+ -- and that sufficient data values have been applied.
+ --
+ -- Remark:
+ -- . The stimuli are applied via mm_wr and mm_rd, which are controlled in a
+ -- random manner.
+ -- . To ensure that all relevant conditions have been covered it is necessary
+ -- to run as long as necessary so that wr_availw_is_0='1' and
+ -- rd_usedw_is_0='1' have occurred.
entity tb_dp_fifo_to_mm is
end tb_dp_fifo_to_mm;
@@ -138,7 +138,7 @@ begin
else
state_wr <= s_random;
end if;
- state_wr <= s_one_go;
+ state_wr <= s_one_go;
when s_one_go =>
if unsigned(wr_availw) > 0 then
mm_wr <= '1';
@@ -176,7 +176,7 @@ begin
else
state_rd <= s_random;
end if;
- state_rd <= s_one_go;
+ state_rd <= s_one_go;
when s_one_go =>
if unsigned(rd_usedw) > 0 then
mm_rd <= '1';
@@ -197,66 +197,66 @@ begin
end process;
u_from_mm : entity work.dp_fifo_from_mm
- generic map (
- g_fifo_size => c_fifo_size,
- g_fifo_af_margin => c_fifo_af_margin,
- g_mm_word_w => c_mm_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST soure connected to FIFO input
- src_out => wr_sosi,
- usedw => fifo_usedw,
- -- Control for FIFO read access
- mm_wr => mm_wr,
- mm_wrdata => mm_wrdata,
- mm_usedw => OPEN,
- mm_availw => wr_availw
- );
+ generic map (
+ g_fifo_size => c_fifo_size,
+ g_fifo_af_margin => c_fifo_af_margin,
+ g_mm_word_w => c_mm_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST soure connected to FIFO input
+ src_out => wr_sosi,
+ usedw => fifo_usedw,
+ -- Control for FIFO read access
+ mm_wr => mm_wr,
+ mm_wrdata => mm_wrdata,
+ mm_usedw => OPEN,
+ mm_availw => wr_availw
+ );
u_fifo : entity work.dp_fifo_sc
- generic map (
- g_data_w => c_mm_data_w,
- g_use_ctrl => false,
- g_fifo_size => c_fifo_size,
- g_fifo_af_margin => c_fifo_af_margin,
- g_fifo_rl => c_rl
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => wr_sosi,
- -- Monitor FIFO filling
- wr_ful => fifo_full,
- usedw => fifo_usedw,
- rd_emp => OPEN,
- -- ST source
- src_in => rd_siso,
- src_out => rd_sosi
- );
+ generic map (
+ g_data_w => c_mm_data_w,
+ g_use_ctrl => false,
+ g_fifo_size => c_fifo_size,
+ g_fifo_af_margin => c_fifo_af_margin,
+ g_fifo_rl => c_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => wr_sosi,
+ -- Monitor FIFO filling
+ wr_ful => fifo_full,
+ usedw => fifo_usedw,
+ rd_emp => OPEN,
+ -- ST source
+ src_in => rd_siso,
+ src_out => rd_sosi
+ );
rd_siso.ready <= mm_rd;
u_to_mm : entity work.dp_fifo_to_mm
- generic map (
- g_fifo_size => c_fifo_size,
- g_mm_word_w => c_mm_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink connected to FIFO output
- snk_out => rd_siso,
- snk_in => rd_sosi,
- usedw => fifo_usedw,
- -- Control for FIFO read access
- mm_rd => mm_rd,
- mm_rddata => mm_rddata,
- mm_usedw => rd_usedw
- );
+ generic map (
+ g_fifo_size => c_fifo_size,
+ g_mm_word_w => c_mm_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink connected to FIFO output
+ snk_out => rd_siso,
+ snk_in => rd_sosi,
+ usedw => fifo_usedw,
+ -- Control for FIFO read access
+ mm_rd => mm_rd,
+ mm_rddata => mm_rddata,
+ mm_usedw => rd_usedw
+ );
p_verify : process(clk)
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd
index 2c7c60352a..dc7b0bc4cc 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd
@@ -75,14 +75,14 @@
-- Self test result is OK when there is no FAILURE due to FIFO overflow.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_xonoff is
generic (
@@ -166,16 +166,16 @@ begin
begin
while true loop
proc_dp_gen_frame(c_ready_latency,
- c_data_w,
- c_symbol_w,
- c_symbol_init,
- c_nof_symbols,
- c_bsn + I, -- use bsn to identify the inputs
- c_sync,
- clk,
- in_en,
- bg_siso,
- bg_sosi_arr(I));
+ c_data_w,
+ c_symbol_w,
+ c_symbol_init,
+ c_nof_symbols,
+ c_bsn + I, -- use bsn to identify the inputs
+ c_sync,
+ clk,
+ in_en,
+ bg_siso,
+ bg_sosi_arr(I));
wait for g_gap_size * c_clk_period;
end loop;
-- Use WHILE LOOP and WAIT to avoid warning (vcom-1090) Possible infinite loop:
@@ -185,17 +185,17 @@ begin
gen_dp_xonoff : if g_use_in_xonoff generate
u_dp_xonoff : entity work.dp_xonoff
- port map (
- rst => rst,
- clk => clk,
- -- Frame in
- in_siso => OPEN,
- in_sosi => bg_sosi_arr(I),
- -- Frame out
- out_siso => fifo_in_siso_arr(I),
- out_sosi => fifo_in_sosi_arr(I),
- out_en => dp_out_en_arr(I)
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Frame in
+ in_siso => OPEN,
+ in_sosi => bg_sosi_arr(I),
+ -- Frame out
+ out_siso => fifo_in_siso_arr(I),
+ out_sosi => fifo_in_sosi_arr(I),
+ out_en => dp_out_en_arr(I)
+ );
end generate;
no_dp_xonoff : if not g_use_in_xonoff generate
@@ -204,35 +204,35 @@ begin
end generate;
u_in_fifo : entity work.dp_fifo_sc
- generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_nof_input_w,
- g_use_bsn => true, -- use bsn to identify the inputs
- g_use_ctrl => true, -- sop & eop
- g_fifo_size => c_in_fifo_size,
- g_fifo_af_margin => c_fifo_af_ready,
- g_fifo_af_xon => c_fifo_af_xon,
- g_fifo_rl => c_ready_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor FIFO filling
- wr_ful => in_fifo_wr_ful_arr(I),
- usedw => in_fifo_usedw_arr(I),
- rd_emp => in_fifo_rd_emp_arr(I),
- -- ST sink
- snk_out => fifo_in_siso_arr(I), -- flush control via out_siso.xon
- snk_in => fifo_in_sosi_arr(I),
- -- ST source
- src_in => mux_in_siso_arr(I),
- src_out => mux_in_sosi_arr(I)
- );
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_nof_input_w,
+ g_use_bsn => true, -- use bsn to identify the inputs
+ g_use_ctrl => true, -- sop & eop
+ g_fifo_size => c_in_fifo_size,
+ g_fifo_af_margin => c_fifo_af_ready,
+ g_fifo_af_xon => c_fifo_af_xon,
+ g_fifo_rl => c_ready_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => in_fifo_wr_ful_arr(I),
+ usedw => in_fifo_usedw_arr(I),
+ rd_emp => in_fifo_rd_emp_arr(I),
+ -- ST sink
+ snk_out => fifo_in_siso_arr(I), -- flush control via out_siso.xon
+ snk_in => fifo_in_sosi_arr(I),
+ -- ST source
+ src_in => mux_in_siso_arr(I),
+ src_out => mux_in_sosi_arr(I)
+ );
end generate;
-- Enable input after reset and disable it before tb_end, to read FIFOs empty
in_en <= '0', '1' after c_clk_period * 17,
- '0' after 4 * c_tb_nof_clk_cycles * c_clk_period;
+ '0' after 4 * c_tb_nof_clk_cycles * c_clk_period;
-- Also verify toggling external siso.xon flow control
out_siso.xon <= '1',
@@ -246,21 +246,21 @@ begin
-- Multiplexer
------------------------------------------------------------------------------
u_dp_mux : entity work.dp_mux
- generic map (
- g_nof_input => g_nof_inputs,
- g_fifo_size => array_init(1024, g_nof_inputs), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, g_nof_inputs) -- must match g_nof_input, even when g_use_fifo=FALSE
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => mux_in_siso_arr,
- snk_in_arr => mux_in_sosi_arr,
- -- ST source
- src_in => mux_out_siso,
- src_out => mux_out_sosi
- );
+ generic map (
+ g_nof_input => g_nof_inputs,
+ g_fifo_size => array_init(1024, g_nof_inputs), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, g_nof_inputs) -- must match g_nof_input, even when g_use_fifo=FALSE
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => mux_in_siso_arr,
+ snk_in_arr => mux_in_sosi_arr,
+ -- ST source
+ src_in => mux_out_siso,
+ src_out => mux_out_sosi
+ );
------------------------------------------------------------------------------
-- Output
@@ -268,17 +268,17 @@ begin
gen_dp_xonoff : if g_use_out_xonoff generate
u_dp_xonoff : entity work.dp_xonoff
- port map (
- rst => rst,
- clk => clk,
- -- Frame in
- in_siso => mux_out_siso,
- in_sosi => mux_out_sosi,
- -- Frame out
- out_siso => fifo_fill_in_siso,
- out_sosi => fifo_fill_in_sosi,
- out_en => dp_out_en
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Frame in
+ in_siso => mux_out_siso,
+ in_sosi => mux_out_sosi,
+ -- Frame out
+ out_siso => fifo_fill_in_siso,
+ out_sosi => fifo_fill_in_sosi,
+ out_en => dp_out_en
+ );
end generate;
no_dp_xonoff : if not g_use_out_xonoff generate
@@ -288,29 +288,29 @@ begin
end generate;
u_out_fifo : entity work.dp_fifo_fill_sc
- --u_out_fifo : ENTITY work.dp_fifo_fill_eop_sc
- generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_nof_input_w,
- g_use_bsn => true, -- use bsn to identify the inputs
- g_fifo_fill => c_out_fifo_fill,
- g_fifo_size => c_out_fifo_size,
- g_fifo_af_margin => c_fifo_af_ready,
- g_fifo_af_xon => c_fifo_af_xon,
- g_fifo_rl => c_ready_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor FIFO filling
- wr_ful => out_fifo_wr_ful,
- usedw => out_fifo_usedw,
- rd_emp => out_fifo_rd_emp,
- -- ST sink
- snk_out => fifo_fill_in_siso,
- snk_in => fifo_fill_in_sosi,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ --u_out_fifo : ENTITY work.dp_fifo_fill_eop_sc
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_nof_input_w,
+ g_use_bsn => true, -- use bsn to identify the inputs
+ g_fifo_fill => c_out_fifo_fill,
+ g_fifo_size => c_out_fifo_size,
+ g_fifo_af_margin => c_fifo_af_ready,
+ g_fifo_af_xon => c_fifo_af_xon,
+ g_fifo_rl => c_ready_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => out_fifo_wr_ful,
+ usedw => out_fifo_usedw,
+ rd_emp => out_fifo_rd_emp,
+ -- ST sink
+ snk_out => fifo_fill_in_siso,
+ snk_in => fifo_fill_in_sosi,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd b/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
index bb5e1dce66..609c35dddd 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
@@ -29,13 +29,13 @@
-- . Observe m.flush_en and m.snk_in and m.src_out signals in Wave Window
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_flush is
generic (
@@ -256,23 +256,23 @@ begin
------------------------------------------------------------------------------
u_dut: entity work.dp_flush
- generic map (
- g_ready_latency => g_rl,
- g_framed_xon => g_framed_xon,
- g_framed_xoff => g_framed_xoff
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => in_sosi,
- snk_out => in_siso,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi,
- -- Enable flush
- flush_en => flush_en
- );
+ generic map (
+ g_ready_latency => g_rl,
+ g_framed_xon => g_framed_xon,
+ g_framed_xoff => g_framed_xoff
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => in_sosi,
+ snk_out => in_siso,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi,
+ -- Enable flush
+ flush_en => flush_en
+ );
-- Map record field to signals for easier monitoring in wave window
m.snk_out_ready <= in_siso.ready;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd b/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
index 1a752aaa71..02221ea6c9 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
@@ -26,13 +26,13 @@
-- . Verify stream through dp_unfolder->dp_folder stages
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_folder is
end tb_dp_folder;
@@ -94,30 +94,30 @@ begin
dp_unfolder_snk_in_arr(0) <= proc_dp_gen_block_data_src_out;
u_dp_unfolder : entity work.dp_unfolder
- generic map (
- g_nof_inputs => c_nof_inputs,
- g_nof_unfolds => c_nof_unfolds,
- g_output_align => false -- We're going to fold these outputs again, so don't align them!
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in_arr => dp_unfolder_snk_in_arr,
- src_out_arr => dp_folder_snk_in_arr
- );
+ generic map (
+ g_nof_inputs => c_nof_inputs,
+ g_nof_unfolds => c_nof_unfolds,
+ g_output_align => false -- We're going to fold these outputs again, so don't align them!
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in_arr => dp_unfolder_snk_in_arr,
+ src_out_arr => dp_folder_snk_in_arr
+ );
u_dp_folder : entity work.dp_folder
- generic map (
- g_nof_inputs => c_nof_unfolded_streams,
- g_nof_folds => -1 -- Fold until 1 output remains,
--- g_output_block_size => c_packet_len
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in_arr => dp_folder_snk_in_arr,
- src_out_arr => dp_folder_src_out_arr
- );
+ generic map (
+ g_nof_inputs => c_nof_unfolded_streams,
+ g_nof_folds => -1 -- Fold until 1 output remains,
+ -- g_output_block_size => c_packet_len
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in_arr => dp_folder_snk_in_arr,
+ src_out_arr => dp_folder_src_out_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd b/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
index 8b0d02b22b..1b4f41b0a6 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_frame_rd is
end tb_dp_frame_rd;
@@ -53,7 +53,7 @@ architecture tb of tb_dp_frame_rd is
--CONSTANT c_throttle_eof : BOOLEAN := TRUE; -- when false immediately continue request next frame after eof
constant c_throttle_eof : boolean := false;
constant c_frame_request : std_logic := '1'; -- when '1' then always request, else only in state s_request when not frm_ack
- -- use '1' to verify c_throttle_eof=FALSE
+ -- use '1' to verify c_throttle_eof=FALSE
type t_state_enum is (s_request, s_eof, s_err);
@@ -97,46 +97,47 @@ architecture tb of tb_dp_frame_rd is
signal exp_data : std_logic_vector(c_data_w - 1 downto 0) := TO_UVEC(100, c_data_w);
- procedure proc_frame(constant in_sof : in std_logic;
- constant in_data : in std_logic_vector(c_data_w - 1 downto 0);
- constant empty_length : in natural;
- signal clk : in std_logic;
- signal frm_data : out std_logic_vector(c_data_w - 1 downto 0);
- signal frm_val : out std_logic;
- signal frm_sof : out std_logic;
- signal frm_eof : out std_logic) is
+ procedure proc_frame(
+ constant in_sof : in std_logic;
+ constant in_data : in std_logic_vector(c_data_w - 1 downto 0);
+ constant empty_length : in natural;
+ signal clk : in std_logic;
+ signal frm_data : out std_logic_vector(c_data_w - 1 downto 0);
+ signal frm_val : out std_logic;
+ signal frm_sof : out std_logic;
+ signal frm_eof : out std_logic) is
variable v_frm_data : std_logic_vector(frm_data'range);
- begin
- frm_val <= '1';
- -- sof
- frm_sof <= in_sof;
- v_frm_data := INCR_UVEC(in_data, 1);
+begin
+ frm_val <= '1';
+ -- sof
+ frm_sof <= in_sof;
+ v_frm_data := INCR_UVEC(in_data, 1);
+ frm_data <= v_frm_data;
+ wait until rising_edge(clk);
+ frm_sof <= '0';
+ for I in 2 to c_frame_length / 2 - 1 loop
+ v_frm_data := INCR_UVEC(v_frm_data, 1);
frm_data <= v_frm_data;
wait until rising_edge(clk);
- frm_sof <= '0';
- for I in 2 to c_frame_length / 2 - 1 loop
- v_frm_data := INCR_UVEC(v_frm_data, 1);
- frm_data <= v_frm_data;
- wait until rising_edge(clk);
- end loop;
- frm_val <= '0';
- for I in 1 to empty_length loop wait until rising_edge(clk); end loop;
- frm_val <= '1';
- for I in c_frame_length / 2 to c_frame_length - 1 loop
- v_frm_data := INCR_UVEC(v_frm_data, 1);
- frm_data <= v_frm_data;
- wait until rising_edge(clk);
- end loop;
- -- eof
- frm_eof <= '1';
+ end loop;
+ frm_val <= '0';
+ for I in 1 to empty_length loop wait until rising_edge(clk); end loop;
+ frm_val <= '1';
+ for I in c_frame_length / 2 to c_frame_length - 1 loop
v_frm_data := INCR_UVEC(v_frm_data, 1);
frm_data <= v_frm_data;
wait until rising_edge(clk);
- frm_val <= '0';
- frm_sof <= '0';
- frm_eof <= '0';
- -- gap
- for I in 1 to c_gap_length loop wait until rising_edge(clk); end loop;
+ end loop;
+ -- eof
+ frm_eof <= '1';
+ v_frm_data := INCR_UVEC(v_frm_data, 1);
+ frm_data <= v_frm_data;
+ wait until rising_edge(clk);
+ frm_val <= '0';
+ frm_sof <= '0';
+ frm_eof <= '0';
+ -- gap
+ for I in 1 to c_gap_length loop wait until rising_edge(clk); end loop;
end proc_frame;
begin
clk <= not clk after clk_period / 2;
@@ -199,59 +200,59 @@ begin
fifo_rd_eof <= rd_sosi.eop;
u_fifo : entity work.dp_fifo_sc
- generic map (
- g_data_w => c_data_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_ctrl => true,
- g_fifo_size => c_fifo_nof_words,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => OPEN, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- usedw => fifo_usedw,
- src_in => rd_siso, -- IN = request from downstream ST sink
- src_out => rd_sosi
- );
+ generic map (
+ g_data_w => c_data_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_ctrl => true,
+ g_fifo_size => c_fifo_nof_words,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => OPEN, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ usedw => fifo_usedw,
+ src_in => rd_siso, -- IN = request from downstream ST sink
+ src_out => rd_sosi
+ );
u_dut : entity work.dp_frame_rd
- generic map (
- g_dat_w => c_data_w,
- g_frm_cnt_max => 1,
- g_throttle_num => c_throttle_num,
- g_throttle_den => c_throttle_den,
- g_throttle_sof => c_throttle_sof,
- g_throttle_eof => c_throttle_eof
- )
- port map (
- rst => rst,
- clk => clk,
-
- frm_req => frm_req,
- frm_flush => frm_flush,
- frm_ack => frm_ack,
- frm_busy => frm_busy,
- frm_err => frm_err,
- frm_done => frm_done,
-
- rd_req => fifo_rd_req,
- rd_dat => fifo_rd_data,
- rd_val => fifo_rd_val,
- rd_sof => fifo_rd_sof,
- rd_eof => fifo_rd_eof,
-
- out_dat => out_data,
- out_val => out_val,
- out_sof => out_sof,
- out_eof => out_eof
- );
+ generic map (
+ g_dat_w => c_data_w,
+ g_frm_cnt_max => 1,
+ g_throttle_num => c_throttle_num,
+ g_throttle_den => c_throttle_den,
+ g_throttle_sof => c_throttle_sof,
+ g_throttle_eof => c_throttle_eof
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ frm_req => frm_req,
+ frm_flush => frm_flush,
+ frm_ack => frm_ack,
+ frm_busy => frm_busy,
+ frm_err => frm_err,
+ frm_done => frm_done,
+
+ rd_req => fifo_rd_req,
+ rd_dat => fifo_rd_data,
+ rd_val => fifo_rd_val,
+ rd_sof => fifo_rd_sof,
+ rd_eof => fifo_rd_eof,
+
+ out_dat => out_data,
+ out_val => out_val,
+ out_sof => out_sof,
+ out_eof => out_eof
+ );
p_output_stimuli : process
begin
@@ -294,7 +295,7 @@ begin
if out_val = '1' then
prev_out_data <= out_data;
if verify_en = '1' and unsigned(out_data) /= unsigned(prev_out_data) + 1 then
- report "Wrong out_data count" severity ERROR;
+ report "Wrong out_data count" severity ERROR;
end if;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
index 3030dbaa28..a5a9751269 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_packetizing_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_packetizing_pkg.all;
entity tb_dp_frame_scheduler is
generic (
@@ -136,15 +136,16 @@ architecture tb of tb_dp_frame_scheduler is
signal expected_fsn_x : natural;
signal expected_fsn_b : natural;
- procedure proc_tx_packet(constant c_packet_size : in natural;
- constant c_sfd : in std_logic_vector;
- constant c_fsn_word : in natural;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal out_sof : out std_logic;
- signal out_eof : out std_logic;
- signal out_val : out std_logic;
- signal out_dat : inout std_logic_vector(c_lane_dat_w - 1 downto 0)) is
+ procedure proc_tx_packet(
+ constant c_packet_size : in natural;
+ constant c_sfd : in std_logic_vector;
+ constant c_fsn_word : in natural;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal out_sof : out std_logic;
+ signal out_eof : out std_logic;
+ signal out_val : out std_logic;
+ signal out_dat : inout std_logic_vector(c_lane_dat_w - 1 downto 0)) is
begin
out_sof <= '0';
out_eof <= '0';
@@ -177,9 +178,10 @@ architecture tb of tb_dp_frame_scheduler is
end if;
end proc_tx_packet;
- procedure proc_idle(constant c_idle_size : in natural;
- signal rst : in std_logic;
- signal clk : in std_logic) is
+ procedure proc_idle(
+ constant c_idle_size : in natural;
+ signal rst : in std_logic;
+ signal clk : in std_logic) is
begin
if rst = '1' then
wait until rising_edge(clk);
@@ -190,9 +192,10 @@ architecture tb of tb_dp_frame_scheduler is
end if;
end proc_idle;
- procedure proc_cnt(constant c_max : in natural;
- signal rst : in std_logic;
- signal cnt : inout natural) is
+ procedure proc_cnt(
+ constant c_max : in natural;
+ signal rst : in std_logic;
+ signal cnt : inout natural) is
begin
if rst = '0' then
cnt <= cnt + 1; -- increment packet counter
@@ -244,36 +247,36 @@ begin
begin
-- Send a crosslet packets
proc_tx_packet(c_packet_size_x,
- c_sfd_x,
- fsn_x,
- rst,
- clk,
- lane_tx_xsof,
- lane_tx_xeof,
- lane_tx_xval,
- lane_tx_xdat);
+ c_sfd_x,
+ fsn_x,
+ rst,
+ clk,
+ lane_tx_xsof,
+ lane_tx_xeof,
+ lane_tx_xval,
+ lane_tx_xdat);
proc_cnt(c_fsn_max, rst, fsn_x);
proc_idle(c_idle_size_x - 1, -- min 1 to tx one cycle earlier in every slice
- rst,
- clk);
+ rst,
+ clk);
end process;
p_tx_beamlets : process
begin
-- Send a beamlet packet at start of every slice
proc_tx_packet(c_packet_size_b,
- c_sfd_b,
- fsn_b,
- rst,
- clk,
- lane_tx_bsof,
- lane_tx_beof,
- lane_tx_bval,
- lane_tx_bdat);
+ c_sfd_b,
+ fsn_b,
+ rst,
+ clk,
+ lane_tx_bsof,
+ lane_tx_beof,
+ lane_tx_bval,
+ lane_tx_bdat);
proc_cnt(c_fsn_max, rst, fsn_b);
proc_idle(c_idle_size_b, -- tx at start of every slice
- rst,
- clk);
+ rst,
+ clk);
end process;
------------------------------------------------------------------------------
@@ -287,25 +290,25 @@ begin
gen_scheduler : if g_dut_verify_mux = false generate
dut : entity work.dp_frame_scheduler
- generic map (
- g_dat_w => c_lane_dat_w,
- g_nof_input => c_nof_input,
- g_fifo_rl => c_dut_fifo_rl,
- g_fifo_size => (c_x_scheduler_size, c_b_scheduler_size), -- 1 DOWNTO 0
- g_fifo_fill => (c_x_scheduler_fill, c_b_scheduler_fill) -- 1 DOWNTO 0
- )
- port map (
- rst => rst_dut,
- clk => clk,
- in_dat => scheduler_dat,
- in_val => scheduler_val,
- in_sof => scheduler_sof,
- in_eof => scheduler_eof,
- out_dat => lane_tx_dat,
- out_val => lane_tx_val,
- out_sof => lane_tx_sof,
- out_eof => lane_tx_eof
- );
+ generic map (
+ g_dat_w => c_lane_dat_w,
+ g_nof_input => c_nof_input,
+ g_fifo_rl => c_dut_fifo_rl,
+ g_fifo_size => (c_x_scheduler_size, c_b_scheduler_size), -- 1 DOWNTO 0
+ g_fifo_fill => (c_x_scheduler_fill, c_b_scheduler_fill) -- 1 DOWNTO 0
+ )
+ port map (
+ rst => rst_dut,
+ clk => clk,
+ in_dat => scheduler_dat,
+ in_val => scheduler_val,
+ in_sof => scheduler_sof,
+ in_eof => scheduler_eof,
+ out_dat => lane_tx_dat,
+ out_val => lane_tx_val,
+ out_sof => lane_tx_sof,
+ out_eof => lane_tx_eof
+ );
end generate;
gen_mux : if g_dut_verify_mux = true generate
@@ -326,29 +329,29 @@ begin
lane_tx_channel <= lane_tx_sosi.channel(c_nof_input_w - 1 downto 0);
dut : entity work.dp_mux
- generic map (
- g_data_w => c_lane_dat_w,
- g_empty_w => 1, -- not used
- g_in_channel_w => 1, -- not used
- g_error_w => 1, -- not used
- g_use_empty => false,
- g_use_in_channel => false,
- g_use_error => false,
- g_nof_input => c_nof_input,
- g_use_fifo => true,
- g_fifo_size => (c_b_scheduler_size, c_x_scheduler_size), -- 0 TO 1
- g_fifo_fill => (c_b_scheduler_fill, c_x_scheduler_fill) -- 0 TO 1
- )
- port map (
- rst => rst_dut,
- clk => clk,
- -- ST sinks
- snk_out_arr => OPEN, -- OUT = request to upstream ST source
- snk_in_arr => scheduler_sosi,
- -- ST source
- src_in => c_dp_siso_rdy, -- IN = request from downstream ST sink
- src_out => lane_tx_sosi
- );
+ generic map (
+ g_data_w => c_lane_dat_w,
+ g_empty_w => 1, -- not used
+ g_in_channel_w => 1, -- not used
+ g_error_w => 1, -- not used
+ g_use_empty => false,
+ g_use_in_channel => false,
+ g_use_error => false,
+ g_nof_input => c_nof_input,
+ g_use_fifo => true,
+ g_fifo_size => (c_b_scheduler_size, c_x_scheduler_size), -- 0 TO 1
+ g_fifo_fill => (c_b_scheduler_fill, c_x_scheduler_fill) -- 0 TO 1
+ )
+ port map (
+ rst => rst_dut,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => OPEN, -- OUT = request to upstream ST source
+ snk_in_arr => scheduler_sosi,
+ -- ST source
+ src_in => c_dp_siso_rdy, -- IN = request from downstream ST sink
+ src_out => lane_tx_sosi
+ );
end generate;
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd b/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd
index 45705b5ea1..3ad5968fef 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_gap is
end tb_dp_gap;
@@ -118,7 +118,7 @@ begin
wait;
end process;
- -- Generate tx_sosi for DUT using counter data generator
+ -- Generate tx_sosi for DUT using counter data generator
proc_dp_gen_data(c_rl, c_dat_w, c_tx_init, rst, clk, tx_enable, tx_siso, tx_sosi);
-- Enable verification when valid output data is expected, i.e. when prev_data should be /= 'X'
@@ -133,19 +133,19 @@ begin
proc_dp_verify_data("gap_sosi.data", c_rl, clk, verify_en, gap_siso.ready, gap_sosi.valid, gap_sosi.data(c_dat_w - 1 downto 0), prev_data2);
dut : entity work.dp_gap
- generic map (
- g_dat_len => 100,
- g_gap_len => 5,
- g_gap_extend => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => tx_siso,
- snk_in => tx_sosi,
-
- src_in => gap_siso,
- src_out => gap_sosi
- );
+ generic map (
+ g_dat_len => 100,
+ g_gap_len => 5,
+ g_gap_extend => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => tx_siso,
+ snk_in => tx_sosi,
+
+ src_in => gap_siso,
+ src_out => gap_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd b/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
index 901fe867b8..34506a6cf5 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
@@ -21,16 +21,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
-use common_lib.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
+ use common_lib.common_str_pkg.all;
entity tb_dp_hdr_insert_remove is
generic (
@@ -85,9 +85,9 @@ architecture tb of tb_dp_hdr_insert_remove is
signal prev_out_bsn : std_logic_vector(c_bsn_w - 1 downto 0) := (others => '1'); -- = -1
signal prev_out_channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0) := TO_SVEC(c_channel_init - 1, c_dp_stream_channel_w);
signal prev_out_err : std_logic_vector(c_dp_stream_error_w - 1 downto 0) := TO_SVEC(c_err_init - 1, c_dp_stream_error_w);
--- SIGNAL expected_out_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
--- SIGNAL expected_out_channel : STD_LOGIC_VECTOR(c_dp_stream_channel_w-1 DOWNTO 0);
--- SIGNAL expected_out_err : STD_LOGIC_VECTOR(c_dp_stream_error_w-1 DOWNTO 0);
+ -- SIGNAL expected_out_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
+ -- SIGNAL expected_out_channel : STD_LOGIC_VECTOR(c_dp_stream_channel_w-1 DOWNTO 0);
+ -- SIGNAL expected_out_err : STD_LOGIC_VECTOR(c_dp_stream_error_w-1 DOWNTO 0);
-- tb dut
signal in_siso : t_dp_siso;
@@ -209,9 +209,9 @@ begin
end loop;
-- End of stimuli
--- expected_out_bsn <= INCR_UVEC(v_bsn, -1);
--- expected_out_channel <= TO_UVEC(v_channel-1, c_dp_stream_channel_w);
--- expected_out_err <= TO_UVEC(v_err-1, c_dp_stream_error_w);
+ -- expected_out_bsn <= INCR_UVEC(v_bsn, -1);
+ -- expected_out_channel <= TO_UVEC(v_channel-1, c_dp_stream_channel_w);
+ -- expected_out_err <= TO_UVEC(v_err-1, c_dp_stream_error_w);
proc_common_wait_some_cycles(st_clk, 50); -- depends on stream control
verify_done <= '1';
@@ -249,50 +249,50 @@ begin
-- DUT
------------------------------------------------------------------------------
u_hdr_insert : entity work.dp_hdr_insert
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_hdr_nof_words => c_hdr_nof_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- ram_mosi => ram_hdr_mosi,
- reg_mosi => reg_hdr_mosi,
-
- snk_out => in_siso,
- snk_in => in_sosi,
-
- src_in => hdr_siso,
- src_out => hdr_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_hdr_nof_words => c_hdr_nof_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ ram_mosi => ram_hdr_mosi,
+ reg_mosi => reg_hdr_mosi,
+
+ snk_out => in_siso,
+ snk_in => in_sosi,
+
+ src_in => hdr_siso,
+ src_out => hdr_sosi
+ );
u_hdr_remove : entity work.dp_hdr_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_hdr_nof_words => c_hdr_nof_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- snk_out => hdr_siso,
- snk_in => hdr_sosi,
-
- sla_in => ram_hdr_mosi,
- sla_out => hdr_data_miso,
-
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_hdr_nof_words => c_hdr_nof_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ snk_out => hdr_siso,
+ snk_in => hdr_sosi,
+
+ sla_in => ram_hdr_mosi,
+ sla_out => hdr_data_miso,
+
+ src_in => out_siso,
+ src_out => out_sosi
+ );
-- Map to slv to ease monitoring in wave window
in_data <= in_sosi.data(g_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
index cb7c1b30ae..23c7b71027 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_latency_adapter is
end tb_dp_latency_adapter;
@@ -211,20 +211,20 @@ begin
gen_chain : for I in 0 to c_nof_dut - 1 generate
dut : entity work.dp_latency_adapter
- generic map (
- g_in_latency => c_dut_latency(I - 1),
- g_out_latency => c_dut_latency(I)
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => dut_siso(I - 1),
- snk_in => dut_sosi(I - 1),
- -- ST source
- src_in => dut_siso(I),
- src_out => dut_sosi(I)
- );
+ generic map (
+ g_in_latency => c_dut_latency(I - 1),
+ g_out_latency => c_dut_latency(I)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => dut_siso(I - 1),
+ snk_in => dut_sosi(I - 1),
+ -- ST source
+ src_in => dut_siso(I),
+ src_out => dut_sosi(I)
+ );
end generate;
-- map record to sl, slv
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd b/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
index a0a272ebb6..c4ac6b0bca 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
-
--- Purpose: Verify dp_latency_fifo
--- Description:
--- p_stimuli --> dp_latency_fifo --> verify
--- Usage:
--- > as 10
--- > run -all -- signal tb_end will stop the simulation by stopping the clk
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
+
+ -- Purpose: Verify dp_latency_fifo
+ -- Description:
+ -- p_stimuli --> dp_latency_fifo --> verify
+ -- Usage:
+ -- > as 10
+ -- > run -all -- signal tb_end will stop the simulation by stopping the clk
entity tb_dp_latency_fifo is
generic (
@@ -193,26 +193,26 @@ begin
------------------------------------------------------------------------------
dut : entity work.dp_latency_fifo
- generic map (
- g_bypass => g_bypass,
- g_input_rl => g_input_rl, -- input ready latency
- g_output_rl => g_output_rl, -- output ready latency
- g_fifo_size => g_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor FIFO filling
- usedw => fifo_usedw,
- wr_ful => fifo_ful,
- rd_emp => fifo_emp,
- -- ST sink
- snk_in => in_sosi,
- snk_out => in_siso,
- -- ST source
- src_out => out_sosi,
- src_in => out_siso
- );
+ generic map (
+ g_bypass => g_bypass,
+ g_input_rl => g_input_rl, -- input ready latency
+ g_output_rl => g_output_rl, -- output ready latency
+ g_fifo_size => g_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ usedw => fifo_usedw,
+ wr_ful => fifo_ful,
+ rd_emp => fifo_emp,
+ -- ST sink
+ snk_in => in_sosi,
+ snk_out => in_siso,
+ -- ST source
+ src_out => out_sosi,
+ src_in => out_siso
+ );
-- Map to slv to ease monitoring in wave window
in_data <= in_sosi.data(c_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
index bc34fa7cc5..3509d88df1 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_mux is
generic (
@@ -258,31 +258,31 @@ begin
end process;
dut : entity work.dp_mux
- generic map (
- g_data_w => c_dp_data_w,
- g_empty_w => c_dp_empty_w,
- g_in_channel_w => c_dut_in_channel_w,
- g_error_w => 1,
- g_use_empty => g_dut_use_empty,
- g_use_in_channel => g_dut_use_in_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_mode => g_mode,
- g_nof_input => g_dut_nof_input,
- g_use_fifo => g_dut_use_fifo,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_fill => g_dut_fifo_fill
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- sel_ctrl => sel_ctrl,
- -- ST sinks
- snk_out_arr => in_siso, -- OUT = request to upstream ST source
- snk_in_arr => in_sosi,
- -- ST source
- src_in => mux_siso, -- IN = request from downstream ST sink
- src_out => mux_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_empty_w => c_dp_empty_w,
+ g_in_channel_w => c_dut_in_channel_w,
+ g_error_w => 1,
+ g_use_empty => g_dut_use_empty,
+ g_use_in_channel => g_dut_use_in_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_mode => g_mode,
+ g_nof_input => g_dut_nof_input,
+ g_use_fifo => g_dut_use_fifo,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_fill => g_dut_fifo_fill
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ sel_ctrl => sel_ctrl,
+ -- ST sinks
+ snk_out_arr => in_siso, -- OUT = request to upstream ST source
+ snk_in_arr => in_sosi,
+ -- ST source
+ src_in => mux_siso, -- IN = request from downstream ST sink
+ src_out => mux_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
index 4cca345bbd..336a5d1bbe 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
@@ -36,16 +36,16 @@
-- . signal tb_end will stop the simulation by stopping the clk
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_offload_rx_filter is
end tb_dp_offload_rx_filter;
@@ -67,35 +67,36 @@ architecture tb of tb_dp_offload_rx_filter is
constant c_nof_packets : natural := 5;
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 9 + 1;
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
- ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
- ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
- ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
- ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
- ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
- ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
- ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
- ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ),
- ( field_name_pad("usr_hdr_word_align" ), " ", 16, field_default(0) ) );
+ constant c_hdr_field_arr : t_common_field_arr(
+ c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
+ ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ),
+ ( field_name_pad("usr_hdr_word_align" ), " ", 16, field_default(0) ) );
----------------------------------------------------------------------------
-- Clocks and resets
@@ -167,45 +168,45 @@ begin
p_special_stimuli : process(in_sosi.sop)
begin
- if in_sosi.sop = '1' then
- counter <= counter + 1;
- if toggle then
- hdr_fields_out_arr <= hdr_fields_in_arr;
- else
- hdr_fields_out_arr <= hdr_fields_wrong_arr;
- end if;
- toggle <= not toggle;
+ if in_sosi.sop = '1' then
+ counter <= counter + 1;
+ if toggle then
+ hdr_fields_out_arr <= hdr_fields_in_arr;
+ else
+ hdr_fields_out_arr <= hdr_fields_wrong_arr;
+ end if;
+ toggle <= not toggle;
else
- hdr_fields_out_arr <= hdr_fields_rst;
+ hdr_fields_out_arr <= hdr_fields_rst;
end if;
- if c_nof_packets + 1 <= counter then
- tb_end <= '1';
+ if c_nof_packets + 1 <= counter then
+ tb_end <= '1';
end if;
end process;
dut : entity work.dp_offload_rx_filter
- generic map(
- g_nof_streams => c_nof_streams, -- : POSITIVE;
- g_data_w => c_data_w, -- : NATURAL;
- g_hdr_field_arr => c_hdr_field_arr, -- : t_common_field_arr;
- g_eth_dst_mac_ena => true, -- : BOOLEAN;
- g_ip_dst_addr_ena => true, -- : BOOLEAN;
- g_ip_total_length_ena => true, -- : BOOLEAN;
- g_udp_dst_port_ena => true -- : BOOLEAN
- )
- port map(
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- snk_in_arr => snk_in_arr,
- snk_out_arr => snk_out_arr,
-
- src_out_arr => src_out_arr,
- src_in_arr => src_in_arr,
-
- hdr_fields_out_arr => hdr_fields_out_arr,
- hdr_fields_in_arr => hdr_fields_in_arr
- );
+ generic map(
+ g_nof_streams => c_nof_streams, -- : POSITIVE;
+ g_data_w => c_data_w, -- : NATURAL;
+ g_hdr_field_arr => c_hdr_field_arr, -- : t_common_field_arr;
+ g_eth_dst_mac_ena => true, -- : BOOLEAN;
+ g_ip_dst_addr_ena => true, -- : BOOLEAN;
+ g_ip_total_length_ena => true, -- : BOOLEAN;
+ g_udp_dst_port_ena => true -- : BOOLEAN
+ )
+ port map(
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_in_arr => snk_in_arr,
+ snk_out_arr => snk_out_arr,
+
+ src_out_arr => src_out_arr,
+ src_in_arr => src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr,
+ hdr_fields_in_arr => hdr_fields_in_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
index 41811773fe..8f9717db73 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
@@ -53,17 +53,17 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_offload_tx_v3 is
generic (
@@ -91,9 +91,10 @@ architecture tb of tb_dp_offload_tx_v3 is
-- . If g_symbol_w < g_data_w then boundary is at last symbol, so empty is 1.
constant c_nof_symbols_per_data : natural := g_data_w / g_symbol_w;
constant c_nof_symbols_per_bsn : natural := c_dp_stream_bsn_w / g_symbol_w; -- = 64 / g_symbol_w
- constant c_bsn_w : natural := sel_a_b(c_nof_symbols_per_data = 1,
- g_symbol_w * c_nof_symbols_per_bsn,
- g_symbol_w * (c_nof_symbols_per_bsn - g_empty));
+ constant c_bsn_w : natural := sel_a_b(
+ c_nof_symbols_per_data = 1,
+ g_symbol_w * c_nof_symbols_per_bsn,
+ g_symbol_w * (c_nof_symbols_per_bsn - g_empty));
constant c_use_shortened_header : boolean := c_bsn_w <= c_word_w;
-- dp_stream_stimuli
@@ -134,142 +135,147 @@ architecture tb of tb_dp_offload_tx_v3 is
-- Notes:
-- . pre-calculated ip_header_checksum is valid only for UNB0, FN0 targeting IP 10.10.10.10
-- . udp_total_length = 176 beamlets * 64b / 8b = 1408B + 14 DP bytes + 8 UDP bytes = 1430B
- constant c_udp_offload_hdr_field_arr : t_common_field_arr(c_udp_offload_nof_hdr_fields - 1 downto 0) := ( -- index
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ), -- 21
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(x"0123456789AB") ), -- 20
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ), -- 19
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), -- 18
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ), -- 17
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ), -- 16
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ), -- 15
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ), -- 14
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ), -- 13
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ), -- 12
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ), -- 11
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ), -- 10
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(29928) ), -- 9
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ), -- 8
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ), -- 7
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ), -- 6
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- 5
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ), -- 4
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ), -- 3
- ( field_name_pad("dp_reserved" ), "RW", 47, field_default(x"010203040506") ), -- 2
- ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ), -- 1
- ( field_name_pad("dp_bsn" ), "RW", c_bsn_w, field_default(0) ) ); -- 0
+ constant c_udp_offload_hdr_field_arr : t_common_field_arr(
+ c_udp_offload_nof_hdr_fields - 1 downto 0) := ( -- index
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ), -- 21
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(x"0123456789AB") ), -- 20
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ), -- 19
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), -- 18
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ), -- 17
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ), -- 16
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ), -- 15
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ), -- 14
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ), -- 13
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ), -- 12
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ), -- 11
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ), -- 10
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(29928) ), -- 9
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ), -- 8
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ), -- 7
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ), -- 6
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- 5
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ), -- 4
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ), -- 3
+ ( field_name_pad("dp_reserved" ), "RW", 47, field_default(x"010203040506") ), -- 2
+ ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ), -- 1
+ ( field_name_pad("dp_bsn" ), "RW", c_bsn_w, field_default(0) ) ); -- 0
-- TX: Corresponding storage of c_udp_offload_hdr_field_arr in MM register words
-- . Note: It appears that the tx_hdr_word read values are the MM write values, so read of value from logic fields (with MM override '0', e.g. dp_bsn, eth_src_mac) is not supported.
- constant c_expected_tx_hdr_word_arr_default : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_default - 1) := ( -- word address
- X"00000000", -- 0 = dp_bsn[31:0] -- readback is MM value, not the logic value
- X"00000000", -- 1 = dp_bsn[c_bsn_w-1:32]
- X"00000000", -- 2 = dp_sync
- X"03040506", -- 3 = dp_reserved[31:0]
- X"00000102", -- 4 = dp_reserved[47:32]
- X"00000000", -- 5 = udp_checksum
- X"00000596", -- 6 = udp_total_length
- X"00000000", -- 7 = udp_dst_port
- X"00000000", -- 8 = udp_src_port -- readback is MM value, not the logic value
- X"C0A80001", -- 9 = ip_dst_addr
- X"C0A80009", -- 10 = ip_src_addr
- X"000074E8", -- 11 = ip_header_checksum
- X"00000011", -- 12 = ip_protocol
- X"0000007F", -- 13 = ip_time_to_live
- X"00000000", -- 14 = ip_fragment_offset
- X"00000002", -- 15 = ip_flags
- X"00000000", -- 16 = ip_identification
- X"000005AA", -- 17 = ip_total_length
- X"00000000", -- 18 = ip_services
- X"00000005", -- 19 = ip_header_length
- X"00000004", -- 20 = ip_version
- X"00000800", -- 21 = eth_type[15:0]
- X"456789AB", -- 22 = eth_src_mac[31:0] -- readback is MM value, not the logic value
- X"00000123", -- 23 = eth_src_mac[47:32]
- X"214368AC", -- 24 = eth_dst_mac[31:0]
- X"0000001B"); -- 25 = eth_dst_mac[47:32]
-
- constant c_expected_tx_hdr_word_arr_shortened : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_shortened - 1) := ( -- word address
- X"00000000", -- 0 = dp_bsn[c_bsn_w-1:0] -- readback is MM value, not the logic value
- X"00000000", -- 1 = dp_sync
- X"03040506", -- 2 = dp_reserved[31:0]
- X"00000102", -- 3 = dp_reserved[47:32]
- X"00000000", -- 4 = udp_checksum
- X"00000596", -- 5 = udp_total_length
- X"00000000", -- 6 = udp_dst_port
- X"00000000", -- 7 = udp_src_port -- readback is MM value, not the logic value
- X"C0A80001", -- 8 = ip_dst_addr
- X"C0A80009", -- 9 = ip_src_addr
- X"000074E8", -- 10 = ip_header_checksum
- X"00000011", -- 11 = ip_protocol
- X"0000007F", -- 12 = ip_time_to_live
- X"00000000", -- 13 = ip_fragment_offset
- X"00000002", -- 14 = ip_flags
- X"00000000", -- 15 = ip_identification
- X"000005AA", -- 16 = ip_total_length
- X"00000000", -- 17 = ip_services
- X"00000005", -- 18 = ip_header_length
- X"00000004", -- 19 = ip_version
- X"00000800", -- 20 = eth_type[15:0]
- X"456789AB", -- 21 = eth_src_mac[31:0] -- readback is MM value, not the logic value
- X"00000123", -- 22 = eth_src_mac[47:32]
- X"214368AC", -- 23 = eth_dst_mac[31:0]
- X"0000001B"); -- 24 = eth_dst_mac[47:32]
+ constant c_expected_tx_hdr_word_arr_default : t_slv_32_arr(
+ 0 to c_udp_offload_nof_hdr_words_default - 1) := ( -- word address
+ X"00000000", -- 0 = dp_bsn[31:0] -- readback is MM value, not the logic value
+ X"00000000", -- 1 = dp_bsn[c_bsn_w-1:32]
+ X"00000000", -- 2 = dp_sync
+ X"03040506", -- 3 = dp_reserved[31:0]
+ X"00000102", -- 4 = dp_reserved[47:32]
+ X"00000000", -- 5 = udp_checksum
+ X"00000596", -- 6 = udp_total_length
+ X"00000000", -- 7 = udp_dst_port
+ X"00000000", -- 8 = udp_src_port -- readback is MM value, not the logic value
+ X"C0A80001", -- 9 = ip_dst_addr
+ X"C0A80009", -- 10 = ip_src_addr
+ X"000074E8", -- 11 = ip_header_checksum
+ X"00000011", -- 12 = ip_protocol
+ X"0000007F", -- 13 = ip_time_to_live
+ X"00000000", -- 14 = ip_fragment_offset
+ X"00000002", -- 15 = ip_flags
+ X"00000000", -- 16 = ip_identification
+ X"000005AA", -- 17 = ip_total_length
+ X"00000000", -- 18 = ip_services
+ X"00000005", -- 19 = ip_header_length
+ X"00000004", -- 20 = ip_version
+ X"00000800", -- 21 = eth_type[15:0]
+ X"456789AB", -- 22 = eth_src_mac[31:0] -- readback is MM value, not the logic value
+ X"00000123", -- 23 = eth_src_mac[47:32]
+ X"214368AC", -- 24 = eth_dst_mac[31:0]
+ X"0000001B"); -- 25 = eth_dst_mac[47:32]
+
+ constant c_expected_tx_hdr_word_arr_shortened : t_slv_32_arr(
+ 0 to c_udp_offload_nof_hdr_words_shortened - 1) := ( -- word address
+ X"00000000", -- 0 = dp_bsn[c_bsn_w-1:0] -- readback is MM value, not the logic value
+ X"00000000", -- 1 = dp_sync
+ X"03040506", -- 2 = dp_reserved[31:0]
+ X"00000102", -- 3 = dp_reserved[47:32]
+ X"00000000", -- 4 = udp_checksum
+ X"00000596", -- 5 = udp_total_length
+ X"00000000", -- 6 = udp_dst_port
+ X"00000000", -- 7 = udp_src_port -- readback is MM value, not the logic value
+ X"C0A80001", -- 8 = ip_dst_addr
+ X"C0A80009", -- 9 = ip_src_addr
+ X"000074E8", -- 10 = ip_header_checksum
+ X"00000011", -- 11 = ip_protocol
+ X"0000007F", -- 12 = ip_time_to_live
+ X"00000000", -- 13 = ip_fragment_offset
+ X"00000002", -- 14 = ip_flags
+ X"00000000", -- 15 = ip_identification
+ X"000005AA", -- 16 = ip_total_length
+ X"00000000", -- 17 = ip_services
+ X"00000005", -- 18 = ip_header_length
+ X"00000004", -- 19 = ip_version
+ X"00000800", -- 20 = eth_type[15:0]
+ X"456789AB", -- 21 = eth_src_mac[31:0] -- readback is MM value, not the logic value
+ X"00000123", -- 22 = eth_src_mac[47:32]
+ X"214368AC", -- 23 = eth_dst_mac[31:0]
+ X"0000001B"); -- 24 = eth_dst_mac[47:32]
-- RX: Corresponding storage of c_udp_offload_hdr_field_arr in MM register words
- constant c_expected_rx_hdr_word_arr_default : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_default - 1) := ( -- word address
- X"00000002", -- 0 = dp_bsn[31:0] -- dynamic value obtained from simulation
- X"00000000", -- 1 = dp_bsn[c_bsn_w-1:32]
- X"00000001", -- 2 = dp_sync -- dynamic value obtained from simulation
- X"03040506", -- 3 = dp_reserved[31:0]
- X"00000102", -- 4 = dp_reserved[47:32]
- X"00000000", -- 5 = udp_checksum
- X"00000596", -- 6 = udp_total_length
- X"00000000", -- 7 = udp_dst_port
- X"00000000", -- 8 = udp_src_port
- X"C0A80001", -- 9 = ip_dst_addr
- X"C0A80009", -- 10 = ip_src_addr
- X"000074E8", -- 11 = ip_header_checksum
- X"00000011", -- 12 = ip_protocol
- X"0000007F", -- 13 = ip_time_to_live
- X"00000000", -- 14 = ip_fragment_offset
- X"00000002", -- 15 = ip_flags
- X"00000000", -- 16 = ip_identification
- X"000005AA", -- 17 = ip_total_length
- X"00000000", -- 18 = ip_services
- X"00000005", -- 19 = ip_header_length
- X"00000004", -- 20 = ip_version
- X"00000800", -- 21 = eth_type[15:0]
- X"86080000", -- 22 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
- X"00000022", -- 23 = eth_src_mac[47:32]
- X"214368AC", -- 24 = eth_dst_mac[31:0]
- X"0000001B"); -- 25 = eth_dst_mac[47:32]
-
- constant c_expected_rx_hdr_word_arr_shortened : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_shortened - 1) := ( -- word address
- X"00000002", -- 0 = dp_bsn[c_bsn_w-1:0] -- dynamic value obtained from simulation
- X"00000001", -- 1 = dp_sync -- dynamic value obtained from simulation
- X"03040506", -- 2 = dp_reserved[31:0]
- X"00000102", -- 3 = dp_reserved[47:32]
- X"00000000", -- 4 = udp_checksum
- X"00000596", -- 5 = udp_total_length
- X"00000000", -- 6 = udp_dst_port
- X"00000000", -- 7 = udp_src_port
- X"C0A80001", -- 8 = ip_dst_addr
- X"C0A80009", -- 9 = ip_src_addr
- X"000074E8", -- 10 = ip_header_checksum
- X"00000011", -- 11 = ip_protocol
- X"0000007F", -- 12 = ip_time_to_live
- X"00000000", -- 13 = ip_fragment_offset
- X"00000002", -- 14 = ip_flags
- X"00000000", -- 15 = ip_identification
- X"000005AA", -- 16 = ip_total_length
- X"00000000", -- 17 = ip_services
- X"00000005", -- 18 = ip_header_length
- X"00000004", -- 19 = ip_version
- X"00000800", -- 20 = eth_type[15:0]
- X"86080000", -- 21 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
- X"00000022", -- 22 = eth_src_mac[47:32]
- X"214368AC", -- 23 = eth_dst_mac[31:0]
- X"0000001B"); -- 24 = eth_dst_mac[47:32]
+ constant c_expected_rx_hdr_word_arr_default : t_slv_32_arr(
+ 0 to c_udp_offload_nof_hdr_words_default - 1) := ( -- word address
+ X"00000002", -- 0 = dp_bsn[31:0] -- dynamic value obtained from simulation
+ X"00000000", -- 1 = dp_bsn[c_bsn_w-1:32]
+ X"00000001", -- 2 = dp_sync -- dynamic value obtained from simulation
+ X"03040506", -- 3 = dp_reserved[31:0]
+ X"00000102", -- 4 = dp_reserved[47:32]
+ X"00000000", -- 5 = udp_checksum
+ X"00000596", -- 6 = udp_total_length
+ X"00000000", -- 7 = udp_dst_port
+ X"00000000", -- 8 = udp_src_port
+ X"C0A80001", -- 9 = ip_dst_addr
+ X"C0A80009", -- 10 = ip_src_addr
+ X"000074E8", -- 11 = ip_header_checksum
+ X"00000011", -- 12 = ip_protocol
+ X"0000007F", -- 13 = ip_time_to_live
+ X"00000000", -- 14 = ip_fragment_offset
+ X"00000002", -- 15 = ip_flags
+ X"00000000", -- 16 = ip_identification
+ X"000005AA", -- 17 = ip_total_length
+ X"00000000", -- 18 = ip_services
+ X"00000005", -- 19 = ip_header_length
+ X"00000004", -- 20 = ip_version
+ X"00000800", -- 21 = eth_type[15:0]
+ X"86080000", -- 22 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
+ X"00000022", -- 23 = eth_src_mac[47:32]
+ X"214368AC", -- 24 = eth_dst_mac[31:0]
+ X"0000001B"); -- 25 = eth_dst_mac[47:32]
+
+ constant c_expected_rx_hdr_word_arr_shortened : t_slv_32_arr(
+ 0 to c_udp_offload_nof_hdr_words_shortened - 1) := ( -- word address
+ X"00000002", -- 0 = dp_bsn[c_bsn_w-1:0] -- dynamic value obtained from simulation
+ X"00000001", -- 1 = dp_sync -- dynamic value obtained from simulation
+ X"03040506", -- 2 = dp_reserved[31:0]
+ X"00000102", -- 3 = dp_reserved[47:32]
+ X"00000000", -- 4 = udp_checksum
+ X"00000596", -- 5 = udp_total_length
+ X"00000000", -- 6 = udp_dst_port
+ X"00000000", -- 7 = udp_src_port
+ X"C0A80001", -- 8 = ip_dst_addr
+ X"C0A80009", -- 9 = ip_src_addr
+ X"000074E8", -- 10 = ip_header_checksum
+ X"00000011", -- 11 = ip_protocol
+ X"0000007F", -- 12 = ip_time_to_live
+ X"00000000", -- 13 = ip_fragment_offset
+ X"00000002", -- 14 = ip_flags
+ X"00000000", -- 15 = ip_identification
+ X"000005AA", -- 16 = ip_total_length
+ X"00000000", -- 17 = ip_services
+ X"00000005", -- 18 = ip_header_length
+ X"00000004", -- 19 = ip_version
+ X"00000800", -- 20 = eth_type[15:0]
+ X"86080000", -- 21 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
+ X"00000022", -- 22 = eth_src_mac[47:32]
+ X"214368AC", -- 23 = eth_dst_mac[31:0]
+ X"0000001B"); -- 24 = eth_dst_mac[47:32]
-- From apertif_unb1_fn_beamformer_udp_offload.vhd: 221 111111111000 0000 000
-- Override ('1') only the Ethernet fields so we can use MM defaults there. 109 876543210987 6543 210
@@ -353,38 +359,38 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_data_init => c_data_init,
- g_bsn_init => c_bsn_init,
- -- specific
- g_in_dat_w => g_data_w,
- g_nof_repeat => c_nof_packets,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_wait_last_evt
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_data_init => c_data_init,
+ g_bsn_init => c_bsn_init,
+ -- specific
+ g_in_dat_w => g_data_w,
+ g_nof_repeat => c_nof_packets,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_wait_last_evt
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -418,37 +424,37 @@ begin
verify_last_snk_in_evt.err <= '0';
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => g_data_w,
- g_pkt_len => c_expected_pkt_len
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => g_data_w,
+ g_pkt_len => c_expected_pkt_len
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT offload Tx
@@ -458,23 +464,23 @@ begin
-- Use FIFO to mimic apertif_unb1_fn_beamformer_udp_offload.vhd, without FIFO dp_stream_stimuli
-- would handle the back pressure
u_dp_fifo_sc : entity work.dp_fifo_sc
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => 64,
- g_use_sync => true,
- g_use_bsn => true,
- g_fifo_size => 1024
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => OPEN, -- stimuli_src_in
- snk_in => stimuli_src_out,
-
- src_in => dp_fifo_sc_src_in,
- src_out => dp_fifo_sc_src_out
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => 64,
+ g_use_sync => true,
+ g_use_bsn => true,
+ g_fifo_size => 1024
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => OPEN, -- stimuli_src_in
+ snk_in => stimuli_src_out,
+
+ src_in => dp_fifo_sc_src_in,
+ src_out => dp_fifo_sc_src_out
+ );
dp_offload_tx_snk_in_arr(0) <= dp_fifo_sc_src_out;
dp_fifo_sc_src_in <= dp_offload_tx_snk_out_arr(0);
@@ -493,32 +499,32 @@ begin
tx_hdr_fields_in_arr(0)(field_hi(c_udp_offload_hdr_field_arr, "dp_bsn" ) downto field_lo(c_udp_offload_hdr_field_arr, "dp_bsn" )) <= dp_offload_tx_snk_in_arr(0).bsn(c_bsn_w - 1 downto 0);
u_tx : entity work.dp_offload_tx_v3
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_hdr_field_arr => c_udp_offload_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_tx_snk_in_arr,
- snk_out_arr => dp_offload_tx_snk_out_arr,
-
- src_out_arr => tx_offload_sosi_arr,
- src_in_arr => tx_offload_siso_arr,
-
- hdr_fields_in_arr => tx_hdr_fields_in_arr,
- hdr_fields_out_arr => tx_hdr_fields_out_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_hdr_field_arr => c_udp_offload_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_tx_snk_in_arr,
+ snk_out_arr => dp_offload_tx_snk_out_arr,
+
+ src_out_arr => tx_offload_sosi_arr,
+ src_in_arr => tx_offload_siso_arr,
+
+ hdr_fields_in_arr => tx_hdr_fields_in_arr,
+ hdr_fields_out_arr => tx_hdr_fields_out_arr
+ );
p_rd_tx_hdr_words : process
variable v_word : std_logic_vector(c_word_w - 1 downto 0);
@@ -575,33 +581,33 @@ begin
------------------------------------------------------------------------------
u_rx : entity work.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_hdr_field_arr => c_udp_offload_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- snk_in_arr => link_offload_sosi_arr,
- snk_out_arr => link_offload_siso_arr,
-
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
-
- hdr_fields_out_arr => rx_hdr_fields_out_arr,
- hdr_fields_raw_arr => rx_hdr_fields_raw_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_hdr_field_arr => c_udp_offload_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ snk_in_arr => link_offload_sosi_arr,
+ snk_out_arr => link_offload_siso_arr,
+
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => rx_hdr_fields_out_arr,
+ hdr_fields_raw_arr => rx_hdr_fields_raw_arr
+ );
p_restore_sync_bsn : process(dp_offload_rx_src_out_arr, rx_hdr_fields_out_arr)
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
index f0d5e7bde9..42244b34d5 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
@@ -27,13 +27,13 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_packet is
generic (
@@ -66,8 +66,8 @@ architecture tb of tb_dp_packet is
constant c_nof_ch : natural := 10;
constant c_len_arr : t_natural_arr(0 to c_nof_ch - 1) := (1, 1, 1, 2, 3, 5, 10, 17, 32, 100);
-- Use these to verify the entire channel field width.
--- CONSTANT c_nof_ch : NATURAL := c_channel_mod + 10;
--- CONSTANT c_len_arr : t_natural_arr(0 TO c_nof_ch-1) := array_init(1, c_nof_ch, 0);
+ -- CONSTANT c_nof_ch : NATURAL := c_channel_mod + 10;
+ -- CONSTANT c_len_arr : t_natural_arr(0 TO c_nof_ch-1) := array_init(1, c_nof_ch, 0);
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
@@ -241,19 +241,19 @@ begin
-- Encode the data block to a DP packet
u_dp_packet_enc : entity work.dp_packet_enc
- generic map (
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => in_siso,
- snk_in => in_sosi,
- -- ST source
- src_in => enc_siso,
- src_out => enc_sosi
- );
+ generic map (
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- ST source
+ src_in => enc_siso,
+ src_out => enc_sosi
+ );
-- Restrict to link g_data_w
enc_siso <= pkt_siso;
@@ -276,19 +276,19 @@ begin
-- Decode the DP packet into a data block
u_dp_packet_dec : entity work.dp_packet_dec
- generic map (
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => pkt_siso,
- snk_in => pkt_sosi,
- -- ST source
- src_in => rx_siso,
- src_out => rx_sosi
- );
+ generic map (
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => pkt_siso,
+ snk_in => pkt_sosi,
+ -- ST source
+ src_in => rx_siso,
+ src_out => rx_sosi
+ );
-- Map to slv to ease monitoring in wave window
rx_data <= rx_sosi.data(rx_data'range);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
index 6466f7e36b..8c6353b59b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
@@ -45,13 +45,13 @@
-- . Add tb_tb_dp_packet_merge to the DP lib regression testbench tb_tb_tb_backpressure.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_packet_merge is
generic (
@@ -296,22 +296,22 @@ begin
-- Merge every g_nof_pkt incomming packets into output packets
u_dp_packet_merge : entity work.dp_packet_merge
- generic map (
- g_nof_pkt => g_nof_pkt,
- g_align_at_sync => g_align_at_sync,
- g_bsn_increment => g_bsn_increment,
- g_bsn_err_bi => c_bsn_err_bi
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => dp_packet_merge_snk_out,
- snk_in => dp_packet_merge_snk_in,
-
- src_in => dp_packet_merge_src_in,
- src_out => dp_packet_merge_src_out
- );
+ generic map (
+ g_nof_pkt => g_nof_pkt,
+ g_align_at_sync => g_align_at_sync,
+ g_bsn_increment => g_bsn_increment,
+ g_bsn_err_bi => c_bsn_err_bi
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => dp_packet_merge_snk_out,
+ snk_in => dp_packet_merge_snk_in,
+
+ src_in => dp_packet_merge_src_in,
+ src_out => dp_packet_merge_src_out
+ );
------------------------------------------------------------------------------
-- Optional reverse DUT dp_packet_unmerge
@@ -323,19 +323,19 @@ begin
gen_dp_packet_unmerge : if g_use_dp_packet_unmerge = true generate
u_dp_packet_unmerge : entity work.dp_packet_unmerge
- generic map (
- g_nof_pkt => g_nof_pkt
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => dp_packet_merge_src_in,
- snk_in => dp_packet_merge_src_out,
-
- src_in => dp_packet_unmerge_src_in,
- src_out => dp_packet_unmerge_src_out
- );
+ generic map (
+ g_nof_pkt => g_nof_pkt
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => dp_packet_merge_src_in,
+ snk_in => dp_packet_merge_src_out,
+
+ src_in => dp_packet_unmerge_src_in,
+ src_out => dp_packet_unmerge_src_out
+ );
dp_packet_unmerge_src_in <= verify_snk_out;
verify_snk_in <= dp_packet_unmerge_src_out;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
index 7046fe0e48..b24763867c 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_packetizing_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_packetizing_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_packetizing is
generic (
@@ -66,90 +66,91 @@ architecture tb of tb_dp_packetizing is
constant c_nof_block_per_sync : natural := 10;
constant c_fifo_size : natural := c_usr_block_size;
- constant c_fifo_fill : integer := sel_a_b(g_usr_nof_words <= g_phy_nof_words,
- 0, -- no_xmt_pacer (dummy value)
- c_usr_block_size - c_phy_block_size); -- gen_xmt_pacer
-
- constant c_rcv_fifo_nof_words : natural := c_phy_block_size;
-
- signal sl0 : std_logic := '1';
- signal sl1 : std_logic := '1';
-
- signal clk : std_logic := '1';
- signal rst : std_logic := '1';
-
- signal sync_nr : natural;
- signal block_nr : natural;
-
- signal in_sync : std_logic := '0';
- signal in_val : std_logic := '0';
- signal in_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '0');
-
- signal xmt_fsn : std_logic_vector(c_fsn_w - 1 downto 0) := (others => '0');
- signal xmt_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '0');
- signal xmt_val : std_logic;
- signal xmt_sof : std_logic;
- signal xmt_eof : std_logic;
- signal xmt_err : std_logic;
-
- signal xmt_frm_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '0');
- signal xmt_frm_val : std_logic;
- signal xmt_frm_sof : std_logic;
- signal xmt_frm_eof : std_logic;
-
- signal xmt_pack_dat : std_logic_vector(g_phy_dat_w - 1 downto 0) := (others => '0');
- signal xmt_pack_val : std_logic;
- signal xmt_pack_sof : std_logic;
- signal xmt_pack_eof : std_logic;
-
- signal xmt_pace_dat : std_logic_vector(g_phy_dat_w - 1 downto 0) := (others => '0');
- signal xmt_pace_val : std_logic_vector(0 downto 0);
- signal xmt_pace_sof : std_logic_vector(0 downto 0);
- signal xmt_pace_eof : std_logic_vector(0 downto 0);
-
- signal xmt_pace_sosi : t_dp_sosi;
- signal phy_tx_sosi : t_dp_sosi;
-
- signal phy_tx_dat : std_logic_vector(g_phy_dat_w - 1 downto 0) := (others => '0');
- signal phy_tx_val : std_logic;
-
- signal phy_rx_dat : std_logic_vector(g_phy_dat_w - 1 downto 0) := (others => '0');
- signal phy_rx_val : std_logic;
-
- signal rcv_pack_dat : std_logic_vector(g_phy_dat_w - 1 downto 0) := (others => '0');
- signal rcv_pack_val : std_logic;
- signal rcv_pack_sof : std_logic;
- signal rcv_pack_eof : std_logic;
-
- signal rcv_pack_sosi : t_dp_sosi;
- signal rcv_fifo_rd_siso : t_dp_siso;
- signal rcv_fifo_rd_sosi : t_dp_sosi;
-
- signal rcv_fifo_rd_req : std_logic;
- signal rcv_fifo_rd_dat : std_logic_vector(g_phy_dat_w - 1 downto 0);
- signal rcv_fifo_rd_val : std_logic;
- signal rcv_fifo_rd_sof : std_logic;
- signal rcv_fifo_rd_eof : std_logic;
-
- signal rcv_throttle_dat : std_logic_vector(g_phy_dat_w - 1 downto 0) := (others => '0');
- signal rcv_throttle_val : std_logic;
- signal rcv_throttle_sof : std_logic;
- signal rcv_throttle_eof : std_logic;
-
- signal rcv_frm_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '0');
- signal rcv_frm_val : std_logic;
- signal rcv_frm_sof : std_logic;
- signal rcv_frm_eof : std_logic;
-
- signal rcv_sync : std_logic;
- signal rcv_fsn : std_logic_vector(c_fsn_w - 1 downto 0) := (others => '0');
- signal rcv_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '0');
- signal rcv_val : std_logic;
- signal rcv_sof : std_logic;
- signal rcv_eof : std_logic;
- signal rcv_err : std_logic := '0';
-
- signal prev_rcv_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '1'); -- -1 to also verify first sample 0 correctly
+ constant c_fifo_fill : integer := sel_a_b(
+ g_usr_nof_words <= g_phy_nof_words,
+ 0, -- no_xmt_pacer (dummy value)
+ c_usr_block_size - c_phy_block_size); -- gen_xmt_pacer
+
+ constant c_rcv_fifo_nof_words : natural := c_phy_block_size;
+
+ signal sl0 : std_logic := '1';
+ signal sl1 : std_logic := '1';
+
+ signal clk : std_logic := '1';
+ signal rst : std_logic := '1';
+
+ signal sync_nr : natural;
+ signal block_nr : natural;
+
+ signal in_sync : std_logic := '0';
+ signal in_val : std_logic := '0';
+ signal in_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '0');
+
+ signal xmt_fsn : std_logic_vector(c_fsn_w - 1 downto 0) := (others => '0');
+ signal xmt_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '0');
+ signal xmt_val : std_logic;
+ signal xmt_sof : std_logic;
+ signal xmt_eof : std_logic;
+ signal xmt_err : std_logic;
+
+ signal xmt_frm_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '0');
+ signal xmt_frm_val : std_logic;
+ signal xmt_frm_sof : std_logic;
+ signal xmt_frm_eof : std_logic;
+
+ signal xmt_pack_dat : std_logic_vector(g_phy_dat_w - 1 downto 0) := (others => '0');
+ signal xmt_pack_val : std_logic;
+ signal xmt_pack_sof : std_logic;
+ signal xmt_pack_eof : std_logic;
+
+ signal xmt_pace_dat : std_logic_vector(g_phy_dat_w - 1 downto 0) := (others => '0');
+ signal xmt_pace_val : std_logic_vector(0 downto 0);
+ signal xmt_pace_sof : std_logic_vector(0 downto 0);
+ signal xmt_pace_eof : std_logic_vector(0 downto 0);
+
+ signal xmt_pace_sosi : t_dp_sosi;
+ signal phy_tx_sosi : t_dp_sosi;
+
+ signal phy_tx_dat : std_logic_vector(g_phy_dat_w - 1 downto 0) := (others => '0');
+ signal phy_tx_val : std_logic;
+
+ signal phy_rx_dat : std_logic_vector(g_phy_dat_w - 1 downto 0) := (others => '0');
+ signal phy_rx_val : std_logic;
+
+ signal rcv_pack_dat : std_logic_vector(g_phy_dat_w - 1 downto 0) := (others => '0');
+ signal rcv_pack_val : std_logic;
+ signal rcv_pack_sof : std_logic;
+ signal rcv_pack_eof : std_logic;
+
+ signal rcv_pack_sosi : t_dp_sosi;
+ signal rcv_fifo_rd_siso : t_dp_siso;
+ signal rcv_fifo_rd_sosi : t_dp_sosi;
+
+ signal rcv_fifo_rd_req : std_logic;
+ signal rcv_fifo_rd_dat : std_logic_vector(g_phy_dat_w - 1 downto 0);
+ signal rcv_fifo_rd_val : std_logic;
+ signal rcv_fifo_rd_sof : std_logic;
+ signal rcv_fifo_rd_eof : std_logic;
+
+ signal rcv_throttle_dat : std_logic_vector(g_phy_dat_w - 1 downto 0) := (others => '0');
+ signal rcv_throttle_val : std_logic;
+ signal rcv_throttle_sof : std_logic;
+ signal rcv_throttle_eof : std_logic;
+
+ signal rcv_frm_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '0');
+ signal rcv_frm_val : std_logic;
+ signal rcv_frm_sof : std_logic;
+ signal rcv_frm_eof : std_logic;
+
+ signal rcv_sync : std_logic;
+ signal rcv_fsn : std_logic_vector(c_fsn_w - 1 downto 0) := (others => '0');
+ signal rcv_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '0');
+ signal rcv_val : std_logic;
+ signal rcv_sof : std_logic;
+ signal rcv_eof : std_logic;
+ signal rcv_err : std_logic := '0';
+
+ signal prev_rcv_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '1'); -- -1 to also verify first sample 0 correctly
begin
clk <= not clk after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -160,27 +161,27 @@ begin
-- Generate data path input data
proc_dp_gen_block_data(c_nof_block_per_sync,
- c_usr_block_size,
- c_gap_size,
- g_usr_nof_words, -- apply throttle at generator
- g_phy_nof_words,
- rst,
- clk,
- sync_nr,
- block_nr,
- in_sync,
- in_val,
- in_dat);
+ c_usr_block_size,
+ c_gap_size,
+ g_usr_nof_words, -- apply throttle at generator
+ g_phy_nof_words,
+ rst,
+ clk,
+ sync_nr,
+ block_nr,
+ in_sync,
+ in_val,
+ in_dat);
-- Verify the data path output data
proc_dp_verify_data("rcv_dat",
- 1, -- c_ready_latency, any value > 0 suits here
- clk,
- sl1, -- verify_en
- sl1, -- out_ready
- rcv_val,
- rcv_dat,
- prev_rcv_dat);
+ 1, -- c_ready_latency, any value > 0 suits here
+ clk,
+ sl1, -- verify_en
+ sl1, -- out_ready
+ rcv_val,
+ rcv_dat,
+ prev_rcv_dat);
-- Verify the data path output CRC (avoid error message at initialisation)
assert NOW = 0 ps or rcv_err = '0' report "rcv_err = '1' indicating CRC error" severity ERROR;
@@ -191,95 +192,95 @@ begin
-- Determine the data block control signals: sof, eof, err and fsn
u_frame_fsn : entity work.dp_frame_fsn
- generic map (
- g_fsn_w => c_fsn_w,
- g_dat_w => g_usr_dat_w,
- g_use_sync => true,
- g_block_size => c_usr_block_size
- )
- port map (
- rst => rst,
- clk => clk,
- in_sync => in_sync,
- in_val => in_val,
- in_dat => in_dat,
- out_fsn => xmt_fsn,
- out_dat => xmt_dat,
- out_val => xmt_val,
- out_sof => xmt_sof,
- out_eof => xmt_eof,
- out_err => xmt_err
- );
+ generic map (
+ g_fsn_w => c_fsn_w,
+ g_dat_w => g_usr_dat_w,
+ g_use_sync => true,
+ g_block_size => c_usr_block_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sync => in_sync,
+ in_val => in_val,
+ in_dat => in_dat,
+ out_fsn => xmt_fsn,
+ out_dat => xmt_dat,
+ out_val => xmt_val,
+ out_sof => xmt_sof,
+ out_eof => xmt_eof,
+ out_err => xmt_err
+ );
-- Insert the fsn and err into the internal data path frame format
u_frame : entity work.dp_frame
- generic map (
- g_fsn_w => c_fsn_w,
- g_dat_w => g_usr_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_fsn => xmt_fsn,
- in_dat => xmt_dat,
- in_val => xmt_val,
- in_sof => xmt_sof,
- in_eof => xmt_eof,
- in_err => xmt_err,
-
- out_dat => xmt_frm_dat,
- out_val => xmt_frm_val,
- out_sof => xmt_frm_sof,
- out_eof => xmt_frm_eof
- );
+ generic map (
+ g_fsn_w => c_fsn_w,
+ g_dat_w => g_usr_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_fsn => xmt_fsn,
+ in_dat => xmt_dat,
+ in_val => xmt_val,
+ in_sof => xmt_sof,
+ in_eof => xmt_eof,
+ in_err => xmt_err,
+
+ out_dat => xmt_frm_dat,
+ out_val => xmt_frm_val,
+ out_sof => xmt_frm_sof,
+ out_eof => xmt_frm_eof
+ );
-- Pack the user data width frame data into the PHY data width frame data
-- Note:
-- . The proc_dp_gen_block_data appies throttling if g_usr_nof_words <
-- g_phy_nof_words, so xmt_frm_val has a sufficiently slow pace.
u_frame_pack : entity work.dp_frame_repack
- generic map (
- g_in_dat_w => g_usr_dat_w,
- g_in_nof_words => g_usr_nof_words,
- g_out_dat_w => g_phy_dat_w,
- g_out_nof_words => g_phy_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => xmt_frm_dat,
- in_val => xmt_frm_val,
- in_sof => xmt_frm_sof,
- in_eof => xmt_frm_eof,
-
- out_dat => xmt_pack_dat,
- out_val => xmt_pack_val,
- out_sof => xmt_pack_sof,
- out_eof => xmt_pack_eof
- );
+ generic map (
+ g_in_dat_w => g_usr_dat_w,
+ g_in_nof_words => g_usr_nof_words,
+ g_out_dat_w => g_phy_dat_w,
+ g_out_nof_words => g_phy_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => xmt_frm_dat,
+ in_val => xmt_frm_val,
+ in_sof => xmt_frm_sof,
+ in_eof => xmt_frm_eof,
+
+ out_dat => xmt_pack_dat,
+ out_val => xmt_pack_val,
+ out_sof => xmt_pack_sof,
+ out_eof => xmt_pack_eof
+ );
-- Transmit the internal data path frame as a dp PHY frame with SFD and a true CRC
u_frame_tx : entity work.dp_frame_tx
- generic map (
- g_sfd => c_dp_sfd,
- g_dat_w => g_phy_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => xmt_pack_dat,
- in_val => xmt_pack_val,
- in_sof => xmt_pack_sof,
- in_eof => xmt_pack_eof,
-
- out_dat => xmt_pace_dat,
- out_val => xmt_pace_val(0),
- out_sof => xmt_pace_sof(0),
- out_eof => xmt_pace_eof(0)
- );
+ generic map (
+ g_sfd => c_dp_sfd,
+ g_dat_w => g_phy_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => xmt_pack_dat,
+ in_val => xmt_pack_val,
+ in_sof => xmt_pack_sof,
+ in_eof => xmt_pack_eof,
+
+ out_dat => xmt_pace_dat,
+ out_val => xmt_pace_val(0),
+ out_sof => xmt_pace_sof(0),
+ out_eof => xmt_pace_eof(0)
+ );
------------------------------------------------------------------------------
-- PHY LINK INTERFACE
@@ -287,37 +288,37 @@ begin
-- Model the transceiver link
u_transceiver_link : entity work.dp_phy_link
- generic map (
- g_latency => c_phy_link_latency,
- g_valid_support => c_phy_link_valid_support
- )
- port map (
- in_dat => phy_tx_dat,
- in_val => phy_tx_val,
-
- out_dat => phy_rx_dat,
- out_val => phy_rx_val
- );
+ generic map (
+ g_latency => c_phy_link_latency,
+ g_valid_support => c_phy_link_valid_support
+ )
+ port map (
+ in_dat => phy_tx_dat,
+ in_val => phy_tx_val,
+
+ out_dat => phy_rx_dat,
+ out_val => phy_rx_val
+ );
-- Receive the dp PHY frame with SFD and a true CRC and extract the internal data path frame
u_frame_rx : entity work.dp_frame_rx
- generic map (
- g_sfd => c_dp_sfd,
- g_dat_w => g_phy_dat_w,
- g_block_size => c_phy_block_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => phy_rx_dat,
- in_val => phy_rx_val,
-
- out_dat => rcv_pack_dat,
- out_val => rcv_pack_val,
- out_sof => rcv_pack_sof,
- out_eof => rcv_pack_eof
- );
+ generic map (
+ g_sfd => c_dp_sfd,
+ g_dat_w => g_phy_dat_w,
+ g_block_size => c_phy_block_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => phy_rx_dat,
+ in_val => phy_rx_val,
+
+ out_dat => rcv_pack_dat,
+ out_val => rcv_pack_val,
+ out_sof => rcv_pack_sof,
+ out_eof => rcv_pack_eof
+ );
-- Transceiver link interface control
gen_valid_support : if c_phy_link_valid_support = true generate
@@ -372,26 +373,26 @@ begin
phy_tx_val <= phy_tx_sosi.valid;
u_fifo_fill : entity work.dp_fifo_fill
- generic map (
- g_data_w => g_phy_dat_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_fifo_fill => c_fifo_fill,
- g_fifo_size => c_fifo_size,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => OPEN, -- OUT = request to upstream ST source
- snk_in => xmt_pace_sosi,
- src_in => c_dp_siso_rdy, -- IN = request from downstream ST sink
- src_out => phy_tx_sosi
- );
+ generic map (
+ g_data_w => g_phy_dat_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_fifo_fill => c_fifo_fill,
+ g_fifo_size => c_fifo_size,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => OPEN, -- OUT = request to upstream ST source
+ snk_in => xmt_pace_sosi,
+ src_in => c_dp_siso_rdy, -- IN = request from downstream ST sink
+ src_out => phy_tx_sosi
+ );
end generate;
-- ==> 2) Use FIFO and dp_frame_rd to throttle the output frame for unpack if necessary
@@ -416,58 +417,58 @@ begin
rcv_fifo_rd_eof <= rcv_fifo_rd_sosi.eop;
dut : entity work.dp_fifo_sc
- generic map (
- g_data_w => g_phy_dat_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_ctrl => true,
- g_fifo_size => c_rcv_fifo_nof_words,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => OPEN, -- OUT = request to upstream ST source
- snk_in => rcv_pack_sosi,
- usedw => OPEN,
- src_in => rcv_fifo_rd_siso, -- IN = request from downstream ST sink
- src_out => rcv_fifo_rd_sosi
- );
+ generic map (
+ g_data_w => g_phy_dat_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_ctrl => true,
+ g_fifo_size => c_rcv_fifo_nof_words,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => OPEN, -- OUT = request to upstream ST source
+ snk_in => rcv_pack_sosi,
+ usedw => OPEN,
+ src_in => rcv_fifo_rd_siso, -- IN = request from downstream ST sink
+ src_out => rcv_fifo_rd_sosi
+ );
u_rcv_throttle : entity work.dp_frame_rd
- generic map (
- g_dat_w => g_phy_dat_w,
- g_throttle_num => g_phy_nof_words,
- g_throttle_den => g_usr_nof_words,
- g_throttle_sof => false,
- g_throttle_eof => false
- )
- port map (
- rst => rst,
- clk => clk,
-
- frm_req => '1',
- frm_flush => '0',
- frm_ack => OPEN,
- frm_busy => OPEN,
- frm_err => OPEN,
- frm_done => OPEN,
-
- rd_req => rcv_fifo_rd_req,
- rd_dat => rcv_fifo_rd_dat,
- rd_val => rcv_fifo_rd_val,
- rd_sof => rcv_fifo_rd_sof,
- rd_eof => rcv_fifo_rd_eof,
-
- out_dat => rcv_throttle_dat,
- out_val => rcv_throttle_val,
- out_sof => rcv_throttle_sof,
- out_eof => rcv_throttle_eof
- );
+ generic map (
+ g_dat_w => g_phy_dat_w,
+ g_throttle_num => g_phy_nof_words,
+ g_throttle_den => g_usr_nof_words,
+ g_throttle_sof => false,
+ g_throttle_eof => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ frm_req => '1',
+ frm_flush => '0',
+ frm_ack => OPEN,
+ frm_busy => OPEN,
+ frm_err => OPEN,
+ frm_done => OPEN,
+
+ rd_req => rcv_fifo_rd_req,
+ rd_dat => rcv_fifo_rd_dat,
+ rd_val => rcv_fifo_rd_val,
+ rd_sof => rcv_fifo_rd_sof,
+ rd_eof => rcv_fifo_rd_eof,
+
+ out_dat => rcv_throttle_dat,
+ out_val => rcv_throttle_val,
+ out_sof => rcv_throttle_sof,
+ out_eof => rcv_throttle_eof
+ );
end generate; -- gen_rcv_throttle
end generate; -- no_valid_support
@@ -477,48 +478,48 @@ begin
-- Unpack the PHY data width frame data into the user data width frame data
u_frame_unpack : entity work.dp_frame_repack
- generic map (
- g_in_dat_w => g_phy_dat_w,
- g_in_nof_words => g_phy_nof_words,
- g_out_dat_w => g_usr_dat_w,
- g_out_nof_words => g_usr_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => rcv_throttle_dat,
- in_val => rcv_throttle_val,
- in_sof => rcv_throttle_sof,
- in_eof => rcv_throttle_eof,
-
- out_dat => rcv_frm_dat,
- out_val => rcv_frm_val,
- out_sof => rcv_frm_sof,
- out_eof => rcv_frm_eof
- );
+ generic map (
+ g_in_dat_w => g_phy_dat_w,
+ g_in_nof_words => g_phy_nof_words,
+ g_out_dat_w => g_usr_dat_w,
+ g_out_nof_words => g_usr_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => rcv_throttle_dat,
+ in_val => rcv_throttle_val,
+ in_sof => rcv_throttle_sof,
+ in_eof => rcv_throttle_eof,
+
+ out_dat => rcv_frm_dat,
+ out_val => rcv_frm_val,
+ out_sof => rcv_frm_sof,
+ out_eof => rcv_frm_eof
+ );
-- Extract the dat, fsn and err from the internal data path frame format
u_unframe : entity work.dp_unframe
- generic map (
- g_fsn_w => c_fsn_w,
- g_dat_w => g_usr_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => rcv_frm_dat,
- in_val => rcv_frm_val,
- in_sof => rcv_frm_sof,
- in_eof => rcv_frm_eof,
-
- out_fsn => rcv_fsn,
- out_sync => rcv_sync,
- out_dat => rcv_dat,
- out_val => rcv_val,
- out_sof => rcv_sof,
- out_eof => rcv_eof,
- out_err => rcv_err
- );
+ generic map (
+ g_fsn_w => c_fsn_w,
+ g_dat_w => g_usr_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => rcv_frm_dat,
+ in_val => rcv_frm_val,
+ in_sof => rcv_frm_sof,
+ in_eof => rcv_frm_eof,
+
+ out_fsn => rcv_fsn,
+ out_sync => rcv_sync,
+ out_dat => rcv_dat,
+ out_val => rcv_val,
+ out_sof => rcv_sof,
+ out_eof => rcv_eof,
+ out_err => rcv_err
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
index f5bfc3ebe3..85d3dbc5c5 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
-
--- Purpose: Verify dp_pad_insert and dp_pad_remove
--- Description:
--- p_stimuli --> dp_pad_insert --> dp_pad_remove --> verify
--- Usage:
--- > as 10
--- > run -all -- signal tb_end will stop the simulation by stopping the clk
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
+
+ -- Purpose: Verify dp_pad_insert and dp_pad_remove
+ -- Description:
+ -- p_stimuli --> dp_pad_insert --> dp_pad_remove --> verify
+ -- Usage:
+ -- > as 10
+ -- > run -all -- signal tb_end will stop the simulation by stopping the clk
entity tb_dp_pad_insert_remove is
generic (
@@ -221,34 +221,34 @@ begin
-- DUT
------------------------------------------------------------------------------
u_pad_insert : entity work.dp_pad_insert
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_padding => g_nof_padding
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => in_siso,
- snk_in => in_sosi,
- src_in => pad_siso,
- src_out => pad_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_padding => g_nof_padding
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ src_in => pad_siso,
+ src_out => pad_sosi
+ );
u_pad_remove : entity work.dp_pad_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_padding => g_nof_padding
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => pad_siso,
- snk_in => pad_sosi,
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_padding => g_nof_padding
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => pad_siso,
+ snk_in => pad_sosi,
+ src_in => out_siso,
+ src_out => out_sosi
+ );
-- Map to slv to ease monitoring in wave window
in_data <= in_sosi.data(g_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
index aec011b91b..8d82b3f74c 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_pipeline is
generic (
@@ -145,15 +145,15 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
index 87366a3388..a09503152e 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
@@ -28,13 +28,13 @@
-- . The verify procedures check the correct output
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_pipeline_ready is
generic (
@@ -150,20 +150,20 @@ begin
-- proc_dp_gen_block_data() only supports RL=0 or 1, so use a latency adpater to support any g_in_latency
u_input_adapt : entity work.dp_latency_adapter
- generic map (
- g_in_latency => c_rl,
- g_out_latency => g_in_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => in_siso,
- snk_in => in_sosi,
- -- ST source
- src_in => adapt_siso,
- src_out => adapt_sosi
- );
+ generic map (
+ g_in_latency => c_rl,
+ g_out_latency => g_in_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- ST source
+ src_in => adapt_siso,
+ src_out => adapt_sosi
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -172,7 +172,7 @@ begin
-- Verification logistics
verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1'; -- enable verify after first output sop
count_eop <= count_eop + 1 when rising_edge(clk) and out_sosi.eop = '1' and((g_out_latency > 0) or
- (g_out_latency = 0 and out_siso.ready = '1')); -- count number of output eop
+ (g_out_latency = 0 and out_siso.ready = '1')); -- count number of output eop
verify_done <= '1' when rising_edge(clk) and count_eop = g_nof_repeat; -- signal verify done after g_nof_repeat frames
-- Actual verification of the output streams
@@ -195,18 +195,18 @@ begin
------------------------------------------------------------------------------
pipeline : entity work.dp_pipeline_ready
- generic map (
- g_in_latency => g_in_latency,
- g_out_latency => g_out_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => adapt_siso,
- snk_in => adapt_sosi,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ g_in_latency => g_in_latency,
+ g_out_latency => g_out_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => adapt_siso,
+ snk_in => adapt_sosi,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd b/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd
index da2ad8b364..84a19d40c2 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd
@@ -20,20 +20,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.tb_dp_pkg.all;
-
--- Purpose: Test bench to check reinterleave function on DP level
--- Usage:
--- > as 6
--- > run 2us
--- Remark:
--- This TB is only used to visually inspect the wave window to see
--- if all functions well on DP level. The actual reinterleaving itself
--- is verified more thoroughly in tb_common_reinterleave.
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.tb_dp_pkg.all;
+
+ -- Purpose: Test bench to check reinterleave function on DP level
+ -- Usage:
+ -- > as 6
+ -- > run 2us
+ -- Remark:
+ -- This TB is only used to visually inspect the wave window to see
+ -- if all functions well on DP level. The actual reinterleaving itself
+ -- is verified more thoroughly in tb_common_reinterleave.
entity tb_dp_reinterleave is
generic (
@@ -44,7 +44,7 @@ entity tb_dp_reinterleave is
g_inter_block_size : natural := 2;
g_use_complex : boolean := true;
g_align_out : boolean := true
- );
+ );
end;
architecture rtl of tb_dp_reinterleave is
@@ -94,7 +94,7 @@ begin
proc_common_wait_some_cycles(clk, c_input_inval);
v_bsn := INCR_UVEC(v_bsn, 1);
end loop;
- end process;
+ end process;
-----------------------------------------------------------------------------
-- The I/O of common_reinterleave and its lower level components operate
@@ -116,20 +116,20 @@ begin
-- DUT
-----------------------------------------------------------------------------
u_reinterleave : entity work.dp_reinterleave
- generic map (
- g_nof_in => g_nof_in,
- g_deint_block_size => g_deint_block_size,
- g_nof_out => g_nof_out,
- g_inter_block_size => g_inter_block_size,
- g_dat_w => g_dat_w,
- g_use_complex => g_use_complex,
- g_align_out => g_align_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in_arr => snk_in_arr,
- src_out_arr => src_out_arr
- );
+ generic map (
+ g_nof_in => g_nof_in,
+ g_deint_block_size => g_deint_block_size,
+ g_nof_out => g_nof_out,
+ g_inter_block_size => g_inter_block_size,
+ g_dat_w => g_dat_w,
+ g_use_complex => g_use_complex,
+ g_align_out => g_align_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in_arr => snk_in_arr,
+ src_out_arr => src_out_arr
+ );
end rtl;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd b/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd
index f8137c37ce..4385a0ca80 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd
@@ -32,13 +32,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_repack is
generic (
@@ -222,28 +222,28 @@ begin
stimuli_src_in <= pack_src_in;
u_pack : entity work.dp_repack
- generic map (
- g_in_dat_w => g_in_dat_w,
- g_in_nof_words => g_in_nof_words,
- g_out_dat_w => g_pack_dat_w,
- g_out_nof_words => g_pack_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => stimuli_src_out.data(g_in_dat_w - 1 downto 0),
- in_val => stimuli_src_out.valid,
- in_sof => stimuli_src_out.sop,
- in_eof => stimuli_src_out.eop,
- in_sync => stimuli_src_out.sync, -- DP style sync at sof
-
- out_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
- out_val => pack_src_out.valid,
- out_sof => pack_src_out.sop,
- out_eof => pack_src_out.eop,
- sof_sync => pack_src_out.sync -- DP style sync at sof, passes on in_sync
- );
+ generic map (
+ g_in_dat_w => g_in_dat_w,
+ g_in_nof_words => g_in_nof_words,
+ g_out_dat_w => g_pack_dat_w,
+ g_out_nof_words => g_pack_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => stimuli_src_out.data(g_in_dat_w - 1 downto 0),
+ in_val => stimuli_src_out.valid,
+ in_sof => stimuli_src_out.sop,
+ in_eof => stimuli_src_out.eop,
+ in_sync => stimuli_src_out.sync, -- DP style sync at sof
+
+ out_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
+ out_val => pack_src_out.valid,
+ out_sof => pack_src_out.sop,
+ out_eof => pack_src_out.eop,
+ sof_sync => pack_src_out.sync -- DP style sync at sof, passes on in_sync
+ );
------------------------------------------------------------------------------
-- Unpack
@@ -252,28 +252,28 @@ begin
pack_src_in <= unpack_src_in;
u_unpack : entity work.dp_repack
- generic map (
- g_in_dat_w => g_pack_dat_w,
- g_in_nof_words => g_pack_nof_words,
- g_out_dat_w => g_in_dat_w,
- g_out_nof_words => g_in_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
- in_val => pack_src_out.valid,
- in_sof => pack_src_out.sop,
- in_eof => pack_src_out.eop,
- in_sync => pack_src_out.sync, -- DP style sync at sof
-
- out_dat => unpack_src_out.data(g_in_dat_w - 1 downto 0),
- out_val => unpack_src_out.valid,
- out_sof => unpack_src_out.sop,
- out_eof => unpack_src_out.eop,
- sof_sync => unpack_src_out.sync -- DP style sync at sof, passes on in_sync
- );
+ generic map (
+ g_in_dat_w => g_pack_dat_w,
+ g_in_nof_words => g_pack_nof_words,
+ g_out_dat_w => g_in_dat_w,
+ g_out_nof_words => g_in_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
+ in_val => pack_src_out.valid,
+ in_sof => pack_src_out.sop,
+ in_eof => pack_src_out.eop,
+ in_sync => pack_src_out.sync, -- DP style sync at sof
+
+ out_dat => unpack_src_out.data(g_in_dat_w - 1 downto 0),
+ out_val => unpack_src_out.valid,
+ out_sof => unpack_src_out.sop,
+ out_eof => unpack_src_out.eop,
+ sof_sync => unpack_src_out.sync -- DP style sync at sof, passes on in_sync
+ );
unpack_src_in <= verify_snk_out;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd b/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd
index 1fbc042d83..f63544f833 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd
@@ -40,13 +40,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_repack_data is
generic (
@@ -132,39 +132,39 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_data_init => c_data_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => g_in_dat_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_data_init => c_data_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => g_in_dat_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -198,65 +198,65 @@ begin
verify_last_snk_in_evt.err <= last_snk_in_evt;
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => g_in_dat_w,
- g_pkt_len => c_expected_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => g_in_dat_w,
+ g_pkt_len => c_expected_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT Pack
------------------------------------------------------------------------------
u_pack : entity work.dp_repack_data
- generic map (
- g_enable_repack_in => c_enable_repack_in,
- g_enable_repack_out => c_enable_repack_out,
- g_in_bypass => g_in_bypass,
- g_in_dat_w => g_in_dat_w,
- g_in_nof_words => g_in_nof_words,
- g_in_symbol_w => g_in_symbol_w,
- g_out_bypass => g_pack_bypass,
- g_out_dat_w => g_pack_dat_w,
- g_out_nof_words => g_pack_nof_words,
- g_out_symbol_w => g_pack_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => stimuli_src_in,
- snk_in => stimuli_src_out,
-
- src_in => pack_src_in,
- src_out => pack_src_out
- );
+ generic map (
+ g_enable_repack_in => c_enable_repack_in,
+ g_enable_repack_out => c_enable_repack_out,
+ g_in_bypass => g_in_bypass,
+ g_in_dat_w => g_in_dat_w,
+ g_in_nof_words => g_in_nof_words,
+ g_in_symbol_w => g_in_symbol_w,
+ g_out_bypass => g_pack_bypass,
+ g_out_dat_w => g_pack_dat_w,
+ g_out_nof_words => g_pack_nof_words,
+ g_out_symbol_w => g_pack_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => stimuli_src_in,
+ snk_in => stimuli_src_out,
+
+ src_in => pack_src_in,
+ src_out => pack_src_out
+ );
pack_src_out_data <= pack_src_out.data(g_pack_dat_w - 1 downto 0);
@@ -271,28 +271,28 @@ begin
gen_unpack : if c_no_unpack = false generate
u_unpack : entity work.dp_repack_data
- generic map (
- g_enable_repack_in => c_enable_repack_out,
- g_enable_repack_out => c_enable_repack_in,
- g_in_bypass => g_pack_bypass,
- g_in_dat_w => g_pack_dat_w,
- g_in_nof_words => g_pack_nof_words,
- g_in_symbol_w => g_pack_symbol_w,
- g_out_bypass => g_in_bypass,
- g_out_dat_w => g_in_dat_w,
- g_out_nof_words => g_in_nof_words,
- g_out_symbol_w => g_in_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => pack_src_in,
- snk_in => pack_src_out,
-
- src_in => unpack_src_in,
- src_out => unpack_src_out
- );
+ generic map (
+ g_enable_repack_in => c_enable_repack_out,
+ g_enable_repack_out => c_enable_repack_in,
+ g_in_bypass => g_pack_bypass,
+ g_in_dat_w => g_pack_dat_w,
+ g_in_nof_words => g_pack_nof_words,
+ g_in_symbol_w => g_pack_symbol_w,
+ g_out_bypass => g_in_bypass,
+ g_out_dat_w => g_in_dat_w,
+ g_out_nof_words => g_in_nof_words,
+ g_out_symbol_w => g_in_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => pack_src_in,
+ snk_in => pack_src_out,
+
+ src_in => unpack_src_in,
+ src_out => unpack_src_out
+ );
end generate;
unpack_src_out_data <= unpack_src_out.data(g_in_dat_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd b/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd
index 062f9d2dee..f37260a3ea 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd
@@ -32,13 +32,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_repack_legacy is
generic (
@@ -46,13 +46,13 @@ entity tb_dp_repack_legacy is
g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- specific
--- g_in_dat_w : NATURAL := 8;
--- g_in_nof_words : NATURAL := 9;
--- g_pack_dat_w : NATURAL := 24;
--- g_pack_nof_words : NATURAL := 3;
--- g_nof_repeat : NATURAL := 24;
--- g_pkt_len : NATURAL := 36; -- must be a multiple of g_in_nof_words
--- g_pkt_gap : NATURAL := 4 -- must be >= g_pack_nof_words
+ -- g_in_dat_w : NATURAL := 8;
+ -- g_in_nof_words : NATURAL := 9;
+ -- g_pack_dat_w : NATURAL := 24;
+ -- g_pack_nof_words : NATURAL := 3;
+ -- g_nof_repeat : NATURAL := 24;
+ -- g_pkt_len : NATURAL := 36; -- must be a multiple of g_in_nof_words
+ -- g_pkt_gap : NATURAL := 4 -- must be >= g_pack_nof_words
g_in_dat_w : natural := 8;
g_in_nof_words : natural := 4;
g_pack_dat_w : natural := 16;
@@ -120,39 +120,39 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_data_init => c_data_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => g_in_dat_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_data_init => c_data_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => g_in_dat_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -186,37 +186,37 @@ begin
verify_last_snk_in_evt.err <= '0';
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => g_in_dat_w,
- g_pkt_len => g_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => g_in_dat_w,
+ g_pkt_len => g_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT Pack
@@ -225,28 +225,28 @@ begin
stimuli_src_in <= pack_src_in;
u_pack : entity work.dp_repack_legacy
- generic map (
- g_in_dat_w => g_in_dat_w,
- g_in_nof_words => g_in_nof_words,
- g_out_dat_w => g_pack_dat_w,
- g_out_nof_words => g_pack_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => stimuli_src_out.data(g_in_dat_w - 1 downto 0),
- in_val => stimuli_src_out.valid,
- in_sof => stimuli_src_out.sop,
- in_eof => stimuli_src_out.eop,
- in_sync => stimuli_src_out.sync, -- DP style sync at sof
-
- out_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
- out_val => pack_src_out.valid,
- out_sof => pack_src_out.sop,
- out_eof => pack_src_out.eop,
- sof_sync => pack_src_out.sync -- DP style sync at sof, passes on in_sync
- );
+ generic map (
+ g_in_dat_w => g_in_dat_w,
+ g_in_nof_words => g_in_nof_words,
+ g_out_dat_w => g_pack_dat_w,
+ g_out_nof_words => g_pack_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => stimuli_src_out.data(g_in_dat_w - 1 downto 0),
+ in_val => stimuli_src_out.valid,
+ in_sof => stimuli_src_out.sop,
+ in_eof => stimuli_src_out.eop,
+ in_sync => stimuli_src_out.sync, -- DP style sync at sof
+
+ out_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
+ out_val => pack_src_out.valid,
+ out_sof => pack_src_out.sop,
+ out_eof => pack_src_out.eop,
+ sof_sync => pack_src_out.sync -- DP style sync at sof, passes on in_sync
+ );
------------------------------------------------------------------------------
-- DUT Unpack
@@ -255,28 +255,28 @@ begin
pack_src_in <= unpack_src_in;
u_unpack : entity work.dp_repack_legacy
- generic map (
- g_in_dat_w => g_pack_dat_w,
- g_in_nof_words => g_pack_nof_words,
- g_out_dat_w => g_in_dat_w,
- g_out_nof_words => g_in_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
- in_val => pack_src_out.valid,
- in_sof => pack_src_out.sop,
- in_eof => pack_src_out.eop,
- in_sync => pack_src_out.sync, -- DP style sync at sof
-
- out_dat => unpack_src_out.data(g_in_dat_w - 1 downto 0),
- out_val => unpack_src_out.valid,
- out_sof => unpack_src_out.sop,
- out_eof => unpack_src_out.eop,
- sof_sync => unpack_src_out.sync -- DP style sync at sof, passes on in_sync
- );
+ generic map (
+ g_in_dat_w => g_pack_dat_w,
+ g_in_nof_words => g_pack_nof_words,
+ g_out_dat_w => g_in_dat_w,
+ g_out_nof_words => g_in_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
+ in_val => pack_src_out.valid,
+ in_sof => pack_src_out.sop,
+ in_eof => pack_src_out.eop,
+ in_sync => pack_src_out.sync, -- DP style sync at sof
+
+ out_dat => unpack_src_out.data(g_in_dat_w - 1 downto 0),
+ out_val => unpack_src_out.valid,
+ out_sof => unpack_src_out.sop,
+ out_eof => unpack_src_out.eop,
+ sof_sync => unpack_src_out.sync -- DP style sync at sof, passes on in_sync
+ );
unpack_src_in <= verify_snk_out;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
index 163c4635bf..b3808c75ad 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
@@ -40,14 +40,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_reverse_n_data is
generic (
@@ -120,40 +120,40 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_flow_control => e_active, -- always active, no flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_use_complex => false,
- g_data_init => c_data_init,
- g_re_init => c_re_init,
- g_im_init => c_im_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => c_data_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => c_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => c_dp_siso_rdy,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_flow_control => e_active, -- always active, no flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_use_complex => false,
+ g_data_init => c_data_init,
+ g_re_init => c_re_init,
+ g_im_init => c_im_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => c_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => c_dp_siso_rdy,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -183,34 +183,34 @@ begin
verify_last_snk_in_evt.err <= last_snk_in_evt;
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_flow_control => e_active, -- always active, no flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => c_data_w,
- g_pkt_len => c_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => OPEN,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_flow_control => e_active, -- always active, no flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_pkt_len => c_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => OPEN,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT: Using dp_reverse_n_data
@@ -222,37 +222,37 @@ begin
-- Reverse
u_reverse : entity work.dp_reverse_n_data
- generic map (
- g_pipeline_demux_in => g_pipeline,
- g_pipeline_demux_out => 0,
- g_pipeline_mux_in => 0,
- g_pipeline_mux_out => g_pipeline,
- g_reverse_len => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => stimuli_src_out,
- src_out => reverse_src_out
- );
+ generic map (
+ g_pipeline_demux_in => g_pipeline,
+ g_pipeline_demux_out => 0,
+ g_pipeline_mux_in => 0,
+ g_pipeline_mux_out => g_pipeline,
+ g_reverse_len => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => stimuli_src_out,
+ src_out => reverse_src_out
+ );
-- Reverse again to unreverse
u_unreverse : entity work.dp_reverse_n_data
- generic map (
- g_pipeline_demux_in => g_pipeline,
- g_pipeline_demux_out => 0,
- g_pipeline_mux_in => 0,
- g_pipeline_mux_out => g_pipeline,
- g_reverse_len => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => reverse_src_out,
- src_out => verify_snk_in
- );
+ generic map (
+ g_pipeline_demux_in => g_pipeline,
+ g_pipeline_demux_out => 0,
+ g_pipeline_mux_in => 0,
+ g_pipeline_mux_out => g_pipeline,
+ g_reverse_len => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => reverse_src_out,
+ src_out => verify_snk_in
+ );
------------------------------------------------------------------------------
-- DUT: Using dp_reverse_n_data_fc, but with c_dp_siso_rdy so no flow control
@@ -260,33 +260,33 @@ begin
-- Reverse
u_reverse_fc : entity work.dp_reverse_n_data_fc
- generic map (
- g_pipeline_in => g_pipeline,
- g_pipeline_out => g_pipeline,
- g_reverse_len => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => stimuli_src_out,
- src_out => reverse_fc_src_out
- );
+ generic map (
+ g_pipeline_in => g_pipeline,
+ g_pipeline_out => g_pipeline,
+ g_reverse_len => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => stimuli_src_out,
+ src_out => reverse_fc_src_out
+ );
-- Reverse again to unreverse
u_unreverse_fc : entity work.dp_reverse_n_data_fc
- generic map (
- g_pipeline_in => g_pipeline,
- g_pipeline_out => g_pipeline,
- g_reverse_len => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => reverse_fc_src_out,
- src_out => verify_fc_snk_in
- );
+ generic map (
+ g_pipeline_in => g_pipeline,
+ g_pipeline_out => g_pipeline,
+ g_reverse_len => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => reverse_fc_src_out,
+ src_out => verify_fc_snk_in
+ );
-- Verify that dp_reverse_n_data_fc is equivalent to dp_reverse_n_data, when
-- no flow control is used.
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd
index 5d89c3ab55..2c43780345 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd
@@ -36,14 +36,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_reverse_n_data_fc is
generic (
@@ -79,9 +79,10 @@ architecture tb of tb_dp_reverse_n_data_fc is
constant c_flow_control_latency_pls : natural := g_nof_repeat * c_pkt_len * (c_verify_pulse_period * c_stimuli_pulse_period) / (c_stimuli_pulse_active * c_verify_pulse_active);
constant c_flow_control_latency_rnd : natural := g_nof_repeat * c_pkt_len;
- constant c_flow_control_latency : natural := sel_a_b(g_flow_control_stimuli = e_pulse or g_flow_control_verify = e_pulse,
- c_flow_control_latency_pls,
- c_flow_control_latency_rnd); -- worst case value
+ constant c_flow_control_latency : natural := sel_a_b(
+ g_flow_control_stimuli = e_pulse or g_flow_control_verify = e_pulse,
+ c_flow_control_latency_pls,
+ c_flow_control_latency_rnd); -- worst case value
constant c_data_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
constant c_dsp_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
@@ -123,43 +124,43 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_use_complex => false,
- g_data_init => c_data_init,
- g_re_init => c_re_init,
- g_im_init => c_im_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => c_data_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => c_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_use_complex => false,
+ g_data_init => c_data_init,
+ g_re_init => c_re_init,
+ g_im_init => c_im_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => c_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -189,37 +190,37 @@ begin
verify_last_snk_in_evt.err <= last_snk_in_evt;
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => c_data_w,
- g_pkt_len => c_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_pkt_len => c_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT
@@ -227,37 +228,37 @@ begin
-- Reverse
u_reverse_fc : entity work.dp_reverse_n_data_fc
- generic map (
- g_pipeline_in => g_pipeline,
- g_pipeline_out => g_pipeline,
- g_reverse_len => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => stimuli_src_in,
- snk_in => stimuli_src_out,
- src_in => reverse_src_in,
- src_out => reverse_src_out
- );
+ generic map (
+ g_pipeline_in => g_pipeline,
+ g_pipeline_out => g_pipeline,
+ g_reverse_len => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => stimuli_src_in,
+ snk_in => stimuli_src_out,
+ src_in => reverse_src_in,
+ src_out => reverse_src_out
+ );
-- Reverse again to unreverse
u_unreverse_fc : entity work.dp_reverse_n_data_fc
- generic map (
- g_pipeline_in => g_pipeline,
- g_pipeline_out => g_pipeline,
- g_reverse_len => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => reverse_src_in,
- snk_in => reverse_src_out,
- src_in => verify_snk_out,
- src_out => verify_snk_in
- );
+ generic map (
+ g_pipeline_in => g_pipeline,
+ g_pipeline_out => g_pipeline,
+ g_reverse_len => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => reverse_src_in,
+ snk_in => reverse_src_out,
+ src_in => verify_snk_out,
+ src_out => verify_snk_in
+ );
------------------------------------------------------------------------------
-- Auxiliary
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
index 2079df7627..d2ea7a2e44 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
@@ -30,12 +30,12 @@
-- needed
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_rsn_source is
generic (
@@ -324,17 +324,17 @@ begin
-- Verify sync at sop and at expected_sync
proc_dp_verify_sync(exp_rs_start_bsn,
- g_pps_interval,
- g_rs_block_size,
- true, -- use BSN as RSN
- clk,
- verify_en,
- rs_sosi.sync,
- rs_sosi.sop,
- rs_sosi.bsn,
- dbg_nof_blk,
- dbg_accumulate,
- dbg_expected_bsn);
+ g_pps_interval,
+ g_rs_block_size,
+ true, -- use BSN as RSN
+ clk,
+ verify_en,
+ rs_sosi.sync,
+ rs_sosi.sop,
+ rs_sosi.bsn,
+ dbg_nof_blk,
+ dbg_accumulate,
+ dbg_expected_bsn);
-- Verify rs_sosi by comparing with exp_grid_rs, this again verifies rs_sosi.sync, sop and bsn
p_verify_rs_sosi_grid : process(clk)
@@ -390,48 +390,48 @@ begin
-----------------------------------------------------------------------------
u_bsn : entity work.dp_bsn_source_v2
- generic map (
- g_block_size => g_bs_block_size,
- g_nof_clk_per_sync => g_pps_interval,
- g_bsn_w => c_bsn_w,
- g_bsn_time_offset_w => c_bsn_time_offset_w
- )
- port map (
- rst => rst,
- clk => clk,
- pps => ref_grid_bs.pps,
- -- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
-
- dp_on_status => dp_on_status, -- = src_out.valid
- bs_restart => bs_restart, -- = src_out.sync for first sync after dp_on went high
- bs_new_interval => bs_new_interval, -- active during first src_out.sync interval
-
- bsn_init => bsn_init,
- bsn_time_offset => bsn_time_offset,
-
- -- Streaming
- src_out => bs_sosi
- );
+ generic map (
+ g_block_size => g_bs_block_size,
+ g_nof_clk_per_sync => g_pps_interval,
+ g_bsn_w => c_bsn_w,
+ g_bsn_time_offset_w => c_bsn_time_offset_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pps => ref_grid_bs.pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+
+ dp_on_status => dp_on_status, -- = src_out.valid
+ bs_restart => bs_restart, -- = src_out.sync for first sync after dp_on went high
+ bs_new_interval => bs_new_interval, -- active during first src_out.sync interval
+
+ bsn_init => bsn_init,
+ bsn_time_offset => bsn_time_offset,
+
+ -- Streaming
+ src_out => bs_sosi
+ );
u_rsn : entity work.dp_rsn_source
- generic map (
- g_bs_block_size => g_bs_block_size,
- g_rs_block_size => g_rs_block_size,
- g_nof_clk_per_sync => g_pps_interval,
- g_bsn_w => c_bsn_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Input stream sosi control using BSN
- bs_sosi => bs_sosi, -- input reference stream using BSN
-
- -- Output stream sosi control using RSN
- rs_sosi => rs_sosi, -- output stream using RSN and g_rs_block_size, g_nof_clk_per_sync
- rs_restart => rs_restart, -- = rs_sosi.sync for first sync after bs_sosi.valid went high
- rs_new_interval => rs_new_interval -- = active during first rs_sosi.sync interval
- );
+ generic map (
+ g_bs_block_size => g_bs_block_size,
+ g_rs_block_size => g_rs_block_size,
+ g_nof_clk_per_sync => g_pps_interval,
+ g_bsn_w => c_bsn_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Input stream sosi control using BSN
+ bs_sosi => bs_sosi, -- input reference stream using BSN
+
+ -- Output stream sosi control using RSN
+ rs_sosi => rs_sosi, -- output stream using RSN and g_rs_block_size, g_nof_clk_per_sync
+ rs_restart => rs_restart, -- = rs_sosi.sync for first sync after bs_sosi.valid went high
+ rs_new_interval => rs_new_interval -- = active during first rs_sosi.sync interval
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
index 2801b29fc2..c31a2dd744 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
@@ -37,15 +37,15 @@
-- Remarks:
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_selector_arr is
generic (
@@ -181,59 +181,59 @@ begin
-- DUT that selects pipe_sosi_arr
u_dut_pipe : entity work.dp_selector_arr
- generic map(
- g_nof_arr => c_nof_streams,
- g_pipeline => 1
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => rst,
- mm_clk => clk,
-
- reg_selector_mosi => mm_mosi_pipe,
- reg_selector_miso => OPEN,
-
- -- Streaming clock domain
- dp_rst => rst,
- dp_clk => clk,
-
- -- ST sinks
- pipe_sosi_arr => pipe_sosi_arr,
- ref_sosi_arr => ref_sosi_arr,
- -- ST source
- out_sosi_arr => out_pipe_sosi_arr
- );
+ generic map(
+ g_nof_arr => c_nof_streams,
+ g_pipeline => 1
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => rst,
+ mm_clk => clk,
+
+ reg_selector_mosi => mm_mosi_pipe,
+ reg_selector_miso => OPEN,
+
+ -- Streaming clock domain
+ dp_rst => rst,
+ dp_clk => clk,
+
+ -- ST sinks
+ pipe_sosi_arr => pipe_sosi_arr,
+ ref_sosi_arr => ref_sosi_arr,
+ -- ST source
+ out_sosi_arr => out_pipe_sosi_arr
+ );
-- DUT that selects ref_sosi_arr
u_dut_ref : entity work.dp_selector_arr
- generic map(
- g_nof_arr => c_nof_streams,
- g_pipeline => 1
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => rst,
- mm_clk => clk,
-
- reg_selector_mosi => mm_mosi_ref,
- reg_selector_miso => OPEN,
-
- -- Streaming clock domain
- dp_rst => rst,
- dp_clk => clk,
-
- -- ST sinks
- pipe_sosi_arr => pipe_sosi_arr,
- ref_sosi_arr => ref_sosi_arr,
- -- ST source
- out_sosi_arr => out_ref_sosi_arr
- );
+ generic map(
+ g_nof_arr => c_nof_streams,
+ g_pipeline => 1
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => rst,
+ mm_clk => clk,
+
+ reg_selector_mosi => mm_mosi_ref,
+ reg_selector_miso => OPEN,
+
+ -- Streaming clock domain
+ dp_rst => rst,
+ dp_clk => clk,
+
+ -- ST sinks
+ pipe_sosi_arr => pipe_sosi_arr,
+ ref_sosi_arr => ref_sosi_arr,
+ -- ST source
+ out_sosi_arr => out_ref_sosi_arr
+ );
p_stim: process
begin
- wait until rst = '0';
- proc_mem_mm_bus_wr(0, x"0", clk, mm_mosi_ref); -- select ref_sosi_arr on dut_ref
- proc_mem_mm_bus_wr(0, x"1", clk, mm_mosi_pipe); -- select pipe_sosi_arr on dut_pipe
- wait;
- end process;
+ wait until rst = '0';
+ proc_mem_mm_bus_wr(0, x"0", clk, mm_mosi_ref); -- select ref_sosi_arr on dut_ref
+ proc_mem_mm_bus_wr(0, x"1", clk, mm_mosi_pipe); -- select pipe_sosi_arr on dut_pipe
+ wait;
+ end process;
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd b/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd
index dfa71d0f18..dcf4288546 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd
@@ -32,15 +32,15 @@
--
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_shiftram is
generic (
@@ -150,7 +150,7 @@ begin
begin
state <= 0;
reg_mosi <= c_mem_mosi_rst;
- proc_common_wait_some_cycles(mm_clk, 10);
+ proc_common_wait_some_cycles(mm_clk, 10);
proc_mem_mm_bus_wr( 0, c_half_nof_words, mm_clk, reg_mosi);
proc_common_wait_some_cycles(mm_clk, 12);
state <= 1;
@@ -184,28 +184,28 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dut: entity work.dp_shiftram
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_words => g_nof_words,
- g_data_w => g_data_w,
- g_use_sync_in => g_use_sync_in
-
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sync_in => sync_in,
-
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- Streaming sink
- snk_in_arr => ref_sosi_arr,
- -- Streaming source
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_words => g_nof_words,
+ g_data_w => g_data_w,
+ g_use_sync_in => g_use_sync_in
+
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sync_in => sync_in,
+
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- Streaming sink
+ snk_in_arr => ref_sosi_arr,
+ -- Streaming source
+ src_out_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd b/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
index 1d249b0aa1..76902eb875 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_shiftreg is
end tb_dp_shiftreg;
@@ -145,23 +145,23 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_shiftreg
- generic map (
- g_output_reg => c_dut_output_reg,
- g_flush_eop => c_dut_flush_eop,
- g_modify_support => c_modify_support,
- g_nof_words => c_dut_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- -- Control shift register contents
- cur_shiftreg_inputs => cur_shiftreg_inputs,
- new_shiftreg_inputs => new_shiftreg_inputs,
- -- ST source
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_output_reg => c_dut_output_reg,
+ g_flush_eop => c_dut_flush_eop,
+ g_modify_support => c_modify_support,
+ g_nof_words => c_dut_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ -- Control shift register contents
+ cur_shiftreg_inputs => cur_shiftreg_inputs,
+ new_shiftreg_inputs => new_shiftreg_inputs,
+ -- ST source
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_split.vhd b/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
index 47278fc5b0..c63ebc0cae 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
--- run 300 us
+ -- run 300 us
entity tb_dp_split is
generic (
g_data_w : natural := 64; -- g_data_w/g_symbol_w must be an integer
g_symbol_w : natural := 16; -- use sufficient width to avoid wrap in proc_dp_gen_frame()
- -- use symbols width that contains whole nibbles (4-bit) to easy debugging in HEX
+ -- use symbols width that contains whole nibbles (4-bit) to easy debugging in HEX
g_nof_symbols_max : natural := 50; -- maximum supported frame size
g_random_control : boolean := false -- use TRUE for random snk_in.valid and src_in.ready control
);
@@ -108,8 +108,8 @@ begin
-- frames
vINIT := 0;
--- FOR vLEN IN 3 TO 3 LOOP
--- FOR vNOF IN 1 TO 1 LOOP --vLEN+c_nof_symbols_per_data LOOP
+ -- FOR vLEN IN 3 TO 3 LOOP
+ -- FOR vNOF IN 1 TO 1 LOOP --vLEN+c_nof_symbols_per_data LOOP
for vLEN in 1 to g_nof_symbols_max loop
for vNOF in 0 to vLEN + c_nof_symbols_per_data loop
nof_symbols <= TO_UVEC(vNOF, c_nof_symbols_w);
@@ -137,20 +137,20 @@ begin
end process;
dut : entity work.dp_split
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => g_nof_symbols_max
- )
- port map (
- rst => rst,
- clk => clk,
- nof_symbols => nof_symbols,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- src_in_arr => out_siso, -- IN = request from downstream ST sink
- src_out_arr => out_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => g_nof_symbols_max
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ nof_symbols => nof_symbols,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ src_in_arr => out_siso, -- IN = request from downstream ST sink
+ src_out_arr => out_sosi
+ );
-- Output verify
-- Note that verify per frame can only verify frames that are longer than 1 data word
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd b/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
index 55c713be62..e0c446159c 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
@@ -32,15 +32,15 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_components_pkg.all;
entity tb_dp_strobe_total_count is
generic (
@@ -110,22 +110,22 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => g_nof_blocks_per_sync * c_tb_nof_sync,
- g_pkt_len => g_nof_valid_per_blk,
- g_pkt_gap => g_gap_size
- )
- port map (
- rst => stimuli_rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => g_nof_blocks_per_sync * c_tb_nof_sync,
+ g_pkt_len => g_nof_valid_per_blk,
+ g_pkt_gap => g_gap_size
+ )
+ port map (
+ rst => stimuli_rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
stimuli_strobe_arr(0) <= stimuli_sosi.sync;
stimuli_strobe_arr(1) <= stimuli_sosi.sop;
@@ -135,25 +135,25 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dut : entity work.dp_strobe_total_count
- generic map (
- g_mm_w => g_mm_w,
- g_nof_counts => c_nof_counts,
- g_count_w => g_count_w,
- g_clip => c_clip
- )
- port map (
- dp_rst => rst,
- dp_clk => dp_clk,
-
- ref_sync => stimuli_sosi.sync,
- in_strobe_arr => stimuli_strobe_arr,
-
- mm_rst => rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_mosi,
- reg_miso => reg_miso
- );
+ generic map (
+ g_mm_w => g_mm_w,
+ g_nof_counts => c_nof_counts,
+ g_count_w => g_count_w,
+ g_clip => c_clip
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ ref_sync => stimuli_sosi.sync,
+ in_strobe_arr => stimuli_strobe_arr,
+
+ mm_rst => rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso
+ );
------------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
index 22cf16f4c6..9ad0cb4bbc 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
@@ -35,13 +35,13 @@
-- . the tb is self checking
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_sync_checker is
generic (
@@ -251,19 +251,19 @@ begin
-- DUT function
dut : entity work.dp_sync_checker
- generic map (
- g_nof_blk_per_sync => g_nof_blk_per_sync
- )
- port map (
- dp_rst => rst,
- dp_clk => clk,
- snk_out => dut_snk_out,
- snk_in => dut_snk_in,
- src_in => dut_src_in,
- src_out => dut_src_out,
- nof_early_syncs => dut_nof_early_syncs,
- nof_late_syncs => dut_nof_late_syncs
- );
+ generic map (
+ g_nof_blk_per_sync => g_nof_blk_per_sync
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => clk,
+ snk_out => dut_snk_out,
+ snk_in => dut_snk_in,
+ src_in => dut_src_in,
+ src_out => dut_src_out,
+ nof_early_syncs => dut_nof_early_syncs,
+ nof_late_syncs => dut_nof_late_syncs
+ );
-- Connect DUT source output stream to verification
dut_src_in <= verify_snk_out;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
index d11d579d64..39c45725cd 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
@@ -32,13 +32,13 @@
-- proc_dp_verify_bsn().
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_sync_insert is
generic (
@@ -148,18 +148,18 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dut: entity work.dp_sync_insert
- generic map (
- g_nof_data_per_blk => g_nof_data_per_block,
- g_nof_blk_per_sync => g_nof_blk_per_sync
- )
- port map (
- rst => rst,
- clk => clk,
- -- Streaming sink
- snk_in => ref_sosi,
- -- Streaming source
- src_out => out_sosi
- );
+ generic map (
+ g_nof_data_per_blk => g_nof_data_per_block,
+ g_nof_blk_per_sync => g_nof_blk_per_sync
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Streaming sink
+ snk_in => ref_sosi,
+ -- Streaming source
+ src_out => out_sosi
+ );
------------------------------------------------------------------------------
-- Verification
@@ -185,8 +185,8 @@ begin
-- Verify output global and local bsn
proc_dp_verify_bsn(true, 1, c_nof_replicated_sync, g_nof_blk_per_sync,
- clk, out_sosi.sync, out_sosi.sop, out_sosi.bsn,
- verify_bsn_en, cnt_replicated_global_bsn, prev_out_sosi_global.bsn, prev_out_sosi_local.bsn);
+ clk, out_sosi.sync, out_sosi.sop, out_sosi.bsn,
+ verify_bsn_en, cnt_replicated_global_bsn, prev_out_sosi_global.bsn, prev_out_sosi_local.bsn);
-- Verify output packet ctrl
proc_dp_verify_sop_and_eop(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, out_hold_sop);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
index 481331ffe8..bbe0862896 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
@@ -35,14 +35,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_sync_insert_v2 is
generic (
@@ -165,25 +165,25 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dut: entity work.dp_sync_insert_v2
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_blk_per_sync => g_nof_blk_per_sync,
- g_nof_blk_per_sync_min => g_nof_blk_per_sync_min
- )
- port map (
- mm_rst => rst,
- mm_clk => mm_clk,
- dp_rst => rst,
- dp_clk => dp_clk,
-
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- Streaming sink
- in_sosi_arr => ref_sosi_arr,
- -- Streaming source
- out_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_blk_per_sync => g_nof_blk_per_sync,
+ g_nof_blk_per_sync_min => g_nof_blk_per_sync_min
+ )
+ port map (
+ mm_rst => rst,
+ mm_clk => mm_clk,
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- Streaming sink
+ in_sosi_arr => ref_sosi_arr,
+ -- Streaming source
+ out_sosi_arr => out_sosi_arr
+ );
------------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
index 3ec876e8a3..3059e674dd 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
@@ -35,14 +35,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_sync_recover is
generic (
@@ -85,7 +85,7 @@ begin
------------------------------------------------------------------------------
p_stimuli : process
- variable v_bsn : natural;
+ variable v_bsn : natural;
begin
proc_common_wait_until_low(dp_clk, rst);
proc_common_wait_some_cycles(dp_clk, 5);
@@ -170,20 +170,20 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dut: entity work.dp_sync_recover
- generic map (
- g_nof_data_per_block => g_nof_data_per_block
- )
- port map (
- dp_rst => rst,
- dp_clk => dp_clk,
-
- -- Streaming sink
- in_sosi => ref_sosi,
- recover_val => dly_ref_sosi_arr(g_dut_latency).valid,
- restart => restart,
- -- Streaming source
- out_sosi => out_sosi
- );
+ generic map (
+ g_nof_data_per_block => g_nof_data_per_block
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ -- Streaming sink
+ in_sosi => ref_sosi,
+ recover_val => dly_ref_sosi_arr(g_dut_latency).valid,
+ restart => restart,
+ -- Streaming source
+ out_sosi => out_sosi
+ );
------------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd b/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd
index 7f85cf3f48..3fe4916d86 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_tail_remove is
generic (
@@ -71,11 +71,11 @@ begin
wait for 10 * c_clk_period;
wait until rising_edge(clk);
- for i in 0 to c_nof_frames loop
- proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, v_symbol_init, c_nof_symbols_per_frame, v_bsn, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0));
- v_symbol_init := v_symbol_init + c_nof_symbols_per_frame;
- v_bsn := v_bsn + 1;
- end loop;
+ for i in 0 to c_nof_frames loop
+ proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, v_symbol_init, c_nof_symbols_per_frame, v_bsn, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0));
+ v_symbol_init := v_symbol_init + c_nof_symbols_per_frame;
+ v_bsn := v_bsn + 1;
+ end loop;
wait;
end process;
@@ -87,11 +87,11 @@ begin
wait for 15 * c_clk_period;
wait until rising_edge(clk);
- for i in 0 to c_nof_frames loop
- proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, v_symbol_init, c_nof_symbols_per_tail, v_bsn, '0', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1));
- v_symbol_init := v_symbol_init + c_nof_symbols_per_tail;
- v_bsn := v_bsn + 1;
- end loop;
+ for i in 0 to c_nof_frames loop
+ proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, v_symbol_init, c_nof_symbols_per_tail, v_bsn, '0', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1));
+ v_symbol_init := v_symbol_init + c_nof_symbols_per_tail;
+ v_bsn := v_bsn + 1;
+ end loop;
-- As the tail frame will allways be last we can end the TB here:
tb_end <= '1';
@@ -101,34 +101,34 @@ begin
-- Concatenate the two streams so we can remove stream 1 (='tail')
u_dp_concat : entity work.dp_concat
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- src_in => concat_siso,
- src_out => concat_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ src_in => concat_siso,
+ src_out => concat_sosi
+ );
-- Now feed the concatenated streams into dp_tail_remove to remove the tail
u_dp_tail_remove : entity work.dp_tail_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => c_nof_symbols_per_tail
- )
- port map (
- st_rst => rst,
- st_clk => clk,
-
- snk_out => concat_siso,
- snk_in => concat_sosi,
-
- src_in => detailed_siso,
- src_out => detailed_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => c_nof_symbols_per_tail
+ )
+ port map (
+ st_rst => rst,
+ st_clk => clk,
+
+ snk_out => concat_siso,
+ snk_in => concat_sosi,
+
+ src_in => detailed_siso,
+ src_out => detailed_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_throttle_sop.vhd b/libraries/base/dp/tb/vhdl/tb_dp_throttle_sop.vhd
index 13cc297acc..06505b1ced 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_throttle_sop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_throttle_sop.vhd
@@ -29,11 +29,11 @@
-- without throttling as the minimum of c_period is met.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_throttle_sop is
end tb_dp_throttle_sop;
@@ -91,36 +91,36 @@ begin
-- FIFO acts as sink that dp_throttle_sop provides a constant flow for
-----------------------------------------------------------------------------
u_dp_fifo_sc : entity work.dp_fifo_sc
- generic map (
- g_data_w => c_gen_data_w,
- g_use_bsn => false,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_sync => false,
- g_use_ctrl => true,
- g_fifo_size => 100
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => gen_src_in,
- snk_in => gen_src_out,
- src_in => fifo_src_in,
- src_out => fifo_src_out
- );
+ generic map (
+ g_data_w => c_gen_data_w,
+ g_use_bsn => false,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_sync => false,
+ g_use_ctrl => true,
+ g_fifo_size => 100
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => gen_src_in,
+ snk_in => gen_src_out,
+ src_in => fifo_src_in,
+ src_out => fifo_src_out
+ );
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
u_dp_throttle_sop : entity work.dp_throttle_sop
- generic map (
- g_period => c_period
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => fifo_src_in,
- snk_in => fifo_src_out
- );
+ generic map (
+ g_period => c_period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => fifo_src_in,
+ snk_in => fifo_src_out
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd b/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
index f9587df95d..6d81047af1 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
@@ -32,13 +32,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_throttle_xon is
generic (
@@ -168,8 +168,8 @@ begin
-- Verify incrementing global BSN
proc_dp_verify_bsn(false, 1, 1, g_nof_block_per_sync,
- clk, verify_snk_in.sync, verify_snk_in.sop, verify_snk_in.bsn,
- verify_en_bsn, cnt_replicated_global_bsn, prev_out_bsn_global, prev_out_bsn_local);
+ clk, verify_snk_in.sync, verify_snk_in.sop, verify_snk_in.bsn,
+ verify_en_bsn, cnt_replicated_global_bsn, prev_out_bsn_global, prev_out_bsn_local);
p_verify_xonxoff : process(clk)
begin
@@ -211,20 +211,20 @@ begin
------------------------------------------------------------------------------
u_dut : entity work.dp_throttle_xon
- generic map (
- g_restart_at_sync => g_restart_at_sync,
- g_block_size => g_block_size,
- g_nof_block_on => g_nof_block_on,
- g_nof_clk_off => c_nof_clk_off
- )
- port map (
- rst => rst,
- clk => clk,
- -- Frame in
- snk_out => stimuli_src_in,
- snk_in => stimuli_src_out,
- -- Frame out
- src_in => verify_snk_out, -- flush control via out_siso.xon
- src_out => verify_snk_in
- );
+ generic map (
+ g_restart_at_sync => g_restart_at_sync,
+ g_block_size => g_block_size,
+ g_nof_block_on => g_nof_block_on,
+ g_nof_clk_off => c_nof_clk_off
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Frame in
+ snk_out => stimuli_src_in,
+ snk_in => stimuli_src_out,
+ -- Frame out
+ src_in => verify_snk_out, -- flush control via out_siso.xon
+ src_out => verify_snk_in
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
index bd86e59c73..4fcd1a28d4 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
@@ -52,13 +52,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_xonoff is
generic (
@@ -277,16 +277,16 @@ begin
-- DUT function
gen_dut : for I in 0 to g_nof_dut - 1 generate
u_dut : entity work.dp_xonoff
- port map (
- rst => rst,
- clk => clk,
- -- Frame in
- in_siso => dut_siso_arr(I - 1),
- in_sosi => dut_sosi_arr(I - 1),
- -- Frame out
- out_siso => dut_siso_arr(I), -- flush control via out_siso.xon
- out_sosi => dut_sosi_arr(I)
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Frame in
+ in_siso => dut_siso_arr(I - 1),
+ in_sosi => dut_sosi_arr(I - 1),
+ -- Frame out
+ out_siso => dut_siso_arr(I), -- flush control via out_siso.xon
+ out_sosi => dut_sosi_arr(I)
+ );
end generate;
-- Connect DUT source output stream to verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd b/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
index 46d08b2d87..0a3e807645 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
@@ -26,11 +26,11 @@
-- > run -all
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_dp_xonoff_reg_timeout is
end tb_dp_xonoff_reg_timeout;
@@ -94,19 +94,19 @@ begin
end process;
u_dut : entity work.dp_xonoff_reg_timeout
- generic map (
- g_mm_timeout => 1,
- g_sim => true
- )
- port map (
- mm_rst => rst,
- mm_clk => clk,
- st_rst => rst,
- st_clk => st_clk,
+ generic map (
+ g_mm_timeout => 1,
+ g_sim => true
+ )
+ port map (
+ mm_rst => rst,
+ mm_clk => clk,
+ st_rst => rst,
+ st_clk => st_clk,
- sla_in => sla_in_mosi,
- sla_out => sla_out_miso,
+ sla_in => sla_in_mosi,
+ sla_out => sla_out_miso,
- xonoff_reg => xonoff_reg
- );
+ xonoff_reg => xonoff_reg
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
index 20d75a9e96..ccceba7f7c 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
@@ -26,15 +26,15 @@
-- . View *_64 BSN values as radix hex in Wave window to recognize BSN hi word.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_mmp_dp_bsn_sync_scheduler is
end tb_mmp_dp_bsn_sync_scheduler;
@@ -365,52 +365,52 @@ begin
-- Generate data blocks with input sync
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => c_nof_block_per_input_sync,
- g_err_init => 0,
- g_err_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
- g_channel_init => 0,
- g_channel_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
- g_nof_repeat => c_sim_nof_blocks,
- g_pkt_len => c_block_size,
- g_pkt_gap => c_input_gap_size
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => c_nof_block_per_input_sync,
+ g_err_init => 0,
+ g_err_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
+ g_channel_init => 0,
+ g_channel_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
+ g_nof_repeat => c_sim_nof_blocks,
+ g_pkt_len => c_block_size,
+ g_pkt_gap => c_input_gap_size
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_mmp_dp_bsn_sync_scheduler : entity work.mmp_dp_bsn_sync_scheduler
- generic map (
- g_bsn_w => c_bsn_w,
- g_block_size => c_block_size,
- g_ctrl_interval_size_min => c_ctrl_interval_size_min
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM control
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- Streaming
- in_sosi => in_sosi,
- out_sosi => out_sosi,
- out_start => out_start,
- out_enable => out_enable
- );
+ generic map (
+ g_bsn_w => c_bsn_w,
+ g_block_size => c_block_size,
+ g_ctrl_interval_size_min => c_ctrl_interval_size_min
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM control
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- Streaming
+ in_sosi => in_sosi,
+ out_sosi => out_sosi,
+ out_start => out_start,
+ out_enable => out_enable
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
index ad32c92176..2310c5ba14 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
@@ -33,15 +33,15 @@
-- automatically.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_mms_dp_bsn_align is
generic (
@@ -295,7 +295,7 @@ begin
verify_dis_arr <= (others => '0');
proc_common_wait_some_cycles(clk, 1000);
--- verify_dis_arr <= (OTHERS=>'1');
+ -- verify_dis_arr <= (OTHERS=>'1');
-- . enforce large BSN misalignment
tb_state <= s_large_bsn_diff;
@@ -304,8 +304,8 @@ begin
proc_common_wait_until_high(clk, bsn_event_ack);
bsn_event <= '0';
-- expect no output, because difference remains too large, so do not restart verify_en here and leave it commented:
--- proc_common_wait_some_cycles(clk, 100);
--- verify_dis_arr <= (OTHERS=>'0');
+ -- proc_common_wait_some_cycles(clk, 100);
+ -- verify_dis_arr <= (OTHERS=>'0');
proc_common_wait_some_cycles(clk, 1000);
verify_dis_arr <= (others => '1');
@@ -326,10 +326,10 @@ begin
tb_state <= s_disable_one_input;
verify_dis_arr <= (others => '1');
--- in_en_event <= '1';
+ -- in_en_event <= '1';
in_en_arr(c_event_input) <= '0'; -- switch an input off
--- proc_common_wait_some_cycles(clk, 1);
--- in_en_event <= '0';
+ -- proc_common_wait_some_cycles(clk, 1);
+ -- in_en_event <= '0';
proc_common_wait_some_cycles(mm_clk, 1);
proc_mem_mm_bus_wr(c_event_input, x"0", mm_clk, mm_mosi);
@@ -340,10 +340,10 @@ begin
tb_state <= s_enable_inputs;
verify_dis_arr <= (others => '1');
--- in_en_event <= '1';
+ -- in_en_event <= '1';
in_en_arr(c_event_input) <= '1'; -- switch this input on
--- proc_common_wait_some_cycles(clk, 1);
--- in_en_event <= '0';
+ -- proc_common_wait_some_cycles(clk, 1);
+ -- in_en_event <= '0';
proc_common_wait_some_cycles(mm_clk, 1);
proc_mem_mm_bus_wr(c_event_input, x"1", mm_clk, mm_mosi);
@@ -422,29 +422,29 @@ begin
-- DUT
------------------------------------------------------------------------------
u_mms_bsn_align : entity work.mms_dp_bsn_align
- generic map (
- g_block_size => g_block_size,
- g_nof_input => g_nof_input,
- g_xoff_timeout => c_xoff_timeout,
- g_sop_timeout => c_sop_timeout,
- g_bsn_latency => g_bsn_latency,
- g_bsn_request_pipeline => g_bsn_request_pipeline,
- g_cross_clock_domain => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => mm_mosi,
- reg_miso => mm_miso,
- -- Streaming clock domain
- dp_rst => rst,
- dp_clk => clk,
- -- ST sinks
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ g_block_size => g_block_size,
+ g_nof_input => g_nof_input,
+ g_xoff_timeout => c_xoff_timeout,
+ g_sop_timeout => c_sop_timeout,
+ g_bsn_latency => g_bsn_latency,
+ g_bsn_request_pipeline => g_bsn_request_pipeline,
+ g_cross_clock_domain => true
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => mm_mosi,
+ reg_miso => mm_miso,
+ -- Streaming clock domain
+ dp_rst => rst,
+ dp_clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
index 13cb45b509..55f6185d99 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
@@ -30,14 +30,14 @@
-- > view expanded bs_sosi in Wave window
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_mms_dp_bsn_source is
end tb_mms_dp_bsn_source;
@@ -83,97 +83,97 @@ begin
p_mm_stimuli : process
begin
- wait until rst = '0';
- proc_common_wait_some_cycles(clk, 10);
-
- -- Write initial BSN and number of block per sync interval
- proc_mem_mm_bus_wr(c_mm_addr_bsn_lo, c_init_bsn, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_wr(c_mm_addr_bsn_hi, 0, clk, mm_miso, mm_mosi); -- must also write hi part to trigger transfer accross clock domain
- proc_mem_mm_bus_wr(c_mm_addr_nof_block_per_sync, c_nof_block_per_sync, clk, mm_miso, mm_mosi);
- proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
-
- --------------------------------------------------------------------------
- -- DP on immediate
- --------------------------------------------------------------------------
-
- -- Wait until after PPS
- proc_common_wait_until_hi_lo(clk, pps);
-
- -- Write DP on immediate
- proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_on_immediate, clk, mm_miso, mm_mosi);
- proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
-
- -- Read dp on status
- proc_mem_mm_bus_rd(c_mm_addr_dp_on, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
- proc_common_wait_some_cycles(clk, 1);
- assert mm_dp_on_status = c_mm_dp_on_immediate report "Wrong DP on status, expected DP on immediate." severity ERROR;
-
- -- Read BSN twice in same PPS interval
- proc_common_wait_some_cycles(clk, 3 * c_block_size);
-
- proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_bsn(c_word_w - 1 downto 0) <= mm_miso.rddata(c_word_w - 1 downto 0);
- proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_bsn(2 * c_word_w - 1 downto c_word_w) <= mm_miso.rddata(c_word_w - 1 downto 0);
-
- proc_common_wait_some_cycles(clk, c_block_size);
-
- mm_bsn_prev <= mm_bsn;
- proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_bsn(c_word_w - 1 downto 0) <= mm_miso.rddata(c_word_w - 1 downto 0);
- proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_bsn(2 * c_word_w - 1 downto c_word_w) <= mm_miso.rddata(c_word_w - 1 downto 0);
- proc_common_wait_some_cycles(clk, 1);
-
- -- Uncomment appropriate assert line dependent on fixed code for capture_bsn in mms_dp_bsn_source:
- --ASSERT mm_bsn_prev<mm_bsn REPORT "Wrong BSN, expected incrementing BSN during PPS or sync interval." SEVERITY ERROR;
- assert mm_bsn_prev = mm_bsn report "Wrong BSN, expected constant BSN during PPS or sync interval." severity ERROR;
-
- -- Run few sync intervals
- proc_common_wait_some_cycles(clk, 3 * c_sync_interval);
-
- -- Write DP off
- proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_off, clk, mm_miso, mm_mosi);
- proc_common_wait_some_cycles(clk, c_block_size);
-
- -- Read dp on status
- proc_mem_mm_bus_rd(c_mm_addr_dp_on, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
- proc_common_wait_some_cycles(clk, 1);
- assert mm_dp_on_status = c_mm_dp_off report "Wrong DP on status, expected DP off." severity ERROR;
-
- proc_common_wait_some_cycles(clk, c_sync_interval);
- tb_end <= '1';
- wait;
+ wait until rst = '0';
+ proc_common_wait_some_cycles(clk, 10);
+
+ -- Write initial BSN and number of block per sync interval
+ proc_mem_mm_bus_wr(c_mm_addr_bsn_lo, c_init_bsn, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_wr(c_mm_addr_bsn_hi, 0, clk, mm_miso, mm_mosi); -- must also write hi part to trigger transfer accross clock domain
+ proc_mem_mm_bus_wr(c_mm_addr_nof_block_per_sync, c_nof_block_per_sync, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
+
+ --------------------------------------------------------------------------
+ -- DP on immediate
+ --------------------------------------------------------------------------
+
+ -- Wait until after PPS
+ proc_common_wait_until_hi_lo(clk, pps);
+
+ -- Write DP on immediate
+ proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_on_immediate, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
+
+ -- Read dp on status
+ proc_mem_mm_bus_rd(c_mm_addr_dp_on, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
+ proc_common_wait_some_cycles(clk, 1);
+ assert mm_dp_on_status = c_mm_dp_on_immediate report "Wrong DP on status, expected DP on immediate." severity ERROR;
+
+ -- Read BSN twice in same PPS interval
+ proc_common_wait_some_cycles(clk, 3 * c_block_size);
+
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(c_word_w - 1 downto 0) <= mm_miso.rddata(c_word_w - 1 downto 0);
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(2 * c_word_w - 1 downto c_word_w) <= mm_miso.rddata(c_word_w - 1 downto 0);
+
+ proc_common_wait_some_cycles(clk, c_block_size);
+
+ mm_bsn_prev <= mm_bsn;
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(c_word_w - 1 downto 0) <= mm_miso.rddata(c_word_w - 1 downto 0);
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(2 * c_word_w - 1 downto c_word_w) <= mm_miso.rddata(c_word_w - 1 downto 0);
+ proc_common_wait_some_cycles(clk, 1);
+
+ -- Uncomment appropriate assert line dependent on fixed code for capture_bsn in mms_dp_bsn_source:
+ --ASSERT mm_bsn_prev<mm_bsn REPORT "Wrong BSN, expected incrementing BSN during PPS or sync interval." SEVERITY ERROR;
+ assert mm_bsn_prev = mm_bsn report "Wrong BSN, expected constant BSN during PPS or sync interval." severity ERROR;
+
+ -- Run few sync intervals
+ proc_common_wait_some_cycles(clk, 3 * c_sync_interval);
+
+ -- Write DP off
+ proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_off, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, c_block_size);
+
+ -- Read dp on status
+ proc_mem_mm_bus_rd(c_mm_addr_dp_on, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
+ proc_common_wait_some_cycles(clk, 1);
+ assert mm_dp_on_status = c_mm_dp_off report "Wrong DP on status, expected DP off." severity ERROR;
+
+ proc_common_wait_some_cycles(clk, c_sync_interval);
+ tb_end <= '1';
+ wait;
end process;
u_dut : entity work.mms_dp_bsn_source
- generic map (
- g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_block_size => c_block_size,
- g_nof_block_per_sync => 1, -- overrule via MM write
- g_bsn_w => c_dp_stream_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
- dp_pps => pps,
-
- -- Memory-mapped clock domain
- reg_mosi => mm_mosi, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
- reg_miso => mm_miso, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
-
- -- Streaming clock domain
- bs_sosi => bs_sosi
- );
+ generic map (
+ g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_block_size => c_block_size,
+ g_nof_block_per_sync => 1, -- overrule via MM write
+ g_bsn_w => c_dp_stream_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+ dp_pps => pps,
+
+ -- Memory-mapped clock domain
+ reg_mosi => mm_mosi, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
+ reg_miso => mm_miso, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
index a17112b675..b7e54915a1 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
@@ -31,14 +31,14 @@
-- > view expanded bs_sosi in Wave window
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_mms_dp_bsn_source_v2 is
end tb_mms_dp_bsn_source_v2;
@@ -89,116 +89,116 @@ begin
p_mm_stimuli : process
begin
- wait until rst = '0';
- proc_common_wait_some_cycles(clk, 10);
-
- -- Write initial BSN and number of block per sync interval
- proc_mem_mm_bus_wr(c_mm_addr_bsn_lo, c_bsn_init, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_wr(c_mm_addr_bsn_hi, 0, clk, mm_miso, mm_mosi); -- must also write hi part to trigger transfer accross clock domain
- proc_mem_mm_bus_wr(c_mm_addr_nof_block_per_sync, c_nof_block_per_sync, clk, mm_miso, mm_mosi);
- proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
-
- --------------------------------------------------------------------------
- -- DP on immediate
- --------------------------------------------------------------------------
-
- -- Wait until after PPS
- proc_common_wait_until_hi_lo(clk, pps);
-
- -- Write DP on immediate
- proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_on_immediate, clk, mm_miso, mm_mosi);
- proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
-
- -- Read dp on status
- proc_mem_mm_bus_rd(c_mm_addr_dp_on, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
- proc_common_wait_some_cycles(clk, 1);
- assert mm_dp_on_status = c_mm_dp_on_immediate report "Wrong DP on status, expected DP on immediate." severity ERROR;
-
- -- Read BSN twice in same PPS interval
- proc_common_wait_some_cycles(clk, c_block_size);
-
- proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_bsn(c_word_w - 1 downto 0) <= mm_miso.rddata(c_word_w - 1 downto 0);
- proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_bsn(2 * c_word_w - 1 downto c_word_w) <= mm_miso.rddata(c_word_w - 1 downto 0);
-
- proc_common_wait_some_cycles(clk, c_block_size);
-
- mm_bsn_prev <= mm_bsn;
- proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_bsn(c_word_w - 1 downto 0) <= mm_miso.rddata(c_word_w - 1 downto 0);
- proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_bsn(2 * c_word_w - 1 downto c_word_w) <= mm_miso.rddata(c_word_w - 1 downto 0);
- proc_common_wait_some_cycles(clk, 1);
-
- -- Uncomment appropriate assert line dependent on fixed code for capture_bsn in mms_dp_bsn_source:
- --ASSERT mm_bsn_prev<mm_bsn REPORT "Wrong BSN, expected incrementing BSN during PPS or sync interval." SEVERITY ERROR;
- assert mm_bsn_prev = mm_bsn report "Wrong BSN, expected constant BSN during PPS or sync interval." severity ERROR;
-
- -- Run few sync intervals
- proc_common_wait_some_cycles(clk, 3 * c_sync_interval);
-
- -- Write DP off
- proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_off, clk, mm_miso, mm_mosi);
- proc_common_wait_some_cycles(clk, c_block_size);
-
- -- Read dp on status
- proc_mem_mm_bus_rd(c_mm_addr_dp_on, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
- proc_common_wait_some_cycles(clk, 1);
- assert mm_dp_on_status = c_mm_dp_off report "Wrong DP on status, expected DP off." severity ERROR;
-
- -- Set bsn_time_offset and read back 2 times 0 and 5
- proc_mem_mm_bus_wr(c_mm_addr_bsn_time_offset, 0, clk, mm_miso, mm_mosi);
- proc_common_wait_some_cycles(clk, 2 * c_cross_clock_domain_latency);
-
- proc_mem_mm_bus_rd(c_mm_addr_bsn_time_offset, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_bsn_time_offset(c_bsn_time_offset_w - 1 downto 0) <= mm_miso.rddata(c_bsn_time_offset_w - 1 downto 0);
- proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(mm_bsn_time_offset(c_bsn_time_offset_w - 1 downto 0)) = 0 report "Wrong offset, expected 0" severity ERROR;
-
- proc_mem_mm_bus_wr(c_mm_addr_bsn_time_offset, 5, clk, mm_miso, mm_mosi);
- proc_common_wait_some_cycles(clk, 2 * c_cross_clock_domain_latency);
-
- proc_mem_mm_bus_rd(c_mm_addr_bsn_time_offset, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_bsn_time_offset(c_bsn_time_offset_w - 1 downto 0) <= mm_miso.rddata(c_bsn_time_offset_w - 1 downto 0);
- proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(mm_bsn_time_offset(c_bsn_time_offset_w - 1 downto 0)) = 5 report "Wrong offset, expected 5" severity ERROR;
-
- proc_common_wait_some_cycles(clk, c_sync_interval);
- tb_end <= '1';
- wait;
+ wait until rst = '0';
+ proc_common_wait_some_cycles(clk, 10);
+
+ -- Write initial BSN and number of block per sync interval
+ proc_mem_mm_bus_wr(c_mm_addr_bsn_lo, c_bsn_init, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_wr(c_mm_addr_bsn_hi, 0, clk, mm_miso, mm_mosi); -- must also write hi part to trigger transfer accross clock domain
+ proc_mem_mm_bus_wr(c_mm_addr_nof_block_per_sync, c_nof_block_per_sync, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
+
+ --------------------------------------------------------------------------
+ -- DP on immediate
+ --------------------------------------------------------------------------
+
+ -- Wait until after PPS
+ proc_common_wait_until_hi_lo(clk, pps);
+
+ -- Write DP on immediate
+ proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_on_immediate, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
+
+ -- Read dp on status
+ proc_mem_mm_bus_rd(c_mm_addr_dp_on, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
+ proc_common_wait_some_cycles(clk, 1);
+ assert mm_dp_on_status = c_mm_dp_on_immediate report "Wrong DP on status, expected DP on immediate." severity ERROR;
+
+ -- Read BSN twice in same PPS interval
+ proc_common_wait_some_cycles(clk, c_block_size);
+
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(c_word_w - 1 downto 0) <= mm_miso.rddata(c_word_w - 1 downto 0);
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(2 * c_word_w - 1 downto c_word_w) <= mm_miso.rddata(c_word_w - 1 downto 0);
+
+ proc_common_wait_some_cycles(clk, c_block_size);
+
+ mm_bsn_prev <= mm_bsn;
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(c_word_w - 1 downto 0) <= mm_miso.rddata(c_word_w - 1 downto 0);
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(2 * c_word_w - 1 downto c_word_w) <= mm_miso.rddata(c_word_w - 1 downto 0);
+ proc_common_wait_some_cycles(clk, 1);
+
+ -- Uncomment appropriate assert line dependent on fixed code for capture_bsn in mms_dp_bsn_source:
+ --ASSERT mm_bsn_prev<mm_bsn REPORT "Wrong BSN, expected incrementing BSN during PPS or sync interval." SEVERITY ERROR;
+ assert mm_bsn_prev = mm_bsn report "Wrong BSN, expected constant BSN during PPS or sync interval." severity ERROR;
+
+ -- Run few sync intervals
+ proc_common_wait_some_cycles(clk, 3 * c_sync_interval);
+
+ -- Write DP off
+ proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_off, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, c_block_size);
+
+ -- Read dp on status
+ proc_mem_mm_bus_rd(c_mm_addr_dp_on, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
+ proc_common_wait_some_cycles(clk, 1);
+ assert mm_dp_on_status = c_mm_dp_off report "Wrong DP on status, expected DP off." severity ERROR;
+
+ -- Set bsn_time_offset and read back 2 times 0 and 5
+ proc_mem_mm_bus_wr(c_mm_addr_bsn_time_offset, 0, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, 2 * c_cross_clock_domain_latency);
+
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_time_offset, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn_time_offset(c_bsn_time_offset_w - 1 downto 0) <= mm_miso.rddata(c_bsn_time_offset_w - 1 downto 0);
+ proc_common_wait_some_cycles(clk, 1);
+ assert TO_UINT(mm_bsn_time_offset(c_bsn_time_offset_w - 1 downto 0)) = 0 report "Wrong offset, expected 0" severity ERROR;
+
+ proc_mem_mm_bus_wr(c_mm_addr_bsn_time_offset, 5, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, 2 * c_cross_clock_domain_latency);
+
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_time_offset, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn_time_offset(c_bsn_time_offset_w - 1 downto 0) <= mm_miso.rddata(c_bsn_time_offset_w - 1 downto 0);
+ proc_common_wait_some_cycles(clk, 1);
+ assert TO_UINT(mm_bsn_time_offset(c_bsn_time_offset_w - 1 downto 0)) = 5 report "Wrong offset, expected 5" severity ERROR;
+
+ proc_common_wait_some_cycles(clk, c_sync_interval);
+ tb_end <= '1';
+ wait;
end process;
u_dut : entity work.mms_dp_bsn_source_v2
- generic map (
- g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_block_size => c_block_size,
- g_nof_clk_per_sync => 200 * 10**6, -- overrule via MM write
- g_bsn_w => c_dp_stream_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
- dp_pps => pps,
-
- -- Memory-mapped clock domain
- reg_mosi => mm_mosi, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
- reg_miso => mm_miso, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
-
- -- Streaming clock domain
- bs_sosi => bs_sosi
- );
+ generic map (
+ g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_block_size => c_block_size,
+ g_nof_clk_per_sync => 200 * 10**6, -- overrule via MM write
+ g_bsn_w => c_dp_stream_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+ dp_pps => pps,
+
+ -- Memory-mapped clock domain
+ reg_mosi => mm_mosi, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
+ reg_miso => mm_miso, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd
index f37559d352..171809ba06 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
entity tb_mms_dp_fields is
end tb_mms_dp_fields;
@@ -34,13 +34,15 @@ architecture tb of tb_mms_dp_fields is
constant clk_period : time := 10 ns;
constant c_delay_len : natural := 3;
- constant c_field_arr : t_common_field_arr(2 downto 0) := (( field_name_pad("test_field_2"), "RW", 36, field_default(x"BADC0DE56") ), -- 0xCAFEDEADB
- ( field_name_pad("test_field_1"), "RO", 8, field_default(x"AA") ), -- 0xEE
- ( field_name_pad("test_field_0"), "RO", 4, field_default(x"B") )); -- 0xF
+ constant c_field_arr : t_common_field_arr(
+ 2 downto 0) := (( field_name_pad("test_field_2"), "RW", 36, field_default(x"BADC0DE56") ), -- 0xCAFEDEADB
+ ( field_name_pad("test_field_1"), "RO", 8, field_default(x"AA") ), -- 0xEE
+ ( field_name_pad("test_field_0"), "RO", 4, field_default(x"B") )); -- 0xF
- constant c_field_arr2: t_common_field_arr(2 downto 0) := (( field_name_pad("test_field_2"), "RO", 4 , field_default(x"B")), -- 0xF
- ( field_name_pad("test_field_1"), "RO", 8 , field_default(x"AA")), -- 0xEE
- ( field_name_pad("test_field_0"), "RW", 36, field_default(x"BADC0DE56"))); -- 0xCAFEDEADB
+ constant c_field_arr2: t_common_field_arr(
+ 2 downto 0) := (( field_name_pad("test_field_2"), "RO", 4 , field_default(x"B")), -- 0xF
+ ( field_name_pad("test_field_1"), "RO", 8 , field_default(x"AA")), -- 0xEE
+ ( field_name_pad("test_field_0"), "RW", 36, field_default(x"BADC0DE56"))); -- 0xCAFEDEADB
signal clk : std_logic := '0';
signal rst : std_logic := '1';
@@ -55,47 +57,47 @@ begin
rst <= '0' after 100 ns;
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_field_arr => c_field_arr2
- )
- port map (
- mm_clk => clk,
- mm_rst => rst,
+ generic map(
+ g_field_arr => c_field_arr2
+ )
+ port map (
+ mm_clk => clk,
+ mm_rst => rst,
- mm_mosi => mm_mosi,
- mm_miso => mm_miso,
+ mm_mosi => mm_mosi,
+ mm_miso => mm_miso,
- slv_clk => clk,
- slv_rst => rst,
+ slv_clk => clk,
+ slv_rst => rst,
- slv_in => my_slv,
- slv_out => slv_out
- );
+ slv_in => my_slv,
+ slv_out => slv_out
+ );
p_stim: process
begin
- wait until rst = '0';
- proc_mem_mm_bus_rd(0, clk, mm_mosi);
- proc_mem_mm_bus_rd(1, clk, mm_mosi);
- proc_mem_mm_bus_rd(2, clk, mm_mosi);
- proc_mem_mm_bus_rd(3, clk, mm_mosi);
-
- -- c_field_arr write
--- proc_mem_mm_bus_wr(2, x"AFEDEADB", clk, mm_mosi);
--- proc_mem_mm_bus_wr(3, x"0000000C", clk, mm_mosi);
-
- -- c_field_arr2 write
- proc_mem_mm_bus_wr(0, x"AFEDEADB", clk, mm_mosi);
- proc_mem_mm_bus_wr(1, x"0000000C", clk, mm_mosi);
-
- -- Wait until words have been written
- wait for 250 ns;
-
- proc_mem_mm_bus_rd(0, clk, mm_mosi);
- proc_mem_mm_bus_rd(1, clk, mm_mosi);
- proc_mem_mm_bus_rd(2, clk, mm_mosi);
- proc_mem_mm_bus_rd(3, clk, mm_mosi);
-
- wait;
- end process;
+ wait until rst = '0';
+ proc_mem_mm_bus_rd(0, clk, mm_mosi);
+ proc_mem_mm_bus_rd(1, clk, mm_mosi);
+ proc_mem_mm_bus_rd(2, clk, mm_mosi);
+ proc_mem_mm_bus_rd(3, clk, mm_mosi);
+
+ -- c_field_arr write
+ -- proc_mem_mm_bus_wr(2, x"AFEDEADB", clk, mm_mosi);
+ -- proc_mem_mm_bus_wr(3, x"0000000C", clk, mm_mosi);
+
+ -- c_field_arr2 write
+ proc_mem_mm_bus_wr(0, x"AFEDEADB", clk, mm_mosi);
+ proc_mem_mm_bus_wr(1, x"0000000C", clk, mm_mosi);
+
+ -- Wait until words have been written
+ wait for 250 ns;
+
+ proc_mem_mm_bus_rd(0, clk, mm_mosi);
+ proc_mem_mm_bus_rd(1, clk, mm_mosi);
+ proc_mem_mm_bus_rd(2, clk, mm_mosi);
+ proc_mem_mm_bus_rd(3, clk, mm_mosi);
+
+ wait;
+ end process;
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd
index 006cf2502a..bfd3d6be3a 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd
@@ -36,15 +36,15 @@
-- . signal tb_end will stop the simulation by stopping the clk
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_mms_dp_fifo_fill is
generic (
@@ -149,11 +149,11 @@ begin
proc_mem_mm_bus_rd(I * c_nof_regs_per_stream + c_reg_max_used_words_offset, mm_clk, reg_dp_fifo_fill_mosi);
end loop;
--- proc_mem_mm_bus_rd(2, mm_clk, reg_dp_fifo_fill_mosi);
+ -- proc_mem_mm_bus_rd(2, mm_clk, reg_dp_fifo_fill_mosi);
-- Read out the rd_empty bit
proc_common_wait_some_cycles(mm_clk, 100);
--- proc_mem_mm_bus_rd(1, mm_clk, reg_dp_fifo_fill_mosi);
+ -- proc_mem_mm_bus_rd(1, mm_clk, reg_dp_fifo_fill_mosi);
for I in 0 to g_nof_streams - 1 loop
proc_mem_mm_bus_rd(I * c_nof_regs_per_stream + c_reg_fifo_flags, mm_clk, reg_dp_fifo_fill_mosi);
end loop;
@@ -165,7 +165,7 @@ begin
for I in 0 to g_nof_streams - 1 loop
proc_mem_mm_bus_rd(I * c_nof_regs_per_stream + c_reg_fifo_flags, mm_clk, reg_dp_fifo_fill_mosi);
end loop;
--- proc_mem_mm_bus_rd(1, mm_clk, reg_dp_fifo_fill_mosi);
+ -- proc_mem_mm_bus_rd(1, mm_clk, reg_dp_fifo_fill_mosi);
proc_common_wait_some_cycles(mm_clk, 10);
tb_end <= '1';
@@ -173,41 +173,41 @@ begin
end process;
dut : entity work.mms_dp_fifo_fill
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_use_complex => true,
- g_fifo_fill => g_dut_fifo_fill,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_af_margin => 4,
- g_fifo_rl => g_dut_fifo_rl
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_dp_fifo_fill_mosi,
- reg_miso => reg_dp_fifo_fill_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- ST sink
- snk_out_arr => OPEN,
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => open
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_use_complex => true,
+ g_fifo_fill => g_dut_fifo_fill,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_af_margin => 4,
+ g_fifo_rl => g_dut_fifo_rl
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_dp_fifo_fill_mosi,
+ reg_miso => reg_dp_fifo_fill_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- ST sink
+ snk_out_arr => OPEN,
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => open
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd
index 3ec6d17329..62b28fdd10 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd
@@ -29,16 +29,16 @@
-- The tb is self stopping and self checking.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_mms_dp_force_data_parallel_arr is
generic (
@@ -149,17 +149,17 @@ begin
snk_in_complex <= func_dp_stream_set_data(snk_in_re, INCR_UVEC(snk_in.data, 2), "IM"); -- apply im = data+2
u_snk_in_complex_dly : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- latency of DUT
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_out => OPEN,
- snk_in => snk_in_complex,
- src_in => src_in_arr(0),
- src_out => snk_in_complex_dly
- );
+ generic map (
+ g_pipeline => 1 -- latency of DUT
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_out => OPEN,
+ snk_in => snk_in_complex,
+ src_in => src_in_arr(0),
+ src_out => snk_in_complex_dly
+ );
snk_out <= snk_out_arr(0); -- use stream 0 for flow control, all tb streams have same flow control
snk_in_arr <= (others => snk_in_complex); -- apply same default tb data to all streams
@@ -296,73 +296,73 @@ begin
gen_one : if g_nof_streams = 1 generate
u_dut_one : entity work.mms_dp_force_data_parallel
- generic map (
- g_dat_w => g_dat_w,
- g_increment_data => g_increment_data,
- g_increment_re => g_increment_re,
- g_increment_im => g_increment_im,
- g_increment_data_on_sop => g_increment_on_sop,
- g_increment_re_on_sop => g_increment_on_sop,
- g_increment_im_on_sop => g_increment_on_sop,
- g_restart_data_on_sync => g_restart_on_sync,
- g_restart_re_on_sync => g_restart_on_sync,
- g_restart_im_on_sync => g_restart_on_sync,
- g_restart_data_on_sop => g_restart_on_sop,
- g_restart_re_on_sop => g_restart_on_sop,
- g_restart_im_on_sop => g_restart_on_sop
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM control
- reg_force_data_mosi => reg_force_data_mosi,
- reg_force_data_miso => reg_force_data_miso,
- -- ST sink
- snk_out => snk_out_arr(0),
- snk_in => snk_in_arr(0),
- -- ST source
- src_in => src_in_arr(0),
- src_out => src_out_arr(0)
- );
+ generic map (
+ g_dat_w => g_dat_w,
+ g_increment_data => g_increment_data,
+ g_increment_re => g_increment_re,
+ g_increment_im => g_increment_im,
+ g_increment_data_on_sop => g_increment_on_sop,
+ g_increment_re_on_sop => g_increment_on_sop,
+ g_increment_im_on_sop => g_increment_on_sop,
+ g_restart_data_on_sync => g_restart_on_sync,
+ g_restart_re_on_sync => g_restart_on_sync,
+ g_restart_im_on_sync => g_restart_on_sync,
+ g_restart_data_on_sop => g_restart_on_sop,
+ g_restart_re_on_sop => g_restart_on_sop,
+ g_restart_im_on_sop => g_restart_on_sop
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM control
+ reg_force_data_mosi => reg_force_data_mosi,
+ reg_force_data_miso => reg_force_data_miso,
+ -- ST sink
+ snk_out => snk_out_arr(0),
+ snk_in => snk_in_arr(0),
+ -- ST source
+ src_in => src_in_arr(0),
+ src_out => src_out_arr(0)
+ );
end generate;
gen_arr : if g_nof_streams > 1 generate
u_dut_arr : entity work.mms_dp_force_data_parallel_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_dat_w => g_dat_w,
- g_increment_data => g_increment_data,
- g_increment_re => g_increment_re,
- g_increment_im => g_increment_im,
- g_increment_data_on_sop => g_increment_on_sop,
- g_increment_re_on_sop => g_increment_on_sop,
- g_increment_im_on_sop => g_increment_on_sop,
- g_restart_data_on_sync => g_restart_on_sync,
- g_restart_re_on_sync => g_restart_on_sync,
- g_restart_im_on_sync => g_restart_on_sync,
- g_restart_data_on_sop => g_restart_on_sop,
- g_restart_re_on_sop => g_restart_on_sop,
- g_restart_im_on_sop => g_restart_on_sop
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM control
- reg_force_data_mosi => reg_force_data_mosi,
- reg_force_data_miso => reg_force_data_miso,
- -- ST sink
- snk_out_arr => snk_out_arr,
- snk_in_arr => snk_in_arr,
- -- ST source
- src_in_arr => src_in_arr,
- src_out_arr => src_out_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_dat_w => g_dat_w,
+ g_increment_data => g_increment_data,
+ g_increment_re => g_increment_re,
+ g_increment_im => g_increment_im,
+ g_increment_data_on_sop => g_increment_on_sop,
+ g_increment_re_on_sop => g_increment_on_sop,
+ g_increment_im_on_sop => g_increment_on_sop,
+ g_restart_data_on_sync => g_restart_on_sync,
+ g_restart_re_on_sync => g_restart_on_sync,
+ g_restart_im_on_sync => g_restart_on_sync,
+ g_restart_data_on_sop => g_restart_on_sop,
+ g_restart_re_on_sop => g_restart_on_sop,
+ g_restart_im_on_sop => g_restart_on_sop
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM control
+ reg_force_data_mosi => reg_force_data_mosi,
+ reg_force_data_miso => reg_force_data_miso,
+ -- ST sink
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ -- ST source
+ src_in_arr => src_in_arr,
+ src_out_arr => src_out_arr
+ );
end generate;
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd
index 4b9c1555db..23a997aeef 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd
@@ -29,16 +29,16 @@
-- The tb is self stopping and self checking.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_mms_dp_force_data_serial_arr is
generic (
@@ -147,17 +147,17 @@ begin
snk_in_complex <= func_dp_stream_set_data(snk_in_re, INCR_UVEC(snk_in.data, 2), "IM"); -- apply im = data+2
u_snk_in_complex_dly : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- latency of DUT
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_out => OPEN,
- snk_in => snk_in_complex,
- src_in => src_in_arr(0),
- src_out => snk_in_complex_dly
- );
+ generic map (
+ g_pipeline => 1 -- latency of DUT
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_out => OPEN,
+ snk_in => snk_in_complex,
+ src_in => src_in_arr(0),
+ src_out => snk_in_complex_dly
+ );
snk_out <= snk_out_arr(0); -- use stream 0 for flow control, all tb streams have same flow control
snk_in_arr <= (others => snk_in_complex); -- apply same default tb data to all streams
@@ -292,53 +292,53 @@ begin
gen_one : if g_nof_streams = 1 generate
u_dut_one : entity work.mms_dp_force_data_serial
- generic map (
- g_dat_w => g_dat_w,
- g_index_period => g_index_period,
- g_index_sample_block_n => g_index_sample_block_n
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM control
- reg_force_data_mosi => reg_force_data_mosi,
- reg_force_data_miso => reg_force_data_miso,
- -- ST sink
- snk_out => snk_out_arr(0),
- snk_in => snk_in_arr(0),
- -- ST source
- src_in => src_in_arr(0),
- src_out => src_out_arr(0)
- );
+ generic map (
+ g_dat_w => g_dat_w,
+ g_index_period => g_index_period,
+ g_index_sample_block_n => g_index_sample_block_n
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM control
+ reg_force_data_mosi => reg_force_data_mosi,
+ reg_force_data_miso => reg_force_data_miso,
+ -- ST sink
+ snk_out => snk_out_arr(0),
+ snk_in => snk_in_arr(0),
+ -- ST source
+ src_in => src_in_arr(0),
+ src_out => src_out_arr(0)
+ );
end generate;
gen_arr : if g_nof_streams > 1 generate
u_dut_arr : entity work.mms_dp_force_data_serial_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_dat_w => g_dat_w,
- g_index_period => g_index_period,
- g_index_sample_block_n => g_index_sample_block_n
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM control
- reg_force_data_mosi => reg_force_data_mosi,
- reg_force_data_miso => reg_force_data_miso,
- -- ST sink
- snk_out_arr => snk_out_arr,
- snk_in_arr => snk_in_arr,
- -- ST source
- src_in_arr => src_in_arr,
- src_out_arr => src_out_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_dat_w => g_dat_w,
+ g_index_period => g_index_period,
+ g_index_sample_block_n => g_index_sample_block_n
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM control
+ reg_force_data_mosi => reg_force_data_mosi,
+ reg_force_data_miso => reg_force_data_miso,
+ -- ST sink
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ -- ST source
+ src_in_arr => src_in_arr,
+ src_out_arr => src_out_arr
+ );
end generate;
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
index 17f4264509..e6fa0656b2 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
@@ -28,16 +28,16 @@
-- The tb is self stopping and self checking.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_mms_dp_gain_arr is
generic (
@@ -123,15 +123,15 @@ begin
in_sosi_arr <= (others => in_sosi); -- use same data on all input streams
u_in_sosi_dly : entity work.dp_pipeline
- generic map (
- g_pipeline => 3 -- latency of DUT
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => in_sosi,
- src_out => in_sosi_dly
- );
+ generic map (
+ g_pipeline => 3 -- latency of DUT
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => in_sosi,
+ src_out => in_sosi_dly
+ );
p_mm_stimuli : process
variable v_gain_re : integer;
@@ -223,65 +223,65 @@ begin
gen_one : if g_nof_streams = 1 generate
u_dut_one : entity work.mms_dp_gain
- generic map (
- g_technology => g_technology,
- g_complex_data => g_complex_data,
- g_complex_gain => g_complex_gain,
- g_gain_init_re => 1,
- g_gain_init_im => 0,
- g_gain_w => c_gain_w,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM access to gain
- reg_gain_re_mosi => reg_gain_re_mosi,
- reg_gain_re_miso => reg_gain_re_miso,
- reg_gain_im_mosi => reg_gain_im_mosi,
- reg_gain_im_miso => reg_gain_im_miso,
-
- -- ST
- in_sosi => in_sosi_arr(0),
- out_sosi => out_sosi_arr(0)
- );
+ generic map (
+ g_technology => g_technology,
+ g_complex_data => g_complex_data,
+ g_complex_gain => g_complex_gain,
+ g_gain_init_re => 1,
+ g_gain_init_im => 0,
+ g_gain_w => c_gain_w,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM access to gain
+ reg_gain_re_mosi => reg_gain_re_mosi,
+ reg_gain_re_miso => reg_gain_re_miso,
+ reg_gain_im_mosi => reg_gain_im_mosi,
+ reg_gain_im_miso => reg_gain_im_miso,
+
+ -- ST
+ in_sosi => in_sosi_arr(0),
+ out_sosi => out_sosi_arr(0)
+ );
end generate;
gen_arr : if g_nof_streams > 1 generate
u_dut_arr : entity work.mms_dp_gain_arr
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_complex_data => g_complex_data,
- g_complex_gain => g_complex_gain,
- g_gain_init_re => 1,
- g_gain_init_im => 0,
- g_gain_w => c_gain_w,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM access to gain
- reg_gain_re_mosi => reg_gain_re_mosi,
- reg_gain_re_miso => reg_gain_re_miso,
- reg_gain_im_mosi => reg_gain_im_mosi,
- reg_gain_im_miso => reg_gain_im_miso,
-
- -- ST
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_complex_data => g_complex_data,
+ g_complex_gain => g_complex_gain,
+ g_gain_init_re => 1,
+ g_gain_init_im => 0,
+ g_gain_w => c_gain_w,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM access to gain
+ reg_gain_re_mosi => reg_gain_re_mosi,
+ reg_gain_re_miso => reg_gain_re_miso,
+ reg_gain_im_mosi => reg_gain_im_mosi,
+ reg_gain_im_miso => reg_gain_im_miso,
+
+ -- ST
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => out_sosi_arr
+ );
end generate;
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
index 5c3eb33571..af5586fa5c 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
@@ -27,16 +27,16 @@
-- The tb is self stopping and self checking.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_mms_dp_gain_serial_arr is
generic (
@@ -146,28 +146,28 @@ begin
end process;
u_in_sosi_dly : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dut_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => in_sosi,
- src_out => in_sosi_dly
- );
+ generic map (
+ g_pipeline => c_dut_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => in_sosi,
+ src_out => in_sosi_dly
+ );
u_gains_rd_address_dly : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_dut_latency,
- g_in_dat_w => c_nof_gains_w,
- g_out_dat_w => c_nof_gains_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_dat => gains_rd_address,
- out_dat => gains_rd_address_dly
- );
+ generic map (
+ g_pipeline => c_dut_latency,
+ g_in_dat_w => c_nof_gains_w,
+ g_out_dat_w => c_nof_gains_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => gains_rd_address,
+ out_dat => gains_rd_address_dly
+ );
p_mm_stimuli : process
begin
@@ -255,67 +255,67 @@ begin
gen_one : if g_nof_streams = 1 generate
u_dut_one : entity work.mms_dp_gain_serial
- generic map (
- g_technology => c_tech_select_default,
- g_nof_gains => g_nof_gains, -- number of gains in series per stream
- g_complex_data => g_complex_data,
- g_complex_gain => g_complex_gain,
- g_gain_w => c_gain_w,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w,
- g_gains_file_name => "UNUSED", -- "UNUSED" or relative path to some "gains_#.hex" file, where # is the stream index
- g_gains_write_only => false -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode to save memory. When FALSE it is True Dual Port.
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_gains_mosi => ram_gains_mosi, -- write side
- ram_gains_miso => ram_gains_miso,
-
- -- ST interface
- gains_rd_address => gains_rd_address, -- read side, same read address for all streams
-
- in_sosi => in_sosi_arr(0),
- out_sosi => out_sosi_arr(0)
- );
+ generic map (
+ g_technology => c_tech_select_default,
+ g_nof_gains => g_nof_gains, -- number of gains in series per stream
+ g_complex_data => g_complex_data,
+ g_complex_gain => g_complex_gain,
+ g_gain_w => c_gain_w,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w,
+ g_gains_file_name => "UNUSED", -- "UNUSED" or relative path to some "gains_#.hex" file, where # is the stream index
+ g_gains_write_only => false -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode to save memory. When FALSE it is True Dual Port.
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_gains_mosi => ram_gains_mosi, -- write side
+ ram_gains_miso => ram_gains_miso,
+
+ -- ST interface
+ gains_rd_address => gains_rd_address, -- read side, same read address for all streams
+
+ in_sosi => in_sosi_arr(0),
+ out_sosi => out_sosi_arr(0)
+ );
end generate;
gen_par : if g_nof_streams > 1 generate
u_dut_par : entity work.mms_dp_gain_serial_arr
- generic map (
- g_technology => c_tech_select_default,
- g_nof_streams => g_nof_streams,
- g_nof_gains => g_nof_gains, -- number of gains in series per stream
- g_complex_data => g_complex_data,
- g_complex_gain => g_complex_gain,
- g_gain_w => c_gain_w,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w,
- g_gains_file_name => "UNUSED", -- "UNUSED" or relative path to some "gains_#.hex" file, where # is the stream index
- g_gains_write_only => false -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode to save memory. When FALSE it is True Dual Port.
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_gains_mosi => ram_gains_mosi, -- write side
- ram_gains_miso => ram_gains_miso,
-
- -- ST interface
- gains_rd_address => gains_rd_address, -- read side, same read address for all streams
-
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_technology => c_tech_select_default,
+ g_nof_streams => g_nof_streams,
+ g_nof_gains => g_nof_gains, -- number of gains in series per stream
+ g_complex_data => g_complex_data,
+ g_complex_gain => g_complex_gain,
+ g_gain_w => c_gain_w,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w,
+ g_gains_file_name => "UNUSED", -- "UNUSED" or relative path to some "gains_#.hex" file, where # is the stream index
+ g_gains_write_only => false -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode to save memory. When FALSE it is True Dual Port.
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_gains_mosi => ram_gains_mosi, -- write side
+ ram_gains_miso => ram_gains_miso,
+
+ -- ST interface
+ gains_rd_address => gains_rd_address, -- read side, same read address for all streams
+
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => out_sosi_arr
+ );
end generate;
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd
index 869118a709..85ae3e38fe 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd
@@ -29,16 +29,16 @@
-- The tb can be simple as the components in the DUT are already verified.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_mms_dp_scale is
end tb_mms_dp_scale;
@@ -107,15 +107,15 @@ begin
in_sosi.valid <= cnt_val;
u_in_sosi_dly : entity work.dp_pipeline
- generic map (
- g_pipeline => 3 -- latency of DUT
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => in_sosi,
- src_out => in_sosi_dly
- );
+ generic map (
+ g_pipeline => 3 -- latency of DUT
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => in_sosi,
+ src_out => in_sosi_dly
+ );
p_mm_stimuli : process
begin
@@ -158,7 +158,7 @@ begin
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
- u_dut : entity work.mms_dp_scale
+ u_dut : entity work.mms_dp_scale
generic map (
g_complex_data => c_complex_data,
g_complex_gain => c_complex_gain,
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
index 16982fd0cd..a3cf4e5e3c 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
@@ -35,15 +35,15 @@
-- . the tb is self checking
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_mms_dp_sync_checker is
generic (
@@ -268,22 +268,22 @@ begin
-- DUT function
dut : entity work.mms_dp_sync_checker
- generic map (
- g_cross_clock_domain => true,
- g_nof_blk_per_sync => g_nof_blk_per_sync
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => rst,
- dp_clk => clk,
- snk_out => dut_snk_out,
- snk_in => dut_snk_in,
- src_in => dut_src_in,
- src_out => dut_src_out,
- reg_dp_sync_checker_mosi => mm_mosi,
- reg_dp_sync_checker_miso => mm_miso
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_nof_blk_per_sync => g_nof_blk_per_sync
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => rst,
+ dp_clk => clk,
+ snk_out => dut_snk_out,
+ snk_in => dut_snk_in,
+ src_in => dut_src_in,
+ src_out => dut_src_out,
+ reg_dp_sync_checker_mosi => mm_mosi,
+ reg_dp_sync_checker_miso => mm_miso
+ );
-- Connect DUT source output stream to verification
dut_src_in <= verify_snk_out;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd
index 25c9376f2c..285df331a3 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd
@@ -35,15 +35,15 @@
-- When g_combine_streams = TRUE: check that all streams start again atthe same time.
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_mms_dp_xonoff is
generic (
@@ -157,62 +157,62 @@ begin
stimuli_src_in <= c_dp_siso_rdy;
u_dut : entity work.mms_dp_xonoff
- generic map(
- g_nof_streams => c_nof_streams,
- g_combine_streams => g_combine_streams,
- g_bypass => false
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => rst,
- mm_clk => clk,
-
- reg_mosi => mm_mosi,
- reg_miso => mm_miso,
-
- -- Streaming clock domain
- dp_rst => rst,
- dp_clk => clk,
-
- -- ST sinks
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_nof_streams,
+ g_combine_streams => g_combine_streams,
+ g_bypass => false
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => rst,
+ mm_clk => clk,
+
+ reg_mosi => mm_mosi,
+ reg_miso => mm_miso,
+
+ -- Streaming clock domain
+ dp_rst => rst,
+ dp_clk => clk,
+
+ -- ST sinks
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr
+ );
p_stim: process
begin
- wait until rst = '0';
- proc_mem_mm_bus_wr(0, x"1", clk, mm_mosi);
- proc_mem_mm_bus_wr(2, x"1", clk, mm_mosi);
- proc_mem_mm_bus_wr(4, x"1", clk, mm_mosi);
- proc_mem_mm_bus_wr(6, x"1", clk, mm_mosi);
+ wait until rst = '0';
+ proc_mem_mm_bus_wr(0, x"1", clk, mm_mosi);
+ proc_mem_mm_bus_wr(2, x"1", clk, mm_mosi);
+ proc_mem_mm_bus_wr(4, x"1", clk, mm_mosi);
+ proc_mem_mm_bus_wr(6, x"1", clk, mm_mosi);
- wait for 500 ns;
+ wait for 500 ns;
- proc_mem_mm_bus_wr(0, x"0", clk, mm_mosi);
- proc_mem_mm_bus_wr(2, x"0", clk, mm_mosi);
- proc_mem_mm_bus_wr(4, x"0", clk, mm_mosi);
- proc_mem_mm_bus_wr(6, x"0", clk, mm_mosi);
+ proc_mem_mm_bus_wr(0, x"0", clk, mm_mosi);
+ proc_mem_mm_bus_wr(2, x"0", clk, mm_mosi);
+ proc_mem_mm_bus_wr(4, x"0", clk, mm_mosi);
+ proc_mem_mm_bus_wr(6, x"0", clk, mm_mosi);
- wait for 1200 ns;
+ wait for 1200 ns;
- proc_mem_mm_bus_wr(0, x"1", clk, mm_mosi);
+ proc_mem_mm_bus_wr(0, x"1", clk, mm_mosi);
- wait for 1400 ns;
+ wait for 1400 ns;
- proc_mem_mm_bus_wr(2, x"1", clk, mm_mosi);
+ proc_mem_mm_bus_wr(2, x"1", clk, mm_mosi);
- wait for 2000 ns;
+ wait for 2000 ns;
- proc_mem_mm_bus_wr(4, x"1", clk, mm_mosi);
+ proc_mem_mm_bus_wr(4, x"1", clk, mm_mosi);
- wait for 1700 ns;
+ wait for 1700 ns;
- proc_mem_mm_bus_wr(6, x"1", clk, mm_mosi);
+ proc_mem_mm_bus_wr(6, x"1", clk, mm_mosi);
- wait;
- end process;
+ wait;
+ end process;
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd
index 85eb2eafed..7e014af8a2 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
--- > as 2
--- > run -all --> OK
+ -- > as 2
+ -- > run -all --> OK
entity tb_tb2_dp_demux is
end tb_tb2_dp_demux;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb2_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb_tb2_dp_mux.vhd
index a82257f888..2c75cd0f5e 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb2_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb2_dp_mux.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
--- > as 2
--- > run -all --> OK
+ -- > as 2
+ -- > run -all --> OK
entity tb_tb2_dp_mux is
end tb_tb2_dp_mux;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb3_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_tb3_dp_demux.vhd
index 5d6bee41f5..cd72d3b265 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb3_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb3_dp_demux.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
--- > as 2
--- > run -all --> OK
+ -- > as 2
+ -- > run -all --> OK
entity tb_tb3_dp_demux is
end tb_tb3_dp_demux;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb3_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb_tb3_dp_mux.vhd
index 140f3d8ff1..e2232e8b87 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb3_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb3_dp_mux.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
--- > as 2
--- > run -all --> OK
+ -- > as 2
+ -- > run -all --> OK
entity tb_tb3_dp_mux is
end tb_tb3_dp_mux;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd
index fcca299fdb..b66225126d 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd
@@ -30,8 +30,8 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_block_from_mm is
end tb_tb_dp_block_from_mm;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen.vhd
index ccb522b9b6..eec5f8d8d3 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_block_gen is
end tb_tb_dp_block_gen;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
index a48141d030..cc36da36e0 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
@@ -25,8 +25,8 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_block_gen_valid_arr is
end tb_tb_dp_block_gen_valid_arr;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape.vhd
index c9853ef71b..ec4b6a40c2 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape.vhd
@@ -23,8 +23,8 @@
-- Purpose: Verify pipelining or no pipelining of dp_block_reshape
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_block_reshape is
end tb_tb_dp_block_reshape;
@@ -35,7 +35,7 @@ begin
-- > as 5
-- > run -all --> OK
--- g_pipeline : NATURAL := 1 -- use 0 or 1
+ -- g_pipeline : NATURAL := 1 -- use 0 or 1
u_comb : entity work.tb_dp_block_reshape generic map (0);
u_pipe : entity work.tb_dp_block_reshape generic map (1);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape_sync.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape_sync.vhd
index d137defec7..0a5b7281bd 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape_sync.vhd
@@ -23,8 +23,8 @@
-- Purpose: Verify pipelining or no pipelining of dp_block_reshape_sync
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_block_reshape_sync is
end tb_tb_dp_block_reshape_sync;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_select.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_select.vhd
index e4ea053afe..3ea74c7dc8 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_select.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_select.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
--- Author: Eric Kooistra, 14 Dec 2018
--- Purpose: Verify multiple variations of tb_dp_block_select
--- Description:
--- Usage:
--- > as 3
--- > run -all
+ -- Author: Eric Kooistra, 14 Dec 2018
+ -- Purpose: Verify multiple variations of tb_dp_block_select
+ -- Description:
+ -- Usage:
+ -- > as 3
+ -- > run -all
entity tb_tb_dp_block_select is
end tb_tb_dp_block_select;
@@ -39,10 +39,10 @@ architecture tb of tb_tb_dp_block_select is
constant c_length : natural := 5;
constant c_end : natural := c_length - 1;
begin
--- g_dut_pipeline : NATURAL := 1;
--- g_nof_blocks_per_sync : NATURAL := c_length;
--- g_index_lo : NATURAL := 0;
--- g_index_hi : NATURAL := c_length-1 = c_end
+ -- g_dut_pipeline : NATURAL := 1;
+ -- g_nof_blocks_per_sync : NATURAL := c_length;
+ -- g_index_lo : NATURAL := 0;
+ -- g_index_hi : NATURAL := c_length-1 = c_end
u_0_end_comb : entity work.tb_dp_block_select generic map(0, c_length, 0, c_end); -- pass on unchanged without pipeline so combinatorially
u_0_end : entity work.tb_dp_block_select generic map(1, c_length, 0, c_end); -- pass on unchanged with pipeline
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_bsn_at_sync.vhd
index 5b129050da..e5fecef9e4 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_bsn_at_sync.vhd
@@ -27,7 +27,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_block_validate_bsn_at_sync is
end tb_tb_dp_block_validate_bsn_at_sync;
@@ -38,9 +38,9 @@ architecture tb of tb_tb_dp_block_validate_bsn_at_sync is
constant c_blk_per_sync : natural := 5;
constant c_data_per_blk : natural := 9;
begin
--- g_nof_blocks_per_sync : NATURAL := 5;
--- g_nof_data_per_blk : NATURAL := 6;
--- g_bsn_init : NATURAL := 7 -- >= g_nof_blocks_per_sync for discarded sync, < g_nof_blocks_per_sync for no discarded sync.
+ -- g_nof_blocks_per_sync : NATURAL := 5;
+ -- g_nof_data_per_blk : NATURAL := 6;
+ -- g_bsn_init : NATURAL := 7 -- >= g_nof_blocks_per_sync for discarded sync, < g_nof_blocks_per_sync for no discarded sync.
u_smaller : entity work.tb_dp_block_validate_bsn_at_sync generic map(c_blk_per_sync, c_data_per_blk, c_blk_per_sync - 4); -- g_bsn_init < g_nof_blocks_per_sync
u_equal : entity work.tb_dp_block_validate_bsn_at_sync generic map(c_blk_per_sync, c_data_per_blk, c_blk_per_sync); -- g_bsn_init = g_nof_blocks_per_sync
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_channel.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_channel.vhd
index b88c0ada78..5368f2b047 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_channel.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_channel.vhd
@@ -27,7 +27,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_block_validate_channel is
end tb_tb_dp_block_validate_channel;
@@ -39,11 +39,11 @@ architecture tb of tb_tb_dp_block_validate_channel is
constant c_data_per_blk : natural := 9;
constant c_gap_size : natural := 5;
begin
--- g_nof_blocks_per_sync : NATURAL := 8;
--- g_nof_data_per_blk : NATURAL := 8;
--- g_gap_size : NATURAL := 5;
--- g_remove_channel : NATURAL := 0;
--- g_mode : STRING := "="
+ -- g_nof_blocks_per_sync : NATURAL := 8;
+ -- g_nof_data_per_blk : NATURAL := 8;
+ -- g_gap_size : NATURAL := 5;
+ -- g_remove_channel : NATURAL := 0;
+ -- g_mode : STRING := "="
u_equal : entity work.tb_dp_block_validate_channel generic map(c_blk_per_sync, c_data_per_blk, c_gap_size, 7, "=");
u_smaller : entity work.tb_dp_block_validate_channel generic map(c_blk_per_sync, c_data_per_blk, c_gap_size, 7, "<");
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_err.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_err.vhd
index da1be4d735..857ac08adc 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_err.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_err.vhd
@@ -27,7 +27,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_block_validate_err is
end tb_tb_dp_block_validate_err;
@@ -40,12 +40,12 @@ architecture tb of tb_tb_dp_block_validate_err is
constant c_max_block_size : natural := 9;
constant c_nof_err_counts : natural := 5;
begin
--- g_nof_blocks_per_sync : NATURAL := 5;
--- g_nof_data_per_blk : NATURAL := 9;
--- g_max_block_size : NATURAL := 9;
--- g_nof_err_counts : NATURAL := 8;
--- g_gap_size : NATURAL := 4;
--- g_cnt_w : NATURAL := 3
+ -- g_nof_blocks_per_sync : NATURAL := 5;
+ -- g_nof_data_per_blk : NATURAL := 9;
+ -- g_max_block_size : NATURAL := 9;
+ -- g_nof_err_counts : NATURAL := 8;
+ -- g_gap_size : NATURAL := 4;
+ -- g_cnt_w : NATURAL := 3
u_normal : entity work.tb_dp_block_validate_err generic map(c_blk_per_sync, c_data_per_blk, c_max_block_size, c_nof_err_counts, 4, 3);
u_clip : entity work.tb_dp_block_validate_err generic map(c_blk_per_sync, c_data_per_blk, c_max_block_size, c_nof_err_counts, 4, 3);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_length.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_length.vhd
index c5ec1d291f..c95b591d17 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_length.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_length.vhd
@@ -27,7 +27,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_block_validate_length is
end tb_tb_dp_block_validate_length;
@@ -40,10 +40,10 @@ architecture tb of tb_tb_dp_block_validate_length is
constant c_exp_length : natural := 9;
constant c_err_bi : natural := 3;
begin
--- g_nof_blocks_per_sync : NATURAL := 5;
--- g_nof_data_per_blk : NATURAL := 9;
--- g_expected_length : NATURAL := 3;
--- g_err_bi : NATURAL := 3
+ -- g_nof_blocks_per_sync : NATURAL := 5;
+ -- g_nof_data_per_blk : NATURAL := 9;
+ -- g_expected_length : NATURAL := 3;
+ -- g_err_bi : NATURAL := 3
u_equal : entity work.tb_dp_block_validate_length generic map(c_blk_per_sync, c_data_per_blk, c_exp_length, c_err_bi); -- g_expected_length = g_nof_data_per_blk
u_smaller : entity work.tb_dp_block_validate_length generic map(c_blk_per_sync, c_data_per_blk, c_exp_length - 3, c_err_bi); -- g_expected_length < g_nof_data_per_blk
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd
index 98e4893c43..8085cbe77a 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_bsn_align is
end tb_tb_dp_bsn_align;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
index d1ac6698b7..0a02fded8b 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
@@ -24,8 +24,8 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_bsn_align_v2 is
end tb_tb_dp_bsn_align_v2;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
index cf58ac3979..37fb92f0cc 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
--- > as 4
--- > run -all --> OK
+ -- > as 4
+ -- > run -all --> OK
entity tb_tb_dp_bsn_source_v2 is
end tb_tb_dp_bsn_source_v2;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
index 23ff128bc4..970d041319 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
@@ -23,11 +23,11 @@
-- Purpose: Multi test bench for tb_dp_bsn_sync_scheduler.vhd
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
--- > as 4
--- > run -all --> OK
+ -- > as 4
+ -- > run -all --> OK
entity tb_tb_dp_bsn_sync_scheduler is
end tb_tb_dp_bsn_sync_scheduler;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_calculate_crc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_calculate_crc.vhd
index b3bf5be97e..18cc225ee3 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_calculate_crc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_calculate_crc.vhd
@@ -28,14 +28,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_calculate_crc is
end tb_tb_dp_calculate_crc;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_concat.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_concat.vhd
index 502254befc..1af5eb0e44 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_concat.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_concat.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_concat is
end tb_tb_dp_concat;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_concat_field_blk.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_concat_field_blk.vhd
index 69e2c6d1f7..de9ae2f8a4 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_concat_field_blk.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_concat_field_blk.vhd
@@ -26,8 +26,8 @@
-- > run -all --> OK
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_concat_field_blk is
end tb_tb_dp_concat_field_blk;
@@ -35,14 +35,14 @@ end tb_tb_dp_concat_field_blk;
architecture tb of tb_tb_dp_concat_field_blk is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- -- general
--- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
--- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
--- -- specific
--- g_data_w : NATURAL := 64;
--- g_nof_repeat : NATURAL := 13;
--- g_pkt_len : NATURAL := 100;
--- g_pkt_gap : NATURAL := 0
+ -- -- general
+ -- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- -- specific
+ -- g_data_w : NATURAL := 64;
+ -- g_nof_repeat : NATURAL := 13;
+ -- g_pkt_len : NATURAL := 100;
+ -- g_pkt_gap : NATURAL := 0
u_large_gap : entity work.tb_dp_concat_field_blk generic map (e_active, e_active, 64, 13, 100, 10); -- g_pkt_gap > header length
u_zero_gap : entity work.tb_dp_concat_field_blk generic map (e_active, e_active, 64, 13, 100, 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_counter.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_counter.vhd
index d97d8f4ae2..04f58c9f65 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_counter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_counter.vhd
@@ -21,15 +21,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.tb_dp_pkg.all;
--- Purpose: Verify multiple variations of tb_dp_counter
--- Description:
--- Usage:
--- > as 6
--- > run -all
+ -- Purpose: Verify multiple variations of tb_dp_counter
+ -- Description:
+ -- Usage:
+ -- > as 6
+ -- > run -all
entity tb_tb_dp_counter is
end tb_tb_dp_counter;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_interleave_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_interleave_to_one.vhd
index 4f1ab4f582..e19ba764f1 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_interleave_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_interleave_to_one.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_deinterleave_interleave_to_one is
end tb_tb_dp_deinterleave_interleave_to_one;
@@ -40,19 +40,19 @@ architecture tb of tb_tb_dp_deinterleave_interleave_to_one is
constant c_rep_act : natural := 5;
constant c_rep_rnd : natural := 100;
begin
--- -- general
--- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
--- -- specific
--- g_use_complex : BOOLEAN := FALSE;
--- g_nof_repeat : NATURAL := 5;
--- g_nof_streams : NATURAL := 4;
--- g_pkt_len : NATURAL := 12; -- typcially multiple of g_nof_streams
--- g_pkt_gap : NATURAL := 10
+ -- -- general
+ -- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- -- specific
+ -- g_use_complex : BOOLEAN := FALSE;
+ -- g_nof_repeat : NATURAL := 5;
+ -- g_nof_streams : NATURAL := 4;
+ -- g_pkt_len : NATURAL := 12; -- typcially multiple of g_nof_streams
+ -- g_pkt_gap : NATURAL := 10
--- g_nof_streams
--- | g_pkt_len
--- | | g_pkt_gap
--- | | |
+ -- g_nof_streams
+ -- | g_pkt_len
+ -- | | g_pkt_gap
+ -- | | |
u_act_1_12_0 : entity work.tb_dp_deinterleave_interleave_to_one generic map(e_active, false, c_rep_act, 1, 12, 0);
u_act_2_12_0 : entity work.tb_dp_deinterleave_interleave_to_one generic map(e_active, false, c_rep_act, 2, 12, 0);
u_act_3_12_0 : entity work.tb_dp_deinterleave_interleave_to_one generic map(e_active, false, c_rep_act, 3, 12, 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_one_to_n_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_one_to_n_to_one.vhd
index 45d727f2a6..373c4859e0 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_one_to_n_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_one_to_n_to_one.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_deinterleave_one_to_n_to_one is
end tb_tb_dp_deinterleave_one_to_n_to_one;
@@ -40,23 +40,23 @@ architecture tb of tb_tb_dp_deinterleave_one_to_n_to_one is
constant c_rep_act : natural := 5;
constant c_rep_rnd : natural := 100;
begin
--- -- general
--- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
--- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
--- -- specific
--- g_use_fifo : BOOLEAN := TRUE; -- use TRUE to break flow control between 1 to N and N to 1
--- g_use_complex : BOOLEAN := FALSE; -- needed when g_use_fifo=TRUE
--- g_pipeline : NATURAL := 1; -- 0 for combinatorial, > 0 for registers
--- g_nof_repeat : NATURAL := 5;
--- g_nof_streams : NATURAL := 4;
--- g_pkt_len : NATURAL := 11; -- should be multiple of g_nof_streams
--- g_pkt_gap : NATURAL := 0
+ -- -- general
+ -- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- -- specific
+ -- g_use_fifo : BOOLEAN := TRUE; -- use TRUE to break flow control between 1 to N and N to 1
+ -- g_use_complex : BOOLEAN := FALSE; -- needed when g_use_fifo=TRUE
+ -- g_pipeline : NATURAL := 1; -- 0 for combinatorial, > 0 for registers
+ -- g_nof_repeat : NATURAL := 5;
+ -- g_nof_streams : NATURAL := 4;
+ -- g_pkt_len : NATURAL := 11; -- should be multiple of g_nof_streams
+ -- g_pkt_gap : NATURAL := 0
--- g_pipeline
--- | g_nof_streams
--- | | g_pkt_len
--- | | | g_pkt_gap
--- | | | |
+ -- g_pipeline
+ -- | g_nof_streams
+ -- | | g_pkt_len
+ -- | | | g_pkt_gap
+ -- | | | |
u_act_act_pipe_1_12_0 : entity work.tb_dp_deinterleave_one_to_n_to_one generic map(e_active, e_active, true, false, 1, c_rep_act, 1, 12, 0);
u_act_act_pipe_2_12_0 : entity work.tb_dp_deinterleave_one_to_n_to_one generic map(e_active, e_active, true, false, 1, c_rep_act, 2, 12, 0);
u_act_act_pipe_3_12_0 : entity work.tb_dp_deinterleave_one_to_n_to_one generic map(e_active, e_active, true, false, 1, c_rep_act, 3, 12, 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_demux.vhd
index a027706fbe..e6ee1e777c 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_demux.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_demux is
end tb_tb_dp_demux;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_distribute.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_distribute.vhd
index 50a0a330ec..d2c514b056 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_distribute.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_distribute.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_distribute is
end tb_tb_dp_distribute;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_example_dut.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_example_dut.vhd
index df13417b87..1efeea0fb3 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_example_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_example_dut.vhd
@@ -21,15 +21,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.tb_dp_pkg.all;
--- Purpose: Verify multiple variations of tb_dp_example_dut
--- Description:
--- Usage:
--- > as 6
--- > run -all
+ -- Purpose: Verify multiple variations of tb_dp_example_dut
+ -- Description:
+ -- Usage:
+ -- > as 6
+ -- > run -all
entity tb_tb_dp_example_dut is
end tb_tb_dp_example_dut;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd
index 3da7df71ce..b69f88be9f 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
--- Purpose: Verify multiple variations of tb_dp_example_no_dut
--- Description:
--- Usage:
--- > as 3
--- > run -all
+ -- Purpose: Verify multiple variations of tb_dp_example_no_dut
+ -- Description:
+ -- Usage:
+ -- > as 3
+ -- > run -all
entity tb_tb_dp_example_no_dut is
end tb_tb_dp_example_no_dut;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc.vhd
index 46f94d01c3..15a6e05175 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_fifo_dc is
end tb_tb_dp_fifo_dc;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
index 2df85ef7d2..904582f01e 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
@@ -24,7 +24,7 @@
-- Purpose: Test multiple instances of tb_dp_fifo_dc_arr.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_fifo_dc_arr is
end tb_tb_dp_fifo_dc_arr;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd
index 71f4afcd32..65e2a9a9d2 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_fifo_dc_mixed_widths is
end tb_tb_dp_fifo_dc_mixed_widths;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill.vhd
index 8bed5bd937..d32a7e48d8 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_fifo_fill is
end tb_tb_dp_fifo_fill;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
index 4c793ad522..d4e80e07fd 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
@@ -35,7 +35,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_fifo_fill_eop is
end tb_tb_dp_fifo_fill_eop;
@@ -71,5 +71,5 @@ begin
u_dut_dc_0_rand_no_gap : entity work.tb_dp_fifo_fill_eop generic map (g_dut_use_dual_clock => true, g_dut_fifo_rl => 0, g_dut_use_random_ctrl => true, g_dut_use_gap => false);
u_dut_sc_1_blk_gt_fill : entity work.tb_dp_fifo_fill_eop generic map (g_dut_use_dual_clock => false, g_dut_fifo_rl => 1, g_dut_use_random_ctrl => false, g_dut_use_gap => false,
- g_dut_fifo_fill => 10, g_block_size => 20);
+ g_dut_fifo_fill => 10, g_block_size => 20);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd
index c6711c48e2..5c8c4c450f 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_fifo_fill_sc is
end tb_tb_dp_fifo_fill_sc;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_info.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_info.vhd
index 3a1e772519..febc15f3c0 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_info.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_info.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
--- Purpose: Verify multiple variations of tb_dp_fifo_info
--- Description:
--- Usage:
--- > as 3
--- > run -all
+ -- Purpose: Verify multiple variations of tb_dp_fifo_info
+ -- Description:
+ -- Usage:
+ -- > as 3
+ -- > run -all
entity tb_tb_dp_fifo_info is
end tb_tb_dp_fifo_info;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_sc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_sc.vhd
index fbfee60637..1df867cd50 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_sc.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_fifo_sc is
end tb_tb_dp_fifo_sc;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd
index 1a43d7cf57..a2664138d4 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
--- Purpose: Verify multiple variations of tb_dp_flush
--- Description:
--- Usage:
--- > as 2
--- > run -all
+ -- Purpose: Verify multiple variations of tb_dp_flush
+ -- Description:
+ -- Usage:
+ -- > as 2
+ -- > run -all
entity tb_tb_dp_flush is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_frame_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_frame_scheduler.vhd
index 7b3a6d8112..d3e6351d24 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_frame_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_frame_scheduler.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_frame_scheduler is
end tb_tb_dp_frame_scheduler;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd
index b2d70fca28..702dbb18c1 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_latency_fifo is
end tb_tb_dp_latency_fifo;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_mux.vhd
index 582a55eaed..48ac61cc4d 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_mux.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_mux is
end tb_tb_dp_mux;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_offload_tx_v3.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_offload_tx_v3.vhd
index 615f42cfd5..4111671414 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_offload_tx_v3.vhd
@@ -24,8 +24,8 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all; -- for t_dp_flow_control_enum
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all; -- for t_dp_flow_control_enum
entity tb_tb_dp_offload_tx_v3 is
end tb_tb_dp_offload_tx_v3;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet.vhd
index ed199b8dbb..ac112b4ca8 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
--- Purpose: Verify multiple variations of tb_dp_packet
--- Description:
--- Usage:
--- > as 2
--- > run -all
+ -- Purpose: Verify multiple variations of tb_dp_packet
+ -- Description:
+ -- Usage:
+ -- > as 2
+ -- > run -all
entity tb_tb_dp_packet is
end tb_tb_dp_packet;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd
index 46fbd725ba..d8cd0de0d1 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
--- Purpose: Verify multiple variations of tb_dp_packet_merge
--- Description:
--- Usage:
--- > as 3
--- > run -all
+ -- Purpose: Verify multiple variations of tb_dp_packet_merge
+ -- Description:
+ -- Usage:
+ -- > as 3
+ -- > run -all
entity tb_tb_dp_packet_merge is
end tb_tb_dp_packet_merge;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_packetizing.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_packetizing.vhd
index f7df2030e1..66b91bcd8a 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_packetizing.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_packetizing.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_packetizing is
end tb_tb_dp_packetizing;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_pad_insert_remove.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_pad_insert_remove.vhd
index b44aa851f6..9bb7703ff6 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_pad_insert_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_pad_insert_remove.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_pad_insert_remove is
end tb_tb_dp_pad_insert_remove;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline.vhd
index bf7764dd7a..6a39dfd74a 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
--- > as 3
--- > run -all --> OK
+ -- > as 3
+ -- > run -all --> OK
entity tb_tb_dp_pipeline is
end tb_tb_dp_pipeline;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline_ready.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline_ready.vhd
index 78c897f854..e53dc97073 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline_ready.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline_ready.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
--- > as 2
--- > run -all --> OK
+ -- > as 2
+ -- > run -all --> OK
entity tb_tb_dp_pipeline_ready is
end tb_tb_dp_pipeline_ready;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd
index f61ac82582..be111156cf 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd
@@ -21,15 +21,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-
--- Purpose: Verify multiple variations of tb_dp_repack_data
--- Description:
--- Usage:
--- > as 6
--- > run -all
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+
+ -- Purpose: Verify multiple variations of tb_dp_repack_data
+ -- Description:
+ -- Usage:
+ -- > as 6
+ -- > run -all
entity tb_tb_dp_repack_data is
end tb_tb_dp_repack_data;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data.vhd
index 5ac3ae84d2..8df924bf76 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data.vhd
@@ -26,8 +26,8 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_reverse_n_data is
end tb_tb_dp_reverse_n_data;
@@ -37,15 +37,15 @@ architecture tb of tb_tb_dp_reverse_n_data is
constant c_rep_act : natural := 3;
begin
--- g_pipeline : NATURAL := 1; -- 0 for combinatorial, > 0 for registers
--- g_nof_repeat : NATURAL := 5;
--- g_reverse_len : NATURAL := 4;
--- g_pkt_gap : NATURAL := 0
+ -- g_pipeline : NATURAL := 1; -- 0 for combinatorial, > 0 for registers
+ -- g_nof_repeat : NATURAL := 5;
+ -- g_reverse_len : NATURAL := 4;
+ -- g_pkt_gap : NATURAL := 0
--- g_pipeline
--- | g_reverse_len
--- | | g_pkt_gap
--- | | |
+ -- g_pipeline
+ -- | g_reverse_len
+ -- | | g_pkt_gap
+ -- | | |
u_pipe_1_0 : entity work.tb_dp_reverse_n_data generic map(1, c_rep_act, 1, 0);
u_comb_2_0 : entity work.tb_dp_reverse_n_data generic map(0, c_rep_act, 2, 0);
u_pipe_2_0 : entity work.tb_dp_reverse_n_data generic map(1, c_rep_act, 2, 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data_fc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data_fc.vhd
index 85ad8c0022..e598ed20e6 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data_fc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data_fc.vhd
@@ -26,8 +26,8 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_reverse_n_data_fc is
end tb_tb_dp_reverse_n_data_fc;
@@ -38,19 +38,19 @@ architecture tb of tb_tb_dp_reverse_n_data_fc is
constant c_rep_act : natural := 3;
constant c_rep_rnd : natural := 100;
begin
--- -- general
--- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
--- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
--- -- specific
--- g_pipeline : NATURAL := 1; -- 0 for combinatorial, > 0 for registers
--- g_nof_repeat : NATURAL := 5;
--- g_reverse_len : NATURAL := 4;
--- g_pkt_gap : NATURAL := 0
+ -- -- general
+ -- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- -- specific
+ -- g_pipeline : NATURAL := 1; -- 0 for combinatorial, > 0 for registers
+ -- g_nof_repeat : NATURAL := 5;
+ -- g_reverse_len : NATURAL := 4;
+ -- g_pkt_gap : NATURAL := 0
--- g_pipeline
--- | g_reverse_len
--- | | g_pkt_gap
--- | | |
+ -- g_pipeline
+ -- | g_reverse_len
+ -- | | g_pkt_gap
+ -- | | |
u_act_act_pipe_1_0 : entity work.tb_dp_reverse_n_data_fc generic map(e_active, e_active, 1, c_rep_act, 1, 0);
u_act_act_pipe_2_0 : entity work.tb_dp_reverse_n_data_fc generic map(e_active, e_active, 1, c_rep_act, 2, 0);
u_act_act_pipe_4_7 : entity work.tb_dp_reverse_n_data_fc generic map(e_active, e_active, 1, c_rep_act, 4, 7);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd
index 484aa4dba3..882b283b44 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd
@@ -28,8 +28,8 @@
-- > run -all --> OK
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_rsn_source is
end tb_tb_dp_rsn_source;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_split.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_split.vhd
index c57e02ba18..40c1565fae 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_split.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_split.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_split is
end tb_tb_dp_split;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd
index c7195a0344..0885cdf14c 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd
@@ -26,7 +26,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_strobe_total_count is
end tb_tb_dp_strobe_total_count;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_checker.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_checker.vhd
index 155a8c4c9d..866f36ddcc 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_checker.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_checker.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
--- Purpose: Verify multiple variations of tb_dp_sync_checker
--- Description:
--- Usage:
--- > as 3
--- > run -all
+ -- Purpose: Verify multiple variations of tb_dp_sync_checker
+ -- Description:
+ -- Usage:
+ -- > as 3
+ -- > run -all
entity tb_tb_dp_sync_checker is
end tb_tb_dp_sync_checker;
@@ -37,18 +37,18 @@ architecture tb of tb_tb_dp_sync_checker is
constant c_nof_repeat : natural := 100;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- -- general
--- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
--- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
--- -- specific
--- g_in_dat_w : NATURAL := 32;
--- g_in_nof_words : NATURAL := 1;
--- g_nof_repeat : NATURAL := 100;
--- g_pkt_len : NATURAL := 16; -- must be a multiple of g_in_nof_words
--- g_pkt_gap : NATURAL := 0;
--- g_sync_period : NATURAL := 16; -- The sync period generated in the stimuli.
--- -- DUT
--- g_nof_blk_per_sync : POSITIVE := 16 -- The sync period as expected by the sync_checker
+ -- -- general
+ -- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- -- specific
+ -- g_in_dat_w : NATURAL := 32;
+ -- g_in_nof_words : NATURAL := 1;
+ -- g_nof_repeat : NATURAL := 100;
+ -- g_pkt_len : NATURAL := 16; -- must be a multiple of g_in_nof_words
+ -- g_pkt_gap : NATURAL := 0;
+ -- g_sync_period : NATURAL := 16; -- The sync period generated in the stimuli.
+ -- -- DUT
+ -- g_nof_blk_per_sync : POSITIVE := 16 -- The sync period as expected by the sync_checker
u_sync_ok : entity work.tb_dp_sync_checker generic map(e_active, e_active, 16, 1, c_nof_repeat, 16, 0, 16, 16);
u_sync_early : entity work.tb_dp_sync_checker generic map(e_active, e_active, 16, 1, c_nof_repeat, 16, 0, 14, 16);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert.vhd
index bb53bc054a..20a4dbd4f0 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
--- Purpose: Verify multiple variations of tb_dp_sync_insert
--- Description:
--- Usage:
--- > as 3
--- > run -all
+ -- Purpose: Verify multiple variations of tb_dp_sync_insert
+ -- Description:
+ -- Usage:
+ -- > as 3
+ -- > run -all
entity tb_tb_dp_sync_insert is
end tb_tb_dp_sync_insert;
@@ -36,13 +36,13 @@ architecture tb of tb_tb_dp_sync_insert is
constant c_nof_repeat : natural := 100;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- g_block_size_input : NATURAL := 16;
--- g_nof_blk_per_sync_input : NATURAL := 32;
--- g_gap_size_during_block : NATURAL := 0;
--- g_gap_size_between_block : NATURAL := 0;
--- g_nof_data_per_block : NATURAL := 8;
--- g_nof_blk_per_sync : NATURAL := 4;
--- g_nof_repeat : NATURAL := 14
+ -- g_block_size_input : NATURAL := 16;
+ -- g_nof_blk_per_sync_input : NATURAL := 32;
+ -- g_gap_size_during_block : NATURAL := 0;
+ -- g_gap_size_between_block : NATURAL := 0;
+ -- g_nof_data_per_block : NATURAL := 8;
+ -- g_nof_blk_per_sync : NATURAL := 4;
+ -- g_nof_repeat : NATURAL := 14
u_no_gaps : entity work.tb_dp_sync_insert generic map(16, 32, 0, 0, 8, 4, 14);
u_no_gap : entity work.tb_dp_sync_insert generic map(16, 32, 1, 3, 8, 4, 14);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
index 78b416f87b..65d8820dc7 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
@@ -28,7 +28,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_sync_insert_v2 is
end tb_tb_dp_sync_insert_v2;
@@ -36,14 +36,14 @@ end tb_tb_dp_sync_insert_v2;
architecture tb of tb_tb_dp_sync_insert_v2 is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- g_nof_streams : NATURAL := 2;
--- g_block_size_input : NATURAL := 16;
--- g_nof_blk_per_sync_input : NATURAL := 32;
--- g_gap_size_during_block : NATURAL := 0;
--- g_gap_size_between_block : NATURAL := 0;
--- g_nof_blk_per_sync : NATURAL := 8;
--- g_nof_blk_per_sync_min : NATURAL := 2;
--- g_nof_repeat : NATURAL := 14
+ -- g_nof_streams : NATURAL := 2;
+ -- g_block_size_input : NATURAL := 16;
+ -- g_nof_blk_per_sync_input : NATURAL := 32;
+ -- g_gap_size_during_block : NATURAL := 0;
+ -- g_gap_size_between_block : NATURAL := 0;
+ -- g_nof_blk_per_sync : NATURAL := 8;
+ -- g_nof_blk_per_sync_min : NATURAL := 2;
+ -- g_nof_repeat : NATURAL := 14
u_no_gaps : entity work.tb_dp_sync_insert_v2 generic map(2, 16, 32, 0, 0, 8, 2, 14);
u_gap : entity work.tb_dp_sync_insert_v2 generic map(2, 16, 32, 1, 3, 8, 2, 14);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd
index 31fedc8eb4..c5299f698b 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd
@@ -28,7 +28,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_dp_sync_recover is
end tb_tb_dp_sync_recover;
@@ -36,14 +36,14 @@ end tb_tb_dp_sync_recover;
architecture tb of tb_tb_dp_sync_recover is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- g_nof_data_per_block : NATURAL := 16;
--- g_nof_blk_per_sync : NATURAL := 8;
--- g_gap_size_during_block : NATURAL := 0;
--- g_gap_size_between_block : NATURAL := 0;
--- g_init_bsn : NATURAL := 23;
--- g_bsn_at_restart : NATURAL := 40; -- the bsn index at which to restart the dut.
--- g_dut_latency : NATURAL := 25;
--- g_nof_repeat : NATURAL := 14
+ -- g_nof_data_per_block : NATURAL := 16;
+ -- g_nof_blk_per_sync : NATURAL := 8;
+ -- g_gap_size_during_block : NATURAL := 0;
+ -- g_gap_size_between_block : NATURAL := 0;
+ -- g_init_bsn : NATURAL := 23;
+ -- g_bsn_at_restart : NATURAL := 40; -- the bsn index at which to restart the dut.
+ -- g_dut_latency : NATURAL := 25;
+ -- g_nof_repeat : NATURAL := 14
u_no_gaps : entity work.tb_dp_sync_recover generic map(16, 8, 0, 0, 3, 50, 10, 14);
u_gap : entity work.tb_dp_sync_recover generic map(16, 8, 1, 3, 3, 50, 10, 14);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_throttle_xon.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_throttle_xon.vhd
index 6b9190e152..35f0ef7d8d 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_throttle_xon.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_throttle_xon.vhd
@@ -29,8 +29,8 @@
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_throttle_xon is
end tb_tb_dp_throttle_xon;
@@ -41,15 +41,15 @@ begin
-- > as 3
-- > run -all --> OK
--- -- general
--- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random flow control
--- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random flow control
--- -- specific
--- g_restart_at_sync : BOOLEAN := FALSE; -- if true restart xon control at each snk_in_sync, else and start at first valid and never restart
--- g_block_size : NATURAL := 10; -- number of valid data per block marked by sop and eop
--- g_nof_block_on : NATURAL := 13; -- number of blocks that snk_out.xon is active
--- g_nof_block_per_sync : NATURAL := 10;
--- g_nof_clk_off : NATURAL := 37 -- must be > g_block_size, number of clock cycles that snk_out.xon is kept inactive
+ -- -- general
+ -- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random flow control
+ -- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random flow control
+ -- -- specific
+ -- g_restart_at_sync : BOOLEAN := FALSE; -- if true restart xon control at each snk_in_sync, else and start at first valid and never restart
+ -- g_block_size : NATURAL := 10; -- number of valid data per block marked by sop and eop
+ -- g_nof_block_on : NATURAL := 13; -- number of blocks that snk_out.xon is active
+ -- g_nof_block_per_sync : NATURAL := 10;
+ -- g_nof_clk_off : NATURAL := 37 -- must be > g_block_size, number of clock cycles that snk_out.xon is kept inactive
u_act_xon_shorter_than_sync_interval : entity work.tb_dp_throttle_xon generic map (e_active, e_active, false, 20, 7, 10, 37);
u_act_xon_equal_to_sync_interval : entity work.tb_dp_throttle_xon generic map (e_active, e_active, false, 20, 10, 10, 37);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_xonoff.vhd
index cfa9826d63..cc4821e956 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_xonoff.vhd
@@ -29,8 +29,8 @@
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_dp_xonoff is
end tb_tb_dp_xonoff;
@@ -43,16 +43,16 @@ begin
-- > as 3
-- > run -all --> OK
--- -- general
--- g_flow_control_stimuli : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
--- g_flow_control_verify : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
--- -- specific
--- g_in_dat_w : NATURAL := 32;
--- g_in_nof_words : NATURAL := 1;
--- g_nof_repeat : NATURAL := 1000;
--- g_nof_dut : NATURAL := 10;
--- g_pkt_len : NATURAL := 5; -- must be a multiple of g_in_nof_words
--- g_pkt_gap : NATURAL := 4
+ -- -- general
+ -- g_flow_control_stimuli : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
+ -- g_flow_control_verify : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
+ -- -- specific
+ -- g_in_dat_w : NATURAL := 32;
+ -- g_in_nof_words : NATURAL := 1;
+ -- g_nof_repeat : NATURAL := 1000;
+ -- g_nof_dut : NATURAL := 10;
+ -- g_pkt_len : NATURAL := 5; -- must be a multiple of g_in_nof_words
+ -- g_pkt_gap : NATURAL := 4
u_act_act : entity work.tb_dp_xonoff generic map (e_active, e_active, 32, 1, c_rep, 10, 5, 1);
u_rnd_rnd_1 : entity work.tb_dp_xonoff generic map (e_random, e_random, 32, 1, c_rep, 1, 5, 3);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
index 9d05799188..bd12889359 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
@@ -24,8 +24,8 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_mmp_dp_bsn_align_v2 is
end tb_tb_mmp_dp_bsn_align_v2;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
index bdde22c2c0..534aec3a7b 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_mms_dp_force_data_parallel_arr is
end tb_tb_mms_dp_force_data_parallel_arr;
@@ -37,20 +37,20 @@ end tb_tb_mms_dp_force_data_parallel_arr;
architecture tb of tb_tb_mms_dp_force_data_parallel_arr is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
--- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random verify ready flow control
--- g_nof_streams : NATURAL := 1; -- >= 1
--- g_dat_w : NATURAL := 32; -- must be <= 32 to fit INTEGER range
--- g_force_stream : INTEGER := 0; -- must be < g_nof_streams, force data on this stream
--- g_force_data : INTEGER := -1;
--- g_force_re : INTEGER := 2;
--- g_force_im : INTEGER := -3;
--- g_increment_data : INTEGER := 0;
--- g_increment_re : INTEGER := 0;
--- g_increment_im : INTEGER := 0;
--- g_increment_on_sop : BOOLEAN := FALSE; -- in this tb use same generic for data, re, im
--- g_restart_on_sync : BOOLEAN := FALSE; -- in this tb use same generic for data, re, im
--- g_restart_on_sop : BOOLEAN := FALSE -- in this tb use same generic for data, re, im
+ -- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
+ -- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random verify ready flow control
+ -- g_nof_streams : NATURAL := 1; -- >= 1
+ -- g_dat_w : NATURAL := 32; -- must be <= 32 to fit INTEGER range
+ -- g_force_stream : INTEGER := 0; -- must be < g_nof_streams, force data on this stream
+ -- g_force_data : INTEGER := -1;
+ -- g_force_re : INTEGER := 2;
+ -- g_force_im : INTEGER := -3;
+ -- g_increment_data : INTEGER := 0;
+ -- g_increment_re : INTEGER := 0;
+ -- g_increment_im : INTEGER := 0;
+ -- g_increment_on_sop : BOOLEAN := FALSE; -- in this tb use same generic for data, re, im
+ -- g_restart_on_sync : BOOLEAN := FALSE; -- in this tb use same generic for data, re, im
+ -- g_restart_on_sop : BOOLEAN := FALSE -- in this tb use same generic for data, re, im
u_act_force_data_one_stream : entity work.tb_mms_dp_force_data_parallel_arr generic map (e_active, e_active, 1, 16, 0, -1, 2, -3, 0, 0, 0, false, false, false);
u_act_force_data_incr_stream : entity work.tb_mms_dp_force_data_parallel_arr generic map (e_active, e_active, 1, 16, 0, -1, 2, -3, 1, 1, 1, false, false, false);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd
index b406e3c7e6..5263eb3143 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_mms_dp_force_data_serial_arr is
end tb_tb_mms_dp_force_data_serial_arr;
@@ -37,18 +37,18 @@ end tb_tb_mms_dp_force_data_serial_arr;
architecture tb of tb_tb_mms_dp_force_data_serial_arr is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
--- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random verify ready flow control
--- g_nof_streams : NATURAL := 1; -- >= 1
--- g_dat_w : NATURAL := 5; -- must be <= 32 to fit INTEGER range
--- g_force_stream : INTEGER := 0; -- must be < g_nof_streams, force data on this stream
--- g_force_value : BOOLEAN := TRUE; -- when TRUE force value at index, else pass on snk_in at index
--- g_force_index : NATURAL := 3; -- sample index or block index in time dependent on g_index_sample_block_n
--- g_force_data : INTEGER := -1;
--- g_force_re : INTEGER := 2;
--- g_force_im : INTEGER := -3;
--- g_index_period : NATURAL := 17; -- number of indices in time, must be <= 2*31 to fit in NATURAL range
--- g_index_sample_block_n : BOOLEAN := TRUE -- when TRUE sample index in block, else block index in sync interval
+ -- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
+ -- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random verify ready flow control
+ -- g_nof_streams : NATURAL := 1; -- >= 1
+ -- g_dat_w : NATURAL := 5; -- must be <= 32 to fit INTEGER range
+ -- g_force_stream : INTEGER := 0; -- must be < g_nof_streams, force data on this stream
+ -- g_force_value : BOOLEAN := TRUE; -- when TRUE force value at index, else pass on snk_in at index
+ -- g_force_index : NATURAL := 3; -- sample index or block index in time dependent on g_index_sample_block_n
+ -- g_force_data : INTEGER := -1;
+ -- g_force_re : INTEGER := 2;
+ -- g_force_im : INTEGER := -3;
+ -- g_index_period : NATURAL := 17; -- number of indices in time, must be <= 2*31 to fit in NATURAL range
+ -- g_index_sample_block_n : BOOLEAN := TRUE -- when TRUE sample index in block, else block index in sync interval
u_act_force_data_value_sample_one_stream : entity work.tb_mms_dp_force_data_serial_arr generic map (e_active, e_active, 1, 16, 0, true, 7, -1, 2, -3, 17, true);
u_rnd_force_data_value_sample_stream0 : entity work.tb_mms_dp_force_data_serial_arr generic map (e_random, e_random, 3, 16, 0, true, 7, -1, 2, -3, 17, true);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_arr.vhd
index 0902c69d97..45e1dbbdb5 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_arr.vhd
@@ -28,9 +28,9 @@
-- > run -all
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_tb_mms_dp_gain_arr is
end tb_tb_mms_dp_gain_arr;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_serial_arr.vhd
index 96e76fd8d6..03c78df51d 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_serial_arr.vhd
@@ -27,9 +27,9 @@
-- > run -all
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.tb_dp_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_tb_mms_dp_gain_serial_arr is
end tb_tb_mms_dp_gain_serial_arr;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_tb_dp_backpressure.vhd b/libraries/base/dp/tb/vhdl/tb_tb_tb_dp_backpressure.vhd
index 0b9f0629d4..3726781485 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_tb_dp_backpressure.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_tb_dp_backpressure.vhd
@@ -29,9 +29,9 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_tb_tb_dp_backpressure is
end tb_tb_tb_dp_backpressure;
diff --git a/libraries/base/mm/src/vhdl/mm_arbiter.vhd b/libraries/base/mm/src/vhdl/mm_arbiter.vhd
index 0fe99f1a06..7c616dc3b2 100644
--- a/libraries/base/mm/src/vhdl/mm_arbiter.vhd
+++ b/libraries/base/mm/src/vhdl/mm_arbiter.vhd
@@ -22,9 +22,9 @@
-- Purpose: VHDL wrapper for wbs_arbiter.v
library IEEE, technology_lib, tech_fifo_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mm_arbiter is
generic (
@@ -52,56 +52,56 @@ architecture str of mm_arbiter is
-- Wishbone Arbiter
----------------------------------------------------------------------------
component wbs_arbiter
- generic(
- NUM_SLAVES : natural;
- SLAVE_ADDR : std_logic_vector; -- NUM_SLAVES concatenated 32b integers
- SLAVE_HIGH : std_logic_vector; -- NUM_SLAVES concatenated 32b integers
- TIMEOUT : natural
- );
- port (
- wb_clk_i : in std_logic;
- wb_rst_i : in std_logic;
+ generic(
+ NUM_SLAVES : natural;
+ SLAVE_ADDR : std_logic_vector; -- NUM_SLAVES concatenated 32b integers
+ SLAVE_HIGH : std_logic_vector; -- NUM_SLAVES concatenated 32b integers
+ TIMEOUT : natural
+ );
+ port (
+ wb_clk_i : in std_logic;
+ wb_rst_i : in std_logic;
- wbm_cyc_i : in std_logic;
- wbm_stb_i : in std_logic;
- wbm_we_i : in std_logic;
- wbm_sel_i : in std_logic_vector( 4 - 1 downto 0);
- wbm_adr_i : in std_logic_vector(c_word_w - 1 downto 0);
- wbm_dat_i : in std_logic_vector(c_word_w - 1 downto 0);
- wbm_dat_o : out std_logic_vector(c_word_w - 1 downto 0);
- wbm_ack_o : out std_logic;
- wbm_err_o : out std_logic;
+ wbm_cyc_i : in std_logic;
+ wbm_stb_i : in std_logic;
+ wbm_we_i : in std_logic;
+ wbm_sel_i : in std_logic_vector( 4 - 1 downto 0);
+ wbm_adr_i : in std_logic_vector(c_word_w - 1 downto 0);
+ wbm_dat_i : in std_logic_vector(c_word_w - 1 downto 0);
+ wbm_dat_o : out std_logic_vector(c_word_w - 1 downto 0);
+ wbm_ack_o : out std_logic;
+ wbm_err_o : out std_logic;
- wbs_cyc_o : out std_logic_vector(g_nof_slaves - 1 downto 0);
- wbs_stb_o : out std_logic_vector(g_nof_slaves - 1 downto 0);
- wbs_we_o : out std_logic;
- wbs_sel_o : out std_logic_vector( 4 - 1 downto 0);
- wbs_adr_o : out std_logic_vector(c_word_w - 1 downto 0);
- wbs_dat_o : out std_logic_vector(c_word_w - 1 downto 0);
- wbs_dat_i : in std_logic_vector(g_nof_slaves * c_word_w - 1 downto 0);
- wbs_ack_i : in std_logic_vector(g_nof_slaves - 1 downto 0)
- );
+ wbs_cyc_o : out std_logic_vector(g_nof_slaves - 1 downto 0);
+ wbs_stb_o : out std_logic_vector(g_nof_slaves - 1 downto 0);
+ wbs_we_o : out std_logic;
+ wbs_sel_o : out std_logic_vector( 4 - 1 downto 0);
+ wbs_adr_o : out std_logic_vector(c_word_w - 1 downto 0);
+ wbs_dat_o : out std_logic_vector(c_word_w - 1 downto 0);
+ wbs_dat_i : in std_logic_vector(g_nof_slaves * c_word_w - 1 downto 0);
+ wbs_ack_i : in std_logic_vector(g_nof_slaves - 1 downto 0)
+ );
end component;
--- input wb_clk_i, wb_rst_i;
---
--- input wbm_cyc_i;
--- input wbm_stb_i;
--- input wbm_we_i;
--- input [3:0] wbm_sel_i;
--- input [31:0] wbm_adr_i;
--- input [31:0] wbm_dat_i;
--- output [31:0] wbm_dat_o;
--- output wbm_ack_o;
--- output wbm_err_o;
---
--- output [NUM_SLAVES - 1:0] wbs_cyc_o;
--- output [NUM_SLAVES - 1:0] wbs_stb_o;
--- output wbs_we_o;
--- output [3:0] wbs_sel_o;
--- output [31:0] wbs_adr_o;
--- output [31:0] wbs_dat_o;
--- input [NUM_SLAVES*32 - 1:0] wbs_dat_i;
--- input [NUM_SLAVES - 1:0] wbs_ack_i;
+ -- input wb_clk_i, wb_rst_i;
+ --
+ -- input wbm_cyc_i;
+ -- input wbm_stb_i;
+ -- input wbm_we_i;
+ -- input [3:0] wbm_sel_i;
+ -- input [31:0] wbm_adr_i;
+ -- input [31:0] wbm_dat_i;
+ -- output [31:0] wbm_dat_o;
+ -- output wbm_ack_o;
+ -- output wbm_err_o;
+ --
+ -- output [NUM_SLAVES - 1:0] wbs_cyc_o;
+ -- output [NUM_SLAVES - 1:0] wbs_stb_o;
+ -- output wbs_we_o;
+ -- output [3:0] wbs_sel_o;
+ -- output [31:0] wbs_adr_o;
+ -- output [31:0] wbs_dat_o;
+ -- input [NUM_SLAVES*32 - 1:0] wbs_dat_i;
+ -- input [NUM_SLAVES - 1:0] wbs_ack_i;
----------------------------------------------------------------------------
-- wbs_arbiter i/o signals
@@ -156,7 +156,7 @@ architecture str of mm_arbiter is
type t_wb_miso is record -- Master In Slave Out
dat : std_logic_vector(c_word_w - 1 downto 0);
ack : std_logic;
--- err : STD_LOGIC;
+ -- err : STD_LOGIC;
end record;
type t_wb_miso_arr is array (integer range <>) of t_wb_miso;
@@ -165,34 +165,34 @@ architecture str of mm_arbiter is
signal wbs_mosi_arr : t_wb_mosi_arr(g_nof_slaves - 1 downto 0);
signal wbs_miso_arr : t_wb_miso_arr(g_nof_slaves - 1 downto 0);
begin
--- wbs_arbiter #(
--- .NUM_SLAVES (N_WB_SLAVES),
--- .SLAVE_ADDR (SLAVE_BASE),
--- .SLAVE_HIGH (SLAVE_HIGH),
--- .TIMEOUT (1024)
--- ) wbs_arbiter_inst (
--- .wb_clk_i (wb_clk_i), //mm_clk
--- .wb_rst_i (wb_rst_i), //mm_rst
---
--- .wbm_cyc_i (wbm_cyc_o),//
--- .wbm_stb_i (wbm_stb_o),//
--- .wbm_we_i (wbm_we_o), //master_mosi.wr
--- .wbm_sel_i (wbm_sel_o),//byte select, one hot.
--- .wbm_adr_i (wbm_adr_o),//master_mosi.address
--- .wbm_dat_i (wbm_dat_o),//master_miso.data
--- .wbm_dat_o (wbm_dat_i),//master_mosi.data
--- .wbm_ack_o (wbm_ack_i),//master_miso.rdval
--- .wbm_err_o (wbm_err_i),//
---
--- .wbs_cyc_o (wbs_cyc_o),//
--- .wbs_stb_o (wbs_stb_o),//
--- .wbs_we_o (wbs_we_o), //Write not read.
--- .wbs_sel_o (wbs_sel_o),//Byte select, one hot.
--- .wbs_adr_o (wbs_adr_o),//slave_mosi.address
--- .wbs_dat_o (wbs_dat_o),//slave_mosi.data
--- .wbs_dat_i (wbs_dat_i),//slave_miso.data
--- .wbs_ack_i (wbs_ack_i) //slave_miso.rdval
--- );
+ -- wbs_arbiter #(
+ -- .NUM_SLAVES (N_WB_SLAVES),
+ -- .SLAVE_ADDR (SLAVE_BASE),
+ -- .SLAVE_HIGH (SLAVE_HIGH),
+ -- .TIMEOUT (1024)
+ -- ) wbs_arbiter_inst (
+ -- .wb_clk_i (wb_clk_i), //mm_clk
+ -- .wb_rst_i (wb_rst_i), //mm_rst
+ --
+ -- .wbm_cyc_i (wbm_cyc_o),//
+ -- .wbm_stb_i (wbm_stb_o),//
+ -- .wbm_we_i (wbm_we_o), //master_mosi.wr
+ -- .wbm_sel_i (wbm_sel_o),//byte select, one hot.
+ -- .wbm_adr_i (wbm_adr_o),//master_mosi.address
+ -- .wbm_dat_i (wbm_dat_o),//master_miso.data
+ -- .wbm_dat_o (wbm_dat_i),//master_mosi.data
+ -- .wbm_ack_o (wbm_ack_i),//master_miso.rdval
+ -- .wbm_err_o (wbm_err_i),//
+ --
+ -- .wbs_cyc_o (wbs_cyc_o),//
+ -- .wbs_stb_o (wbs_stb_o),//
+ -- .wbs_we_o (wbs_we_o), //Write not read.
+ -- .wbs_sel_o (wbs_sel_o),//Byte select, one hot.
+ -- .wbs_adr_o (wbs_adr_o),//slave_mosi.address
+ -- .wbs_dat_o (wbs_dat_o),//slave_mosi.data
+ -- .wbs_dat_i (wbs_dat_i),//slave_miso.data
+ -- .wbs_ack_i (wbs_ack_i) //slave_miso.rdval
+ -- );
----------------------------------------------------------------------------
-- Wire wbs_arbiter master side i/o to WB SLV array types
diff --git a/libraries/base/mm/src/vhdl/mm_bus.vhd b/libraries/base/mm/src/vhdl/mm_bus.vhd
index 6c6bf43ccb..3cd02235e0 100644
--- a/libraries/base/mm/src/vhdl/mm_bus.vhd
+++ b/libraries/base/mm/src/vhdl/mm_bus.vhd
@@ -104,9 +104,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mm_bus is
generic (
@@ -136,44 +136,44 @@ architecture str of mm_bus is
begin
-- MM bus
u_mm_bus_pipe : entity work.mm_bus_pipe
- generic map (
- g_nof_slaves => g_nof_slaves,
- g_base_arr => g_base_arr,
- g_width_arr => g_width_arr,
- g_rd_latency_arr => g_rd_latency_arr,
- g_waitrequest_arr => g_waitrequest_arr,
- g_pipeline_mosi => g_pipeline_mosi,
- g_pipeline_miso_rdval => g_pipeline_miso_rdval,
- g_pipeline_miso_wait => g_pipeline_miso_wait
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- master_mosi => master_mosi,
- master_miso => master_miso,
- slave_mosi_arr => bus_mosi_arr,
- slave_miso_arr => bus_miso_arr
- );
+ generic map (
+ g_nof_slaves => g_nof_slaves,
+ g_base_arr => g_base_arr,
+ g_width_arr => g_width_arr,
+ g_rd_latency_arr => g_rd_latency_arr,
+ g_waitrequest_arr => g_waitrequest_arr,
+ g_pipeline_mosi => g_pipeline_mosi,
+ g_pipeline_miso_rdval => g_pipeline_miso_rdval,
+ g_pipeline_miso_wait => g_pipeline_miso_wait
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ master_mosi => master_mosi,
+ master_miso => master_miso,
+ slave_mosi_arr => bus_mosi_arr,
+ slave_miso_arr => bus_miso_arr
+ );
-- The MM bus interface with the MM slaves
gen_slave_ports : for I in 0 to g_nof_slaves - 1 generate
-- Rewire not connected slaves and slave that do not need mosi flow control via miso.waitrequest
u_slave_enable : entity work.mm_slave_enable
- generic map (
- g_enable => g_slave_enable_arr(I),
- g_waitrequest => g_waitrequest_arr(I),
- g_rd_latency => g_rd_latency_arr(I)
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- -- MM input RL = 1
- in_mosi => bus_mosi_arr(I),
- in_miso => bus_miso_arr(I),
- -- MM output RL = 0
- out_mosi => slave_mosi_arr(I),
- out_miso => slave_miso_arr(I)
- );
+ generic map (
+ g_enable => g_slave_enable_arr(I),
+ g_waitrequest => g_waitrequest_arr(I),
+ g_rd_latency => g_rd_latency_arr(I)
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ -- MM input RL = 1
+ in_mosi => bus_mosi_arr(I),
+ in_miso => bus_miso_arr(I),
+ -- MM output RL = 0
+ out_mosi => slave_mosi_arr(I),
+ out_miso => slave_miso_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/mm/src/vhdl/mm_bus_comb.vhd b/libraries/base/mm/src/vhdl/mm_bus_comb.vhd
index eb27973b62..f37920029f 100644
--- a/libraries/base/mm/src/vhdl/mm_bus_comb.vhd
+++ b/libraries/base/mm/src/vhdl/mm_bus_comb.vhd
@@ -103,9 +103,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mm_bus_comb is
generic (
@@ -166,8 +166,8 @@ begin
if v_base = g_base_arr(I) / 2**g_width_arr(I) then
slave_index_arr(0) <= I; -- return index of addressed slave
exit; -- Found addressed slave, no need to loop further. EXIT is
- -- not realy needed, because there can only be one
- -- addressed slave so loop further will not change the index.
+ -- not realy needed, because there can only be one
+ -- addressed slave so loop further will not change the index.
end if;
end loop;
end process;
diff --git a/libraries/base/mm/src/vhdl/mm_fields.vhd b/libraries/base/mm/src/vhdl/mm_fields.vhd
index 6538f9f912..6607061a88 100644
--- a/libraries/base/mm/src/vhdl/mm_fields.vhd
+++ b/libraries/base/mm/src/vhdl/mm_fields.vhd
@@ -65,11 +65,11 @@
-- Remarks:
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
entity mm_fields is
generic (
@@ -98,11 +98,12 @@ end mm_fields;
architecture str of mm_fields is
constant c_reg_nof_words : natural := field_nof_words(g_field_arr, c_word_w);
- constant c_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_reg_nof_words),
- dat_w => c_word_w,
- nof_dat => c_reg_nof_words,
- init_sl => '0');
+ constant c_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_reg_nof_words),
+ dat_w => c_word_w,
+ nof_dat => c_reg_nof_words,
+ init_sl => '0');
constant c_slv_out_defaults : std_logic_vector(field_slv_out_len(g_field_arr) - 1 downto 0) := field_map_defaults(g_field_arr);
-- Map the default values onto c_init_reg
@@ -152,22 +153,22 @@ begin
-- Actual MM <-> SLV R/W functionality is provided by common_reg_r_w_dc
-----------------------------------------------------------------------------
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_readback => false,
- g_reg => c_reg,
- g_init_reg => c_init_reg
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => slv_rst,
- st_clk => slv_clk,
-
- sla_in => mm_mosi,
- sla_out => mm_miso,
-
- in_reg => reg_slv_in,
- out_reg => reg_slv_out
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_readback => false,
+ g_reg => c_reg,
+ g_init_reg => c_init_reg
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => slv_rst,
+ st_clk => slv_clk,
+
+ sla_in => mm_mosi,
+ sla_out => mm_miso,
+
+ in_reg => reg_slv_in,
+ out_reg => reg_slv_out
+ );
end str;
diff --git a/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd b/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd
index 558c420219..01ea94138f 100644
--- a/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd
+++ b/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd
@@ -33,9 +33,9 @@
-- cycle later due to the pipelining.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mm_latency_adapter is
generic (
@@ -80,22 +80,22 @@ begin
out_ready <= not out_miso.waitrequest;
u_rl : entity common_lib.common_rl_decrease
- generic map (
- g_adapt => g_adapt,
- g_dat_w => c_data_w
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- ST sink: RL = 1
- snk_out_ready => in_ready,
- snk_in_dat => in_data,
- snk_in_val => in_val,
- -- ST source: RL = 0
- src_in_ready => out_ready,
- src_out_dat => out_data,
- src_out_val => out_val
- );
+ generic map (
+ g_adapt => g_adapt,
+ g_dat_w => c_data_w
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- ST sink: RL = 1
+ snk_out_ready => in_ready,
+ snk_in_dat => in_data,
+ snk_in_val => in_val,
+ -- ST source: RL = 0
+ src_in_ready => out_ready,
+ src_out_dat => out_data,
+ src_out_val => out_val
+ );
out_mosi.address <= func_slv_extract(c_mem_address_w, c_mem_data_w, 1, 1, out_data, 0);
out_mosi.wrdata <= func_slv_extract(c_mem_address_w, c_mem_data_w, 1, 1, out_data, 1);
diff --git a/libraries/base/mm/src/vhdl/mm_master_mux.vhd b/libraries/base/mm/src/vhdl/mm_master_mux.vhd
index 0eb66110d9..203be91779 100644
--- a/libraries/base/mm/src/vhdl/mm_master_mux.vhd
+++ b/libraries/base/mm/src/vhdl/mm_master_mux.vhd
@@ -57,9 +57,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mm_master_mux is
generic (
@@ -103,9 +103,9 @@ begin
if master_mosi_arr(I).wr = '1' or master_mosi_arr(I).rd = '1' then
index <= I; -- index of active master
exit; -- Found active master, no need to loop further. EXIT is not
- -- realy needed, because there should be only one active
- -- master, and if there are more active masters, then it
- -- does not matter whether the first or the last is selected.
+ -- realy needed, because there should be only one active
+ -- master, and if there are more active masters, then it
+ -- does not matter whether the first or the last is selected.
end if;
end loop;
end process;
diff --git a/libraries/base/mm/src/vhdl/mm_pipeline.vhd b/libraries/base/mm/src/vhdl/mm_pipeline.vhd
index bef70460dd..7968eaece2 100644
--- a/libraries/base/mm/src/vhdl/mm_pipeline.vhd
+++ b/libraries/base/mm/src/vhdl/mm_pipeline.vhd
@@ -91,9 +91,9 @@
-- percent of throughput.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mm_pipeline is
generic (
diff --git a/libraries/base/mm/src/vhdl/mm_slave_enable.vhd b/libraries/base/mm/src/vhdl/mm_slave_enable.vhd
index dad3178dbd..c70daddd29 100644
--- a/libraries/base/mm/src/vhdl/mm_slave_enable.vhd
+++ b/libraries/base/mm/src/vhdl/mm_slave_enable.vhd
@@ -47,9 +47,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mm_slave_enable is
generic (
@@ -76,15 +76,15 @@ architecture rtl of mm_slave_enable is
begin
-- Use mosi.rd to create miso.rdval for unconnected slave or for slaves that do not support rdval
u_rdval : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => g_rd_latency
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- in_dat => rd,
- out_dat => rdval
- );
+ generic map (
+ g_pipeline => g_rd_latency
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ in_dat => rd,
+ out_dat => rdval
+ );
no_slave : if g_enable = false generate
out_mosi <= c_mem_mosi_rst;
diff --git a/libraries/base/mm/src/vhdl/mm_slave_mux.vhd b/libraries/base/mm/src/vhdl/mm_slave_mux.vhd
index 09459a54a9..959caa5874 100644
--- a/libraries/base/mm/src/vhdl/mm_slave_mux.vhd
+++ b/libraries/base/mm/src/vhdl/mm_slave_mux.vhd
@@ -30,9 +30,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mm_slave_mux is
generic (
@@ -51,17 +51,17 @@ end mm_slave_mux;
architecture str of mm_slave_mux is
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_broadcast => g_broadcast,
- g_nof_mosi => g_nof_mosi,
- g_mult_addr_w => g_mosi_addr_w,
- g_rd_latency => 0
- )
- port map (
- clk => '0', -- only used when g_rd_latency > 0
- mosi => mosi,
- miso => miso,
- mosi_arr => mosi_arr,
- miso_arr => miso_arr
- );
+ generic map (
+ g_broadcast => g_broadcast,
+ g_nof_mosi => g_nof_mosi,
+ g_mult_addr_w => g_mosi_addr_w,
+ g_rd_latency => 0
+ )
+ port map (
+ clk => '0', -- only used when g_rd_latency > 0
+ mosi => mosi,
+ miso => miso,
+ mosi_arr => mosi_arr,
+ miso_arr => miso_arr
+ );
end str;
diff --git a/libraries/base/mm/tb/vhdl/mm_file.vhd b/libraries/base/mm/tb/vhdl/mm_file.vhd
index f04fb7d4b0..5dbbb87511 100644
--- a/libraries/base/mm/tb/vhdl/mm_file.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file.vhd
@@ -77,16 +77,16 @@
-- speed (and stability).
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use work.mm_file_pkg.all;
-use IEEE.std_logic_textio.all;
-use std.textio.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use work.mm_file_pkg.all;
+ use IEEE.std_logic_textio.all;
+ use std.textio.all;
entity mm_file is
generic (
diff --git a/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd b/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
index c742fee221..e34ededa99 100644
--- a/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
@@ -113,95 +113,108 @@
-- all subsequent accesses will start at falling_edge(mm_clk)
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use std.textio.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use std.textio.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_str_pkg.all;
package mm_file_pkg is
-- Constants used by mm_file.vhd
constant c_mmf_mm_clk_period : time := 100 ps; -- Default mm_clk period in simulation. Set much faster than DP clock to speed up
- -- simulation of MM access. Without file IO throttling 100 ps is a good balance
- -- between simulation speed and file IO rate.
+ -- simulation of MM access. Without file IO throttling 100 ps is a good balance
+ -- between simulation speed and file IO rate.
constant c_mmf_mm_timeout : time := 1000 ns; -- Default MM file IO timeout period. Set large enough to account for MM-DP clock
- -- domain crossing delays. Use 0 ns to disable file IO throttling, to have file IO
- -- at the mm_clk rate.
+ -- domain crossing delays. Use 0 ns to disable file IO throttling, to have file IO
+ -- at the mm_clk rate.
constant c_mmf_mm_pause : time := 100 ns; -- Default MM file IO pause period after timeout. Balance between file IO rate
- -- reduction and responsiveness to new MM access.
+ -- reduction and responsiveness to new MM access.
-- Procedure to (re)create empty file
- procedure mmf_file_create(filename: in string);
+ procedure mmf_file_create(
+ filename: in string);
-- Procedure to perform an MM access from file
- procedure mmf_mm_from_file(signal mm_clk : in std_logic;
- signal mm_rst : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- rd_filename: in string;
- wr_filename: in string;
- rd_latency: in natural);
+ procedure mmf_mm_from_file(
+ signal mm_clk : in std_logic;
+ signal mm_rst : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ rd_filename: in string;
+ wr_filename: in string;
+ rd_latency: in natural);
-- Procedure to process a simulation status request from the .ctrl file and provide response via the .stat file
- procedure mmf_sim_ctrl_from_file(rd_filename: in string;
- wr_filename: in string);
+ procedure mmf_sim_ctrl_from_file(
+ rd_filename: in string;
+ wr_filename: in string);
-- Procedure to poll the simulation status
- procedure mmf_poll_sim_ctrl_file(rd_file_name: in string;
- wr_file_name: in string);
+ procedure mmf_poll_sim_ctrl_file(
+ rd_file_name: in string;
+ wr_file_name: in string);
-- Procedure to poll the simulation status
- procedure mmf_poll_sim_ctrl_file(signal mm_clk : in std_logic;
- rd_file_name: in string;
- wr_file_name: in string);
+ procedure mmf_poll_sim_ctrl_file(
+ signal mm_clk : in std_logic;
+ rd_file_name: in string;
+ wr_file_name: in string);
-- Procedures that keep reading the file until it has been made empty or not empty by some other program,
-- to ensure the file is ready for a new write access
- procedure mmf_wait_for_file_status(rd_filename : in string; -- file name with extension
- exit_on_empty : in boolean;
- signal mm_clk : in std_logic);
-
- procedure mmf_wait_for_file_empty(rd_filename : in string; -- file name with extension
- signal mm_clk : in std_logic);
- procedure mmf_wait_for_file_not_empty(rd_filename : in string; -- file name with extension
- signal mm_clk : in std_logic);
+ procedure mmf_wait_for_file_status(
+ rd_filename : in string; -- file name with extension
+ exit_on_empty : in boolean;
+ signal mm_clk : in std_logic);
+
+ procedure mmf_wait_for_file_empty(
+ rd_filename : in string; -- file name with extension
+ signal mm_clk : in std_logic);
+ procedure mmf_wait_for_file_not_empty(
+ rd_filename : in string; -- file name with extension
+ signal mm_clk : in std_logic);
-- Procedure to issue a write access via the MM request .ctrl file
- procedure mmf_mm_bus_wr(filename : in string; -- file name without extension
- wr_addr : in integer; -- use integer to support full 32 bit range
- wr_data : in integer;
- signal mm_clk : in std_logic);
+ procedure mmf_mm_bus_wr(
+ filename : in string; -- file name without extension
+ wr_addr : in integer; -- use integer to support full 32 bit range
+ wr_data : in integer;
+ signal mm_clk : in std_logic);
-- Procedure to issue a read access via the MM request .ctrl file and get the read data from the MM response file
- procedure mmf_mm_bus_rd(filename : in string; -- file name without extension
- rd_latency : in natural;
- rd_addr : in integer; -- use integer to support full 32 bit range
- signal rd_data : out std_logic_vector(c_word_w - 1 downto 0);
- signal mm_clk : in std_logic);
+ procedure mmf_mm_bus_rd(
+ filename : in string; -- file name without extension
+ rd_latency : in natural;
+ rd_addr : in integer; -- use integer to support full 32 bit range
+ signal rd_data : out std_logic_vector(c_word_w - 1 downto 0);
+ signal mm_clk : in std_logic);
-- . rd_latency = 1
- procedure mmf_mm_bus_rd(filename : in string;
- rd_addr : in integer;
- signal rd_data : out std_logic_vector(c_word_w - 1 downto 0);
- signal mm_clk : in std_logic);
+ procedure mmf_mm_bus_rd(
+ filename : in string;
+ rd_addr : in integer;
+ signal rd_data : out std_logic_vector(c_word_w - 1 downto 0);
+ signal mm_clk : in std_logic);
-- Procedure that reads the rd_data every rd_interval until has the specified rd_value, the proc arguments can be understood as a sentence
- procedure mmf_mm_wait_until_value(filename : in string; -- file name without extension
- rd_addr : in integer;
- c_representation : in string; -- treat rd_data as "SIGNED" or "UNSIGNED" 32 bit word
- signal rd_data : inout std_logic_vector(c_word_w - 1 downto 0);
- c_condition : in string; -- ">", ">=", "=", "<=", "<", "/="
- c_rd_value : in integer;
- c_rd_interval : in time;
- signal mm_clk : in std_logic);
+ procedure mmf_mm_wait_until_value(
+ filename : in string; -- file name without extension
+ rd_addr : in integer;
+ c_representation : in string; -- treat rd_data as "SIGNED" or "UNSIGNED" 32 bit word
+ signal rd_data : inout std_logic_vector(c_word_w - 1 downto 0);
+ c_condition : in string; -- ">", ">=", "=", "<=", "<", "/="
+ c_rd_value : in integer;
+ c_rd_interval : in time;
+ signal mm_clk : in std_logic);
-- Procedure to get NOW via simulator status
- procedure mmf_sim_get_now(filename : in string; -- file name without extension
- signal rd_now : out string;
- signal mm_clk : in std_logic);
+ procedure mmf_sim_get_now(
+ filename : in string; -- file name without extension
+ signal rd_now : out string;
+ signal mm_clk : in std_logic);
-- Functions to create prefixes for the mmf file filename
function mmf_prefix(name : string; index : natural) return string; -- generic prefix name with index to be used for a file IO filename
@@ -231,38 +244,39 @@ package mm_file_pkg is
-- Declare mm_file component to support positional generic and port mapping of many instances in a TB
----------------------------------------------------------------------------
component mm_file
- generic(
- g_file_prefix : string;
- g_file_enable : std_logic := '1';
- g_mm_rd_latency : natural := 2;
- g_mm_timeout : time := c_mmf_mm_timeout;
- g_mm_pause : time := c_mmf_mm_pause
- );
- port (
- mm_rst : in std_logic;
- mm_clk : in std_logic;
- mm_master_out : out t_mem_mosi;
- mm_master_in : in t_mem_miso
- );
+ generic(
+ g_file_prefix : string;
+ g_file_enable : std_logic := '1';
+ g_mm_rd_latency : natural := 2;
+ g_mm_timeout : time := c_mmf_mm_timeout;
+ g_mm_pause : time := c_mmf_mm_pause
+ );
+ port (
+ mm_rst : in std_logic;
+ mm_clk : in std_logic;
+ mm_master_out : out t_mem_mosi;
+ mm_master_in : in t_mem_miso
+ );
end component;
end mm_file_pkg;
package body mm_file_pkg is
procedure mmf_file_create(filename: in string) is
- file created_file : TEXT open write_mode is filename;
+ file created_file : TEXT open write_mode is filename;
begin
-- Write the file with nothing in it
write(created_file, "");
end;
- procedure mmf_mm_from_file(signal mm_clk : in std_logic;
- signal mm_rst : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- rd_filename: in string;
- wr_filename: in string;
- rd_latency: in natural) is
+ procedure mmf_mm_from_file(
+ signal mm_clk : in std_logic;
+ signal mm_rst : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ rd_filename: in string;
+ wr_filename: in string;
+ rd_latency: in natural) is
file rd_file : TEXT;
file wr_file : TEXT;
@@ -279,81 +293,82 @@ package body mm_file_pkg is
-- (data) DEADBEEF
-- ...as a hex address 'A' would fit in only 4 bits, causing an error in hread().
variable v_addr_slv : std_logic_vector(c_word_w - 1 downto 0);
- variable v_data_slv : std_logic_vector(c_word_w - 1 downto 0);
+ variable v_data_slv : std_logic_vector(c_word_w - 1 downto 0);
- variable v_rd_wr_str : string(1 to 2); -- Contains 'RD' or 'WR'
+ variable v_rd_wr_str : string(1 to 2); -- Contains 'RD' or 'WR'
begin
- proc_common_wait_until_low(mm_clk, mm_rst);
+ proc_common_wait_until_low(mm_clk, mm_rst);
- -- We have to open the file explicitely so we can check the status
- file_open(open_status_rd, rd_file, rd_filename, read_mode);
+ -- We have to open the file explicitely so we can check the status
+ file_open(open_status_rd, rd_file, rd_filename, read_mode);
- -- open_status may throw an error if the file is being written to by some other program
- if open_status_rd = open_ok then
+ -- open_status may throw an error if the file is being written to by some other program
+ if open_status_rd = open_ok then
- if not endfile(rd_file) then
- -- The file is not empty: process its contents
+ if not endfile(rd_file) then
+ -- The file is not empty: process its contents
- -- Read a line from it, first line indicates RD or WR
- readline(rd_file, rd_line);
- read(rd_line, v_rd_wr_str);
+ -- Read a line from it, first line indicates RD or WR
+ readline(rd_file, rd_line);
+ read(rd_line, v_rd_wr_str);
- -- The second line represents the address offset:
- readline(rd_file, rd_line);
- hread(rd_line, v_addr_slv); -- read the string as HEX and assign to SLV.
+ -- The second line represents the address offset:
+ readline(rd_file, rd_line);
+ hread(rd_line, v_addr_slv); -- read the string as HEX and assign to SLV.
- -- Write only: The third line contains the data to write:
- if v_rd_wr_str = "WR" then
- readline(rd_file, rd_line);
- hread(rd_line, v_data_slv); -- read the string as HEX and assign to SLV.
- end if;
+ -- Write only: The third line contains the data to write:
+ if v_rd_wr_str = "WR" then
+ readline(rd_file, rd_line);
+ hread(rd_line, v_data_slv); -- read the string as HEX and assign to SLV.
+ end if;
- -- We're done reading MM request from the .ctrl file.
- -- Clear the .ctrl file by closing and recreating it, because we don't want to do the same
- -- MM request again the next time this procedure is called.
- file_close(rd_file);
- mmf_file_create(rd_filename);
-
- -- Execute the MM request to the MM slave
- if v_rd_wr_str = "WR" then
- print_str("[" & time_to_str(now) & "] " & rd_filename & ": Writing 0x" & slv_to_hex(v_data_slv) & " to address 0x" & slv_to_hex(v_addr_slv));
- -- Treat 32 bit hex data from file as 32 bit VHDL INTEGER, so need to use signed TO_SINT() to avoid out of NATURAL range
- -- warning in simulation due to '1' sign bit, because unsigned VHDL NATURAL only fits 31 bits
- proc_mem_mm_bus_wr(TO_UINT(v_addr_slv), TO_SINT(v_data_slv), mm_clk, mm_miso, mm_mosi);
-
- elsif v_rd_wr_str = "RD" then
- proc_mem_mm_bus_rd(TO_UINT(v_addr_slv), mm_clk, mm_miso, mm_mosi);
- if rd_latency > 0 then
- proc_mem_mm_bus_rd_latency(rd_latency, mm_clk);
- end if;
- v_data_slv := mm_miso.rddata(31 downto 0);
- print_str("[" & time_to_str(now) & "] " & rd_filename & ": Reading from address 0x" & slv_to_hex(v_addr_slv) & ": 0x" & slv_to_hex(v_data_slv));
-
- -- Write the RD response read data to the .stat file
- file_open(open_status_wr, wr_file, wr_filename, write_mode);
- hwrite(wr_line, v_data_slv);
- writeline(wr_file, wr_line);
- file_close(wr_file);
+ -- We're done reading MM request from the .ctrl file.
+ -- Clear the .ctrl file by closing and recreating it, because we don't want to do the same
+ -- MM request again the next time this procedure is called.
+ file_close(rd_file);
+ mmf_file_create(rd_filename);
+
+ -- Execute the MM request to the MM slave
+ if v_rd_wr_str = "WR" then
+ print_str("[" & time_to_str(now) & "] " & rd_filename & ": Writing 0x" & slv_to_hex(v_data_slv) & " to address 0x" & slv_to_hex(v_addr_slv));
+ -- Treat 32 bit hex data from file as 32 bit VHDL INTEGER, so need to use signed TO_SINT() to avoid out of NATURAL range
+ -- warning in simulation due to '1' sign bit, because unsigned VHDL NATURAL only fits 31 bits
+ proc_mem_mm_bus_wr(TO_UINT(v_addr_slv), TO_SINT(v_data_slv), mm_clk, mm_miso, mm_mosi);
+
+ elsif v_rd_wr_str = "RD" then
+ proc_mem_mm_bus_rd(TO_UINT(v_addr_slv), mm_clk, mm_miso, mm_mosi);
+ if rd_latency > 0 then
+ proc_mem_mm_bus_rd_latency(rd_latency, mm_clk);
end if;
-
- else
- -- Nothing to process; wait one MM clock cycle.
- proc_common_wait_some_cycles(mm_clk, 1);
+ v_data_slv := mm_miso.rddata(31 downto 0);
+ print_str("[" & time_to_str(now) & "] " & rd_filename & ": Reading from address 0x" & slv_to_hex(v_addr_slv) & ": 0x" & slv_to_hex(v_data_slv));
+
+ -- Write the RD response read data to the .stat file
+ file_open(open_status_wr, wr_file, wr_filename, write_mode);
+ hwrite(wr_line, v_data_slv);
+ writeline(wr_file, wr_line);
+ file_close(wr_file);
end if;
else
- report "mmf_mm_from_file() could not open " & rd_filename & " at " & time_to_str(now) severity NOTE;
- -- Try again next time; wait one MM clock cycle.
+ -- Nothing to process; wait one MM clock cycle.
proc_common_wait_some_cycles(mm_clk, 1);
end if;
- -- The END implicitely close the rd_file, if still necessary.
+ else
+ report "mmf_mm_from_file() could not open " & rd_filename & " at " & time_to_str(now) severity NOTE;
+ -- Try again next time; wait one MM clock cycle.
+ proc_common_wait_some_cycles(mm_clk, 1);
+ end if;
+
+ -- The END implicitely close the rd_file, if still necessary.
end;
- procedure mmf_sim_ctrl_from_file(rd_filename: in string;
- wr_filename: in string) is
+ procedure mmf_sim_ctrl_from_file(
+ rd_filename: in string;
+ wr_filename: in string) is
file rd_file : TEXT;
file wr_file : TEXT;
@@ -368,43 +383,43 @@ package body mm_file_pkg is
begin
- -- We have to open the file explicitely so we can check the status
- file_open(open_status_rd, rd_file, rd_filename, read_mode);
+ -- We have to open the file explicitely so we can check the status
+ file_open(open_status_rd, rd_file, rd_filename, read_mode);
- -- open_status may throw an error if the file is being written to by some other program
- if open_status_rd = open_ok then
+ -- open_status may throw an error if the file is being written to by some other program
+ if open_status_rd = open_ok then
- if not endfile(rd_file) then
- -- The file is not empty: process its contents
+ if not endfile(rd_file) then
+ -- The file is not empty: process its contents
- -- Read a line from it, interpret the simulation request
- readline(rd_file, rd_line);
- read(rd_line, v_rd_wr_str);
+ -- Read a line from it, interpret the simulation request
+ readline(rd_file, rd_line);
+ read(rd_line, v_rd_wr_str);
- -- We're done reading this simulation request .ctrl file. Clear the file by closing and recreating it.
- file_close(rd_file);
- mmf_file_create(rd_filename);
-
- -- Execute the simulation request
- if v_rd_wr_str = "GET_SIM_TIME" then
- -- Write the GET_SIM_TIME response time NOW to the .stat file
- file_open(open_status_wr, wr_file, wr_filename, write_mode);
- write(wr_line, time_to_str(now));
- writeline(wr_file, wr_line);
- file_close(wr_file);
- end if;
+ -- We're done reading this simulation request .ctrl file. Clear the file by closing and recreating it.
+ file_close(rd_file);
+ mmf_file_create(rd_filename);
- else
- -- Nothing to process; wait in procedure mmf_poll_sim_ctrl_file
- null;
+ -- Execute the simulation request
+ if v_rd_wr_str = "GET_SIM_TIME" then
+ -- Write the GET_SIM_TIME response time NOW to the .stat file
+ file_open(open_status_wr, wr_file, wr_filename, write_mode);
+ write(wr_line, time_to_str(now));
+ writeline(wr_file, wr_line);
+ file_close(wr_file);
end if;
else
- report "mmf_mm_from_file() could not open " & rd_filename & " at " & time_to_str(now) severity NOTE;
- -- Try again next time; wait in procedure mmf_poll_sim_ctrl_file
+ -- Nothing to process; wait in procedure mmf_poll_sim_ctrl_file
+ null;
end if;
- -- The END implicitely close the rd_file, if still necessary.
+ else
+ report "mmf_mm_from_file() could not open " & rd_filename & " at " & time_to_str(now) severity NOTE;
+ -- Try again next time; wait in procedure mmf_poll_sim_ctrl_file
+ end if;
+
+ -- The END implicitely close the rd_file, if still necessary.
end;
procedure mmf_poll_sim_ctrl_file(rd_file_name: in string; wr_file_name : in string) is
@@ -420,8 +435,9 @@ package body mm_file_pkg is
end;
- procedure mmf_poll_sim_ctrl_file(signal mm_clk : in std_logic;
- rd_file_name: in string; wr_file_name : in string) is
+ procedure mmf_poll_sim_ctrl_file(
+ signal mm_clk : in std_logic;
+ rd_file_name: in string; wr_file_name : in string) is
begin
-- Create the ctrl file that we're going to read from
print_str("[" & time_to_str(now) & "] " & rd_file_name & ": Created" );
@@ -434,9 +450,10 @@ package body mm_file_pkg is
end;
- procedure mmf_wait_for_file_status(rd_filename : in string; -- file name with extension
- exit_on_empty : in boolean;
- signal mm_clk : in std_logic) is
+ procedure mmf_wait_for_file_status(
+ rd_filename : in string; -- file name with extension
+ exit_on_empty : in boolean;
+ signal mm_clk : in std_logic) is
file rd_file : TEXT;
variable open_status_rd : file_open_status;
variable v_endfile : boolean;
@@ -479,22 +496,25 @@ package body mm_file_pkg is
-- The END implicitely close the file, if still necessary.
end;
- procedure mmf_wait_for_file_empty(rd_filename : in string; -- file name with extension
- signal mm_clk : in std_logic) is
+ procedure mmf_wait_for_file_empty(
+ rd_filename : in string; -- file name with extension
+ signal mm_clk : in std_logic) is
begin
mmf_wait_for_file_status(rd_filename, true, mm_clk);
end;
- procedure mmf_wait_for_file_not_empty(rd_filename : in string; -- file name with extension
- signal mm_clk : in std_logic) is
+ procedure mmf_wait_for_file_not_empty(
+ rd_filename : in string; -- file name with extension
+ signal mm_clk : in std_logic) is
begin
mmf_wait_for_file_status(rd_filename, false, mm_clk);
end;
- procedure mmf_mm_bus_wr(filename : in string; -- file name without extension
- wr_addr : in integer; -- use integer to support full 32 bit range
- wr_data : in integer;
- signal mm_clk : in std_logic) is
+ procedure mmf_mm_bus_wr(
+ filename : in string; -- file name without extension
+ wr_addr : in integer; -- use integer to support full 32 bit range
+ wr_data : in integer;
+ signal mm_clk : in std_logic) is
constant ctrl_filename : string := filename & ".ctrl";
file ctrl_file : TEXT;
variable open_status_wr : file_open_status;
@@ -525,11 +545,12 @@ package body mm_file_pkg is
-- The END implicitely close the ctrl_file, if still necessary.
end;
- procedure mmf_mm_bus_rd(filename : in string; -- file name without extension
- rd_latency : in natural;
- rd_addr : in integer; -- use integer to support full 32 bit range
- signal rd_data : out std_logic_vector(c_word_w - 1 downto 0);
- signal mm_clk : in std_logic) is
+ procedure mmf_mm_bus_rd(
+ filename : in string; -- file name without extension
+ rd_latency : in natural;
+ rd_addr : in integer; -- use integer to support full 32 bit range
+ signal rd_data : out std_logic_vector(c_word_w - 1 downto 0);
+ signal mm_clk : in std_logic) is
constant ctrl_filename : string := filename & ".ctrl";
constant stat_filename : string := filename & ".stat";
file ctrl_file : TEXT;
@@ -541,93 +562,96 @@ package body mm_file_pkg is
variable v_rd_data : std_logic_vector(c_word_w - 1 downto 0);
begin
- -- Clear the .stat file by recreating it, because we don't want to do read old file data again
- mmf_file_create(stat_filename);
-
- -- Write MM RD access to the .ctrl file.
- -- The MM device is ready for a new MM request, because any previous MM request has finished at
- -- mmf_mm_bus_wr() or mmf_mm_bus_rd() procedure exit, therefore just overwrite the .ctrl file.
- file_open(open_status_wr, ctrl_file, ctrl_filename, write_mode);
- -- open_status may throw an error if the file is being written to by some other program
- if open_status_wr = open_ok then
- write(wr_line, string'("RD"));
- writeline(ctrl_file, wr_line);
- hwrite(wr_line, TO_SVEC(rd_addr, c_word_w));
- writeline(ctrl_file, wr_line);
- file_close(ctrl_file);
- else
- report "mmf_mm_bus_rd() could not open " & ctrl_filename & " at " & time_to_str(now) severity FAILURE;
- end if;
-
- -- Wait until the MM RD access has written the read data to the .stat file
- mmf_wait_for_file_not_empty(stat_filename, mm_clk);
-
- -- Read the MM RD access read data from the .stat file
- file_open(open_status_rd, stat_file, stat_filename, read_mode);
- -- open_status may throw an error if the file is being written to by some other program
- if open_status_rd = open_ok then
- readline(stat_file, rd_line);
- hread(rd_line, v_rd_data);
- file_close(stat_file);
- rd_data <= v_rd_data;
- -- wait to ensure rd_data has got v_rd_data, otherwise rd_data still holds the old data on procedure exit
- -- the wait should be < mm_clk period/2 to not affect the read rate
- wait for 1 fs;
- else
- report "mmf_mm_bus_rd() could not open " & stat_filename & " at " & time_to_str(now) severity FAILURE;
- end if;
-
- -- No need to prepare for next MM request, because:
- -- . the .ctrl file must already be empty because the .stat file was there
- -- . the .stat file will be cleared on this procedure entry
-
- -- The END implicitely closes the files, if still necessary
+ -- Clear the .stat file by recreating it, because we don't want to do read old file data again
+ mmf_file_create(stat_filename);
+
+ -- Write MM RD access to the .ctrl file.
+ -- The MM device is ready for a new MM request, because any previous MM request has finished at
+ -- mmf_mm_bus_wr() or mmf_mm_bus_rd() procedure exit, therefore just overwrite the .ctrl file.
+ file_open(open_status_wr, ctrl_file, ctrl_filename, write_mode);
+ -- open_status may throw an error if the file is being written to by some other program
+ if open_status_wr = open_ok then
+ write(wr_line, string'("RD"));
+ writeline(ctrl_file, wr_line);
+ hwrite(wr_line, TO_SVEC(rd_addr, c_word_w));
+ writeline(ctrl_file, wr_line);
+ file_close(ctrl_file);
+ else
+ report "mmf_mm_bus_rd() could not open " & ctrl_filename & " at " & time_to_str(now) severity FAILURE;
+ end if;
+
+ -- Wait until the MM RD access has written the read data to the .stat file
+ mmf_wait_for_file_not_empty(stat_filename, mm_clk);
+
+ -- Read the MM RD access read data from the .stat file
+ file_open(open_status_rd, stat_file, stat_filename, read_mode);
+ -- open_status may throw an error if the file is being written to by some other program
+ if open_status_rd = open_ok then
+ readline(stat_file, rd_line);
+ hread(rd_line, v_rd_data);
+ file_close(stat_file);
+ rd_data <= v_rd_data;
+ -- wait to ensure rd_data has got v_rd_data, otherwise rd_data still holds the old data on procedure exit
+ -- the wait should be < mm_clk period/2 to not affect the read rate
+ wait for 1 fs;
+ else
+ report "mmf_mm_bus_rd() could not open " & stat_filename & " at " & time_to_str(now) severity FAILURE;
+ end if;
+
+ -- No need to prepare for next MM request, because:
+ -- . the .ctrl file must already be empty because the .stat file was there
+ -- . the .stat file will be cleared on this procedure entry
+
+ -- The END implicitely closes the files, if still necessary
end;
-- rd_latency = 1
- procedure mmf_mm_bus_rd(filename : in string;
- rd_addr : in integer;
- signal rd_data : out std_logic_vector(c_word_w - 1 downto 0);
- signal mm_clk : in std_logic) is
+ procedure mmf_mm_bus_rd(
+ filename : in string;
+ rd_addr : in integer;
+ signal rd_data : out std_logic_vector(c_word_w - 1 downto 0);
+ signal mm_clk : in std_logic) is
begin
mmf_mm_bus_rd(filename, 1, rd_addr, rd_data, mm_clk);
end;
- procedure mmf_mm_wait_until_value(filename : in string; -- file name without extension
- rd_addr : in integer;
- c_representation : in string; -- treat rd_data as "SIGNED" or "UNSIGNED" 32 bit word
- signal rd_data : inout std_logic_vector(c_word_w - 1 downto 0);
- c_condition : in string; -- ">", ">=", "=", "<=", "<", "/="
- c_rd_value : in integer;
- c_rd_interval : in time;
- signal mm_clk : in std_logic) is
- begin
+ procedure mmf_mm_wait_until_value(
+ filename : in string; -- file name without extension
+ rd_addr : in integer;
+ c_representation : in string; -- treat rd_data as "SIGNED" or "UNSIGNED" 32 bit word
+ signal rd_data : inout std_logic_vector(c_word_w - 1 downto 0);
+ c_condition : in string; -- ">", ">=", "=", "<=", "<", "/="
+ c_rd_value : in integer;
+ c_rd_interval : in time;
+ signal mm_clk : in std_logic) is
+ begin
while true loop
-- Read current
mmf_mm_bus_rd(filename, rd_addr, rd_data, mm_clk); -- only read low part
if c_representation = "SIGNED" then
if c_condition = ">" then if TO_SINT(rd_data) > c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition = ">=" then if TO_SINT(rd_data) >= c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition = "/=" then if TO_SINT(rd_data) /= c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition = "<=" then if TO_SINT(rd_data) <= c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition = "<" then if TO_SINT(rd_data) < c_rd_value then exit; else wait for c_rd_interval; end if;
- else if TO_SINT(rd_data) = c_rd_value then exit; else wait for c_rd_interval; end if; -- default: "="
- end if;
+ elsif c_condition = ">=" then if TO_SINT(rd_data) >= c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition = "/=" then if TO_SINT(rd_data) /= c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition = "<=" then if TO_SINT(rd_data) <= c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition = "<" then if TO_SINT(rd_data) < c_rd_value then exit; else wait for c_rd_interval; end if;
+ else if TO_SINT(rd_data) = c_rd_value then exit; else wait for c_rd_interval; end if; -- default: "="
+ end if;
else -- default: UNSIGED
- if c_condition = ">" then if TO_UINT(rd_data) > c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition = ">=" then if TO_UINT(rd_data) >= c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition = "/=" then if TO_UINT(rd_data) /= c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition = "<=" then if TO_UINT(rd_data) <= c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition = "<" then if TO_UINT(rd_data) < c_rd_value then exit; else wait for c_rd_interval; end if;
- else if TO_UINT(rd_data) = c_rd_value then exit; else wait for c_rd_interval; end if; -- default: "="
- end if;
+ if c_condition = ">" then if TO_UINT(rd_data) > c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition = ">=" then if TO_UINT(rd_data) >= c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition = "/=" then if TO_UINT(rd_data) /= c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition = "<=" then if TO_UINT(rd_data) <= c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition = "<" then if TO_UINT(rd_data) < c_rd_value then exit; else wait for c_rd_interval; end if;
+ else if TO_UINT(rd_data) = c_rd_value then exit; else wait for c_rd_interval; end if; -- default: "="
+ end if;
end if;
end loop;
- end mmf_mm_wait_until_value;
+ end mmf_mm_wait_until_value;
- procedure mmf_sim_get_now(filename : in string; -- file name without extension
- signal rd_now : out string;
- signal mm_clk : in std_logic) is
+ procedure mmf_sim_get_now(
+ filename : in string; -- file name without extension
+ signal rd_now : out string;
+ signal mm_clk : in std_logic) is
constant ctrl_filename : string := filename & ".ctrl";
constant stat_filename : string := filename & ".stat";
file ctrl_file : TEXT;
@@ -639,43 +663,43 @@ package body mm_file_pkg is
variable v_rd_now : string(rd_now'range);
begin
- -- Clear the sim.stat file by recreating it, because we don't want to do read old simulator status again
- mmf_file_create(stat_filename);
-
- -- Write GET_SIM_TIME to the sim.ctrl file
- -- The simulation is ready for a new simulation status request, because any previous simulation status request has finished at
- -- mmf_sim_get_now() procedure exit, therefore just overwrite the .ctrl file.
- file_open(open_status_wr, ctrl_file, ctrl_filename, write_mode);
- -- open_status may throw an error if the file is being written to by some other program
- if open_status_wr = open_ok then
- write(wr_line, string'("GET_SIM_TIME"));
- writeline(ctrl_file, wr_line);
- file_close(ctrl_file);
- else
- report "mmf_sim_get_now() could not open " & ctrl_filename & " at " & time_to_str(now) severity FAILURE;
- end if;
-
- -- Wait until the simulation has written the simulation status to the sim.stat file
- mmf_wait_for_file_not_empty(stat_filename, mm_clk);
-
- -- Read the GET_SIM_TIME simulation status from the .stat file
- file_open(open_status_rd, stat_file, stat_filename, read_mode);
- -- open_status may throw an error if the file is being written to by some other program
- if open_status_rd = open_ok then
- readline(stat_file, rd_line);
- read(rd_line, v_rd_now);
- file_close(stat_file);
- rd_now <= v_rd_now;
- print_str("GET_SIM_TIME = " & v_rd_now & " at " & time_to_str(now));
- else
- report "mmf_sim_get_now() could not open " & stat_filename & " at " & time_to_str(now) severity FAILURE;
- end if;
-
- -- No need to prepare for next simulation status request, because:
- -- . the .ctrl file must already be empty because the .stat file was there
- -- . the .stat file will be cleared on this procedure entry
-
- -- The END implicitely closes the files, if still necessary
+ -- Clear the sim.stat file by recreating it, because we don't want to do read old simulator status again
+ mmf_file_create(stat_filename);
+
+ -- Write GET_SIM_TIME to the sim.ctrl file
+ -- The simulation is ready for a new simulation status request, because any previous simulation status request has finished at
+ -- mmf_sim_get_now() procedure exit, therefore just overwrite the .ctrl file.
+ file_open(open_status_wr, ctrl_file, ctrl_filename, write_mode);
+ -- open_status may throw an error if the file is being written to by some other program
+ if open_status_wr = open_ok then
+ write(wr_line, string'("GET_SIM_TIME"));
+ writeline(ctrl_file, wr_line);
+ file_close(ctrl_file);
+ else
+ report "mmf_sim_get_now() could not open " & ctrl_filename & " at " & time_to_str(now) severity FAILURE;
+ end if;
+
+ -- Wait until the simulation has written the simulation status to the sim.stat file
+ mmf_wait_for_file_not_empty(stat_filename, mm_clk);
+
+ -- Read the GET_SIM_TIME simulation status from the .stat file
+ file_open(open_status_rd, stat_file, stat_filename, read_mode);
+ -- open_status may throw an error if the file is being written to by some other program
+ if open_status_rd = open_ok then
+ readline(stat_file, rd_line);
+ read(rd_line, v_rd_now);
+ file_close(stat_file);
+ rd_now <= v_rd_now;
+ print_str("GET_SIM_TIME = " & v_rd_now & " at " & time_to_str(now));
+ else
+ report "mmf_sim_get_now() could not open " & stat_filename & " at " & time_to_str(now) severity FAILURE;
+ end if;
+
+ -- No need to prepare for next simulation status request, because:
+ -- . the .ctrl file must already be empty because the .stat file was there
+ -- . the .stat file will be cleared on this procedure entry
+
+ -- The END implicitely closes the files, if still necessary
end;
-- Functions to create prefixes for the mmf file filename
diff --git a/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd b/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
index ded649d443..c76ef0e5ba 100644
--- a/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use work.mm_file_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use work.mm_file_pkg.all;
package mm_file_unb_pkg is
type t_c_mmf_unb_sys is record
diff --git a/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd b/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd
index 7584ee7983..7d2458aae7 100644
--- a/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd
@@ -48,10 +48,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
entity mm_waitrequest_model is
generic (
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd b/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
index 7c4046568a..2574ab724d 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
@@ -45,15 +45,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
entity tb_mm_bus is
- generic (
+ generic (
g_nof_slaves : positive := 1; -- Number of slave memory interfaces on the MM bus array.
g_base_offset : natural := 0; -- Address of first slave on the MM bus
g_width_w : positive := 4; -- Address width of each slave memory in the MM bus array.
@@ -87,11 +87,12 @@ architecture tb of tb_mm_bus is
constant c_read_latency : natural := c_pipeline_mosi + g_rd_latency + c_pipeline_miso_rdval;
constant c_data_w : natural := 32;
- constant c_test_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => g_width_w,
- dat_w => c_data_w,
- nof_dat => c_slave_span,
- init_sl => '0');
+ constant c_test_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => g_width_w,
+ dat_w => c_data_w,
+ nof_dat => c_slave_span,
+ init_sl => '0');
signal mm_rst : std_logic;
signal mm_clk : std_logic := '1';
signal tb_end : std_logic;
@@ -186,60 +187,60 @@ begin
-- The MM bus
-----------------------------------------------------------------------------
u_mm_bus: entity work.mm_bus
- generic map (
- g_nof_slaves => g_nof_slaves,
- g_base_arr => c_base_arr,
- g_width_arr => c_width_arr,
- g_rd_latency_arr => c_rd_latency_arr,
- g_slave_enable_arr => c_slave_enable_arr,
- g_waitrequest_arr => c_waitrequest_arr,
- g_pipeline_mosi => g_pipeline_mosi,
- g_pipeline_miso_rdval => g_pipeline_miso_rdval,
- g_pipeline_miso_wait => g_pipeline_miso_wait
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- master_mosi => master_mosi,
- master_miso => master_miso,
- slave_mosi_arr => slave_mosi_arr,
- slave_miso_arr => slave_miso_arr
- );
+ generic map (
+ g_nof_slaves => g_nof_slaves,
+ g_base_arr => c_base_arr,
+ g_width_arr => c_width_arr,
+ g_rd_latency_arr => c_rd_latency_arr,
+ g_slave_enable_arr => c_slave_enable_arr,
+ g_waitrequest_arr => c_waitrequest_arr,
+ g_pipeline_mosi => g_pipeline_mosi,
+ g_pipeline_miso_rdval => g_pipeline_miso_rdval,
+ g_pipeline_miso_wait => g_pipeline_miso_wait
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ master_mosi => master_mosi,
+ master_miso => master_miso,
+ slave_mosi_arr => slave_mosi_arr,
+ slave_miso_arr => slave_miso_arr
+ );
-----------------------------------------------------------------------------
-- Model the MM slaves
-----------------------------------------------------------------------------
gen_slaves : for I in 0 to g_nof_slaves - 1 generate
u_waitrequest_model : entity work.mm_waitrequest_model
- generic map (
- g_waitrequest => g_waitrequest,
- g_seed => I
- )
- port map (
- mm_clk => mm_clk,
- bus_mosi => slave_mosi_arr(I),
- bus_miso => slave_miso_arr(I),
- slave_mosi => ram_mosi_arr(I),
- slave_miso => ram_miso_arr(I)
- );
+ generic map (
+ g_waitrequest => g_waitrequest,
+ g_seed => I
+ )
+ port map (
+ mm_clk => mm_clk,
+ bus_mosi => slave_mosi_arr(I),
+ bus_miso => slave_miso_arr(I),
+ slave_mosi => ram_mosi_arr(I),
+ slave_miso => ram_miso_arr(I)
+ );
u_ram : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_test_ram,
- g_init_file => "UNUSED"
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- clken => '1',
- wr_en => ram_mosi_arr(I).wr,
- wr_adr => ram_mosi_arr(I).address(g_width_w - 1 downto 0),
- wr_dat => ram_mosi_arr(I).wrdata(c_data_w - 1 downto 0),
- rd_en => ram_mosi_arr(I).rd,
- rd_adr => ram_mosi_arr(I).address(g_width_w - 1 downto 0),
- rd_dat => ram_miso_arr(I).rddata(c_data_w - 1 downto 0),
- rd_val => ram_miso_arr(I).rdval
- );
+ generic map (
+ g_ram => c_test_ram,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ clken => '1',
+ wr_en => ram_mosi_arr(I).wr,
+ wr_adr => ram_mosi_arr(I).address(g_width_w - 1 downto 0),
+ wr_dat => ram_mosi_arr(I).wrdata(c_data_w - 1 downto 0),
+ rd_en => ram_mosi_arr(I).rd,
+ rd_adr => ram_mosi_arr(I).address(g_width_w - 1 downto 0),
+ rd_dat => ram_miso_arr(I).rddata(c_data_w - 1 downto 0),
+ rd_val => ram_miso_arr(I).rdval
+ );
end generate;
end tb;
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_file.vhd b/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
index ce5bfc5ca2..358d3d0b02 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
@@ -43,13 +43,13 @@
-- For example observe mm_mosi, mm_miso, rd_now and out_reg_arr in wave window.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.mm_file_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.mm_file_pkg.all;
entity tb_mm_file is
generic (
@@ -166,48 +166,48 @@ begin
end process;
u_mm_file : entity work.mm_file
- generic map(
- g_file_prefix => c_reg_r_w_dc_file_pathname,
- g_mm_rd_latency => c_mem_reg.latency, -- the mm_file g_mm_rd_latency must be >= the MM slave read latency
- g_mm_timeout => g_mm_timeout,
- g_mm_pause => g_mm_pause
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- mm_master_out => mm_mosi,
- mm_master_in => mm_miso
- );
+ generic map(
+ g_file_prefix => c_reg_r_w_dc_file_pathname,
+ g_mm_rd_latency => c_mem_reg.latency, -- the mm_file g_mm_rd_latency must be >= the MM slave read latency
+ g_mm_timeout => g_mm_timeout,
+ g_mm_pause => g_mm_pause
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ mm_master_out => mm_mosi,
+ mm_master_in => mm_miso
+ );
-- Target MM reg
u_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 0,
- g_readback => false,
- g_reg => c_mem_reg
- --g_init_reg => STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := (OTHERS => '0')
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => mm_rst,
- st_clk => mm_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => mm_mosi,
- sla_out => mm_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => reg_wr_arr,
- reg_rd_arr => reg_rd_arr,
- in_new => in_new,
- in_reg => in_reg,
- out_reg => out_reg,
- out_new => out_new
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 0,
+ g_readback => false,
+ g_reg => c_mem_reg
+ --g_init_reg => STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := (OTHERS => '0')
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => mm_rst,
+ st_clk => mm_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => mm_mosi,
+ sla_out => mm_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => reg_wr_arr,
+ reg_rd_arr => reg_rd_arr,
+ in_new => in_new,
+ in_reg => in_reg,
+ out_reg => out_reg,
+ out_new => out_new
+ );
in_reg <= out_reg;
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd b/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
index f939920bf7..f71f444bf7 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
@@ -43,15 +43,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
entity tb_mm_master_mux is
- generic (
+ generic (
g_nof_masters : positive := 2; -- Number of master memory interfaces on the MM bus array.
g_base_arr : t_nat_natural_arr := (0, 256); -- Address base per slave port of mm_bus
g_width_arr : t_nat_natural_arr := (4, 8); -- Address width per slave port of mm_bus
@@ -82,11 +82,12 @@ architecture tb of tb_mm_master_mux is
constant c_addr_w : natural := largest(ceil_log2(largest(g_base_arr)), largest(g_width_arr)) + 1;
constant c_data_w : natural := 32;
- constant c_test_ram : t_c_mem := (latency => c_ram_rd_latency,
- adr_w => c_addr_w,
- dat_w => c_data_w,
- nof_dat => 2**c_addr_w,
- init_sl => '0');
+ constant c_test_ram : t_c_mem := (
+ latency => c_ram_rd_latency,
+ adr_w => c_addr_w,
+ dat_w => c_data_w,
+ nof_dat => 2**c_addr_w,
+ init_sl => '0');
signal mm_rst : std_logic;
signal mm_clk : std_logic := '1';
signal tb_end : std_logic;
@@ -154,66 +155,66 @@ begin
-- Model multiple masters using stimuli from a single master
u_masters : entity work.mm_bus
- generic map (
- g_nof_slaves => g_nof_masters,
- g_base_arr => g_base_arr,
- g_width_arr => g_width_arr,
- g_rd_latency_arr => c_ram_rd_latency_arr,
- g_slave_enable_arr => c_slave_enable_arr,
- g_waitrequest_arr => c_waitrequest_arr,
- g_pipeline_mosi => g_pipeline_bus_mosi,
- g_pipeline_miso_rdval => g_pipeline_bus_miso_rdval,
- g_pipeline_miso_wait => g_pipeline_bus_miso_wait
- )
- port map (
- mm_clk => mm_clk,
- master_mosi => stimuli_mosi,
- master_miso => stimuli_miso,
- slave_mosi_arr => master_mosi_arr,
- slave_miso_arr => master_miso_arr
- );
+ generic map (
+ g_nof_slaves => g_nof_masters,
+ g_base_arr => g_base_arr,
+ g_width_arr => g_width_arr,
+ g_rd_latency_arr => c_ram_rd_latency_arr,
+ g_slave_enable_arr => c_slave_enable_arr,
+ g_waitrequest_arr => c_waitrequest_arr,
+ g_pipeline_mosi => g_pipeline_bus_mosi,
+ g_pipeline_miso_rdval => g_pipeline_bus_miso_rdval,
+ g_pipeline_miso_wait => g_pipeline_bus_miso_wait
+ )
+ port map (
+ mm_clk => mm_clk,
+ master_mosi => stimuli_mosi,
+ master_miso => stimuli_miso,
+ slave_mosi_arr => master_mosi_arr,
+ slave_miso_arr => master_miso_arr
+ );
-- DUT = device under test
u_dut: entity work.mm_master_mux
- generic map (
- g_nof_masters => g_nof_masters,
- g_rd_latency_min => c_read_latency
- )
- port map (
- mm_clk => mm_clk,
- master_mosi_arr => master_mosi_arr,
- master_miso_arr => master_miso_arr,
- mux_mosi => mux_mosi,
- mux_miso => mux_miso
- );
+ generic map (
+ g_nof_masters => g_nof_masters,
+ g_rd_latency_min => c_read_latency
+ )
+ port map (
+ mm_clk => mm_clk,
+ master_mosi_arr => master_mosi_arr,
+ master_miso_arr => master_miso_arr,
+ mux_mosi => mux_mosi,
+ mux_miso => mux_miso
+ );
-- Model master access to MM bus with multiple slaves using a single RAM
u_waitrequest_model : entity work.mm_waitrequest_model
- generic map (
- g_waitrequest => g_waitrequest
- )
- port map (
- mm_clk => mm_clk,
- bus_mosi => mux_mosi,
- bus_miso => mux_miso,
- slave_mosi => ram_mosi,
- slave_miso => ram_miso
- );
+ generic map (
+ g_waitrequest => g_waitrequest
+ )
+ port map (
+ mm_clk => mm_clk,
+ bus_mosi => mux_mosi,
+ bus_miso => mux_miso,
+ slave_mosi => ram_mosi,
+ slave_miso => ram_miso
+ );
u_ram : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_test_ram,
- g_init_file => "UNUSED"
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- wr_en => ram_mosi.wr,
- wr_adr => ram_mosi.address(c_addr_w - 1 downto 0),
- wr_dat => ram_mosi.wrdata(c_data_w - 1 downto 0),
- rd_en => ram_mosi.rd,
- rd_adr => ram_mosi.address(c_addr_w - 1 downto 0),
- rd_dat => ram_miso.rddata(c_data_w - 1 downto 0),
- rd_val => ram_miso.rdval
- );
+ generic map (
+ g_ram => c_test_ram,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ wr_en => ram_mosi.wr,
+ wr_adr => ram_mosi.address(c_addr_w - 1 downto 0),
+ wr_dat => ram_mosi.wrdata(c_data_w - 1 downto 0),
+ rd_en => ram_mosi.rd,
+ rd_adr => ram_mosi.address(c_addr_w - 1 downto 0),
+ rd_dat => ram_miso.rddata(c_data_w - 1 downto 0),
+ rd_val => ram_miso.rdval
+ );
end tb;
diff --git a/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd b/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd
index 508a66f587..35de2a0ed8 100644
--- a/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd
@@ -26,8 +26,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_tb_mm_bus is
end tb_tb_mm_bus;
diff --git a/libraries/base/mm/tb/vhdl/tb_tb_mm_file.vhd b/libraries/base/mm/tb/vhdl/tb_tb_mm_file.vhd
index 469bf97212..571881edfb 100644
--- a/libraries/base/mm/tb/vhdl/tb_tb_mm_file.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_tb_mm_file.vhd
@@ -27,7 +27,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_mm_file is
end tb_tb_mm_file;
diff --git a/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd b/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd
index fb6d289c65..d11e39c054 100644
--- a/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd
@@ -26,8 +26,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_tb_mm_master_mux is
end tb_tb_mm_master_mux;
diff --git a/libraries/base/reorder/src/vhdl/mms_reorder_rewire.vhd b/libraries/base/reorder/src/vhdl/mms_reorder_rewire.vhd
index 7769954f47..3cc1ec7f11 100644
--- a/libraries/base/reorder/src/vhdl/mms_reorder_rewire.vhd
+++ b/libraries/base/reorder/src/vhdl/mms_reorder_rewire.vhd
@@ -48,12 +48,12 @@
-- Some more remarks:
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.reorder_pkg.all;
entity mms_reorder_rewire is
generic (
@@ -87,43 +87,43 @@ architecture str of mms_reorder_rewire is
signal sel_reg : std_logic_vector(sel_a_b(g_use_sel_table, g_sel_in_w, g_sel_in_w * g_nof_streams) - 1 downto 0) := (others => '0');
begin
u_register : entity work.reorder_rewire_reg
- generic map(
- g_nof_streams => g_nof_streams,
- g_sel_in_w => g_sel_in_w,
- g_cross_clock_domain => true
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_sel_in_w => g_sel_in_w,
+ g_cross_clock_domain => true
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- sel_reg => sel_reg
- );
+ -- MM registers in st_clk domain
+ sel_reg => sel_reg
+ );
u_rewire: entity work.reorder_rewire
- generic map(
- g_select_table => g_select_table,
- g_nof_streams => g_nof_streams,
- g_sel_in_w => g_sel_in_w,
- g_use_sel_table => g_use_sel_table
- )
- port map(
- -- System
- sel_in => sel_reg,
+ generic map(
+ g_select_table => g_select_table,
+ g_nof_streams => g_nof_streams,
+ g_sel_in_w => g_sel_in_w,
+ g_use_sel_table => g_use_sel_table
+ )
+ port map(
+ -- System
+ sel_in => sel_reg,
- -- Inputs from transceiver
- input_sosi_arr => snk_in_arr,
- input_siso_arr => snk_out_arr,
+ -- Inputs from transceiver
+ input_sosi_arr => snk_in_arr,
+ input_siso_arr => snk_out_arr,
- -- Outputs to processing
- output_sosi_arr => src_out_arr,
- output_siso_arr => src_in_arr
- );
+ -- Outputs to processing
+ output_sosi_arr => src_out_arr,
+ output_siso_arr => src_in_arr
+ );
end str;
diff --git a/libraries/base/reorder/src/vhdl/reorder_col.vhd b/libraries/base/reorder/src/vhdl/reorder_col.vhd
index b169627075..20a3208cbe 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col.vhd
@@ -51,11 +51,11 @@
-- support the input_siso signal, e.g. based on store_done and retrieve_done.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity reorder_col is
generic (
@@ -89,17 +89,19 @@ end reorder_col;
architecture str of reorder_col is
constant c_data_w : natural := c_nof_complex * g_dsp_data_w;
- constant c_store_buf : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_ch_in),
- dat_w => c_data_w,
- nof_dat => g_nof_ch_in,
- init_sl => '0'); -- ST side : stat_mosi
+ constant c_store_buf : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_ch_in),
+ dat_w => c_data_w,
+ nof_dat => g_nof_ch_in,
+ init_sl => '0'); -- ST side : stat_mosi
- constant c_select_buf : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_ch_sel),
- dat_w => ceil_log2(g_nof_ch_in),
- nof_dat => g_nof_ch_sel,
- init_sl => '0');
+ constant c_select_buf : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_ch_sel),
+ dat_w => ceil_log2(g_nof_ch_in),
+ nof_dat => g_nof_ch_sel,
+ init_sl => '0');
constant c_data_nof_pages : natural := 2; -- fixed dual page SS
constant c_info_nof_pages : natural := 2; -- fixed, fits the dual page block latency and logic latency of the SS
@@ -132,110 +134,110 @@ begin
-- (no bursting) by enforcing a minimum period of g_nof_ch_sel
-----------------------------------------------------------------------------
u_dp_throttle_sop : entity dp_lib.dp_throttle_sop
- generic map (
- g_period => g_nof_ch_sel
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_out => input_siso,
- snk_in => input_sosi
- );
+ generic map (
+ g_period => g_nof_ch_sel
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_out => input_siso,
+ snk_in => input_sosi
+ );
u_store : entity work.reorder_store
- generic map (
- g_dsp_data_w => g_dsp_data_w,
- g_nof_ch_in => g_nof_ch_in,
- g_use_complex => g_use_complex
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_ch_in => g_nof_ch_in,
+ g_use_complex => g_use_complex
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- -- Streaming
- input_sosi => input_sosi,
- -- Timing
- store_done => store_done,
- -- Write store buffer control
- store_mosi => store_mosi
- );
+ -- Streaming
+ input_sosi => input_sosi,
+ -- Timing
+ store_done => store_done,
+ -- Write store buffer control
+ store_mosi => store_mosi
+ );
u_store_buf : entity common_lib.common_paged_ram_r_w
- generic map (
- g_str => "use_adr",
- g_data_w => c_store_buf.dat_w,
- g_nof_pages => c_data_nof_pages,
- g_page_sz => c_store_buf.nof_dat,
- g_wr_start_page => 0,
- g_rd_start_page => 0,
- g_rd_latency => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- wr_next_page => store_done,
- wr_adr => store_mosi.address(c_store_buf.adr_w - 1 downto 0),
- wr_en => store_mosi.wr,
- wr_dat => store_mosi.wrdata(c_store_buf.dat_w - 1 downto 0),
- rd_next_page => retrieve_done,
- rd_adr => retrieve_mosi.address(c_store_buf.adr_w - 1 downto 0),
- rd_en => retrieve_mosi.rd,
- rd_dat => retrieve_miso.rddata(c_store_buf.dat_w - 1 downto 0),
- rd_val => retrieve_miso.rdval
- );
+ generic map (
+ g_str => "use_adr",
+ g_data_w => c_store_buf.dat_w,
+ g_nof_pages => c_data_nof_pages,
+ g_page_sz => c_store_buf.nof_dat,
+ g_wr_start_page => 0,
+ g_rd_start_page => 0,
+ g_rd_latency => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ wr_next_page => store_done,
+ wr_adr => store_mosi.address(c_store_buf.adr_w - 1 downto 0),
+ wr_en => store_mosi.wr,
+ wr_dat => store_mosi.wrdata(c_store_buf.dat_w - 1 downto 0),
+ rd_next_page => retrieve_done,
+ rd_adr => retrieve_mosi.address(c_store_buf.adr_w - 1 downto 0),
+ rd_en => retrieve_mosi.rd,
+ rd_dat => retrieve_miso.rddata(c_store_buf.dat_w - 1 downto 0),
+ rd_val => retrieve_miso.rdval
+ );
u_select_buf : entity common_lib.common_ram_crw_crw
- generic map (
- g_ram => c_select_buf,
- g_init_file => g_select_file_name
- )
- port map (
- -- MM side
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_ss_ss_mosi.wr,
- wr_dat_a => ram_ss_ss_mosi.wrdata(c_select_buf.dat_w - 1 downto 0),
- adr_a => ram_ss_ss_mosi.address(c_select_buf.adr_w - 1 downto 0),
- rd_en_a => ram_ss_ss_mosi.rd,
- rd_dat_a => ram_ss_ss_miso.rddata(c_select_buf.dat_w - 1 downto 0),
- rd_val_a => ram_ss_ss_miso.rdval,
- -- ST side
- rst_b => dp_rst,
- clk_b => dp_clk,
- wr_en_b => select_mosi.wr,
- wr_dat_b => select_mosi.wrdata(c_select_buf.dat_w - 1 downto 0),
- adr_b => select_mosi.address(c_select_buf.adr_w - 1 downto 0),
- rd_en_b => select_mosi.rd,
- rd_dat_b => select_miso.rddata(c_select_buf.dat_w - 1 downto 0),
- rd_val_b => select_miso.rdval
- );
+ generic map (
+ g_ram => c_select_buf,
+ g_init_file => g_select_file_name
+ )
+ port map (
+ -- MM side
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_ss_ss_mosi.wr,
+ wr_dat_a => ram_ss_ss_mosi.wrdata(c_select_buf.dat_w - 1 downto 0),
+ adr_a => ram_ss_ss_mosi.address(c_select_buf.adr_w - 1 downto 0),
+ rd_en_a => ram_ss_ss_mosi.rd,
+ rd_dat_a => ram_ss_ss_miso.rddata(c_select_buf.dat_w - 1 downto 0),
+ rd_val_a => ram_ss_ss_miso.rdval,
+ -- ST side
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+ wr_en_b => select_mosi.wr,
+ wr_dat_b => select_mosi.wrdata(c_select_buf.dat_w - 1 downto 0),
+ adr_b => select_mosi.address(c_select_buf.adr_w - 1 downto 0),
+ rd_en_b => select_mosi.rd,
+ rd_dat_b => select_miso.rddata(c_select_buf.dat_w - 1 downto 0),
+ rd_val_b => select_miso.rdval
+ );
u_retrieve : entity work.reorder_retrieve
- generic map (
- g_dsp_data_w => g_dsp_data_w,
- g_nof_ch_in => g_nof_ch_in,
- g_nof_ch_sel => g_nof_ch_sel
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_ch_in => g_nof_ch_in,
+ g_nof_ch_sel => g_nof_ch_sel
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- -- Timing
- store_done => store_done,
+ -- Timing
+ store_done => store_done,
- -- Read store_buf control
- retrieve_mosi => retrieve_mosi,
- retrieve_miso => retrieve_miso,
- retrieve_done => retrieve_done,
+ -- Read store_buf control
+ retrieve_mosi => retrieve_mosi,
+ retrieve_miso => retrieve_miso,
+ retrieve_done => retrieve_done,
- -- Read select_buf control
- select_mosi => select_mosi,
- select_miso => select_miso,
+ -- Read select_buf control
+ select_mosi => select_mosi,
+ select_miso => select_miso,
- -- Streaming
- output_sosi => retrieve_sosi,
- output_siso => retrieve_siso
- );
+ -- Streaming
+ output_sosi => retrieve_sosi,
+ output_siso => retrieve_siso
+ );
-- Page delay the input_sosi info (sync, BSN, channel at sop and err, empty at eop) and combine
-- it with the retrieved SS data to get the output_sosi.
@@ -243,20 +245,20 @@ begin
info_eop_wr_en <= input_sosi.eop & store_done;
u_info_sosi : entity dp_lib.dp_paged_sop_eop_reg
- generic map (
- g_nof_pages => c_info_nof_pages
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- page write enable ctrl
- sop_wr_en => info_sop_wr_en,
- eop_wr_en => info_eop_wr_en,
- -- ST sink
- snk_in => input_sosi,
- -- ST source
- src_out => info_sosi_paged
- );
+ generic map (
+ g_nof_pages => c_info_nof_pages
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- page write enable ctrl
+ sop_wr_en => info_sop_wr_en,
+ eop_wr_en => info_eop_wr_en,
+ -- ST sink
+ snk_in => input_sosi,
+ -- ST source
+ src_out => info_sosi_paged
+ );
-- Account for retrieve rd latency is 1, for sop related info it is not
-- critical that it arrives early, but for eop related info it is.
@@ -265,18 +267,18 @@ begin
-- Adapt output ready latency (RL), defaults to wires when c_output_rl = c_retrieve_lat
u_rl : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => c_retrieve_lat,
- g_out_latency => c_output_rl
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out => retrieve_siso,
- snk_in => retrieve_info_sosi,
- -- ST source
- src_in => output_siso,
- src_out => output_sosi
- );
+ generic map (
+ g_in_latency => c_retrieve_lat,
+ g_out_latency => c_output_rl
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => retrieve_siso,
+ snk_in => retrieve_info_sosi,
+ -- ST source
+ src_in => output_siso,
+ src_out => output_sosi
+ );
end str;
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
index 2aac2334fc..b57c2a5fb2 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
@@ -53,11 +53,11 @@
-- that has g_nof_inputs instances of reorder_col_select.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity reorder_col_select is
generic (
@@ -92,11 +92,12 @@ end reorder_col_select;
architecture str of reorder_col_select is
constant c_data_w : natural := c_nof_complex * g_dsp_data_w;
- constant c_store_buf : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_ch_in),
- dat_w => c_data_w,
- nof_dat => g_nof_ch_in,
- init_sl => '0'); -- ST side : stat_mosi
+ constant c_store_buf : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_ch_in),
+ dat_w => c_data_w,
+ nof_dat => g_nof_ch_in,
+ init_sl => '0'); -- ST side : stat_mosi
constant c_data_nof_pages : natural := 2; -- fixed dual page SS
constant c_info_nof_pages : natural := 2; -- fixed, fits the dual page block latency and logic latency of the SS
@@ -140,64 +141,64 @@ begin
output_nof_ch_sel <= nof_ch_sel_reg;
u_store : entity work.reorder_store
- generic map (
- g_dsp_data_w => g_dsp_data_w,
- g_nof_ch_in => g_nof_ch_in,
- g_use_complex => g_use_complex
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- Dynamic reorder block size control
- nof_ch_in => nof_ch_in_reg,
- -- Streaming
- input_sosi => input_sosi_reg,
- -- Timing
- store_busy => store_busy,
- store_done => store_done,
- -- Write store buffer control
- store_mosi => store_mosi
- );
+ generic map (
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_ch_in => g_nof_ch_in,
+ g_use_complex => g_use_complex
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Dynamic reorder block size control
+ nof_ch_in => nof_ch_in_reg,
+ -- Streaming
+ input_sosi => input_sosi_reg,
+ -- Timing
+ store_busy => store_busy,
+ store_done => store_done,
+ -- Write store buffer control
+ store_mosi => store_mosi
+ );
u_store_buf : entity common_lib.common_paged_ram_r_w
- generic map (
- g_str => "use_adr",
- g_data_w => c_store_buf.dat_w,
- g_nof_pages => c_data_nof_pages,
- g_page_sz => c_store_buf.nof_dat,
- g_wr_start_page => 0,
- g_rd_start_page => 1,
- g_rd_latency => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- wr_next_page => store_done,
- wr_adr => store_mosi.address(c_store_buf.adr_w - 1 downto 0),
- wr_en => store_mosi.wr,
- wr_dat => store_mosi.wrdata(c_store_buf.dat_w - 1 downto 0),
- rd_next_page => store_done,
- rd_adr => col_select_mosi.address(c_store_buf.adr_w - 1 downto 0),
- rd_en => col_select_mosi.rd,
- rd_dat => i_col_select_miso.rddata(c_store_buf.dat_w - 1 downto 0),
- rd_val => i_col_select_miso.rdval
- );
+ generic map (
+ g_str => "use_adr",
+ g_data_w => c_store_buf.dat_w,
+ g_nof_pages => c_data_nof_pages,
+ g_page_sz => c_store_buf.nof_dat,
+ g_wr_start_page => 0,
+ g_rd_start_page => 1,
+ g_rd_latency => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ wr_next_page => store_done,
+ wr_adr => store_mosi.address(c_store_buf.adr_w - 1 downto 0),
+ wr_en => store_mosi.wr,
+ wr_dat => store_mosi.wrdata(c_store_buf.dat_w - 1 downto 0),
+ rd_next_page => store_done,
+ rd_adr => col_select_mosi.address(c_store_buf.adr_w - 1 downto 0),
+ rd_en => col_select_mosi.rd,
+ rd_dat => i_col_select_miso.rddata(c_store_buf.dat_w - 1 downto 0),
+ rd_val => i_col_select_miso.rdval
+ );
-- Enable retrieve when a block has been stored, disable retrieve when the block has been output
u_retrieve_en : entity common_lib.common_switch
- generic map (
- g_rst_level => '0',
- g_priority_lo => false, -- store_done has priority over nxt_retrieve_done when they occur simultaneously
- g_or_high => true,
- g_and_low => false
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- switch_high => store_done,
- switch_low => retrieve_eop_dly(0),
- out_level => retrieve_en
- );
+ generic map (
+ g_rst_level => '0',
+ g_priority_lo => false, -- store_done has priority over nxt_retrieve_done when they occur simultaneously
+ g_or_high => true,
+ g_and_low => false
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ switch_high => store_done,
+ switch_low => retrieve_eop_dly(0),
+ out_level => retrieve_en
+ );
-- Determine reorder_busy
nxt_retrieve_busy <= '0' when ch_cnt = 0 and retrieve_en = '0' else '1';
@@ -264,20 +265,20 @@ begin
info_eop_wr_en <= input_sosi_reg.eop & store_done;
u_info_sosi : entity dp_lib.dp_paged_sop_eop_reg
- generic map (
- g_nof_pages => c_info_nof_pages
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- page write enable ctrl
- sop_wr_en => info_sop_wr_en,
- eop_wr_en => info_eop_wr_en,
- -- ST sink
- snk_in => input_sosi_reg,
- -- ST source
- src_out => info_sosi_paged
- );
+ generic map (
+ g_nof_pages => c_info_nof_pages
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- page write enable ctrl
+ sop_wr_en => info_sop_wr_en,
+ eop_wr_en => info_eop_wr_en,
+ -- ST sink
+ snk_in => input_sosi_reg,
+ -- ST source
+ src_out => info_sosi_paged
+ );
-- Account for retrieve rd latency is 1, for sop related info it is not
-- critical that it arrives early, but for eop related info it is.
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd b/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
index ce8a2c0bad..dcaa79f32c 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
@@ -31,11 +31,11 @@
--
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity reorder_col_wide is
generic (
@@ -79,46 +79,46 @@ begin
-- Combine the internal array of mm interfaces for the selection
-- memory to one array that is connected to the port of the ss_wide wunit
u_mem_mux_select : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_wb_factor,
- g_mult_addr_w => c_mem_addr_w
- )
- port map (
- mosi => ram_ss_ss_wide_mosi,
- miso => ram_ss_ss_wide_miso,
- mosi_arr => ram_ss_ss_wide_mosi_arr,
- miso_arr => ram_ss_ss_wide_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_wb_factor,
+ g_mult_addr_w => c_mem_addr_w
+ )
+ port map (
+ mosi => ram_ss_ss_wide_mosi,
+ miso => ram_ss_ss_wide_miso,
+ mosi_arr => ram_ss_ss_wide_mosi_arr,
+ miso_arr => ram_ss_ss_wide_miso_arr
+ );
---------------------------------------------------------------
-- INSTANTIATE MULTIPLE SINGLE CHANNEL SUBBAND SELECT UNITS
---------------------------------------------------------------
gen_reorder_col_arr : for I in 0 to g_wb_factor - 1 generate
u_reorder_col : entity work.reorder_col
- generic map (
- g_dsp_data_w => g_dsp_data_w,
- g_nof_ch_in => c_nof_ch_in,
- g_nof_ch_sel => c_nof_ch_sel,
- g_select_file_name => sel_a_b(g_select_file_prefix = "UNUSED", "UNUSED", g_select_file_prefix & "_" & natural'image(I) & ".hex"),
- g_use_complex => g_use_complex
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_ch_in => c_nof_ch_in,
+ g_nof_ch_sel => c_nof_ch_sel,
+ g_select_file_name => sel_a_b(g_select_file_prefix = "UNUSED", "UNUSED", g_select_file_prefix & "_" & natural'image(I) & ".hex"),
+ g_use_complex => g_use_complex
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- Memory Mapped
- ram_ss_ss_mosi => ram_ss_ss_wide_mosi_arr(I),
- ram_ss_ss_miso => ram_ss_ss_wide_miso_arr(I),
+ -- Memory Mapped
+ ram_ss_ss_mosi => ram_ss_ss_wide_mosi_arr(I),
+ ram_ss_ss_miso => ram_ss_ss_wide_miso_arr(I),
- -- Streaming
- input_sosi => input_sosi_arr(I),
- input_siso => input_siso_arr(I),
+ -- Streaming
+ input_sosi => input_sosi_arr(I),
+ input_siso => input_siso_arr(I),
- output_sosi => output_sosi_arr(I),
- output_siso => output_siso_arr(I)
- );
+ output_sosi => output_sosi_arr(I),
+ output_siso => output_siso_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd b/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
index 41916d90e0..52d1ad61d9 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
@@ -29,11 +29,11 @@
--
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity reorder_col_wide_select is
generic (
@@ -71,28 +71,28 @@ begin
-- by col_select_mosi to each stream.
gen_nof_input : for I in 0 to g_nof_inputs - 1 generate
u_reorder_col_select : entity work.reorder_col_select
- generic map (
- g_dsp_data_w => g_dsp_data_w,
- g_nof_ch_in => g_nof_ch_in,
- g_nof_ch_sel => g_nof_ch_sel,
- g_use_complex => g_use_complex
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_ch_in => g_nof_ch_in,
+ g_nof_ch_sel => g_nof_ch_sel,
+ g_use_complex => g_use_complex
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- Dynamic reorder block size control, same for all streams
- nof_ch_in => nof_ch_in,
- nof_ch_sel => nof_ch_sel,
+ -- Dynamic reorder block size control, same for all streams
+ nof_ch_in => nof_ch_in,
+ nof_ch_sel => nof_ch_sel,
- -- Memory Mapped
- col_select_mosi => col_select_mosi,
- col_select_miso => col_select_miso_arr(I),
+ -- Memory Mapped
+ col_select_mosi => col_select_mosi,
+ col_select_miso => col_select_miso_arr(I),
- -- Streaming
- input_sosi => input_sosi_arr(I),
- output_sosi => output_sosi_arr(I)
- );
+ -- Streaming
+ input_sosi => input_sosi_arr(I),
+ output_sosi => output_sosi_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/reorder/src/vhdl/reorder_matrix.vhd b/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
index 49a71a8025..2807371bb0 100644
--- a/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
@@ -47,11 +47,11 @@
--
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity reorder_matrix is
generic (
@@ -97,99 +97,99 @@ begin
-----------------------------------------------------------------------------
gen_dp_throttle_sop : for i in 0 to g_nof_inputs - 1 generate
u_dp_throttle_sop : entity dp_lib.dp_throttle_sop
- generic map (
- g_period => g_frame_size_out
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_out => input_siso_arr(i),
- snk_in => input_sosi_arr(i)
- );
+ generic map (
+ g_period => g_frame_size_out
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_out => input_siso_arr(i),
+ snk_in => input_sosi_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- Reorder input streams
-----------------------------------------------------------------------------
u_input_reorder : entity work.reorder_row
- generic map(
- g_nof_inputs => g_nof_inputs,
- g_nof_outputs => g_nof_internals,
- g_dsp_data_w => g_dsp_data_w,
- g_frame_size => g_frame_size_in,
- g_ram_init_file => g_reorder_in_file_name,
- g_pipeline_in => 1,
- g_pipeline_in_m => 1,
- g_pipeline_out => 1
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped
- ram_ss_reorder_mosi => ram_ss_reorder_in_mosi,
- ram_ss_reorder_miso => ram_ss_reorder_in_miso,
-
- -- Streaming
- input_sosi_arr => input_sosi_arr,
- output_sosi_arr => ss_wide_in_sosi_arr
- );
+ generic map(
+ g_nof_inputs => g_nof_inputs,
+ g_nof_outputs => g_nof_internals,
+ g_dsp_data_w => g_dsp_data_w,
+ g_frame_size => g_frame_size_in,
+ g_ram_init_file => g_reorder_in_file_name,
+ g_pipeline_in => 1,
+ g_pipeline_in_m => 1,
+ g_pipeline_out => 1
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped
+ ram_ss_reorder_mosi => ram_ss_reorder_in_mosi,
+ ram_ss_reorder_miso => ram_ss_reorder_in_miso,
+
+ -- Streaming
+ input_sosi_arr => input_sosi_arr,
+ output_sosi_arr => ss_wide_in_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Serial word selection per stream
-----------------------------------------------------------------------------
u_ss_wide : entity work.reorder_col_wide
- generic map (
- g_wb_factor => g_nof_internals,
- g_dsp_data_w => g_dsp_data_w,
- g_nof_ch_in => g_frame_size_in,
- g_nof_ch_sel => g_frame_size_out,
- g_select_file_prefix => g_ss_wide_file_prefix
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
-
- -- Streaming
- input_sosi_arr => ss_wide_in_sosi_arr,
- input_siso_arr => OPEN,
- output_sosi_arr => ss_wide_out_sosi_arr
- );
+ generic map (
+ g_wb_factor => g_nof_internals,
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_ch_in => g_frame_size_in,
+ g_nof_ch_sel => g_frame_size_out,
+ g_select_file_prefix => g_ss_wide_file_prefix
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+
+ -- Streaming
+ input_sosi_arr => ss_wide_in_sosi_arr,
+ input_siso_arr => OPEN,
+ output_sosi_arr => ss_wide_out_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Reorder output streams
-----------------------------------------------------------------------------
u_output_reorder : entity work.reorder_row
- generic map(
- g_nof_inputs => g_nof_internals,
- g_nof_outputs => g_nof_outputs,
- g_dsp_data_w => g_dsp_data_w,
- g_frame_size => g_frame_size_out,
- g_ram_init_file => g_reorder_out_file_name,
- g_pipeline_in => 1,
- g_pipeline_in_m => 1,
- g_pipeline_out => 1
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped
- ram_ss_reorder_mosi => ram_ss_reorder_out_mosi,
- ram_ss_reorder_miso => ram_ss_reorder_out_miso,
-
- -- Streaming
- input_sosi_arr => ss_wide_out_sosi_arr,
- output_sosi_arr => output_sosi_arr
- );
+ generic map(
+ g_nof_inputs => g_nof_internals,
+ g_nof_outputs => g_nof_outputs,
+ g_dsp_data_w => g_dsp_data_w,
+ g_frame_size => g_frame_size_out,
+ g_ram_init_file => g_reorder_out_file_name,
+ g_pipeline_in => 1,
+ g_pipeline_in_m => 1,
+ g_pipeline_out => 1
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped
+ ram_ss_reorder_mosi => ram_ss_reorder_out_mosi,
+ ram_ss_reorder_miso => ram_ss_reorder_out_miso,
+
+ -- Streaming
+ input_sosi_arr => ss_wide_out_sosi_arr,
+ output_sosi_arr => output_sosi_arr
+ );
end str;
diff --git a/libraries/base/reorder/src/vhdl/reorder_pkg.vhd b/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
index caad085b16..ee0fac76ae 100644
--- a/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
package reorder_pkg is
type t_reorder_seq is record
@@ -41,7 +41,7 @@ package reorder_pkg is
type t_reorder_table is array(integer range 0 to 31, integer range 0 to 31) of natural;
constant c_reorder_table: t_reorder_table :=
- (
+ (
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
@@ -74,7 +74,7 @@ package reorder_pkg is
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
- );
+ );
-- Block and data counters to derive select_copi.address for transpose
-- reording between nof_blocks_per_packet and nof_data_per_block.
@@ -90,12 +90,13 @@ package reorder_pkg is
-- Input block has nof_ch = nof_data_per_block * nof_blocks_per_packet
-- data per packet. The transpose.select_copi.address order will yield
-- transposed output, with nof_blocks_per_packet and nof_data_per_block.
- function func_reorder_transpose(nof_blocks_per_packet : natural;
- nof_data_per_block : natural;
- transpose : t_reorder_transpose)
- return t_reorder_transpose;
+ function func_reorder_transpose(
+ nof_blocks_per_packet : natural;
+ nof_data_per_block : natural;
+ transpose : t_reorder_transpose)
+ return t_reorder_transpose;
-end reorder_pkg;
+ end reorder_pkg;
package body reorder_pkg is
-- A transpose process and an undo transpose process can both use
@@ -134,10 +135,11 @@ package body reorder_pkg is
-- data_out: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- out_sosi
--
-- to restore the original order.
- function func_reorder_transpose(nof_blocks_per_packet : natural;
- nof_data_per_block : natural;
- transpose : t_reorder_transpose)
- return t_reorder_transpose is
+ function func_reorder_transpose(
+ nof_blocks_per_packet : natural;
+ nof_data_per_block : natural;
+ transpose : t_reorder_transpose)
+ return t_reorder_transpose is
variable v : t_reorder_transpose;
begin
v := transpose;
@@ -166,4 +168,4 @@ package body reorder_pkg is
return v;
end;
-end reorder_pkg;
+ end reorder_pkg;
diff --git a/libraries/base/reorder/src/vhdl/reorder_retreive.vhd b/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
index b8b15f6837..af71d35bb8 100644
--- a/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
@@ -20,28 +20,28 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-
--- Purpose: Retrieve blocks of g_nof_ch_sel complex data words from a dual
--- page data buffer
--- Description:
--- The retrieve control uses a channel select buffer to know the order
--- in which the g_nof_ch_sel complex data words have to be retrieved from the
--- dual page input data buffer. The order is arbitrary and the same channel
--- may be selected multiple times.
--- Remarks:
--- . Typcially output_siso.ready='1'. When g_nof_ch_sel < g_nof_ch_in/2, then a
--- toggling output_siso.ready can be used to multiplex this reorder retrieve output
--- with another reorder retrieve output stream.
--- . The retrieve_done signal occurs when the last data of the block is read
--- requested, so 1 cycle before the output_sosi.eop.
--- . The timing of the ch_cnt for the retrieve_mosi.address is such that the
--- reorder_col can store a frame and retrieve it immediately in any order, so worst
--- case the last stored data can be retrieved first.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+
+ -- Purpose: Retrieve blocks of g_nof_ch_sel complex data words from a dual
+ -- page data buffer
+ -- Description:
+ -- The retrieve control uses a channel select buffer to know the order
+ -- in which the g_nof_ch_sel complex data words have to be retrieved from the
+ -- dual page input data buffer. The order is arbitrary and the same channel
+ -- may be selected multiple times.
+ -- Remarks:
+ -- . Typcially output_siso.ready='1'. When g_nof_ch_sel < g_nof_ch_in/2, then a
+ -- toggling output_siso.ready can be used to multiplex this reorder retrieve output
+ -- with another reorder retrieve output stream.
+ -- . The retrieve_done signal occurs when the last data of the block is read
+ -- requested, so 1 cycle before the output_sosi.eop.
+ -- . The timing of the ch_cnt for the retrieve_mosi.address is such that the
+ -- reorder_col can store a frame and retrieve it immediately in any order, so worst
+ -- case the last stored data can be retrieved first.
entity reorder_retrieve is
generic (
@@ -109,22 +109,22 @@ begin
-- Enable retrieve when a block has been stored, disable retrieve when the block has been output
u_retrieve_en : entity common_lib.common_switch
- generic map (
- g_rst_level => '0',
- -- store_done has priority over nxt_retrieve_done when they occur simultaneously
- g_priority_lo => false,
- g_or_high => true,
- g_and_low => false
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => store_done,
- -- can not use retrieve_done with g_and_low = TRUE, because if retrieve_done
- -- occurs after next store_done then that page gets missed
- switch_low => nxt_retrieve_done,
- out_level => retrieve_en
- );
+ generic map (
+ g_rst_level => '0',
+ -- store_done has priority over nxt_retrieve_done when they occur simultaneously
+ g_priority_lo => false,
+ g_or_high => true,
+ g_and_low => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => store_done,
+ -- can not use retrieve_done with g_and_low = TRUE, because if retrieve_done
+ -- occurs after next store_done then that page gets missed
+ switch_low => nxt_retrieve_done,
+ out_level => retrieve_en
+ );
retrieve_ready <= retrieve_en and output_siso.ready;
diff --git a/libraries/base/reorder/src/vhdl/reorder_rewire.vhd b/libraries/base/reorder/src/vhdl/reorder_rewire.vhd
index 63abd6919c..e97db9f924 100644
--- a/libraries/base/reorder/src/vhdl/reorder_rewire.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_rewire.vhd
@@ -48,12 +48,12 @@
-- Some more remarks:
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.reorder_pkg.all;
entity reorder_rewire is
generic(
diff --git a/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd b/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd
index db85b9f482..fe60f94f59 100644
--- a/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd
@@ -40,9 +40,9 @@
-- |-----------------------------------------------------------------------|
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity reorder_rewire_reg is
generic (
@@ -71,11 +71,12 @@ architecture str of reorder_rewire_reg is
constant c_nof_required_registers : natural := 1; -- c_nof_required_bits MOD c_word_w;
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_required_registers),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_required_registers,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_required_registers),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_required_registers,
+ init_sl => '0');
-- FUNCTION array_init(init : NATURAL; nof, width : NATURAL) RETURN STD_LOGIC_VECTOR; -- useful to init an unconstrained std_logic_vector with repetitive content
constant c_reg_init : std_logic_vector(g_nof_streams * g_sel_in_w - 1 downto 0) := array_init(0, g_nof_streams, g_sel_in_w, 1);
@@ -84,32 +85,32 @@ architecture str of reorder_rewire_reg is
signal sel_in_reg : std_logic_vector(c_word_w - 1 downto 0);
begin
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1,
- g_readback => true,
- g_reg => c_mm_reg,
- g_init_reg => RESIZE_UVEC(c_reg_init, c_mem_reg_init_w) -- RESIZE_UVEC(TO_UVEC(1, c_word_w), c_mem_reg_init_w)
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1,
+ g_readback => true,
+ g_reg => c_mm_reg,
+ g_init_reg => RESIZE_UVEC(c_reg_init, c_mem_reg_init_w) -- RESIZE_UVEC(TO_UVEC(1, c_word_w), c_mem_reg_init_w)
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => sla_in,
- sla_out => sla_out,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => sla_in,
+ sla_out => sla_out,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_new => OPEN,
- in_reg => sel_in_reg, -- read
- out_reg => sel_in_reg, -- write
- out_new => open
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_new => OPEN,
+ in_reg => sel_in_reg, -- read
+ out_reg => sel_in_reg, -- write
+ out_new => open
+ );
sel_reg <= sel_in_reg(g_nof_streams * g_sel_in_w - 1 downto 0);
end str;
diff --git a/libraries/base/reorder/src/vhdl/reorder_row.vhd b/libraries/base/reorder/src/vhdl/reorder_row.vhd
index b02b86889f..6cfa19453f 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row.vhd
@@ -32,11 +32,11 @@
--
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity reorder_row is
generic (
@@ -81,17 +81,19 @@ architecture str of reorder_row is
constant c_mem_dat_w_mm : natural := 2**(true_log2(c_select_dat_w_mm));
constant c_mem_dat_w_dp : natural := 2**(true_log2(c_select_word_w));
- constant c_select_buf_mm : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_mem_nof_dat_mm),
- dat_w => c_mem_dat_w_mm,
- nof_dat => c_mem_nof_dat_mm,
- init_sl => '0');
+ constant c_select_buf_mm : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_mem_nof_dat_mm),
+ dat_w => c_mem_dat_w_mm,
+ nof_dat => c_mem_nof_dat_mm,
+ init_sl => '0');
- constant c_select_buf_dp : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_frame_size),
- dat_w => c_mem_dat_w_dp,
- nof_dat => g_frame_size,
- init_sl => '0');
+ constant c_select_buf_dp : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_frame_size),
+ dat_w => c_mem_dat_w_dp,
+ nof_dat => g_frame_size,
+ init_sl => '0');
constant c_data_w : natural := g_dsp_data_w * c_nof_complex;
constant c_mem_ratio_w : natural := c_mem_dat_w_dp / c_mem_dat_w_mm;
@@ -121,13 +123,13 @@ begin
gen_input : for I in g_nof_inputs - 1 downto 0 generate
use_complex : if g_use_complex generate
reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <=
- r.pipe_sosi_2arr(0)(I).im(g_dsp_data_w - 1 downto 0) &
- r.pipe_sosi_2arr(0)(I).re(g_dsp_data_w - 1 downto 0);
+ r.pipe_sosi_2arr(0)(I).im(g_dsp_data_w - 1 downto 0) &
+ r.pipe_sosi_2arr(0)(I).re(g_dsp_data_w - 1 downto 0);
end generate;
- use_data : if not g_use_complex generate
+ use_data : if not g_use_complex generate
reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <=
- r.pipe_sosi_2arr(0)(I).data(c_data_w - 1 downto 0);
+ r.pipe_sosi_2arr(0)(I).data(c_data_w - 1 downto 0);
end generate;
end generate;
@@ -138,21 +140,21 @@ begin
-- reorder_select signal.
---------------------------------------------------------------
u_reorder : entity common_lib.common_select_m_symbols
- generic map (
- g_nof_input => g_nof_inputs,
- g_nof_output => g_nof_outputs,
- g_symbol_w => c_nof_complex * g_dsp_data_w,
- g_pipeline_in => g_pipeline_in,
- g_pipeline_in_m => g_pipeline_in_m,
- g_pipeline_out => g_pipeline_out
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_data => reorder_in_dat,
- in_select => reorder_select(g_nof_outputs * c_select_w - 1 downto 0),
- out_data => reorder_out_dat
- );
+ generic map (
+ g_nof_input => g_nof_inputs,
+ g_nof_output => g_nof_outputs,
+ g_symbol_w => c_nof_complex * g_dsp_data_w,
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_in_m => g_pipeline_in_m,
+ g_pipeline_out => g_pipeline_out
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_data => reorder_in_dat,
+ in_select => reorder_select(g_nof_outputs * c_select_w - 1 downto 0),
+ out_data => reorder_out_dat
+ );
---------------------------------------------------------------
-- SELECTION BUFFER
@@ -160,29 +162,29 @@ begin
-- Buffer containing the selection words for a complete frame.
---------------------------------------------------------------
u_select_buf : entity common_lib.common_ram_crw_crw_ratio
- generic map(
- g_ram_a => c_select_buf_mm,
- g_ram_b => c_select_buf_dp,
- g_init_file => g_ram_init_file
- )
- port map (
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_ss_reorder_mosi.wr,
- wr_dat_a => ram_ss_reorder_mosi.wrdata(c_select_buf_mm.dat_w - 1 downto 0),
- adr_a => ram_ss_reorder_mosi.address(c_select_buf_mm.adr_w - 1 downto 0),
- rd_en_a => ram_ss_reorder_mosi.rd,
- rd_dat_a => ram_ss_reorder_miso.rddata(c_select_buf_mm.dat_w - 1 downto 0),
- rd_val_a => ram_ss_reorder_miso.rdval,
-
- rst_b => dp_rst,
- clk_b => dp_clk,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- adr_b => reorder_chan_cnt,
- rd_dat_b => reorder_select,
- rd_val_b => open
- );
+ generic map(
+ g_ram_a => c_select_buf_mm,
+ g_ram_b => c_select_buf_dp,
+ g_init_file => g_ram_init_file
+ )
+ port map (
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_ss_reorder_mosi.wr,
+ wr_dat_a => ram_ss_reorder_mosi.wrdata(c_select_buf_mm.dat_w - 1 downto 0),
+ adr_a => ram_ss_reorder_mosi.address(c_select_buf_mm.adr_w - 1 downto 0),
+ rd_en_a => ram_ss_reorder_mosi.rd,
+ rd_dat_a => ram_ss_reorder_miso.rddata(c_select_buf_mm.dat_w - 1 downto 0),
+ rd_val_a => ram_ss_reorder_miso.rdval,
+
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ adr_b => reorder_chan_cnt,
+ rd_dat_b => reorder_select,
+ rd_val_b => open
+ );
---------------------------------------------------------------
-- ADDRESS COUNTER
@@ -191,19 +193,19 @@ begin
---------------------------------------------------------------
gen_cnt : if g_frame_size > 1 generate
u_adr_chn_cnt : entity common_lib.common_counter
- generic map(
- g_latency => 1,
- g_init => 0,
- g_width => c_select_buf_dp.adr_w,
- g_max => g_frame_size
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- cnt_en => input_sosi_arr(0).valid,
- cnt_clr => input_sosi_arr(0).eop,
- count => reorder_chan_cnt
- );
+ generic map(
+ g_latency => 1,
+ g_init => 0,
+ g_width => c_select_buf_dp.adr_w,
+ g_max => g_frame_size
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ cnt_en => input_sosi_arr(0).valid,
+ cnt_clr => input_sosi_arr(0).eop,
+ count => reorder_chan_cnt
+ );
end generate;
gen_no_cnt : if g_frame_size = 1 generate
@@ -218,7 +220,7 @@ begin
-- Also the data-output of the select_m_symbols block is merged
-- here with the rest of the pipelined SOSI signals.
---------------------------------------------------------------
- comb : process(r, input_sosi_arr, reorder_out_dat)
+ comb : process(r, input_sosi_arr, reorder_out_dat)
variable v : reg_type;
-- Use intermediate variables to avoid too long code lines
variable v_re : std_logic_vector(g_dsp_data_w - 1 downto 0);
diff --git a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
index 429639223a..ecc6a50c57 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
@@ -32,11 +32,11 @@
-- in_select always has to be defined on the same clock cycle as the in_sosi data.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity reorder_row_select is
generic (
@@ -85,13 +85,13 @@ begin
gen_input : for I in g_nof_inputs - 1 downto 0 generate
use_complex : if g_use_complex generate
reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <=
- input_sosi_arr(I).im(g_dsp_data_w - 1 downto 0) &
- input_sosi_arr(I).re(g_dsp_data_w - 1 downto 0);
+ input_sosi_arr(I).im(g_dsp_data_w - 1 downto 0) &
+ input_sosi_arr(I).re(g_dsp_data_w - 1 downto 0);
end generate;
use_data : if not g_use_complex generate
reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <=
- input_sosi_arr(I).data(c_data_w - 1 downto 0);
+ input_sosi_arr(I).data(c_data_w - 1 downto 0);
end generate;
end generate;
@@ -102,21 +102,21 @@ begin
-- in_select signal.
---------------------------------------------------------------
u_reorder : entity common_lib.common_select_m_symbols
- generic map (
- g_nof_input => g_nof_inputs,
- g_nof_output => g_nof_outputs,
- g_symbol_w => c_data_w,
- g_pipeline_in => g_pipeline_in,
- g_pipeline_in_m => g_pipeline_in_m,
- g_pipeline_out => g_pipeline_out
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_data => reorder_in_dat,
- in_select => in_select,
- out_data => reorder_out_dat
- );
+ generic map (
+ g_nof_input => g_nof_inputs,
+ g_nof_output => g_nof_outputs,
+ g_symbol_w => c_data_w,
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_in_m => g_pipeline_in_m,
+ g_pipeline_out => g_pipeline_out
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_data => reorder_in_dat,
+ in_select => in_select,
+ out_data => reorder_out_dat
+ );
---------------------------------------------------------------
-- REGISTERING AND PIPELINING
diff --git a/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd b/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
index e23186e439..c786ac900e 100644
--- a/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
@@ -143,16 +143,16 @@
-- 3) Also be sure that nof_blocks is larger than or equal to rd_chunksize
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.reorder_pkg.all;
entity reorder_sequencer is
generic (
g_reorder_seq : t_reorder_seq := c_reorder_seq;
g_data_w_ratio : positive := 1 -- (256/256) Ratio between datawidth of the memory controller and SOSI domain
- ); -- Used to determine the width of counters.
+ ); -- Used to determine the width of counters.
port (
-- Clocks and reset
dp_rst : in std_logic; -- reset synchronous with st_clk
@@ -165,7 +165,7 @@ entity reorder_sequencer is
burstsize : out std_logic_vector;
done : in std_logic
- );
+ );
end reorder_sequencer;
architecture rtl of reorder_sequencer is
@@ -218,8 +218,8 @@ begin
case r.state is
when s_idle =>
if(done = '1') then
- v.first_write := '1';
- v.state := s_first_write;
+ v.first_write := '1';
+ v.state := s_first_write;
end if;
when s_first_write =>
@@ -231,11 +231,11 @@ begin
when s_write =>
if(done = '1') then
- v.wr_not_rd := '1';
- v.ddr3_en := '1';
- v.start_addr := r.wr_page_offset + r.wr_block_offset;
- v.burstsize := c_wr_chunksize;
- v.state := s_wait_wr;
+ v.wr_not_rd := '1';
+ v.ddr3_en := '1';
+ v.start_addr := r.wr_page_offset + r.wr_block_offset;
+ v.burstsize := c_wr_chunksize;
+ v.state := s_wait_wr;
end if;
when s_wait_wr =>
@@ -246,14 +246,14 @@ begin
when s_read =>
if(done = '1') then
- v.wr_not_rd := '0';
- if( r.first_write = '0') then
- v.ddr3_en := '1';
- end if;
- v.start_addr := r.rd_page_offset + r.rd_block_offset + r.rd_chunks_offset;
- v.burstsize := c_rd_chunksize;
- v.switch_cnt := r.switch_cnt + 1;
- v.state := s_wait_rd;
+ v.wr_not_rd := '0';
+ if( r.first_write = '0') then
+ v.ddr3_en := '1';
+ end if;
+ v.start_addr := r.rd_page_offset + r.rd_block_offset + r.rd_chunks_offset;
+ v.burstsize := c_rd_chunksize;
+ v.switch_cnt := r.switch_cnt + 1;
+ v.state := s_wait_rd;
end if;
when s_wait_rd =>
@@ -261,24 +261,24 @@ begin
v.rd_block_offset := r.rd_block_offset + c_rd_block_increment;
if(r.rd_block_offset + c_rd_block_increment >= c_page_size) then
- v.rd_chunks_offset := r.rd_chunks_offset + c_rd_chunksize;
- v.rd_block_offset := r.rd_block_offset + c_rd_block_increment - c_page_size;
+ v.rd_chunks_offset := r.rd_chunks_offset + c_rd_chunksize;
+ v.rd_block_offset := r.rd_block_offset + c_rd_block_increment - c_page_size;
end if;
if(r.switch_cnt = g_reorder_seq.rd_nof_chunks) then
- v.switch_cnt := 0;
- v.state := s_write;
- if(r.page_cnt = g_reorder_seq.nof_blocks) then
- v.rd_page_offset := r.wr_page_offset;
- v.wr_page_offset := r.rd_page_offset;
- v.page_cnt := 0;
- v.first_write := '0';
- v.rd_block_offset := 0;
- v.rd_chunks_offset := 0;
- v.wr_block_offset := 0;
- end if;
+ v.switch_cnt := 0;
+ v.state := s_write;
+ if(r.page_cnt = g_reorder_seq.nof_blocks) then
+ v.rd_page_offset := r.wr_page_offset;
+ v.wr_page_offset := r.rd_page_offset;
+ v.page_cnt := 0;
+ v.first_write := '0';
+ v.rd_block_offset := 0;
+ v.rd_chunks_offset := 0;
+ v.wr_block_offset := 0;
+ end if;
else
- v.state := s_read;
+ v.state := s_read;
end if;
when others =>
@@ -286,19 +286,19 @@ begin
end case;
if(dp_rst = '1') then
- v.rd_page_offset := c_page_size;
- v.wr_page_offset := 0;
- v.page_cnt := 0;
- v.switch_cnt := 0;
- v.ddr3_en := '0';
- v.wr_not_rd := '0';
- v.wr_block_offset := 0;
- v.rd_block_offset := 0;
- v.rd_chunks_offset := 0;
- v.start_addr := 0;
- v.burstsize := 0;
- v.first_write := '1';
- v.state := s_idle;
+ v.rd_page_offset := c_page_size;
+ v.wr_page_offset := 0;
+ v.page_cnt := 0;
+ v.switch_cnt := 0;
+ v.ddr3_en := '0';
+ v.wr_not_rd := '0';
+ v.wr_block_offset := 0;
+ v.rd_block_offset := 0;
+ v.rd_chunks_offset := 0;
+ v.start_addr := 0;
+ v.burstsize := 0;
+ v.first_write := '1';
+ v.state := s_idle;
end if;
rin <= v;
diff --git a/libraries/base/reorder/src/vhdl/reorder_store.vhd b/libraries/base/reorder/src/vhdl/reorder_store.vhd
index 75207311ae..0aab2ef9b0 100644
--- a/libraries/base/reorder/src/vhdl/reorder_store.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_store.vhd
@@ -20,34 +20,34 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-
--- Purpose: Controller that store blocks of nof_ch_in (complex) input data
--- words in a dual page data buffer
--- Description:
--- Write databuf control for nof_ch_in (complex) input data words and pulse
--- store_done for each nof_ch_in data words that have been written.
--- Maximum size for the dual page buffer is g_nof_ch_in. Default nof_ch_in
--- = g_nof_ch_in, but it can be used with smaller reorder block sizes.
--- Remarks:
--- . The reorder_store stores the complex input_sosi.re,im as concatenated
--- data = im & re with data width c_data_w, when g_use_complex = true. When
--- g_use_complex = false it stores c_data_w width of the input_sosi.data.
--- . The reorder_col does not use input_sosi.sop and eop, because it uses a
--- ch_cnt. Hence the input_sosi only needs to carry data, im, re and valid,
--- the input_sosi.sop and eop are ignored. The ch_cnt is needed anyway to
--- set the store_mosi.address. The nof_ch_in defines the number of valid
--- per input block, so from input_sosi.sop to input_sosi.eop. The
--- reorder_store assumes that the first input_sosi.valid corresponds to a
--- input_sosi.sop. The ch_cnt restarts at the and of a block, so when
--- ch_cnt = nof_ch_in-1.
--- . The store_done signal occurs when the last data of the input_sosi block
--- is being written, so 1 cycle after the input_sosi.eop.
--- . The store_busy goes high at in_sosi.sop and goes low after store_done.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+
+ -- Purpose: Controller that store blocks of nof_ch_in (complex) input data
+ -- words in a dual page data buffer
+ -- Description:
+ -- Write databuf control for nof_ch_in (complex) input data words and pulse
+ -- store_done for each nof_ch_in data words that have been written.
+ -- Maximum size for the dual page buffer is g_nof_ch_in. Default nof_ch_in
+ -- = g_nof_ch_in, but it can be used with smaller reorder block sizes.
+ -- Remarks:
+ -- . The reorder_store stores the complex input_sosi.re,im as concatenated
+ -- data = im & re with data width c_data_w, when g_use_complex = true. When
+ -- g_use_complex = false it stores c_data_w width of the input_sosi.data.
+ -- . The reorder_col does not use input_sosi.sop and eop, because it uses a
+ -- ch_cnt. Hence the input_sosi only needs to carry data, im, re and valid,
+ -- the input_sosi.sop and eop are ignored. The ch_cnt is needed anyway to
+ -- set the store_mosi.address. The nof_ch_in defines the number of valid
+ -- per input block, so from input_sosi.sop to input_sosi.eop. The
+ -- reorder_store assumes that the first input_sosi.valid corresponds to a
+ -- input_sosi.sop. The ch_cnt restarts at the and of a block, so when
+ -- ch_cnt = nof_ch_in-1.
+ -- . The store_done signal occurs when the last data of the input_sosi block
+ -- is being written, so 1 cycle after the input_sosi.eop.
+ -- . The store_busy goes high at in_sosi.sop and goes low after store_done.
entity reorder_store is
generic (
diff --git a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
index e62740d57c..0f75d579bb 100644
--- a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
@@ -76,12 +76,12 @@
-- Remarks:
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.reorder_pkg.all;
entity reorder_transpose is
generic(
@@ -126,7 +126,7 @@ entity reorder_transpose is
from_mem_snk_in : in t_dp_sosi;
from_mem_snk_out : out t_dp_siso := c_dp_siso_rdy
- );
+ );
end reorder_transpose;
architecture str of reorder_transpose is
@@ -255,79 +255,79 @@ begin
-- . to easy timing closure by decoupling the external memory interface and
-- the streaming input interface somewhat more (erko)
u_dp_pipeline_input : entity dp_lib.dp_pipeline
- generic map(
- g_pipeline => g_pipeline_input
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out => merged_snk_out,
- snk_in => merged_snk_in,
- -- ST source
- src_in => pipe_merged_snk_out,
- src_out => pipe_merged_snk_in
- );
+ generic map(
+ g_pipeline => g_pipeline_input
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => merged_snk_out,
+ snk_in => merged_snk_in,
+ -- ST source
+ src_in => pipe_merged_snk_out,
+ src_out => pipe_merged_snk_in
+ );
u_sync_check_and_restore : entity dp_lib.mms_dp_sync_checker
- generic map(
- g_nof_blk_per_sync => g_reorder_seq.nof_blocks
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- snk_out => pipe_merged_snk_out,
- snk_in => pipe_merged_snk_in,
- src_in => sync_checked_src_in,
- src_out => sync_checked_src_out,
- reg_dp_sync_checker_mosi => reg_dp_sync_checker_mosi,
- reg_dp_sync_checker_miso => reg_dp_sync_checker_miso
- );
+ generic map(
+ g_nof_blk_per_sync => g_reorder_seq.nof_blocks
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ snk_out => pipe_merged_snk_out,
+ snk_in => pipe_merged_snk_in,
+ src_in => sync_checked_src_in,
+ src_out => sync_checked_src_out,
+ reg_dp_sync_checker_mosi => reg_dp_sync_checker_mosi,
+ reg_dp_sync_checker_miso => reg_dp_sync_checker_miso
+ );
gen_pre_transpose : if g_ena_pre_transp = true generate
-- Packet merge is required for reorder_col.
u_dp_packet_merge : entity dp_lib.dp_packet_merge
- generic map (
- g_nof_pkt => g_reorder_seq.rd_chunksize
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_nof_pkt => g_reorder_seq.rd_chunksize
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- snk_out => sync_checked_src_in,
- snk_in => sync_checked_src_out,
+ snk_out => sync_checked_src_in,
+ snk_in => sync_checked_src_out,
- src_in => ss_in_siso,
- src_out => ss_in_sosi
- );
+ src_in => ss_in_siso,
+ src_out => ss_in_sosi
+ );
u_single_ss : entity work.reorder_col
- generic map (
- g_dsp_data_w => c_data_w_pre,
- g_nof_ch_in => c_nof_ch_in,
- g_nof_ch_sel => c_nof_ch_sel,
- g_select_file_name => g_select_file,
- g_use_complex => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped
- ram_ss_ss_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_miso => ram_ss_ss_transp_miso,
-
- -- Streaming
- input_sosi => ss_in_sosi,
- input_siso => OPEN, -- Don't allow backpressure.
-
- output_sosi => i_to_mem_src_out,
- output_siso => to_mem_src_in
- );
+ generic map (
+ g_dsp_data_w => c_data_w_pre,
+ g_nof_ch_in => c_nof_ch_in,
+ g_nof_ch_sel => c_nof_ch_sel,
+ g_select_file_name => g_select_file,
+ g_use_complex => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped
+ ram_ss_ss_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_miso => ram_ss_ss_transp_miso,
+
+ -- Streaming
+ input_sosi => ss_in_sosi,
+ input_siso => OPEN, -- Don't allow backpressure.
+
+ output_sosi => i_to_mem_src_out,
+ output_siso => to_mem_src_in
+ );
end generate;
gen_not_pre_transpose : if g_ena_pre_transp = false generate
@@ -345,106 +345,106 @@ begin
dvr_wr_flush_en <= '0';
u_ddr_sequencer: entity work.reorder_sequencer
- generic map(
- g_reorder_seq => g_reorder_seq,
- g_data_w_ratio => c_data_w_ratio
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map(
+ g_reorder_seq => g_reorder_seq,
+ g_data_w_ratio => c_data_w_ratio
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- en_evt => dvr_en,
- wr_not_rd => dvr_wr_not_rd,
+ en_evt => dvr_en,
+ wr_not_rd => dvr_wr_not_rd,
- address => dvr_start_address,
- burstsize => dvr_nof_data,
+ address => dvr_start_address,
+ burstsize => dvr_nof_data,
- done => dvr_done
- );
+ done => dvr_done
+ );
---------------------------------------------------------------
-- FIFO FOR SYNC-BSN
---------------------------------------------------------------
u_sync_bsn_fifo : entity common_lib.common_fifo_sc
- generic map (
- g_use_lut => true, -- Make this FIFO in logic, since it's only 2 words deep.
- g_reset => false,
- g_init => false,
- g_dat_w => c_dp_stream_bsn_w,
- g_nof_words => 4 -- 2 sync intervals should be sufficient, choose 4 to be safe (erko)
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- wr_dat => pipe_merged_snk_in.bsn,
- wr_req => pipe_merged_snk_in.sync,
- wr_ful => open ,
- rd_dat => rd_dat_i,
- rd_req => rd_req_i,
- rd_emp => open,
- rd_val => rd_val_i,
- usedw => open
- );
+ generic map (
+ g_use_lut => true, -- Make this FIFO in logic, since it's only 2 words deep.
+ g_reset => false,
+ g_init => false,
+ g_dat_w => c_dp_stream_bsn_w,
+ g_nof_words => 4 -- 2 sync intervals should be sufficient, choose 4 to be safe (erko)
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ wr_dat => pipe_merged_snk_in.bsn,
+ wr_req => pipe_merged_snk_in.sync,
+ wr_ful => open ,
+ rd_dat => rd_dat_i,
+ rd_req => rd_req_i,
+ rd_emp => open,
+ rd_val => rd_val_i,
+ usedw => open
+ );
---------------------------------------------------------------
-- CREATE READ-AHEAD FIFO INTERFACE FOR SYNC-BSN
---------------------------------------------------------------
u_fifo_adapter : entity common_lib.common_fifo_rd
- generic map (
- g_dat_w => c_dp_stream_bsn_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink: RL = 1
- fifo_req => rd_req_i,
- fifo_dat => rd_dat_i,
- fifo_val => rd_val_i,
- -- ST source: RL = 0
- rd_req => block_gen_out_sosi.sync,
- rd_dat => sync_bsn,
- rd_val => open
- );
+ generic map (
+ g_dat_w => c_dp_stream_bsn_w
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink: RL = 1
+ fifo_req => rd_req_i,
+ fifo_dat => rd_dat_i,
+ fifo_val => rd_val_i,
+ -- ST source: RL = 0
+ rd_req => block_gen_out_sosi.sync,
+ rd_dat => sync_bsn,
+ rd_val => open
+ );
-----------------------
-- Pipeline to match latency of dp_block_gen
-----------------------
u_dp_pipeline : entity dp_lib.dp_pipeline
- generic map(
- g_pipeline => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => from_mem_snk_in,
- -- ST source
- src_in => OPEN,
- src_out => from_mem_out_sosi
- );
+ generic map(
+ g_pipeline => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => from_mem_snk_in,
+ -- ST source
+ src_in => OPEN,
+ src_out => from_mem_out_sosi
+ );
--------------------
-- DP BLOCK GEN (providing sop/eop)
--------------------
u_dp_block_gen : entity dp_lib.dp_block_gen
- generic map(
- g_use_src_in => false,
- g_nof_data => g_frame_size_out,
- g_nof_blk_per_sync => g_reorder_seq.nof_blocks,
- g_empty => 0,
- g_channel => 0,
- g_error => 0
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- snk_in => from_mem_snk_in,
-
- -- Use incoming data to generate more data
- src_out => block_gen_out_sosi,
- en => '1'
- );
+ generic map(
+ g_use_src_in => false,
+ g_nof_data => g_frame_size_out,
+ g_nof_blk_per_sync => g_reorder_seq.nof_blocks,
+ g_empty => 0,
+ g_channel => 0,
+ g_error => 0
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => from_mem_snk_in,
+
+ -- Use incoming data to generate more data
+ src_out => block_gen_out_sosi,
+ en => '1'
+ );
from_mem_snk_out <= src_in_arr(0);
@@ -483,16 +483,16 @@ begin
-- the streaming output interface somewhat more (erko)
-----------------------
u_dp_pipeline_arr : entity dp_lib.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => g_pipeline_output -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => merge_src_out_arr,
- -- ST source
- src_out_arr => i_src_out_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => g_pipeline_output -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => merge_src_out_arr,
+ -- ST source
+ src_out_arr => i_src_out_arr
+ );
end str;
diff --git a/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd b/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd
index 262a2b142e..ae456e307c 100644
--- a/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd
@@ -37,17 +37,17 @@
-- > Evalute the WAVE window.
library IEEE, common_lib, mm_lib, diag_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
entity tb_mmf_reorder_matrix is
generic(
@@ -152,7 +152,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -161,142 +161,151 @@ begin
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_ram_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+ u_mm_file_ram_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
- u_mm_file_reg_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+ u_mm_file_reg_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
- u_mm_file_ram_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+ u_mm_file_ram_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
- u_mm_file_reg_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+ u_mm_file_reg_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
- u_mm_file_ram_ss_reorder_in : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER_IN")
- port map(mm_rst, mm_clk, ram_ss_reorder_in_mosi, ram_ss_reorder_in_miso);
+ u_mm_file_ram_ss_reorder_in : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER_IN")
+ port map(mm_rst, mm_clk, ram_ss_reorder_in_mosi, ram_ss_reorder_in_miso);
- u_mm_file_ram_ss_reorder_out : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER_OUT")
- port map(mm_rst, mm_clk, ram_ss_reorder_out_mosi, ram_ss_reorder_out_miso);
+ u_mm_file_ram_ss_reorder_out : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER_OUT")
+ port map(mm_rst, mm_clk, ram_ss_reorder_out_mosi, ram_ss_reorder_out_miso);
- u_mm_file_ram_ss_ss_wide : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_SS_WIDE")
- port map(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso);
+ u_mm_file_ram_ss_ss_wide : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_SS_WIDE")
+ port map(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => c_bg_nof_output_streams,
- g_buf_dat_w => c_bg_buf_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w,
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut : entity work.reorder_matrix
- generic map(
- g_nof_inputs => g_nof_inputs,
- g_nof_internals => g_nof_internals,
- g_nof_outputs => g_nof_outputs,
- g_dsp_data_w => g_dsp_data_w,
- g_frame_size_in => g_frame_size_in,
- g_frame_size_out => g_frame_size_out
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- Memory Mapped
- ram_ss_reorder_in_mosi => ram_ss_reorder_in_mosi,
- ram_ss_reorder_in_miso => ram_ss_reorder_in_miso,
- ram_ss_reorder_out_mosi => ram_ss_reorder_out_mosi,
- ram_ss_reorder_out_miso => ram_ss_reorder_out_miso,
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- -- Streaming
- input_sosi_arr => bg_sosi_arr,
- output_sosi_arr => out_sosi_arr,
- output_siso_arr => out_siso_arr
- );
+ generic map(
+ g_nof_inputs => g_nof_inputs,
+ g_nof_internals => g_nof_internals,
+ g_nof_outputs => g_nof_outputs,
+ g_dsp_data_w => g_dsp_data_w,
+ g_frame_size_in => g_frame_size_in,
+ g_frame_size_out => g_frame_size_out
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- Memory Mapped
+ ram_ss_reorder_in_mosi => ram_ss_reorder_in_mosi,
+ ram_ss_reorder_in_miso => ram_ss_reorder_in_miso,
+ ram_ss_reorder_out_mosi => ram_ss_reorder_out_mosi,
+ ram_ss_reorder_out_miso => ram_ss_reorder_out_miso,
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ -- Streaming
+ input_sosi_arr => bg_sosi_arr,
+ output_sosi_arr => out_sosi_arr,
+ output_siso_arr => out_siso_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_re,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
- ram_data_buf_miso => ram_diag_data_buf_re_miso,
- reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
- reg_data_buf_miso => reg_diag_data_buf_re_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_im,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
- ram_data_buf_miso => ram_diag_data_buf_im_miso,
- reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
- reg_data_buf_miso => reg_diag_data_buf_im_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_im,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd b/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd
index ee1bdadda1..c88958ed77 100644
--- a/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd
@@ -37,17 +37,17 @@
-- > Evalute the WAVE window.
library IEEE, common_lib, mm_lib, diag_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
entity tb_mmf_reorder_row is
generic(
@@ -148,7 +148,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -157,140 +157,147 @@ begin
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_ram_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+ u_mm_file_ram_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
- u_mm_file_reg_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+ u_mm_file_reg_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
- u_mm_file_ram_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+ u_mm_file_ram_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
- u_mm_file_reg_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+ u_mm_file_reg_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
- u_mm_file_ram_ss_reorder : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER")
- port map(mm_rst, mm_clk, ram_ss_reorder_mosi, ram_ss_reorder_miso);
+ u_mm_file_ram_ss_reorder : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER")
+ port map(mm_rst, mm_clk, ram_ss_reorder_mosi, ram_ss_reorder_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => c_bg_nof_output_streams,
- g_buf_dat_w => c_bg_buf_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w,
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut : entity work.reorder_row
- generic map(
- g_nof_inputs => g_nof_inputs,
- g_nof_outputs => g_nof_outputs,
- g_dsp_data_w => g_dsp_data_w,
- g_frame_size => g_frame_size,
- g_ram_init_file => g_ram_init_file,
- g_pipeline_in => g_pipeline_in,
- g_pipeline_in_m => g_pipeline_in_m,
- g_pipeline_out => g_pipeline_out
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- Memory Mapped
- ram_ss_reorder_mosi => ram_ss_reorder_mosi,
- ram_ss_reorder_miso => ram_ss_reorder_miso,
- -- Streaming
- input_sosi_arr => bg_sosi_arr,
- output_sosi_arr => out_sosi_arr,
- output_siso_arr => out_siso_arr
- );
+ generic map(
+ g_nof_inputs => g_nof_inputs,
+ g_nof_outputs => g_nof_outputs,
+ g_dsp_data_w => g_dsp_data_w,
+ g_frame_size => g_frame_size,
+ g_ram_init_file => g_ram_init_file,
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_in_m => g_pipeline_in_m,
+ g_pipeline_out => g_pipeline_out
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- Memory Mapped
+ ram_ss_reorder_mosi => ram_ss_reorder_mosi,
+ ram_ss_reorder_miso => ram_ss_reorder_miso,
+ -- Streaming
+ input_sosi_arr => bg_sosi_arr,
+ output_sosi_arr => out_sosi_arr,
+ output_siso_arr => out_siso_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_re,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
- ram_data_buf_miso => ram_diag_data_buf_re_miso,
-
- reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
- reg_data_buf_miso => reg_diag_data_buf_re_miso,
-
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_im,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
- ram_data_buf_miso => ram_diag_data_buf_im_miso,
-
- reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
- reg_data_buf_miso => reg_diag_data_buf_im_miso,
-
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_im,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd b/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
index 5572720cd7..2d3381da05 100644
--- a/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
@@ -31,25 +31,25 @@
-- > Evalute u_dr_mem_ctrl/u_io_driver/ctlr_mosi in the WAVE window for wr and rd activity.
library IEEE, common_lib, mm_lib, diag_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.reorder_pkg.all;
entity tb_mms_reorder_rewire is
generic (
g_nof_streams : positive := 8;
g_in_dat_w : positive := 8;
g_use_sel_table : boolean := false
- );
+ );
end tb_mms_reorder_rewire;
architecture tb of tb_mms_reorder_rewire is
@@ -89,8 +89,8 @@ architecture tb of tb_mms_reorder_rewire is
signal reg_reorder_rewire_miso : t_mem_miso := c_mem_miso_rst;
constant c_sel_table: t_reorder_table :=
- (
- --FN0 FN1 FN2 FN3 BN0 BN1 BN2 BN3
+ (
+ --FN0 FN1 FN2 FN3 BN0 BN1 BN2 BN3
( 19, 10, 13, 16, 8 , 8 , 8 , 8 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 0
( 10, 13, 16, 19, 11, 11, 11, 11, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 1
( 13, 16, 19, 10, 14, 14, 14, 14, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 2
@@ -123,7 +123,7 @@ architecture tb of tb_mms_reorder_rewire is
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
- );
+ );
-- Custom definitions of constants
constant c_bg_block_len : natural := 16;
@@ -139,14 +139,15 @@ architecture tb of tb_mms_reorder_rewire is
constant c_bg_data_file_prefix : string := "UNUSED"; -- "../../../src/hex/tb_bg_dat";
constant c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, 128, 1);
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable: On by default in simulation; MM enable required on hardware.
- '0', -- enable_sync
- TO_UVEC( c_bg_block_len, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC ( c_bg_block_len - 1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable: On by default in simulation; MM enable required on hardware.
+ '0', -- enable_sync
+ TO_UVEC( c_bg_block_len, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(c_bg_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC ( c_bg_block_len - 1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
-- Configuration of the databuffers:
constant c_db_nof_streams : positive := g_nof_streams;
@@ -175,7 +176,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -185,101 +186,106 @@ begin
-- MM buses
----------------------------------------------------------------------------
-- TB
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+ u_mm_file_ram_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
- u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+ u_mm_file_reg_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
- u_mm_file_reg_reorder_rewire : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_REORDER_REWIRE")
- port map(mm_rst, mm_clk, reg_reorder_rewire_mosi, reg_reorder_rewire_miso);
+ u_mm_file_reg_reorder_rewire : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_REORDER_REWIRE")
+ port map(mm_rst, mm_clk, reg_reorder_rewire_mosi, reg_reorder_rewire_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => c_bg_nof_output_streams,
- g_buf_dat_w => c_bg_buf_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w,
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix,
- g_diag_block_gen_rst => c_bg_ctrl
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix,
+ g_diag_block_gen_rst => c_bg_ctrl
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut : entity work.mms_reorder_rewire
- generic map (
- g_select_table => c_sel_table,
- g_nof_streams => g_nof_streams,
- g_sel_in_w => c_sel_in_w,
- g_use_sel_table => g_use_sel_table
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- reg_mosi => reg_reorder_rewire_mosi,
- reg_miso => reg_reorder_rewire_miso,
+ generic map (
+ g_select_table => c_sel_table,
+ g_nof_streams => g_nof_streams,
+ g_sel_in_w => c_sel_in_w,
+ g_use_sel_table => g_use_sel_table
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ reg_mosi => reg_reorder_rewire_mosi,
+ reg_miso => reg_reorder_rewire_miso,
- -- ST sinks
- snk_out_arr => bg_siso_arr,
- snk_in_arr => bg_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr
- );
+ -- ST sinks
+ snk_out_arr => bg_siso_arr,
+ snk_in_arr => bg_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer
----------------------------------------------------------------------------
u_data_buf : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- -- ST interface
- in_sync => out_sosi_arr(0).sync,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => out_sosi_arr(0).sync,
+ in_sosi_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
index c0669ea2df..71ae4fa990 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
@@ -20,36 +20,36 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-
--- Usage:
--- > as 10
--- > run -all
--- . Observe in_sosi and out_sosi in the Wave window
---
--- Description:
--- . This tb_ss for the subband select (SS) self verifies the data, sync and BSN
--- . The flow control is selected via g_mode_in_en and g_mode_out_ready.
---
--- Remark:
--- . Use tb_tb_ss for multi-tb DUT verification.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+
+ -- Usage:
+ -- > as 10
+ -- > run -all
+ -- . Observe in_sosi and out_sosi in the Wave window
+ --
+ -- Description:
+ -- . This tb_ss for the subband select (SS) self verifies the data, sync and BSN
+ -- . The flow control is selected via g_mode_in_en and g_mode_out_ready.
+ --
+ -- Remark:
+ -- . Use tb_tb_ss for multi-tb DUT verification.
entity tb_reorder_col is
generic (
-- Flow control
g_mode_in_en : natural := 0; -- use 0 for active in_sosi.valid control
- -- use 1 for random in_sosi.valid control
+ -- use 1 for random in_sosi.valid control
g_mode_out_ready : natural := 0; -- use 0 for active out_siso.ready control
- -- use 1 for toggling out_siso.ready control, requires g_nof_ch_sel <= g_nof_ch_in/2
- -- use 2 for inverted toggling out_siso.ready control, requires g_nof_ch_sel <= g_nof_ch_in/2
+ -- use 1 for toggling out_siso.ready control, requires g_nof_ch_sel <= g_nof_ch_in/2
+ -- use 2 for inverted toggling out_siso.ready control, requires g_nof_ch_sel <= g_nof_ch_in/2
-- Test duration
g_nof_sync : natural := 10;
@@ -218,11 +218,42 @@ begin
end process;
u_reverse_ss : entity work.reorder_col
+ generic map (
+ g_use_output_rl_adapter => g_use_output_rl_adapter,
+ g_dsp_data_w => c_dsp_data_w,
+ g_nof_ch_in => g_nof_ch_in,
+ g_nof_ch_sel => g_nof_ch_in,
+ g_use_complex => g_use_complex
+ )
+ port map (
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+
+ -- Memory Mapped
+ ram_ss_ss_mosi => mm_reverse_mosi,
+ ram_ss_ss_miso => OPEN,
+
+ -- Streaming
+ input_sosi => dp_sosi,
+
+ output_sosi => reverse_sosi,
+ output_siso => c_dp_siso_rdy
+ );
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- DUT : SS
+ ------------------------------------------------------------------------------
+ in_sosi <= dp_sosi when g_reverse_ss_map = false else reverse_sosi;
+
+ u_dut_ss : entity work.reorder_col
generic map (
g_use_output_rl_adapter => g_use_output_rl_adapter,
g_dsp_data_w => c_dsp_data_w,
g_nof_ch_in => g_nof_ch_in,
- g_nof_ch_sel => g_nof_ch_in,
+ g_nof_ch_sel => g_nof_ch_sel,
g_use_complex => g_use_complex
)
port map (
@@ -232,46 +263,15 @@ begin
dp_clk => clk,
-- Memory Mapped
- ram_ss_ss_mosi => mm_reverse_mosi,
+ ram_ss_ss_mosi => mm_dut_mosi,
ram_ss_ss_miso => OPEN,
-- Streaming
- input_sosi => dp_sosi,
+ input_sosi => in_sosi,
- output_sosi => reverse_sosi,
- output_siso => c_dp_siso_rdy
+ output_sosi => out_sosi,
+ output_siso => out_siso
);
- end generate;
-
- ------------------------------------------------------------------------------
- -- DUT : SS
- ------------------------------------------------------------------------------
- in_sosi <= dp_sosi when g_reverse_ss_map = false else reverse_sosi;
-
- u_dut_ss : entity work.reorder_col
- generic map (
- g_use_output_rl_adapter => g_use_output_rl_adapter,
- g_dsp_data_w => c_dsp_data_w,
- g_nof_ch_in => g_nof_ch_in,
- g_nof_ch_sel => g_nof_ch_sel,
- g_use_complex => g_use_complex
- )
- port map (
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
-
- -- Memory Mapped
- ram_ss_ss_mosi => mm_dut_mosi,
- ram_ss_ss_miso => OPEN,
-
- -- Streaming
- input_sosi => in_sosi,
-
- output_sosi => out_sosi,
- output_siso => out_siso
- );
------------------------------------------------------------------------------
-- Verify
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
index c335260390..6df1e508c6 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
@@ -65,14 +65,14 @@
-- by stopping the clk and thus all toggling.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.reorder_pkg.all;
entity tb_reorder_col_select_all is
generic(
@@ -188,21 +188,21 @@ begin
-- First packet in sync interval
v_nof_ch := nof_ch_input;
proc_dp_gen_block_data(c_rl,
- c_use_data,
- g_dsp_data_w,
- g_dsp_data_w,
- v_data, -- data
- v_data, -- re
- v_data + 1, -- im
- v_nof_ch,
- v_info + 2, -- channel
- v_info + 3, -- error
- '1', -- with sync
- v_bsn, -- bsn
- clk,
- in_en,
- in_siso,
- in_sosi);
+ c_use_data,
+ g_dsp_data_w,
+ g_dsp_data_w,
+ v_data, -- data
+ v_data, -- re
+ v_data + 1, -- im
+ v_nof_ch,
+ v_info + 2, -- channel
+ v_info + 3, -- error
+ '1', -- with sync
+ v_bsn, -- bsn
+ clk,
+ in_en,
+ in_siso,
+ in_sosi);
proc_common_wait_some_cycles(clk, g_inter_packet_gap);
for J in 0 to g_nof_packets_per_sync - 2 loop
-- Next packets in sync interval
@@ -211,21 +211,21 @@ begin
v_info := v_info + 1;
v_data := v_data + v_nof_ch;
proc_dp_gen_block_data(c_rl,
- c_use_data,
- g_dsp_data_w,
- g_dsp_data_w,
- v_data, -- data
- v_data, -- re
- v_data + 1, -- im
- v_nof_ch,
- v_info + 2, -- channel
- v_info + 3, -- error
- '0', -- no sync
- v_bsn, -- bsn
- clk,
- in_en,
- in_siso,
- in_sosi);
+ c_use_data,
+ g_dsp_data_w,
+ g_dsp_data_w,
+ v_data, -- data
+ v_data, -- re
+ v_data + 1, -- im
+ v_nof_ch,
+ v_info + 2, -- channel
+ v_info + 3, -- error
+ '0', -- no sync
+ v_bsn, -- bsn
+ clk,
+ in_en,
+ in_siso,
+ in_sosi);
proc_common_wait_some_cycles(clk, g_inter_packet_gap);
end loop;
v_bsn := INCR_UVEC(v_bsn, 1);
@@ -271,26 +271,26 @@ begin
verify_en_out_sosi_long <= verify_en_sosi when sel_long = true else c_dp_sosi_sl_rst;
u_verify_out_sosi : entity dp_lib.dp_stream_verify
- generic map (
- -- initializations
- g_sync_period => g_nof_packets_per_sync, -- BSN increment per sync interval
- g_sync_offset => 0, -- first BSN
- -- specific
- g_in_dat_w => c_data_w,
- g_pkt_len => c_nof_ch
- )
- port map (
- rst => rst,
- clk => clk,
- -- Verify data
- snk_in => out_sosi,
- -- During stimuli
- verify_snk_in_enable => verify_en_out_sosi,
-
- -- End of stimuli
- expected_snk_in => c_dp_sosi_rst,
- verify_expected_snk_in_evt => c_dp_sosi_sl_rst
- );
+ generic map (
+ -- initializations
+ g_sync_period => g_nof_packets_per_sync, -- BSN increment per sync interval
+ g_sync_offset => 0, -- first BSN
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_pkt_len => c_nof_ch
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Verify data
+ snk_in => out_sosi,
+ -- During stimuli
+ verify_snk_in_enable => verify_en_out_sosi,
+
+ -- End of stimuli
+ expected_snk_in => c_dp_sosi_rst,
+ verify_expected_snk_in_evt => c_dp_sosi_sl_rst
+ );
-- When g_use_dynamic_selection = true then c_nof_sync = 2 and second sync interval
-- will contain the long packets. All sync intervals have g_nof_packets_per_sync.
@@ -298,26 +298,26 @@ begin
-- sync interval with the long packets, will start with BSN = g_sync_offset =
-- g_nof_packets_per_sync.
u_verify_out_sosi_long : entity dp_lib.dp_stream_verify
- generic map (
- -- initializations
- g_sync_period => g_nof_packets_per_sync,
- g_sync_offset => g_nof_packets_per_sync,
- -- specific
- g_in_dat_w => c_data_w,
- g_pkt_len => c_nof_ch_long
- )
- port map (
- rst => rst,
- clk => clk,
- -- Verify data
- snk_in => out_sosi,
- -- During stimuli
- verify_snk_in_enable => verify_en_out_sosi_long,
-
- -- End of stimuli
- expected_snk_in => c_dp_sosi_rst,
- verify_expected_snk_in_evt => c_dp_sosi_sl_rst
- );
+ generic map (
+ -- initializations
+ g_sync_period => g_nof_packets_per_sync,
+ g_sync_offset => g_nof_packets_per_sync,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_pkt_len => c_nof_ch_long
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Verify data
+ snk_in => out_sosi,
+ -- During stimuli
+ verify_snk_in_enable => verify_en_out_sosi_long,
+
+ -- End of stimuli
+ expected_snk_in => c_dp_sosi_rst,
+ verify_expected_snk_in_evt => c_dp_sosi_sl_rst
+ );
------------------------------------------------------------------------------
-- DUT
@@ -387,64 +387,64 @@ begin
g_nof_data_per_block * c_factor_dat;
u_transpose : entity work.reorder_col_select
- generic map (
- g_dsp_data_w => g_dsp_data_w,
- g_nof_ch_in => c_nof_ch_long,
- g_nof_ch_sel => c_nof_ch_long,
- g_use_complex => g_use_complex
- )
- port map (
- dp_rst => rst,
- dp_clk => clk,
-
- reorder_busy => reorder_busy_transposed,
-
- -- Dynamic reorder block size control
- nof_ch_in => nof_ch_input,
- nof_ch_sel => nof_ch_input,
-
- -- Captured reorder block size control used for output_sosi
- output_nof_ch_in => nof_ch_transposed,
- output_nof_ch_sel => open,
-
- -- Memory Mapped
- col_select_mosi => r_transpose.select_copi,
- col_select_miso => select_cipo, -- only used for waitrequest
-
- -- Streaming
- input_sosi => in_sosi,
- output_sosi => transposed_sosi
- );
+ generic map (
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_ch_in => c_nof_ch_long,
+ g_nof_ch_sel => c_nof_ch_long,
+ g_use_complex => g_use_complex
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => clk,
+
+ reorder_busy => reorder_busy_transposed,
+
+ -- Dynamic reorder block size control
+ nof_ch_in => nof_ch_input,
+ nof_ch_sel => nof_ch_input,
+
+ -- Captured reorder block size control used for output_sosi
+ output_nof_ch_in => nof_ch_transposed,
+ output_nof_ch_sel => open,
+
+ -- Memory Mapped
+ col_select_mosi => r_transpose.select_copi,
+ col_select_miso => select_cipo, -- only used for waitrequest
+
+ -- Streaming
+ input_sosi => in_sosi,
+ output_sosi => transposed_sosi
+ );
u_undo_transpose : entity work.reorder_col_select
- generic map (
- g_dsp_data_w => g_dsp_data_w,
- g_nof_ch_in => c_nof_ch_long,
- g_nof_ch_sel => c_nof_ch_long,
- g_use_complex => g_use_complex
- )
- port map (
- dp_rst => rst,
- dp_clk => clk,
-
- reorder_busy => reorder_busy_output,
-
- -- Dynamic reorder block size control
- nof_ch_in => nof_ch_transposed,
- nof_ch_sel => nof_ch_transposed,
-
- -- Captured reorder block size control used for output_sosi
- output_nof_ch_in => nof_ch_output,
- output_nof_ch_sel => open,
-
- -- Memory Mapped
- col_select_mosi => r_undo_transpose.select_copi,
- col_select_miso => undo_select_cipo, -- only used for waitrequest
-
- -- Streaming
- input_sosi => transposed_sosi,
- output_sosi => out_sosi
- );
+ generic map (
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_ch_in => c_nof_ch_long,
+ g_nof_ch_sel => c_nof_ch_long,
+ g_use_complex => g_use_complex
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => clk,
+
+ reorder_busy => reorder_busy_output,
+
+ -- Dynamic reorder block size control
+ nof_ch_in => nof_ch_transposed,
+ nof_ch_sel => nof_ch_transposed,
+
+ -- Captured reorder block size control used for output_sosi
+ output_nof_ch_in => nof_ch_output,
+ output_nof_ch_sel => open,
+
+ -- Memory Mapped
+ col_select_mosi => r_undo_transpose.select_copi,
+ col_select_miso => undo_select_cipo, -- only used for waitrequest
+
+ -- Streaming
+ input_sosi => transposed_sosi,
+ output_sosi => out_sosi
+ );
reorder_busy <= reorder_busy_transposed or reorder_busy_output;
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd
index d6d5d66f9c..2b25faebbf 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd
@@ -20,21 +20,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-
--- Usage:
--- > as 10
--- > run -all
--- . Observe in_sosi_arr and out_sosi_arr in the Wave window
---
--- Description:
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+
+ -- Usage:
+ -- > as 10
+ -- > run -all
+ -- . Observe in_sosi_arr and out_sosi_arr in the Wave window
+ --
+ -- Description:
entity tb_reorder_col_wide is
end tb_reorder_col_wide;
@@ -152,27 +152,27 @@ begin
end process;
u_dut : entity work.reorder_col_wide
- generic map (
- g_wb_factor => c_wb_factor,
- g_dsp_data_w => c_dsp_data_w,
- g_nof_ch_in => c_nof_ch_in,
- g_nof_ch_sel => c_nof_ch_sel,
- g_select_file_prefix => c_select_file_prefix
- )
- port map (
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
-
- -- Memory Mapped
- ram_ss_ss_wide_mosi => mm_mosi,
- ram_ss_ss_wide_miso => mm_miso,
-
- -- Streaming
- input_sosi_arr => in_sosi_arr,
-
- output_sosi_arr => out_sosi_arr,
- output_siso_arr => out_siso_arr
- );
+ generic map (
+ g_wb_factor => c_wb_factor,
+ g_dsp_data_w => c_dsp_data_w,
+ g_nof_ch_in => c_nof_ch_in,
+ g_nof_ch_sel => c_nof_ch_sel,
+ g_select_file_prefix => c_select_file_prefix
+ )
+ port map (
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+
+ -- Memory Mapped
+ ram_ss_ss_wide_mosi => mm_mosi,
+ ram_ss_ss_wide_miso => mm_miso,
+
+ -- Streaming
+ input_sosi_arr => in_sosi_arr,
+
+ output_sosi_arr => out_sosi_arr,
+ output_siso_arr => out_siso_arr
+ );
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
index 126bfc83b1..60a5f05dc7 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
@@ -61,14 +61,14 @@
-- |A0 B0 C0 D0 E0 F0 G0 H0 I0 J0 K0 L0 A16 B16 C16 D16 E16 F16 G16 H16 I16 J16 K16 L16|
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_reorder_col_wide_row_select is
generic(
@@ -130,7 +130,7 @@ begin
rst <= '1', '0' after c_clk_period * 7;
p_select_stimuli : process
- variable k : natural;
+ variable k : natural;
begin
for rep in 0 to g_nof_sync * g_nof_block_per_sync - 1 loop
k := g_nof_ch_sel_col * (rep / g_nof_block_per_sync) * g_ch_sel_step;
@@ -151,17 +151,17 @@ begin
end process;
u_pipe_in_select : entity common_lib.common_pipeline
- generic map(
- g_pipeline => c_in_select_dly,
- g_in_dat_w => c_in_select_w,
- g_out_dat_w => c_in_select_w
- )
- port map(
- rst => rst,
- clk => clk,
- in_dat => reorder_row_in_select,
- out_dat => in_select
- );
+ generic map(
+ g_pipeline => c_in_select_dly,
+ g_in_dat_w => c_in_select_w,
+ g_out_dat_w => c_in_select_w
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ in_dat => reorder_row_in_select,
+ out_dat => in_select
+ );
------------------------------------------------------------------------------
-- Data blocks
------------------------------------------------------------------------------
@@ -210,16 +210,16 @@ begin
-- Verification
------------------------------------------------------------------------------
u_pipeline_arr : entity dp_lib.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_outputs
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_nof_streams => g_nof_outputs
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- snk_in_arr => out_sosi_arr,
- src_out_arr => dly_out_sosi_arr
- );
+ snk_in_arr => out_sosi_arr,
+ src_out_arr => dly_out_sosi_arr
+ );
gen_verify : for O in 0 to g_nof_outputs - 1 generate
p_generate_exp_data : process
@@ -275,43 +275,43 @@ begin
end generate;
u_dut_col : entity work.reorder_col_wide_select
- generic map (
- g_nof_inputs => g_nof_inputs,
- g_dsp_data_w => g_dsp_data_w,
- g_nof_ch_in => g_nof_ch_in,
- g_nof_ch_sel => c_nof_ch_sel,
- g_use_complex => c_use_complex
- )
- port map (
- dp_rst => rst,
- dp_clk => clk,
+ generic map (
+ g_nof_inputs => g_nof_inputs,
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_ch_in => g_nof_ch_in,
+ g_nof_ch_sel => c_nof_ch_sel,
+ g_use_complex => c_use_complex
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => clk,
- -- Memory Mapped
- col_select_mosi => mm_mosi,
- col_select_miso => mm_miso,
+ -- Memory Mapped
+ col_select_mosi => mm_mosi,
+ col_select_miso => mm_miso,
- -- Streaming
- input_sosi_arr => in_sosi_arr,
- output_sosi_arr => col_wide_select_sosi_arr
- );
+ -- Streaming
+ input_sosi_arr => in_sosi_arr,
+ output_sosi_arr => col_wide_select_sosi_arr
+ );
u_dut_row : entity work.reorder_row_select
- generic map (
- g_dsp_data_w => g_dsp_data_w,
- g_nof_inputs => g_nof_inputs,
- g_nof_outputs => g_nof_outputs,
- g_pipeline_in => g_reorder_row_select_pipe_in,
- g_pipeline_in_m => g_reorder_row_select_pipe_in_m,
- g_pipeline_out => g_reorder_row_select_pipe_out
- )
- port map (
- dp_rst => rst,
- dp_clk => clk,
+ generic map (
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_inputs => g_nof_inputs,
+ g_nof_outputs => g_nof_outputs,
+ g_pipeline_in => g_reorder_row_select_pipe_in,
+ g_pipeline_in_m => g_reorder_row_select_pipe_in_m,
+ g_pipeline_out => g_reorder_row_select_pipe_out
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => clk,
- in_select => in_select,
+ in_select => in_select,
- -- Streaming
- input_sosi_arr => col_wide_select_sosi_arr,
- output_sosi_arr => out_sosi_arr
- );
+ -- Streaming
+ input_sosi_arr => col_wide_select_sosi_arr,
+ output_sosi_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
index 62d32e038f..c78a9e34fc 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
@@ -31,37 +31,37 @@
-- > Evalute u_dr_mem_ctrl/u_io_driver/ctlr_mosi in the WAVE window for wr and rd activity.
library IEEE, common_lib, mm_lib, diag_lib, dp_lib, io_ddr_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.reorder_pkg.all;
-
---
--- CONSTANT c_wr_chunksize : NATURAL := 176; --240 for 6-bit or 176 for 8-bit; --g_bf.nof_weights;
--- CONSTANT c_rd_chunksize : NATURAL := 16; --32;
--- CONSTANT c_rd_nof_chunks : NATURAL := 11; --15 for 6-bit or 11 for 8-bit
--- CONSTANT c_rd_interval : NATURAL := c_rd_chunksize;
--- CONSTANT c_gapsize : NATURAL := 0;
--- CONSTANT c_nof_blocks : NATURAL := sel_a_b(g_sim, 16, 800000); --800000 781250);
--- CONSTANT c_bsn_sync_time_out : NATURAL := (c_nof_blocks * g_bf.nof_weights * 10)/8;
---
--- CONSTANT c_reorder_seq_conf : t_reorder_seq := (c_wr_chunksize,
--- c_rd_chunksize,
--- c_rd_nof_chunks,
--- c_rd_interval,
--- c_gapsize,
--- c_nof_blocks);
---
---
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.reorder_pkg.all;
+
+ --
+ -- CONSTANT c_wr_chunksize : NATURAL := 176; --240 for 6-bit or 176 for 8-bit; --g_bf.nof_weights;
+ -- CONSTANT c_rd_chunksize : NATURAL := 16; --32;
+ -- CONSTANT c_rd_nof_chunks : NATURAL := 11; --15 for 6-bit or 11 for 8-bit
+ -- CONSTANT c_rd_interval : NATURAL := c_rd_chunksize;
+ -- CONSTANT c_gapsize : NATURAL := 0;
+ -- CONSTANT c_nof_blocks : NATURAL := sel_a_b(g_sim, 16, 800000); --800000 781250);
+ -- CONSTANT c_bsn_sync_time_out : NATURAL := (c_nof_blocks * g_bf.nof_weights * 10)/8;
+ --
+ -- CONSTANT c_reorder_seq_conf : t_reorder_seq := (c_wr_chunksize,
+ -- c_rd_chunksize,
+ -- c_rd_nof_chunks,
+ -- c_rd_interval,
+ -- c_gapsize,
+ -- c_nof_blocks);
+ --
+ --
entity tb_reorder_transpose is
generic (
@@ -77,7 +77,7 @@ entity tb_reorder_transpose is
g_frame_size_in : natural := 256;
g_frame_size_out : natural := 176;
g_ena_pre_transp : boolean := true
- );
+ );
end tb_reorder_transpose;
architecture tb of tb_reorder_transpose is
@@ -131,12 +131,13 @@ architecture tb of tb_reorder_transpose is
signal reg_io_ddr_miso : t_mem_miso := c_mem_miso_rst;
-- Compose the Constants for the DUT
- constant c_reorder_seq_conf : t_reorder_seq := (g_wr_chunksize,
- g_rd_chunksize,
- g_rd_nof_chunks,
- g_rd_interval,
- g_gapsize,
- g_nof_blocks);
+ constant c_reorder_seq_conf : t_reorder_seq := (
+ g_wr_chunksize,
+ g_rd_chunksize,
+ g_rd_nof_chunks,
+ g_rd_interval,
+ g_gapsize,
+ g_nof_blocks);
constant c_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
@@ -209,7 +210,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -219,60 +220,69 @@ begin
-- MM buses
----------------------------------------------------------------------------
-- TB
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_ram_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+ u_mm_file_ram_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
- u_mm_file_reg_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+ u_mm_file_reg_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
- u_mm_file_ram_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+ u_mm_file_ram_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
- u_mm_file_reg_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+ u_mm_file_reg_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
- u_mm_file_ram_ss_ss_transp : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_SS_SS_WIDE")
- port map(mm_rst, mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
+ u_mm_file_ram_ss_ss_transp : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_SS_SS_WIDE")
+ port map(mm_rst, mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
- u_mm_file_reg_dp_sync_checker : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DP_SYNC_CHECKER")
- port map(mm_rst, mm_clk, reg_dp_sync_checker_mosi, reg_dp_sync_checker_miso);
+ u_mm_file_reg_dp_sync_checker : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DP_SYNC_CHECKER")
+ port map(mm_rst, mm_clk, reg_dp_sync_checker_mosi, reg_dp_sync_checker_miso);
- u_mm_file_reg_io_ddr : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_IO_DDR")
- port map(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+ u_mm_file_reg_io_ddr : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_IO_DDR")
+ port map(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => c_bg_nof_output_streams,
- g_buf_dat_w => c_bg_buf_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w,
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
gen_chang_in_imaginary_part : process(bg_sosi_arr)
begin
@@ -286,172 +296,172 @@ begin
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut: entity work.reorder_transpose
- generic map(
- g_nof_streams => c_bg_nof_output_streams,
- g_in_dat_w => c_bg_buf_dat_w / c_nof_complex,
- g_frame_size_in => g_frame_size_in,
- g_frame_size_out => g_frame_size_out,
- g_use_complex => c_use_complex,
- g_mem_dat_w => g_mem_dat_w,
- g_ena_pre_transp => g_ena_pre_transp,
- g_reorder_seq => c_reorder_seq_conf
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- ST sink
- snk_out_arr => bg_siso_arr,
- snk_in_arr => dut_in_arr,
-
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr,
-
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- reg_dp_sync_checker_mosi => reg_dp_sync_checker_mosi,
- reg_dp_sync_checker_miso => reg_dp_sync_checker_miso,
-
- -- Control interface to the external memory
- dvr_miso => ctlr_dvr_miso,
- dvr_mosi => ctlr_dvr_mosi,
-
- -- Data interface to the external memory
- to_mem_src_out => to_mem_sosi,
- to_mem_src_in => to_mem_siso,
-
- from_mem_snk_in => from_mem_sosi,
- from_mem_snk_out => from_mem_siso
-
- );
+ generic map(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_in_dat_w => c_bg_buf_dat_w / c_nof_complex,
+ g_frame_size_in => g_frame_size_in,
+ g_frame_size_out => g_frame_size_out,
+ g_use_complex => c_use_complex,
+ g_mem_dat_w => g_mem_dat_w,
+ g_ena_pre_transp => g_ena_pre_transp,
+ g_reorder_seq => c_reorder_seq_conf
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- ST sink
+ snk_out_arr => bg_siso_arr,
+ snk_in_arr => dut_in_arr,
+
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr,
+
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ reg_dp_sync_checker_mosi => reg_dp_sync_checker_mosi,
+ reg_dp_sync_checker_miso => reg_dp_sync_checker_miso,
+
+ -- Control interface to the external memory
+ dvr_miso => ctlr_dvr_miso,
+ dvr_mosi => ctlr_dvr_mosi,
+
+ -- Data interface to the external memory
+ to_mem_src_out => to_mem_sosi,
+ to_mem_src_in => to_mem_siso,
+
+ from_mem_snk_in => from_mem_sosi,
+ from_mem_snk_out => from_mem_siso
+
+ );
u_ddr_mem_ctrl : entity io_ddr_lib.io_ddr
- generic map(
- g_tech_ddr => c_tech_ddr, -- : t_c_tech_ddr;
- g_cross_domain_dvr_ctlr => false, -- TRUE, -- : BOOLEAN := TRUE;
- g_wr_data_w => c_data_w, -- : NATURAL := 32;
- g_wr_fifo_depth => c_wr_fifo_depth, -- : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
- g_rd_fifo_depth => c_rd_fifo_depth, -- : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
- g_rd_data_w => c_data_w, -- : NATURAL := 32;
- g_wr_flush_mode => "SYN", -- : STRING := "VAL"; -- "VAL", "SOP", "SYN"
- g_wr_flush_use_channel => false, -- : BOOLEAN := FALSE;
- g_wr_flush_start_channel => 0, -- : NATURAL := 0;
- g_wr_flush_nof_channels => 1 -- : POSITIVE := 1
- )
- port map (
- -- DDR reference clock
- ctlr_ref_clk => dp_clk_in,
- ctlr_ref_rst => dp_rst_in,
-
- -- DDR controller clock domain
- ctlr_clk_out => dp_clk, -- output clock of the ddr controller is used as DP clk.
- ctlr_rst_out => dp_rst,
-
- ctlr_clk_in => dp_clk,
- ctlr_rst_in => dp_rst,
-
- -- MM clock + reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Driver clock domain
- dvr_clk => dp_clk,
- dvr_rst => dp_rst,
-
- dvr_miso => ctlr_dvr_miso,
- dvr_mosi => ctlr_dvr_mosi,
-
- -- Write FIFO clock domain
- wr_clk => dp_clk,
- wr_rst => dp_rst,
-
- wr_fifo_usedw => OPEN,
- wr_sosi => to_mem_sosi,
- wr_siso => to_mem_siso,
-
- -- Read FIFO clock domain
- rd_clk => dp_clk,
- rd_rst => dp_rst,
-
- rd_fifo_usedw => OPEN,
- rd_sosi => from_mem_sosi,
- rd_siso => from_mem_siso,
-
- -- DDR3 PHY external interface
- phy3_in => phy_in,
- phy3_io => phy_io,
- phy3_ou => phy_ou
- );
+ generic map(
+ g_tech_ddr => c_tech_ddr, -- : t_c_tech_ddr;
+ g_cross_domain_dvr_ctlr => false, -- TRUE, -- : BOOLEAN := TRUE;
+ g_wr_data_w => c_data_w, -- : NATURAL := 32;
+ g_wr_fifo_depth => c_wr_fifo_depth, -- : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
+ g_rd_fifo_depth => c_rd_fifo_depth, -- : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
+ g_rd_data_w => c_data_w, -- : NATURAL := 32;
+ g_wr_flush_mode => "SYN", -- : STRING := "VAL"; -- "VAL", "SOP", "SYN"
+ g_wr_flush_use_channel => false, -- : BOOLEAN := FALSE;
+ g_wr_flush_start_channel => 0, -- : NATURAL := 0;
+ g_wr_flush_nof_channels => 1 -- : POSITIVE := 1
+ )
+ port map (
+ -- DDR reference clock
+ ctlr_ref_clk => dp_clk_in,
+ ctlr_ref_rst => dp_rst_in,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => dp_clk, -- output clock of the ddr controller is used as DP clk.
+ ctlr_rst_out => dp_rst,
+
+ ctlr_clk_in => dp_clk,
+ ctlr_rst_in => dp_rst,
+
+ -- MM clock + reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Driver clock domain
+ dvr_clk => dp_clk,
+ dvr_rst => dp_rst,
+
+ dvr_miso => ctlr_dvr_miso,
+ dvr_mosi => ctlr_dvr_mosi,
+
+ -- Write FIFO clock domain
+ wr_clk => dp_clk,
+ wr_rst => dp_rst,
+
+ wr_fifo_usedw => OPEN,
+ wr_sosi => to_mem_sosi,
+ wr_siso => to_mem_siso,
+
+ -- Read FIFO clock domain
+ rd_clk => dp_clk,
+ rd_rst => dp_rst,
+
+ rd_fifo_usedw => OPEN,
+ rd_sosi => from_mem_sosi,
+ rd_siso => from_mem_siso,
+
+ -- DDR3 PHY external interface
+ phy3_in => phy_in,
+ phy3_io => phy_io,
+ phy3_ou => phy_ou
+ );
u_tech_ddr_memory_model : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_tech_ddr
- )
- port map (
- mem3_in => phy_ou,
- mem3_io => phy_io
- );
+ generic map (
+ g_tech_ddr => c_tech_ddr
+ )
+ port map (
+ mem3_in => phy_ou,
+ mem3_io => phy_io
+ );
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_re,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
- ram_data_buf_miso => ram_diag_data_buf_re_miso,
- reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
- reg_data_buf_miso => reg_diag_data_buf_re_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_im,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
- ram_data_buf_miso => ram_diag_data_buf_im_miso,
- reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
- reg_data_buf_miso => reg_diag_data_buf_im_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_im,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd
index 5e1b814ea4..256393b855 100644
--- a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_reorder_col is
end tb_tb_reorder_col;
diff --git a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
index 279f2bdb4b..9397bbcb26 100644
--- a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
@@ -28,7 +28,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_reorder_col_select_all is
end tb_tb_reorder_col_select_all;
@@ -36,15 +36,15 @@ end tb_tb_reorder_col_select_all;
architecture tb of tb_tb_reorder_col_select_all is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- g_dsp_data_w : natural := 16; -- complex data width, = c_data_w / 2
--- g_nof_sync : natural := 2;
--- g_nof_packets_per_sync : natural := 3;
--- g_nof_blocks_per_packet : natural := 5;
--- g_nof_data_per_block : natural := 3;
--- g_inter_valid_gap : natural := 5; -- nof clk gap in in_sosi.valid
--- g_inter_packet_gap : natural := 0; -- nof clk gap between in_sosi.eop and next in_sosi.sop
--- g_use_complex : boolean := false;
--- g_use_dynamic_selection : boolean := true
+ -- g_dsp_data_w : natural := 16; -- complex data width, = c_data_w / 2
+ -- g_nof_sync : natural := 2;
+ -- g_nof_packets_per_sync : natural := 3;
+ -- g_nof_blocks_per_packet : natural := 5;
+ -- g_nof_data_per_block : natural := 3;
+ -- g_inter_valid_gap : natural := 5; -- nof clk gap in in_sosi.valid
+ -- g_inter_packet_gap : natural := 0; -- nof clk gap between in_sosi.eop and next in_sosi.sop
+ -- g_use_complex : boolean := false;
+ -- g_use_dynamic_selection : boolean := true
u_complex_5_3_no_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 2, 5, 3, 0, 0, true, false);
u_data_5_3_no_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 3, 5, 3, 0, 0, false, false);
diff --git a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
index 1306c592df..fb686a48cc 100644
--- a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
@@ -28,7 +28,7 @@
-- Description: See tb_reorder_col_wide_row_select
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_reorder_col_wide_row_select is
end tb_tb_reorder_col_wide_row_select;
diff --git a/libraries/base/ring/src/vhdl/ring_info.vhd b/libraries/base/ring/src/vhdl/ring_info.vhd
index f30cde027d..eacd04f226 100644
--- a/libraries/base/ring/src/vhdl/ring_info.vhd
+++ b/libraries/base/ring/src/vhdl/ring_info.vhd
@@ -31,11 +31,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.ring_pkg.all;
entity ring_info is
port (
@@ -57,24 +57,24 @@ architecture str of ring_info is
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_ring_info_field_arr) - 1 downto 0);
begin
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
- g_field_arr => c_ring_info_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ g_field_arr => c_ring_info_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_copi,
- mm_miso => reg_cipo,
+ mm_mosi => reg_copi,
+ mm_miso => reg_cipo,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_in_val => '1',
+ slv_in_val => '1',
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
-- get "RW" fields from mm_fields
ring_info.O_rn <= mm_fields_out(field_hi(c_ring_info_field_arr, "O_rn") downto field_lo(c_ring_info_field_arr, "O_rn"));
diff --git a/libraries/base/ring/src/vhdl/ring_lane.vhd b/libraries/base/ring/src/vhdl/ring_lane.vhd
index aae48c720d..da8ea22a4b 100644
--- a/libraries/base/ring/src/vhdl/ring_lane.vhd
+++ b/libraries/base/ring/src/vhdl/ring_lane.vhd
@@ -28,12 +28,12 @@
-- Remark:
library IEEE, common_lib, mm_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.ring_pkg.all;
entity ring_lane is
generic (
@@ -90,84 +90,84 @@ architecture str of ring_lane is
signal lane_info : t_ring_lane_info;
begin
u_ring_lane_info : entity work.ring_lane_info
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_ring_lane_info_copi,
- reg_miso => reg_ring_lane_info_cipo,
+ reg_mosi => reg_ring_lane_info_copi,
+ reg_miso => reg_ring_lane_info_cipo,
- lane_direction => c_lane_direction,
- lane_info => lane_info
- );
+ lane_direction => c_lane_direction,
+ lane_info => lane_info
+ );
u_ring_rx : entity work.ring_rx
- generic map (
- g_use_dp_layer => g_use_dp_layer,
- g_lane_direction => g_lane_direction,
- g_total_nof_packets_w => g_lane_total_nof_packets_w,
- g_data_w => g_lane_data_w,
- g_nof_rx_monitors => g_nof_rx_monitors,
- g_err_bi => g_err_bi,
- g_block_size => g_lane_packet_length,
- g_nof_err_counts => g_nof_err_counts,
- g_check_channel => g_bsn_at_sync_check_channel,
- g_sync_timeout => g_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => from_lane_sosi,
- lane_rx_cable_sosi => lane_rx_cable_sosi,
- lane_rx_board_sosi => lane_rx_board_sosi,
- bs_sosi => bs_sosi,
-
- reg_bsn_monitor_v2_copi => reg_bsn_monitor_v2_ring_rx_copi,
- reg_bsn_monitor_v2_cipo => reg_bsn_monitor_v2_ring_rx_cipo,
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo,
-
- ref_sync => bs_sosi.sync,
- rx_select => rx_select,
- this_rn => this_rn,
- N_rn => N_rn
- );
+ generic map (
+ g_use_dp_layer => g_use_dp_layer,
+ g_lane_direction => g_lane_direction,
+ g_total_nof_packets_w => g_lane_total_nof_packets_w,
+ g_data_w => g_lane_data_w,
+ g_nof_rx_monitors => g_nof_rx_monitors,
+ g_err_bi => g_err_bi,
+ g_block_size => g_lane_packet_length,
+ g_nof_err_counts => g_nof_err_counts,
+ g_check_channel => g_bsn_at_sync_check_channel,
+ g_sync_timeout => g_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => from_lane_sosi,
+ lane_rx_cable_sosi => lane_rx_cable_sosi,
+ lane_rx_board_sosi => lane_rx_board_sosi,
+ bs_sosi => bs_sosi,
+
+ reg_bsn_monitor_v2_copi => reg_bsn_monitor_v2_ring_rx_copi,
+ reg_bsn_monitor_v2_cipo => reg_bsn_monitor_v2_ring_rx_cipo,
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo,
+
+ ref_sync => bs_sosi.sync,
+ rx_select => rx_select,
+ this_rn => this_rn,
+ N_rn => N_rn
+ );
u_ring_tx : entity work.ring_tx
- generic map (
- g_use_dp_layer => g_use_dp_layer,
- g_lane_direction => g_lane_direction,
- g_data_w => g_lane_data_w,
- g_nof_tx_monitors => g_nof_tx_monitors,
- g_validate_channel => g_validate_channel,
- g_mode => g_validate_channel_mode,
- g_sync_timeout => g_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- to_lane_sosi => to_lane_sosi,
- lane_tx_cable_sosi => lane_tx_cable_sosi,
- lane_tx_board_sosi => lane_tx_board_sosi,
-
- reg_bsn_monitor_v2_copi => reg_bsn_monitor_v2_ring_tx_copi,
- reg_bsn_monitor_v2_cipo => reg_bsn_monitor_v2_ring_tx_cipo,
-
- ref_sync => bs_sosi.sync,
- tx_select => tx_select,
- remove_channel => lane_info.transport_nof_hops,
- this_rn => this_rn,
- N_rn => N_rn
- );
+ generic map (
+ g_use_dp_layer => g_use_dp_layer,
+ g_lane_direction => g_lane_direction,
+ g_data_w => g_lane_data_w,
+ g_nof_tx_monitors => g_nof_tx_monitors,
+ g_validate_channel => g_validate_channel,
+ g_mode => g_validate_channel_mode,
+ g_sync_timeout => g_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ to_lane_sosi => to_lane_sosi,
+ lane_tx_cable_sosi => lane_tx_cable_sosi,
+ lane_tx_board_sosi => lane_tx_board_sosi,
+
+ reg_bsn_monitor_v2_copi => reg_bsn_monitor_v2_ring_tx_copi,
+ reg_bsn_monitor_v2_cipo => reg_bsn_monitor_v2_ring_tx_cipo,
+
+ ref_sync => bs_sosi.sync,
+ tx_select => tx_select,
+ remove_channel => lane_info.transport_nof_hops,
+ this_rn => this_rn,
+ N_rn => N_rn
+ );
end str;
diff --git a/libraries/base/ring/src/vhdl/ring_lane_info.vhd b/libraries/base/ring/src/vhdl/ring_lane_info.vhd
index 83c2cf4ca3..823ff4ba45 100644
--- a/libraries/base/ring/src/vhdl/ring_lane_info.vhd
+++ b/libraries/base/ring/src/vhdl/ring_lane_info.vhd
@@ -31,11 +31,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.ring_pkg.all;
entity ring_lane_info is
port (
@@ -61,20 +61,20 @@ architecture str of ring_lane_info is
signal lane_info_ro: t_ring_lane_info; -- ro = read only
begin
u_mm_fields: entity work.ring_lane_info_reg
- port map (
+ port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
- lane_info_ro => lane_info_ro,
- lane_info => lane_info
- );
+ lane_info_ro => lane_info_ro,
+ lane_info => lane_info
+ );
lane_info_ro.lane_direction <= lane_direction;
end str;
diff --git a/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd b/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd
index d2a145621a..c1943f6f36 100644
--- a/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd
+++ b/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd
@@ -31,11 +31,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.ring_pkg.all;
entity ring_lane_info_reg is
port (
@@ -74,25 +74,25 @@ begin
end process;
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
- g_field_arr => c_ring_lane_info_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ g_field_arr => c_ring_lane_info_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi,
- mm_miso => reg_miso,
+ mm_mosi => reg_mosi,
+ mm_miso => reg_miso,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_in => mm_fields_in,
- slv_in_val => '1',
+ slv_in => mm_fields_in,
+ slv_in_val => '1',
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
-- add "RO" fields to mm_fields
mm_fields_in(field_hi(c_ring_lane_info_field_arr, "lane_direction") downto field_lo(c_ring_lane_info_field_arr, "lane_direction")) <= slv(lane_info_rd.lane_direction);
diff --git a/libraries/base/ring/src/vhdl/ring_mux.vhd b/libraries/base/ring/src/vhdl/ring_mux.vhd
index da34e38528..d036aa3d78 100644
--- a/libraries/base/ring/src/vhdl/ring_mux.vhd
+++ b/libraries/base/ring/src/vhdl/ring_mux.vhd
@@ -29,11 +29,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity ring_mux is
generic (
@@ -79,31 +79,31 @@ begin
remote_siso <= dp_mux_in_siso_arr(1);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_nof_input => c_nof_input,
- g_append_channel_lo => false, -- Keep channels the same as the input.
- g_use_fifo => true,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_empty_w => g_empty_w,
- g_in_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_in_channel => true,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_size => g_fifo_size
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_nof_input => c_nof_input,
+ g_append_channel_lo => false, -- Keep channels the same as the input.
+ g_use_fifo => true,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_empty_w => g_empty_w,
+ g_in_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_in_channel => true,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_size => g_fifo_size
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- snk_out_arr => dp_mux_in_siso_arr,
- snk_in_arr => dp_mux_in_sosi_arr,
+ snk_out_arr => dp_mux_in_siso_arr,
+ snk_in_arr => dp_mux_in_sosi_arr,
- src_in => mux_siso,
- src_out => mux_sosi
- );
+ src_in => mux_siso,
+ src_out => mux_sosi
+ );
end str;
diff --git a/libraries/base/ring/src/vhdl/ring_pkg.vhd b/libraries/base/ring/src/vhdl/ring_pkg.vhd
index 58bb4193dd..11f394de1f 100644
--- a/libraries/base/ring/src/vhdl/ring_pkg.vhd
+++ b/libraries/base/ring/src/vhdl/ring_pkg.vhd
@@ -27,27 +27,28 @@
-- Remark:
-------------------------------------------------------------------------------
library ieee, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
package ring_pkg is
--- lane info, see https://support.astron.nl/confluence/x/jyu7Ag
+ -- lane info, see https://support.astron.nl/confluence/x/jyu7Ag
type t_ring_lane_info is record
transport_nof_hops : std_logic_vector(c_word_w - 1 downto 0);
lane_direction : std_logic;
end record;
constant c_ring_lane_info_rst : t_ring_lane_info :=
- ( (others => '0'), '0' );
+ ( (others => '0'), '0' );
- constant c_ring_lane_info_field_arr : t_common_field_arr(1 downto 0) :=
- ( (field_name_pad("transport_nof_hops"), "RW", 32, field_default(0)),
- (field_name_pad("lane_direction"), "RO", 1, field_default(0)) );
+ constant c_ring_lane_info_field_arr : t_common_field_arr(
+ 1 downto 0) :=
+ ( (field_name_pad("transport_nof_hops"), "RW", 32, field_default(0)),
+ (field_name_pad("lane_direction"), "RO", 1, field_default(0)) );
--- ring info, see https://support.astron.nl/confluence/x/jyu7Ag
+ -- ring info, see https://support.astron.nl/confluence/x/jyu7Ag
type t_ring_info is record
O_rn : std_logic_vector(c_byte_w - 1 downto 0);
N_rn : std_logic_vector(c_byte_w - 1 downto 0);
@@ -56,13 +57,14 @@ package ring_pkg is
end record;
constant c_ring_info_rst : t_ring_info :=
- ( (others => '0'), (others => '0'), '0', '0' );
+ ( (others => '0'), (others => '0'), '0', '0' );
- constant c_ring_info_field_arr : t_common_field_arr(3 downto 0) :=
- ( (field_name_pad("O_rn"), "RW", 8, field_default( 0)),
- (field_name_pad("N_rn"), "RW", 8, field_default(16)),
- (field_name_pad("use_cable_to_next_rn"), "RW", 1, field_default( 0)),
- (field_name_pad("use_cable_to_previous_rn"), "RW", 1, field_default( 0)) );
+ constant c_ring_info_field_arr : t_common_field_arr(
+ 3 downto 0) :=
+ ( (field_name_pad("O_rn"), "RW", 8, field_default( 0)),
+ (field_name_pad("N_rn"), "RW", 8, field_default(16)),
+ (field_name_pad("use_cable_to_next_rn"), "RW", 1, field_default( 0)),
+ (field_name_pad("use_cable_to_previous_rn"), "RW", 1, field_default( 0)) );
constant c_ring_eth_dst_mac : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := x"FFFFFFFFFFFF";
constant c_ring_eth_src_mac : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := x"002286080000";
@@ -73,29 +75,31 @@ package ring_pkg is
constant c_ring_eth_nof_hdr_fields : natural := 3;
constant c_ring_eth_hdr_field_sel : std_logic_vector(c_ring_eth_nof_hdr_fields - 1 downto 0) := "000";
- constant c_ring_eth_hdr_field_arr : t_common_field_arr(c_ring_eth_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(c_ring_eth_dst_mac) ),
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(c_ring_eth_src_mac) ),
- ( field_name_pad("eth_type" ), "RW", 16, field_default(0) )
- );
+ constant c_ring_eth_hdr_field_arr : t_common_field_arr(
+ c_ring_eth_nof_hdr_fields - 1 downto 0) := (
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(c_ring_eth_dst_mac) ),
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(c_ring_eth_src_mac) ),
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(0) )
+ );
constant c_ring_eth_hdr_field_size : natural := ceil_div(field_slv_len(c_ring_eth_hdr_field_arr), c_longword_w); -- = 14/8 = 2 longwords
constant c_ring_dp_nof_hdr_fields : natural := 6;
constant c_ring_dp_hdr_field_sel : std_logic_vector(c_ring_dp_nof_hdr_fields - 1 downto 0) := "000" & "000";
- constant c_ring_dp_hdr_field_arr : t_common_field_arr(c_ring_dp_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(c_ring_eth_dst_mac) ),
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(c_ring_eth_src_mac) ),
- ( field_name_pad("eth_type" ), "RW", 16, field_default(0) ),
- ( field_name_pad("dp_channel" ), "RW", 16, field_default(0) ),
- ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
- ( field_name_pad("dp_bsn" ), "RW", 63, field_default(0) )
- );
+ constant c_ring_dp_hdr_field_arr : t_common_field_arr(
+ c_ring_dp_nof_hdr_fields - 1 downto 0) := (
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(c_ring_eth_dst_mac) ),
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(c_ring_eth_src_mac) ),
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("dp_channel" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("dp_bsn" ), "RW", 63, field_default(0) )
+ );
constant c_ring_dp_hdr_field_size : natural := ceil_div(field_slv_len(c_ring_dp_hdr_field_arr), c_longword_w); -- = 24/8 = 3 longwords
function func_ring_nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : natural) return natural;
function func_ring_nof_hops_to_source_rn(hops, this_rn, N_rn : std_logic_vector; lane_dir : natural) return std_logic_vector; -- return vector length is same as hops vector length
- end package ring_pkg;
+ end package ring_pkg;
package body ring_pkg is
function func_ring_nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : natural) return natural is
@@ -126,4 +130,4 @@ package body ring_pkg is
return TO_UVEC(func_ring_nof_hops_to_source_rn(TO_UINT(hops), TO_UINT(this_rn), TO_UINT(N_rn), lane_dir),hops'length);
end;
-end ring_pkg;
+ end ring_pkg;
diff --git a/libraries/base/ring/src/vhdl/ring_rx.vhd b/libraries/base/ring/src/vhdl/ring_rx.vhd
index 42c1b8d206..61e62cbac0 100644
--- a/libraries/base/ring/src/vhdl/ring_rx.vhd
+++ b/libraries/base/ring/src/vhdl/ring_rx.vhd
@@ -28,12 +28,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.ring_pkg.all;
entity ring_rx is
generic (
@@ -99,17 +99,17 @@ begin
-- Validate length
u_dp_block_validate_length : entity dp_lib.dp_block_validate_length
- generic map (
- g_err_bi => g_err_bi,
- g_expected_length => c_packet_size
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => lane_rx_sosi,
- src_out => packet_sosi
- );
+ generic map (
+ g_err_bi => g_err_bi,
+ g_expected_length => c_packet_size
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => lane_rx_sosi,
+ src_out => packet_sosi
+ );
-- Validate error field
-- . Use ref_sync as capture moment for the running MM total counts in dp_block_validate_err.
@@ -117,52 +117,52 @@ begin
-- and because the rx_packet_sosi can carry packets from multiple sources (so multiple sync
-- intervals multiplexed on one lane).
u_dp_block_validate_err : entity dp_lib.dp_block_validate_err
- generic map (
- g_cnt_w => c_word_w, -- <= c_word_w = 32
- g_blk_cnt_w => g_total_nof_packets_w, -- <= c_longword_w = 64
- g_max_block_size => c_packet_size,
- g_min_block_size => c_packet_size,
- g_nof_err_counts => g_nof_err_counts,
- g_fifo_size => c_packet_size, -- can be same as g_max_block_size as src_in.ready = '1'
- g_use_sync => false, -- no need to pass on ref_sync
- g_data_w => g_data_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ref_sync => ref_sync,
-
- snk_in => packet_sosi,
- src_out => validated_sosi,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_dp_block_validate_err_copi,
- reg_miso => reg_dp_block_validate_err_cipo
- );
+ generic map (
+ g_cnt_w => c_word_w, -- <= c_word_w = 32
+ g_blk_cnt_w => g_total_nof_packets_w, -- <= c_longword_w = 64
+ g_max_block_size => c_packet_size,
+ g_min_block_size => c_packet_size,
+ g_nof_err_counts => g_nof_err_counts,
+ g_fifo_size => c_packet_size, -- can be same as g_max_block_size as src_in.ready = '1'
+ g_use_sync => false, -- no need to pass on ref_sync
+ g_data_w => g_data_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ref_sync => ref_sync,
+
+ snk_in => packet_sosi,
+ src_out => validated_sosi,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_block_validate_err_copi,
+ reg_miso => reg_dp_block_validate_err_cipo
+ );
-- Removing ETH/DP header
u_dp_offload_rx: entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- snk_in_arr(0) => validated_sosi,
- src_out_arr(0) => offload_rx_sosi,
-
- hdr_fields_out_arr(0) => hdr_fields_out,
- hdr_fields_raw_arr(0) => hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_in_arr(0) => validated_sosi,
+ src_out_arr(0) => offload_rx_sosi,
+
+ hdr_fields_out_arr(0) => hdr_fields_out,
+ hdr_fields_raw_arr(0) => hdr_fields_raw
+ );
-- Use dp layer
gen_dp_layer : if g_use_dp_layer generate
@@ -176,23 +176,23 @@ begin
-- Validate bsn at sync
u_dp_block_validate_bsn_at_sync : entity dp_lib.dp_block_validate_bsn_at_sync
- generic map (
- g_check_channel => g_check_channel
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_check_channel => g_check_channel
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- in_sosi => decoded_sosi,
- bs_sosi => bs_sosi,
- out_sosi => from_lane_sosi,
+ in_sosi => decoded_sosi,
+ bs_sosi => bs_sosi,
+ out_sosi => from_lane_sosi,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_dp_block_validate_bsn_at_sync_copi,
- reg_miso => reg_dp_block_validate_bsn_at_sync_cipo
- );
+ reg_mosi => reg_dp_block_validate_bsn_at_sync_copi,
+ reg_miso => reg_dp_block_validate_bsn_at_sync_cipo
+ );
-- Convert nof_hops to source RN
p_hop_to_src_rn: process(dp_rst, dp_clk)
@@ -211,34 +211,34 @@ begin
end process;
u_dp_demux : entity dp_lib.dp_demux
- generic map (
- g_nof_output => g_nof_rx_monitors
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => piped_monitor_sosi,
- src_out_arr => demux_sosi_arr
- );
+ generic map (
+ g_nof_output => g_nof_rx_monitors
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => piped_monitor_sosi,
+ src_out_arr => demux_sosi_arr
+ );
monitor_sosi_arr <= func_dp_stream_arr_reverse_range(demux_sosi_arr); -- Fix reversed bus.
-- BSN Monitors
u_mms_dp_bsn_monitor_v2 : entity dp_lib.mms_dp_bsn_monitor_v2
- generic map (
- g_nof_streams => g_nof_rx_monitors,
- g_sync_timeout => g_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_v2_copi,
- reg_miso => reg_bsn_monitor_v2_cipo,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_sosi_arr => monitor_sosi_arr,
- ref_sync => ref_sync
- );
+ generic map (
+ g_nof_streams => g_nof_rx_monitors,
+ g_sync_timeout => g_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_copi,
+ reg_miso => reg_bsn_monitor_v2_cipo,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_sosi_arr => monitor_sosi_arr,
+ ref_sync => ref_sync
+ );
end generate;
-- Do not use dp layer
diff --git a/libraries/base/ring/src/vhdl/ring_tx.vhd b/libraries/base/ring/src/vhdl/ring_tx.vhd
index 059e6fb0a3..89c7d6b31e 100644
--- a/libraries/base/ring/src/vhdl/ring_tx.vhd
+++ b/libraries/base/ring/src/vhdl/ring_tx.vhd
@@ -29,12 +29,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.ring_pkg.all;
entity ring_tx is
generic (
@@ -95,18 +95,18 @@ begin
-- Validate transport_nof_hops
gen_validate : if g_validate_channel generate
u_dp_block_validate_channel: entity dp_lib.dp_block_validate_channel
- generic map (
- g_mode => g_mode
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_sosi => to_lane_sosi,
- out_keep_sosi => validated_sosi,
-
- remove_channel => remove_channel
- );
+ generic map (
+ g_mode => g_mode
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_sosi => to_lane_sosi,
+ out_keep_sosi => validated_sosi,
+
+ remove_channel => remove_channel
+ );
end generate;
-- Don't validate transport_nof_hops
@@ -141,44 +141,44 @@ begin
-- Fifo for inserting header
u_dp_fifo_sc: entity dp_lib.dp_fifo_sc
- generic map (
- g_data_w => g_data_w,
- g_empty_w => c_empty_w,
- g_use_empty => c_use_empty,
- g_fifo_size => c_fifo_size
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => tx_sosi,
-
- src_out => tx_fifo_sosi,
- src_in => tx_fifo_siso
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_empty_w => c_empty_w,
+ g_use_empty => c_use_empty,
+ g_fifo_size => c_fifo_size
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => tx_sosi,
+
+ src_out => tx_fifo_sosi,
+ src_in => tx_fifo_siso
+ );
-- Inserting ETH/DP header
u_dp_offload_tx_v3: entity dp_lib.dp_offload_tx_v3
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_sel
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- snk_in_arr(0) => tx_fifo_sosi,
- snk_out_arr(0) => tx_fifo_siso,
- src_out_arr(0) => lane_tx_sosi,
-
- hdr_fields_in_arr(0) => hdr_fields_in_reg
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_sel
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_in_arr(0) => tx_fifo_sosi,
+ snk_out_arr(0) => tx_fifo_siso,
+ src_out_arr(0) => lane_tx_sosi,
+
+ hdr_fields_in_arr(0) => hdr_fields_in_reg
+ );
-- Select output based on tx_select
p_sel_out : process(lane_tx_sosi, tx_select)
@@ -210,33 +210,33 @@ begin
end process;
u_dp_demux : entity dp_lib.dp_demux
- generic map (
- g_nof_output => g_nof_tx_monitors
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => piped_monitor_sosi,
- src_out_arr => demux_sosi_arr
- );
+ generic map (
+ g_nof_output => g_nof_tx_monitors
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => piped_monitor_sosi,
+ src_out_arr => demux_sosi_arr
+ );
monitor_sosi_arr <= func_dp_stream_arr_reverse_range(demux_sosi_arr); -- Fix reversed bus.
u_mms_dp_bsn_monitor_v2 : entity dp_lib.mms_dp_bsn_monitor_v2
- generic map (
- g_nof_streams => g_nof_tx_monitors,
- g_sync_timeout => g_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_v2_copi,
- reg_miso => reg_bsn_monitor_v2_cipo,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_sosi_arr => monitor_sosi_arr,
- ref_sync => ref_sync
- );
+ generic map (
+ g_nof_streams => g_nof_tx_monitors,
+ g_sync_timeout => g_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_copi,
+ reg_miso => reg_bsn_monitor_v2_cipo,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_sosi_arr => monitor_sosi_arr,
+ ref_sync => ref_sync
+ );
end generate;
end str;
diff --git a/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd b/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
index 7ce9647230..5d87cca6d4 100644
--- a/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
+++ b/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
@@ -31,12 +31,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.ring_pkg.all;
entity tb_ring_lane_info is
end tb_ring_lane_info;
diff --git a/libraries/base/sens/src/vhdl/sens.vhd b/libraries/base/sens/src/vhdl/sens.vhd
index b6dbc55dab..f9daf8b7f3 100644
--- a/libraries/base/sens/src/vhdl/sens.vhd
+++ b/libraries/base/sens/src/vhdl/sens.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use i2c_lib.i2c_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use i2c_lib.i2c_pkg.all;
entity sens is
generic (
@@ -54,7 +54,7 @@ architecture str of sens is
-- I2C clock rate settings
constant c_i2c_sens_clk_cnt : natural := 399; -- (200 MHz/ 5 / (399+1)) = 100 kbps
constant c_i2c_sens_comma_w : natural := 0; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
- -- 0 = no comma time
+ -- 0 = no comma time
constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, c_i2c_sens_clk_cnt); -- define I2C clock rate
constant c_sens_comma_w : natural := sel_a_b(g_sim, 0, c_i2c_sens_comma_w); -- define I2C comma time
@@ -68,39 +68,39 @@ architecture str of sens is
signal smbus_out_ack : std_logic;
begin
ctrl : entity work.sens_ctrl
- generic map (
- g_clk_cnt_w => c_update_clk_cnt_w,
- g_evt_dat_w => sens_data'LENGTH,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- evt_val_reg => sens_evt,
- evt_dat_reg => sens_data
- );
+ generic map (
+ g_clk_cnt_w => c_update_clk_cnt_w,
+ g_evt_dat_w => sens_data'LENGTH,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ evt_val_reg => sens_evt,
+ evt_dat_reg => sens_data
+ );
smbus : entity i2c_lib.i2c_smbus
- generic map (
- g_i2c_phy => c_sens_phy
- )
- port map (
- gs_sim => cs_sim,
- clk => clk,
- rst => rst,
- in_dat => smbus_in_dat,
- in_req => smbus_in_val,
- out_dat => smbus_out_dat,
- out_val => smbus_out_val,
- out_err => smbus_out_err,
- out_ack => smbus_out_ack,
- scl => scl,
- sda => sda
- );
-end architecture;
+ generic map (
+ g_i2c_phy => c_sens_phy
+ )
+ port map (
+ gs_sim => cs_sim,
+ clk => clk,
+ rst => rst,
+ in_dat => smbus_in_dat,
+ in_req => smbus_in_val,
+ out_dat => smbus_out_dat,
+ out_val => smbus_out_val,
+ out_err => smbus_out_err,
+ out_ack => smbus_out_ack,
+ scl => scl,
+ sda => sda
+ );
+ end architecture;
diff --git a/libraries/base/sens/src/vhdl/sens_ctrl.vhd b/libraries/base/sens/src/vhdl/sens_ctrl.vhd
index e3a0cc0b37..370c443474 100644
--- a/libraries/base/sens/src/vhdl/sens_ctrl.vhd
+++ b/libraries/base/sens/src/vhdl/sens_ctrl.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_max6652_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_max6652_pkg.all;
entity sens_ctrl is
generic (
@@ -63,11 +63,11 @@ architecture rtl of sens_ctrl is
SMBUS_READ_BYTE , ADR_MAX6652 , MAX6652_REG_READ_VCC,
SMBUS_READ_BYTE , ADR_MAX6652 , MAX6652_REG_READ_TEMP,
SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_REMOTE_TEMP,
--- For debugging, use AP temp fields in RSR to read other info from the sensor, e.g.:
--- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_STATUS,
--- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_CONFIG,
--- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_REMOTE_HIGH,
--- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_REMOTE_LOW,
+ -- For debugging, use AP temp fields in RSR to read other info from the sensor, e.g.:
+ -- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_STATUS,
+ -- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_CONFIG,
+ -- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_REMOTE_HIGH,
+ -- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_REMOTE_LOW,
SMBUS_READ_BYTE , ADR_MAX1617_AP0, MAX1617_CMD_READ_REMOTE_TEMP,
SMBUS_READ_BYTE , ADR_MAX1617_AP1, MAX1617_CMD_READ_REMOTE_TEMP,
SMBUS_READ_BYTE , ADR_MAX1617_AP2, MAX1617_CMD_READ_REMOTE_TEMP,
@@ -84,7 +84,7 @@ architecture rtl of sens_ctrl is
SMBUS_WRITE_BYTE, ADR_MAX1617_AP2, MAX1617_CMD_WRITE_REMOTE_HIGH, g_temp_high,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP3, MAX1617_CMD_WRITE_REMOTE_HIGH, g_temp_high,
SMBUS_C_NOP
- );
+ );
signal seq_start : std_logic; -- The I2C sequence to read out the sensors is started when clk_cnt = 0
signal nxt_seq_start : std_logic;
diff --git a/libraries/base/sens/tb/vhdl/tb_sens.vhd b/libraries/base/sens/tb/vhdl/tb_sens.vhd
index db6ed53a02..26c05a0c09 100644
--- a/libraries/base/sens/tb/vhdl/tb_sens.vhd
+++ b/libraries/base/sens/tb/vhdl/tb_sens.vhd
@@ -23,10 +23,10 @@ entity tb_sens is
end tb_sens;
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
architecture tb of tb_sens is
constant c_clk_period : time := 5 ns;
@@ -112,81 +112,81 @@ begin
-- I2C master
sens : entity work.sens
- generic map (
- --g_sim => 0 -- for real time I2C link debugging purposes
- g_sim => 1
- )
- port map(
- rst => rst,
- clk => clk,
- scl => scl,
- sda => sda,
- sens_evt => sens_evt,
- sens_data => sens_data
- );
+ generic map (
+ --g_sim => 0 -- for real time I2C link debugging purposes
+ g_sim => 1
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ scl => scl,
+ sda => sda,
+ sens_evt => sens_evt,
+ sens_data => sens_data
+ );
-- I2C slaves
sens_temp_bp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_bp_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_bp_temp
- );
+ generic map (
+ g_address => c_bp_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_bp_temp
+ );
sens_temp_ap0 : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_ap0_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_ap0_temp
- );
+ generic map (
+ g_address => c_ap0_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_ap0_temp
+ );
sens_temp_ap1 : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_ap1_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_ap1_temp
- );
+ generic map (
+ g_address => c_ap1_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_ap1_temp
+ );
sens_temp_ap2 : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_ap2_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_ap2_temp
- );
+ generic map (
+ g_address => c_ap2_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_ap2_temp
+ );
sens_temp_ap3 : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_ap3_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_ap3_temp
- );
+ generic map (
+ g_address => c_ap3_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_ap3_temp
+ );
sens_volt_bp : entity i2c_lib.dev_max6652
- generic map (
- g_address => c_bp_volt_address
- )
- port map (
- scl => scl,
- sda => sda,
- volt_2v5 => c_volt_1v2,
- volt_3v3 => c_volt_2v5,
- volt_12v => c_volt_nc,
- volt_vcc => c_volt_3v3,
- temp => c_temp_pcb
- );
+ generic map (
+ g_address => c_bp_volt_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ volt_2v5 => c_volt_1v2,
+ volt_3v3 => c_volt_2v5,
+ volt_12v => c_volt_nc,
+ volt_vcc => c_volt_3v3,
+ temp => c_temp_pcb
+ );
end tb;
diff --git a/libraries/base/ss/src/vhdl/ss.vhd b/libraries/base/ss/src/vhdl/ss.vhd
index e53037f69f..899e8477bb 100644
--- a/libraries/base/ss/src/vhdl/ss.vhd
+++ b/libraries/base/ss/src/vhdl/ss.vhd
@@ -51,12 +51,12 @@
-- support the input_siso signal, e.g. based on store_done and retrieve_done.
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity ss is
generic (
@@ -88,17 +88,19 @@ entity ss is
end ss;
architecture str of ss is
- constant c_store_buf : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_ch_in),
- dat_w => c_nof_complex * g_dsp_data_w,
- nof_dat => g_nof_ch_in,
- init_sl => '0'); -- ST side : stat_mosi
+ constant c_store_buf : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_ch_in),
+ dat_w => c_nof_complex * g_dsp_data_w,
+ nof_dat => g_nof_ch_in,
+ init_sl => '0'); -- ST side : stat_mosi
- constant c_select_buf : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_ch_sel),
- dat_w => ceil_log2(g_nof_ch_in),
- nof_dat => g_nof_ch_sel,
- init_sl => '0');
+ constant c_select_buf : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_ch_sel),
+ dat_w => ceil_log2(g_nof_ch_in),
+ nof_dat => g_nof_ch_sel,
+ init_sl => '0');
constant c_data_nof_pages : natural := 2; -- fixed dual page SS
constant c_info_nof_pages : natural := 2; -- fixed, fits the dual page block latency and logic latency of the SS
@@ -131,150 +133,150 @@ begin
-- (no bursting) by enforcing a minimum period of g_nof_ch_sel
-----------------------------------------------------------------------------
u_dp_throttle_sop : entity dp_lib.dp_throttle_sop
- generic map (
- g_period => g_nof_ch_sel
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_out => input_siso,
- snk_in => input_sosi
- );
+ generic map (
+ g_period => g_nof_ch_sel
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_out => input_siso,
+ snk_in => input_sosi
+ );
u_store : entity work.ss_store
- generic map (
- g_dsp_data_w => g_dsp_data_w,
- g_nof_ch_in => g_nof_ch_in,
- g_use_complex => g_use_complex
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_ch_in => g_nof_ch_in,
+ g_use_complex => g_use_complex
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- -- Streaming
- input_sosi => input_sosi,
+ -- Streaming
+ input_sosi => input_sosi,
- -- Timing
- store_done => store_done,
+ -- Timing
+ store_done => store_done,
- -- Write store buffer control
- store_mosi => store_mosi
- );
+ -- Write store buffer control
+ store_mosi => store_mosi
+ );
u_store_buf : entity common_lib.common_paged_ram_r_w
- generic map (
- g_technology => g_technology,
- g_str => "use_adr",
- g_data_w => c_store_buf.dat_w,
- g_nof_pages => c_data_nof_pages,
- g_page_sz => c_store_buf.nof_dat,
- g_wr_start_page => 0,
- g_rd_start_page => 0,
- g_rd_latency => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- wr_next_page => store_done,
- wr_adr => store_mosi.address(c_store_buf.adr_w - 1 downto 0),
- wr_en => store_mosi.wr,
- wr_dat => store_mosi.wrdata(c_store_buf.dat_w - 1 downto 0),
- rd_next_page => retrieve_done,
- rd_adr => retrieve_mosi.address(c_store_buf.adr_w - 1 downto 0),
- rd_en => retrieve_mosi.rd,
- rd_dat => retrieve_miso.rddata(c_store_buf.dat_w - 1 downto 0),
- rd_val => retrieve_miso.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_str => "use_adr",
+ g_data_w => c_store_buf.dat_w,
+ g_nof_pages => c_data_nof_pages,
+ g_page_sz => c_store_buf.nof_dat,
+ g_wr_start_page => 0,
+ g_rd_start_page => 0,
+ g_rd_latency => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ wr_next_page => store_done,
+ wr_adr => store_mosi.address(c_store_buf.adr_w - 1 downto 0),
+ wr_en => store_mosi.wr,
+ wr_dat => store_mosi.wrdata(c_store_buf.dat_w - 1 downto 0),
+ rd_next_page => retrieve_done,
+ rd_adr => retrieve_mosi.address(c_store_buf.adr_w - 1 downto 0),
+ rd_en => retrieve_mosi.rd,
+ rd_dat => retrieve_miso.rddata(c_store_buf.dat_w - 1 downto 0),
+ rd_val => retrieve_miso.rdval
+ );
u_select_buf : entity common_lib.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => c_select_buf,
- g_init_file => g_select_file_name
- )
- port map (
- -- MM side
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_ss_ss_mosi.wr,
- wr_dat_a => ram_ss_ss_mosi.wrdata(c_select_buf.dat_w - 1 downto 0),
- adr_a => ram_ss_ss_mosi.address(c_select_buf.adr_w - 1 downto 0),
- rd_en_a => ram_ss_ss_mosi.rd,
- rd_dat_a => ram_ss_ss_miso.rddata(c_select_buf.dat_w - 1 downto 0),
- rd_val_a => ram_ss_ss_miso.rdval,
- -- ST side
- rst_b => dp_rst,
- clk_b => dp_clk,
- wr_en_b => select_mosi.wr,
- wr_dat_b => select_mosi.wrdata(c_select_buf.dat_w - 1 downto 0),
- adr_b => select_mosi.address(c_select_buf.adr_w - 1 downto 0),
- rd_en_b => select_mosi.rd,
- rd_dat_b => select_miso.rddata(c_select_buf.dat_w - 1 downto 0),
- rd_val_b => select_miso.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_select_buf,
+ g_init_file => g_select_file_name
+ )
+ port map (
+ -- MM side
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_ss_ss_mosi.wr,
+ wr_dat_a => ram_ss_ss_mosi.wrdata(c_select_buf.dat_w - 1 downto 0),
+ adr_a => ram_ss_ss_mosi.address(c_select_buf.adr_w - 1 downto 0),
+ rd_en_a => ram_ss_ss_mosi.rd,
+ rd_dat_a => ram_ss_ss_miso.rddata(c_select_buf.dat_w - 1 downto 0),
+ rd_val_a => ram_ss_ss_miso.rdval,
+ -- ST side
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+ wr_en_b => select_mosi.wr,
+ wr_dat_b => select_mosi.wrdata(c_select_buf.dat_w - 1 downto 0),
+ adr_b => select_mosi.address(c_select_buf.adr_w - 1 downto 0),
+ rd_en_b => select_mosi.rd,
+ rd_dat_b => select_miso.rddata(c_select_buf.dat_w - 1 downto 0),
+ rd_val_b => select_miso.rdval
+ );
u_retrieve : entity work.ss_retrieve
- generic map (
- g_dsp_data_w => g_dsp_data_w,
- g_nof_ch_in => g_nof_ch_in,
- g_nof_ch_sel => g_nof_ch_sel
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_ch_in => g_nof_ch_in,
+ g_nof_ch_sel => g_nof_ch_sel
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- -- Timing
- store_done => store_done,
+ -- Timing
+ store_done => store_done,
- -- Read store_buf control
- retrieve_mosi => retrieve_mosi,
- retrieve_miso => retrieve_miso,
- retrieve_done => retrieve_done,
+ -- Read store_buf control
+ retrieve_mosi => retrieve_mosi,
+ retrieve_miso => retrieve_miso,
+ retrieve_done => retrieve_done,
- -- Read select_buf control
- select_mosi => select_mosi,
- select_miso => select_miso,
+ -- Read select_buf control
+ select_mosi => select_mosi,
+ select_miso => select_miso,
- -- Streaming
- output_sosi => retrieve_sosi,
- output_siso => retrieve_siso
- );
+ -- Streaming
+ output_sosi => retrieve_sosi,
+ output_siso => retrieve_siso
+ );
u_rl : entity dp_lib.dp_latency_adapter -- defaults to wires when c_output_rl = c_retrieve_lat
- generic map (
- g_in_latency => c_retrieve_lat,
- g_out_latency => c_output_rl
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out => retrieve_siso,
- snk_in => retrieve_sosi,
- -- ST source
- src_in => ss_siso,
- src_out => ss_sosi
- );
+ generic map (
+ g_in_latency => c_retrieve_lat,
+ g_out_latency => c_output_rl
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => retrieve_siso,
+ snk_in => retrieve_sosi,
+ -- ST source
+ src_in => ss_siso,
+ src_out => ss_sosi
+ );
-- Page delay the input_sosi info (sync, BSN, channel at sop and err, empty at eop) and combine it with the retrieved SS data to get the output_sosi
info_sop_wr_en <= input_sosi.sop & store_done;
info_eop_wr_en <= input_sosi.eop & store_done;
u_info_sosi : entity dp_lib.dp_paged_sop_eop_reg
- generic map (
- g_nof_pages => c_info_nof_pages
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- page write enable ctrl
- sop_wr_en => info_sop_wr_en,
- eop_wr_en => info_eop_wr_en,
- -- ST sink
- snk_in => input_sosi,
- -- ST source
- src_out => info_sosi
- );
+ generic map (
+ g_nof_pages => c_info_nof_pages
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- page write enable ctrl
+ sop_wr_en => info_sop_wr_en,
+ eop_wr_en => info_eop_wr_en,
+ -- ST sink
+ snk_in => input_sosi,
+ -- ST source
+ src_out => info_sosi
+ );
output_sosi <= func_dp_stream_combine_info_and_data(info_sosi, ss_sosi);
ss_siso <= output_siso;
diff --git a/libraries/base/ss/src/vhdl/ss_parallel.vhd b/libraries/base/ss/src/vhdl/ss_parallel.vhd
index 4a458c7ed4..189a41171e 100644
--- a/libraries/base/ss/src/vhdl/ss_parallel.vhd
+++ b/libraries/base/ss/src/vhdl/ss_parallel.vhd
@@ -47,12 +47,12 @@
--
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity ss_parallel is
generic (
@@ -99,102 +99,102 @@ begin
-----------------------------------------------------------------------------
gen_dp_throttle_sop : for i in 0 to g_nof_inputs - 1 generate
u_dp_throttle_sop : entity dp_lib.dp_throttle_sop
- generic map (
- g_period => g_frame_size_out
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_out => input_siso_arr(i),
- snk_in => input_sosi_arr(i)
- );
+ generic map (
+ g_period => g_frame_size_out
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_out => input_siso_arr(i),
+ snk_in => input_sosi_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- Reorder input streams
-----------------------------------------------------------------------------
u_input_reorder : entity work.ss_reorder
- generic map(
- g_technology => g_technology,
- g_nof_inputs => g_nof_inputs,
- g_nof_outputs => g_nof_internals,
- g_dsp_data_w => g_dsp_data_w,
- g_frame_size => g_frame_size_in,
- g_ram_init_file => g_reorder_in_file_name,
- g_pipeline_in => 1,
- g_pipeline_in_m => 1,
- g_pipeline_out => 1
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped
- ram_ss_reorder_mosi => ram_ss_reorder_in_mosi,
- ram_ss_reorder_miso => ram_ss_reorder_in_miso,
-
- -- Streaming
- input_sosi_arr => input_sosi_arr,
- output_sosi_arr => ss_wide_in_sosi_arr
- );
+ generic map(
+ g_technology => g_technology,
+ g_nof_inputs => g_nof_inputs,
+ g_nof_outputs => g_nof_internals,
+ g_dsp_data_w => g_dsp_data_w,
+ g_frame_size => g_frame_size_in,
+ g_ram_init_file => g_reorder_in_file_name,
+ g_pipeline_in => 1,
+ g_pipeline_in_m => 1,
+ g_pipeline_out => 1
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped
+ ram_ss_reorder_mosi => ram_ss_reorder_in_mosi,
+ ram_ss_reorder_miso => ram_ss_reorder_in_miso,
+
+ -- Streaming
+ input_sosi_arr => input_sosi_arr,
+ output_sosi_arr => ss_wide_in_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Serial word selection per stream
-----------------------------------------------------------------------------
u_ss_wide : entity work.ss_wide
- generic map (
- g_technology => g_technology,
- g_wb_factor => g_nof_internals,
- g_dsp_data_w => g_dsp_data_w,
- g_nof_ch_in => g_frame_size_in,
- g_nof_ch_sel => g_frame_size_out,
- g_select_file_prefix => g_ss_wide_file_prefix
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
-
- -- Streaming
- input_sosi_arr => ss_wide_in_sosi_arr,
- input_siso_arr => OPEN,
- output_sosi_arr => ss_wide_out_sosi_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_wb_factor => g_nof_internals,
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_ch_in => g_frame_size_in,
+ g_nof_ch_sel => g_frame_size_out,
+ g_select_file_prefix => g_ss_wide_file_prefix
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+
+ -- Streaming
+ input_sosi_arr => ss_wide_in_sosi_arr,
+ input_siso_arr => OPEN,
+ output_sosi_arr => ss_wide_out_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Reorder output streams
-----------------------------------------------------------------------------
u_output_reorder : entity work.ss_reorder
- generic map(
- g_technology => g_technology,
- g_nof_inputs => g_nof_internals,
- g_nof_outputs => g_nof_outputs,
- g_dsp_data_w => g_dsp_data_w,
- g_frame_size => g_frame_size_out,
- g_ram_init_file => g_reorder_out_file_name,
- g_pipeline_in => 1,
- g_pipeline_in_m => 1,
- g_pipeline_out => 1
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped
- ram_ss_reorder_mosi => ram_ss_reorder_out_mosi,
- ram_ss_reorder_miso => ram_ss_reorder_out_miso,
-
- -- Streaming
- input_sosi_arr => ss_wide_out_sosi_arr,
- output_sosi_arr => output_sosi_arr
- );
+ generic map(
+ g_technology => g_technology,
+ g_nof_inputs => g_nof_internals,
+ g_nof_outputs => g_nof_outputs,
+ g_dsp_data_w => g_dsp_data_w,
+ g_frame_size => g_frame_size_out,
+ g_ram_init_file => g_reorder_out_file_name,
+ g_pipeline_in => 1,
+ g_pipeline_in_m => 1,
+ g_pipeline_out => 1
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped
+ ram_ss_reorder_mosi => ram_ss_reorder_out_mosi,
+ ram_ss_reorder_miso => ram_ss_reorder_out_miso,
+
+ -- Streaming
+ input_sosi_arr => ss_wide_out_sosi_arr,
+ output_sosi_arr => output_sosi_arr
+ );
end str;
diff --git a/libraries/base/ss/src/vhdl/ss_reorder.vhd b/libraries/base/ss/src/vhdl/ss_reorder.vhd
index 1f00b179dd..6bc865aaa6 100644
--- a/libraries/base/ss/src/vhdl/ss_reorder.vhd
+++ b/libraries/base/ss/src/vhdl/ss_reorder.vhd
@@ -32,12 +32,12 @@
--
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity ss_reorder is
generic (
@@ -79,17 +79,19 @@ architecture str of ss_reorder is
constant c_mem_nof_dat_mm : natural := 2**(true_log2(c_nof_mm_regs_per_sel)) * g_frame_size;
constant c_mem_dat_w_dp : natural := 2**(ceil_log2(c_select_word_w));
- constant c_select_buf_mm : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_mem_nof_dat_mm),
- dat_w => c_mem_dat_w_mm,
- nof_dat => c_mem_nof_dat_mm,
- init_sl => '0');
+ constant c_select_buf_mm : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_mem_nof_dat_mm),
+ dat_w => c_mem_dat_w_mm,
+ nof_dat => c_mem_nof_dat_mm,
+ init_sl => '0');
- constant c_select_buf_dp : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_frame_size),
- dat_w => c_mem_dat_w_dp,
- nof_dat => g_frame_size,
- init_sl => '0');
+ constant c_select_buf_dp : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_frame_size),
+ dat_w => c_mem_dat_w_dp,
+ nof_dat => g_frame_size,
+ init_sl => '0');
constant c_data_w : natural := g_dsp_data_w * c_nof_complex;
@@ -117,7 +119,7 @@ begin
---------------------------------------------------------------
gen_input : for I in g_nof_inputs - 1 downto 0 generate
reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <= r.pipe_sosi_2arr(0)(I).im(g_dsp_data_w - 1 downto 0) &
- r.pipe_sosi_2arr(0)(I).re(g_dsp_data_w - 1 downto 0);
+ r.pipe_sosi_2arr(0)(I).re(g_dsp_data_w - 1 downto 0);
end generate;
---------------------------------------------------------------
@@ -127,21 +129,21 @@ begin
-- reorder_select signal.
---------------------------------------------------------------
u_reorder : entity common_lib.common_select_m_symbols
- generic map (
- g_nof_input => g_nof_inputs,
- g_nof_output => g_nof_outputs,
- g_symbol_w => c_nof_complex * g_dsp_data_w,
- g_pipeline_in => g_pipeline_in,
- g_pipeline_in_m => g_pipeline_in_m,
- g_pipeline_out => g_pipeline_out
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_data => reorder_in_dat,
- in_select => reorder_select(g_nof_outputs * c_select_w - 1 downto 0),
- out_data => reorder_out_dat
- );
+ generic map (
+ g_nof_input => g_nof_inputs,
+ g_nof_output => g_nof_outputs,
+ g_symbol_w => c_nof_complex * g_dsp_data_w,
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_in_m => g_pipeline_in_m,
+ g_pipeline_out => g_pipeline_out
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_data => reorder_in_dat,
+ in_select => reorder_select(g_nof_outputs * c_select_w - 1 downto 0),
+ out_data => reorder_out_dat
+ );
---------------------------------------------------------------
-- SELECTION BUFFER
@@ -149,30 +151,30 @@ begin
-- Buffer containing the selection words for a complete frame.
---------------------------------------------------------------
u_select_buf : entity common_lib.common_ram_crw_crw_ratio
- generic map(
- g_technology => g_technology,
- g_ram_a => c_select_buf_mm,
- g_ram_b => c_select_buf_dp,
- g_init_file => g_ram_init_file
- )
- port map (
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_ss_reorder_mosi.wr,
- wr_dat_a => ram_ss_reorder_mosi.wrdata(c_select_buf_mm.dat_w - 1 downto 0),
- adr_a => ram_ss_reorder_mosi.address(c_select_buf_mm.adr_w - 1 downto 0),
- rd_en_a => ram_ss_reorder_mosi.rd,
- rd_dat_a => ram_ss_reorder_miso.rddata(c_select_buf_mm.dat_w - 1 downto 0),
- rd_val_a => ram_ss_reorder_miso.rdval,
-
- rst_b => dp_rst,
- clk_b => dp_clk,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- adr_b => reorder_chan_cnt,
- rd_dat_b => reorder_select,
- rd_val_b => open
- );
+ generic map(
+ g_technology => g_technology,
+ g_ram_a => c_select_buf_mm,
+ g_ram_b => c_select_buf_dp,
+ g_init_file => g_ram_init_file
+ )
+ port map (
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_ss_reorder_mosi.wr,
+ wr_dat_a => ram_ss_reorder_mosi.wrdata(c_select_buf_mm.dat_w - 1 downto 0),
+ adr_a => ram_ss_reorder_mosi.address(c_select_buf_mm.adr_w - 1 downto 0),
+ rd_en_a => ram_ss_reorder_mosi.rd,
+ rd_dat_a => ram_ss_reorder_miso.rddata(c_select_buf_mm.dat_w - 1 downto 0),
+ rd_val_a => ram_ss_reorder_miso.rdval,
+
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ adr_b => reorder_chan_cnt,
+ rd_dat_b => reorder_select,
+ rd_val_b => open
+ );
---------------------------------------------------------------
-- ADDRESS COUNTER
@@ -180,19 +182,19 @@ begin
-- Counter that addresses the selection buffer
---------------------------------------------------------------
u_adr_chn_cnt : entity common_lib.common_counter
- generic map(
- g_latency => 1,
- g_init => 0,
- g_width => c_select_buf_dp.adr_w,
- g_max => g_frame_size
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- cnt_en => input_sosi_arr(0).valid,
- cnt_clr => input_sosi_arr(0).eop,
- count => reorder_chan_cnt
- );
+ generic map(
+ g_latency => 1,
+ g_init => 0,
+ g_width => c_select_buf_dp.adr_w,
+ g_max => g_frame_size
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ cnt_en => input_sosi_arr(0).valid,
+ cnt_clr => input_sosi_arr(0).eop,
+ count => reorder_chan_cnt
+ );
---------------------------------------------------------------
-- REGISTERING AND PIPELINING
@@ -202,7 +204,7 @@ begin
-- Also the data-output of the select_m_symbols block is merged
-- here with the rest of the pipelined SOSI signals.
---------------------------------------------------------------
- comb : process(r, input_sosi_arr, reorder_out_dat)
+ comb : process(r, input_sosi_arr, reorder_out_dat)
variable v : reg_type;
begin
v := r;
diff --git a/libraries/base/ss/src/vhdl/ss_retrieve.vhd b/libraries/base/ss/src/vhdl/ss_retrieve.vhd
index 2d4c2b3c4b..d4a2f329ea 100644
--- a/libraries/base/ss/src/vhdl/ss_retrieve.vhd
+++ b/libraries/base/ss/src/vhdl/ss_retrieve.vhd
@@ -20,28 +20,28 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-
--- Purpose: Retrieve blocks of g_nof_ch_sel complex data words from a dual
--- page data buffer
--- Description:
--- The retrieve control uses a channel select buffer to know the order
--- in which the g_nof_ch_sel complex data words have to be retrieved from the
--- dual page input data buffer. The order is arbitrary and the same channel
--- may be selected multiple times.
--- Remarks:
--- . Typcially output_siso.ready='1'. When g_nof_ch_sel < g_nof_ch_in/2, then a
--- toggling output_siso.ready can be used to multiplex this SS retrieve output
--- with another SS retrieve output stream.
--- . The retrieve_done signal occurs when the last data of the block is read
--- requested, so 1 cycle before the output_sosi.eop.
--- . The timing of the ch_cnt for the retrieve_mosi.address is such that the
--- SS can store a frame and retrieve it immediately in any order, so worst
--- case the last stored data can be retrieved first.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+
+ -- Purpose: Retrieve blocks of g_nof_ch_sel complex data words from a dual
+ -- page data buffer
+ -- Description:
+ -- The retrieve control uses a channel select buffer to know the order
+ -- in which the g_nof_ch_sel complex data words have to be retrieved from the
+ -- dual page input data buffer. The order is arbitrary and the same channel
+ -- may be selected multiple times.
+ -- Remarks:
+ -- . Typcially output_siso.ready='1'. When g_nof_ch_sel < g_nof_ch_in/2, then a
+ -- toggling output_siso.ready can be used to multiplex this SS retrieve output
+ -- with another SS retrieve output stream.
+ -- . The retrieve_done signal occurs when the last data of the block is read
+ -- requested, so 1 cycle before the output_sosi.eop.
+ -- . The timing of the ch_cnt for the retrieve_mosi.address is such that the
+ -- SS can store a frame and retrieve it immediately in any order, so worst
+ -- case the last stored data can be retrieved first.
entity ss_retrieve is
generic (
@@ -108,19 +108,19 @@ begin
-- Enable retrieve when a block has been stored, disable retrieve when the block has been output
u_retrieve_en : entity common_lib.common_switch
- generic map (
- g_rst_level => '0',
- g_priority_lo => false, -- store_done has priority over nxt_retrieve_done when they occur simultaneously
- g_or_high => true,
- g_and_low => false
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => store_done,
- switch_low => nxt_retrieve_done, -- can not use retrieve_done with g_and_low = TRUE, because if retrieve_done occurs after next store_done then that page gets missed
- out_level => retrieve_en
- );
+ generic map (
+ g_rst_level => '0',
+ g_priority_lo => false, -- store_done has priority over nxt_retrieve_done when they occur simultaneously
+ g_or_high => true,
+ g_and_low => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => store_done,
+ switch_low => nxt_retrieve_done, -- can not use retrieve_done with g_and_low = TRUE, because if retrieve_done occurs after next store_done then that page gets missed
+ out_level => retrieve_en
+ );
retrieve_ready <= retrieve_en and output_siso.ready;
diff --git a/libraries/base/ss/src/vhdl/ss_store.vhd b/libraries/base/ss/src/vhdl/ss_store.vhd
index b0acf7da04..b0c79380d1 100644
--- a/libraries/base/ss/src/vhdl/ss_store.vhd
+++ b/libraries/base/ss/src/vhdl/ss_store.vhd
@@ -20,28 +20,28 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-
--- Purpose: Controller that store blocks of g_nof_ch_in complex input data
--- words in a dual page data buffer
--- Description:
--- Write databuf control for g_nof_ch_in complex input data words and pulse
--- store_done for each g_nof_ch_in data words that have been written.
--- Remarks:
--- . The SS stores the complex input data as concatenated data = im & re with
--- data width 2 * g_dsp_data_w.
--- . The SS does not use input sop and eop, because it uses a ch_cnt. Hence
--- the input_sosi only needs to carry im, re and valid, the sop and eop are
--- ignored. The ch_cnt is needed anyway to set the store_mosi.address. The
--- g_nof_ch_in defines the number of valid per input block, so from sop to
--- eop. The ss_store assumes that the first valid corresponds to a sop. The
--- ch_cnt restarts at the and of a block, so when ch_cnt = g_nof_ch_in-1.
--- . The store_done signal occurs when the last data of the block is being
--- written, so 1 cycle after the input_sosi.eop.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+
+ -- Purpose: Controller that store blocks of g_nof_ch_in complex input data
+ -- words in a dual page data buffer
+ -- Description:
+ -- Write databuf control for g_nof_ch_in complex input data words and pulse
+ -- store_done for each g_nof_ch_in data words that have been written.
+ -- Remarks:
+ -- . The SS stores the complex input data as concatenated data = im & re with
+ -- data width 2 * g_dsp_data_w.
+ -- . The SS does not use input sop and eop, because it uses a ch_cnt. Hence
+ -- the input_sosi only needs to carry im, re and valid, the sop and eop are
+ -- ignored. The ch_cnt is needed anyway to set the store_mosi.address. The
+ -- g_nof_ch_in defines the number of valid per input block, so from sop to
+ -- eop. The ss_store assumes that the first valid corresponds to a sop. The
+ -- ch_cnt restarts at the and of a block, so when ch_cnt = g_nof_ch_in-1.
+ -- . The store_done signal occurs when the last data of the block is being
+ -- written, so 1 cycle after the input_sosi.eop.
entity ss_store is
generic (
diff --git a/libraries/base/ss/src/vhdl/ss_wide.vhd b/libraries/base/ss/src/vhdl/ss_wide.vhd
index 37bb7363cc..54f283589b 100644
--- a/libraries/base/ss/src/vhdl/ss_wide.vhd
+++ b/libraries/base/ss/src/vhdl/ss_wide.vhd
@@ -32,12 +32,12 @@
--
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity ss_wide is
generic (
@@ -82,47 +82,47 @@ begin
-- Combine the internal array of mm interfaces for the selection
-- memory to one array that is connected to the port of the ss_wide wunit
u_mem_mux_select : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_wb_factor,
- g_mult_addr_w => c_mem_addr_w
- )
- port map (
- mosi => ram_ss_ss_wide_mosi,
- miso => ram_ss_ss_wide_miso,
- mosi_arr => ram_ss_ss_wide_mosi_arr,
- miso_arr => ram_ss_ss_wide_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_wb_factor,
+ g_mult_addr_w => c_mem_addr_w
+ )
+ port map (
+ mosi => ram_ss_ss_wide_mosi,
+ miso => ram_ss_ss_wide_miso,
+ mosi_arr => ram_ss_ss_wide_mosi_arr,
+ miso_arr => ram_ss_ss_wide_miso_arr
+ );
---------------------------------------------------------------
-- INSTANTIATE MULTIPLE SINGLE CHANNEL SUBBAND SELECT UNITS
---------------------------------------------------------------
gen_ss_singles : for I in 0 to g_wb_factor - 1 generate
u_single_ss : entity work.ss
- generic map (
- g_technology => g_technology,
- g_dsp_data_w => g_dsp_data_w,
- g_nof_ch_in => c_nof_ch_in,
- g_nof_ch_sel => c_nof_ch_sel,
- g_select_file_name => sel_a_b(g_select_file_prefix = "UNUSED", "UNUSED", g_select_file_prefix & "_" & natural'image(I) & ".hex"),
- g_use_complex => g_use_complex
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_technology => g_technology,
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_ch_in => c_nof_ch_in,
+ g_nof_ch_sel => c_nof_ch_sel,
+ g_select_file_name => sel_a_b(g_select_file_prefix = "UNUSED", "UNUSED", g_select_file_prefix & "_" & natural'image(I) & ".hex"),
+ g_use_complex => g_use_complex
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- Memory Mapped
- ram_ss_ss_mosi => ram_ss_ss_wide_mosi_arr(I),
- ram_ss_ss_miso => ram_ss_ss_wide_miso_arr(I),
+ -- Memory Mapped
+ ram_ss_ss_mosi => ram_ss_ss_wide_mosi_arr(I),
+ ram_ss_ss_miso => ram_ss_ss_wide_miso_arr(I),
- -- Streaming
- input_sosi => input_sosi_arr(I),
- input_siso => input_siso_arr(I),
+ -- Streaming
+ input_sosi => input_sosi_arr(I),
+ input_siso => input_siso_arr(I),
- output_sosi => output_sosi_arr(I),
- output_siso => output_siso_arr(I)
- );
+ output_sosi => output_sosi_arr(I),
+ output_siso => output_siso_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/ss/tb/vhdl/tb_mmf_ss_parallel.vhd b/libraries/base/ss/tb/vhdl/tb_mmf_ss_parallel.vhd
index df1f353929..87562323e1 100644
--- a/libraries/base/ss/tb/vhdl/tb_mmf_ss_parallel.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_mmf_ss_parallel.vhd
@@ -37,17 +37,17 @@
-- > Evalute the WAVE window.
library IEEE, common_lib, mm_lib, diag_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
entity tb_mmf_ss_parallel is
generic(
@@ -152,7 +152,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -161,142 +161,151 @@ begin
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_ram_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+ u_mm_file_ram_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
- u_mm_file_reg_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+ u_mm_file_reg_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
- u_mm_file_ram_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+ u_mm_file_ram_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
- u_mm_file_reg_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+ u_mm_file_reg_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
- u_mm_file_ram_ss_reorder_in : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER_IN")
- port map(mm_rst, mm_clk, ram_ss_reorder_in_mosi, ram_ss_reorder_in_miso);
+ u_mm_file_ram_ss_reorder_in : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER_IN")
+ port map(mm_rst, mm_clk, ram_ss_reorder_in_mosi, ram_ss_reorder_in_miso);
- u_mm_file_ram_ss_reorder_out : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER_OUT")
- port map(mm_rst, mm_clk, ram_ss_reorder_out_mosi, ram_ss_reorder_out_miso);
+ u_mm_file_ram_ss_reorder_out : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER_OUT")
+ port map(mm_rst, mm_clk, ram_ss_reorder_out_mosi, ram_ss_reorder_out_miso);
- u_mm_file_ram_ss_ss_wide : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_SS_WIDE")
- port map(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso);
+ u_mm_file_ram_ss_ss_wide : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_SS_WIDE")
+ port map(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => c_bg_nof_output_streams,
- g_buf_dat_w => c_bg_buf_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w,
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut : entity work.ss_parallel
- generic map(
- g_nof_inputs => g_nof_inputs,
- g_nof_internals => g_nof_internals,
- g_nof_outputs => g_nof_outputs,
- g_dsp_data_w => g_dsp_data_w,
- g_frame_size_in => g_frame_size_in,
- g_frame_size_out => g_frame_size_out
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- Memory Mapped
- ram_ss_reorder_in_mosi => ram_ss_reorder_in_mosi,
- ram_ss_reorder_in_miso => ram_ss_reorder_in_miso,
- ram_ss_reorder_out_mosi => ram_ss_reorder_out_mosi,
- ram_ss_reorder_out_miso => ram_ss_reorder_out_miso,
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- -- Streaming
- input_sosi_arr => bg_sosi_arr,
- output_sosi_arr => out_sosi_arr,
- output_siso_arr => out_siso_arr
- );
+ generic map(
+ g_nof_inputs => g_nof_inputs,
+ g_nof_internals => g_nof_internals,
+ g_nof_outputs => g_nof_outputs,
+ g_dsp_data_w => g_dsp_data_w,
+ g_frame_size_in => g_frame_size_in,
+ g_frame_size_out => g_frame_size_out
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- Memory Mapped
+ ram_ss_reorder_in_mosi => ram_ss_reorder_in_mosi,
+ ram_ss_reorder_in_miso => ram_ss_reorder_in_miso,
+ ram_ss_reorder_out_mosi => ram_ss_reorder_out_mosi,
+ ram_ss_reorder_out_miso => ram_ss_reorder_out_miso,
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ -- Streaming
+ input_sosi_arr => bg_sosi_arr,
+ output_sosi_arr => out_sosi_arr,
+ output_siso_arr => out_siso_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_re,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
- ram_data_buf_miso => ram_diag_data_buf_re_miso,
- reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
- reg_data_buf_miso => reg_diag_data_buf_re_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_im,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
- ram_data_buf_miso => ram_diag_data_buf_im_miso,
- reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
- reg_data_buf_miso => reg_diag_data_buf_im_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_im,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/ss/tb/vhdl/tb_mmf_ss_reorder.vhd b/libraries/base/ss/tb/vhdl/tb_mmf_ss_reorder.vhd
index 589296951b..0695a51d82 100644
--- a/libraries/base/ss/tb/vhdl/tb_mmf_ss_reorder.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_mmf_ss_reorder.vhd
@@ -37,17 +37,17 @@
-- > Evalute the WAVE window.
library IEEE, common_lib, mm_lib, diag_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
entity tb_mmf_ss_reorder is
generic(
@@ -148,7 +148,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -157,140 +157,147 @@ begin
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_ram_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+ u_mm_file_ram_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
- u_mm_file_reg_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+ u_mm_file_reg_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
- u_mm_file_ram_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+ u_mm_file_ram_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
- u_mm_file_reg_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+ u_mm_file_reg_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
- u_mm_file_ram_ss_reorder : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER")
- port map(mm_rst, mm_clk, ram_ss_reorder_mosi, ram_ss_reorder_miso);
+ u_mm_file_ram_ss_reorder : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER")
+ port map(mm_rst, mm_clk, ram_ss_reorder_mosi, ram_ss_reorder_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => c_bg_nof_output_streams,
- g_buf_dat_w => c_bg_buf_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w,
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut : entity work.ss_reorder
- generic map(
- g_nof_inputs => g_nof_inputs,
- g_nof_outputs => g_nof_outputs,
- g_dsp_data_w => g_dsp_data_w,
- g_frame_size => g_frame_size,
- g_ram_init_file => g_ram_init_file,
- g_pipeline_in => g_pipeline_in,
- g_pipeline_in_m => g_pipeline_in_m,
- g_pipeline_out => g_pipeline_out
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- Memory Mapped
- ram_ss_reorder_mosi => ram_ss_reorder_mosi,
- ram_ss_reorder_miso => ram_ss_reorder_miso,
- -- Streaming
- input_sosi_arr => bg_sosi_arr,
- output_sosi_arr => out_sosi_arr,
- output_siso_arr => out_siso_arr
- );
+ generic map(
+ g_nof_inputs => g_nof_inputs,
+ g_nof_outputs => g_nof_outputs,
+ g_dsp_data_w => g_dsp_data_w,
+ g_frame_size => g_frame_size,
+ g_ram_init_file => g_ram_init_file,
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_in_m => g_pipeline_in_m,
+ g_pipeline_out => g_pipeline_out
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- Memory Mapped
+ ram_ss_reorder_mosi => ram_ss_reorder_mosi,
+ ram_ss_reorder_miso => ram_ss_reorder_miso,
+ -- Streaming
+ input_sosi_arr => bg_sosi_arr,
+ output_sosi_arr => out_sosi_arr,
+ output_siso_arr => out_siso_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_re,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
- ram_data_buf_miso => ram_diag_data_buf_re_miso,
-
- reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
- reg_data_buf_miso => reg_diag_data_buf_re_miso,
-
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_im,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
- ram_data_buf_miso => ram_diag_data_buf_im_miso,
-
- reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
- reg_data_buf_miso => reg_diag_data_buf_im_miso,
-
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_im,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/ss/tb/vhdl/tb_ss.vhd b/libraries/base/ss/tb/vhdl/tb_ss.vhd
index 35585289e6..27feb093f2 100644
--- a/libraries/base/ss/tb/vhdl/tb_ss.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_ss.vhd
@@ -20,36 +20,36 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-
--- Usage:
--- > as 10
--- > run -all
--- . Observe in_sosi and out_sosi in the Wave window
---
--- Description:
--- . This tb_ss for the subband select (SS) self verifies the data, sync and BSN
--- . The flow control is selected via g_mode_in_en and g_mode_out_ready.
---
--- Remark:
--- . Use tb_tb_ss for multi-tb DUT verification.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+
+ -- Usage:
+ -- > as 10
+ -- > run -all
+ -- . Observe in_sosi and out_sosi in the Wave window
+ --
+ -- Description:
+ -- . This tb_ss for the subband select (SS) self verifies the data, sync and BSN
+ -- . The flow control is selected via g_mode_in_en and g_mode_out_ready.
+ --
+ -- Remark:
+ -- . Use tb_tb_ss for multi-tb DUT verification.
entity tb_ss is
generic (
-- Flow control
g_mode_in_en : natural := 0; -- use 0 for active in_sosi.valid control
- -- use 1 for random in_sosi.valid control
+ -- use 1 for random in_sosi.valid control
g_mode_out_ready : natural := 0; -- use 0 for active out_siso.ready control
- -- use 1 for toggling out_siso.ready control, requires g_nof_ch_sel <= g_nof_ch_in/2
- -- use 2 for inverted toggling out_siso.ready control, requires g_nof_ch_sel <= g_nof_ch_in/2
+ -- use 1 for toggling out_siso.ready control, requires g_nof_ch_sel <= g_nof_ch_in/2
+ -- use 2 for inverted toggling out_siso.ready control, requires g_nof_ch_sel <= g_nof_ch_in/2
-- Test duration
g_nof_sync : natural := 10;
@@ -218,11 +218,42 @@ begin
end process;
u_reverse_ss : entity work.ss
+ generic map (
+ g_use_output_rl_adapter => g_use_output_rl_adapter,
+ g_dsp_data_w => c_dsp_data_w,
+ g_nof_ch_in => g_nof_ch_in,
+ g_nof_ch_sel => g_nof_ch_in,
+ g_use_complex => g_use_complex
+ )
+ port map (
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+
+ -- Memory Mapped
+ ram_ss_ss_mosi => mm_reverse_mosi,
+ ram_ss_ss_miso => OPEN,
+
+ -- Streaming
+ input_sosi => dp_sosi,
+
+ output_sosi => reverse_sosi,
+ output_siso => c_dp_siso_rdy
+ );
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- DUT : SS
+ ------------------------------------------------------------------------------
+ in_sosi <= dp_sosi when g_reverse_ss_map = false else reverse_sosi;
+
+ u_dut_ss : entity work.ss
generic map (
g_use_output_rl_adapter => g_use_output_rl_adapter,
g_dsp_data_w => c_dsp_data_w,
g_nof_ch_in => g_nof_ch_in,
- g_nof_ch_sel => g_nof_ch_in,
+ g_nof_ch_sel => g_nof_ch_sel,
g_use_complex => g_use_complex
)
port map (
@@ -232,46 +263,15 @@ begin
dp_clk => clk,
-- Memory Mapped
- ram_ss_ss_mosi => mm_reverse_mosi,
+ ram_ss_ss_mosi => mm_dut_mosi,
ram_ss_ss_miso => OPEN,
-- Streaming
- input_sosi => dp_sosi,
+ input_sosi => in_sosi,
- output_sosi => reverse_sosi,
- output_siso => c_dp_siso_rdy
+ output_sosi => out_sosi,
+ output_siso => out_siso
);
- end generate;
-
- ------------------------------------------------------------------------------
- -- DUT : SS
- ------------------------------------------------------------------------------
- in_sosi <= dp_sosi when g_reverse_ss_map = false else reverse_sosi;
-
- u_dut_ss : entity work.ss
- generic map (
- g_use_output_rl_adapter => g_use_output_rl_adapter,
- g_dsp_data_w => c_dsp_data_w,
- g_nof_ch_in => g_nof_ch_in,
- g_nof_ch_sel => g_nof_ch_sel,
- g_use_complex => g_use_complex
- )
- port map (
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
-
- -- Memory Mapped
- ram_ss_ss_mosi => mm_dut_mosi,
- ram_ss_ss_miso => OPEN,
-
- -- Streaming
- input_sosi => in_sosi,
-
- output_sosi => out_sosi,
- output_siso => out_siso
- );
------------------------------------------------------------------------------
-- Verify
diff --git a/libraries/base/ss/tb/vhdl/tb_ss_wide.vhd b/libraries/base/ss/tb/vhdl/tb_ss_wide.vhd
index c4b8e4051d..7fe0873f3e 100644
--- a/libraries/base/ss/tb/vhdl/tb_ss_wide.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_ss_wide.vhd
@@ -20,21 +20,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-
--- Usage:
--- > as 10
--- > run -all
--- . Observe in_sosi_arr and out_sosi_arr in the Wave window
---
--- Description:
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+
+ -- Usage:
+ -- > as 10
+ -- > run -all
+ -- . Observe in_sosi_arr and out_sosi_arr in the Wave window
+ --
+ -- Description:
entity tb_ss_wide is
end tb_ss_wide;
@@ -152,27 +152,27 @@ begin
end process;
u_dut : entity work.ss_wide
- generic map (
- g_wb_factor => c_wb_factor,
- g_dsp_data_w => c_dsp_data_w,
- g_nof_ch_in => c_nof_ch_in,
- g_nof_ch_sel => c_nof_ch_sel,
- g_select_file_prefix => c_select_file_prefix
- )
- port map (
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
-
- -- Memory Mapped
- ram_ss_ss_wide_mosi => mm_mosi,
- ram_ss_ss_wide_miso => mm_miso,
-
- -- Streaming
- input_sosi_arr => in_sosi_arr,
-
- output_sosi_arr => out_sosi_arr,
- output_siso_arr => out_siso_arr
- );
+ generic map (
+ g_wb_factor => c_wb_factor,
+ g_dsp_data_w => c_dsp_data_w,
+ g_nof_ch_in => c_nof_ch_in,
+ g_nof_ch_sel => c_nof_ch_sel,
+ g_select_file_prefix => c_select_file_prefix
+ )
+ port map (
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+
+ -- Memory Mapped
+ ram_ss_ss_wide_mosi => mm_mosi,
+ ram_ss_ss_wide_miso => mm_miso,
+
+ -- Streaming
+ input_sosi_arr => in_sosi_arr,
+
+ output_sosi_arr => out_sosi_arr,
+ output_siso_arr => out_siso_arr
+ );
end tb;
diff --git a/libraries/base/ss/tb/vhdl/tb_tb_ss.vhd b/libraries/base/ss/tb/vhdl/tb_tb_ss.vhd
index 48c9b93725..e19a5cf000 100644
--- a/libraries/base/ss/tb/vhdl/tb_tb_ss.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_tb_ss.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_ss is
end tb_tb_ss;
diff --git a/libraries/base/uth/src/vhdl/uth_pkg.vhd b/libraries/base/uth/src/vhdl/uth_pkg.vhd
index fc4b0c498b..8212eb3db3 100644
--- a/libraries/base/uth/src/vhdl/uth_pkg.vhd
+++ b/libraries/base/uth/src/vhdl/uth_pkg.vhd
@@ -20,13 +20,13 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, easics_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-use easics_lib.PCK_CRC8_D8.all;
-use easics_lib.PCK_CRC16_D16.all;
-use easics_lib.PCK_CRC32_D32.all;
-use easics_lib.PCK_CRC64_D64.all;
+ use easics_lib.PCK_CRC8_D8.all;
+ use easics_lib.PCK_CRC16_D16.all;
+ use easics_lib.PCK_CRC32_D32.all;
+ use easics_lib.PCK_CRC64_D64.all;
package uth_pkg is
--<constants>--
diff --git a/libraries/base/uth/src/vhdl/uth_rx.vhd b/libraries/base/uth/src/vhdl/uth_rx.vhd
index 6d186c500d..132f765a63 100644
--- a/libraries/base/uth/src/vhdl/uth_rx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_rx.vhd
@@ -20,119 +20,119 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.uth_pkg.all;
-
--- Purpose: Extract the data block from an UTH frame.
--- Usage:
--- This entity has two architectures:
--- . rtl_adapt
--- . rtl_hold <== PREFERRED, although both are suitable
---
--- Remarks:
--- . Both architectures verify correct with tb_uth and tb_tb_uth.
--- . Running tb_tb_uth with random ready for c_repeat=10 shows that
--- verify_done occurs 1.006 later when using rtl_hold than when using
--- rtl_adapt.
--- . If the sink does not need flow control then the RL adapter can be
--- omitted using g_use_src_in=FALSE.
--- . The RL 2->1 adapter costs 3 registers, this compares to the src_buf
--- with dp_hold_input that takes 1 register. Hence g_use_src_in=TRUE then
--- the 'rtl_hold' architecture will take less logic resources. However
--- when g_use_src_in=FALSE then it depends on whether the synthesis tool
--- can optimize such that it notices that src_hld is equivalent to src_buf.
---
--- Description:
--- From the input UTH frame stream:
---
--- ------------------------------------------------
--- ... idle | pre | sfd | tlen | data ... | crc | idle ...
--- ------------------------------------------------
---
--- detect and output the block data:
---
--- -----------------------
--- | data ... |
--- -----------------------
--- sop eop
--- val val ... val
--- err
--- channel ...
---
--- Mark the sop and eop of each frame and check the received CRC.
---
--- . An UTH frame consists of preable, sfd, tlen, data and crc. The UTH frame
--- starts with one c_uth_preamble word. The last data word is held during the
--- crc and output at the eop. The received crc is passed on via the SOSI
--- err field, where 0 indicates OK and 1 indicates an crc error. The SOSI
--- err field is active at the output eop.
--- . The sop is detected based on a c_uth_preamble to c_uth_sfd word transition
--- and the eop is then determined by counting nof_data data words. The UTH
--- frame overhead words are stripped, only the payload data is output,
--- indicated by the output sop and eop.
--- . While counting valid data words the component is insensitive to possible
--- c_uth_preamble/c_uth_sfd words in the data. Hence the output is always a
--- full block, if for some reason the input UTH framing got corrupted, then
--- this will reflect in the crc so the SOSI err field will note error.
--- Another UTH frame may even get lost, but the UTH frame reception will
--- recover on a next sop detection.
--- . Without backpressure (so ready='1') and continuous valid data the UTH Tx
--- frame is valid from sop to eop (so no gaps) and als between UTH Tx frames
--- there are no gaps if their there are sufficient input blocks.
--- For the Rx payloads there is a 1 cycle gap just before the eop, due to the
--- processing of the CRC. Between Rx payloads there is a gap of 3 cycles
--- between the eop and the sop due to the 3 UTH frame header words (preamble,
--- sfd and tlen) that get removed from the UTH Rx packets.
--- . The uth_rx supports packet level flow control by flushing packets from
--- the sink when src_in.xon is XOFF. Therefore the indication to the sink is
--- always XON.
--- . Typically choose the rx timeout g_timeout_w=0 if a link is fixed after
--- power up (e.g. for UniBoard mesh). If the link can stop and start
--- asynchronously (e.g. changing cables, transmitter restart) then choose
--- g_timeout_w sufficient to fit the frame period (e.g. for UniBoard back
--- via CX4 instead of via backplane).
--- . In p_state the rx timeout restart after every active snk_in.valid, this in
--- principle allows using a smaller timeout that is sufficient to span the
--- inactive gaps of snk_in.valid, so then g_timeout_w <= frame period is
--- sufficient. An alternative implementation for the timeout would be to let
--- the timeout run from the sop, the timeout must then at least span the
--- frame period. The frame period can vary somewhat due to mutliplexing
--- so g_timeout_w would then have to be set to ceil_log2(frame period)+1.
---
--- Remarks:
--- . Determine nxt_crc outside the p_state machine process, because that makes
--- the code more clear and more similar to uth_tx.vhd.
--- . Do not use:
--- IF valid='1' THEN
--- CASE state IS ... etc ...
--- but instead do:
--- CASE state IS ... etc ... and evaluate valid='1' per '=>' clause,
--- because that provides better control over what to do when valid='0'
--- and it makes the code more clear.
---
--- Design steps:
--- 1) First made uth_tx, because it is needed to test this uth_rx.
--- 2) ARCHITECTURE rtl_adapt:
--- As a first step this uth_rx was implemented based on snk_in.valid and not
--- taking account of src_in.ready, because that is easier. The src_out then
--- can have two valid data after src_in.ready went low, so this then needs
--- to be accounted for by using a RL 2 -> 1 latency adapter.
--- 3) For testing the tb_uth.vhd is used, with the streaming control signals
--- always active or some random or all random, what ever is appropriate.
--- 4) Initially only g_use_this_siso=FALSE was used and later on also the TRUE
--- option was implemented.
--- . When g_use_this_siso=TRUE then in addition uth_rx can also be ready
--- when it is receiving idle or the header to increase the throughput.
--- . When g_use_this_siso=FALSE then uth_rx does not need to control snk_out
--- and it is ready when the downstream sink is ready, this may ease
--- achieving timing closure.
--- 5) ARCHITECTURE rtl_hold:
--- Finally the RL 2 -> 1 latency adapter at the output was 'replaced' by a
--- dp_hold_input at the input. The p_state machine now maintains the RL = 1
--- by using the outputs from the dp_hold_input.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.uth_pkg.all;
+
+ -- Purpose: Extract the data block from an UTH frame.
+ -- Usage:
+ -- This entity has two architectures:
+ -- . rtl_adapt
+ -- . rtl_hold <== PREFERRED, although both are suitable
+ --
+ -- Remarks:
+ -- . Both architectures verify correct with tb_uth and tb_tb_uth.
+ -- . Running tb_tb_uth with random ready for c_repeat=10 shows that
+ -- verify_done occurs 1.006 later when using rtl_hold than when using
+ -- rtl_adapt.
+ -- . If the sink does not need flow control then the RL adapter can be
+ -- omitted using g_use_src_in=FALSE.
+ -- . The RL 2->1 adapter costs 3 registers, this compares to the src_buf
+ -- with dp_hold_input that takes 1 register. Hence g_use_src_in=TRUE then
+ -- the 'rtl_hold' architecture will take less logic resources. However
+ -- when g_use_src_in=FALSE then it depends on whether the synthesis tool
+ -- can optimize such that it notices that src_hld is equivalent to src_buf.
+ --
+ -- Description:
+ -- From the input UTH frame stream:
+ --
+ -- ------------------------------------------------
+ -- ... idle | pre | sfd | tlen | data ... | crc | idle ...
+ -- ------------------------------------------------
+ --
+ -- detect and output the block data:
+ --
+ -- -----------------------
+ -- | data ... |
+ -- -----------------------
+ -- sop eop
+ -- val val ... val
+ -- err
+ -- channel ...
+ --
+ -- Mark the sop and eop of each frame and check the received CRC.
+ --
+ -- . An UTH frame consists of preable, sfd, tlen, data and crc. The UTH frame
+ -- starts with one c_uth_preamble word. The last data word is held during the
+ -- crc and output at the eop. The received crc is passed on via the SOSI
+ -- err field, where 0 indicates OK and 1 indicates an crc error. The SOSI
+ -- err field is active at the output eop.
+ -- . The sop is detected based on a c_uth_preamble to c_uth_sfd word transition
+ -- and the eop is then determined by counting nof_data data words. The UTH
+ -- frame overhead words are stripped, only the payload data is output,
+ -- indicated by the output sop and eop.
+ -- . While counting valid data words the component is insensitive to possible
+ -- c_uth_preamble/c_uth_sfd words in the data. Hence the output is always a
+ -- full block, if for some reason the input UTH framing got corrupted, then
+ -- this will reflect in the crc so the SOSI err field will note error.
+ -- Another UTH frame may even get lost, but the UTH frame reception will
+ -- recover on a next sop detection.
+ -- . Without backpressure (so ready='1') and continuous valid data the UTH Tx
+ -- frame is valid from sop to eop (so no gaps) and als between UTH Tx frames
+ -- there are no gaps if their there are sufficient input blocks.
+ -- For the Rx payloads there is a 1 cycle gap just before the eop, due to the
+ -- processing of the CRC. Between Rx payloads there is a gap of 3 cycles
+ -- between the eop and the sop due to the 3 UTH frame header words (preamble,
+ -- sfd and tlen) that get removed from the UTH Rx packets.
+ -- . The uth_rx supports packet level flow control by flushing packets from
+ -- the sink when src_in.xon is XOFF. Therefore the indication to the sink is
+ -- always XON.
+ -- . Typically choose the rx timeout g_timeout_w=0 if a link is fixed after
+ -- power up (e.g. for UniBoard mesh). If the link can stop and start
+ -- asynchronously (e.g. changing cables, transmitter restart) then choose
+ -- g_timeout_w sufficient to fit the frame period (e.g. for UniBoard back
+ -- via CX4 instead of via backplane).
+ -- . In p_state the rx timeout restart after every active snk_in.valid, this in
+ -- principle allows using a smaller timeout that is sufficient to span the
+ -- inactive gaps of snk_in.valid, so then g_timeout_w <= frame period is
+ -- sufficient. An alternative implementation for the timeout would be to let
+ -- the timeout run from the sop, the timeout must then at least span the
+ -- frame period. The frame period can vary somewhat due to mutliplexing
+ -- so g_timeout_w would then have to be set to ceil_log2(frame period)+1.
+ --
+ -- Remarks:
+ -- . Determine nxt_crc outside the p_state machine process, because that makes
+ -- the code more clear and more similar to uth_tx.vhd.
+ -- . Do not use:
+ -- IF valid='1' THEN
+ -- CASE state IS ... etc ...
+ -- but instead do:
+ -- CASE state IS ... etc ... and evaluate valid='1' per '=>' clause,
+ -- because that provides better control over what to do when valid='0'
+ -- and it makes the code more clear.
+ --
+ -- Design steps:
+ -- 1) First made uth_tx, because it is needed to test this uth_rx.
+ -- 2) ARCHITECTURE rtl_adapt:
+ -- As a first step this uth_rx was implemented based on snk_in.valid and not
+ -- taking account of src_in.ready, because that is easier. The src_out then
+ -- can have two valid data after src_in.ready went low, so this then needs
+ -- to be accounted for by using a RL 2 -> 1 latency adapter.
+ -- 3) For testing the tb_uth.vhd is used, with the streaming control signals
+ -- always active or some random or all random, what ever is appropriate.
+ -- 4) Initially only g_use_this_siso=FALSE was used and later on also the TRUE
+ -- option was implemented.
+ -- . When g_use_this_siso=TRUE then in addition uth_rx can also be ready
+ -- when it is receiving idle or the header to increase the throughput.
+ -- . When g_use_this_siso=FALSE then uth_rx does not need to control snk_out
+ -- and it is ready when the downstream sink is ready, this may ease
+ -- achieving timing closure.
+ -- 5) ARCHITECTURE rtl_hold:
+ -- Finally the RL 2 -> 1 latency adapter at the output was 'replaced' by a
+ -- dp_hold_input at the input. The p_state machine now maintains the RL = 1
+ -- by using the outputs from the dp_hold_input.
entity uth_rx is
generic (
@@ -172,10 +172,11 @@ architecture rtl_adapt of uth_rx is
type t_state is (s_sfd, s_tlen, s_sop, s_data, s_crc, s_eop, s_flush);
-- handle rx timeout
- procedure proc_handle_rx_timeout(signal valid : in std_logic;
- signal timeout_evt : in std_logic;
- signal clr : out std_logic;
- variable v_state : inout t_state) is -- use variable v_state instead of signal to avoid getting latches
+ procedure proc_handle_rx_timeout(
+ signal valid : in std_logic;
+ signal timeout_evt : in std_logic;
+ signal clr : out std_logic;
+ variable v_state : inout t_state) is -- use variable v_state instead of signal to avoid getting latches
begin
if valid = '1' then
clr <= '1'; -- restart timeout_cnt during frame rx and remain in current state
@@ -248,20 +249,20 @@ begin
use_src_in : if g_use_src_in = true generate
u_rl_adapt : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 2, -- uth_rx does cause one cycle latency, so using dp_latency_adapter to fit current src_in.ready again (using dp_pipeline does not apply here)
- g_out_latency => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => blk_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => 2, -- uth_rx does cause one cycle latency, so using dp_latency_adapter to fit current src_in.ready again (using dp_pipeline does not apply here)
+ g_out_latency => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => blk_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
p_clk : process (clk, rst)
@@ -296,15 +297,15 @@ begin
gen_timeout : if g_timeout_w > 0 generate
u_timeout_cnt : entity common_lib.common_counter
- generic map (
- g_width => c_timeout_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => timeout_cnt_clr,
- count => timeout_cnt
- );
+ generic map (
+ g_width => c_timeout_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => timeout_cnt_clr,
+ count => timeout_cnt
+ );
timeout_evt <= timeout_cnt(g_timeout_w); -- check MSbit for timeout of 2**g_timeout_w clk cycles
@@ -321,17 +322,17 @@ begin
rx_tlen <= snk_in.data(g_data_w - 1 downto 0);
u_rx_tlen : entity work.uth_rx_tlen
- generic map (
- g_data_w => g_data_w,
- g_nof_ch => g_nof_ch,
- g_typ_arr => g_typ_arr,
- g_len_arr => g_len_arr
- )
- port map (
- tlen => rx_tlen,
- nof_data => nof_data,
- channel => channel
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_nof_ch => g_nof_ch,
+ g_typ_arr => g_typ_arr,
+ g_len_arr => g_len_arr
+ )
+ port map (
+ tlen => rx_tlen,
+ nof_data => nof_data,
+ channel => channel
+ );
-- Calculate CRC
p_crc : process(crc, crc_init, snk_in)
@@ -478,10 +479,11 @@ architecture rtl_hold of uth_rx is
type t_state is (s_sfd, s_tlen, s_sop, s_data, s_crc, s_eop, s_flush);
-- handle rx timeout
- procedure proc_handle_rx_timeout(signal valid : in std_logic;
- signal timeout_evt : in std_logic;
- signal clr : out std_logic;
- variable v_state : inout t_state) is -- use variable v_state instead of signal to avoid getting latches
+ procedure proc_handle_rx_timeout(
+ signal valid : in std_logic;
+ signal timeout_evt : in std_logic;
+ signal clr : out std_logic;
+ variable v_state : inout t_state) is -- use variable v_state instead of signal to avoid getting latches
begin
if valid = '1' then
clr <= '1'; -- restart timeout_cnt during frame rx and remain in current state
@@ -588,15 +590,15 @@ begin
gen_timeout : if g_timeout_w > 0 generate
u_timeout_cnt : entity common_lib.common_counter
- generic map (
- g_width => c_timeout_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => timeout_cnt_clr,
- count => timeout_cnt
- );
+ generic map (
+ g_width => c_timeout_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => timeout_cnt_clr,
+ count => timeout_cnt
+ );
timeout_evt <= timeout_cnt(g_timeout_w); -- check MSbit for timeout of 2**g_timeout_w clk cycles
@@ -610,34 +612,34 @@ begin
nxt_src_buf <= next_src_buf;
u_hold : entity dp_lib.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in,
- -- ST source
- src_in => hold_src_in,
- next_src_out => next_src_buf,
- pend_src_out => pend_src_buf,
- src_out_reg => src_buf
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in,
+ -- ST source
+ src_in => hold_src_in,
+ next_src_out => next_src_buf,
+ pend_src_out => pend_src_buf,
+ src_out_reg => src_buf
+ );
-- Derive nof_data and channel number from tlen
rx_tlen <= pend_src_buf.data(g_data_w - 1 downto 0); -- can use pend_src_buf instead of next_src_buf because no need to depend on this_siso
u_rx_tlen : entity work.uth_rx_tlen
- generic map (
- g_data_w => g_data_w,
- g_nof_ch => g_nof_ch,
- g_typ_arr => g_typ_arr,
- g_len_arr => g_len_arr
- )
- port map (
- tlen => rx_tlen,
- nof_data => nof_data,
- channel => channel
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_nof_ch => g_nof_ch,
+ g_typ_arr => g_typ_arr,
+ g_len_arr => g_len_arr
+ )
+ port map (
+ tlen => rx_tlen,
+ nof_data => nof_data,
+ channel => channel
+ );
-- Calculate CRC
p_crc : process(crc, crc_init, next_src_buf)
diff --git a/libraries/base/uth/src/vhdl/uth_rx_tlen.vhd b/libraries/base/uth/src/vhdl/uth_rx_tlen.vhd
index 77a4beeb5a..e00a3a0474 100644
--- a/libraries/base/uth/src/vhdl/uth_rx_tlen.vhd
+++ b/libraries/base/uth/src/vhdl/uth_rx_tlen.vhd
@@ -20,38 +20,38 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.uth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.uth_pkg.all;
--- Purpose: Determine UTH frame length and channel from Rx tlen field value
---
--- Description:
--- This uth_rx_tlen only lets the g_nof_ch different UTH frames through. The
--- frame 'tlen' should match the g_typ_arr. When it matches then the use
--- the corresponding length value from g_len_arr for passing the payload from
--- the UTH frame on to the corresponding channel. All other UTH frames that
--- may appear with 'tlen' that are not in g_typ_arr will get discarded.
---
--- * Example 1:
--- g_data_w = 8
--- g_nof_ch = 1
--- g_typ_arr = 30
--- g_len_arr = 30
--- channel = don't care
---
--- * Example 2:
--- g_data_w = 8
--- g_nof_ch = 5
--- g_typ_arr = 30, 128, 201, 200, 60
--- g_len_arr = 30, 25, 20, 20, 60
--- channel = 0, 1, 2, 3, 4
---
--- Note that the g_typ_arr entries must all be unique. By using different
--- TLEN types it is possible to have different kind of packets with the same
--- length, e.g. like for TLEN type is 200 and 201 in example 2.
+ -- Purpose: Determine UTH frame length and channel from Rx tlen field value
+ --
+ -- Description:
+ -- This uth_rx_tlen only lets the g_nof_ch different UTH frames through. The
+ -- frame 'tlen' should match the g_typ_arr. When it matches then the use
+ -- the corresponding length value from g_len_arr for passing the payload from
+ -- the UTH frame on to the corresponding channel. All other UTH frames that
+ -- may appear with 'tlen' that are not in g_typ_arr will get discarded.
+ --
+ -- * Example 1:
+ -- g_data_w = 8
+ -- g_nof_ch = 1
+ -- g_typ_arr = 30
+ -- g_len_arr = 30
+ -- channel = don't care
+ --
+ -- * Example 2:
+ -- g_data_w = 8
+ -- g_nof_ch = 5
+ -- g_typ_arr = 30, 128, 201, 200, 60
+ -- g_len_arr = 30, 25, 20, 20, 60
+ -- channel = 0, 1, 2, 3, 4
+ --
+ -- Note that the g_typ_arr entries must all be unique. By using different
+ -- TLEN types it is possible to have different kind of packets with the same
+ -- length, e.g. like for TLEN type is 200 and 201 in example 2.
entity uth_rx_tlen is
generic (
diff --git a/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd b/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd
index 4db9301b8b..59d3baad0e 100644
--- a/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd
+++ b/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd
@@ -29,13 +29,13 @@
-- application needs so.
library IEEE, common_lib, technology_lib, dp_lib, uth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_packet_pkg.all;
-use work.uth_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_packet_pkg.all;
+ use work.uth_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity uth_terminal_bidir is
generic (
@@ -114,12 +114,12 @@ architecture str of uth_terminal_bidir is
-- Rx
constant c_rx_input_use_fifo : boolean := false; -- Note that mms_tr_nonbonded also already contains an clock-domain crossing FIFO for which the size can be set via c_rx_phy_fifo_size.
- -- Furthermore typically Rx does not need slack because frame headers and tails are stripped.
+ -- Furthermore typically Rx does not need slack because frame headers and tails are stripped.
constant c_rx_input_fifo_fill : natural := 0;
constant c_rx_input_fifo_size : natural := c_bram_m9k_fifo_depth; -- choose to use full BRAM size = 256 for FIFO depth
begin
- gen_tx : if g_use_tx = true generate
- u_uth_terminal_tx : entity work.uth_terminal_tx
+ gen_tx : if g_use_tx = true generate
+ u_uth_terminal_tx : entity work.uth_terminal_tx
generic map (
g_technology => g_technology,
-- Terminal IO
@@ -164,10 +164,10 @@ begin
src_in_arr => tx_uth_siso_arr,
src_out_arr => tx_uth_sosi_arr
);
- end generate;
+ end generate;
- gen_rx : if g_use_rx = true generate
- u_uth_terminal_rx : entity work.uth_terminal_rx
+ gen_rx : if g_use_rx = true generate
+ u_uth_terminal_rx : entity work.uth_terminal_rx
generic map (
g_technology => g_technology,
-- Terminal IO
@@ -209,6 +209,6 @@ begin
mon_pkt_sosi_arr => rx_mon_pkt_sosi_arr,
mon_dist_sosi_arr => rx_mon_dist_sosi_arr
);
- end generate;
+ end generate;
end str;
diff --git a/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd b/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
index e31b474623..6b6a229385 100644
--- a/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
@@ -40,12 +40,12 @@
-- the CRC) in the original DP packet err field at bit index g_uth_err_bi.
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.uth_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.uth_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity uth_terminal_rx is
generic (
@@ -124,85 +124,85 @@ begin
gen_fifo : if g_input_use_fifo = true generate
-- Input FIFO passes DP/Uthernet packets, so the sosi control fields (sync, bsn, empty, channel and error) are encoded in the packet data
u_fifo_fill : entity dp_lib.dp_fifo_fill
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_packet_data_w,
+ g_fifo_fill => g_input_fifo_fill,
+ g_fifo_af_margin => g_input_fifo_af_margin,
+ g_fifo_size => g_input_fifo_size,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => in_siso_arr(I),
+ src_out => in_sosi_arr(I)
+ );
+ end generate;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- UTHernet receiver
+ ------------------------------------------------------------------------------
+
+ gen_input : for I in g_nof_input - 1 downto 0 generate
+ --u_uth_rx : ENTITY work.uth_rx(rtl_adapt) -- requires using g_fifo_af_margin >= 10
+ u_uth_rx : entity work.uth_rx(rtl_hold) -- can use default g_fifo_af_margin >= 4
generic map (
- g_technology => g_technology,
- g_data_w => g_packet_data_w,
- g_fifo_fill => g_input_fifo_fill,
- g_fifo_af_margin => g_input_fifo_af_margin,
- g_fifo_size => g_input_fifo_size,
- g_fifo_rl => 1
+ g_data_w => g_packet_data_w,
+ g_len_max => g_uth_len_max,
+ g_nof_ch => g_uth_nof_ch,
+ g_typ_arr => g_uth_typ_arr,
+ g_len_arr => g_uth_len_arr,
+ g_use_this_siso => true, -- default use TRUE for best throughput performance
+ g_use_src_in => true, -- default use TRUE for src_in.ready flow control else use FALSE to avoid RL adapter when src_in.ready='1' fixed
+ g_timeout_w => g_uth_timeout_w
)
port map (
rst => rst,
clk => clk,
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
+ -- ST sinks
+ snk_out => in_siso_arr(I),
+ snk_in => in_sosi_arr(I),
-- ST source
- src_in => in_siso_arr(I),
- src_out => in_sosi_arr(I)
+ src_in => pkt_siso_arr(I),
+ src_out => pkt_sosi_arr(I)
);
- end generate;
end generate;
------------------------------------------------------------------------------
- -- UTHernet receiver
+ -- DP distribute: g_nof_input --> g_nof_output
------------------------------------------------------------------------------
- gen_input : for I in g_nof_input - 1 downto 0 generate
- --u_uth_rx : ENTITY work.uth_rx(rtl_adapt) -- requires using g_fifo_af_margin >= 10
- u_uth_rx : entity work.uth_rx(rtl_hold) -- can use default g_fifo_af_margin >= 4
+ u_distribute : entity dp_lib.dp_distribute
generic map (
- g_data_w => g_packet_data_w,
- g_len_max => g_uth_len_max,
- g_nof_ch => g_uth_nof_ch,
- g_typ_arr => g_uth_typ_arr,
- g_len_arr => g_uth_len_arr,
- g_use_this_siso => true, -- default use TRUE for best throughput performance
- g_use_src_in => true, -- default use TRUE for src_in.ready flow control else use FALSE to avoid RL adapter when src_in.ready='1' fixed
- g_timeout_w => g_uth_timeout_w
+ g_technology => g_technology,
+ -- Distribution IO
+ g_tx => false,
+ g_nof_input => g_nof_input,
+ g_nof_output => g_nof_output,
+ g_transpose => false,
+ g_code_channel_lo => true,
+ g_data_w => g_packet_data_w,
+ -- Scheduling
+ g_rx_mux_mode => g_mux_mode, -- default 0 for non-blocking mux, but 1 also works in simulation and on hardware provided that the inputs are garantueed to arrive
+ -- Input FIFO
+ g_use_fifo => false
)
port map (
- rst => rst,
- clk => clk,
+ rst => rst,
+ clk => clk,
-- ST sinks
- snk_out => in_siso_arr(I),
- snk_in => in_sosi_arr(I),
+ snk_out_arr => pkt_siso_arr,
+ snk_in_arr => pkt_sosi_arr,
-- ST source
- src_in => pkt_siso_arr(I),
- src_out => pkt_sosi_arr(I)
+ src_in_arr => dist_siso_arr,
+ src_out_arr => dist_sosi_arr
);
- end generate;
-
- ------------------------------------------------------------------------------
- -- DP distribute: g_nof_input --> g_nof_output
- ------------------------------------------------------------------------------
-
- u_distribute : entity dp_lib.dp_distribute
- generic map (
- g_technology => g_technology,
- -- Distribution IO
- g_tx => false,
- g_nof_input => g_nof_input,
- g_nof_output => g_nof_output,
- g_transpose => false,
- g_code_channel_lo => true,
- g_data_w => g_packet_data_w,
- -- Scheduling
- g_rx_mux_mode => g_mux_mode, -- default 0 for non-blocking mux, but 1 also works in simulation and on hardware provided that the inputs are garantueed to arrive
- -- Input FIFO
- g_use_fifo => false
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => pkt_siso_arr,
- snk_in_arr => pkt_sosi_arr,
- -- ST source
- src_in_arr => dist_siso_arr,
- src_out_arr => dist_sosi_arr
- );
------------------------------------------------------------------------------
-- Output FIFO (g_output_use_fifo)
@@ -218,27 +218,27 @@ begin
-- Output FIFO passes DP packets, so the sosi control fields (sync, bsn, empty, channel and error) are encoded in the packet data.
-- However if g_use_uth_err=TRUE then the Uthernet CRC error status is passed on via the sosi error field using 1 bit.
u_fifo_fill : entity dp_lib.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_data_w => g_packet_data_w,
- g_error_w => c_uth_crc_err_w, -- = 1, one bit CRC error status from uth_rx
- g_use_error => g_use_uth_err,
- g_use_channel => false, -- FALSE because c_packet_channel_lo is coded in the CHAN field of the DP packet data
- g_fifo_fill => g_output_fifo_fill,
- g_fifo_af_margin => g_output_fifo_af_margin,
- g_fifo_size => g_output_fifo_size,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => dist_siso_arr(I),
- snk_in => dist_sosi_arr(I),
- -- ST source
- src_in => out_siso_arr(I),
- src_out => out_sosi_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_packet_data_w,
+ g_error_w => c_uth_crc_err_w, -- = 1, one bit CRC error status from uth_rx
+ g_use_error => g_use_uth_err,
+ g_use_channel => false, -- FALSE because c_packet_channel_lo is coded in the CHAN field of the DP packet data
+ g_fifo_fill => g_output_fifo_fill,
+ g_fifo_af_margin => g_output_fifo_af_margin,
+ g_fifo_size => g_output_fifo_size,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => dist_siso_arr(I),
+ snk_in => dist_sosi_arr(I),
+ -- ST source
+ src_in => out_siso_arr(I),
+ src_out => out_sosi_arr(I)
+ );
end generate;
end generate;
@@ -248,23 +248,23 @@ begin
gen_output : for I in g_nof_output - 1 downto 0 generate
u_dec : entity dp_lib.dp_packet_dec
- generic map (
- g_data_w => g_packet_data_w,
- g_channel_lo => c_packet_channel_lo,
- g_phy_err_bi => g_uth_err_bi,
- g_use_phy_err => g_use_uth_err,
- g_use_this_siso => true -- default use TRUE for best throughput performance
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => out_siso_arr(I),
- snk_in => out_sosi_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_data_arr(I)
- );
+ generic map (
+ g_data_w => g_packet_data_w,
+ g_channel_lo => c_packet_channel_lo,
+ g_phy_err_bi => g_uth_err_bi,
+ g_use_phy_err => g_use_uth_err,
+ g_use_this_siso => true -- default use TRUE for best throughput performance
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => out_siso_arr(I),
+ snk_in => out_sosi_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_data_arr(I)
+ );
end generate;
------------------------------------------------------------------------------
diff --git a/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd b/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
index 9b177da33e..e1417042f2 100644
--- a/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
@@ -39,11 +39,11 @@
-- are then output without data not valid gaps during the packet.
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity uth_terminal_tx is
generic (
@@ -134,85 +134,85 @@ begin
gen_input_fifo : for I in g_nof_input - 1 downto 0 generate
gen_fifo : if g_input_use_fifo = true generate
u_fifo_fill : entity dp_lib.dp_fifo_fill
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => g_input_bsn_w,
+ g_empty_w => g_input_empty_w,
+ g_channel_w => g_input_channel_w,
+ g_error_w => g_input_error_w,
+ g_use_bsn => g_input_use_bsn,
+ g_use_empty => g_input_use_empty,
+ g_use_channel => g_input_use_channel,
+ g_use_error => g_input_use_error,
+ g_use_sync => g_input_use_sync,
+ g_fifo_fill => g_input_fifo_fill,
+ g_fifo_size => g_input_fifo_size,
+ g_fifo_af_margin => g_input_fifo_af_margin,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => sel_dat_sosi_arr(I),
+ -- ST source
+ src_in => in_siso_arr(I),
+ src_out => in_sosi_arr(I)
+ );
+ end generate;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- DP Packet encoder
+ ------------------------------------------------------------------------------
+ gen_input : for I in g_nof_input - 1 downto 0 generate
+ u_enc : entity dp_lib.dp_packet_enc
generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => g_input_bsn_w,
- g_empty_w => g_input_empty_w,
- g_channel_w => g_input_channel_w,
- g_error_w => g_input_error_w,
- g_use_bsn => g_input_use_bsn,
- g_use_empty => g_input_use_empty,
- g_use_channel => g_input_use_channel,
- g_use_error => g_input_use_error,
- g_use_sync => g_input_use_sync,
- g_fifo_fill => g_input_fifo_fill,
- g_fifo_size => g_input_fifo_size,
- g_fifo_af_margin => g_input_fifo_af_margin,
- g_fifo_rl => 1
+ g_data_w => g_packet_data_w,
+ g_channel_lo => c_packet_channel_lo
)
port map (
rst => rst,
clk => clk,
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => sel_dat_sosi_arr(I),
+ -- ST sinks
+ snk_out => in_siso_arr(I),
+ snk_in => in_sosi_arr(I),
-- ST source
- src_in => in_siso_arr(I),
- src_out => in_sosi_arr(I)
+ src_in => pkt_siso_arr(I),
+ src_out => pkt_sosi_arr(I)
);
- end generate;
end generate;
------------------------------------------------------------------------------
- -- DP Packet encoder
+ -- DP distribute: g_nof_input --> g_nof_output
------------------------------------------------------------------------------
- gen_input : for I in g_nof_input - 1 downto 0 generate
- u_enc : entity dp_lib.dp_packet_enc
+ u_distribute : entity dp_lib.dp_distribute
generic map (
- g_data_w => g_packet_data_w,
- g_channel_lo => c_packet_channel_lo
+ g_technology => g_technology,
+ -- Distribution IO
+ g_tx => true,
+ g_nof_input => g_nof_input,
+ g_nof_output => g_nof_output,
+ g_transpose => false,
+ g_code_channel_lo => true,
+ g_data_w => g_packet_data_w,
+ -- Scheduling
+ g_tx_mux_mode => g_mux_mode, -- default 0 for non-blocking mux, but 1 also works in simulation and on hardware provided that the inputs are garantueed to arrive
+ -- Input FIFO
+ g_use_fifo => false
)
port map (
- rst => rst,
- clk => clk,
+ rst => rst,
+ clk => clk,
-- ST sinks
- snk_out => in_siso_arr(I),
- snk_in => in_sosi_arr(I),
+ snk_out_arr => pkt_siso_arr,
+ snk_in_arr => pkt_sosi_arr,
-- ST source
- src_in => pkt_siso_arr(I),
- src_out => pkt_sosi_arr(I)
+ src_in_arr => dist_siso_arr,
+ src_out_arr => dist_sosi_arr
);
- end generate;
-
- ------------------------------------------------------------------------------
- -- DP distribute: g_nof_input --> g_nof_output
- ------------------------------------------------------------------------------
- u_distribute : entity dp_lib.dp_distribute
- generic map (
- g_technology => g_technology,
- -- Distribution IO
- g_tx => true,
- g_nof_input => g_nof_input,
- g_nof_output => g_nof_output,
- g_transpose => false,
- g_code_channel_lo => true,
- g_data_w => g_packet_data_w,
- -- Scheduling
- g_tx_mux_mode => g_mux_mode, -- default 0 for non-blocking mux, but 1 also works in simulation and on hardware provided that the inputs are garantueed to arrive
- -- Input FIFO
- g_use_fifo => false
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => pkt_siso_arr,
- snk_in_arr => pkt_sosi_arr,
- -- ST source
- src_in_arr => dist_siso_arr,
- src_out_arr => dist_sosi_arr
- );
------------------------------------------------------------------------------
-- UTHernet transmitter
@@ -220,21 +220,21 @@ begin
gen_output : for I in g_nof_output - 1 downto 0 generate
--u_uth_tx : ENTITY work.uth_tx(rtl_delay) -- requires using g_fifo_af_margin >= 10
u_uth_tx : entity work.uth_tx(rtl_hold) -- can use default g_fifo_af_margin >= 4
- generic map (
- g_data_w => g_packet_data_w,
- g_nof_ch => g_uth_nof_ch, -- g_nof_ch, the channels are numbered from 0 TO g_nof_ch-1, each channel represents a type of UTH frame
- g_typ_arr => g_uth_typ_arr -- g_nof_ch number of TLEN type values indexed by sink input channel, use unconstraint type to allow generic g_nof_ch
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => dist_siso_arr(I),
- snk_in => dist_sosi_arr(I),
- -- ST source
- src_in => out_siso_arr(I),
- src_out => out_sosi_arr(I)
- );
+ generic map (
+ g_data_w => g_packet_data_w,
+ g_nof_ch => g_uth_nof_ch, -- g_nof_ch, the channels are numbered from 0 TO g_nof_ch-1, each channel represents a type of UTH frame
+ g_typ_arr => g_uth_typ_arr -- g_nof_ch number of TLEN type values indexed by sink input channel, use unconstraint type to allow generic g_nof_ch
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => dist_siso_arr(I),
+ snk_in => dist_sosi_arr(I),
+ -- ST source
+ src_in => out_siso_arr(I),
+ src_out => out_sosi_arr(I)
+ );
end generate;
------------------------------------------------------------------------------
@@ -249,24 +249,24 @@ begin
gen_fifo : if g_output_use_fifo = true generate
-- Output FIFO passes DP/Uthernet packets, so the sosi control fields (sync, bsn, empty, channel and error) are encoded in the packet data
u_fifo_fill : entity dp_lib.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_data_w => g_packet_data_w,
- g_fifo_fill => g_output_fifo_fill,
- g_fifo_size => g_output_fifo_size,
- g_fifo_af_margin => g_output_fifo_af_margin,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => out_siso_arr(I),
- snk_in => out_sosi_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_packet_data_w,
+ g_fifo_fill => g_output_fifo_fill,
+ g_fifo_size => g_output_fifo_size,
+ g_fifo_af_margin => g_output_fifo_af_margin,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => out_siso_arr(I),
+ snk_in => out_sosi_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
end generate;
end str;
diff --git a/libraries/base/uth/src/vhdl/uth_tx.vhd b/libraries/base/uth/src/vhdl/uth_tx.vhd
index e06f41ba99..3eebe85573 100644
--- a/libraries/base/uth/src/vhdl/uth_tx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_tx.vhd
@@ -20,107 +20,107 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.uth_pkg.all;
-
--- Purpose: Assemble an UTH frame for a data block.
--- Usage:
--- This entity has two architectures:
---
--- . rtl_delay <== better not use this one
--- . rtl_hold <== PREFERRED
---
--- Remarks:
--- . Both architectures verify correct with tb_uth and tb_tb_uth.
--- . In addition an architecture rtl_adapt could have been made, that would
--- use p_state and an RL 2->1 adapter similar as for uth_rx, but that has
--- not been done, because having rtl_hold is sufficient.
---
--- Description:
---
--- Pass on the block of input data:
---
--- -----------------------
--- | data ... |
--- -----------------------
--- sop eop
--- val val ... val
---
--- into an output UTH frame:
---
--- ------------------------------------------------
--- idle | pre | sfd | tlen | data ... | crc | idle ...
--- ------------------------------------------------
--- sop eop
--- val val val val ... val
---
--- The uth_rx does the reverse.
---
--- . The input data is a block of data marked by in_sop and in_eop. If the PHY
--- supports out_val then the input block may have gaps where in_val is '0'
--- else the in_val has to remain active during the block. The minimum block
--- size is 1 data word, whereby the valid, sop and eop are all active.
--- . The uth_tx does support backpressure from the downstream sink.
--- . The uth_tx does give backpressure to the up stream source. If the up
--- stream source does not support the ready then it this can be handled by
--- placing a dp_latency_adapter in between.
--- . If the down stream sink is always ready then uth_tx can continuously
--- output UTH frames, i.e. out_sop directly after out_eop, if sufficient
--- input data blocks are provided.
--- . After the in_sop the uth_tx first outputs the preamble, the sfd (start of
--- frame delimiter) and the tlen (type or length) words.
--- . If the tlen word represents a length then its value must match the nof
--- input data words in a block, because then uth_rx will interpret it as UTH
--- payload length. Hence the tlen length must be known and fixed, it is not
--- dynamically derived from in_sop, in_val and in_eop, because that would
--- require some block store and forward buffering.
--- . Else if the tlen word represents a type, then it can have an arbitrary
--- value, because then uth_rx will know the fixed length that corresponds to
--- that UTH type. Typically the UTH type value should be larger than the
--- largest supported UTH length value, to support both on the same PHY link.
--- . The g_data_w is the width of the PHY link, so typically 16, 32 or 64 bit
--- for transceivers, 256 bit for DDR3. The user input data width must be
--- <= g_data_w, if necessary the input data words get resized.
--- . The internal CRC calculation uses the width c_crc_w. The c_crc_w is derived
--- from g_data_w by func_uth_crc_w() in uth_pkg.vhd. The CRC polynomial can
--- be 8, 16, 32 or 64 bit.
--- . The preamble word just before the sfd is also marked valid and indicated by
--- the out_sop to ensure that there is at least one preamble word between UTH
--- frames. The original intention was to send idle = preamble words between
--- UTH frames, but instead now the uth_tx puts in arbitriary idle words, with
--- out_val = '0' between UTH frames. It is allowed to use idle = preamble,
--- but not using the preamble word between frames decreases the chance on a
--- false sfd detection even more.
--- . The out_val, out_sop and out_eop signals are available to ease subsequent
--- UTH frame scheduling, but they do not have to be used on the actual PHY
--- link.
---
--- Design steps:
--- 1) First made uth_tx, because it is needed to test this uth_rx.
--- 2) ARCHITECTURE rtl_delay:
--- As a first step this uth_rx was implemented based on snk_in.valid and not
--- taking account of src_in.ready, because that is easier. However the fact
--- that this uth_tx has more output data than input data, due to the header
--- overhead makes the use of the RL 6 -> 1 latency adapter less trivial. A
--- way arround this would have been to use a state machine instead of
--- p_frame similar as the state machine in uth_rx(rtl_adapt). The state
--- machine then controls snk_out.ready to stop further input during the
--- overhead insertion and a RL 2 -> 1 latency adapter is then sufficient.
--- can have two valid data after src_in.ready went low, so this then needs
--- to be accounted for by using a RL 2 -> 1 latency adapter, similar as in
--- uth_rx(rtl_adapt).
--- 3) For testing the tb_uth.vhd is used using fixed streaming control.
--- 4) Made uth_rx to be able to test a complete UTH communication link, and
--- included random streaming control.
--- 5) ARCHITECTURE rtl_hold:
--- The RL 2 -> 1 latency adapter at the output was 'replaced' by a
--- dp_hold_input at the input. The p_state machine now maintains the RL = 1
--- by using the outputs from the dp_hold_input.
--- 6) Added duty-cycle pulse streaming control to tb_uth to be able to better
--- test uth_tx(rtl_delay).
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.uth_pkg.all;
+
+ -- Purpose: Assemble an UTH frame for a data block.
+ -- Usage:
+ -- This entity has two architectures:
+ --
+ -- . rtl_delay <== better not use this one
+ -- . rtl_hold <== PREFERRED
+ --
+ -- Remarks:
+ -- . Both architectures verify correct with tb_uth and tb_tb_uth.
+ -- . In addition an architecture rtl_adapt could have been made, that would
+ -- use p_state and an RL 2->1 adapter similar as for uth_rx, but that has
+ -- not been done, because having rtl_hold is sufficient.
+ --
+ -- Description:
+ --
+ -- Pass on the block of input data:
+ --
+ -- -----------------------
+ -- | data ... |
+ -- -----------------------
+ -- sop eop
+ -- val val ... val
+ --
+ -- into an output UTH frame:
+ --
+ -- ------------------------------------------------
+ -- idle | pre | sfd | tlen | data ... | crc | idle ...
+ -- ------------------------------------------------
+ -- sop eop
+ -- val val val val ... val
+ --
+ -- The uth_rx does the reverse.
+ --
+ -- . The input data is a block of data marked by in_sop and in_eop. If the PHY
+ -- supports out_val then the input block may have gaps where in_val is '0'
+ -- else the in_val has to remain active during the block. The minimum block
+ -- size is 1 data word, whereby the valid, sop and eop are all active.
+ -- . The uth_tx does support backpressure from the downstream sink.
+ -- . The uth_tx does give backpressure to the up stream source. If the up
+ -- stream source does not support the ready then it this can be handled by
+ -- placing a dp_latency_adapter in between.
+ -- . If the down stream sink is always ready then uth_tx can continuously
+ -- output UTH frames, i.e. out_sop directly after out_eop, if sufficient
+ -- input data blocks are provided.
+ -- . After the in_sop the uth_tx first outputs the preamble, the sfd (start of
+ -- frame delimiter) and the tlen (type or length) words.
+ -- . If the tlen word represents a length then its value must match the nof
+ -- input data words in a block, because then uth_rx will interpret it as UTH
+ -- payload length. Hence the tlen length must be known and fixed, it is not
+ -- dynamically derived from in_sop, in_val and in_eop, because that would
+ -- require some block store and forward buffering.
+ -- . Else if the tlen word represents a type, then it can have an arbitrary
+ -- value, because then uth_rx will know the fixed length that corresponds to
+ -- that UTH type. Typically the UTH type value should be larger than the
+ -- largest supported UTH length value, to support both on the same PHY link.
+ -- . The g_data_w is the width of the PHY link, so typically 16, 32 or 64 bit
+ -- for transceivers, 256 bit for DDR3. The user input data width must be
+ -- <= g_data_w, if necessary the input data words get resized.
+ -- . The internal CRC calculation uses the width c_crc_w. The c_crc_w is derived
+ -- from g_data_w by func_uth_crc_w() in uth_pkg.vhd. The CRC polynomial can
+ -- be 8, 16, 32 or 64 bit.
+ -- . The preamble word just before the sfd is also marked valid and indicated by
+ -- the out_sop to ensure that there is at least one preamble word between UTH
+ -- frames. The original intention was to send idle = preamble words between
+ -- UTH frames, but instead now the uth_tx puts in arbitriary idle words, with
+ -- out_val = '0' between UTH frames. It is allowed to use idle = preamble,
+ -- but not using the preamble word between frames decreases the chance on a
+ -- false sfd detection even more.
+ -- . The out_val, out_sop and out_eop signals are available to ease subsequent
+ -- UTH frame scheduling, but they do not have to be used on the actual PHY
+ -- link.
+ --
+ -- Design steps:
+ -- 1) First made uth_tx, because it is needed to test this uth_rx.
+ -- 2) ARCHITECTURE rtl_delay:
+ -- As a first step this uth_rx was implemented based on snk_in.valid and not
+ -- taking account of src_in.ready, because that is easier. However the fact
+ -- that this uth_tx has more output data than input data, due to the header
+ -- overhead makes the use of the RL 6 -> 1 latency adapter less trivial. A
+ -- way arround this would have been to use a state machine instead of
+ -- p_frame similar as the state machine in uth_rx(rtl_adapt). The state
+ -- machine then controls snk_out.ready to stop further input during the
+ -- overhead insertion and a RL 2 -> 1 latency adapter is then sufficient.
+ -- can have two valid data after src_in.ready went low, so this then needs
+ -- to be accounted for by using a RL 2 -> 1 latency adapter, similar as in
+ -- uth_rx(rtl_adapt).
+ -- 3) For testing the tb_uth.vhd is used using fixed streaming control.
+ -- 4) Made uth_rx to be able to test a complete UTH communication link, and
+ -- included random streaming control.
+ -- 5) ARCHITECTURE rtl_hold:
+ -- The RL 2 -> 1 latency adapter at the output was 'replaced' by a
+ -- dp_hold_input at the input. The p_state machine now maintains the RL = 1
+ -- by using the outputs from the dp_hold_input.
+ -- 6) Added duty-cycle pulse streaming control to tb_uth to be able to better
+ -- test uth_tx(rtl_delay).
entity uth_tx is
generic (
@@ -275,35 +275,35 @@ begin
-- to avoid that p_state already receive a sop for next frame. The frm_siso.ready can be released again when the eop leaves
-- the RL adapter buffer (i.e. g_or_high=TRUE), because then it is free to buffer for the next UTH packet.
u_frm_ready : entity common_lib.common_switch
- generic map (
- g_rst_level => '1',
- g_priority_lo => false,
- g_or_high => true, -- combinatorially force out_level high
- g_and_low => true -- combinatorially force out_level low
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => adapt_sosi.eop,
- switch_low => snk_in_dly(0).eop,
- out_level => frm_siso.ready
- );
+ generic map (
+ g_rst_level => '1',
+ g_priority_lo => false,
+ g_or_high => true, -- combinatorially force out_level high
+ g_and_low => true -- combinatorially force out_level low
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => adapt_sosi.eop,
+ switch_low => snk_in_dly(0).eop,
+ out_level => frm_siso.ready
+ );
u_out_adapt : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => c_out_rl_max,
- g_out_latency => g_out_rl
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => adapt_siso,
- snk_in => frm_sosi,
- -- ST source
- src_in => src_in,
- src_out => adapt_sosi
- );
+ generic map (
+ g_in_latency => c_out_rl_max,
+ g_out_latency => g_out_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => adapt_siso,
+ snk_in => frm_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => adapt_sosi
+ );
end rtl_delay;
architecture rtl_hold of uth_tx is
@@ -360,18 +360,18 @@ begin
nxt_src_buf <= next_src_buf;
u_hold : entity dp_lib.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in,
- -- ST source
- src_in => hold_src_in,
- next_src_out => next_src_buf,
- pend_src_out => pend_src_buf,
- src_out_reg => src_buf
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in,
+ -- ST source
+ src_in => hold_src_in,
+ next_src_out => next_src_buf,
+ pend_src_out => pend_src_buf,
+ src_out_reg => src_buf
+ );
-- Determine tlen
tx_tlen_index <= TO_UINT(pend_src_buf.channel(c_channel_w - 1 downto 0)) when g_nof_ch > 1 else 0;
diff --git a/libraries/base/uth/tb/vhdl/tb_tb_tb_uth_regression.vhd b/libraries/base/uth/tb/vhdl/tb_tb_tb_uth_regression.vhd
index 09a01aca47..cbc310fa1a 100644
--- a/libraries/base/uth/tb/vhdl/tb_tb_tb_uth_regression.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_tb_tb_uth_regression.vhd
@@ -29,7 +29,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_tb_uth_regression is
end tb_tb_tb_uth_regression;
diff --git a/libraries/base/uth/tb/vhdl/tb_tb_uth.vhd b/libraries/base/uth/tb/vhdl/tb_tb_uth.vhd
index 587b343f21..48b48f74d7 100644
--- a/libraries/base/uth/tb/vhdl/tb_tb_uth.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_tb_uth.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
--- as 10
--- run -all
+ -- as 10
+ -- run -all
entity tb_tb_uth is
end tb_tb_uth;
diff --git a/libraries/base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd b/libraries/base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd
index 772792144e..893ddc34f0 100644
--- a/libraries/base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
--- as 2
--- run -all
+ -- as 2
+ -- run -all
entity tb_tb_uth_dp_packet is
end tb_tb_uth_dp_packet;
diff --git a/libraries/base/uth/tb/vhdl/tb_tb_uth_terminals.vhd b/libraries/base/uth/tb/vhdl/tb_tb_uth_terminals.vhd
index ee5ed3ed22..c3150a0eed 100644
--- a/libraries/base/uth/tb/vhdl/tb_tb_uth_terminals.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_tb_uth_terminals.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
--- as 2
--- run -all
+ -- as 2
+ -- run -all
entity tb_tb_uth_terminals is
end tb_tb_uth_terminals;
diff --git a/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd b/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
index 3c5cf552cd..6a698810c4 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
@@ -36,14 +36,14 @@
-- Remark:
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_packet_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_packet_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_uth_terminals is
generic (
@@ -274,40 +274,40 @@ begin
-- n --> m
tx : entity work.uth_terminal_tx
- generic map (
- -- Terminal IO
- g_nof_input => g_nof_input,
- g_nof_output => g_nof_serial,
- -- . DP Packet
- g_data_w => c_data_w,
- g_packet_data_w => c_data_w,
- -- . Uthernet
- g_uth_nof_ch => c_uth_nof_ch,
- g_uth_typ_ofs => c_uth_typ_ofs,
- g_uth_typ_arr => c_uth_typ_arr,
- -- Input FIFO
- g_input_use_fifo => g_tx_use_fifo,
- g_input_bsn_w => c_bsn_w,
- g_input_channel_w => c_channel_w,
- g_input_use_bsn => c_use_bsn,
- g_input_use_channel => c_use_channel,
- g_input_use_sync => c_use_sync,
- g_input_fifo_af_margin => c_fifo_af_margin,
- g_input_fifo_fill => g_tx_fifo_fill,
- g_input_fifo_size => c_fifo_size,
- -- Output FIFO
- g_output_use_fifo => false
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_in_arr => tx_serial_siso_arr,
- src_out_arr => tx_serial_sosi_arr
- );
+ generic map (
+ -- Terminal IO
+ g_nof_input => g_nof_input,
+ g_nof_output => g_nof_serial,
+ -- . DP Packet
+ g_data_w => c_data_w,
+ g_packet_data_w => c_data_w,
+ -- . Uthernet
+ g_uth_nof_ch => c_uth_nof_ch,
+ g_uth_typ_ofs => c_uth_typ_ofs,
+ g_uth_typ_arr => c_uth_typ_arr,
+ -- Input FIFO
+ g_input_use_fifo => g_tx_use_fifo,
+ g_input_bsn_w => c_bsn_w,
+ g_input_channel_w => c_channel_w,
+ g_input_use_bsn => c_use_bsn,
+ g_input_use_channel => c_use_channel,
+ g_input_use_sync => c_use_sync,
+ g_input_fifo_af_margin => c_fifo_af_margin,
+ g_input_fifo_fill => g_tx_fifo_fill,
+ g_input_fifo_size => c_fifo_size,
+ -- Output FIFO
+ g_output_use_fifo => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_in_arr => tx_serial_siso_arr,
+ src_out_arr => tx_serial_sosi_arr
+ );
-- Model PHY link by a FIFO
no_phy_fifo : if g_phy_fifo_size = 0 generate
@@ -318,73 +318,73 @@ begin
gen_phy_fifo : if g_phy_fifo_size > 0 generate
gen_nof_serial : for I in 0 to g_nof_serial - 1 generate
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
- generic map (
- g_data_w => c_data_w,
- g_bsn_w => 1,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_bsn => false,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_sync => false,
- g_use_ctrl => false,
- g_use_complex => false,
- g_fifo_size => g_phy_fifo_size,
- g_fifo_af_margin => 4,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor FIFO filling
- wr_ful => OPEN,
- usedw => OPEN,
- rd_emp => OPEN,
- -- ST sink
- snk_out => tx_serial_siso_arr(I),
- snk_in => tx_serial_sosi_arr(I),
- -- ST source
- src_in => rx_serial_siso_arr(I),
- src_out => rx_serial_sosi_arr(I)
- );
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => 1,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_bsn => false,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_sync => false,
+ g_use_ctrl => false,
+ g_use_complex => false,
+ g_fifo_size => g_phy_fifo_size,
+ g_fifo_af_margin => 4,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => OPEN,
+ usedw => OPEN,
+ rd_emp => OPEN,
+ -- ST sink
+ snk_out => tx_serial_siso_arr(I),
+ snk_in => tx_serial_sosi_arr(I),
+ -- ST source
+ src_in => rx_serial_siso_arr(I),
+ src_out => rx_serial_sosi_arr(I)
+ );
end generate;
end generate;
-- m --> n
rx : entity work.uth_terminal_rx
- generic map (
- -- Terminal IO
- g_nof_input => g_nof_serial,
- g_nof_output => g_nof_input,
- -- . DP Packet
- g_data_w => c_data_w,
- g_packet_data_w => c_data_w,
- -- . Uthernet
- g_uth_nof_ch => c_uth_nof_ch,
- g_uth_len_max => c_uth_len_max,
- g_uth_typ_arr => c_uth_typ_arr,
- g_uth_len_arr => c_uth_len_arr,
- g_use_uth_err => false,
- g_uth_err_bi => 0,
- g_uth_timeout_w => g_uth_rx_timeout_w,
- -- Input FIFO
- g_input_use_fifo => g_rx_use_fifo,
- g_input_fifo_af_margin => c_fifo_af_margin,
- g_input_fifo_fill => g_rx_fifo_fill,
- g_input_fifo_size => c_fifo_size,
- -- Output FIFO
- g_output_use_fifo => false
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => rx_serial_siso_arr,
- snk_in_arr => rx_serial_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ -- Terminal IO
+ g_nof_input => g_nof_serial,
+ g_nof_output => g_nof_input,
+ -- . DP Packet
+ g_data_w => c_data_w,
+ g_packet_data_w => c_data_w,
+ -- . Uthernet
+ g_uth_nof_ch => c_uth_nof_ch,
+ g_uth_len_max => c_uth_len_max,
+ g_uth_typ_arr => c_uth_typ_arr,
+ g_uth_len_arr => c_uth_len_arr,
+ g_use_uth_err => false,
+ g_uth_err_bi => 0,
+ g_uth_timeout_w => g_uth_rx_timeout_w,
+ -- Input FIFO
+ g_input_use_fifo => g_rx_use_fifo,
+ g_input_fifo_af_margin => c_fifo_af_margin,
+ g_input_fifo_fill => g_rx_fifo_fill,
+ g_input_fifo_size => c_fifo_size,
+ -- Output FIFO
+ g_output_use_fifo => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => rx_serial_siso_arr,
+ snk_in_arr => rx_serial_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/util/src/vhdl/util_heater.vhd b/libraries/base/util/src/vhdl/util_heater.vhd
index 14ca41286e..63e3c59e87 100644
--- a/libraries/base/util/src/vhdl/util_heater.vhd
+++ b/libraries/base/util/src/vhdl/util_heater.vhd
@@ -21,36 +21,36 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use work.util_heater_pkg.all;
-
--- Purpose:
--- Use multiplier DSP elements, RAM and logic in an FPGA to heat up the PFGA
--- to see how the FPGA behaves when it gets warm. This is useful to verify
--- whether the FPGA remains functional, especially its various external IO
--- interfaces (e.g. gigabit transceivers and DDR memory).
--- Desription:
--- The heater elements can be enabled or disabled via an MM register.
--- Each heater element consists of a MAC4. A MAC4 uses 4 18x18 multipliers.
--- The MAC4 inputs are random so: mac4 = r0r1 + r1r2 + r2r3+ r3r0. For
--- g_pipeline > 0 the output data gets pipelined to use more logic. For
--- g_nof_ram > the output data is put through a FIFO to use more RAM. The
--- final output data gets XOR-ed to get a single bit value that can be read
--- via the same MM register. The read value is not relevant, but the read
--- access connection ensures that the heater element logic will not be
--- optimized away by synthesis.
--- The number of heater elements can be set via g_nof_mac4. The MM register
--- allows enabling 0, 1, more or all MAC4 under SW control. In this way it
--- is possible to vary the power consumption during run time.
--- Using common_pipeline.vhd to invoke logic can get implemented in RAM
--- blocks for larger pipeline settings. Therefor g_nof_logic to instantiate
--- util_logic stages to enforce using logic (LUTs and FF).
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use work.util_heater_pkg.all;
+
+ -- Purpose:
+ -- Use multiplier DSP elements, RAM and logic in an FPGA to heat up the PFGA
+ -- to see how the FPGA behaves when it gets warm. This is useful to verify
+ -- whether the FPGA remains functional, especially its various external IO
+ -- interfaces (e.g. gigabit transceivers and DDR memory).
+ -- Desription:
+ -- The heater elements can be enabled or disabled via an MM register.
+ -- Each heater element consists of a MAC4. A MAC4 uses 4 18x18 multipliers.
+ -- The MAC4 inputs are random so: mac4 = r0r1 + r1r2 + r2r3+ r3r0. For
+ -- g_pipeline > 0 the output data gets pipelined to use more logic. For
+ -- g_nof_ram > the output data is put through a FIFO to use more RAM. The
+ -- final output data gets XOR-ed to get a single bit value that can be read
+ -- via the same MM register. The read value is not relevant, but the read
+ -- access connection ensures that the heater element logic will not be
+ -- optimized away by synthesis.
+ -- The number of heater elements can be set via g_nof_mac4. The MM register
+ -- allows enabling 0, 1, more or all MAC4 under SW control. In this way it
+ -- is possible to vary the power consumption during run time.
+ -- Using common_pipeline.vhd to invoke logic can get implemented in RAM
+ -- blocks for larger pipeline settings. Therefor g_nof_logic to instantiate
+ -- util_logic stages to enforce using logic (LUTs and FF).
entity util_heater is
generic (
@@ -73,11 +73,12 @@ end;
architecture rtl of util_heater is
-- Use MM bus data width = c_word_w = 32
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => c_util_heater_reg_addr_w,
- dat_w => c_word_w,
- nof_dat => c_util_heater_reg_nof_words,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_util_heater_reg_addr_w,
+ dat_w => c_word_w,
+ nof_dat => c_util_heater_reg_nof_words,
+ init_sl => '0');
constant c_remote_len : natural := 5; -- >> 0 to ease timing to reach logic throughout the whole chip
constant c_sync_delay_len : natural := c_meta_delay_len + c_remote_len; -- >= c_meta_delay_len=3
@@ -150,25 +151,25 @@ begin
-- MM clock domain
------------------------------------------------------------------------------
u_mm_reg : entity common_lib.common_reg_r_w
- generic map (
- g_reg => c_mm_reg,
- g_init_reg => (others => '0')
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- control side
- wr_en => sla_in.wr,
- wr_adr => sla_in.address(c_mm_reg.adr_w - 1 downto 0),
- wr_dat => sla_in.wrdata(c_mm_reg.dat_w - 1 downto 0),
- rd_en => sla_in.rd,
- rd_adr => sla_in.address(c_mm_reg.adr_w - 1 downto 0),
- rd_dat => sla_out.rddata(c_mm_reg.dat_w - 1 downto 0),
- rd_val => OPEN,
- -- data side
- out_reg => mm_reg_en,
- in_reg => mm_reg_xor
- );
+ generic map (
+ g_reg => c_mm_reg,
+ g_init_reg => (others => '0')
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- control side
+ wr_en => sla_in.wr,
+ wr_adr => sla_in.address(c_mm_reg.adr_w - 1 downto 0),
+ wr_dat => sla_in.wrdata(c_mm_reg.dat_w - 1 downto 0),
+ rd_en => sla_in.rd,
+ rd_adr => sla_in.address(c_mm_reg.adr_w - 1 downto 0),
+ rd_dat => sla_out.rddata(c_mm_reg.dat_w - 1 downto 0),
+ rd_val => OPEN,
+ -- data side
+ out_reg => mm_reg_en,
+ in_reg => mm_reg_xor
+ );
mm_element_en <= mm_reg_en(mm_element_en'range);
mm_reg_xor(mm_element_xor'range) <= mm_element_xor;
@@ -184,29 +185,29 @@ begin
-- MM --> ST
u_cross_en : entity common_lib.common_async
- generic map (
- g_rst_level => '0',
- g_delay_len => c_sync_delay_len
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- din => mm_element_en(I),
- dout => st_element_en(I)
- );
+ generic map (
+ g_rst_level => '0',
+ g_delay_len => c_sync_delay_len
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ din => mm_element_en(I),
+ dout => st_element_en(I)
+ );
-- MM <-- ST
u_cross_xor : entity common_lib.common_async
- generic map (
- g_rst_level => '0',
- g_delay_len => c_sync_delay_len
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_element_xor(I),
- dout => mm_element_xor(I)
- );
+ generic map (
+ g_rst_level => '0',
+ g_delay_len => c_sync_delay_len
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_element_xor(I),
+ dout => mm_element_xor(I)
+ );
end generate;
------------------------------------------------------------------------------
@@ -240,56 +241,56 @@ begin
nxt_prsg_3 <= func_common_random(prsg_3);
u_prsg_0_reg : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_remote_len,
- g_in_dat_w => prsg_0'LENGTH,
- g_out_dat_w => prsg_0'length
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- in_dat => prsg_0,
- out_dat => prsg_0_reg
- );
+ generic map (
+ g_pipeline => c_remote_len,
+ g_in_dat_w => prsg_0'LENGTH,
+ g_out_dat_w => prsg_0'length
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ in_dat => prsg_0,
+ out_dat => prsg_0_reg
+ );
u_prsg_1_reg : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_remote_len,
- g_in_dat_w => prsg_1'LENGTH,
- g_out_dat_w => prsg_1'length
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- in_dat => prsg_1,
- out_dat => prsg_1_reg
- );
+ generic map (
+ g_pipeline => c_remote_len,
+ g_in_dat_w => prsg_1'LENGTH,
+ g_out_dat_w => prsg_1'length
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ in_dat => prsg_1,
+ out_dat => prsg_1_reg
+ );
u_prsg_2_reg : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_remote_len,
- g_in_dat_w => prsg_2'LENGTH,
- g_out_dat_w => prsg_2'length
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- in_dat => prsg_2,
- out_dat => prsg_2_reg
- );
+ generic map (
+ g_pipeline => c_remote_len,
+ g_in_dat_w => prsg_2'LENGTH,
+ g_out_dat_w => prsg_2'length
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ in_dat => prsg_2,
+ out_dat => prsg_2_reg
+ );
u_prsg_3_reg : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_remote_len,
- g_in_dat_w => prsg_3'LENGTH,
- g_out_dat_w => prsg_3'length
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- in_dat => prsg_3,
- out_dat => prsg_3_reg
- );
+ generic map (
+ g_pipeline => c_remote_len,
+ g_in_dat_w => prsg_3'LENGTH,
+ g_out_dat_w => prsg_3'length
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ in_dat => prsg_3,
+ out_dat => prsg_3_reg
+ );
------------------------------------------------------------------------------
-- Heater elements
@@ -311,38 +312,38 @@ begin
-- Complex multipliers, these should get mapped on DSP elements in the FPGA
u_dsp : entity common_mult_lib.common_mult_add4 -- (rtl)
- generic map (
- g_technology => g_technology,
- g_in_a_w => c_in_dat_w,
- g_in_b_w => c_in_dat_w,
- g_res_w => c_mac_out_dat_w,
- g_pipeline_input => c_mac_pipeline_input,
- g_pipeline_product => c_mac_pipeline_product,
- g_pipeline_adder => c_mac_pipeline_adder,
- g_pipeline_output => c_mac_pipeline_output
- )
- port map (
- clk => st_clk,
- clken => st_clken(I),
- in_a => in_dat_a(I),
- in_b => in_dat_b(I),
- res => mac4(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_in_a_w => c_in_dat_w,
+ g_in_b_w => c_in_dat_w,
+ g_res_w => c_mac_out_dat_w,
+ g_pipeline_input => c_mac_pipeline_input,
+ g_pipeline_product => c_mac_pipeline_product,
+ g_pipeline_adder => c_mac_pipeline_adder,
+ g_pipeline_output => c_mac_pipeline_output
+ )
+ port map (
+ clk => st_clk,
+ clken => st_clken(I),
+ in_a => in_dat_a(I),
+ in_b => in_dat_b(I),
+ res => mac4(I)
+ );
-- Pipeline, use g_pipeline > 0 to run some more logic resources or to ease achieving timing closure
u_logic : entity common_lib.common_pipeline
- generic map (
- g_pipeline => g_pipeline, -- use 0 for no logic, so only wires
- g_in_dat_w => c_mac_out_dat_w,
- g_out_dat_w => c_fifo_dat_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- clken => st_clken(I),
- in_dat => mac4(I),
- out_dat => fifo_in_dat(I)
- );
+ generic map (
+ g_pipeline => g_pipeline, -- use 0 for no logic, so only wires
+ g_in_dat_w => c_mac_out_dat_w,
+ g_out_dat_w => c_fifo_dat_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ clken => st_clken(I),
+ in_dat => mac4(I),
+ out_dat => fifo_in_dat(I)
+ );
----------------------------------------------------------------------------
-- RAM
@@ -351,23 +352,23 @@ begin
-- FIFO, use g_nof_ram > 0 to use RAM or g_nof_ram = 0 to bypass
gen_ram : if g_nof_ram > 0 generate
u_fifo : entity common_lib.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_dat_w => c_fifo_dat_w,
- g_nof_words => g_nof_ram * c_nof_fifo_dat_in_1kbyte_ram
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- wr_dat => fifo_in_dat(I),
- wr_req => st_clken(I),
- wr_ful => OPEN,
- rd_dat => fifo_out_dat(I),
- rd_req => st_clken(I),
- rd_emp => OPEN,
- rd_val => OPEN,
- usedw => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_nof_ram * c_nof_fifo_dat_in_1kbyte_ram
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ wr_dat => fifo_in_dat(I),
+ wr_req => st_clken(I),
+ wr_ful => OPEN,
+ rd_dat => fifo_out_dat(I),
+ rd_req => st_clken(I),
+ rd_emp => OPEN,
+ rd_val => OPEN,
+ usedw => open
+ );
end generate;
no_ram : if g_nof_ram = 0 generate
@@ -380,15 +381,15 @@ begin
gen_logic : if g_nof_logic > 0 generate
u_logic : entity work.util_logic
- generic map (
- g_nof_reg => g_nof_logic
- )
- port map (
- clk => st_clk,
- clken => st_clken(I),
- in_dat => fifo_out_dat(I),
- out_dat => logic_dat(I)
- );
+ generic map (
+ g_nof_reg => g_nof_logic
+ )
+ port map (
+ clk => st_clk,
+ clken => st_clken(I),
+ in_dat => fifo_out_dat(I),
+ out_dat => logic_dat(I)
+ );
end generate;
no_logic : if g_nof_logic = 0 generate
diff --git a/libraries/base/util/src/vhdl/util_heater_pkg.vhd b/libraries/base/util/src/vhdl/util_heater_pkg.vhd
index dae51ab7ab..e7bdf9d281 100644
--- a/libraries/base/util/src/vhdl/util_heater_pkg.vhd
+++ b/libraries/base/util/src/vhdl/util_heater_pkg.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package util_heater_pkg is
------------------------------------------------------------------------------
diff --git a/libraries/base/util/src/vhdl/util_logic.vhd b/libraries/base/util/src/vhdl/util_logic.vhd
index b50cc43071..da8032d650 100644
--- a/libraries/base/util/src/vhdl/util_logic.vhd
+++ b/libraries/base/util/src/vhdl/util_logic.vhd
@@ -29,7 +29,7 @@
-- feedback with XOR at every stage to enforce using logic (LUTs and FF).
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity util_logic is
generic (
diff --git a/libraries/base/util/tb/vhdl/tb_util_heater.vhd b/libraries/base/util/tb/vhdl/tb_util_heater.vhd
index 6441abf566..35cc76e5d2 100644
--- a/libraries/base/util/tb/vhdl/tb_util_heater.vhd
+++ b/libraries/base/util/tb/vhdl/tb_util_heater.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.util_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.util_heater_pkg.all;
entity tb_util_heater is
end tb_util_heater;
@@ -100,19 +100,19 @@ begin
end process;
dut : entity work.util_heater
- generic map (
- g_nof_mac4 => c_nof_mac4,
- g_pipeline => c_pipeline,
- g_nof_ram => c_nof_ram,
- g_nof_logic => c_nof_logic
- )
- port map (
- mm_rst => mm_rst, -- MM is the microprocessor control clock domain
- mm_clk => mm_clk,
- st_rst => st_rst, -- ST is the DSP clock domain
- st_clk => st_clk,
- -- Memory Mapped Slave
- sla_in => mm_mosi,
- sla_out => mm_miso
- );
+ generic map (
+ g_nof_mac4 => c_nof_mac4,
+ g_pipeline => c_pipeline,
+ g_nof_ram => c_nof_ram,
+ g_nof_logic => c_nof_logic
+ )
+ port map (
+ mm_rst => mm_rst, -- MM is the microprocessor control clock domain
+ mm_clk => mm_clk,
+ st_rst => st_rst, -- ST is the DSP clock domain
+ st_clk => st_clk,
+ -- Memory Mapped Slave
+ sla_in => mm_mosi,
+ sla_out => mm_miso
+ );
end tb;
diff --git a/libraries/dsp/beamformer/src/vhdl/beamformer.vhd b/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
index 25a30b681c..eb3277d18e 100644
--- a/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
+++ b/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
@@ -42,13 +42,13 @@
-- to TRUE.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib, common_mult_lib, technology_lib, dp_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity beamformer is
generic (
@@ -86,11 +86,12 @@ architecture str of beamformer is
------------------------------------------------------------------------------
-- Weights RAM
------------------------------------------------------------------------------
- constant c_common_ram_crw_crw_ram : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_weights),
- dat_w => c_nof_complex * g_weights_w,
- nof_dat => g_nof_weights,
- init_sl => '0');
+ constant c_common_ram_crw_crw_ram : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_weights),
+ dat_w => c_nof_complex * g_weights_w,
+ nof_dat => g_nof_weights,
+ init_sl => '0');
type t_common_ram_crw_crw_adr_b_arr is array(g_nof_inputs - 1 downto 0) of std_logic_vector(ceil_log2(g_nof_weights) - 1 downto 0);
type t_common_ram_crw_crw_rd_dat_b_arr is array(g_nof_inputs - 1 downto 0) of std_logic_vector(c_nof_complex * g_weights_w - 1 downto 0);
@@ -143,31 +144,31 @@ begin
-- Dual clock RAM
u_common_ram_crw_crw : entity common_lib.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => c_common_ram_crw_crw_ram,
- g_init_file => sel_a_b(g_weights_file = "UNUSED", "UNUSED", g_weights_file & "_" & natural'image(i) & ".hex"),
- g_true_dual_port => g_weights_ram_dual_port
- )
- port map (
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_mosi_arr(i).wr,
- wr_dat_a => ram_mosi_arr(i).wrdata(c_common_ram_crw_crw_ram.dat_w - 1 downto 0),
- adr_a => ram_mosi_arr(i).address(c_common_ram_crw_crw_ram.adr_w - 1 downto 0),
- rd_en_a => ram_mosi_arr(i).rd,
- rd_dat_a => ram_miso_arr(i).rddata(c_common_ram_crw_crw_ram.dat_w - 1 downto 0),
- rd_val_a => ram_miso_arr(i).rdval,
-
- rst_b => dp_rst,
- clk_b => dp_clk,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- adr_b => common_ram_crw_crw_adr_b_arr(i),
- rd_en_b => common_ram_crw_crw_rd_en_b_arr(i),
- rd_dat_b => common_ram_crw_crw_rd_dat_b_arr(i),
- rd_val_b => common_ram_crw_crw_rd_val_b_arr(i)
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_common_ram_crw_crw_ram,
+ g_init_file => sel_a_b(g_weights_file = "UNUSED", "UNUSED", g_weights_file & "_" & natural'image(i) & ".hex"),
+ g_true_dual_port => g_weights_ram_dual_port
+ )
+ port map (
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_mosi_arr(i).wr,
+ wr_dat_a => ram_mosi_arr(i).wrdata(c_common_ram_crw_crw_ram.dat_w - 1 downto 0),
+ adr_a => ram_mosi_arr(i).address(c_common_ram_crw_crw_ram.adr_w - 1 downto 0),
+ rd_en_a => ram_mosi_arr(i).rd,
+ rd_dat_a => ram_miso_arr(i).rddata(c_common_ram_crw_crw_ram.dat_w - 1 downto 0),
+ rd_val_a => ram_miso_arr(i).rdval,
+
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ adr_b => common_ram_crw_crw_adr_b_arr(i),
+ rd_en_b => common_ram_crw_crw_rd_en_b_arr(i),
+ rd_dat_b => common_ram_crw_crw_rd_dat_b_arr(i),
+ rd_val_b => common_ram_crw_crw_rd_val_b_arr(i)
+ );
-- RAM output rewired to SOSI array
common_ram_crw_crw_src_out_arr(i).re <= RESIZE_DP_DSP_DATA(common_ram_crw_crw_rd_dat_b_arr(i)( g_weights_w - 1 downto 0));
@@ -182,28 +183,28 @@ begin
gen_weight_reg : if g_use_weight_reg = true generate
gen_common_reg_r_w_dc : for i in 0 to g_nof_inputs - 1 generate
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => g_weights_ram_dual_port,
- g_reg => c_common_ram_crw_crw_ram
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => ram_mosi_arr(i),
- sla_out => ram_miso_arr(i),
-
- -- MM registers in st_clk domain
- reg_wr_arr => open,
- reg_rd_arr => open,
- in_reg => common_reg_r_w_dc_in_reg_slv_arr(i),
- out_reg => common_reg_r_w_dc_out_reg_slv_arr(i)
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => g_weights_ram_dual_port,
+ g_reg => c_common_ram_crw_crw_ram
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => ram_mosi_arr(i),
+ sla_out => ram_miso_arr(i),
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => open,
+ reg_rd_arr => open,
+ in_reg => common_reg_r_w_dc_in_reg_slv_arr(i),
+ out_reg => common_reg_r_w_dc_out_reg_slv_arr(i)
+ );
-- Rewire the concatenated SLV array to something we can index properly [g_nof_inputs][g_nof_weights]
gen_common_reg_r_w_dc_out_reg_2arr : for j in 0 to g_nof_weights - 1 generate
@@ -225,33 +226,33 @@ begin
-- Combine the individual MM buses into one
------------------------------------------------------------------------------
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_inputs,
- g_mult_addr_w => ceil_log2(g_nof_weights)
- )
- port map (
- mosi => ram_mosi,
- miso => ram_miso,
- mosi_arr => ram_mosi_arr,
- miso_arr => ram_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_inputs,
+ g_mult_addr_w => ceil_log2(g_nof_weights)
+ )
+ port map (
+ mosi => ram_mosi,
+ miso => ram_miso,
+ mosi_arr => ram_mosi_arr,
+ miso_arr => ram_miso_arr
+ );
------------------------------------------------------------------------------
-- Pipeline to align snk_in_arr with dp_ram_src_out_arr
------------------------------------------------------------------------------
u_dp_pipeline_arr : entity dp_lib.dp_pipeline_arr
- generic map(
- g_nof_streams => g_nof_inputs,
- g_pipeline => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map(
+ g_nof_streams => g_nof_inputs,
+ g_pipeline => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- snk_in_arr => snk_in_arr,
+ snk_in_arr => snk_in_arr,
- src_out_arr => dp_pipeline_arr_src_out_arr
- );
+ src_out_arr => dp_pipeline_arr_src_out_arr
+ );
------------------------------------------------------------------------------
-- Multiplier stage
@@ -262,34 +263,34 @@ begin
end generate;
u_dp_complex_mult : entity dp_lib.dp_complex_mult
- generic map (
- g_nof_multipliers => g_nof_inputs,
- g_data_w => g_data_w,
- g_variant => g_mult_variant
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
-
- snk_in_2arr_2 => dp_complex_mult_snk_in_2arr_2,
- src_out_arr => dp_complex_mult_src_out_arr
- );
+ generic map (
+ g_nof_multipliers => g_nof_inputs,
+ g_data_w => g_data_w,
+ g_variant => g_mult_variant
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in_2arr_2 => dp_complex_mult_snk_in_2arr_2,
+ src_out_arr => dp_complex_mult_src_out_arr
+ );
------------------------------------------------------------------------------
-- Adder stage
------------------------------------------------------------------------------
u_dp_complex_add : entity dp_lib.dp_complex_add
- generic map (
- g_nof_inputs => g_nof_inputs,
- g_data_w => 2 * g_data_w
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
-
- snk_in_arr => dp_complex_mult_src_out_arr,
- src_out => src_out
- );
+ generic map (
+ g_nof_inputs => g_nof_inputs,
+ g_data_w => 2 * g_data_w
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in_arr => dp_complex_mult_src_out_arr,
+ src_out => src_out
+ );
------------------------------------------------------------------------------
-- Registers
diff --git a/libraries/dsp/beamformer/tb/vhdl/tb_tb_beamformer.vhd b/libraries/dsp/beamformer/tb/vhdl/tb_tb_beamformer.vhd
index cea840d000..2846f7e7d6 100644
--- a/libraries/dsp/beamformer/tb/vhdl/tb_tb_beamformer.vhd
+++ b/libraries/dsp/beamformer/tb/vhdl/tb_tb_beamformer.vhd
@@ -27,7 +27,7 @@
-- .
library IEEE, common_lib, dp_lib, technology_lib, diag_lib, mm_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_beamformer is
end tb_tb_beamformer;
@@ -35,28 +35,28 @@ end tb_tb_beamformer;
architecture tb of tb_tb_beamformer is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- Usage
--- > as 8
--- > run -all
--- > Testbenches are self-checking
+ -- Usage
+ -- > as 8
+ -- > run -all
+ -- > Testbenches are self-checking
---
--- g_tb_index : NATURAL := 0; -- use different index to avoid MM file conflict in multi tb
--- --g_technology : NATURAL := c_tech_select_default;
--- g_nof_inputs : NATURAL := 2;
--- g_nof_weights : NATURAL := 32;
--- g_data_w : NATURAL := 8; --8b complex input data
--- g_use_weight_ram : BOOLEAN := FALSE;
--- g_use_weight_reg : BOOLEAN := TRUE
---
+ --
+ -- g_tb_index : NATURAL := 0; -- use different index to avoid MM file conflict in multi tb
+ -- --g_technology : NATURAL := c_tech_select_default;
+ -- g_nof_inputs : NATURAL := 2;
+ -- g_nof_weights : NATURAL := 32;
+ -- g_data_w : NATURAL := 8; --8b complex input data
+ -- g_use_weight_ram : BOOLEAN := FALSE;
+ -- g_use_weight_reg : BOOLEAN := TRUE
+ --
--- do test for different number of inputs
--- . (weights in RAM)
-sim_i01_ram_beamformer : entity work.tb_beamformer generic map (1, 1, 32, 8, true, false);
-sim_i02_ram_beamformer : entity work.tb_beamformer generic map (2, 2, 32, 8, true, false);
-sim_i32_ram_beamformer : entity work.tb_beamformer generic map (3, 32, 32, 8, true, false);
--- . (weights in Registers)
-sim_i01_reg_beamformer : entity work.tb_beamformer generic map (4, 1, 32, 8, false, true);
-sim_i02_reg_beamformer : entity work.tb_beamformer generic map (5, 2, 32, 8, false, true);
-sim_i32_reg_beamformer : entity work.tb_beamformer generic map (6, 32, 32, 8, false, true);
+ -- do test for different number of inputs
+ -- . (weights in RAM)
+ sim_i01_ram_beamformer : entity work.tb_beamformer generic map (1, 1, 32, 8, true, false);
+ sim_i02_ram_beamformer : entity work.tb_beamformer generic map (2, 2, 32, 8, true, false);
+ sim_i32_ram_beamformer : entity work.tb_beamformer generic map (3, 32, 32, 8, true, false);
+ -- . (weights in Registers)
+ sim_i01_reg_beamformer : entity work.tb_beamformer generic map (4, 1, 32, 8, false, true);
+ sim_i02_reg_beamformer : entity work.tb_beamformer generic map (5, 2, 32, 8, false, true);
+ sim_i32_reg_beamformer : entity work.tb_beamformer generic map (6, 32, 32, 8, false, true);
end tb;
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
index d9fa0804e7..67305fc628 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
@@ -20,22 +20,22 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, bf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use bf_lib.bf_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use bf_lib.bf_pkg.all;
entity mmm_unb1_fn_bf is
generic (
@@ -173,56 +173,72 @@ begin
i_tse_clk <= not i_tse_clk after c_tse_clk_period / 2;
eth1g_mm_rst <= '1', '0' after c_tse_clk_period * 5;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_diagnostics : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
- port map(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
+ u_mm_file_reg_diagnostics : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
+ port map(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
- u_mm_file_reg_dp_ram_from_mm : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_RAM_FROM_MM")
- port map(mm_rst, i_mm_clk, reg_dp_ram_from_mm_mosi, reg_dp_ram_from_mm_miso );
+ u_mm_file_reg_dp_ram_from_mm : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_RAM_FROM_MM")
+ port map(mm_rst, i_mm_clk, reg_dp_ram_from_mm_mosi, reg_dp_ram_from_mm_miso );
- u_mm_file_ram_dp_ram_from_mm : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DP_RAM_FROM_MM")
- port map(mm_rst, i_mm_clk, ram_dp_ram_from_mm_mosi, ram_dp_ram_from_mm_miso );
+ u_mm_file_ram_dp_ram_from_mm : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DP_RAM_FROM_MM")
+ port map(mm_rst, i_mm_clk, ram_dp_ram_from_mm_mosi, ram_dp_ram_from_mm_miso );
--- u_mm_file_ram_dp_ram_to_mm : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DP_RAM_TO_MM")
--- PORT MAP(mm_rst, i_mm_clk, ram_dp_ram_to_mm_mosi, ram_dp_ram_to_mm_miso );
+ -- u_mm_file_ram_dp_ram_to_mm : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DP_RAM_TO_MM")
+ -- PORT MAP(mm_rst, i_mm_clk, ram_dp_ram_to_mm_mosi, ram_dp_ram_to_mm_miso );
- u_mm_file_reg_dp_split : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SPLIT")
- port map(mm_rst, i_mm_clk, reg_dp_split_mosi, reg_dp_split_miso );
+ u_mm_file_reg_dp_split : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SPLIT")
+ port map(mm_rst, i_mm_clk, reg_dp_split_mosi, reg_dp_split_miso );
- u_mm_file_reg_dp_pkt_merge : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_PKT_MERGE")
- port map(mm_rst, i_mm_clk, reg_dp_pkt_merge_mosi, reg_dp_pkt_merge_miso );
+ u_mm_file_reg_dp_pkt_merge : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_PKT_MERGE")
+ port map(mm_rst, i_mm_clk, reg_dp_pkt_merge_mosi, reg_dp_pkt_merge_miso );
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_ram_bf_weights : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- port map(mm_rst, i_mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
+ u_mm_file_ram_bf_weights : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
+ port map(mm_rst, i_mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
- u_mm_file_ram_ss_ss_wide : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, i_mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
+ u_mm_file_ram_ss_ss_wide : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ port map(mm_rst, i_mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
- u_mm_file_ram_st_sst_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, i_mm_clk, ram_st_sst_bf_mosi, ram_st_sst_bf_miso );
+ u_mm_file_ram_st_sst_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
+ port map(mm_rst, i_mm_clk, ram_st_sst_bf_mosi, ram_st_sst_bf_miso );
- u_mm_file_reg_st_sst_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ST_SST")
- port map(mm_rst, i_mm_clk, reg_st_sst_bf_mosi, reg_st_sst_bf_miso );
+ u_mm_file_reg_st_sst_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ST_SST")
+ port map(mm_rst, i_mm_clk, reg_st_sst_bf_mosi, reg_st_sst_bf_miso );
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -247,10 +263,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_reg_mosi <= sim_eth1g_reg_mosi;
- else
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
- end if;
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ else
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -268,162 +284,162 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_fn_bf
- port map (
- -- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => OPEN, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
-
- -- the_altpll_0
- areset_to_the_altpll_0 => '0',
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
-
- -- the_avs2_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_st_sst
- coe_address_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.address(c_ram_st_sst_bf_addr_w - 1 downto 0),
- coe_clk_export_from_the_ram_st_sst => OPEN,
- coe_read_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.rd,
- coe_readdata_export_to_the_ram_st_sst => ram_st_sst_bf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_st_sst => OPEN,
- coe_write_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.wr,
- coe_writedata_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_st_sst
- coe_address_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.address(c_reg_st_sst_bf_addr_w - 1 downto 0),
- coe_clk_export_from_the_reg_st_sst => OPEN,
- coe_read_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.rd,
- coe_readdata_export_to_the_reg_st_sst => reg_st_sst_bf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_st_sst => OPEN,
- coe_write_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.wr,
- coe_writedata_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_ss_ss_wide
- coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.address(c_ram_ss_ss_wide_addr_w - 1 downto 0),
- coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
- coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.rd,
- coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_wide_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
- coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.wr,
- coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_bf_weights
- coe_address_export_from_the_ram_bf_weights => ram_bf_weights_mosi.address(c_ram_bf_weights_addr_w - 1 downto 0),
- coe_clk_export_from_the_ram_bf_weights => OPEN,
- coe_read_export_from_the_ram_bf_weights => ram_bf_weights_mosi.rd,
- coe_readdata_export_to_the_ram_bf_weights => ram_bf_weights_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_bf_weights => OPEN,
- coe_write_export_from_the_ram_bf_weights => ram_bf_weights_mosi.wr,
- coe_writedata_export_from_the_ram_bf_weights => ram_bf_weights_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bg_diag_bg
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_addr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dp_ram_from_mm
- coe_clk_export_from_the_reg_dp_ram_from_mm => OPEN,
- coe_reset_export_from_the_reg_dp_ram_from_mm => OPEN,
- coe_address_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.address(0),
- coe_read_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.rd,
- coe_readdata_export_to_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.wr,
- coe_writedata_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_dp_ram_from_mm
- coe_clk_export_from_the_ram_dp_ram_from_mm => OPEN,
- coe_reset_export_from_the_ram_dp_ram_from_mm => OPEN,
- coe_address_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.address(c_dp_ram_mm_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.rd,
- coe_readdata_export_to_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.wr,
- coe_writedata_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ -- 1) global signals:
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => OPEN, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+
+ -- the_altpll_0
+ areset_to_the_altpll_0 => '0',
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+
+ -- the_avs2_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_st_sst
+ coe_address_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.address(c_ram_st_sst_bf_addr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_st_sst => OPEN,
+ coe_read_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.rd,
+ coe_readdata_export_to_the_ram_st_sst => ram_st_sst_bf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_st_sst => OPEN,
+ coe_write_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.wr,
+ coe_writedata_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_st_sst
+ coe_address_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.address(c_reg_st_sst_bf_addr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_st_sst => OPEN,
+ coe_read_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.rd,
+ coe_readdata_export_to_the_reg_st_sst => reg_st_sst_bf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_st_sst => OPEN,
+ coe_write_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.wr,
+ coe_writedata_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_ss_ss_wide
+ coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.address(c_ram_ss_ss_wide_addr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.rd,
+ coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_wide_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.wr,
+ coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_bf_weights
+ coe_address_export_from_the_ram_bf_weights => ram_bf_weights_mosi.address(c_ram_bf_weights_addr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_bf_weights => OPEN,
+ coe_read_export_from_the_ram_bf_weights => ram_bf_weights_mosi.rd,
+ coe_readdata_export_to_the_ram_bf_weights => ram_bf_weights_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_bf_weights => OPEN,
+ coe_write_export_from_the_ram_bf_weights => ram_bf_weights_mosi.wr,
+ coe_writedata_export_from_the_ram_bf_weights => ram_bf_weights_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bg_diag_bg
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_addr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dp_ram_from_mm
+ coe_clk_export_from_the_reg_dp_ram_from_mm => OPEN,
+ coe_reset_export_from_the_reg_dp_ram_from_mm => OPEN,
+ coe_address_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.address(0),
+ coe_read_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.rd,
+ coe_readdata_export_to_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.wr,
+ coe_writedata_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_dp_ram_from_mm
+ coe_clk_export_from_the_ram_dp_ram_from_mm => OPEN,
+ coe_reset_export_from_the_ram_dp_ram_from_mm => OPEN,
+ coe_address_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.address(c_dp_ram_mm_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.rd,
+ coe_readdata_export_to_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.wr,
+ coe_writedata_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
-end;
+ end;
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
index bcf58a4808..b3e4606cde 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
@@ -20,18 +20,18 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, diag_lib, eth_lib, tech_tse_lib, bf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use bf_lib.all;
-use bf_lib.bf_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use bf_lib.all;
+ use bf_lib.bf_pkg.all;
entity node_unb1_fn_bf is
generic(
@@ -101,14 +101,15 @@ architecture str of node_unb1_fn_bf is
constant c_bg_mem_high_addr : natural := c_bg_block_size-1;
constant c_bg_gapsize : natural := 256 - c_bg_block_size; -- 256 = block period used in terminals
constant c_bg_blocks_per_sync : natural := 32; -- Used for sim
- constant c_bg_ctrl : t_diag_block_gen := (sel_a_b(g_sim, '1', '0'), -- enable
- sel_a_b(g_sim, '0', '0'), -- enable_sync
- TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( c_bg_mem_high_addr, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ sel_a_b(g_sim, '1', '0'), -- enable
+ sel_a_b(g_sim, '0', '0'), -- enable_sync
+ TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( c_bg_mem_high_addr, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
signal bf_in_sosi_arr : t_dp_sosi_arr( g_bf.nof_input_streams - 1 downto 0);
signal bg_out_sosi_arr : t_dp_sosi_arr( g_bf.nof_input_streams - 1 downto 0);
@@ -121,35 +122,35 @@ begin
-- Use Block Generator input by default
---------------------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_use_usr_input => true,
- g_use_bg => g_use_block_gen,
- g_nof_streams => g_bf.nof_input_streams, -- 16
- g_use_bg_buffer_ram => true,
- g_buf_dat_w => c_nof_complex * g_bf.in_dat_w, -- 2*16b=32b
- g_buf_addr_w => ceil_log2(c_bg_block_size),
- g_file_name_prefix => g_block_gen_file_prefix,
- g_diag_block_gen_rst => c_bg_ctrl,
- g_usr_bypass_xonoff => true
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- usr_siso_arr => OPEN,
- usr_sosi_arr => ext_in_sosi_arr,
- out_siso_arr => (others => c_dp_siso_rdy),
- out_sosi_arr => bg_out_sosi_arr
- );
+ generic map(
+ g_use_usr_input => true,
+ g_use_bg => g_use_block_gen,
+ g_nof_streams => g_bf.nof_input_streams, -- 16
+ g_use_bg_buffer_ram => true,
+ g_buf_dat_w => c_nof_complex * g_bf.in_dat_w, -- 2*16b=32b
+ g_buf_addr_w => ceil_log2(c_bg_block_size),
+ g_file_name_prefix => g_block_gen_file_prefix,
+ g_diag_block_gen_rst => c_bg_ctrl,
+ g_usr_bypass_xonoff => true
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ usr_siso_arr => OPEN,
+ usr_sosi_arr => ext_in_sosi_arr,
+ out_siso_arr => (others => c_dp_siso_rdy),
+ out_sosi_arr => bg_out_sosi_arr
+ );
bf_in_sosi_arr <= bg_out_sosi_arr;
@@ -162,37 +163,37 @@ begin
---------------------------------------------------------------------------------------
gen_bf : if g_use_bf = true generate
u_bf : entity bf_lib.bf
- generic map (
- g_bf => g_bf,
- g_bf_weights_file_name => g_bf_weights_file_name,
- g_ss_wide_file_prefix => g_ss_wide_file_prefix,
- g_weights_write_only => g_weights_write_only
- )
- port map (
- -- System
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- MM interface
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- ram_st_sst_mosi => ram_st_sst_bf_mosi,
- ram_st_sst_miso => ram_st_sst_bf_miso,
- reg_st_sst_mosi => reg_st_sst_bf_mosi,
- reg_st_sst_miso => reg_st_sst_bf_miso,
-
- -- ST interface
- in_sosi_arr => bf_in_sosi_arr,
- in_siso_arr => ext_in_siso_arr,
-
- out_raw_sosi_arr => out_raw_sosi_arr, -- raw beamlets
- out_bst_sosi_arr => i_out_bst_sosi_arr, -- 16b beamlets
- out_qua_sosi_arr => out_qua_sosi_arr -- 8b beamlets
- );
+ generic map (
+ g_bf => g_bf,
+ g_bf_weights_file_name => g_bf_weights_file_name,
+ g_ss_wide_file_prefix => g_ss_wide_file_prefix,
+ g_weights_write_only => g_weights_write_only
+ )
+ port map (
+ -- System
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- MM interface
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+ ram_st_sst_mosi => ram_st_sst_bf_mosi,
+ ram_st_sst_miso => ram_st_sst_bf_miso,
+ reg_st_sst_mosi => reg_st_sst_bf_mosi,
+ reg_st_sst_miso => reg_st_sst_bf_miso,
+
+ -- ST interface
+ in_sosi_arr => bf_in_sosi_arr,
+ in_siso_arr => ext_in_siso_arr,
+
+ out_raw_sosi_arr => out_raw_sosi_arr, -- raw beamlets
+ out_bst_sosi_arr => i_out_bst_sosi_arr, -- 16b beamlets
+ out_qua_sosi_arr => out_qua_sosi_arr -- 8b beamlets
+ );
end generate;
---------------------------------------------------------------------------------------
@@ -200,37 +201,37 @@ begin
---------------------------------------------------------------------------------------
gen_bf_offload : if g_bf_offload = true and g_sim = false generate
u_dp_offload : entity dp_lib.dp_offload_tx_legacy
- generic map (
- g_nof_streams => g_bf.nof_bf_units,
- g_data_w => c_eth_data_w,
- g_block_size => g_bf.nof_weights, -- = 256
- g_block_nof_sel_words => 20,
- g_nof_words_per_pkt => 360,
- g_hdr_nof_words => c_network_total_header_32b_nof_words,
- g_use_complex => true,
- g_use_input_fifo => true,
- g_use_output_fifo => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- reg_hdr_insert_mosi => reg_hdr_insert_mosi,
- ram_hdr_insert_mosi => ram_hdr_insert_mosi,
- reg_dp_split_mosi => reg_dp_split_mosi,
- reg_dp_split_miso => reg_dp_split_miso,
- reg_dp_pkt_merge_mosi => reg_dp_pkt_merge_mosi,
- reg_dp_pkt_merge_miso => reg_dp_pkt_merge_miso,
-
- dp_sosi_arr => i_out_bst_sosi_arr,
- dp_siso_arr => OPEN, -- No flow control, so we're instantiating an input FIFO.
-
- tx_sosi_arr => bf_out_offload_tx_sosi_arr(g_bf.nof_bf_units - 1 downto 0),
- tx_siso_arr => bf_out_offload_tx_siso_arr(g_bf.nof_bf_units - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_bf.nof_bf_units,
+ g_data_w => c_eth_data_w,
+ g_block_size => g_bf.nof_weights, -- = 256
+ g_block_nof_sel_words => 20,
+ g_nof_words_per_pkt => 360,
+ g_hdr_nof_words => c_network_total_header_32b_nof_words,
+ g_use_complex => true,
+ g_use_input_fifo => true,
+ g_use_output_fifo => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ reg_hdr_insert_mosi => reg_hdr_insert_mosi,
+ ram_hdr_insert_mosi => ram_hdr_insert_mosi,
+ reg_dp_split_mosi => reg_dp_split_mosi,
+ reg_dp_split_miso => reg_dp_split_miso,
+ reg_dp_pkt_merge_mosi => reg_dp_pkt_merge_mosi,
+ reg_dp_pkt_merge_miso => reg_dp_pkt_merge_miso,
+
+ dp_sosi_arr => i_out_bst_sosi_arr,
+ dp_siso_arr => OPEN, -- No flow control, so we're instantiating an input FIFO.
+
+ tx_sosi_arr => bf_out_offload_tx_sosi_arr(g_bf.nof_bf_units - 1 downto 0),
+ tx_siso_arr => bf_out_offload_tx_siso_arr(g_bf.nof_bf_units - 1 downto 0)
+ );
end generate;
end str;
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
index 39ea6ff5ea..33d6aeaa7d 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
@@ -20,19 +20,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib, bf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use bf_lib.bf_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use bf_lib.bf_pkg.all;
entity unb1_fn_bf is
generic (
@@ -47,7 +47,7 @@ entity unb1_fn_bf is
g_bf : t_c_bf := c_bf
);
port (
- -- GENERAL
+ -- GENERAL
CLK : in std_logic; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
@@ -82,7 +82,7 @@ architecture str of unb1_fn_bf is
constant c_ss_wide_file_prefix : string := "hex/ss_wide";
constant c_block_gen_file_prefix : string := "UNUSED";
- -- BF offload
+ -- BF offload
constant c_hdr_nof_words : natural := c_network_total_header_32b_nof_words;
constant c_dp_ram_mm_nof_words : natural := c_hdr_nof_words * (c_eth_data_w / c_word_w);
constant c_dp_ram_mm_adr_w : natural := ceil_log2(c_dp_ram_mm_nof_words);
@@ -181,214 +181,214 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_udp_offload => sel_a_b(c_bf_offload, true, false),
- g_aux => c_unb1_board_aux,
- g_udp_offload_nof_streams => c_nof_streams
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming ports to offload BF out
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_udp_offload => sel_a_b(c_bf_offload, true, false),
+ g_aux => c_unb1_board_aux,
+ g_udp_offload_nof_streams => c_nof_streams
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming ports to offload BF out
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_fn_bf
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_bf => g_bf
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- Diagnostics
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
-
- -- . block generator
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
-
- -- beamformer
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- ram_st_sst_bf_mosi => ram_st_sst_bf_mosi,
- ram_st_sst_bf_miso => ram_st_sst_bf_miso,
- reg_st_sst_bf_mosi => reg_st_sst_bf_mosi,
- reg_st_sst_bf_miso => reg_st_sst_bf_miso,
-
- -- dp_offload -- dp_offload
- reg_dp_ram_from_mm_mosi => reg_dp_ram_from_mm_mosi,
- reg_dp_ram_from_mm_miso => reg_dp_ram_from_mm_miso,
- ram_dp_ram_from_mm_mosi => ram_dp_ram_from_mm_mosi,
- ram_dp_ram_from_mm_miso => ram_dp_ram_from_mm_miso,
- reg_dp_split_mosi => reg_dp_split_mosi,
- reg_dp_split_miso => reg_dp_split_miso,
- reg_dp_pkt_merge_mosi => reg_dp_pkt_merge_mosi,
- reg_dp_pkt_merge_miso => reg_dp_pkt_merge_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_bf => g_bf
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- Diagnostics
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ -- . block generator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+
+ -- beamformer
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+ ram_st_sst_bf_mosi => ram_st_sst_bf_mosi,
+ ram_st_sst_bf_miso => ram_st_sst_bf_miso,
+ reg_st_sst_bf_mosi => reg_st_sst_bf_mosi,
+ reg_st_sst_bf_miso => reg_st_sst_bf_miso,
+
+ -- dp_offload -- dp_offload
+ reg_dp_ram_from_mm_mosi => reg_dp_ram_from_mm_mosi,
+ reg_dp_ram_from_mm_miso => reg_dp_ram_from_mm_miso,
+ ram_dp_ram_from_mm_mosi => ram_dp_ram_from_mm_mosi,
+ ram_dp_ram_from_mm_miso => ram_dp_ram_from_mm_miso,
+ reg_dp_split_mosi => reg_dp_split_mosi,
+ reg_dp_split_miso => reg_dp_split_miso,
+ reg_dp_pkt_merge_mosi => reg_dp_pkt_merge_mosi,
+ reg_dp_pkt_merge_miso => reg_dp_pkt_merge_miso
+ );
u_node_unb1_fn_bf : entity work.node_unb1_fn_bf
- generic map(
- g_bf => g_bf,
- g_bf_offload => c_bf_offload,
- g_bf_weights_file_name => c_bf_weights_file_name,
- g_ss_wide_file_prefix => c_ss_wide_file_prefix,
- g_block_gen_file_prefix => c_block_gen_file_prefix,
- g_weights_write_only => c_weights_write_only
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- -- . block generator
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
-
- -- . beam former
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_st_sst_bf_mosi => ram_st_sst_bf_mosi,
- ram_st_sst_bf_miso => ram_st_sst_bf_miso,
- reg_st_sst_bf_mosi => reg_st_sst_bf_mosi,
- reg_st_sst_bf_miso => reg_st_sst_bf_miso,
-
- -- . hdr_insert for dp offload
- reg_hdr_insert_mosi => reg_dp_ram_from_mm_mosi,
- ram_hdr_insert_mosi => ram_dp_ram_from_mm_mosi,
-
- -- ST interface
- out_bst_sosi_arr => OPEN, -- 16b beamlets
- out_qua_sosi_arr => beams_sosi_arr, -- 8b beamlets
-
- -- DP offload of 16b beamlets to 1GbE via ctrl_unb_common
- bf_out_offload_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- bf_out_offload_tx_siso_arr => eth1g_udp_tx_siso_arr
- );
-end;
+ generic map(
+ g_bf => g_bf,
+ g_bf_offload => c_bf_offload,
+ g_bf_weights_file_name => c_bf_weights_file_name,
+ g_ss_wide_file_prefix => c_ss_wide_file_prefix,
+ g_block_gen_file_prefix => c_block_gen_file_prefix,
+ g_weights_write_only => c_weights_write_only
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ -- . block generator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+
+ -- . beam former
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ ram_st_sst_bf_mosi => ram_st_sst_bf_mosi,
+ ram_st_sst_bf_miso => ram_st_sst_bf_miso,
+ reg_st_sst_bf_mosi => reg_st_sst_bf_mosi,
+ reg_st_sst_bf_miso => reg_st_sst_bf_miso,
+
+ -- . hdr_insert for dp offload
+ reg_hdr_insert_mosi => reg_dp_ram_from_mm_mosi,
+ ram_hdr_insert_mosi => ram_dp_ram_from_mm_mosi,
+
+ -- ST interface
+ out_bst_sosi_arr => OPEN, -- 16b beamlets
+ out_qua_sosi_arr => beams_sosi_arr, -- 8b beamlets
+
+ -- DP offload of 16b beamlets to 1GbE via ctrl_unb_common
+ bf_out_offload_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ bf_out_offload_tx_siso_arr => eth1g_udp_tx_siso_arr
+ );
+ end;
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd
index 2ab0d75b8d..e35d6a3eab 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd
@@ -25,33 +25,33 @@
-- that are used on hardware.
library IEEE, common_lib, unb1_board_lib, i2c_lib, bf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use bf_lib.bf_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use bf_lib.bf_pkg.all;
entity tb_unb1_fn_bf is
-generic(
- -- TYPE t_c_bf IS RECORD
- -- nof_signal_paths : POSITIVE; -- = 64
- -- nof_input_streams : POSITIVE; -- = 16
- -- nof_subbands : POSITIVE; -- = 24
- -- nof_weights : POSITIVE; -- = 256
- -- nof_bf_units : POSITIVE; -- = 4
- -- in_dat_w : POSITIVE; -- = 16
- -- in_weight_w : POSITIVE; -- = 16
- -- bst_gain_w : INTEGER; -- = 1
- -- bst_dat_w : POSITIVE; -- = 16
- -- out_gain_w : INTEGER; -- = -5
- -- out_dat_w : POSITIVE; -- = 8
- -- stat_data_w : POSITIVE; -- = 56
- -- stat_data_sz : POSITIVE; -- = 2
- -- END RECORD;
- g_bf : t_c_bf := (64, 16, 24, 256, 4, 16, 16, 1, 16, -5, 8, 56, 2)
-);
+ generic(
+ -- TYPE t_c_bf IS RECORD
+ -- nof_signal_paths : POSITIVE; -- = 64
+ -- nof_input_streams : POSITIVE; -- = 16
+ -- nof_subbands : POSITIVE; -- = 24
+ -- nof_weights : POSITIVE; -- = 256
+ -- nof_bf_units : POSITIVE; -- = 4
+ -- in_dat_w : POSITIVE; -- = 16
+ -- in_weight_w : POSITIVE; -- = 16
+ -- bst_gain_w : INTEGER; -- = 1
+ -- bst_dat_w : POSITIVE; -- = 16
+ -- out_gain_w : INTEGER; -- = -5
+ -- out_dat_w : POSITIVE; -- = 8
+ -- stat_data_w : POSITIVE; -- = 56
+ -- stat_data_sz : POSITIVE; -- = 2
+ -- END RECORD;
+ g_bf : t_c_bf := (64, 16, 24, 256, 4, 16, 16, 1, 16, -5, 8, 56, 2)
+ );
end tb_unb1_fn_bf;
architecture tb of tb_unb1_fn_bf is
diff --git a/libraries/dsp/bf/src/vhdl/bf.vhd b/libraries/dsp/bf/src/vhdl/bf.vhd
index ef5b683e18..ced0b07a2e 100644
--- a/libraries/dsp/bf/src/vhdl/bf.vhd
+++ b/libraries/dsp/bf/src/vhdl/bf.vhd
@@ -26,12 +26,12 @@
-- all bf_unit modules.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.bf_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.bf_pkg.all;
entity bf is
generic (
@@ -90,55 +90,55 @@ begin
-- Combine the internal array of mm interfaces for the weight factors to one array that is connected to the port of bf
u_mem_mux_weight : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_bf.nof_bf_units,
- g_mult_addr_w => ceil_log2(g_bf.nof_signal_paths * g_bf.nof_weights)
- )
- port map (
- mosi => ram_bf_weights_mosi,
- miso => ram_bf_weights_miso,
- mosi_arr => ram_bf_weights_mosi_arr,
- miso_arr => ram_bf_weights_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_bf.nof_bf_units,
+ g_mult_addr_w => ceil_log2(g_bf.nof_signal_paths * g_bf.nof_weights)
+ )
+ port map (
+ mosi => ram_bf_weights_mosi,
+ miso => ram_bf_weights_miso,
+ mosi_arr => ram_bf_weights_mosi_arr,
+ miso_arr => ram_bf_weights_miso_arr
+ );
-- Combine the internal array of mm interfaces for the beamlet statistics to one array that is connected to the port of bf
u_mem_mux_ram_bst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_bf.nof_bf_units,
- g_mult_addr_w => c_ram_st_addr_w
- )
- port map (
- mosi => ram_st_sst_mosi,
- miso => ram_st_sst_miso,
- mosi_arr => ram_st_sst_mosi_arr,
- miso_arr => ram_st_sst_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_bf.nof_bf_units,
+ g_mult_addr_w => c_ram_st_addr_w
+ )
+ port map (
+ mosi => ram_st_sst_mosi,
+ miso => ram_st_sst_miso,
+ mosi_arr => ram_st_sst_mosi_arr,
+ miso_arr => ram_st_sst_miso_arr
+ );
-- Combine the internal array of mm interfaces for the beamlet statistics to one array that is connected to the port of bf
u_mem_mux_reg_bst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_bf.nof_bf_units,
- g_mult_addr_w => c_reg_st_addr_w
- )
- port map (
- mosi => reg_st_sst_mosi,
- miso => reg_st_sst_miso,
- mosi_arr => reg_st_sst_mosi_arr,
- miso_arr => reg_st_sst_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_bf.nof_bf_units,
+ g_mult_addr_w => c_reg_st_addr_w
+ )
+ port map (
+ mosi => reg_st_sst_mosi,
+ miso => reg_st_sst_miso,
+ mosi_arr => reg_st_sst_mosi_arr,
+ miso_arr => reg_st_sst_miso_arr
+ );
-- Combine the internal array of mm interfaces for the ss_wide to one array that is connected to the port of bf
u_mem_mux_ss_wide : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_bf.nof_bf_units,
- g_mult_addr_w => ceil_log2(g_bf.nof_weights * g_bf.nof_signal_paths)
- )
- port map (
- mosi => ram_ss_ss_wide_mosi,
- miso => ram_ss_ss_wide_miso,
- mosi_arr => ram_ss_ss_wide_mosi_arr,
- miso_arr => ram_ss_ss_wide_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_bf.nof_bf_units,
+ g_mult_addr_w => ceil_log2(g_bf.nof_weights * g_bf.nof_signal_paths)
+ )
+ port map (
+ mosi => ram_ss_ss_wide_mosi,
+ miso => ram_ss_ss_wide_miso,
+ mosi_arr => ram_ss_ss_wide_mosi_arr,
+ miso_arr => ram_ss_ss_wide_miso_arr
+ );
------------------------------------------------------------------------------
-- The BF units
@@ -146,36 +146,36 @@ begin
-- Instantiate multiple BF units.
gen_bf_units : for J in 0 to g_bf.nof_bf_units - 1 generate
u_bf_unit : entity work.bf_unit
- generic map (
- g_bf => g_bf,
- g_bf_weights_file_name => sel_a_b(g_bf_weights_file_name = "UNUSED", g_bf_weights_file_name, g_bf_weights_file_name & "_" & natural'image(J)),
- g_ss_wide_file_prefix => sel_a_b(g_ss_wide_file_prefix = "UNUSED", g_ss_wide_file_prefix, g_ss_wide_file_prefix & "_" & natural'image(J)),
- g_weights_write_only => g_weights_write_only
- )
- port map (
- -- System
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- MM interface
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(J),
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(J),
- ram_bf_weights_mosi => ram_bf_weights_mosi_arr(J),
- ram_bf_weights_miso => ram_bf_weights_miso_arr(J),
- ram_st_sst_mosi => ram_st_sst_mosi_arr(J),
- ram_st_sst_miso => ram_st_sst_miso_arr(J),
- reg_st_sst_mosi => reg_st_sst_mosi_arr(J),
- reg_st_sst_miso => reg_st_sst_miso_arr(J),
-
- -- ST interface
- in_sosi_arr => in_sosi_arr,
- in_siso_arr => in_siso_2arr(J),
- out_raw_sosi => out_raw_sosi_arr(J),
- out_bst_sosi => out_bst_sosi_arr(J),
- out_qua_sosi => out_qua_sosi_arr(J)
- );
+ generic map (
+ g_bf => g_bf,
+ g_bf_weights_file_name => sel_a_b(g_bf_weights_file_name = "UNUSED", g_bf_weights_file_name, g_bf_weights_file_name & "_" & natural'image(J)),
+ g_ss_wide_file_prefix => sel_a_b(g_ss_wide_file_prefix = "UNUSED", g_ss_wide_file_prefix, g_ss_wide_file_prefix & "_" & natural'image(J)),
+ g_weights_write_only => g_weights_write_only
+ )
+ port map (
+ -- System
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- MM interface
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(J),
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(J),
+ ram_bf_weights_mosi => ram_bf_weights_mosi_arr(J),
+ ram_bf_weights_miso => ram_bf_weights_miso_arr(J),
+ ram_st_sst_mosi => ram_st_sst_mosi_arr(J),
+ ram_st_sst_miso => ram_st_sst_miso_arr(J),
+ reg_st_sst_mosi => reg_st_sst_mosi_arr(J),
+ reg_st_sst_miso => reg_st_sst_miso_arr(J),
+
+ -- ST interface
+ in_sosi_arr => in_sosi_arr,
+ in_siso_arr => in_siso_2arr(J),
+ out_raw_sosi => out_raw_sosi_arr(J),
+ out_bst_sosi => out_bst_sosi_arr(J),
+ out_qua_sosi => out_qua_sosi_arr(J)
+ );
end generate gen_bf_units;
in_siso_arr <= in_siso_2arr(0);
diff --git a/libraries/dsp/bf/src/vhdl/bf_pkg.vhd b/libraries/dsp/bf/src/vhdl/bf_pkg.vhd
index 380a12f18f..24f9fb4ffa 100644
--- a/libraries/dsp/bf/src/vhdl/bf_pkg.vhd
+++ b/libraries/dsp/bf/src/vhdl/bf_pkg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package bf_pkg is
constant c_bf_note_fifo_is_ful : boolean := true;
diff --git a/libraries/dsp/bf/src/vhdl/bf_unit.vhd b/libraries/dsp/bf/src/vhdl/bf_unit.vhd
index 73d202ae11..c250b5e51f 100644
--- a/libraries/dsp/bf/src/vhdl/bf_unit.vhd
+++ b/libraries/dsp/bf/src/vhdl/bf_unit.vhd
@@ -45,14 +45,14 @@
-- RAM init files (.hex files) only work when g_weights_write_only is set to FALSE.
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib, common_mult_lib, technology_lib, dp_lib, st_lib, reorder_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.bf_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.bf_pkg.all;
entity bf_unit is
generic (
@@ -93,8 +93,8 @@ architecture str of bf_unit is
constant c_unit_w : positive := g_bf.in_dat_w + g_bf.in_weight_w - c_sign_w; -- skip double sign bit
constant c_prod_w : positive := c_unit_w + c_sum_of_prod_w; -- keep bit for sum of products in complex multiply
constant c_gain_w : integer := largest(g_bf.bst_gain_w, g_bf.out_gain_w); -- keep internal c_sum_w as wide as necessary to fit both BST and qua output
- -- no need to account for adder bit growth of ceil_log2(g_bf.nof_signal_paths),
- -- because default BF sum should not clip to allow next stage of BF
+ -- no need to account for adder bit growth of ceil_log2(g_bf.nof_signal_paths),
+ -- because default BF sum should not clip to allow next stage of BF
constant c_sum_w : positive := c_unit_w + c_gain_w; -- note use c_gain_w >= 1 if complex sum of products bit growth has to be preserved
constant c_bst_lsb_w : natural := c_unit_w + g_bf.bst_gain_w - g_bf.bst_dat_w;
constant c_out_lsb_w : natural := c_unit_w + g_bf.out_gain_w - g_bf.out_dat_w;
@@ -104,11 +104,12 @@ architecture str of bf_unit is
constant c_nof_subbands_per_stream : positive := c_nof_signal_paths_per_stream * g_bf.nof_subbands;
constant c_xst_enable : boolean := true;
- constant c_weights_buf : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_bf.nof_weights),
- dat_w => c_nof_complex * g_bf.in_weight_w,
- nof_dat => g_bf.nof_weights,
- init_sl => '0');
+ constant c_weights_buf : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_bf.nof_weights),
+ dat_w => c_nof_complex * g_bf.in_weight_w,
+ nof_dat => g_bf.nof_weights,
+ init_sl => '0');
-- Latencies
constant c_input_latency : natural := 1; -- due to r
constant c_prod_latency : natural := 3;
@@ -192,16 +193,16 @@ begin
end process;
u_mem_mux_ss_wide : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_bf.nof_input_streams,
- g_mult_addr_w => ceil_log2(g_bf.nof_weights * c_nof_signal_paths_per_stream)
- )
- port map (
- mosi => ram_ss_ss_wide_mosi,
- miso => ram_ss_ss_wide_miso,
- mosi_arr => ram_ss_ss_wide_mosi_arr,
- miso_arr => ram_ss_ss_wide_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_bf.nof_input_streams,
+ g_mult_addr_w => ceil_log2(g_bf.nof_weights * c_nof_signal_paths_per_stream)
+ )
+ port map (
+ mosi => ram_ss_ss_wide_mosi,
+ miso => ram_ss_ss_wide_miso,
+ mosi_arr => ram_ss_ss_wide_mosi_arr,
+ miso_arr => ram_ss_ss_wide_miso_arr
+ );
------------------------------------------------------------------------------
-- The beamformer unit
@@ -216,29 +217,29 @@ begin
in_siso_arr(I) <= ss_wide_in_siso_arr(I * c_nof_signal_paths_per_stream);
u_ss_wide : entity reorder_lib.reorder_col_wide
- generic map (
- g_technology => g_technology,
- g_wb_factor => c_nof_signal_paths_per_stream,
- g_dsp_data_w => g_bf.in_dat_w,
- g_nof_ch_in => c_nof_subbands_per_stream,
- g_nof_ch_sel => g_bf.nof_weights,
- g_select_file_prefix => g_ss_wide_file_prefix
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(I),
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(I),
-
- -- Streaming
- input_sosi_arr => ss_wide_in_sosi_arr((I + 1) * c_nof_signal_paths_per_stream - 1 downto I * c_nof_signal_paths_per_stream),
- input_siso_arr => ss_wide_in_siso_arr((I + 1) * c_nof_signal_paths_per_stream - 1 downto I * c_nof_signal_paths_per_stream),
- output_sosi_arr => bf_in_sosi_arr((I + 1) * c_nof_signal_paths_per_stream - 1 downto I * c_nof_signal_paths_per_stream)
- );
+ generic map (
+ g_technology => g_technology,
+ g_wb_factor => c_nof_signal_paths_per_stream,
+ g_dsp_data_w => g_bf.in_dat_w,
+ g_nof_ch_in => c_nof_subbands_per_stream,
+ g_nof_ch_sel => g_bf.nof_weights,
+ g_select_file_prefix => g_ss_wide_file_prefix
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(I),
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(I),
+
+ -- Streaming
+ input_sosi_arr => ss_wide_in_sosi_arr((I + 1) * c_nof_signal_paths_per_stream - 1 downto I * c_nof_signal_paths_per_stream),
+ input_siso_arr => ss_wide_in_siso_arr((I + 1) * c_nof_signal_paths_per_stream - 1 downto I * c_nof_signal_paths_per_stream),
+ output_sosi_arr => bf_in_sosi_arr((I + 1) * c_nof_signal_paths_per_stream - 1 downto I * c_nof_signal_paths_per_stream)
+ );
end generate;
-- Support readback of the last BF weight write to have some minimal readback functionality
@@ -268,47 +269,47 @@ begin
-- Combine the internal array of mm interfaces to one array that is connected to the port of bf_unit
u_mem_mux_weight : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_bf.nof_signal_paths,
- g_mult_addr_w => ceil_log2(g_bf.nof_weights)
- )
- port map (
- mosi => ram_bf_weights_mosi,
- miso => mm_bf_weights_miso,
- mosi_arr => mm_weight_mosi_arr,
- miso_arr => mm_weight_miso_arr
- );
-
- gen_bf : for I in 0 to g_bf.nof_signal_paths - 1 generate
- -- Instantiate a weight factor memory for each input stage:
- u_weight_ram : entity common_lib.common_ram_crw_crw
generic map (
- g_technology => g_technology,
- g_ram => c_weights_buf,
- g_init_file => sel_a_b(g_bf_weights_file_name = "UNUSED", g_bf_weights_file_name, g_bf_weights_file_name & "_" & natural'image(I) & ".hex"),
- g_true_dual_port => not(g_weights_write_only)
+ g_nof_mosi => g_bf.nof_signal_paths,
+ g_mult_addr_w => ceil_log2(g_bf.nof_weights)
)
port map (
- -- MM side
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => mm_weight_mosi_arr(I).wr,
- wr_dat_a => mm_weight_mosi_arr(I).wrdata(c_weights_buf.dat_w - 1 downto 0),
- adr_a => mm_weight_mosi_arr(I).address(c_weights_buf.adr_w - 1 downto 0),
- rd_en_a => mm_weight_mosi_arr(I).rd,
- rd_dat_a => mm_weight_miso_arr(I).rddata(c_weights_buf.dat_w - 1 downto 0),
- rd_val_a => mm_weight_miso_arr(I).rdval,
- -- MULT side
- rst_b => dp_rst,
- clk_b => dp_clk,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- adr_b => weight_addr,
- rd_en_b => '1',
- rd_dat_b => mult_miso_arr(I).rddata(c_weights_buf.dat_w - 1 downto 0),
- rd_val_b => open
+ mosi => ram_bf_weights_mosi,
+ miso => mm_bf_weights_miso,
+ mosi_arr => mm_weight_mosi_arr,
+ miso_arr => mm_weight_miso_arr
);
+ gen_bf : for I in 0 to g_bf.nof_signal_paths - 1 generate
+ -- Instantiate a weight factor memory for each input stage:
+ u_weight_ram : entity common_lib.common_ram_crw_crw
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_weights_buf,
+ g_init_file => sel_a_b(g_bf_weights_file_name = "UNUSED", g_bf_weights_file_name, g_bf_weights_file_name & "_" & natural'image(I) & ".hex"),
+ g_true_dual_port => not(g_weights_write_only)
+ )
+ port map (
+ -- MM side
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => mm_weight_mosi_arr(I).wr,
+ wr_dat_a => mm_weight_mosi_arr(I).wrdata(c_weights_buf.dat_w - 1 downto 0),
+ adr_a => mm_weight_mosi_arr(I).address(c_weights_buf.adr_w - 1 downto 0),
+ rd_en_a => mm_weight_mosi_arr(I).rd,
+ rd_dat_a => mm_weight_miso_arr(I).rddata(c_weights_buf.dat_w - 1 downto 0),
+ rd_val_a => mm_weight_miso_arr(I).rdval,
+ -- MULT side
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ adr_b => weight_addr,
+ rd_en_b => '1',
+ rd_dat_b => mult_miso_arr(I).rddata(c_weights_buf.dat_w - 1 downto 0),
+ rd_val_b => open
+ );
+
data_re_arr(I) <= r.bf_in_sosi_arr(I).re(g_bf.in_dat_w - 1 downto 0);
data_im_arr(I) <= r.bf_in_sosi_arr(I).im(g_bf.in_dat_w - 1 downto 0);
@@ -316,28 +317,28 @@ begin
weight_im_arr(I) <= mult_miso_arr(I).rddata(2 * g_bf.in_weight_w - 1 downto g_bf.in_weight_w);
u_multiplier : entity common_mult_lib.common_complex_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => g_bf.in_weight_w,
- g_in_b_w => g_bf.in_dat_w,
- g_out_p_w => c_prod_w,
- g_conjugate_b => c_conjugate,
- g_pipeline_input => 1,
- g_pipeline_product => 0,
- g_pipeline_adder => 1,
- g_pipeline_output => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_ar => weight_re_arr(I),
- in_ai => weight_im_arr(I),
- in_br => data_re_arr(I),
- in_bi => data_im_arr(I),
- out_pr => prod_re_arr(I),
- out_pi => prod_im_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => g_bf.in_weight_w,
+ g_in_b_w => g_bf.in_dat_w,
+ g_out_p_w => c_prod_w,
+ g_conjugate_b => c_conjugate,
+ g_pipeline_input => 1,
+ g_pipeline_product => 0,
+ g_pipeline_adder => 1,
+ g_pipeline_output => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_ar => weight_re_arr(I),
+ in_ai => weight_im_arr(I),
+ in_br => data_re_arr(I),
+ in_bi => data_im_arr(I),
+ out_pr => prod_re_arr(I),
+ out_pi => prod_im_arr(I)
+ );
-- Map the product array to a vector for the adder tree input
prod_re_vec((I + 1) * c_prod_w - 1 downto I * c_prod_w) <= prod_re_arr(I);
@@ -346,68 +347,68 @@ begin
-- One adder tree for the real part
u_adder_tree_re : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_adder_stage_latency,
- g_nof_inputs => g_bf.nof_signal_paths,
- g_dat_w => c_prod_w,
- g_sum_w => c_sum_w
- )
- port map (
- clk => dp_clk,
- in_dat => prod_re_vec,
- sum => sum_re
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_adder_stage_latency,
+ g_nof_inputs => g_bf.nof_signal_paths,
+ g_dat_w => c_prod_w,
+ g_sum_w => c_sum_w
+ )
+ port map (
+ clk => dp_clk,
+ in_dat => prod_re_vec,
+ sum => sum_re
+ );
-- One adder tree for the imaginary part
u_adder_tree_im : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_adder_stage_latency,
- g_nof_inputs => g_bf.nof_signal_paths,
- g_dat_w => c_prod_w,
- g_sum_w => c_sum_w
- )
- port map (
- clk => dp_clk,
- in_dat => prod_im_vec,
- sum => sum_im
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_adder_stage_latency,
+ g_nof_inputs => g_bf.nof_signal_paths,
+ g_dat_w => c_prod_w,
+ g_sum_w => c_sum_w
+ )
+ port map (
+ clk => dp_clk,
+ in_dat => prod_im_vec,
+ sum => sum_im
+ );
------------------------------------------------------------------------------
-- Counter used to create addresses for the weight memory
------------------------------------------------------------------------------
weight_adrs_cnt : entity common_lib.common_counter
- generic map(
- g_latency => 1,
- g_init => 0,
- g_width => c_weights_buf.adr_w,
- g_max => g_bf.nof_weights - 1,
- g_step_size => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- cnt_clr => bf_in_sosi_arr(0).eop,
- cnt_en => bf_in_sosi_arr(0).valid,
- count => weight_addr
- );
+ generic map(
+ g_latency => 1,
+ g_init => 0,
+ g_width => c_weights_buf.adr_w,
+ g_max => g_bf.nof_weights - 1,
+ g_step_size => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ cnt_clr => bf_in_sosi_arr(0).eop,
+ cnt_en => bf_in_sosi_arr(0).valid,
+ count => weight_addr
+ );
------------------------------------------------------------------------------
-- Pipeline to align the sosi control
------------------------------------------------------------------------------
u_dp_pipeline : entity dp_lib.dp_pipeline
- generic map(
- g_pipeline => c_bf_unit_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => bf_in_sosi_arr(0),
- -- ST source
- src_out => piped_sosi
- );
+ generic map(
+ g_pipeline => c_bf_unit_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => bf_in_sosi_arr(0),
+ -- ST source
+ src_out => piped_sosi
+ );
process(piped_sosi, sum_re, sum_im)
begin
@@ -424,75 +425,75 @@ begin
-- Requantize for internal BST and out_bst_sosi output
u_dp_requantize_bst : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_bst_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false, -- default BF should not clip
- g_msb_clip_symmetric => false,
- g_gain_w => 0,
- g_pipeline_remove_lsb => 1,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => c_sum_w,
- g_out_dat_w => g_bf.bst_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => beams_raw_sosi,
- src_out => beams_bst_sosi,
- out_ovr => open
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_bst_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false, -- default BF should not clip
+ g_msb_clip_symmetric => false,
+ g_gain_w => 0,
+ g_pipeline_remove_lsb => 1,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => c_sum_w,
+ g_out_dat_w => g_bf.bst_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => beams_raw_sosi,
+ src_out => beams_bst_sosi,
+ out_ovr => open
+ );
out_bst_sosi <= beams_bst_sosi;
-- Requantize for out_qua_sosi output
u_dp_requantize_out : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_out_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false, -- default BF should not clip
- g_msb_clip_symmetric => false,
- g_gain_w => 0,
- g_pipeline_remove_lsb => 1,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => c_sum_w,
- g_out_dat_w => g_bf.out_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => beams_raw_sosi,
- src_out => out_qua_sosi,
- out_ovr => open
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_out_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false, -- default BF should not clip
+ g_msb_clip_symmetric => false,
+ g_gain_w => 0,
+ g_pipeline_remove_lsb => 1,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => c_sum_w,
+ g_out_dat_w => g_bf.out_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => beams_raw_sosi,
+ src_out => out_qua_sosi,
+ out_ovr => open
+ );
------------------------------------------------------------------------------
-- Internal BST
------------------------------------------------------------------------------
u_beamlet_statistics : entity st_lib.st_sst
- generic map(
- g_technology => g_technology,
- g_nof_stat => g_bf.nof_weights,
- g_xst_enable => c_xst_enable,
- g_in_data_w => g_bf.bst_dat_w,
- g_stat_data_w => g_bf.stat_data_w,
- g_stat_data_sz => g_bf.stat_data_sz
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_complex => beams_bst_sosi,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- reg_st_sst_mosi => reg_st_sst_mosi,
- reg_st_sst_miso => reg_st_sst_miso
- );
+ generic map(
+ g_technology => g_technology,
+ g_nof_stat => g_bf.nof_weights,
+ g_xst_enable => c_xst_enable,
+ g_in_data_w => g_bf.bst_dat_w,
+ g_stat_data_w => g_bf.stat_data_w,
+ g_stat_data_sz => g_bf.stat_data_sz
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_complex => beams_bst_sosi,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ reg_st_sst_mosi => reg_st_sst_mosi,
+ reg_st_sst_miso => reg_st_sst_miso
+ );
end str;
diff --git a/libraries/dsp/bf/tb/vhdl/tb_bf.vhd b/libraries/dsp/bf/tb/vhdl/tb_bf.vhd
index c8b63bdf68..c5ef098205 100644
--- a/libraries/dsp/bf/tb/vhdl/tb_bf.vhd
+++ b/libraries/dsp/bf/tb/vhdl/tb_bf.vhd
@@ -37,18 +37,18 @@
-- > Evalute the WAVE window.
library IEEE, common_lib, mm_lib, diag_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.bf_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.bf_pkg.all;
entity tb_bf is
generic(
@@ -127,9 +127,10 @@ architecture tb of tb_bf is
signal reg_st_sst_miso : t_mem_miso := c_mem_miso_rst;
-- Compose the record with generics for the bf_units.
- constant c_bf : t_c_bf := (g_nof_signal_paths, g_nof_input_streams, g_nof_subbands,
- g_nof_weights, g_nof_bf_units, g_in_dat_w, g_in_weight_w, g_bst_gain_w,
- g_bst_dat_w, g_out_gain_w, g_out_dat_w, g_stat_data_w, g_stat_data_sz);
+ constant c_bf : t_c_bf := (
+ g_nof_signal_paths, g_nof_input_streams, g_nof_subbands,
+ g_nof_weights, g_nof_bf_units, g_in_dat_w, g_in_weight_w, g_bst_gain_w,
+ g_bst_dat_w, g_out_gain_w, g_out_dat_w, g_stat_data_w, g_stat_data_sz);
-- Custom definitions of constants
constant c_bg_block_len : natural := c_bf.nof_subbands * c_bf.nof_signal_paths / c_bf.nof_input_streams;
@@ -171,7 +172,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -181,150 +182,160 @@ begin
-- MM buses
----------------------------------------------------------------------------
-- TB
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_ram_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+ u_mm_file_ram_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
- u_mm_file_reg_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+ u_mm_file_reg_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
- u_mm_file_ram_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+ u_mm_file_ram_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
- u_mm_file_reg_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+ u_mm_file_reg_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
-- DUT
- u_mm_file_ram_ss_ss_wide : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_SS_SS_WIDE")
- port map(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso);
+ u_mm_file_ram_ss_ss_wide : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_SS_SS_WIDE")
+ port map(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso);
- u_mm_file_ram_weight : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_WEIGHT")
- port map(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso);
+ u_mm_file_ram_weight : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_WEIGHT")
+ port map(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso);
- u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso);
+ u_mm_file_ram_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_ST_SST")
+ port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso);
- u_mm_file_reg_st_sst : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_ST_SST")
- port map(mm_rst, mm_clk, reg_st_sst_mosi, reg_st_sst_miso);
+ u_mm_file_reg_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_ST_SST")
+ port map(mm_rst, mm_clk, reg_st_sst_mosi, reg_st_sst_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => c_bg_nof_output_streams,
- g_buf_dat_w => c_bg_buf_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w,
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut : entity work.bf
- generic map (
- g_bf => c_bf,
- g_bf_weights_file_name => g_bf_weights_file_name,
- g_ss_wide_file_prefix => g_ss_wide_file_prefix,
- g_weights_write_only => false
- )
- port map (
- -- System
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- MM interface
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- reg_st_sst_mosi => reg_st_sst_mosi,
- reg_st_sst_miso => reg_st_sst_miso,
-
- -- ST interface
- in_sosi_arr => bg_sosi_arr,
- out_raw_sosi_arr => beamlets_sosi_arr, -- raw beamlets
- out_bst_sosi_arr => OPEN, -- 16b beamlets
- out_qua_sosi_arr => open -- 8b beamlets
- );
+ generic map (
+ g_bf => c_bf,
+ g_bf_weights_file_name => g_bf_weights_file_name,
+ g_ss_wide_file_prefix => g_ss_wide_file_prefix,
+ g_weights_write_only => false
+ )
+ port map (
+ -- System
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- MM interface
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ reg_st_sst_mosi => reg_st_sst_mosi,
+ reg_st_sst_miso => reg_st_sst_miso,
+
+ -- ST interface
+ in_sosi_arr => bg_sosi_arr,
+ out_raw_sosi_arr => beamlets_sosi_arr, -- raw beamlets
+ out_bst_sosi_arr => OPEN, -- 16b beamlets
+ out_qua_sosi_arr => open -- 8b beamlets
+ );
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_re,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
- ram_data_buf_miso => ram_diag_data_buf_re_miso,
- reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
- reg_data_buf_miso => reg_diag_data_buf_re_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => beamlets_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => beamlets_sosi_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_im,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
- ram_data_buf_miso => ram_diag_data_buf_im_miso,
- reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
- reg_data_buf_miso => reg_diag_data_buf_im_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => beamlets_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_im,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => beamlets_sosi_arr
+ );
end tb;
diff --git a/libraries/dsp/bf/tb/vhdl/tb_bf_unit.vhd b/libraries/dsp/bf/tb/vhdl/tb_bf_unit.vhd
index 185dbec54c..314ec11a28 100644
--- a/libraries/dsp/bf/tb/vhdl/tb_bf_unit.vhd
+++ b/libraries/dsp/bf/tb/vhdl/tb_bf_unit.vhd
@@ -38,18 +38,18 @@
-- > Evalute the WAVE window.
library IEEE, common_lib, mm_lib, diag_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.bf_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.bf_pkg.all;
entity tb_bf_unit is
generic(
@@ -128,9 +128,10 @@ architecture tb of tb_bf_unit is
signal reg_st_sst_miso : t_mem_miso := c_mem_miso_rst;
-- Compose the record with generics for the bf_units.
- constant c_bf : t_c_bf := (g_nof_signal_paths, g_nof_input_streams, g_nof_subbands,
- g_nof_weights, g_nof_bf_units, g_in_dat_w, g_in_weight_w, g_bst_gain_w,
- g_bst_dat_w, g_out_gain_w, g_out_dat_w, g_stat_data_w, g_stat_data_sz);
+ constant c_bf : t_c_bf := (
+ g_nof_signal_paths, g_nof_input_streams, g_nof_subbands,
+ g_nof_weights, g_nof_bf_units, g_in_dat_w, g_in_weight_w, g_bst_gain_w,
+ g_bst_dat_w, g_out_gain_w, g_out_dat_w, g_stat_data_w, g_stat_data_sz);
-- Custom definitions of constants
constant c_bg_block_len : natural := c_bf.nof_subbands * c_bf.nof_signal_paths / c_bf.nof_input_streams;
@@ -171,7 +172,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -181,151 +182,161 @@ begin
-- MM buses
----------------------------------------------------------------------------
-- TB
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_ram_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+ u_mm_file_ram_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
- u_mm_file_reg_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+ u_mm_file_reg_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
- u_mm_file_ram_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+ u_mm_file_ram_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
- u_mm_file_reg_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+ u_mm_file_reg_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
-- DUT
- u_mm_file_ram_ss_ss_wide : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_SS_SS_WIDE")
- port map(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso);
+ u_mm_file_ram_ss_ss_wide : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_SS_SS_WIDE")
+ port map(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso);
- u_mm_file_ram_bf_weights : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_BF_WEIGHTS")
- port map(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso);
+ u_mm_file_ram_bf_weights : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_BF_WEIGHTS")
+ port map(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso);
- u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso);
+ u_mm_file_ram_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_ST_SST")
+ port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso);
- u_mm_file_reg_st_sst : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_ST_SST")
- port map(mm_rst, mm_clk, reg_st_sst_mosi, reg_st_sst_miso);
+ u_mm_file_reg_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_ST_SST")
+ port map(mm_rst, mm_clk, reg_st_sst_mosi, reg_st_sst_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => c_bg_nof_output_streams,
- g_buf_dat_w => c_bg_buf_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w,
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut : entity work.bf_unit
- generic map (
- g_bf => c_bf,
- g_bf_weights_file_name => g_bf_weights_file_name,
- g_ss_wide_file_prefix => g_ss_wide_file_prefix,
- g_weights_write_only => false
- --g_weights_write_only => TRUE
- )
- port map (
- -- System
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- MM interface
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- reg_st_sst_mosi => reg_st_sst_mosi,
- reg_st_sst_miso => reg_st_sst_miso,
-
- -- ST interface
- in_sosi_arr => bg_sosi_arr,
- out_raw_sosi => out_sosi_arr(0), -- original raw beamlets output with c_sum_w bits.
- out_bst_sosi => open, -- requantized 16b beamlets output that is also used for internal BST.
- out_qua_sosi => open -- requantized 8b beamlets output.
- );
+ generic map (
+ g_bf => c_bf,
+ g_bf_weights_file_name => g_bf_weights_file_name,
+ g_ss_wide_file_prefix => g_ss_wide_file_prefix,
+ g_weights_write_only => false
+ --g_weights_write_only => TRUE
+ )
+ port map (
+ -- System
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- MM interface
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ reg_st_sst_mosi => reg_st_sst_mosi,
+ reg_st_sst_miso => reg_st_sst_miso,
+
+ -- ST interface
+ in_sosi_arr => bg_sosi_arr,
+ out_raw_sosi => out_sosi_arr(0), -- original raw beamlets output with c_sum_w bits.
+ out_bst_sosi => open, -- requantized 16b beamlets output that is also used for internal BST.
+ out_qua_sosi => open -- requantized 8b beamlets output.
+ );
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_re,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
- ram_data_buf_miso => ram_diag_data_buf_re_miso,
- reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
- reg_data_buf_miso => reg_diag_data_buf_re_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_im,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
- ram_data_buf_miso => ram_diag_data_buf_im_miso,
- reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
- reg_data_buf_miso => reg_diag_data_buf_im_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_im,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
index 89a874799d..88b7f05cc8 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
@@ -20,14 +20,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
entity mmm_unb1_correlator is
generic (
@@ -102,93 +102,93 @@ architecture str of mmm_unb1_correlator is
-- . Note the SLV->SL edits, e.g. coe_address_export_from_the_reg_wdi.
-----------------------------------------------------------------------------
component qsys_unb1_correlator is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- mm_clk : out std_logic; -- clk
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- tse_clk : out std_logic; -- clk
- epcs_clk : out std_logic; -- clk
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0); -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- c3_from_the_altpll_0 : out std_logic; -- export
- ram_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_read_export : out std_logic; -- export
- ram_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_write_export : out std_logic; -- export
- ram_diag_data_buf_address_export : out std_logic_vector(14 downto 0); -- export
- ram_diag_data_buf_clk_export : out std_logic; -- export
- ram_diag_data_buf_reset_export : out std_logic; -- export
- reg_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_read_export : out std_logic; -- export
- reg_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_write_export : out std_logic; -- export
- reg_diag_data_buf_address_export : out std_logic_vector(9 downto 0); -- export
- reg_diag_data_buf_clk_export : out std_logic; -- export
- reg_diag_data_buf_reset_export : out std_logic; -- export
- clk_clk : in std_logic;
- reset_reset_n : in std_logic;
- altpll_1_c0_clk : out std_logic;
- altpll_1_areset_conduit_export : in std_logic;
- altpll_1_phasedone_conduit_export : out std_logic;
- altpll_1_locked_conduit_export : out std_logic
- );
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ mm_clk : out std_logic; -- clk
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ phasedone_from_the_altpll_0 : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ tse_clk : out std_logic; -- clk
+ epcs_clk : out std_logic; -- clk
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0); -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ areset_to_the_altpll_0 : in std_logic := 'X'; -- export
+ locked_from_the_altpll_0 : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ c3_from_the_altpll_0 : out std_logic; -- export
+ ram_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_read_export : out std_logic; -- export
+ ram_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_write_export : out std_logic; -- export
+ ram_diag_data_buf_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_diag_data_buf_clk_export : out std_logic; -- export
+ ram_diag_data_buf_reset_export : out std_logic; -- export
+ reg_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_read_export : out std_logic; -- export
+ reg_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_write_export : out std_logic; -- export
+ reg_diag_data_buf_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_diag_data_buf_clk_export : out std_logic; -- export
+ reg_diag_data_buf_reset_export : out std_logic; -- export
+ clk_clk : in std_logic;
+ reset_reset_n : in std_logic;
+ altpll_1_c0_clk : out std_logic;
+ altpll_1_areset_conduit_export : in std_logic;
+ altpll_1_phasedone_conduit_export : out std_logic;
+ altpll_1_locked_conduit_export : out std_logic
+ );
end component qsys_unb1_correlator;
begin
mm_clk <= i_mm_clk;
@@ -200,24 +200,30 @@ begin
i_mm_clk <= not i_mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_clk_period * 5;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -237,7 +243,7 @@ begin
mm_clk => i_mm_clk,
tse_clk => eth1g_tse_clk,
- -- the_altpll_0
+ -- the_altpll_0
locked_from_the_altpll_0 => mm_locked,
phasedone_from_the_altpll_0 => OPEN,
areset_to_the_altpll_0 => xo_rst,
@@ -337,7 +343,7 @@ begin
altpll_1_areset_conduit_export => xo_rst,
altpll_1_phasedone_conduit_export => OPEN,
altpll_1_locked_conduit_export => open
- );
+ );
end generate;
end str;
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd
index d71467e0f7..cd673394c1 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, correlator_lib, diag_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb1_correlator is
generic (
@@ -139,14 +139,15 @@ architecture str of unb1_correlator is
-- it is not used by the correlator.
constant c_bg_blocks_per_sync : natural := largest(c_integration_period, c_nof_visibilities);
- constant c_bg_ctrl : t_diag_block_gen := ('1', -- enable
- '0', -- enable_sync
- TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '1', -- enable
+ '0', -- enable_sync
+ TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
signal block_gen_src_out_arr : t_dp_sosi_arr(c_nof_input_streams - 1 downto 0);
@@ -169,22 +170,22 @@ begin
-- initialization file using Python, see tb/python/gen_subband_hex_files.py
-----------------------------------------------------------------------------
u_mms_diag_block_gen : entity diag_lib.mms_diag_block_gen
- generic map (
- g_nof_streams => c_nof_input_streams,
- g_buf_dat_w => 2 * c_complex_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_name_prefix => "../../../libraries/dsp/correlator/src/hex/complex_subbands_" & natural'image(c_complex_data_w) & "b_" & "fold_" & natural'image(c_nof_input_folds),
- g_diag_block_gen_rst => c_bg_ctrl
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr
- );
+ generic map (
+ g_nof_streams => c_nof_input_streams,
+ g_buf_dat_w => 2 * c_complex_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_name_prefix => "../../../libraries/dsp/correlator/src/hex/complex_subbands_" & natural'image(c_complex_data_w) & "b_" & "fold_" & natural'image(c_nof_input_folds),
+ g_diag_block_gen_rst => c_bg_ctrl
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr
+ );
-----------------------------------------------------------------------------
-- Introduce gaps in the input stream
@@ -194,40 +195,40 @@ begin
-----------------------------------------------------------------------------
gen_dp_fifo_sc : for i in 0 to c_nof_input_streams - 1 generate
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
- generic map (
- g_data_w => 2 * c_complex_data_w,
- g_use_ctrl => false,
- g_use_complex => true,
- g_fifo_size => c_bg_block_size,
- g_fifo_af_margin => 0
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- wr_ful => OPEN,
- usedw => OPEN,
- rd_emp => OPEN,
-
- snk_out => OPEN,
- snk_in => block_gen_src_out_arr(i),
- src_in => dp_fifo_sc_src_in_arr(i),
- src_out => dp_fifo_sc_src_out_arr(i)
- );
+ generic map (
+ g_data_w => 2 * c_complex_data_w,
+ g_use_ctrl => false,
+ g_use_complex => true,
+ g_fifo_size => c_bg_block_size,
+ g_fifo_af_margin => 0
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ wr_ful => OPEN,
+ usedw => OPEN,
+ rd_emp => OPEN,
+
+ snk_out => OPEN,
+ snk_in => block_gen_src_out_arr(i),
+ src_in => dp_fifo_sc_src_in_arr(i),
+ src_out => dp_fifo_sc_src_out_arr(i)
+ );
end generate;
gen_dp_src_out_timer : for i in 0 to c_nof_input_streams - 1 generate
u_dp_src_out_timer : entity dp_lib.dp_src_out_timer
- generic map (
- g_block_period => c_block_period
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_fifo_sc_src_out_arr(i),
- snk_out => dp_fifo_sc_src_in_arr(i)
- );
+ generic map (
+ g_block_period => c_block_period
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => dp_fifo_sc_src_out_arr(i),
+ snk_out => dp_fifo_sc_src_in_arr(i)
+ );
end generate;
correlator_snk_in_arr <= dp_fifo_sc_src_out_arr;
@@ -236,196 +237,196 @@ begin
-- Correlator
-----------------------------------------------------------------------------
u_correlator : entity correlator_lib.correlator
- generic map (
- g_nof_input_streams => c_nof_input_streams,
- g_input_unfold_factor => c_nof_input_folds,
- g_nof_pre_mult_folds => c_nof_pre_mult_folds,
- g_data_w => c_complex_data_w,
- g_conjugate => c_conjugate,
- g_nof_channels => c_nof_channels,
- g_integration_period => c_integration_period
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
-
- snk_in_arr => correlator_snk_in_arr,
- src_out_arr => correlator_src_out_arr
- );
+ generic map (
+ g_nof_input_streams => c_nof_input_streams,
+ g_input_unfold_factor => c_nof_input_folds,
+ g_nof_pre_mult_folds => c_nof_pre_mult_folds,
+ g_data_w => c_complex_data_w,
+ g_conjugate => c_conjugate,
+ g_nof_channels => c_nof_channels,
+ g_integration_period => c_integration_period
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in_arr => correlator_snk_in_arr,
+ src_out_arr => correlator_src_out_arr
+ );
-----------------------------------------------------------------------------
-- Data buffer to be read out by Python
-----------------------------------------------------------------------------
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => 1,
- g_data_w => 64,
- g_data_type => e_complex,
- g_buf_nof_data => c_nof_visibilities,
- g_buf_use_sync => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
-
- in_sync => correlator_src_out_arr(0).sop,
- in_sosi_arr => correlator_src_out_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => 64,
+ g_data_type => e_complex,
+ g_buf_nof_data => c_nof_visibilities,
+ g_buf_use_sync => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+
+ in_sync => correlator_src_out_arr(0).sop,
+ in_sosi_arr => correlator_src_out_arr
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_dp_clk_use_pll => false -- Use altpll_1 in QSYS
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- epcs_clk => '0',
-
- dp_rst => dp_rst,
- dp_clk => OPEN, -- dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => '0',
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_dp_clk_use_pll => false -- Use altpll_1 in QSYS
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ epcs_clk => '0',
+
+ dp_rst => dp_rst,
+ dp_clk => OPEN, -- dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => '0',
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_correlator
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- clk_clk => CLK, -- altpll_1 ref clk (200MHz)
- clk_clk_in_reset_reset_n => xo_rst_n,
- altpll_1_c0_clk => dp_clk, -- altpll_1 output clock
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- . Data buffers
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ clk_clk => CLK, -- altpll_1 ref clk (200MHz)
+ clk_clk_in_reset_reset_n => xo_rst_n,
+ altpll_1_c0_clk => dp_clk, -- altpll_1 output clock
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- . Data buffers
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso
+ );
end str;
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd
index 2b9513a515..c4a8bcc852 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd
@@ -25,11 +25,11 @@
-- Usage:
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_correlator is
end tb_unb1_correlator;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
index 2eb064ad70..14ddd0e38d 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
@@ -22,19 +22,19 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-
--- Purpose:
--- . Keep g_nof_channels serialized accumulators in an array of circular buffers
--- Description:
--- . A single adder per input stream is used to keep g_nof_channels separate sums per stream.
--- . For each stream, the intermediate sums are preserved in a circular buffer (FIFO).
--- . The FIFOs output the running sum such that it aligns with the corresponding channel (to be added
--- to the stored channel sum) at the adder inputs.
--- . The accumulators are cleared on the incoming sync pulse.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+
+ -- Purpose:
+ -- . Keep g_nof_channels serialized accumulators in an array of circular buffers
+ -- Description:
+ -- . A single adder per input stream is used to keep g_nof_channels separate sums per stream.
+ -- . For each stream, the intermediate sums are preserved in a circular buffer (FIFO).
+ -- . The FIFOs output the running sum such that it aligns with the corresponding channel (to be added
+ -- to the stored channel sum) at the adder inputs.
+ -- . The accumulators are cleared on the incoming sync pulse.
entity corr_accumulator is
generic (
@@ -43,7 +43,7 @@ entity corr_accumulator is
g_nof_channel_accs : natural; -- Maximum number of timesamples to accumulate (per channel)
g_data_w : natural; -- Complex input data width
g_note_is_ful : boolean := false -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- -- when FALSE no note reports, to speed up simulation and avoid many notes
+ -- when FALSE no note reports, to speed up simulation and avoid many notes
);
port (
rst : in std_logic;
@@ -104,40 +104,40 @@ begin
-- Complex adder stage
-----------------------------------------------------------------------------
u_corr_adder : entity work.corr_adder
- generic map (
- g_nof_inputs => g_nof_inputs,
- g_data_w => c_acc_data_w
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in_2arr_2 => corr_adder_snk_in_2arr_2,
- src_out_arr => corr_adder_src_out_arr
- );
+ generic map (
+ g_nof_inputs => g_nof_inputs,
+ g_data_w => c_acc_data_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in_2arr_2 => corr_adder_snk_in_2arr_2,
+ src_out_arr => corr_adder_src_out_arr
+ );
-----------------------------------------------------------------------------
-- FIFOs to store the accumulator sums
-----------------------------------------------------------------------------
gen_dp_fifo_sc : for i in 0 to g_nof_inputs - 1 generate
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
- generic map (
- g_note_is_ful => g_note_is_ful,
- g_data_w => 2 * c_acc_data_w,
- g_use_ctrl => false,
- g_use_sync => sel_a_b(i = 0, true, false), -- Pass on sync of stream 0.
- g_use_complex => true,
- g_fifo_size => g_nof_channels,
- g_fifo_af_margin => 1
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => corr_adder_src_out_arr(i),
- src_in => dp_fifo_sc_src_in_arr(i),
- src_out => dp_fifo_sc_src_out_arr(i)
- );
+ generic map (
+ g_note_is_ful => g_note_is_ful,
+ g_data_w => 2 * c_acc_data_w,
+ g_use_ctrl => false,
+ g_use_sync => sel_a_b(i = 0, true, false), -- Pass on sync of stream 0.
+ g_use_complex => true,
+ g_fifo_size => g_nof_channels,
+ g_fifo_af_margin => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => corr_adder_src_out_arr(i),
+ src_in => dp_fifo_sc_src_in_arr(i),
+ src_out => dp_fifo_sc_src_out_arr(i)
+ );
-- Shift out the first accumulated value when it aligns with the corresponding current value at the adder input
-- . this produces the dp_fifo_sc_src_out_arr data in sync with reg_snk_in_arr data
diff --git a/libraries/dsp/correlator/src/vhdl/corr_adder.vhd b/libraries/dsp/correlator/src/vhdl/corr_adder.vhd
index dd81519562..decc4752a0 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_adder.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_adder.vhd
@@ -20,23 +20,23 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
--- Purpose:
--- . Provide an array of complex adders with streaming I/O
--- Description:
--- . Adds snk_in_2arr_2[i][0] to snk_in_2arr_2[i][1] yielding
--- src_out_arr[i] for i in 0..g_nof_inputs-1.
--- . Valid is taken from snk_in_2arr_2(i)(0) only.
+ -- Purpose:
+ -- . Provide an array of complex adders with streaming I/O
+ -- Description:
+ -- . Adds snk_in_2arr_2[i][0] to snk_in_2arr_2[i][1] yielding
+ -- src_out_arr[i] for i in 0..g_nof_inputs-1.
+ -- . Valid is taken from snk_in_2arr_2(i)(0) only.
entity corr_adder is
generic (
g_nof_inputs : natural;
g_data_w : natural
- );
+ );
port (
rst : in std_logic;
clk : in std_logic;
@@ -64,53 +64,53 @@ begin
-----------------------------------------------------------------------------
gen_common_pipeline_sl : for i in 0 to g_nof_inputs - 1 generate
u_common_pipeline_sl : entity common_lib.common_pipeline_sl
+ generic map (
+ g_pipeline => c_pipeline_depth
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => snk_in_2arr_2(i)(0).valid,
+ out_dat => src_out_arr(i).valid
+ );
+ end generate;
+
+ -----------------------------------------------------------------------------
+ -- Delay sync signal of output 0
+ -----------------------------------------------------------------------------
+ u_common_pipeline_sl : entity common_lib.common_pipeline_sl
generic map (
g_pipeline => c_pipeline_depth
)
port map (
rst => rst,
clk => clk,
- in_dat => snk_in_2arr_2(i)(0).valid,
- out_dat => src_out_arr(i).valid
+ in_dat => snk_in_2arr_2(0)(0).sync,
+ out_dat => src_out_arr(0).sync
);
- end generate;
-
- -----------------------------------------------------------------------------
- -- Delay sync signal of output 0
- -----------------------------------------------------------------------------
- u_common_pipeline_sl : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_depth
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => snk_in_2arr_2(0)(0).sync,
- out_dat => src_out_arr(0).sync
- );
-----------------------------------------------------------------------------
-- Complex adder
-----------------------------------------------------------------------------
gen_common_complex_add_sub : for i in 0 to g_nof_inputs - 1 generate
u_common_complex_add_sub : entity common_lib.common_complex_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => c_input_pipeline_depth,
- g_pipeline_output => c_output_pipeline_depth,
- g_in_dat_w => g_data_w,
- g_out_dat_w => g_data_w + 1
- )
- port map (
- clk => clk,
- in_ar => snk_in_2arr_2(i)(0).re(g_data_w - 1 downto 0),
- in_ai => snk_in_2arr_2(i)(0).im(g_data_w - 1 downto 0),
- in_br => snk_in_2arr_2(i)(1).re(g_data_w - 1 downto 0),
- in_bi => snk_in_2arr_2(i)(1).im(g_data_w - 1 downto 0),
- out_re => common_complex_add_sub_src_out_arr(i).re(g_data_w + 1 - 1 downto 0),
- out_im => common_complex_add_sub_src_out_arr(i).im(g_data_w + 1 - 1 downto 0)
- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => c_input_pipeline_depth,
+ g_pipeline_output => c_output_pipeline_depth,
+ g_in_dat_w => g_data_w,
+ g_out_dat_w => g_data_w + 1
+ )
+ port map (
+ clk => clk,
+ in_ar => snk_in_2arr_2(i)(0).re(g_data_w - 1 downto 0),
+ in_ai => snk_in_2arr_2(i)(0).im(g_data_w - 1 downto 0),
+ in_br => snk_in_2arr_2(i)(1).re(g_data_w - 1 downto 0),
+ in_bi => snk_in_2arr_2(i)(1).im(g_data_w - 1 downto 0),
+ out_re => common_complex_add_sub_src_out_arr(i).re(g_data_w + 1 - 1 downto 0),
+ out_im => common_complex_add_sub_src_out_arr(i).im(g_data_w + 1 - 1 downto 0)
+ );
end generate;
-----------------------------------------------------------------------------
diff --git a/libraries/dsp/correlator/src/vhdl/corr_carousel.vhd b/libraries/dsp/correlator/src/vhdl/corr_carousel.vhd
index 3664435b34..3555ef9fa2 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_carousel.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_carousel.vhd
@@ -20,27 +20,27 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
--- Purpose:
--- . Outputs all unique pair permutations of the words at the inputs.
--- Description:
--- . Example permutations of [0,1,2]: [[0,0],[0,1],[0,2],[1,2],[1,1],[2,2]]
--- . c_nof_permutations = g_nof_inputs*(g_nof_inputs+1)/2
--- . Each permutation can be used to calculate one unique visibility.
--- . snk_in_arr(0).valid is used to indicate validity of all inputs.
--- Usage:
--- . Determine g_nof_inputs; e.g. 3
--- . Calculate c_nof_permutations: e.g. 6
--- . Note your output options, e.g.
--- . 6 cycles * 1 output
--- . 3 cycles * 2 outputs
--- . 2 cycles * 3 outputs
--- . 1 cycle * 6 outputs
--- . Set your g_nof_outputs accordingly.
+ -- Purpose:
+ -- . Outputs all unique pair permutations of the words at the inputs.
+ -- Description:
+ -- . Example permutations of [0,1,2]: [[0,0],[0,1],[0,2],[1,2],[1,1],[2,2]]
+ -- . c_nof_permutations = g_nof_inputs*(g_nof_inputs+1)/2
+ -- . Each permutation can be used to calculate one unique visibility.
+ -- . snk_in_arr(0).valid is used to indicate validity of all inputs.
+ -- Usage:
+ -- . Determine g_nof_inputs; e.g. 3
+ -- . Calculate c_nof_permutations: e.g. 6
+ -- . Note your output options, e.g.
+ -- . 6 cycles * 1 output
+ -- . 3 cycles * 2 outputs
+ -- . 2 cycles * 3 outputs
+ -- . 1 cycle * 6 outputs
+ -- . Set your g_nof_outputs accordingly.
entity corr_carousel is
generic (
diff --git a/libraries/dsp/correlator/src/vhdl/corr_folder.vhd b/libraries/dsp/correlator/src/vhdl/corr_folder.vhd
index 99c1a7805c..25eda3cc78 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_folder.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_folder.vhd
@@ -20,21 +20,21 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-
--- Purpose:
--- Description:
--- . nof_outputs = ceil_div(g_nof_inputs, 2^(g_nof_folds)) for g_nof_folds>=0
--- . Examples:
--- . g_nof_inputs=10, g_nof_folds=0 -> nof_outputs=10
--- . g_nof_inputs=10, g_nof_folds=1 -> nof_outputs= 5
--- . g_nof_inputs=10, g_nof_folds=2 -> nof_outputs= 3
--- . g_nof_inputs=10, g_nof_folds=3 -> nof_outputs= 2
--- . g_nof_inputs=10, g_nof_folds=4 -> nof_outputs= 1
--- . g_nof_inputs=10, g_nof_folds<0 -> nof_outputs= 1
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+
+ -- Purpose:
+ -- Description:
+ -- . nof_outputs = ceil_div(g_nof_inputs, 2^(g_nof_folds)) for g_nof_folds>=0
+ -- . Examples:
+ -- . g_nof_inputs=10, g_nof_folds=0 -> nof_outputs=10
+ -- . g_nof_inputs=10, g_nof_folds=1 -> nof_outputs= 5
+ -- . g_nof_inputs=10, g_nof_folds=2 -> nof_outputs= 3
+ -- . g_nof_inputs=10, g_nof_folds=3 -> nof_outputs= 2
+ -- . g_nof_inputs=10, g_nof_folds=4 -> nof_outputs= 1
+ -- . g_nof_inputs=10, g_nof_folds<0 -> nof_outputs= 1
entity corr_folder is
generic (
diff --git a/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd b/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd
index 0c96de2937..92ad02e462 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd
@@ -20,17 +20,17 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-
--- Purpose:
--- . Wrapper for corr_folder that allows the use of t_dp_sosi_2arr_2
--- Description:
--- . Our input is an array of g_nof_inputs*2 sosi buses
--- . Our 2 corr_folder instances below accept an array of 2*g_nof_inputs sosi buses
--- => We need to do a tranposed signal assignment.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+
+ -- Purpose:
+ -- . Wrapper for corr_folder that allows the use of t_dp_sosi_2arr_2
+ -- Description:
+ -- . Our input is an array of g_nof_inputs*2 sosi buses
+ -- . Our 2 corr_folder instances below accept an array of 2*g_nof_inputs sosi buses
+ -- => We need to do a tranposed signal assignment.
entity corr_folder_2arr_2 is
generic (
@@ -65,16 +65,16 @@ begin
-- (0)(0). Since the accumulator now uses a block sync, we need to preserve
-- the sync of all inputs.
------------------------------------------------------------------------------
--- p_dp_pipeline_snk_in_2arr_2: PROCESS(snk_in_2arr_2)
--- BEGIN
--- dp_pipeline_snk_in_2arr_2 <= snk_in_2arr_2;
--- FOR i IN 0 TO g_nof_inputs-1 LOOP
--- FOR j IN 0 TO 2-1 LOOP
--- dp_pipeline_snk_in_2arr_2(i)(j).sync <= '0';
--- END LOOP;
--- END LOOP;
--- dp_pipeline_snk_in_2arr_2(0)(0).sync <= snk_in_2arr_2(0)(0).sync;
--- END PROCESS;
+ -- p_dp_pipeline_snk_in_2arr_2: PROCESS(snk_in_2arr_2)
+ -- BEGIN
+ -- dp_pipeline_snk_in_2arr_2 <= snk_in_2arr_2;
+ -- FOR i IN 0 TO g_nof_inputs-1 LOOP
+ -- FOR j IN 0 TO 2-1 LOOP
+ -- dp_pipeline_snk_in_2arr_2(i)(j).sync <= '0';
+ -- END LOOP;
+ -- END LOOP;
+ -- dp_pipeline_snk_in_2arr_2(0)(0).sync <= snk_in_2arr_2(0)(0).sync;
+ -- END PROCESS;
dp_pipeline_snk_in_2arr_2 <= snk_in_2arr_2;
-----------------------------------------------------------------------------
@@ -91,16 +91,16 @@ begin
gen_dp_pipeline_src_out_2arr2 : for i in 0 to g_nof_inputs - 1 generate
gen_dp_pipeline : for j in 0 to 2 - 1 generate
u_dp_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => 0 + (i rem pow2(g_nof_folds))
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => dp_pipeline_snk_in_2arr_2(i)(j),
- src_out => dp_pipeline_src_out_2arr_2(i)(j)
- );
+ generic map (
+ g_pipeline => 0 + (i rem pow2(g_nof_folds))
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => dp_pipeline_snk_in_2arr_2(i)(j),
+ src_out => dp_pipeline_src_out_2arr_2(i)(j)
+ );
end generate;
end generate;
@@ -118,18 +118,18 @@ begin
------------------------------------------------------------------------------
gen_corr_folder: for i in 0 to 2 - 1 generate
u_corr_folder : entity work.corr_folder
- generic map (
- g_nof_inputs => g_nof_inputs,
- g_nof_folds => g_nof_folds
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in_arr => corr_folder_snk_in_2arr(i),
-
- src_out_arr => corr_folder_src_out_2arr(i)
- );
+ generic map (
+ g_nof_inputs => g_nof_inputs,
+ g_nof_folds => g_nof_folds
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in_arr => corr_folder_snk_in_2arr(i),
+
+ src_out_arr => corr_folder_src_out_2arr(i)
+ );
end generate;
------------------------------------------------------------------------------
diff --git a/libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd b/libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd
index 97a02c1aa4..e51f914fe5 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd
@@ -20,24 +20,24 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
--- Purpose:
--- . Provide an array of multipliers with streaming I/O
--- Description:
--- . Multiplies snk_in_2arr_2[i][0] with snk_in_2arr_2[i][1] yielding
--- src_out_2arr[i] for i in 0..g_nof_inputs-1.
+ -- Purpose:
+ -- . Provide an array of multipliers with streaming I/O
+ -- Description:
+ -- . Multiplies snk_in_2arr_2[i][0] with snk_in_2arr_2[i][1] yielding
+ -- src_out_2arr[i] for i in 0..g_nof_inputs-1.
entity corr_multiplier is
generic (
g_technology : natural := c_tech_select_default;
g_nof_inputs : natural;
g_data_w : natural
- );
+ );
port (
rst : in std_logic;
clk : in std_logic;
@@ -65,31 +65,31 @@ begin
-----------------------------------------------------------------------------
gen_common_complex_mult : for i in 0 to g_nof_inputs - 1 generate
u_common_complex_mult : entity common_mult_lib.common_complex_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => g_data_w,
- g_in_b_w => g_data_w,
- g_out_p_w => 2 * g_data_w, -- default use g_out_p_w = g_in_a_w+g_in_b_w
- g_conjugate_b => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_product => c_pipeline_product,
- g_pipeline_adder => c_pipeline_adder,
- g_pipeline_output => c_pipeline_output
- )
- port map (
- clk => clk,
- clken => '1',
- rst => '0',
- in_ar => snk_in_2arr_2(i)(0).re(g_data_w - 1 downto 0),
- in_ai => snk_in_2arr_2(i)(0).im(g_data_w - 1 downto 0),
- in_br => snk_in_2arr_2(i)(1).re(g_data_w - 1 downto 0),
- in_bi => snk_in_2arr_2(i)(1).im(g_data_w - 1 downto 0),
- in_val => snk_in_2arr_2(i)(0).valid,
- out_pr => common_complex_mult_src_out_arr(i).re(2 * g_data_w - 1 downto 0),
- out_pi => common_complex_mult_src_out_arr(i).im(2 * g_data_w - 1 downto 0),
- out_val => common_complex_mult_src_out_arr(i).valid
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => g_data_w,
+ g_in_b_w => g_data_w,
+ g_out_p_w => 2 * g_data_w, -- default use g_out_p_w = g_in_a_w+g_in_b_w
+ g_conjugate_b => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_product => c_pipeline_product,
+ g_pipeline_adder => c_pipeline_adder,
+ g_pipeline_output => c_pipeline_output
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ rst => '0',
+ in_ar => snk_in_2arr_2(i)(0).re(g_data_w - 1 downto 0),
+ in_ai => snk_in_2arr_2(i)(0).im(g_data_w - 1 downto 0),
+ in_br => snk_in_2arr_2(i)(1).re(g_data_w - 1 downto 0),
+ in_bi => snk_in_2arr_2(i)(1).im(g_data_w - 1 downto 0),
+ in_val => snk_in_2arr_2(i)(0).valid,
+ out_pr => common_complex_mult_src_out_arr(i).re(2 * g_data_w - 1 downto 0),
+ out_pi => common_complex_mult_src_out_arr(i).im(2 * g_data_w - 1 downto 0),
+ out_val => common_complex_mult_src_out_arr(i).valid
+ );
src_out_arr(i).re <= RESIZE_DP_DSP_DATA(common_complex_mult_src_out_arr(i).re(2 * g_data_w - 1 downto 0));
src_out_arr(i).im <= RESIZE_DP_DSP_DATA(common_complex_mult_src_out_arr(i).im(2 * g_data_w - 1 downto 0));
@@ -99,15 +99,15 @@ begin
-----------------------------------------------------------------------------
-- Forward the input sync with the correct latency
-----------------------------------------------------------------------------
- u_common_pipeline_sl : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
+ u_common_pipeline_sl : entity common_lib.common_pipeline_sl
+ generic map (
+ g_pipeline => c_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_dat => snk_in_2arr_2(0)(0).sync,
- out_dat => src_out_arr(0).sync
- );
+ in_dat => snk_in_2arr_2(0)(0).sync,
+ out_dat => src_out_arr(0).sync
+ );
end str;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd b/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
index dffbdd2202..f460eba4ac 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
@@ -20,19 +20,19 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-
--- Purpose:
--- . Forward input stream with added channel (and optional sync, BSN) field
--- Description:
--- . The above is implemented as follows:
--- . dp_block_gen_sop_eop_sync generates the SOP, EOP and Sync
--- . A clocked process adds:
--- . channel based on SOP.
--- . the BSN based on Sync.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+
+ -- Purpose:
+ -- . Forward input stream with added channel (and optional sync, BSN) field
+ -- Description:
+ -- . The above is implemented as follows:
+ -- . dp_block_gen_sop_eop_sync generates the SOP, EOP and Sync
+ -- . A clocked process adds:
+ -- . channel based on SOP.
+ -- . the BSN based on Sync.
entity corr_output_framer is
generic (
@@ -69,19 +69,19 @@ begin
-- dp_block_gen to create correc SOP,EOP and Sync
-----------------------------------------------------------------------------
u_dp_block_gen_sop_eop_sync: entity dp_lib.dp_block_gen
- generic map (
- g_use_src_in => false,
- g_nof_data => g_nof_channels * pow2(g_nof_folds),
- g_nof_blk_per_sync => g_nof_channel_frames_per_sync
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => snk_in_arr(0),
-
- src_out => dp_block_gen_src_out
- );
+ generic map (
+ g_use_src_in => false,
+ g_nof_data => g_nof_channels * pow2(g_nof_folds),
+ g_nof_blk_per_sync => g_nof_channel_frames_per_sync
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => snk_in_arr(0),
+
+ src_out => dp_block_gen_src_out
+ );
-----------------------------------------------------------------------------
-- Create channel (based on SOP) and BSN (based on Sync)
@@ -123,8 +123,8 @@ begin
for i in 0 to g_nof_streams - 1 loop
channel_bsn_src_out.channel <= X"FFFFFFFF"; -- Wrap to 0 on first increment
channel_bsn_src_out.bsn <= X"FFFFFFFF_FFFFFFFF"; -- Wrap to 0 on first increment
--- channel_bsn_src_out.channel <= (OTHERS=>'0');
--- channel_bsn_src_out.bsn <= (OTHERS=>'0');
+ -- channel_bsn_src_out.channel <= (OTHERS=>'0');
+ -- channel_bsn_src_out.bsn <= (OTHERS=>'0');
folded_word_cnt <= (others => '1'); -- Wrap to 0 on first increment
end loop;
elsif rising_edge(clk) then
@@ -139,16 +139,16 @@ begin
-----------------------------------------------------------------------------
gen_dp_pipeline : for i in 0 to g_nof_streams - 1 generate
u_dp_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => 2
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => snk_in_arr(i),
- src_out => dp_pipeline_src_out_arr(i)
- );
+ generic map (
+ g_pipeline => 2
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => snk_in_arr(i),
+ src_out => dp_pipeline_src_out_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
diff --git a/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd b/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd
index 376b3babdd..28df3dbee5 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd
@@ -20,25 +20,25 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-
--- Purpose:
--- . Outputs all unique pair permutations of the words at the inputs.
--- Description:
--- . c_nof_permutations = g_nof_inputs*(g_nof_inputs+1)/2
--- . Example permutations of [0,1,2]: [[0,0],[0,1],[0,2],[1,1],[1,2],[2,2]]
--- . Note the order of the permutations; low pairs to high pairs
--- . All inputs to permutate (snk_in_arr) must be valid on one and the same clock cycle.
--- . Process p_permu_wires is wires only and provides all permutations
--- instantaniously, in parallel:
--- . Low pair [snk_in_arr[0], snk_in_arr[0] ] on permu_out_2arr_2[0]
--- . ..
--- . ..
--- . High pair [snk_in_arr[g_nof_inputs-1],snk_in_arr[g_nof_inputs-1]] on permu_out_2arr_2[g_nof_inputs-1]
--- . Both the input and the output of process p_permu_wires are registered by default.
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+
+ -- Purpose:
+ -- . Outputs all unique pair permutations of the words at the inputs.
+ -- Description:
+ -- . c_nof_permutations = g_nof_inputs*(g_nof_inputs+1)/2
+ -- . Example permutations of [0,1,2]: [[0,0],[0,1],[0,2],[1,1],[1,2],[2,2]]
+ -- . Note the order of the permutations; low pairs to high pairs
+ -- . All inputs to permutate (snk_in_arr) must be valid on one and the same clock cycle.
+ -- . Process p_permu_wires is wires only and provides all permutations
+ -- instantaniously, in parallel:
+ -- . Low pair [snk_in_arr[0], snk_in_arr[0] ] on permu_out_2arr_2[0]
+ -- . ..
+ -- . ..
+ -- . High pair [snk_in_arr[g_nof_inputs-1],snk_in_arr[g_nof_inputs-1]] on permu_out_2arr_2[g_nof_inputs-1]
+ -- . Both the input and the output of process p_permu_wires are registered by default.
entity corr_permutator is
generic (
@@ -74,7 +74,7 @@ begin
-----------------------------------------------------------------------------
gen_input: for i in 0 to g_nof_inputs - 1 generate
gen_input: for j in 0 to g_nof_inputs - 1 generate
- permu_in_2arr(i)(j) <= reg_snk_in_arr(i);
+ permu_in_2arr(i)(j) <= reg_snk_in_arr(i);
end generate;
end generate;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd b/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
index 9289aa4847..95d429483f 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
@@ -22,16 +22,16 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.corr_permutor_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.corr_permutor_pkg.all;
--- Purpose:
--- . Outputs all unique pair permutations of the words at the inputs.
--- Description:
--- .
+ -- Purpose:
+ -- . Outputs all unique pair permutations of the words at the inputs.
+ -- Description:
+ -- .
entity corr_permutor is
generic (
@@ -85,30 +85,30 @@ begin
common_paged_reg_wr_im_arr(i) <= snk_in_arr(i).im(g_data_w - 1 downto 0);
u_common_paged_reg_re : entity common_lib.common_paged_reg
- generic map (
- g_data_w => g_data_w,
- g_nof_pages => 1
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en(0) => snk_in_arr(0).valid,
- wr_dat => common_paged_reg_wr_re_arr(i),
- out_dat => common_paged_reg_out_re_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_nof_pages => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en(0) => snk_in_arr(0).valid,
+ wr_dat => common_paged_reg_wr_re_arr(i),
+ out_dat => common_paged_reg_out_re_arr(i)
+ );
u_common_paged_reg_im : entity common_lib.common_paged_reg
- generic map (
- g_data_w => g_data_w,
- g_nof_pages => 1
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en(0) => snk_in_arr(0).valid,
- wr_dat => common_paged_reg_wr_im_arr(i),
- out_dat => common_paged_reg_out_im_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_nof_pages => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en(0) => snk_in_arr(0).valid,
+ wr_dat => common_paged_reg_wr_im_arr(i),
+ out_dat => common_paged_reg_out_im_arr(i)
+ );
common_paged_reg_src_out_arr(i).re <= RESIZE_DP_DSP_DATA(common_paged_reg_out_re_arr(i));
common_paged_reg_src_out_arr(i).im <= RESIZE_DP_DSP_DATA(common_paged_reg_out_im_arr(i));
@@ -159,28 +159,28 @@ begin
-- level.
-----------------------------------------------------------------------------
u_common_pulse_extend_sync : entity common_lib.common_pulse_extend
- generic map (
- g_nof_cycles => g_nof_cycles
- )
- port map (
- clk => clk,
- rst => rst,
-
- p_in => snk_in_arr(0).sync,
- ep_out => common_pulse_extend_ep_out_sync
- );
+ generic map (
+ g_nof_cycles => g_nof_cycles
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ p_in => snk_in_arr(0).sync,
+ ep_out => common_pulse_extend_ep_out_sync
+ );
u_common_pulse_extend_valid : entity common_lib.common_pulse_extend
- generic map (
- g_nof_cycles => g_nof_cycles
- )
- port map (
- clk => clk,
- rst => rst,
-
- p_in => snk_in_arr(0).valid,
- ep_out => common_pulse_extend_ep_out_valid
- );
+ generic map (
+ g_nof_cycles => g_nof_cycles
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ p_in => snk_in_arr(0).valid,
+ ep_out => common_pulse_extend_ep_out_valid
+ );
-----------------------------------------------------------------------------
-- Output
@@ -209,11 +209,11 @@ begin
if rst = '1' then
cycle_cnt <= (others => '0');
perm_2arr_2 <= (others => (others => c_dp_sosi_rst));
--- snk_out_arr <= (OTHERS=>c_dp_siso_rst);
+ -- snk_out_arr <= (OTHERS=>c_dp_siso_rst);
elsif rising_edge(clk) then
cycle_cnt <= nxt_cycle_cnt;
perm_2arr_2 <= nxt_perm_2arr_2;
--- snk_out_arr <= nxt_snk_out_arr;
+ -- snk_out_arr <= nxt_snk_out_arr;
end if;
end process;
end rtl;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd b/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
index fe370e1429..b709825b79 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
@@ -22,9 +22,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package corr_permutor_pkg is
-- 3D array of dimensions nof_folding_cycles*nof_outputs*2 input indices
diff --git a/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd b/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd
index dc3d2e83c1..05ceb8db73 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd
@@ -20,13 +20,13 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
--- Purpose:
--- Description:
+ -- Purpose:
+ -- Description:
entity corr_unfolder is
generic (
@@ -86,8 +86,8 @@ begin
-- Wire the 2D demux output array to 1D array to match entity I/O type
-----------------------------------------------------------------------------
gen_demux_inputs_0: for i in 0 to c_nof_demuxes - 1 generate
- demux_src_out_arr(2 * i) <= demux_src_out_2arr_2(i)(0);
- demux_src_out_arr(2 * i + 1) <= demux_src_out_2arr_2(i)(1);
+ demux_src_out_arr(2 * i) <= demux_src_out_2arr_2(i)(0);
+ demux_src_out_arr(2 * i + 1) <= demux_src_out_2arr_2(i)(1);
end generate;
-----------------------------------------------------------------------------
@@ -116,16 +116,16 @@ begin
-----------------------------------------------------------------------------
gen_dp_pipeline : for i in 0 to c_nof_outputs - 1 generate
u_dp_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => 0 + (pow2(g_nof_unfolds) - i rem pow2(g_nof_unfolds) - 1)
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => dp_pipeline_snk_in_arr(i),
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_pipeline => 0 + (pow2(g_nof_unfolds) - i rem pow2(g_nof_unfolds) - 1)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => dp_pipeline_snk_in_arr(i),
+ src_out => src_out_arr(i)
+ );
end generate;
end generate;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_visibility_buffer.vhd b/libraries/dsp/correlator/src/vhdl/corr_visibility_buffer.vhd
index 956bc3934e..50d2e3fca3 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_visibility_buffer.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_visibility_buffer.vhd
@@ -20,22 +20,22 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
--- Purpose:
--- . Buffer the visibilities during folding
--- Description:
--- . Consists of an array of FIFOs that are read out periodically.
--- . The output data rate is such that all output streams can be folded into
--- one stream (valid cycles/stream never occur in parallel)
--- . In addition, the FIFOs are read out such that the folder outputs channel
--- blocks of visibilities.
--- . Finally, the output stream is toggled to produce a constant flow
--- instead of a short burst (to the extent that it is allowed by the
--- integration time - a short integration time leaves little headroom).
+ -- Purpose:
+ -- . Buffer the visibilities during folding
+ -- Description:
+ -- . Consists of an array of FIFOs that are read out periodically.
+ -- . The output data rate is such that all output streams can be folded into
+ -- one stream (valid cycles/stream never occur in parallel)
+ -- . In addition, the FIFOs are read out such that the folder outputs channel
+ -- blocks of visibilities.
+ -- . Finally, the output stream is toggled to produce a constant flow
+ -- instead of a short burst (to the extent that it is allowed by the
+ -- integration time - a short integration time leaves little headroom).
entity corr_visibility_buffer is
generic (
@@ -44,7 +44,7 @@ entity corr_visibility_buffer is
g_data_w : natural; -- Complex input data width
g_nof_pre_mult_folds : natural; -- Nof times the data has been folded
g_inter_channel_delay : natural -- Nof delay cycles between output channels
- );
+ );
port (
rst : in std_logic;
clk : in std_logic;
@@ -98,27 +98,27 @@ begin
------------------------------------------------------------------------------
gen_dp_fifo_sc : for i in 0 to g_nof_inputs - 1 generate
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
- generic map (
- g_data_w => 2 * g_data_w,
- g_use_ctrl => false,
- g_use_sync => sel_a_b(i = 0, true, false), -- Pass on sync of stream 0.
- g_use_complex => true,
- g_fifo_size => g_buffer_depth,
- g_fifo_af_margin => 0
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_data_w => 2 * g_data_w,
+ g_use_ctrl => false,
+ g_use_sync => sel_a_b(i = 0, true, false), -- Pass on sync of stream 0.
+ g_use_complex => true,
+ g_fifo_size => g_buffer_depth,
+ g_fifo_af_margin => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- wr_ful => OPEN,
- usedw => OPEN,
- rd_emp => OPEN,
+ wr_ful => OPEN,
+ usedw => OPEN,
+ rd_emp => OPEN,
- snk_out => OPEN,
- snk_in => snk_in_arr(i),
- src_in => dp_fifo_sc_src_in_arr(i),
- src_out => dp_fifo_sc_src_out_arr(i)
- );
+ snk_out => OPEN,
+ snk_in => snk_in_arr(i),
+ src_in => dp_fifo_sc_src_in_arr(i),
+ src_out => dp_fifo_sc_src_out_arr(i)
+ );
end generate;
------------------------------------------------------------------------------
@@ -147,20 +147,20 @@ begin
------------------------------------------------------------------------------
gen_dp_src_out_timer : for i in 0 to g_nof_inputs - 1 generate
u_dp_src_out_timer : entity dp_lib.dp_src_out_timer
- generic map (
- g_init_valid_delay => i * c_vis_block_len, -- relative to dp_fifo_sc_src_out_arr(i).valid
- g_block_period => c_channel_block_length + g_inter_channel_delay,
- g_block_len => c_vis_block_len
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_init_valid_delay => i * c_vis_block_len, -- relative to dp_fifo_sc_src_out_arr(i).valid
+ g_block_period => c_channel_block_length + g_inter_channel_delay,
+ g_block_len => c_vis_block_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- init_valid_delay_ref => snk_in_arr(i).valid,
+ init_valid_delay_ref => snk_in_arr(i).valid,
- snk_in => dp_fifo_sc_src_out_arr(i),
- snk_out => dp_fifo_sc_src_in_arr(i)
- );
+ snk_in => dp_fifo_sc_src_out_arr(i),
+ snk_out => dp_fifo_sc_src_in_arr(i)
+ );
end generate;
src_out_arr <= dp_fifo_sc_src_out_arr;
diff --git a/libraries/dsp/correlator/src/vhdl/correlator_dev.vhd b/libraries/dsp/correlator/src/vhdl/correlator_dev.vhd
index 677ab17f96..95bf0af78d 100644
--- a/libraries/dsp/correlator/src/vhdl/correlator_dev.vhd
+++ b/libraries/dsp/correlator/src/vhdl/correlator_dev.vhd
@@ -22,37 +22,37 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
--- Purpose:
--- . Calculate the cross- and auto correlations of g_nof_inputs inputs for multiple channels using a specified number of multipliers
--- Description:
--- . Number of visibilities (nof_visibilities): (g_nof_inputs*(g_nof_inputs+1))/2
--- . Example: With 24 inputs, nof_visibilities = 24*(24+1)/2=300
--- . One visibility v for one channel of one input pair i0,i1 is calculated as follows: v=accumulate(i0*conj(i1))
--- . Serialization a.k.a folding:
--- . g_nof_mults*g_nof_cycles=nof_visibilities
--- . These 2 generics determine in how many clock cycles the visibilities are produced.
--- . Note: The product (nof_mults*nof_serialization_cycles) must be equal to nof_visibilities!
--- . Examples: (300, 1) = 300 mults* 1 clock cycle (produce all 300 visibilities in one clock cycle)
--- (150, 2) = 150 mults* 2 clock cycles
--- (100, 3) = 100 mults* 3 clock cycles
--- ( 75, 4) = 75 mults* 4 clock cycles
--- ( 60, 5) = 60 mults* 5 clock cycles
--- ( 50, 6) = 50 mults* 6 clock cycles
--- ( 30,10) = 30 mults*10 clock cycles (produce all 300 visibilities in 10 clock cycles)
--- . When serializing the permutation pairs (g_nof_cycles>1), introduce gaps in the input data accordingly.
--- . Channels
--- . For each input stream, g_nof_channels are allowed to be fed in series.
--- . Accumulators
--- . For each (channel per) visibility, an individual accumulator is kept.
--- . The accumulators are emptied on snk_in(0).sync.
--- . To empty the accumulators, assert snk_in(0).sync on the last valid data of your integration period.
--- . g_nof_channel_accs determines the data width of the accumulators.
+ -- Purpose:
+ -- . Calculate the cross- and auto correlations of g_nof_inputs inputs for multiple channels using a specified number of multipliers
+ -- Description:
+ -- . Number of visibilities (nof_visibilities): (g_nof_inputs*(g_nof_inputs+1))/2
+ -- . Example: With 24 inputs, nof_visibilities = 24*(24+1)/2=300
+ -- . One visibility v for one channel of one input pair i0,i1 is calculated as follows: v=accumulate(i0*conj(i1))
+ -- . Serialization a.k.a folding:
+ -- . g_nof_mults*g_nof_cycles=nof_visibilities
+ -- . These 2 generics determine in how many clock cycles the visibilities are produced.
+ -- . Note: The product (nof_mults*nof_serialization_cycles) must be equal to nof_visibilities!
+ -- . Examples: (300, 1) = 300 mults* 1 clock cycle (produce all 300 visibilities in one clock cycle)
+ -- (150, 2) = 150 mults* 2 clock cycles
+ -- (100, 3) = 100 mults* 3 clock cycles
+ -- ( 75, 4) = 75 mults* 4 clock cycles
+ -- ( 60, 5) = 60 mults* 5 clock cycles
+ -- ( 50, 6) = 50 mults* 6 clock cycles
+ -- ( 30,10) = 30 mults*10 clock cycles (produce all 300 visibilities in 10 clock cycles)
+ -- . When serializing the permutation pairs (g_nof_cycles>1), introduce gaps in the input data accordingly.
+ -- . Channels
+ -- . For each input stream, g_nof_channels are allowed to be fed in series.
+ -- . Accumulators
+ -- . For each (channel per) visibility, an individual accumulator is kept.
+ -- . The accumulators are emptied on snk_in(0).sync.
+ -- . To empty the accumulators, assert snk_in(0).sync on the last valid data of your integration period.
+ -- . g_nof_channel_accs determines the data width of the accumulators.
entity correlator_dev is
generic (
@@ -87,53 +87,53 @@ begin
-- . Also performs serialization
-----------------------------------------------------------------------------
u_corr_permutor : entity work.corr_permutor
- generic map (
- g_nof_inputs => g_nof_inputs,
- g_nof_outputs => g_nof_mults,
- g_nof_cycles => g_nof_cycles,
- g_data_w => g_data_w
- )
- port map (
- clk => clk,
- rst => rst,
+ generic map (
+ g_nof_inputs => g_nof_inputs,
+ g_nof_outputs => g_nof_mults,
+ g_nof_cycles => g_nof_cycles,
+ g_data_w => g_data_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
- snk_in_arr => snk_in_arr,
- snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ snk_out_arr => snk_out_arr,
- src_out_2arr_2 => corr_permutor_src_out_2arr_2
- );
+ src_out_2arr_2 => corr_permutor_src_out_2arr_2
+ );
-----------------------------------------------------------------------------
-- Complex multiplier stage
-----------------------------------------------------------------------------
u_corr_multiplier : entity work.corr_multiplier
- generic map (
- g_nof_inputs => g_nof_mults,
- g_data_w => g_data_w
- )
- port map (
- clk => clk,
- rst => rst,
+ generic map (
+ g_nof_inputs => g_nof_mults,
+ g_data_w => g_data_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
- snk_in_2arr_2 => corr_permutor_src_out_2arr_2,
- src_out_arr => corr_multiplier_src_out_arr
- );
+ snk_in_2arr_2 => corr_permutor_src_out_2arr_2,
+ src_out_arr => corr_multiplier_src_out_arr
+ );
-----------------------------------------------------------------------------
-- Accumulator stage
-----------------------------------------------------------------------------
u_corr_accumulator : entity work.corr_accumulator
- generic map (
- g_nof_inputs => g_nof_mults,
- g_nof_channels => c_nof_accumulators,
- g_nof_channel_accs => g_nof_channel_accs,
- g_data_w => 2 * g_data_w -- = Multiplier output data width
- )
- port map (
- clk => clk,
- rst => rst,
+ generic map (
+ g_nof_inputs => g_nof_mults,
+ g_nof_channels => c_nof_accumulators,
+ g_nof_channel_accs => g_nof_channel_accs,
+ g_data_w => 2 * g_data_w -- = Multiplier output data width
+ )
+ port map (
+ clk => clk,
+ rst => rst,
- snk_in_arr => corr_multiplier_src_out_arr,
- src_out_arr => src_out_arr
- );
+ snk_in_arr => corr_multiplier_src_out_arr,
+ src_out_arr => src_out_arr
+ );
end str;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_corr_carousel.vhd b/libraries/dsp/correlator/tb/vhdl/tb_corr_carousel.vhd
index 1bbabccac1..4f6b2c1748 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_corr_carousel.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_corr_carousel.vhd
@@ -20,12 +20,12 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
---USE dp_lib.tb_dp_pkg.ALL;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ --USE dp_lib.tb_dp_pkg.ALL;
+ use common_lib.tb_common_pkg.all;
entity tb_corr_carousel is
generic (
@@ -51,16 +51,16 @@ begin
rst <= '1', '0' after c_clk_period * 7;
u_corr_carousel : entity work.corr_carousel
- generic map (
- g_nof_inputs => g_nof_inputs,
- g_nof_outputs => g_nof_outputs
- )
- port map (
- rst => rst,
- clk => clk,
- snk_in_arr => carousel_snk_in_arr,
- src_out_arr => carousel_src_out_2arr_2
- );
+ generic map (
+ g_nof_inputs => g_nof_inputs,
+ g_nof_outputs => g_nof_outputs
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_in_arr => carousel_snk_in_arr,
+ src_out_arr => carousel_src_out_2arr_2
+ );
p_stimuli: process
begin
@@ -78,7 +78,7 @@ begin
carousel_snk_in_arr(j).data <= (others => '0');
carousel_snk_in_arr(j).valid <= '0';
end loop;
- wait for (c_nof_clk_cycles_per_input_val - 1) * c_clk_period;
+ wait for (c_nof_clk_cycles_per_input_val - 1) * c_clk_period;
end loop;
end process;
end tb;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_corr_folder.vhd b/libraries/dsp/correlator/tb/vhdl/tb_corr_folder.vhd
index 7524b61661..279beb298f 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_corr_folder.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_corr_folder.vhd
@@ -20,11 +20,11 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_corr_folder is
generic (
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_corr_multiplier.vhd b/libraries/dsp/correlator/tb/vhdl/tb_corr_multiplier.vhd
index 665d96178b..73e43e7617 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_corr_multiplier.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_corr_multiplier.vhd
@@ -20,11 +20,11 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_corr_multiplier is
generic (
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_corr_permutator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_corr_permutator.vhd
index 8dd5a4a8b4..fe0ddf97d5 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_corr_permutator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_corr_permutator.vhd
@@ -20,11 +20,11 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_corr_permutator is
generic (
@@ -48,15 +48,15 @@ begin
rst <= '1', '0' after c_clk_period * 7;
u_corr_permutator : entity work.corr_permutator
- generic map (
- g_nof_inputs => g_nof_inputs
- )
- port map (
- rst => rst,
- clk => clk,
- snk_in_arr => permutator_snk_in_arr,
- src_out_2arr_2 => permutator_src_out_2arr_2
- );
+ generic map (
+ g_nof_inputs => g_nof_inputs
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_in_arr => permutator_snk_in_arr,
+ src_out_2arr_2 => permutator_src_out_2arr_2
+ );
p_stimuli: process
begin
@@ -74,7 +74,7 @@ begin
permutator_snk_in_arr(j).data <= (others => '0');
permutator_snk_in_arr(j).valid <= '0';
end loop;
- wait for c_clk_period;
+ wait for c_clk_period;
end loop;
end process;
end tb;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_corr_permutor.vhd b/libraries/dsp/correlator/tb/vhdl/tb_corr_permutor.vhd
index 0a4a7a2802..cf945f1e0b 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_corr_permutor.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_corr_permutor.vhd
@@ -20,11 +20,11 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_corr_permutor is
generic (
@@ -56,18 +56,18 @@ begin
-- Permutor
-------------------------------------------------------------------------------
u_corr_permutor : entity work.corr_permutor
- generic map (
- g_nof_inputs => g_nof_inputs,
- g_nof_outputs => g_nof_outputs,
- g_nof_cycles => g_nof_cycles,
- g_data_w => c_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- snk_in_arr => permutor_snk_in_arr,
- src_out_2arr_2 => permutor_src_out_2arr_2
- );
+ generic map (
+ g_nof_inputs => g_nof_inputs,
+ g_nof_outputs => g_nof_outputs,
+ g_nof_cycles => g_nof_cycles,
+ g_data_w => c_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_in_arr => permutor_snk_in_arr,
+ src_out_2arr_2 => permutor_src_out_2arr_2
+ );
-------------------------------------------------------------------------------
-- Generate stream indices as input data
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
index ee589c12ac..a083046aff 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
@@ -20,21 +20,21 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, diag_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.tb_common_pkg.all;
-use diag_lib.diag_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use common_lib.common_mem_pkg.all;
-
--- Folding rules:
--- . g_nof_input_folds=g_nof_pre_mult_folds : no gaps are needed/desired in the input data.
--- . g_nof_input_folds<g_nof_pre_mult_folds : gaps are required in the input data
--- . g_nof_input_folds>g_nof_pre_mult_folds : is not allowed
--- . Produces unnecessary/undesired gaps in the multiplier output
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use common_lib.common_mem_pkg.all;
+
+ -- Folding rules:
+ -- . g_nof_input_folds=g_nof_pre_mult_folds : no gaps are needed/desired in the input data.
+ -- . g_nof_input_folds<g_nof_pre_mult_folds : gaps are required in the input data
+ -- . g_nof_input_folds>g_nof_pre_mult_folds : is not allowed
+ -- . Produces unnecessary/undesired gaps in the multiplier output
entity tb_correlator is
generic (
g_nof_inputs : natural := 8;
@@ -63,18 +63,19 @@ architecture tb of tb_correlator is
-- allow folding the output onto one stream.
-- . The sync pulse is only there for the human eye (wave window) -
-- it is not used by the correlator.
--- CONSTANT c_bg_blocks_per_sync : NATURAL := largest(c_integration_period, c_nof_visibilities);
+ -- CONSTANT c_bg_blocks_per_sync : NATURAL := largest(c_integration_period, c_nof_visibilities);
constant c_bg_blocks_per_sync : natural := c_integration_period;
- constant c_bg_ctrl : t_diag_block_gen := ('1', -- enable
- '0', -- enable_sync
- TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '1', -- enable
+ '0', -- enable_sync
+ TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
constant c_dp_clk_period : time := 10 ns;
constant c_mm_clk_period : time := 10 ps;
@@ -115,22 +116,22 @@ begin
-- initialization file using Python, see tb/python/gen_subband_hex_files.py
-----------------------------------------------------------------------------
u_mms_diag_block_gen : entity diag_lib.mms_diag_block_gen
- generic map (
- g_nof_streams => c_nof_input_streams,
- g_buf_dat_w => 2 * c_complex_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_name_prefix => "hex/complex_subbands_" & natural'image(c_complex_data_w) & "b_" & "fold_" & natural'image(g_nof_input_folds),
- g_diag_block_gen_rst => c_bg_ctrl
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr
- );
+ generic map (
+ g_nof_streams => c_nof_input_streams,
+ g_buf_dat_w => 2 * c_complex_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_name_prefix => "hex/complex_subbands_" & natural'image(c_complex_data_w) & "b_" & "fold_" & natural'image(g_nof_input_folds),
+ g_diag_block_gen_rst => c_bg_ctrl
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr
+ );
-----------------------------------------------------------------------------
-- Introduce gaps in the input stream
@@ -140,147 +141,149 @@ begin
-----------------------------------------------------------------------------
gen_dp_fifo_sc : for i in 0 to c_nof_input_streams - 1 generate
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
- generic map (
- g_data_w => 2 * c_complex_data_w,
- g_use_sync => true,
- g_use_ctrl => false,
- g_use_complex => true,
- g_fifo_size => c_bg_block_size,
- g_fifo_af_margin => 0
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- wr_ful => OPEN,
- usedw => OPEN,
- rd_emp => OPEN,
-
- snk_out => OPEN,
- snk_in => block_gen_src_out_arr(i),
- src_in => dp_fifo_sc_src_in_arr(i),
- src_out => dp_fifo_sc_src_out_arr(i)
- );
+ generic map (
+ g_data_w => 2 * c_complex_data_w,
+ g_use_sync => true,
+ g_use_ctrl => false,
+ g_use_complex => true,
+ g_fifo_size => c_bg_block_size,
+ g_fifo_af_margin => 0
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ wr_ful => OPEN,
+ usedw => OPEN,
+ rd_emp => OPEN,
+
+ snk_out => OPEN,
+ snk_in => block_gen_src_out_arr(i),
+ src_in => dp_fifo_sc_src_in_arr(i),
+ src_out => dp_fifo_sc_src_out_arr(i)
+ );
end generate;
gen_dp_src_out_timer : for i in 0 to c_nof_input_streams - 1 generate
u_dp_src_out_timer : entity dp_lib.dp_src_out_timer
- generic map (
- g_block_period => c_block_period
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_fifo_sc_src_out_arr(i),
- snk_out => dp_fifo_sc_src_in_arr(i)
- );
+ generic map (
+ g_block_period => c_block_period
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => dp_fifo_sc_src_out_arr(i),
+ snk_out => dp_fifo_sc_src_in_arr(i)
+ );
end generate;
--- correlator_snk_in_arr <= dp_fifo_sc_src_out_arr;
-
--- -----------------------------------------------------------------------------
--- -- We want the correlator inputs to be properly tagged with the following
--- -- fields:
--- -- . Required:
--- -- . Sync pulse - this clears the accumulators
--- -- . Optional but recommended fields that are propagated through the correlator:
--- -- . BSN
--- -- . Channel index (part of which may indicate a channel group (beamlet index)
--- -- . SOP, EOP to tag channel blocks
--- -----------------------------------------------------------------------------
--- u_corr_output_framer : ENTITY work.corr_output_framer --FIXME rename to input_framer
--- GENERIC MAP (
--- g_nof_streams => c_nof_input_streams,
--- g_nof_folds => g_nof_input_folds, -- >0 also folds channel indices
--- g_nof_channels => g_nof_channels,
--- g_nof_channel_frames_per_sync => c_integration_period,
--- g_generate_sync_and_bsn => TRUE, -- Don't use input sync and BSN
--- g_fft_channel_index_reorder => FALSE
--- )
--- PORT MAP (
--- rst => dp_rst,
--- clk => dp_clk,
---
--- snk_in_arr => dp_fifo_sc_src_out_arr,
---
--- src_out_arr => correlator_snk_in_arr
--- );
+ -- correlator_snk_in_arr <= dp_fifo_sc_src_out_arr;
+
+ -- -----------------------------------------------------------------------------
+ -- -- We want the correlator inputs to be properly tagged with the following
+ -- -- fields:
+ -- -- . Required:
+ -- -- . Sync pulse - this clears the accumulators
+ -- -- . Optional but recommended fields that are propagated through the correlator:
+ -- -- . BSN
+ -- -- . Channel index (part of which may indicate a channel group (beamlet index)
+ -- -- . SOP, EOP to tag channel blocks
+ -- -----------------------------------------------------------------------------
+ -- u_corr_output_framer : ENTITY work.corr_output_framer --FIXME rename to input_framer
+ -- GENERIC MAP (
+ -- g_nof_streams => c_nof_input_streams,
+ -- g_nof_folds => g_nof_input_folds, -- >0 also folds channel indices
+ -- g_nof_channels => g_nof_channels,
+ -- g_nof_channel_frames_per_sync => c_integration_period,
+ -- g_generate_sync_and_bsn => TRUE, -- Don't use input sync and BSN
+ -- g_fft_channel_index_reorder => FALSE
+ -- )
+ -- PORT MAP (
+ -- rst => dp_rst,
+ -- clk => dp_clk,
+ --
+ -- snk_in_arr => dp_fifo_sc_src_out_arr,
+ --
+ -- src_out_arr => correlator_snk_in_arr
+ -- );
-----------------------------------------------------------------------------
-- Device under test: correlator
-----------------------------------------------------------------------------
u_correlator : entity work.correlator
- generic map (
- g_nof_input_streams => c_nof_input_streams,
- g_input_unfold_factor => g_nof_input_folds,
- g_nof_pre_mult_folds => g_nof_pre_mult_folds,
- g_data_w => c_complex_data_w,
- g_nof_channels => g_nof_channels,
- g_integration_period => c_integration_period
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
-
- snk_in_arr => dp_fifo_sc_src_out_arr,
- src_out_arr => correlator_src_out_arr
- );
+ generic map (
+ g_nof_input_streams => c_nof_input_streams,
+ g_input_unfold_factor => g_nof_input_folds,
+ g_nof_pre_mult_folds => g_nof_pre_mult_folds,
+ g_data_w => c_complex_data_w,
+ g_nof_channels => g_nof_channels,
+ g_integration_period => c_integration_period
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in_arr => dp_fifo_sc_src_out_arr,
+ src_out_arr => correlator_src_out_arr
+ );
-----------------------------------------------------------------------------
-- Data buffers to be read out by Python
-----------------------------------------------------------------------------
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => 1,
- g_data_w => 64,
- g_data_type => e_complex,
- g_buf_nof_data => c_nof_visibilities,
- g_buf_use_sync => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
-
- in_sync => correlator_src_out_arr(0).sop,
- in_sosi_arr => correlator_src_out_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => 64,
+ g_data_type => e_complex,
+ g_buf_nof_data => c_nof_visibilities,
+ g_buf_use_sync => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+
+ in_sync => correlator_src_out_arr(0).sop,
+ in_sosi_arr => correlator_src_out_arr
+ );
-----------------------------------------------------------------------------
-- Stream recorder to record the correlator output stream to a file
-- . The data buffer can only take snapshots.
-----------------------------------------------------------------------------
u_dp_stream_rec_play : entity dp_lib.dp_stream_rec_play
- generic map (
- g_sim => true,
- g_pass_through => false,
- g_rec_not_play => true,
- g_rec_play_file => "$HDL_WORK/libraries/dsp/correlator/tb/rec/correlator_src_out_arr0.rec",
- g_record_invalid => false
- )
- port map (
- dp_clk => dp_clk,
- snk_in => correlator_src_out_arr(0),
- snk_out => OPEN,
- src_out => OPEN,
- src_in => c_dp_siso_rdy
- );
+ generic map (
+ g_sim => true,
+ g_pass_through => false,
+ g_rec_not_play => true,
+ g_rec_play_file => "$HDL_WORK/libraries/dsp/correlator/tb/rec/correlator_src_out_arr0.rec",
+ g_record_invalid => false
+ )
+ port map (
+ dp_clk => dp_clk,
+ snk_in => correlator_src_out_arr(0),
+ snk_out => OPEN,
+ src_out => OPEN,
+ src_in => c_dp_siso_rdy
+ );
-----------------------------------------------------------------------------
-- MM file I/O with Python
-----------------------------------------------------------------------------
- u_mm_file_ram_diag_data_buffer : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+ u_mm_file_ram_diag_data_buffer : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
- u_mm_file_reg_diag_data_buffer : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+ u_mm_file_reg_diag_data_buffer : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd b/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
index 2b5d972239..160e0b48bb 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
@@ -22,20 +22,20 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, diag_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.tb_common_pkg.all;
-use diag_lib.diag_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use work.corr_permutor_pkg.all;
-use common_lib.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use work.corr_permutor_pkg.all;
+ use common_lib.common_str_pkg.all;
entity tb_correlator_dev is
generic (
@@ -88,7 +88,7 @@ architecture tb of tb_correlator_dev is
constant c_permutation_table : t_corr_permutation_table := corr_permute(g_nof_inputs, g_nof_cycles); -- Returns 3D array of dimensions nof_folding_cycles*g_nof_outputs*2 input indices
signal out_valid_count : integer := 0;
--- SIGNAL nxt_out_valid_count : NATURAL;
+ -- SIGNAL nxt_out_valid_count : NATURAL;
begin
-----------------------------------------------------------------------------
-- Clocks and reset
@@ -113,8 +113,8 @@ begin
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse);
dp_gen_data_en <= '1' and correlator_snk_out_arr(0).ready when g_flow_control_stimuli = e_active and rst = '0' else
- random(random'high) and correlator_snk_out_arr(0).ready when g_flow_control_stimuli = e_random and rst = '0' else
- pulse and correlator_snk_out_arr(0).ready when g_flow_control_stimuli = e_pulse and rst = '0' else '0';
+ random(random'high) and correlator_snk_out_arr(0).ready when g_flow_control_stimuli = e_random and rst = '0' else
+ pulse and correlator_snk_out_arr(0).ready when g_flow_control_stimuli = e_pulse and rst = '0' else '0';
end generate;
-- Count the number of valid input cycles so we know when we can stop the simulation using tb_end
@@ -139,27 +139,27 @@ begin
correlator_snk_in_arr(i).im <= RESIZE_DP_DSP_DATA(dp_gen_data_src_out_arr(i).data); -- Imag = Channel index
-- Create a block sync of g_nof_channels wide
correlator_snk_in_arr(0).sync <= '1' when (in_valid_count >= (int_period_cnt + 1) * g_nof_channels * g_nof_channel_accs - g_nof_channels and
- in_valid_count < (int_period_cnt + 1) * g_nof_channels * g_nof_channel_accs and
- correlator_snk_in_arr(0).valid = '1') else '0';
+ in_valid_count < (int_period_cnt + 1) * g_nof_channels * g_nof_channel_accs and
+ correlator_snk_in_arr(0).valid = '1') else '0';
end generate;
u_correlator_dev : entity work.correlator_dev
- generic map (
- g_data_w => g_data_w ,
- g_nof_inputs => g_nof_inputs,
- g_nof_mults => g_nof_mults,
- g_nof_cycles => g_nof_cycles,
- g_nof_channels => g_nof_channels,
- g_nof_channel_accs => g_nof_channel_accs
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in_arr => correlator_snk_in_arr,
- snk_out_arr => correlator_snk_out_arr,
- src_out_arr => correlator_src_out_arr
- );
+ generic map (
+ g_data_w => g_data_w ,
+ g_nof_inputs => g_nof_inputs,
+ g_nof_mults => g_nof_mults,
+ g_nof_cycles => g_nof_cycles,
+ g_nof_channels => g_nof_channels,
+ g_nof_channel_accs => g_nof_channel_accs
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in_arr => correlator_snk_in_arr,
+ snk_out_arr => correlator_snk_out_arr,
+ src_out_arr => correlator_src_out_arr
+ );
-----------------------------------------------------------------------------
-- Output verification
@@ -173,34 +173,34 @@ begin
-- 3) Get the input pairs that produced the input on that cycle
-- 4) Figure out what the input data was, calc output.
--- p_verify_corr_accumulator_src_out_arr : PROCESS(out_valid_count, correlator_src_out_arr)
--- BEGIN
--- nxt_out_valid_count <= out_valid_count;
--- IF correlator_src_out_arr(0).valid = '1' THEN
--- nxt_out_valid_count <= out_valid_count+1;
---
--- wait until rising_edge(clk);
--- -- Print some information
--- print_str("Correlator output valid count: " & int_to_str(out_valid_count));
--- END IF;
---
--- END PROCESS;
---
+ -- p_verify_corr_accumulator_src_out_arr : PROCESS(out_valid_count, correlator_src_out_arr)
+ -- BEGIN
+ -- nxt_out_valid_count <= out_valid_count;
+ -- IF correlator_src_out_arr(0).valid = '1' THEN
+ -- nxt_out_valid_count <= out_valid_count+1;
+ --
+ -- wait until rising_edge(clk);
+ -- -- Print some information
+ -- print_str("Correlator output valid count: " & int_to_str(out_valid_count));
+ -- END IF;
+ --
+ -- END PROCESS;
+ --
-----------------------------------------------------------------------------
-- Registers
-----------------------------------------------------------------------------
p_clk : process (clk, rst)
begin
if rst = '1' then
--- output_channel <= 0;
--- expected_data <= (OTHERS=>'0');
--- out_valid_count <= 0;
+ -- output_channel <= 0;
+ -- expected_data <= (OTHERS=>'0');
+ -- out_valid_count <= 0;
in_valid_count <= 0;
int_period_cnt <= 0;
- elsif rising_edge(clk) then
--- output_channel <= nxt_output_channel;
--- expected_data <= nxt_expected_data;
--- out_valid_count <= nxt_out_valid_count;
+ elsif rising_edge(clk) then
+ -- output_channel <= nxt_output_channel;
+ -- expected_data <= nxt_expected_data;
+ -- out_valid_count <= nxt_out_valid_count;
in_valid_count <= nxt_in_valid_count;
int_period_cnt <= nxt_int_period_cnt;
end if;
@@ -218,7 +218,7 @@ begin
-- Print some information
print_str("Correlator output valid count: " & int_to_str(out_valid_count));
for i in 0 to g_nof_inputs - 1 loop
--- print_str(". Channel " & int_to_str(g_nof_channels)
+ -- print_str(". Channel " & int_to_str(g_nof_channels)
print_str(". Output " & int_to_str(i) & ", real: " & int_to_str(TO_UINT(correlator_src_out_arr(i).re)));
print_str(". Output " & int_to_str(i) & ", imag: " & int_to_str(TO_UINT(correlator_src_out_arr(i).im)));
end loop;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_tb_corr_accumulator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_tb_corr_accumulator.vhd
index c9b1cb9b50..1350a6f8fb 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_tb_corr_accumulator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_tb_corr_accumulator.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_tb_corr_accumulator is
end tb_tb_corr_accumulator;
@@ -30,15 +30,15 @@ end tb_tb_corr_accumulator;
architecture tb of tb_tb_corr_accumulator is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
- -- g_nof_inputs
- -- | g_nof_channelss
- -- | | g_nof_channel_accs
- -- | | | g_data_w
- -- | | | |
- -- | | | | g_flow_control_stimuli
- -- | | | | |
- -- | | | | |
--- u_tb_corr_accumulator_5 : ENTITY work.tb_corr_accumulator GENERIC MAP ( 1, 5, 16, 32, e_active);
+ -- g_nof_inputs
+ -- | g_nof_channelss
+ -- | | g_nof_channel_accs
+ -- | | | g_data_w
+ -- | | | |
+ -- | | | | g_flow_control_stimuli
+ -- | | | | |
+ -- | | | | |
+ -- u_tb_corr_accumulator_5 : ENTITY work.tb_corr_accumulator GENERIC MAP ( 1, 5, 16, 32, e_active);
u_tb_corr_accumulator_06_a : entity work.tb_corr_accumulator generic map( 1, 6, 11, 31, e_active);
u_tb_corr_accumulator_07_a : entity work.tb_corr_accumulator generic map( 1, 7, 65, 32, e_active);
u_tb_corr_accumulator_08_a : entity work.tb_corr_accumulator generic map( 1, 8, 127, 33, e_active);
diff --git a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
index abd88be852..3d36e7a3a9 100644
--- a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
@@ -27,8 +27,8 @@
-- g_seed = 0 causes the LFSR to remain stuck at 0.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.fft_pkg.all;
entity fft_lfsr is
generic (
diff --git a/libraries/dsp/fft/src/vhdl/fft_pkg.vhd b/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
index 8dda8835b5..6bc58a4f64 100644
--- a/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library ieee, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package fft_pkg is
-- Default FFT switch and unswitch seeds from LOFAR1
@@ -55,11 +55,11 @@ package fft_pkg is
out_gain_w : natural; -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
stage_dat_w : natural; -- = 18, data width used between the stages(= DSP multiplier-width)
guard_w : natural; -- = 2, guard used to avoid overflow in first FFT stage, compensated in last guard_w nof FFT stages.
- -- on average the gain per stage is 2 so guard_w = 1, but the gain can be 1+sqrt(2) [Lyons section
- -- 12.3.2], therefore use input guard_w = 2.
+ -- on average the gain per stage is 2 so guard_w = 1, but the gain can be 1+sqrt(2) [Lyons section
+ -- 12.3.2], therefore use input guard_w = 2.
guard_enable : boolean; -- = true when input needs guarding, false when input requires no guarding but scaling must be
- -- skipped at the last stage(s) compensate for input guard (used in wb fft with pipe fft section
- -- doing the input guard and par fft section doing the output compensation)
+ -- skipped at the last stage(s) compensate for input guard (used in wb fft with pipe fft section
+ -- doing the input guard and par fft section doing the output compensation)
stat_data_w : positive; -- = 56
stat_data_sz : positive; -- = 2
end record;
@@ -89,7 +89,7 @@ package fft_pkg is
function fft_shift(bin : std_logic_vector) return std_logic_vector;
function fft_shift(bin, w : natural) return natural;
-end package fft_pkg;
+ end package fft_pkg;
package body fft_pkg is
function fft_switch_new_seed(seed : std_logic_vector; offset : natural) return std_logic_vector is
@@ -165,4 +165,4 @@ package body fft_pkg is
return TO_UINT(fft_shift(TO_UVEC(bin, w)));
end;
-end fft_pkg;
+ end fft_pkg;
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_bf_par.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_bf_par.vhd
index a18e851bab..d7b8b4a0a9 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_bf_par.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_bf_par.vhd
@@ -29,12 +29,12 @@
--
library ieee, common_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use rTwoSDF_lib.twiddlesPkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use rTwoSDF_lib.twiddlesPkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.fft_pkg.all;
entity fft_r2_bf_par is
generic (
@@ -101,79 +101,79 @@ begin
-- complex butterfly
------------------------------------------------------------------------------
u_bf_re : entity rTwoSDF_lib.rTwoBF
- generic map (
- g_in_a_zdly => c_bf_in_a_zdly,
- g_out_d_zdly => c_bf_out_b_zdly
- )
- port map (
- clk => clk,
- in_a => x_in_re,
- in_b => y_in_re,
- in_sel => '1',
- in_val => in_val,
- out_c => sum_re,
- out_d => dif_re
- );
+ generic map (
+ g_in_a_zdly => c_bf_in_a_zdly,
+ g_out_d_zdly => c_bf_out_b_zdly
+ )
+ port map (
+ clk => clk,
+ in_a => x_in_re,
+ in_b => y_in_re,
+ in_sel => '1',
+ in_val => in_val,
+ out_c => sum_re,
+ out_d => dif_re
+ );
u_bf_im : entity rTwoSDF_lib.rTwoBF
- generic map (
- g_in_a_zdly => c_bf_in_a_zdly,
- g_out_d_zdly => c_bf_out_b_zdly
- )
- port map (
- clk => clk,
- in_a => x_in_im,
- in_b => y_in_im,
- in_sel => '1',
- in_val => in_val,
- out_c => sum_im,
- out_d => dif_im
- );
+ generic map (
+ g_in_a_zdly => c_bf_in_a_zdly,
+ g_out_d_zdly => c_bf_out_b_zdly
+ )
+ port map (
+ clk => clk,
+ in_a => x_in_im,
+ in_b => y_in_im,
+ in_sel => '1',
+ in_val => in_val,
+ out_c => sum_im,
+ out_d => dif_im
+ );
------------------------------------------------------------------------------
-- requantize x output
------------------------------------------------------------------------------
u_requantize_x_re : entity common_lib.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_stage_bit_growth,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false,
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => 0,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => sum_re'LENGTH,
- g_out_dat_w => sum_quant_re'length
- )
- port map (
- clk => clk,
- clken => '1',
- in_dat => sum_re,
- out_dat => sum_quant_re,
- out_ovr => open
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_stage_bit_growth,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => 0,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => sum_re'LENGTH,
+ g_out_dat_w => sum_quant_re'length
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ in_dat => sum_re,
+ out_dat => sum_quant_re,
+ out_ovr => open
+ );
u_requantize_x_im : entity common_lib.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_stage_bit_growth,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false,
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => 0,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => sum_im'LENGTH,
- g_out_dat_w => sum_quant_im'length
- )
- port map (
- clk => clk,
- clken => '1',
- in_dat => sum_im,
- out_dat => sum_quant_im,
- out_ovr => open
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_stage_bit_growth,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => 0,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => sum_im'LENGTH,
+ g_out_dat_w => sum_quant_im'length
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ in_dat => sum_im,
+ out_dat => sum_quant_im,
+ out_ovr => open
+ );
------------------------------------------------------------------------------
-- Butterfly output pipelining: the sum output (output C)
@@ -185,16 +185,16 @@ begin
bf_sum_complex <= sum_quant_im & sum_quant_re;
u_pipeline_sum : entity common_lib.common_pipeline
- generic map (
- g_pipeline => g_pipeline.bf_lat + g_pipeline.mul_lat + g_pipeline.stage_lat,
- g_in_dat_w => bf_sum_complex'length,
- g_out_dat_w => bf_sum_complex'length
- )
- port map (
- clk => clk,
- in_dat => bf_sum_complex,
- out_dat => bf_sum_complex_dly
- );
+ generic map (
+ g_pipeline => g_pipeline.bf_lat + g_pipeline.mul_lat + g_pipeline.stage_lat,
+ g_in_dat_w => bf_sum_complex'length,
+ g_out_dat_w => bf_sum_complex'length
+ )
+ port map (
+ clk => clk,
+ in_dat => bf_sum_complex,
+ out_dat => bf_sum_complex_dly
+ );
-- connect to the output.
x_out_re <= bf_sum_complex_dly( c_out_dat_w - 1 downto 0);
x_out_im <= bf_sum_complex_dly(2 * c_out_dat_w - 1 downto c_out_dat_w);
@@ -208,16 +208,16 @@ begin
bf_dif_complex <= dif_im & dif_re;
u_pipeline_dif : entity common_lib.common_pipeline
- generic map (
- g_pipeline => g_pipeline.bf_lat,
- g_in_dat_w => bf_dif_complex'length,
- g_out_dat_w => bf_dif_complex'length
- )
- port map (
- clk => clk,
- in_dat => bf_dif_complex,
- out_dat => bf_dif_complex_dly
- );
+ generic map (
+ g_pipeline => g_pipeline.bf_lat,
+ g_in_dat_w => bf_dif_complex'length,
+ g_out_dat_w => bf_dif_complex'length
+ )
+ port map (
+ clk => clk,
+ in_dat => bf_dif_complex,
+ out_dat => bf_dif_complex_dly
+ );
dif_out_re <= bf_dif_complex_dly( c_out_dat_w - 1 downto 0);
dif_out_im <= bf_dif_complex_dly(2 * c_out_dat_w - 1 downto c_out_dat_w);
@@ -227,36 +227,36 @@ begin
-- before it drives to the multiplier.
------------------------------------------------------------------------------
u_val_bf_lat : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline.bf_lat
- )
- port map (
- clk => clk,
- in_dat => in_val,
- out_dat => mul_in_val
- );
+ generic map (
+ g_pipeline => g_pipeline.bf_lat
+ )
+ port map (
+ clk => clk,
+ in_dat => in_val,
+ out_dat => mul_in_val
+ );
------------------------------------------------------------------------------
-- twiddle multiplication
------------------------------------------------------------------------------
u_TwiddleMult: entity rTwoSDF_lib.rTwoWMul
- generic map (
- g_stage => g_stage,
- g_lat => g_pipeline.mul_lat
- )
- port map (
- clk => clk,
- rst => rst,
- weight_re => weight_re,
- weight_im => weight_im,
- in_re => dif_out_re,
- in_im => dif_out_im,
- in_val => mul_in_val,
- in_sel => '1', -- Always select the multiplier output
- out_re => mul_out_re,
- out_im => mul_out_im,
- out_val => mul_out_val
- );
+ generic map (
+ g_stage => g_stage,
+ g_lat => g_pipeline.mul_lat
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ weight_re => weight_re,
+ weight_im => weight_im,
+ in_re => dif_out_re,
+ in_im => dif_out_im,
+ in_val => mul_in_val,
+ in_sel => '1', -- Always select the multiplier output
+ out_re => mul_out_re,
+ out_im => mul_out_im,
+ out_val => mul_out_val
+ );
weight_re <= wRe(wMap(g_element, g_stage));
weight_im <= wIm(wMap(g_element, g_stage));
@@ -267,81 +267,81 @@ begin
-- requantize y output
------------------------------------------------------------------------------
u_requantize_y_re : entity common_lib.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_stage_bit_growth,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false,
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => 0,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => mul_out_re'LENGTH,
- g_out_dat_w => mul_quant_re'length
- )
- port map (
- clk => clk,
- clken => '1',
- in_dat => mul_out_re,
- out_dat => mul_quant_re,
- out_ovr => open
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_stage_bit_growth,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => 0,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => mul_out_re'LENGTH,
+ g_out_dat_w => mul_quant_re'length
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ in_dat => mul_out_re,
+ out_dat => mul_quant_re,
+ out_ovr => open
+ );
u_requantize_y_im : entity common_lib.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_stage_bit_growth,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false,
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => 0,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => mul_out_im'LENGTH,
- g_out_dat_w => mul_quant_im'length
- )
- port map (
- clk => clk,
- clken => '1',
- in_dat => mul_out_im,
- out_dat => mul_quant_im,
- out_ovr => open
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_stage_bit_growth,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => 0,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => mul_out_im'LENGTH,
+ g_out_dat_w => mul_quant_im'length
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ in_dat => mul_out_im,
+ out_dat => mul_quant_im,
+ out_ovr => open
+ );
------------------------------------------------------------------------------
-- output
------------------------------------------------------------------------------
u_y_re_stage_lat : entity common_lib.common_pipeline
- generic map (
- g_pipeline => g_pipeline.stage_lat,
- g_in_dat_w => mul_quant_re'LENGTH,
- g_out_dat_w => y_out_re'length
- )
- port map (
- clk => clk,
- in_dat => mul_quant_re,
- out_dat => y_out_re
- );
+ generic map (
+ g_pipeline => g_pipeline.stage_lat,
+ g_in_dat_w => mul_quant_re'LENGTH,
+ g_out_dat_w => y_out_re'length
+ )
+ port map (
+ clk => clk,
+ in_dat => mul_quant_re,
+ out_dat => y_out_re
+ );
u_y_im_stage_lat : entity common_lib.common_pipeline
- generic map (
- g_pipeline => g_pipeline.stage_lat,
- g_in_dat_w => mul_quant_im'LENGTH,
- g_out_dat_w => y_out_im'length
- )
- port map (
- clk => clk,
- in_dat => mul_quant_im,
- out_dat => y_out_im
- );
+ generic map (
+ g_pipeline => g_pipeline.stage_lat,
+ g_in_dat_w => mul_quant_im'LENGTH,
+ g_out_dat_w => y_out_im'length
+ )
+ port map (
+ clk => clk,
+ in_dat => mul_quant_im,
+ out_dat => y_out_im
+ );
u_val_stage_lat : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline.stage_lat
- )
- port map (
- clk => clk,
- in_dat => mul_out_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => g_pipeline.stage_lat
+ )
+ port map (
+ clk => clk,
+ in_dat => mul_out_val,
+ out_dat => out_val
+ );
end str;
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
index 622cd822b8..abb670c5a3 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
@@ -38,10 +38,10 @@
-- explained in fft_sepa.vhd
library ieee, common_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.fft_pkg.all;
entity fft_r2_par is
generic (
@@ -177,255 +177,255 @@ begin
gen_fft_stages: for stage in c_nof_stages downto 1 generate
gen_fft_elements: for element in 0 to c_nof_bf_per_stage-1 generate
u_element : entity work.fft_r2_bf_par
- generic map (
- g_stage => stage,
- g_element => element,
- g_scale_enable => sel_a_b(stage <= g_fft.guard_w, false, true),
- g_pipeline => g_pipeline
- )
- port map (
- clk => clk,
- rst => rst,
- x_in_re => data_re(stage)(2 * element),
- x_in_im => data_im(stage)(2 * element),
- y_in_re => data_re(stage)(2 * element + 1),
- y_in_im => data_im(stage)(2 * element + 1),
- in_val => data_val(stage)(element),
- x_out_re => data_re(stage-1)(func_butterfly_connect(2 * element, stage-1, g_fft.nof_points)),
- x_out_im => data_im(stage-1)(func_butterfly_connect(2 * element, stage-1, g_fft.nof_points)),
- y_out_re => data_re(stage-1)(func_butterfly_connect(2 * element + 1, stage-1, g_fft.nof_points)),
- y_out_im => data_im(stage-1)(func_butterfly_connect(2 * element + 1, stage-1, g_fft.nof_points)),
- out_val => data_val(stage-1)(element)
- );
- end generate;
- end generate;
-
- --------------------------------------------------------------------------------
- -- Optional output reorder
- --------------------------------------------------------------------------------
- gen_reorder : if g_fft.use_reorder and not g_fft.use_fft_shift generate
- -- unflip the bin indices for complex and also required to prepare for g_fft.use_separate of two real
- gen_reordering : for I in 0 to g_fft.nof_points - 1 generate
- int_re_arr(I) <= data_re(0)(flip(I, c_nof_stages));
- int_im_arr(I) <= data_im(0)(flip(I, c_nof_stages));
- end generate;
- end generate;
-
- gen_fft_shift : if g_fft.use_reorder and g_fft.use_fft_shift generate
- -- unflip the bin indices and apply fft_shift for complex only, to have bin frequencies from negative via zero to positive
- gen_reordering : for I in 0 to g_fft.nof_points - 1 generate
- int_re_arr(fft_shift(I, c_nof_stages)) <= data_re(0)(flip(I, c_nof_stages));
- int_im_arr(fft_shift(I, c_nof_stages)) <= data_im(0)(flip(I, c_nof_stages));
- end generate;
- end generate;
-
- no_reorder : if g_fft.use_reorder = false generate
- -- use flipped bin index order as it comes by default
- int_re_arr <= data_re(0);
- int_im_arr <= data_im(0);
- end generate;
-
- int_val <= data_val(0)(0);
-
- --------------------------------------------------------------------------------
- -- Optional separate
- --------------------------------------------------------------------------------
- gen_separate : if g_fft.use_separate generate
- ---------------------------------------------------------------------------
- -- Calulate the positive bins
- ---------------------------------------------------------------------------
- gen_positive_bins : for I in 1 to g_fft.nof_points / 2 - 1 generate
- -- common_add_sub
- a_output_real_adder : entity common_lib.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0,
- g_pipeline_output => c_pipeline_add_sub,
- g_in_dat_w => g_fft.stage_dat_w,
- g_out_dat_w => c_raw_dat_w
- )
- port map (
- clk => clk,
- in_a => int_re_arr(g_fft.nof_points - I),
- in_b => int_re_arr(I),
- result => add_arr(2 * I)
- );
-
- b_output_real_adder : entity common_lib.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0,
- g_pipeline_output => c_pipeline_add_sub,
- g_in_dat_w => g_fft.stage_dat_w,
- g_out_dat_w => c_raw_dat_w
- )
- port map (
- clk => clk,
- in_a => int_im_arr(g_fft.nof_points - I),
- in_b => int_im_arr(I),
- result => add_arr(2 * I + 1)
- );
-
- a_output_imag_subtractor : entity common_lib.common_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0,
- g_pipeline_output => c_pipeline_add_sub,
- g_in_dat_w => g_fft.stage_dat_w,
- g_out_dat_w => c_raw_dat_w
- )
- port map (
- clk => clk,
- in_a => int_im_arr(I),
- in_b => int_im_arr(g_fft.nof_points - I),
- result => sub_arr(2 * I)
- );
-
- b_output_imag_subtractor : entity common_lib.common_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0,
- g_pipeline_output => c_pipeline_add_sub,
- g_in_dat_w => g_fft.stage_dat_w,
- g_out_dat_w => c_raw_dat_w
- )
- port map (
- clk => clk,
- in_a => int_re_arr(g_fft.nof_points - I),
- in_b => int_re_arr(I),
- result => sub_arr(2 * I + 1)
- );
-
- fft_re_arr(2 * I ) <= add_arr(2 * I )(c_raw_dat_w - 1 downto 0); -- A real
- fft_re_arr(2 * I + 1) <= add_arr(2 * I + 1)(c_raw_dat_w - 1 downto 0); -- B real
- fft_im_arr(2 * I ) <= sub_arr(2 * I )(c_raw_dat_w - 1 downto 0); -- A imag
- fft_im_arr(2 * I + 1) <= sub_arr(2 * I + 1)(c_raw_dat_w - 1 downto 0); -- B imag
- end generate;
-
- ---------------------------------------------------------------------------
- -- Generate bin 0 = DC directly
- ---------------------------------------------------------------------------
- -- Index N=g_fft.nof_points wraps to index 0:
- -- . fft_re_arr(0) = (int_re_arr(0) + int_re_arr(N)) / 2 = int_re_arr(0)
- -- . fft_re_arr(1) = (int_im_arr(0) + int_im_arr(N)) / 2 = int_im_arr(0)
- -- . fft_im_arr(0) = (int_im_arr(0) - int_im_arr(N)) / 2 = 0
- -- . fft_im_arr(1) = (int_re_arr(0) - int_re_arr(N)) / 2 = 0
-
- u_pipeline_a_re_0 : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_add_sub,
- g_in_dat_w => g_fft.stage_dat_w,
- g_out_dat_w => g_fft.stage_dat_w
- )
- port map (
- clk => clk,
- in_dat => int_re_arr(0),
- out_dat => int_a_dc
- );
-
- u_pipeline_b_re_0 : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_add_sub,
- g_in_dat_w => g_fft.stage_dat_w,
- g_out_dat_w => g_fft.stage_dat_w
- )
- port map (
- clk => clk,
- in_dat => int_im_arr(0),
- out_dat => int_b_dc
- );
-
- -- The real outputs of A(0) and B(0) are scaled by shift left is * 2 for separate add
- fft_re_arr(0) <= int_a_dc & '0';
- fft_re_arr(1) <= int_b_dc & '0';
-
- -- The imaginary outputs of A(0) and B(0) are always zero in case two real inputs are provided
- fft_im_arr(0) <= (others => '0');
- fft_im_arr(1) <= (others => '0');
-
- ------------------------------------------------------------------------------
- -- Valid pipelining for separate
- ------------------------------------------------------------------------------
- u_seperate_fft_val : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_add_sub
- )
- port map (
- clk => clk,
- in_dat => int_val,
- out_dat => fft_val
- );
- end generate;
-
- no_separate : if g_fft.use_separate = false generate
- assign_outputs : for I in 0 to g_fft.nof_points - 1 generate
- -- c_raw_dat_w = g_fft.stage_dat_w, because g_fft.use_separate=false
- fft_re_arr(I) <= int_re_arr(I);
- fft_im_arr(I) <= int_im_arr(I);
- end generate;
-
- fft_val <= int_val;
- end generate;
-
- ------------------------------------------------------------------------------
- -- Parallel FFT output requantization
- ------------------------------------------------------------------------------
- gen_output_requantizers : for I in 0 to g_fft.nof_points - 1 generate
- u_requantize_re : entity common_lib.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_raw_fraction_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false,
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => c_pipeline_remove_lsb,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => c_raw_dat_w,
- g_out_dat_w => g_fft.out_dat_w
- )
- port map (
- clk => clk,
- in_dat => fft_re_arr(I),
- out_dat => out_re_arr(I),
- out_ovr => open
- );
-
- u_requantize_im : entity common_lib.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_raw_fraction_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false,
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => c_pipeline_remove_lsb,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => c_raw_dat_w,
- g_out_dat_w => g_fft.out_dat_w
- )
- port map (
- clk => clk,
- in_dat => fft_im_arr(I),
- out_dat => out_im_arr(I),
- out_ovr => open
- );
- end generate;
-
- u_out_val : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_remove_lsb
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => fft_val,
- out_dat => out_val
- );
-end str;
+ generic map (
+ g_stage => stage,
+ g_element => element,
+ g_scale_enable => sel_a_b(stage <= g_fft.guard_w, false, true),
+ g_pipeline => g_pipeline
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ x_in_re => data_re(stage)(2 * element),
+ x_in_im => data_im(stage)(2 * element),
+ y_in_re => data_re(stage)(2 * element + 1),
+ y_in_im => data_im(stage)(2 * element + 1),
+ in_val => data_val(stage)(element),
+ x_out_re => data_re(stage-1)(func_butterfly_connect(2 * element, stage-1, g_fft.nof_points)),
+ x_out_im => data_im(stage-1)(func_butterfly_connect(2 * element, stage-1, g_fft.nof_points)),
+ y_out_re => data_re(stage-1)(func_butterfly_connect(2 * element + 1, stage-1, g_fft.nof_points)),
+ y_out_im => data_im(stage-1)(func_butterfly_connect(2 * element + 1, stage-1, g_fft.nof_points)),
+ out_val => data_val(stage-1)(element)
+ );
+ end generate;
+ end generate;
+
+ --------------------------------------------------------------------------------
+ -- Optional output reorder
+ --------------------------------------------------------------------------------
+ gen_reorder : if g_fft.use_reorder and not g_fft.use_fft_shift generate
+ -- unflip the bin indices for complex and also required to prepare for g_fft.use_separate of two real
+ gen_reordering : for I in 0 to g_fft.nof_points - 1 generate
+ int_re_arr(I) <= data_re(0)(flip(I, c_nof_stages));
+ int_im_arr(I) <= data_im(0)(flip(I, c_nof_stages));
+ end generate;
+ end generate;
+
+ gen_fft_shift : if g_fft.use_reorder and g_fft.use_fft_shift generate
+ -- unflip the bin indices and apply fft_shift for complex only, to have bin frequencies from negative via zero to positive
+ gen_reordering : for I in 0 to g_fft.nof_points - 1 generate
+ int_re_arr(fft_shift(I, c_nof_stages)) <= data_re(0)(flip(I, c_nof_stages));
+ int_im_arr(fft_shift(I, c_nof_stages)) <= data_im(0)(flip(I, c_nof_stages));
+ end generate;
+ end generate;
+
+ no_reorder : if g_fft.use_reorder = false generate
+ -- use flipped bin index order as it comes by default
+ int_re_arr <= data_re(0);
+ int_im_arr <= data_im(0);
+ end generate;
+
+ int_val <= data_val(0)(0);
+
+ --------------------------------------------------------------------------------
+ -- Optional separate
+ --------------------------------------------------------------------------------
+ gen_separate : if g_fft.use_separate generate
+ ---------------------------------------------------------------------------
+ -- Calulate the positive bins
+ ---------------------------------------------------------------------------
+ gen_positive_bins : for I in 1 to g_fft.nof_points / 2 - 1 generate
+ -- common_add_sub
+ a_output_real_adder : entity common_lib.common_add_sub
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0,
+ g_pipeline_output => c_pipeline_add_sub,
+ g_in_dat_w => g_fft.stage_dat_w,
+ g_out_dat_w => c_raw_dat_w
+ )
+ port map (
+ clk => clk,
+ in_a => int_re_arr(g_fft.nof_points - I),
+ in_b => int_re_arr(I),
+ result => add_arr(2 * I)
+ );
+
+ b_output_real_adder : entity common_lib.common_add_sub
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0,
+ g_pipeline_output => c_pipeline_add_sub,
+ g_in_dat_w => g_fft.stage_dat_w,
+ g_out_dat_w => c_raw_dat_w
+ )
+ port map (
+ clk => clk,
+ in_a => int_im_arr(g_fft.nof_points - I),
+ in_b => int_im_arr(I),
+ result => add_arr(2 * I + 1)
+ );
+
+ a_output_imag_subtractor : entity common_lib.common_add_sub
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0,
+ g_pipeline_output => c_pipeline_add_sub,
+ g_in_dat_w => g_fft.stage_dat_w,
+ g_out_dat_w => c_raw_dat_w
+ )
+ port map (
+ clk => clk,
+ in_a => int_im_arr(I),
+ in_b => int_im_arr(g_fft.nof_points - I),
+ result => sub_arr(2 * I)
+ );
+
+ b_output_imag_subtractor : entity common_lib.common_add_sub
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0,
+ g_pipeline_output => c_pipeline_add_sub,
+ g_in_dat_w => g_fft.stage_dat_w,
+ g_out_dat_w => c_raw_dat_w
+ )
+ port map (
+ clk => clk,
+ in_a => int_re_arr(g_fft.nof_points - I),
+ in_b => int_re_arr(I),
+ result => sub_arr(2 * I + 1)
+ );
+
+ fft_re_arr(2 * I ) <= add_arr(2 * I )(c_raw_dat_w - 1 downto 0); -- A real
+ fft_re_arr(2 * I + 1) <= add_arr(2 * I + 1)(c_raw_dat_w - 1 downto 0); -- B real
+ fft_im_arr(2 * I ) <= sub_arr(2 * I )(c_raw_dat_w - 1 downto 0); -- A imag
+ fft_im_arr(2 * I + 1) <= sub_arr(2 * I + 1)(c_raw_dat_w - 1 downto 0); -- B imag
+ end generate;
+
+ ---------------------------------------------------------------------------
+ -- Generate bin 0 = DC directly
+ ---------------------------------------------------------------------------
+ -- Index N=g_fft.nof_points wraps to index 0:
+ -- . fft_re_arr(0) = (int_re_arr(0) + int_re_arr(N)) / 2 = int_re_arr(0)
+ -- . fft_re_arr(1) = (int_im_arr(0) + int_im_arr(N)) / 2 = int_im_arr(0)
+ -- . fft_im_arr(0) = (int_im_arr(0) - int_im_arr(N)) / 2 = 0
+ -- . fft_im_arr(1) = (int_re_arr(0) - int_re_arr(N)) / 2 = 0
+
+ u_pipeline_a_re_0 : entity common_lib.common_pipeline
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_add_sub,
+ g_in_dat_w => g_fft.stage_dat_w,
+ g_out_dat_w => g_fft.stage_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => int_re_arr(0),
+ out_dat => int_a_dc
+ );
+
+ u_pipeline_b_re_0 : entity common_lib.common_pipeline
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_add_sub,
+ g_in_dat_w => g_fft.stage_dat_w,
+ g_out_dat_w => g_fft.stage_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => int_im_arr(0),
+ out_dat => int_b_dc
+ );
+
+ -- The real outputs of A(0) and B(0) are scaled by shift left is * 2 for separate add
+ fft_re_arr(0) <= int_a_dc & '0';
+ fft_re_arr(1) <= int_b_dc & '0';
+
+ -- The imaginary outputs of A(0) and B(0) are always zero in case two real inputs are provided
+ fft_im_arr(0) <= (others => '0');
+ fft_im_arr(1) <= (others => '0');
+
+ ------------------------------------------------------------------------------
+ -- Valid pipelining for separate
+ ------------------------------------------------------------------------------
+ u_seperate_fft_val : entity common_lib.common_pipeline_sl
+ generic map (
+ g_pipeline => c_pipeline_add_sub
+ )
+ port map (
+ clk => clk,
+ in_dat => int_val,
+ out_dat => fft_val
+ );
+ end generate;
+
+ no_separate : if g_fft.use_separate = false generate
+ assign_outputs : for I in 0 to g_fft.nof_points - 1 generate
+ -- c_raw_dat_w = g_fft.stage_dat_w, because g_fft.use_separate=false
+ fft_re_arr(I) <= int_re_arr(I);
+ fft_im_arr(I) <= int_im_arr(I);
+ end generate;
+
+ fft_val <= int_val;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Parallel FFT output requantization
+ ------------------------------------------------------------------------------
+ gen_output_requantizers : for I in 0 to g_fft.nof_points - 1 generate
+ u_requantize_re : entity common_lib.common_requantize
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_raw_fraction_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => c_pipeline_remove_lsb,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => c_raw_dat_w,
+ g_out_dat_w => g_fft.out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => fft_re_arr(I),
+ out_dat => out_re_arr(I),
+ out_ovr => open
+ );
+
+ u_requantize_im : entity common_lib.common_requantize
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_raw_fraction_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => c_pipeline_remove_lsb,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => c_raw_dat_w,
+ g_out_dat_w => g_fft.out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => fft_im_arr(I),
+ out_dat => out_im_arr(I),
+ out_ovr => open
+ );
+ end generate;
+
+ u_out_val : entity common_lib.common_pipeline_sl
+ generic map (
+ g_pipeline => c_pipeline_remove_lsb
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => fft_val,
+ out_dat => out_val
+ );
+ end str;
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
index 1df364ce44..218d261d91 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
@@ -71,10 +71,10 @@
--
library ieee, common_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.fft_pkg.all;
entity fft_r2_pipe is
generic (
@@ -160,23 +160,23 @@ begin
in_dat_val <= in_val;
u_switch : entity work.fft_switch
- generic map (
- g_switch_en => c_switch_en,
- g_seed1 => c_switch_seed1,
- g_seed2 => c_switch_seed2,
- g_fft_sz_w => c_switch_sz_w,
- g_dat_w => c_switch_dat_w
- )
- port map (
- in_re => in_dat_re,
- in_im => in_dat_im,
- in_val => in_dat_val,
- out_re => switch_re,
- out_im => switch_im,
- out_val => switch_val,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_switch_en => c_switch_en,
+ g_seed1 => c_switch_seed1,
+ g_seed2 => c_switch_seed2,
+ g_fft_sz_w => c_switch_sz_w,
+ g_dat_w => c_switch_dat_w
+ )
+ port map (
+ in_re => in_dat_re,
+ in_im => in_dat_im,
+ in_val => in_dat_val,
+ out_re => switch_re,
+ out_im => switch_im,
+ out_val => switch_val,
+ clk => clk,
+ rst => rst
+ );
data_re( c_nof_stages) <= scale_and_resize_svec(switch_re, c_in_scale_w, g_fft.stage_dat_w);
data_im( c_nof_stages) <= scale_and_resize_svec(switch_im, c_in_scale_w, g_fft.stage_dat_w);
@@ -187,192 +187,192 @@ begin
------------------------------------------------------------------------------
gen_fft: for stage in c_nof_stages downto 2 generate
u_stages : entity rTwoSDF_lib.rTwoSDFStage
- generic map (
- g_nof_chan => g_fft.nof_chan,
- g_stage => stage,
- g_stage_offset => c_stage_offset,
- g_twiddle_offset => g_fft.twiddle_offset,
- g_scale_enable => sel_a_b(stage <= g_fft.guard_w, false, true),
- g_pipeline => g_pipeline
- )
- port map (
- clk => clk,
- rst => rst,
- in_re => data_re(stage),
- in_im => data_im(stage),
- in_val => data_val(stage),
- out_re => data_re(stage-1),
- out_im => data_im(stage-1),
- out_val => data_val(stage-1)
- );
- end generate;
+ generic map (
+ g_nof_chan => g_fft.nof_chan,
+ g_stage => stage,
+ g_stage_offset => c_stage_offset,
+ g_twiddle_offset => g_fft.twiddle_offset,
+ g_scale_enable => sel_a_b(stage <= g_fft.guard_w, false, true),
+ g_pipeline => g_pipeline
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_re => data_re(stage),
+ in_im => data_im(stage),
+ in_val => data_val(stage),
+ out_re => data_re(stage-1),
+ out_im => data_im(stage-1),
+ out_val => data_val(stage-1)
+ );
+ end generate;
- -- last stage = 1
- u_last_stage : entity rTwoSDF_lib.rTwoSDFStage
- generic map (
- g_nof_chan => g_fft.nof_chan,
- g_stage => 1,
- g_stage_offset => c_stage_offset,
- g_twiddle_offset => g_fft.twiddle_offset,
- g_scale_enable => sel_a_b(1 <= g_fft.guard_w, false, true),
- g_pipeline => g_pipeline
- )
- port map (
- clk => clk,
- rst => rst,
- in_re => data_re(1),
- in_im => data_im(1),
- in_val => data_val(1),
- out_re => data_re(0),
- out_im => data_im(0),
- out_val => data_val(0)
- );
+ -- last stage = 1
+ u_last_stage : entity rTwoSDF_lib.rTwoSDFStage
+ generic map (
+ g_nof_chan => g_fft.nof_chan,
+ g_stage => 1,
+ g_stage_offset => c_stage_offset,
+ g_twiddle_offset => g_fft.twiddle_offset,
+ g_scale_enable => sel_a_b(1 <= g_fft.guard_w, false, true),
+ g_pipeline => g_pipeline
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_re => data_re(1),
+ in_im => data_im(1),
+ in_val => data_val(1),
+ out_re => data_re(0),
+ out_im => data_im(0),
+ out_val => data_val(0)
+ );
- ------------------------------------------------------------------------------
- -- Optional output reorder and separation
- ------------------------------------------------------------------------------
- gen_reorder_and_separate : if g_fft.use_separate or g_fft.use_reorder generate
- in_cplx <= data_im(0) & data_re(0);
+ ------------------------------------------------------------------------------
+ -- Optional output reorder and separation
+ ------------------------------------------------------------------------------
+ gen_reorder_and_separate : if g_fft.use_separate or g_fft.use_reorder generate
+ in_cplx <= data_im(0) & data_re(0);
- u_reorder_sep : entity work.fft_reorder_sepa_pipe
- generic map (
- g_bit_flip => g_fft.use_reorder,
- g_fft_shift => g_fft.use_fft_shift,
- g_separate => g_fft.use_separate,
- g_dont_flip_channels => g_dont_flip_channels,
- g_nof_points => g_fft.nof_points,
- g_nof_chan => g_fft.nof_chan
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => in_cplx, -- c_nof_complex * g_fft.stage_dat_w
- in_val => data_val(0),
- out_dat => out_cplx, -- c_nof_complex * c_raw_dat_w
- out_val => fft_out_val
- );
+ u_reorder_sep : entity work.fft_reorder_sepa_pipe
+ generic map (
+ g_bit_flip => g_fft.use_reorder,
+ g_fft_shift => g_fft.use_fft_shift,
+ g_separate => g_fft.use_separate,
+ g_dont_flip_channels => g_dont_flip_channels,
+ g_nof_points => g_fft.nof_points,
+ g_nof_chan => g_fft.nof_chan
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => in_cplx, -- c_nof_complex * g_fft.stage_dat_w
+ in_val => data_val(0),
+ out_dat => out_cplx, -- c_nof_complex * c_raw_dat_w
+ out_val => fft_out_val
+ );
- -- c_raw_dat_w = g_fft.stage_dat_w when g_fft.use_separate = false
- -- c_raw_dat_w = g_fft.stage_dat_w + 1 when g_fft.use_separate = true
- fft_out_re <= out_cplx( c_raw_dat_w - 1 downto 0);
- fft_out_im <= out_cplx(2 * c_raw_dat_w - 1 downto c_raw_dat_w);
- end generate;
+ -- c_raw_dat_w = g_fft.stage_dat_w when g_fft.use_separate = false
+ -- c_raw_dat_w = g_fft.stage_dat_w + 1 when g_fft.use_separate = true
+ fft_out_re <= out_cplx( c_raw_dat_w - 1 downto 0);
+ fft_out_im <= out_cplx(2 * c_raw_dat_w - 1 downto c_raw_dat_w);
+ end generate;
- no_reorder_no_seperate : if g_fft.use_separate = false and g_fft.use_reorder = false generate
- -- c_raw_dat_w = g_fft.stage_dat_w because g_fft.use_separate = false
- fft_out_re <= data_re(0);
- fft_out_im <= data_im(0);
- fft_out_val <= data_val(0);
- end generate;
+ no_reorder_no_seperate : if g_fft.use_separate = false and g_fft.use_reorder = false generate
+ -- c_raw_dat_w = g_fft.stage_dat_w because g_fft.use_separate = false
+ fft_out_re <= data_re(0);
+ fft_out_im <= data_im(0);
+ fft_out_val <= data_val(0);
+ end generate;
- ------------------------------------------------------------------------------
- -- Undo input random negation of u_switch at FFT output when c_switch_en =
- -- g_fft.use_separate = TRUE
- ------------------------------------------------------------------------------
- u_unswitch : entity work.fft_unswitch
- generic map (
- g_switch_en => c_switch_en,
- g_seed1 => c_switch_seed1,
- g_seed2 => c_switch_seed2,
- g_fft_sz_w => c_switch_sz_w,
- g_dat_w => c_unswitch_dat_w
- )
- port map (
- in_re => fft_out_re,
- in_im => fft_out_im,
- in_val => fft_out_val,
- out_re => raw_re,
- out_im => raw_im,
- out_val => raw_val,
- clk => clk,
- rst => rst
- );
+ ------------------------------------------------------------------------------
+ -- Undo input random negation of u_switch at FFT output when c_switch_en =
+ -- g_fft.use_separate = TRUE
+ ------------------------------------------------------------------------------
+ u_unswitch : entity work.fft_unswitch
+ generic map (
+ g_switch_en => c_switch_en,
+ g_seed1 => c_switch_seed1,
+ g_seed2 => c_switch_seed2,
+ g_fft_sz_w => c_switch_sz_w,
+ g_dat_w => c_unswitch_dat_w
+ )
+ port map (
+ in_re => fft_out_re,
+ in_im => fft_out_im,
+ in_val => fft_out_val,
+ out_re => raw_re,
+ out_im => raw_im,
+ out_val => raw_val,
+ clk => clk,
+ rst => rst
+ );
- ------------------------------------------------------------------------------
- -- Pipelined FFT output requantization
- ------------------------------------------------------------------------------
- u_requantize_re : entity common_lib.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_raw_fraction_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false,
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => c_pipeline_remove_lsb,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => c_raw_dat_w,
- g_out_dat_w => g_fft.out_dat_w
- )
- port map (
- clk => clk,
- in_dat => raw_re,
- out_dat => out_quant_re,
- out_ovr => open
- );
+ ------------------------------------------------------------------------------
+ -- Pipelined FFT output requantization
+ ------------------------------------------------------------------------------
+ u_requantize_re : entity common_lib.common_requantize
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_raw_fraction_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => c_pipeline_remove_lsb,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => c_raw_dat_w,
+ g_out_dat_w => g_fft.out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => raw_re,
+ out_dat => out_quant_re,
+ out_ovr => open
+ );
- u_requantize_im : entity common_lib.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_raw_fraction_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false,
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => c_pipeline_remove_lsb,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => c_raw_dat_w,
- g_out_dat_w => g_fft.out_dat_w
- )
- port map (
- clk => clk,
- in_dat => raw_im,
- out_dat => out_quant_im,
- out_ovr => open
- );
+ u_requantize_im : entity common_lib.common_requantize
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_raw_fraction_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => c_pipeline_remove_lsb,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => c_raw_dat_w,
+ g_out_dat_w => g_fft.out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => raw_im,
+ out_dat => out_quant_im,
+ out_ovr => open
+ );
- u_quant_val : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_remove_lsb
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => raw_val,
- out_dat => out_val
- );
+ u_quant_val : entity common_lib.common_pipeline_sl
+ generic map (
+ g_pipeline => c_pipeline_remove_lsb
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => raw_val,
+ out_dat => out_val
+ );
- ------------------------------------------------------------------------------
- -- Pipelined FFT raw output register
- ------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
+ -- Pipelined FFT raw output register
+ ------------------------------------------------------------------------------
- -- . Pipeline out_raw to align with out_quant, so they can share
- -- out_val.
- u_out_raw_re : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_remove_lsb,
- g_in_dat_w => c_raw_dat_w,
- g_out_dat_w => c_32
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => raw_re,
- out_dat => out_raw_re
- );
+ -- . Pipeline out_raw to align with out_quant, so they can share
+ -- out_val.
+ u_out_raw_re : entity common_lib.common_pipeline
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_remove_lsb,
+ g_in_dat_w => c_raw_dat_w,
+ g_out_dat_w => c_32
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => raw_re,
+ out_dat => out_raw_re
+ );
- u_out_raw_im : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_remove_lsb,
- g_in_dat_w => c_raw_dat_w,
- g_out_dat_w => c_32
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => raw_im,
- out_dat => out_raw_im
- );
-end str;
+ u_out_raw_im : entity common_lib.common_pipeline
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_remove_lsb,
+ g_in_dat_w => c_raw_dat_w,
+ g_out_dat_w => c_32
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => raw_im,
+ out_dat => out_raw_im
+ );
+ end str;
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd
index d2401d7cf4..22ff1a5eaf 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd
@@ -68,10 +68,10 @@
-- library instead of using a dedicated local solution.
library ieee, common_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.fft_pkg.all;
entity fft_r2_wide is
generic (
@@ -129,16 +129,16 @@ architecture rtl of fft_r2_wide is
function func_create_generic_for_par_fft(input : t_fft) return t_fft is
variable v_return : t_fft := input; -- Variable that holds the return value
begin
- v_return.use_reorder := input.use_reorder; -- Pass on use_reorder
- v_return.use_fft_shift := input.use_fft_shift; -- Pass on use_fft_shift
- v_return.use_separate := false; -- Separate function is forced to false, because it is handled outside the parallel fft
- v_return.twiddle_offset := 0; -- Twiddle offset is forced to 0, which is also the input.twiddle_offset default
- v_return.nof_points := input.wb_factor; -- Set the number of points to wb_factor
- v_return.in_dat_w := input.stage_dat_w; -- Specify the input width
- v_return.out_dat_w := input.stage_dat_w; -- Output width
- v_return.out_gain_w := 0; -- Output gain is forced to 0, because it is handled outside the parallel fft
- v_return.guard_w := input.guard_w; -- Set the guard_w here to skip the scaling on the last stages
- v_return.guard_enable := false; -- No input guard.
+ v_return.use_reorder := input.use_reorder; -- Pass on use_reorder
+ v_return.use_fft_shift := input.use_fft_shift; -- Pass on use_fft_shift
+ v_return.use_separate := false; -- Separate function is forced to false, because it is handled outside the parallel fft
+ v_return.twiddle_offset := 0; -- Twiddle offset is forced to 0, which is also the input.twiddle_offset default
+ v_return.nof_points := input.wb_factor; -- Set the number of points to wb_factor
+ v_return.in_dat_w := input.stage_dat_w; -- Specify the input width
+ v_return.out_dat_w := input.stage_dat_w; -- Output width
+ v_return.out_gain_w := 0; -- Output gain is forced to 0, because it is handled outside the parallel fft
+ v_return.guard_w := input.guard_w; -- Set the guard_w here to skip the scaling on the last stages
+ v_return.guard_enable := false; -- No input guard.
return v_return;
end;
@@ -184,20 +184,20 @@ begin
-- Default to fft_r2_pipe when g_fft.wb_factor=1
gen_fft_r2_pipe : if g_fft.wb_factor = 1 generate
u_fft_r2_pipe : entity work.fft_r2_pipe
- generic map (
- g_fft => g_fft,
- g_pipeline => g_pft_pipeline
- )
- port map (
- clk => clk,
- rst => rst,
- in_re => in_re_arr(0)(g_fft.in_dat_w - 1 downto 0),
- in_im => in_im_arr(0)(g_fft.in_dat_w - 1 downto 0),
- in_val => in_val,
- out_quant_re => fft_pipe_out_re,
- out_quant_im => fft_pipe_out_im,
- out_val => out_val
- );
+ generic map (
+ g_fft => g_fft,
+ g_pipeline => g_pft_pipeline
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_re => in_re_arr(0)(g_fft.in_dat_w - 1 downto 0),
+ in_im => in_im_arr(0)(g_fft.in_dat_w - 1 downto 0),
+ in_val => in_val,
+ out_quant_re => fft_pipe_out_re,
+ out_quant_im => fft_pipe_out_im,
+ out_val => out_val
+ );
out_re_arr(0) <= resize_fft_svec(fft_pipe_out_re);
out_im_arr(0) <= resize_fft_svec(fft_pipe_out_im);
@@ -206,20 +206,20 @@ begin
-- Default to fft_r2_par when g_fft.wb_factor=g_fft.nof_points
gen_fft_r2_par : if g_fft.wb_factor = g_fft.nof_points generate
u_fft_r2_par : entity work.fft_r2_par
- generic map (
- g_fft => g_fft,
- g_pipeline => g_fft_pipeline
- )
- port map (
- clk => clk,
- rst => rst,
- in_re_arr => in_re_arr,
- in_im_arr => in_im_arr,
- in_val => in_val,
- out_re_arr => out_re_arr,
- out_im_arr => out_im_arr,
- out_val => out_val
- );
+ generic map (
+ g_fft => g_fft,
+ g_pipeline => g_fft_pipeline
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_re_arr => in_re_arr,
+ in_im_arr => in_im_arr,
+ in_val => in_val,
+ out_re_arr => out_re_arr,
+ out_im_arr => out_im_arr,
+ out_val => out_val
+ );
end generate;
-- Create wideband FFT as combinination of g_fft.wb_factor instances of fft_r2_pipe with one instance of fft_r2_par
@@ -238,20 +238,20 @@ begin
-- pipelined fft's. These pipelines fft's operate in parallel.
gen_pipelined_ffts : for I in g_fft.wb_factor - 1 downto 0 generate
u_pft : entity work.fft_r2_pipe
- generic map (
- g_fft => c_fft_r2_pipe_arr(I), -- generics for the pipelined FFTs
- g_pipeline => g_pft_pipeline -- pipeline generics for the pipelined FFTs
- )
- port map (
- clk => clk,
- rst => rst,
- in_re => in_fft_pipe_re_arr(I)(c_fft_r2_pipe_arr(I).in_dat_w - 1 downto 0),
- in_im => in_fft_pipe_im_arr(I)(c_fft_r2_pipe_arr(I).in_dat_w - 1 downto 0),
- in_val => in_val,
- out_quant_re => out_fft_pipe_re_arr(I)(c_fft_r2_pipe_arr(I).out_dat_w - 1 downto 0),
- out_quant_im => out_fft_pipe_im_arr(I)(c_fft_r2_pipe_arr(I).out_dat_w - 1 downto 0),
- out_val => out_fft_pipe_val(I)
- );
+ generic map (
+ g_fft => c_fft_r2_pipe_arr(I), -- generics for the pipelined FFTs
+ g_pipeline => g_pft_pipeline -- pipeline generics for the pipelined FFTs
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_re => in_fft_pipe_re_arr(I)(c_fft_r2_pipe_arr(I).in_dat_w - 1 downto 0),
+ in_im => in_fft_pipe_im_arr(I)(c_fft_r2_pipe_arr(I).in_dat_w - 1 downto 0),
+ in_val => in_val,
+ out_quant_re => out_fft_pipe_re_arr(I)(c_fft_r2_pipe_arr(I).out_dat_w - 1 downto 0),
+ out_quant_im => out_fft_pipe_im_arr(I)(c_fft_r2_pipe_arr(I).out_dat_w - 1 downto 0),
+ out_val => out_fft_pipe_val(I)
+ );
end generate;
---------------------------------------------------------------
@@ -269,20 +269,20 @@ begin
-- The g_fft.wb_factor outputs of the pipelined fft's are offered
-- to the input of a single parallel FFT.
u_fft : entity work.fft_r2_par
- generic map (
- g_fft => c_fft_r2_par, -- generics for the FFT
- g_pipeline => g_fft_pipeline -- pipeline generics for the parallel FFT
- )
- port map (
- clk => clk,
- rst => rst,
- in_re_arr => in_fft_par_re_arr,
- in_im_arr => in_fft_par_im_arr,
- in_val => in_fft_par,
- out_re_arr => fft_out_re_arr,
- out_im_arr => fft_out_im_arr,
- out_val => fft_out_val
- );
+ generic map (
+ g_fft => c_fft_r2_par, -- generics for the FFT
+ g_pipeline => g_fft_pipeline -- pipeline generics for the parallel FFT
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_re_arr => in_fft_par_re_arr,
+ in_im_arr => in_fft_par_im_arr,
+ in_val => in_fft_par,
+ out_re_arr => fft_out_re_arr,
+ out_im_arr => fft_out_im_arr,
+ out_val => fft_out_val
+ );
---------------------------------------------------------------
-- OPTIONAL: SEPARATION STAGE
@@ -290,22 +290,22 @@ begin
-- When the separate functionality is required:
gen_separate : if g_fft.use_separate generate
u_separator : entity work.fft_sepa_wide
- generic map (
- g_fft => g_fft
- )
- port map (
- clk => clk,
- rst => rst,
- in_re_arr => fft_out_re_arr,
- in_im_arr => fft_out_im_arr,
- in_val => fft_out_val,
- out_re_arr => sep_out_re_arr,
- out_im_arr => sep_out_im_arr,
- out_val => sep_out_val
- );
+ generic map (
+ g_fft => g_fft
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_re_arr => fft_out_re_arr,
+ in_im_arr => fft_out_im_arr,
+ in_val => fft_out_val,
+ out_re_arr => sep_out_re_arr,
+ out_im_arr => sep_out_im_arr,
+ out_val => sep_out_val
+ );
end generate;
- -- In case no separtion is required, the output of the parallel fft is used.
+ -- In case no separtion is required, the output of the parallel fft is used.
no_separate : if g_fft.use_separate = false generate
sep_out_re_arr <= fft_out_re_arr;
sep_out_im_arr <= fft_out_im_arr;
@@ -317,55 +317,55 @@ begin
---------------------------------------------------------------
gen_output_requantizers : for I in g_fft.wb_factor - 1 downto 0 generate
u_requantize_output_re : entity common_lib.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_raw_fraction_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false,
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => c_pipeline_remove_lsb,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => c_raw_dat_w,
- g_out_dat_w => g_fft.out_dat_w
- )
- port map (
- clk => clk,
- in_dat => sep_out_re_arr(I),
- out_dat => out_re_arr(I),
- out_ovr => open
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_raw_fraction_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => c_pipeline_remove_lsb,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => c_raw_dat_w,
+ g_out_dat_w => g_fft.out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => sep_out_re_arr(I),
+ out_dat => out_re_arr(I),
+ out_ovr => open
+ );
u_requantize_output_im : entity common_lib.common_requantize
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_raw_fraction_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => c_pipeline_remove_lsb,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => c_raw_dat_w,
+ g_out_dat_w => g_fft.out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => sep_out_im_arr(I),
+ out_dat => out_im_arr(I),
+ out_ovr => open
+ );
+ end generate;
+
+ u_out_val : entity common_lib.common_pipeline_sl
generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_raw_fraction_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false,
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => c_pipeline_remove_lsb,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => c_raw_dat_w,
- g_out_dat_w => g_fft.out_dat_w
+ g_pipeline => c_pipeline_remove_lsb
)
port map (
- clk => clk,
- in_dat => sep_out_im_arr(I),
- out_dat => out_im_arr(I),
- out_ovr => open
+ rst => rst,
+ clk => clk,
+ in_dat => sep_out_val,
+ out_dat => out_val
);
- end generate;
-
- u_out_val : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_remove_lsb
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sep_out_val,
- out_dat => out_val
- );
end generate;
end rtl;
diff --git a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
index 36d0e53f0d..5aa2b9740b 100644
--- a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
@@ -34,10 +34,10 @@
--
library ieee, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.fft_pkg.all;
entity fft_reorder_sepa_pipe is
generic (
@@ -163,17 +163,17 @@ begin
end generate;
u_adr_point_cnt : entity common_lib.common_counter
- generic map(
- g_latency => 1,
- g_init => 0,
- g_width => ceil_log2(g_nof_points)
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_en => cnt_ena,
- count => adr_points_cnt
- );
+ generic map(
+ g_latency => 1,
+ g_init => 0,
+ g_width => ceil_log2(g_nof_points)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_en => cnt_ena,
+ count => adr_points_cnt
+ );
-- Generate on c_nof_channels to avoid simulation warnings on TO_UINT(adr_chan_cnt) when adr_chan_cnt is a NULL array
one_chan : if c_nof_channels = 1 generate
@@ -185,41 +185,41 @@ begin
end generate;
u_adr_chan_cnt : entity common_lib.common_counter
- generic map(
- g_latency => 1,
- g_init => 0,
- g_width => g_nof_chan
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_en => in_val,
- count => adr_chan_cnt
- );
+ generic map(
+ g_latency => 1,
+ g_init => 0,
+ g_width => g_nof_chan
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_en => in_val,
+ count => adr_chan_cnt
+ );
u_buff : entity common_lib.common_paged_ram_r_w
- generic map (
- g_str => "use_adr",
- g_data_w => c_dat_w,
- g_nof_pages => 2,
- g_page_sz => c_page_size,
- g_wr_start_page => 0,
- g_rd_start_page => 1,
- g_rd_latency => 1
- )
- port map (
- rst => rst,
- clk => clk,
- wr_next_page => next_page,
- wr_adr => wr_adr,
- wr_en => wr_en,
- wr_dat => wr_dat,
- rd_next_page => next_page,
- rd_adr => rd_adr,
- rd_en => rd_en,
- rd_dat => rd_dat,
- rd_val => rd_val
- );
+ generic map (
+ g_str => "use_adr",
+ g_data_w => c_dat_w,
+ g_nof_pages => 2,
+ g_page_sz => c_page_size,
+ g_wr_start_page => 0,
+ g_rd_start_page => 1,
+ g_rd_latency => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_next_page => next_page,
+ wr_adr => wr_adr,
+ wr_en => wr_en,
+ wr_dat => wr_dat,
+ rd_next_page => next_page,
+ rd_adr => rd_adr,
+ rd_en => rd_en,
+ rd_dat => rd_dat,
+ rd_val => rd_val
+ );
-- If the separate functionality is enabled the read address will
-- be composed of an up and down counter that are interleaved. This is
@@ -243,67 +243,67 @@ begin
v.rd_en := '0';
case r.state is
- when s_idle =>
+ when s_idle =>
if(next_page = '1') then -- Both counters are reset on page turn.
- v.rd_en := '1';
- v.switch := '0';
- v.count_up := 0;
- if(g_separate = true) then -- Choose the appropriate run state
- v.count_chan := 0;
- v.count_down := g_nof_points;
- v.state := s_run_separate;
- else
- v.state := s_run_normal;
- end if;
+ v.rd_en := '1';
+ v.switch := '0';
+ v.count_up := 0;
+ if(g_separate = true) then -- Choose the appropriate run state
+ v.count_chan := 0;
+ v.count_down := g_nof_points;
+ v.state := s_run_separate;
+ else
+ v.state := s_run_normal;
+ end if;
end if;
- when s_run_separate =>
+ when s_run_separate =>
v.rd_en := '1';
if(r.switch = '0') then
- v.switch := '1';
- v.count_up := r.count_up + 1;
+ v.switch := '1';
+ v.count_up := r.count_up + 1;
end if;
if(r.switch = '1') then
- v.switch := '0';
- v.count_down := r.count_down - 1;
+ v.switch := '0';
+ v.count_down := r.count_down - 1;
end if;
if(next_page = '1') then -- Both counters are reset on page turn.
- v.count_up := 0;
- v.count_down := g_nof_points;
- v.count_chan := 0;
+ v.count_up := 0;
+ v.count_down := g_nof_points;
+ v.count_chan := 0;
elsif(r.count_up = g_nof_points / 2 and r.count_chan < c_nof_channels - 1) then --
- v.count_up := 0;
- v.count_down := g_nof_points;
- v.count_chan := r.count_chan + 1;
+ v.count_up := 0;
+ v.count_down := g_nof_points;
+ v.count_chan := r.count_chan + 1;
elsif(r.count_up = g_nof_points / 2) then -- Pagereading is done, but there is not yet new data available
- v.rd_en := '0';
- v.state := s_idle;
+ v.rd_en := '0';
+ v.state := s_idle;
end if;
when s_run_normal =>
v.rd_en := '1';
if(next_page = '1') then -- Counters is reset on page turn.
- v.count_up := 0;
+ v.count_up := 0;
elsif(r.count_up = c_page_size-1) then -- Pagereading is done, but there is not yet new data available
- v.rd_en := '0';
- v.state := s_idle;
+ v.rd_en := '0';
+ v.state := s_idle;
else
- v.count_up := r.count_up + 1;
+ v.count_up := r.count_up + 1;
end if;
- when others =>
- v.state := s_idle;
- end case;
+ when others =>
+ v.state := s_idle;
+ end case;
if(rst = '1') then
- v.switch := '0';
- v.rd_en := '0';
- v.count_up := 0;
- v.count_down := 0;
- v.count_chan := 0;
- v.state := s_idle;
+ v.switch := '0';
+ v.rd_en := '0';
+ v.count_up := 0;
+ v.count_down := 0;
+ v.count_chan := 0;
+ v.state := s_idle;
end if;
rin <= v;
@@ -330,14 +330,14 @@ begin
-- separate unit is connected to the output of rtwo_order_separate unit.
-- The 2nd stage of the separate funtion is performed:
u_separate : entity work.fft_sepa
- port map (
- clk => clk,
- rst => rst,
- in_dat => out_dat_i, -- c_dat_w
- in_val => out_val_i,
- out_dat => out_dat, -- c_dat_w + 2
- out_val => out_val
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => out_dat_i, -- c_dat_w
+ in_val => out_val_i,
+ out_dat => out_dat, -- c_dat_w + 2
+ out_val => out_val
+ );
end generate;
-- If the separate functionality is disabled the
diff --git a/libraries/dsp/fft/src/vhdl/fft_sepa.vhd b/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
index f9b660aaae..fcd8990453 100644
--- a/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
@@ -46,9 +46,9 @@
-- c_out_data_w = c_in_data_w + 1 bits, to avoid overflow.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity fft_sepa is
port (
@@ -92,36 +92,36 @@ begin
-- ADDER AND SUBTRACTOR
---------------------------------------------------------------
adder : entity common_lib.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0,
- g_pipeline_output => 1,
- g_in_dat_w => c_in_data_w,
- g_out_dat_w => c_out_data_w -- = c_in_data_w + 1
- )
- port map (
- clk => clk,
- in_a => r.add_reg_a,
- in_b => r.add_reg_b,
- result => add_result
- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0,
+ g_pipeline_output => 1,
+ g_in_dat_w => c_in_data_w,
+ g_out_dat_w => c_out_data_w -- = c_in_data_w + 1
+ )
+ port map (
+ clk => clk,
+ in_a => r.add_reg_a,
+ in_b => r.add_reg_b,
+ result => add_result
+ );
subtractor : entity common_lib.common_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0,
- g_pipeline_output => 1,
- g_in_dat_w => c_in_data_w,
- g_out_dat_w => c_out_data_w -- = c_in_data_w + 1
- )
- port map (
- clk => clk,
- in_a => r.sub_reg_a,
- in_b => r.sub_reg_b,
- result => sub_result
- );
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0,
+ g_pipeline_output => 1,
+ g_in_dat_w => c_in_data_w,
+ g_out_dat_w => c_out_data_w -- = c_in_data_w + 1
+ )
+ port map (
+ clk => clk,
+ in_a => r.sub_reg_a,
+ in_b => r.sub_reg_b,
+ result => sub_result
+ );
---------------------------------------------------------------
-- CONTROL PROCESS
diff --git a/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd b/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
index 720653a425..1de645c664 100644
--- a/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
@@ -39,10 +39,10 @@
--
library ieee, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.fft_pkg.all;
entity fft_sepa_wide is
generic (
@@ -125,43 +125,43 @@ begin
-- Counter will generate the write address
u_wr_adr_cnt : entity common_lib.common_counter
- generic map(
- g_latency => 1,
- g_init => 0,
- g_width => c_adr_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_en => in_val,
- count => wr_adr
- );
+ generic map(
+ g_latency => 1,
+ g_init => 0,
+ g_width => c_adr_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_en => in_val,
+ count => wr_adr
+ );
-- Instantiation of the rams.
gen_dual_paged_rams : for I in g_fft.wb_factor - 1 downto 0 generate
u_buff : entity common_lib.common_paged_ram_r_w
- generic map (
- g_str => "use_adr",
- g_data_w => c_dat_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_size,
- g_wr_start_page => 0,
- g_rd_start_page => 1,
- g_rd_latency => 1
- )
- port map (
- rst => rst,
- clk => clk,
- wr_next_page => next_page,
- wr_adr => wr_adr,
- wr_en => wr_en,
- wr_dat => wr_dat(I),
- rd_next_page => next_page,
- rd_adr => rd_adr_arr(I / (g_fft.wb_factor / 2)),
- rd_en => '1',
- rd_dat => rd_dat_arr(I),
- rd_val => open
- );
+ generic map (
+ g_str => "use_adr",
+ g_data_w => c_dat_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_size,
+ g_wr_start_page => 0,
+ g_rd_start_page => 1,
+ g_rd_latency => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_next_page => next_page,
+ wr_adr => wr_adr,
+ wr_en => wr_en,
+ wr_dat => wr_dat(I),
+ rd_next_page => next_page,
+ rd_adr => rd_adr_arr(I / (g_fft.wb_factor / 2)),
+ rd_en => '1',
+ rd_dat => rd_dat_arr(I),
+ rd_val => open
+ );
end generate;
-- Compose the read-addresses for the memories.
@@ -192,28 +192,28 @@ begin
-- adjacent separate unit.
gen_separators : for I in g_fft.wb_factor - 1 downto 0 generate
u_zipper : entity common_lib.common_zip
- generic map (
- g_nof_streams => c_nof_streams,
- g_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => zip_in_val(I),
- in_dat_arr => zip_in_matrix(I),
- out_val => zip_out_val(I),
- out_dat => zip_out_dat_arr(I)
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => zip_in_val(I),
+ in_dat_arr => zip_in_matrix(I),
+ out_val => zip_out_val(I),
+ out_dat => zip_out_dat_arr(I)
+ );
u_separate : entity work.fft_sepa
- port map (
- clk => clk,
- rst => rst,
- in_dat => zip_out_dat_arr(I), -- c_dat_w
- in_val => zip_out_val(I),
- out_dat => sep_out_dat_arr(I), -- c_dat_w + 2
- out_val => sep_out_val_vec(I)
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => zip_out_dat_arr(I), -- c_dat_w
+ in_val => zip_out_val(I),
+ out_dat => sep_out_dat_arr(I), -- c_dat_w + 2
+ out_val => sep_out_val_vec(I)
+ );
end generate;
---------------------------------------------------------------
@@ -235,25 +235,25 @@ begin
v.count_up := 0;
v.count_down := c_page_size;
if(next_page = '1') then -- Check if next page is asserted, meaning first page is written)
- v.state := s_read;
+ v.state := s_read;
end if;
when s_read =>
if(r.switch = '0') then -- Toggle the switch register from 0 to 1
- v.switch := '1';
+ v.switch := '1';
end if;
if(r.switch = '1') then -- Toggle the switch register from 1 to 0
- v.switch := '0';
- v.count_up := r.count_up + 1; -- Increment the upwards counter
- v.count_down := r.count_down - 1; -- Decrease the downwards counter
+ v.switch := '0';
+ v.count_up := r.count_up + 1; -- Increment the upwards counter
+ v.count_down := r.count_down - 1; -- Decrease the downwards counter
end if;
if(next_page = '1') then -- Both counters are reset on page turn.
- v.count_up := 0;
- v.count_down := c_page_size;
+ v.count_up := 0;
+ v.count_down := c_page_size;
elsif(v.count_up = c_page_size / 2) then -- Pagereading is done, but there is not yet new data available (Note that the value of variable v is checked here)
- v.state := s_idle; -- then go back to idle.
+ v.state := s_idle; -- then go back to idle.
end if;
v.val_odd := r.switch; -- Assignment of the odd and even markers
@@ -282,39 +282,39 @@ begin
---------------------------------------------------------------
gen_align_and_pipeline_stages : for I in g_fft.wb_factor / 2 - 1 downto 0 generate
u_output_pipeline_align : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_pipeline_output + 1, -- Pipeline + one stage for allignment
- g_in_dat_w => c_raw_dat_w,
- g_out_dat_w => c_raw_dat_w
- )
- port map (
- clk => clk,
- in_dat => sep_out_dat_arr(2 * I),
- out_dat => out_dat_arr(2 * I)
- );
+ generic map (
+ g_pipeline => c_pipeline_output + 1, -- Pipeline + one stage for allignment
+ g_in_dat_w => c_raw_dat_w,
+ g_out_dat_w => c_raw_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => sep_out_dat_arr(2 * I),
+ out_dat => out_dat_arr(2 * I)
+ );
u_output_pipeline : entity common_lib.common_pipeline
+ generic map (
+ g_pipeline => c_pipeline_output, -- Only pipeline stage
+ g_in_dat_w => c_raw_dat_w,
+ g_out_dat_w => c_raw_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => sep_out_dat_arr(2 * I + 1),
+ out_dat => out_dat_arr(2 * I + 1)
+ );
+ end generate;
+
+ u_out_val_pipeline : entity common_lib.common_pipeline_sl
generic map (
- g_pipeline => c_pipeline_output, -- Only pipeline stage
- g_in_dat_w => c_raw_dat_w,
- g_out_dat_w => c_raw_dat_w
+ g_pipeline => c_pipeline_output
)
port map (
clk => clk,
- in_dat => sep_out_dat_arr(2 * I + 1),
- out_dat => out_dat_arr(2 * I + 1)
+ in_dat => sep_out_val_vec(1),
+ out_dat => out_val
);
- end generate;
-
- u_out_val_pipeline : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_output
- )
- port map (
- clk => clk,
- in_dat => sep_out_val_vec(1),
- out_dat => out_val
- );
-- Split the concatenated array into a real and imaginary array for the output
gen_output_arrays : for I in g_fft.wb_factor - 1 downto 0 generate
diff --git a/libraries/dsp/fft/src/vhdl/fft_switch.vhd b/libraries/dsp/fft/src/vhdl/fft_switch.vhd
index e1732d2a81..1477be7ea2 100644
--- a/libraries/dsp/fft/src/vhdl/fft_switch.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_switch.vhd
@@ -44,9 +44,9 @@
-- enough, but scrambling both inputs is fine too.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.fft_pkg.all;
entity fft_switch is
generic (
@@ -86,20 +86,20 @@ architecture rtl of fft_switch is
begin
-- Create input strobes to view data blocks for debugging
u_in_strobes : entity common_lib.common_create_strobes_from_valid
- generic map (
- g_pipeline => false,
- g_nof_clk_per_sync => c_nof_clk_per_block * 16, -- void value, sync is not used
- g_nof_clk_per_block => c_nof_clk_per_block
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- out_val => OPEN, -- out_val = in_val, because g_pipeline = FALSE
- out_sop => in_sop,
- out_eop => in_eop,
- out_sync => open
- );
+ generic map (
+ g_pipeline => false,
+ g_nof_clk_per_sync => c_nof_clk_per_block * 16, -- void value, sync is not used
+ g_nof_clk_per_block => c_nof_clk_per_block
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ out_val => OPEN, -- out_val = in_val, because g_pipeline = FALSE
+ out_sop => in_sop,
+ out_eop => in_eop,
+ out_sync => open
+ );
no_switch : if g_switch_en = false generate
-- wire inputs to outputs
@@ -155,17 +155,17 @@ begin
end process;
u_fft_lfsr: entity work.fft_lfsr
- generic map (
- g_seed1 => g_seed1,
- g_seed2 => g_seed2
- )
- port map (
- clk => clk,
- rst => rst,
- in_en => lfsr_en,
- out_bit1 => lfsr_bit1,
- out_bit2 => lfsr_bit2
- );
+ generic map (
+ g_seed1 => g_seed1,
+ g_seed2 => g_seed2
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_en => lfsr_en,
+ out_bit1 => lfsr_bit1,
+ out_bit2 => lfsr_bit2
+ );
end generate;
end rtl;
diff --git a/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd b/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
index 9d1ad5ef00..fabaf84965 100644
--- a/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
@@ -29,9 +29,9 @@
-- c_nof_clk_per_block samples, forever after rst release.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.fft_pkg.all;
entity fft_unswitch is
generic (
@@ -72,20 +72,20 @@ architecture rtl of fft_unswitch is
begin
-- Create input strobes to view data blocks for debugging
u_in_strobes : entity common_lib.common_create_strobes_from_valid
- generic map (
- g_pipeline => false,
- g_nof_clk_per_sync => c_nof_clk_per_block * 16, -- void value, sync is not used
- g_nof_clk_per_block => c_nof_clk_per_block
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- out_val => OPEN, -- out_val = in_val, because g_pipeline = FALSE
- out_sop => in_sop,
- out_eop => in_eop,
- out_sync => open
- );
+ generic map (
+ g_pipeline => false,
+ g_nof_clk_per_sync => c_nof_clk_per_block * 16, -- void value, sync is not used
+ g_nof_clk_per_block => c_nof_clk_per_block
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ out_val => OPEN, -- out_val = in_val, because g_pipeline = FALSE
+ out_sop => in_sop,
+ out_eop => in_eop,
+ out_sync => open
+ );
no_switch : if g_switch_en = false generate
-- wire inputs to outputs
@@ -147,17 +147,17 @@ begin
end process;
u_fft_lfsr: entity work.fft_lfsr
- generic map (
- g_seed1 => g_seed1,
- g_seed2 => g_seed2
- )
- port map (
- clk => clk,
- rst => rst,
- in_en => lfsr_en,
- out_bit1 => lfsr_bit1,
- out_bit2 => lfsr_bit2
- );
+ generic map (
+ g_seed1 => g_seed1,
+ g_seed2 => g_seed2
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_en => lfsr_en,
+ out_bit1 => lfsr_bit1,
+ out_bit2 => lfsr_bit2
+ );
end generate;
end rtl;
diff --git a/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd b/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd
index 3134ef587f..cd28457065 100644
--- a/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd
@@ -34,13 +34,13 @@
-- stages of the wideband fft.
library ieee, common_lib, dp_lib, rTwoSDF_lib, st_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use st_lib.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use st_lib.all;
+ use work.fft_pkg.all;
entity fft_wide_unit is
generic (
@@ -110,16 +110,16 @@ begin
-- statistics to one array that is connected to the port of the
-- fft_wide_unit.
u_mem_mux_sst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_fft.wb_factor,
- g_mult_addr_w => ceil_log2(g_fft.stat_data_sz * c_nof_stats)
- )
- port map (
- mosi => ram_st_sst_mosi,
- miso => ram_st_sst_miso,
- mosi_arr => ram_st_sst_mosi_arr,
- miso_arr => ram_st_sst_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_fft.wb_factor,
+ g_mult_addr_w => ceil_log2(g_fft.stat_data_sz * c_nof_stats)
+ )
+ port map (
+ mosi => ram_st_sst_mosi,
+ miso => ram_st_sst_miso,
+ mosi_arr => ram_st_sst_mosi_arr,
+ miso_arr => ram_st_sst_miso_arr
+ );
---------------------------------------------------------------
-- PREPARE INPUT DATA FOR WIDEBAND FFT
@@ -135,21 +135,21 @@ begin
-- THE WIDEBAND FFT
---------------------------------------------------------------
u_fft_wide : entity work.fft_r2_wide
- generic map(
- g_fft => g_fft, -- generics for the WFFT
- g_pft_pipeline => g_pft_pipeline,
- g_fft_pipeline => g_fft_pipeline
- )
- port map(
- clk => dp_clk,
- rst => dp_rst,
- in_re_arr => fft_in_re_arr,
- in_im_arr => fft_in_im_arr,
- in_val => r.in_sosi_arr(0).valid,
- out_re_arr => fft_out_re_arr,
- out_im_arr => fft_out_im_arr,
- out_val => fft_out_val
- );
+ generic map(
+ g_fft => g_fft, -- generics for the WFFT
+ g_pft_pipeline => g_pft_pipeline,
+ g_fft_pipeline => g_fft_pipeline
+ )
+ port map(
+ clk => dp_clk,
+ rst => dp_rst,
+ in_re_arr => fft_in_re_arr,
+ in_im_arr => fft_in_im_arr,
+ in_val => r.in_sosi_arr(0).valid,
+ out_re_arr => fft_out_re_arr,
+ out_im_arr => fft_out_im_arr,
+ out_val => fft_out_val
+ );
---------------------------------------------------------------
-- FFT CONTROL UNIT
@@ -157,18 +157,18 @@ begin
-- The fft control unit composes the output array in the dp-
-- streaming format.
u_fft_control : entity work.fft_wide_unit_control
- generic map (
- g_fft => g_fft
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- in_re_arr => fft_out_re_arr,
- in_im_arr => fft_out_im_arr,
- in_val => fft_out_val,
- ctrl_sosi => r.in_sosi_arr(0),
- out_sosi_arr => fft_out_sosi_arr
- );
+ generic map (
+ g_fft => g_fft
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ in_re_arr => fft_out_re_arr,
+ in_im_arr => fft_out_im_arr,
+ in_val => fft_out_val,
+ ctrl_sosi => r.in_sosi_arr(0),
+ out_sosi_arr => fft_out_sosi_arr
+ );
---------------------------------------------------------------
-- SUBBAND STATISTICS
@@ -180,43 +180,43 @@ begin
-- than 18 bit. Therefor a quantizer is inserted.
gen_subband_stats: for I in 0 to g_fft.wb_factor - 1 generate
u_quantizer_for_bst : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => true,
- g_msb_clip_symmetric => true,
- g_pipeline_remove_lsb => 1,
- g_pipeline_remove_msb => 1,
- g_in_dat_w => g_fft.out_dat_w,
- g_out_dat_w => g_fft.stage_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => fft_out_sosi_arr(I),
- src_out => sst_in_sosi_arr(I),
- out_ovr => open
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => true,
+ g_pipeline_remove_lsb => 1,
+ g_pipeline_remove_msb => 1,
+ g_in_dat_w => g_fft.out_dat_w,
+ g_out_dat_w => g_fft.stage_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => fft_out_sosi_arr(I),
+ src_out => sst_in_sosi_arr(I),
+ out_ovr => open
+ );
u_subband_stats : entity st_lib.st_sst
- generic map(
- g_nof_stat => c_nof_stats,
- g_in_data_w => g_fft.stage_dat_w,
- g_stat_data_w => g_fft.stat_data_w,
- g_stat_data_sz => g_fft.stat_data_sz
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_complex => sst_in_sosi_arr(I),
- ram_st_sst_mosi => ram_st_sst_mosi_arr(I),
- ram_st_sst_miso => ram_st_sst_miso_arr(I)
- );
+ generic map(
+ g_nof_stat => c_nof_stats,
+ g_in_data_w => g_fft.stage_dat_w,
+ g_stat_data_w => g_fft.stat_data_w,
+ g_stat_data_sz => g_fft.stat_data_sz
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_complex => sst_in_sosi_arr(I),
+ ram_st_sst_mosi => ram_st_sst_mosi_arr(I),
+ ram_st_sst_miso => ram_st_sst_miso_arr(I)
+ );
end generate;
-- Connect to the outside world
diff --git a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
index c31e4c1881..56d53dd2d4 100644
--- a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
@@ -37,12 +37,12 @@
--
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.fft_pkg.all;
entity fft_wide_unit_control is
generic (
@@ -94,93 +94,93 @@ begin
-- INPUT FIFO FOR BSN
---------------------------------------------------------------
u_bsn_fifo : entity common_lib.common_fifo_sc
- generic map (
- g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep.
- g_reset => false,
- g_init => false,
- g_dat_w => c_dp_stream_bsn_w,
- g_nof_words => c_ctrl_fifo_depth
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => ctrl_sosi.bsn,
- wr_req => ctrl_sosi.sop,
- wr_ful => open ,
- rd_dat => bsn,
- rd_req => r.sop_dly(0),
- rd_emp => open ,
- rd_val => open ,
- usedw => open
- );
+ generic map (
+ g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep.
+ g_reset => false,
+ g_init => false,
+ g_dat_w => c_dp_stream_bsn_w,
+ g_nof_words => c_ctrl_fifo_depth
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => ctrl_sosi.bsn,
+ wr_req => ctrl_sosi.sop,
+ wr_ful => open ,
+ rd_dat => bsn,
+ rd_req => r.sop_dly(0),
+ rd_emp => open ,
+ rd_val => open ,
+ usedw => open
+ );
---------------------------------------------------------------
-- INPUT FIFO FOR ERR
---------------------------------------------------------------
u_error_fifo : entity common_lib.common_fifo_sc
- generic map (
- g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep.
- g_reset => false,
- g_init => false,
- g_dat_w => c_dp_stream_error_w,
- g_nof_words => c_ctrl_fifo_depth
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => ctrl_sosi.err,
- wr_req => ctrl_sosi.sop,
- wr_ful => open ,
- rd_dat => err,
- rd_req => r.sop_dly(1),
- rd_emp => open ,
- rd_val => open ,
- usedw => open
- );
+ generic map (
+ g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep.
+ g_reset => false,
+ g_init => false,
+ g_dat_w => c_dp_stream_error_w,
+ g_nof_words => c_ctrl_fifo_depth
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => ctrl_sosi.err,
+ wr_req => ctrl_sosi.sop,
+ wr_ful => open ,
+ rd_dat => err,
+ rd_req => r.sop_dly(1),
+ rd_emp => open ,
+ rd_val => open ,
+ usedw => open
+ );
---------------------------------------------------------------
-- FIFO FOR SYNC-BSN
---------------------------------------------------------------
u_sync_bsn_fifo : entity common_lib.common_fifo_sc
- generic map (
- g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep.
- g_reset => false,
- g_init => false,
- g_dat_w => c_dp_stream_bsn_w,
- g_nof_words => 2
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => ctrl_sosi.bsn,
- wr_req => ctrl_sosi.sync,
- wr_ful => open ,
- rd_dat => rd_dat_i,
- rd_req => rd_req_i,
- rd_emp => open,
- rd_val => rd_val_i,
- usedw => open
- );
+ generic map (
+ g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep.
+ g_reset => false,
+ g_init => false,
+ g_dat_w => c_dp_stream_bsn_w,
+ g_nof_words => 2
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => ctrl_sosi.bsn,
+ wr_req => ctrl_sosi.sync,
+ wr_ful => open ,
+ rd_dat => rd_dat_i,
+ rd_req => rd_req_i,
+ rd_emp => open,
+ rd_val => rd_val_i,
+ usedw => open
+ );
---------------------------------------------------------------
-- CREATE READ-AHEAD FIFO INTERFACE FOR SYNC-BSN
---------------------------------------------------------------
u_fifo_adapter : entity common_lib.common_fifo_rd
- generic map (
- g_dat_w => c_dp_stream_bsn_w
- )
- port map(
- rst => rst,
- clk => clk,
- -- ST sink: RL = 1
- fifo_req => rd_req_i,
- fifo_dat => rd_dat_i,
- fifo_val => rd_val_i,
- -- ST source: RL = 0
- rd_req => rd_req,
- rd_dat => sync_bsn,
- rd_val => open
- );
+ generic map (
+ g_dat_w => c_dp_stream_bsn_w
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ -- ST sink: RL = 1
+ fifo_req => rd_req_i,
+ fifo_dat => rd_dat_i,
+ fifo_val => rd_val_i,
+ -- ST source: RL = 0
+ rd_req => rd_req,
+ rd_dat => sync_bsn,
+ rd_val => open
+ );
rd_req <= r.out_sosi_arr(0).sync; -- (r.sync_detected and not(rd_emp)) or r.rd_first;
@@ -220,55 +220,55 @@ begin
end loop;
if(ctrl_sosi.sync = '1') then -- Check which bsn accompanies the sync
- v.sync_detected := '1';
+ v.sync_detected := '1';
end if;
if(sync_bsn = bsn and r.sop_dly(1) = '1' and r.sync_detected = '1') then -- When the next bsn equals the stored bsn
- for I in g_fft.wb_factor - 1 downto 0 loop -- a sync pulse will be generated that
- v.out_sosi_arr(I).sync := '1'; -- preceeds the sop
- end loop;
- v.sync_detected := '0';
+ for I in g_fft.wb_factor - 1 downto 0 loop -- a sync pulse will be generated that
+ v.out_sosi_arr(I).sync := '1'; -- preceeds the sop
+ end loop;
+ v.sync_detected := '0';
end if;
case r.state is
- when s_idle =>
- if(in_val = '1') then -- Wait for the first data to arrive
- v.packet_cnt := 0; -- Reset the packet counter
- v.state := s_run;
- end if;
+ when s_idle =>
+ if(in_val = '1') then -- Wait for the first data to arrive
+ v.packet_cnt := 0; -- Reset the packet counter
+ v.state := s_run;
+ end if;
- when s_run =>
- v.val_dly(0) := '1'; -- Assert the valid signal (Stream starts)
- v.packet_cnt := r.packet_cnt + 1; -- Increment the packet-counter when in s_run-state
+ when s_run =>
+ v.val_dly(0) := '1'; -- Assert the valid signal (Stream starts)
+ v.packet_cnt := r.packet_cnt + 1; -- Increment the packet-counter when in s_run-state
if(r.packet_cnt = 0) then -- First sample marks
- v.sop_dly(0) := '1'; -- the start of a packet
+ v.sop_dly(0) := '1'; -- the start of a packet
elsif(r.packet_cnt = c_packet_size-1) then -- Last address marks
- v.eop_dly(0) := '1'; -- the end of a packet
- v.packet_cnt := 0; -- Reset the counter
+ v.eop_dly(0) := '1'; -- the end of a packet
+ v.packet_cnt := 0; -- Reset the counter
end if;
if(in_val = '0') then -- If there is no more data:
- v.state := s_hold; -- go wait in the s_hold state
+ v.state := s_hold; -- go wait in the s_hold state
end if;
when s_hold =>
if(in_val = '1') then -- Wait until new valid data arrives
- v.state := s_run;
+ v.state := s_run;
end if;
- when others =>
- v.state := s_idle;
- end case;
+ when others =>
+ v.state := s_idle;
+ end case;
if(rst = '1') then
- v.out_sosi_arr := (others => c_dp_sosi_rst);
- v.val_dly := (others => '0');
- v.sop_dly := (others => '0');
- v.eop_dly := (others => '0');
- v.sync_detected := '0';
- v.packet_cnt := 0;
- v.state := s_idle;
+ v.out_sosi_arr := (others => c_dp_sosi_rst);
+ v.val_dly := (others => '0');
+ v.sop_dly := (others => '0');
+ v.eop_dly := (others => '0');
+ v.sync_detected := '0';
+ v.packet_cnt := 0;
+ v.state := s_idle;
end if;
rin <= v;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd
index 739b0cba34..834e27c47f 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd
@@ -30,10 +30,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.fft_pkg.all;
-use work.tb_fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.fft_pkg.all;
+ use work.tb_fft_pkg.all;
entity tb_fft_functions is
end tb_fft_functions;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd
index 8acfe181c4..3deb37b0c9 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd
@@ -31,9 +31,9 @@
-- start to differ after about c_fft_lfsr_len blocks. Similar for
-- u0_lfsr_bit1 and u1_lfsr_bit1.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.fft_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.fft_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_fft_lfsr is
end tb_fft_lfsr;
@@ -61,28 +61,28 @@ begin
proc_common_gen_pulse(1, c_block_period, '1', rst, clk, in_en);
u0 : entity work.fft_lfsr
- generic map (
- g_seed1 => fft_switch_new_seed(c_fft_switch_seed1, 0),
- g_seed2 => fft_switch_new_seed(c_fft_switch_seed2, 0)
- )
- port map (
- in_en => in_en,
- out_bit1 => u0_lfsr_bit1,
- out_bit2 => u0_lfsr_bit2,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_seed1 => fft_switch_new_seed(c_fft_switch_seed1, 0),
+ g_seed2 => fft_switch_new_seed(c_fft_switch_seed2, 0)
+ )
+ port map (
+ in_en => in_en,
+ out_bit1 => u0_lfsr_bit1,
+ out_bit2 => u0_lfsr_bit2,
+ clk => clk,
+ rst => rst
+ );
u1 : entity work.fft_lfsr
- generic map (
- g_seed1 => fft_switch_new_seed(c_fft_switch_seed1, 1),
- g_seed2 => fft_switch_new_seed(c_fft_switch_seed2, 1)
- )
- port map (
- in_en => in_en,
- out_bit1 => u1_lfsr_bit1,
- out_bit2 => u1_lfsr_bit2,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_seed1 => fft_switch_new_seed(c_fft_switch_seed1, 1),
+ g_seed2 => fft_switch_new_seed(c_fft_switch_seed2, 1)
+ )
+ port map (
+ in_en => in_en,
+ out_bit1 => u1_lfsr_bit1,
+ out_bit2 => u1_lfsr_bit2,
+ clk => clk,
+ rst => rst
+ );
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
index b566285a29..561c62145f 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_textio.all;
-use STD.textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.std_logic_textio.all;
+ use STD.textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.fft_pkg.all;
package tb_fft_pkg is
constant c_fft_nof_subbands_max : natural := 256;
@@ -41,52 +41,57 @@ package tb_fft_pkg is
function fft_index_to_bin_frequency(wb_factor, nof_points, index : natural; use_reorder, use_fft_shift, use_separate : boolean) return natural;
-- use out_val and out_val_cnt to determine the FFT output bin frequency and channel
- procedure proc_fft_out_control(wb_factor : natural;
- nof_points : natural;
- nof_channels : natural;
- use_reorder : boolean;
- use_fft_shift : boolean;
- use_separate : boolean;
- signal out_val_cnt : in natural; -- count at sclk sample rate
- signal out_val : in std_logic;
- signal out_val_a : out std_logic;
- signal out_val_b : out std_logic;
- signal out_channel : out natural;
- signal out_bin : out natural;
- signal out_bin_cnt : out natural);
-
- procedure proc_read_input_file(signal clk : in std_logic;
- signal in_file_data : out t_integer_matrix;
- signal in_file_sync : out std_logic_vector;
- signal in_file_val : out std_logic_vector;
- file_name : in string);
-
- procedure proc_read_input_file(signal clk : in std_logic; -- Same read procedure for data files that do not contain a valid and sync column
- signal in_file_data : out t_integer_matrix;
- file_name : in string);
-
- procedure proc_fft_read_subband_statistics_memory(constant c_fft_lane : in natural;
- constant c_fft : in t_fft;
- signal clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- signal statistics_arr : out t_slv_64_arr);
+ procedure proc_fft_out_control(
+ wb_factor : natural;
+ nof_points : natural;
+ nof_channels : natural;
+ use_reorder : boolean;
+ use_fft_shift : boolean;
+ use_separate : boolean;
+ signal out_val_cnt : in natural; -- count at sclk sample rate
+ signal out_val : in std_logic;
+ signal out_val_a : out std_logic;
+ signal out_val_b : out std_logic;
+ signal out_channel : out natural;
+ signal out_bin : out natural;
+ signal out_bin_cnt : out natural);
+
+ procedure proc_read_input_file(
+ signal clk : in std_logic;
+ signal in_file_data : out t_integer_matrix;
+ signal in_file_sync : out std_logic_vector;
+ signal in_file_val : out std_logic_vector;
+ file_name : in string);
+
+ procedure proc_read_input_file(
+ signal clk : in std_logic; -- Same read procedure for data files that do not contain a valid and sync column
+ signal in_file_data : out t_integer_matrix;
+ file_name : in string);
+
+ procedure proc_fft_read_subband_statistics_memory(
+ constant c_fft_lane : in natural;
+ constant c_fft : in t_fft;
+ signal clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ signal statistics_arr : out t_slv_64_arr);
-- Private procedures
- procedure proc_read_subband_stats(constant nof_subbands : in natural;
- constant offset : in natural;
- signal clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- variable result : out t_slv_64_arr);
-
--- PROCEDURE proc_prepare_input_data(CONSTANT nof_subbands : IN NATURAL;
--- CONSTANT nof_inputs : IN NATURAL;
--- CONSTANT nof_input_streams : IN NATURAL;
--- CONSTANT input_stream_number : IN NATURAL;
--- VARIABLE re_arr : OUT t_integer_arr;
--- VARIABLE im_arr : OUT t_integer_arr;
--- file_name : IN STRING);
+ procedure proc_read_subband_stats(
+ constant nof_subbands : in natural;
+ constant offset : in natural;
+ signal clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ variable result : out t_slv_64_arr);
+
+ -- PROCEDURE proc_prepare_input_data(CONSTANT nof_subbands : IN NATURAL;
+ -- CONSTANT nof_inputs : IN NATURAL;
+ -- CONSTANT nof_input_streams : IN NATURAL;
+ -- CONSTANT input_stream_number : IN NATURAL;
+ -- VARIABLE re_arr : OUT t_integer_arr;
+ -- VARIABLE im_arr : OUT t_integer_arr;
+ -- file_name : IN STRING);
end tb_fft_pkg;
package body tb_fft_pkg is
@@ -356,19 +361,20 @@ package body tb_fft_pkg is
return v_bin;
end fft_index_to_bin_frequency;
- procedure proc_fft_out_control(wb_factor : natural;
- nof_points : natural;
- nof_channels : natural;
- use_reorder : boolean;
- use_fft_shift : boolean;
- use_separate : boolean;
- signal out_val_cnt : in natural; -- count at sclk sample rate
- signal out_val : in std_logic;
- signal out_val_a : out std_logic;
- signal out_val_b : out std_logic;
- signal out_channel : out natural;
- signal out_bin : out natural;
- signal out_bin_cnt : out natural) is
+ procedure proc_fft_out_control(
+ wb_factor : natural;
+ nof_points : natural;
+ nof_channels : natural;
+ use_reorder : boolean;
+ use_fft_shift : boolean;
+ use_separate : boolean;
+ signal out_val_cnt : in natural; -- count at sclk sample rate
+ signal out_val : in std_logic;
+ signal out_val_a : out std_logic;
+ signal out_val_b : out std_logic;
+ signal out_channel : out natural;
+ signal out_bin : out natural;
+ signal out_bin_cnt : out natural) is
-- Purpose: Derive reference control signals from FFT out_val, out_val_cnt
-- and derive an index per block that can be used to determine
-- the frequency bin with fft_index_to_bin_frequency().
@@ -425,7 +431,7 @@ package body tb_fft_pkg is
out_channel <= (out_val_cnt / wb_factor) mod nof_channels; -- the nof_channels are interleaved per wb_factor number of samples
v_index := ((out_val_cnt / wb_factor / nof_channels) * wb_factor +
- (out_val_cnt mod wb_factor)) mod nof_points; -- index within a block independent of nof_channels
+ (out_val_cnt mod wb_factor)) mod nof_points; -- index within a block independent of nof_channels
v_bin := fft_index_to_bin_frequency(wb_factor, nof_points, v_index, use_reorder, use_fft_shift, use_separate);
@@ -439,11 +445,12 @@ package body tb_fft_pkg is
-- Reads data (re, im, sync and val) from a file and writes values
-- to the output signals.
------------------------------------------------------------------------------
- procedure proc_read_input_file( signal clk : in std_logic;
- signal in_file_data : out t_integer_matrix;
- signal in_file_sync : out std_logic_vector;
- signal in_file_val : out std_logic_vector;
- file_name : in string) is
+ procedure proc_read_input_file(
+ signal clk : in std_logic;
+ signal in_file_data : out t_integer_matrix;
+ signal in_file_sync : out std_logic_vector;
+ signal in_file_val : out std_logic_vector;
+ file_name : in string) is
variable v_file_status : FILE_OPEN_STATUS;
file v_in_file : TEXT;
@@ -452,41 +459,41 @@ package body tb_fft_pkg is
variable v_index : integer := 0;
variable v_comma : character;
variable v_sync : std_logic_vector(in_file_sync'range) := (others => '0');
- variable v_val : std_logic_vector(in_file_val'range) := (others => '0');
- variable v_data : t_integer_matrix(in_file_sync'RANGE, 1 to 2) := (others => (others => 0));
+ variable v_val : std_logic_vector(in_file_val'range) := (others => '0');
+ variable v_data : t_integer_matrix(in_file_sync'RANGE, 1 to 2) := (others => (others => 0));
begin
- -- wait 1 clock cycle to avoid that the output messages
- -- in the transcript window get lost in the 0 ps start up messages
- proc_common_wait_some_cycles(clk, 1);
- write(v_log_line, string'("reading file : "));
- write(v_log_line, file_name);
- writeline(output, v_log_line);
- proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE); -- Open the file with data values for reading
- loop
- exit when endfile(v_in_file);
- readline(v_in_file, v_input_line);
-
- read(v_input_line, v_sync(v_index)); -- sync
- read(v_input_line, v_comma);
-
- read(v_input_line, v_val(v_index)); -- valid
- read(v_input_line, v_comma);
-
- read(v_input_line, v_data(v_index,1)); -- real
- read(v_input_line, v_comma);
-
- read(v_input_line, v_data(v_index,2)); -- imag
- v_index := v_index + 1;
- end loop;
- proc_common_close_file(v_file_status, v_in_file); -- Close the file
- write(v_log_line, string'("finished reading file : "));
- write(v_log_line, file_name);
- writeline(output, v_log_line);
-
- in_file_data <= v_data;
- in_file_sync <= v_sync;
- in_file_val <= v_val;
- wait;
+ -- wait 1 clock cycle to avoid that the output messages
+ -- in the transcript window get lost in the 0 ps start up messages
+ proc_common_wait_some_cycles(clk, 1);
+ write(v_log_line, string'("reading file : "));
+ write(v_log_line, file_name);
+ writeline(output, v_log_line);
+ proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE); -- Open the file with data values for reading
+ loop
+ exit when endfile(v_in_file);
+ readline(v_in_file, v_input_line);
+
+ read(v_input_line, v_sync(v_index)); -- sync
+ read(v_input_line, v_comma);
+
+ read(v_input_line, v_val(v_index)); -- valid
+ read(v_input_line, v_comma);
+
+ read(v_input_line, v_data(v_index,1)); -- real
+ read(v_input_line, v_comma);
+
+ read(v_input_line, v_data(v_index,2)); -- imag
+ v_index := v_index + 1;
+ end loop;
+ proc_common_close_file(v_file_status, v_in_file); -- Close the file
+ write(v_log_line, string'("finished reading file : "));
+ write(v_log_line, file_name);
+ writeline(output, v_log_line);
+
+ in_file_data <= v_data;
+ in_file_sync <= v_sync;
+ in_file_val <= v_val;
+ wait;
end proc_read_input_file;
------------------------------------------------------------------------------
@@ -494,9 +501,10 @@ package body tb_fft_pkg is
-- Reads data (re, im, sync and val) from a file and writes values
-- to the output signals.
------------------------------------------------------------------------------
- procedure proc_read_input_file( signal clk : in std_logic;
- signal in_file_data : out t_integer_matrix;
- file_name : in string) is
+ procedure proc_read_input_file(
+ signal clk : in std_logic;
+ signal in_file_data : out t_integer_matrix;
+ file_name : in string) is
variable v_file_status : FILE_OPEN_STATUS;
file v_in_file : TEXT;
@@ -506,72 +514,74 @@ package body tb_fft_pkg is
variable v_comma : character;
variable v_data : t_integer_matrix(in_file_data'RANGE, 1 to 2) := (others => (others => 0));
begin
- -- wait 1 clock cycle to avoid that the output messages
- -- in the transcript window get lost in the 0 ps start up messages
- proc_common_wait_some_cycles(clk, 1);
- write(v_log_line, string'("reading file : "));
- write(v_log_line, file_name);
- writeline(output, v_log_line);
- proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE); -- Open the file with data values for reading
- loop
- exit when v_index = in_file_data'high + 1;
- readline(v_in_file, v_input_line);
-
- read(v_input_line, v_data(v_index,1)); -- real
- read(v_input_line, v_comma);
-
- read(v_input_line, v_data(v_index,2)); -- imag
- v_index := v_index + 1;
- end loop;
- proc_common_close_file(v_file_status, v_in_file); -- Close the file
- write(v_log_line, string'("finished reading file : "));
- write(v_log_line, file_name);
- writeline(output, v_log_line);
-
- in_file_data <= v_data;
- wait;
+ -- wait 1 clock cycle to avoid that the output messages
+ -- in the transcript window get lost in the 0 ps start up messages
+ proc_common_wait_some_cycles(clk, 1);
+ write(v_log_line, string'("reading file : "));
+ write(v_log_line, file_name);
+ writeline(output, v_log_line);
+ proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE); -- Open the file with data values for reading
+ loop
+ exit when v_index = in_file_data'high + 1;
+ readline(v_in_file, v_input_line);
+
+ read(v_input_line, v_data(v_index,1)); -- real
+ read(v_input_line, v_comma);
+
+ read(v_input_line, v_data(v_index,2)); -- imag
+ v_index := v_index + 1;
+ end loop;
+ proc_common_close_file(v_file_status, v_in_file); -- Close the file
+ write(v_log_line, string'("finished reading file : "));
+ write(v_log_line, file_name);
+ writeline(output, v_log_line);
+
+ in_file_data <= v_data;
+ wait;
end proc_read_input_file;
------------------------------------------------------------------------------
-- PROCEDURE: Read the beamlet statistics memory into an matrix
------------------------------------------------------------------------------
- procedure proc_fft_read_subband_statistics_memory(constant c_fft_lane : in natural;
- constant c_fft : in t_fft;
- signal clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- signal statistics_arr : out t_slv_64_arr) is
+ procedure proc_fft_read_subband_statistics_memory(
+ constant c_fft_lane : in natural;
+ constant c_fft : in t_fft;
+ signal clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ signal statistics_arr : out t_slv_64_arr) is
variable v_offset : natural;
variable v_nof_stats : natural := c_fft.nof_points / c_fft.wb_factor;
variable v_statistics_arr : t_slv_64_arr(statistics_arr'range);
begin
- v_offset := c_fft_lane * c_fft.stat_data_sz * v_nof_stats;
- proc_read_subband_stats(v_nof_stats, v_offset, clk, mm_mosi, mm_miso, v_statistics_arr);
- statistics_arr <= v_statistics_arr;
- proc_common_wait_some_cycles(clk, 1); -- ensure that the last statistics_arr value gets assigned too
+ v_offset := c_fft_lane * c_fft.stat_data_sz * v_nof_stats;
+ proc_read_subband_stats(v_nof_stats, v_offset, clk, mm_mosi, mm_miso, v_statistics_arr);
+ statistics_arr <= v_statistics_arr;
+ proc_common_wait_some_cycles(clk, 1); -- ensure that the last statistics_arr value gets assigned too
end proc_fft_read_subband_statistics_memory;
------------------------------------------------------------------------------
-- PROCEDURE: Reads the beamlet statistics into an array.
------------------------------------------------------------------------------
- procedure proc_read_subband_stats( constant nof_subbands : in natural;
- constant offset : in natural;
- signal clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- variable result : out t_slv_64_arr) is
+ procedure proc_read_subband_stats(
+ constant nof_subbands : in natural;
+ constant offset : in natural;
+ signal clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ variable result : out t_slv_64_arr) is
variable v_data_lo : std_logic_vector(31 downto 0);
begin
- for J in 0 to nof_subbands - 1 loop
- -- Memory is 32-bit, therefor each power value (56-bit wide) must be composed out of two reads.
- proc_mem_mm_bus_rd(offset + 2 * J, clk, mm_mosi);
- proc_common_wait_some_cycles(clk, 1);
- v_data_lo := mm_miso.rddata(31 downto 0);
- proc_mem_mm_bus_rd(offset + 2 * J + 1, clk, mm_mosi);
- proc_common_wait_some_cycles(clk, 1);
- result(J) := mm_miso.rddata(31 downto 0) & v_data_lo;
- end loop;
+ for J in 0 to nof_subbands - 1 loop
+ -- Memory is 32-bit, therefor each power value (56-bit wide) must be composed out of two reads.
+ proc_mem_mm_bus_rd(offset + 2 * J, clk, mm_mosi);
+ proc_common_wait_some_cycles(clk, 1);
+ v_data_lo := mm_miso.rddata(31 downto 0);
+ proc_mem_mm_bus_rd(offset + 2 * J + 1, clk, mm_mosi);
+ proc_common_wait_some_cycles(clk, 1);
+ result(J) := mm_miso.rddata(31 downto 0) & v_data_lo;
+ end loop;
end proc_read_subband_stats;
------------------------------------------------------------------------------
@@ -579,28 +589,28 @@ package body tb_fft_pkg is
-- Combinatorial read data from source file and re-arrange in such
-- a way that it represents the data of one input stream
------------------------------------------------------------------------------
--- PROCEDURE proc_prepare_input_data( CONSTANT nof_subbands : IN NATURAL;
--- CONSTANT nof_inputs : IN NATURAL;
--- CONSTANT nof_input_streams : IN NATURAL;
--- CONSTANT input_stream_number : IN NATURAL;
--- VARIABLE re_arr : OUT t_integer_arr;
--- VARIABLE im_arr : OUT t_integer_arr;
--- file_name : IN STRING) IS
--- VARIABLE v_file_status : FILE_OPEN_STATUS;
--- FILE v_in_file : TEXT;
--- VARIABLE v_line : LINE;
--- VARIABLE v_in_temp : t_integer_arr(2*nof_inputs-1 downto 0);
--- CONSTANT c_nof_signal_inputs_per_input_stream : NATURAL := nof_inputs/nof_input_streams;
--- BEGIN
--- proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE); -- Open the file with data values for reading
--- FOR I IN 0 TO nof_subbands-1 LOOP
--- proc_common_readline_file(v_file_status, v_in_file, v_in_temp, 2*nof_inputs); -- Read line with complex subband samples from all inputs
--- FOR J IN 0 TO c_nof_signal_inputs_per_input_stream-1 LOOP
--- re_arr(J*nof_subbands+I) := v_in_temp(2*(J+input_stream_number*c_nof_signal_inputs_per_input_stream));
--- im_arr(J*nof_subbands+I) := v_in_temp(2*(J+input_stream_number*c_nof_signal_inputs_per_input_stream)+1);
--- END LOOP;
--- END LOOP;
--- proc_common_close_file(v_file_status, v_in_file); -- Close the file
--- END proc_prepare_input_data;
+ -- PROCEDURE proc_prepare_input_data( CONSTANT nof_subbands : IN NATURAL;
+ -- CONSTANT nof_inputs : IN NATURAL;
+ -- CONSTANT nof_input_streams : IN NATURAL;
+ -- CONSTANT input_stream_number : IN NATURAL;
+ -- VARIABLE re_arr : OUT t_integer_arr;
+ -- VARIABLE im_arr : OUT t_integer_arr;
+ -- file_name : IN STRING) IS
+ -- VARIABLE v_file_status : FILE_OPEN_STATUS;
+ -- FILE v_in_file : TEXT;
+ -- VARIABLE v_line : LINE;
+ -- VARIABLE v_in_temp : t_integer_arr(2*nof_inputs-1 downto 0);
+ -- CONSTANT c_nof_signal_inputs_per_input_stream : NATURAL := nof_inputs/nof_input_streams;
+ -- BEGIN
+ -- proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE); -- Open the file with data values for reading
+ -- FOR I IN 0 TO nof_subbands-1 LOOP
+ -- proc_common_readline_file(v_file_status, v_in_file, v_in_temp, 2*nof_inputs); -- Read line with complex subband samples from all inputs
+ -- FOR J IN 0 TO c_nof_signal_inputs_per_input_stream-1 LOOP
+ -- re_arr(J*nof_subbands+I) := v_in_temp(2*(J+input_stream_number*c_nof_signal_inputs_per_input_stream));
+ -- im_arr(J*nof_subbands+I) := v_in_temp(2*(J+input_stream_number*c_nof_signal_inputs_per_input_stream)+1);
+ -- END LOOP;
+ -- END LOOP;
+ -- proc_common_close_file(v_file_status, v_in_file); -- Close the file
+ -- END proc_prepare_input_data;
end tb_fft_pkg;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd
index 18b7abe7eb..3107ff516e 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd
@@ -29,17 +29,17 @@
-- Testbench is selftesting.
library IEEE, common_lib, dp_lib, diag_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use rTwoSDF_lib.twiddlesPkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use rTwoSDF_lib.twiddlesPkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
entity tb_fft_r2_bf_par is
generic(
@@ -139,49 +139,49 @@ begin
end process;
u_block_generator : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => c_nof_streams,
- g_buf_dat_w => c_nof_complex * c_in_dat_w,
- g_buf_addr_w => c_bg_addr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
- g_file_name_prefix => c_bg_prefix
- )
- port map(
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
- en_sync => '1',
- ram_bg_data_mosi => ram_bg_data_mosi,
- ram_bg_data_miso => open,
- reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
- reg_bg_ctrl_miso => open,
- out_siso_arr => in_siso_arr,
- out_sosi_arr => in_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_nof_streams,
+ g_buf_dat_w => c_nof_complex * c_in_dat_w,
+ g_buf_addr_w => c_bg_addr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_file_name_prefix => c_bg_prefix
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+ en_sync => '1',
+ ram_bg_data_mosi => ram_bg_data_mosi,
+ ram_bg_data_miso => open,
+ reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
+ reg_bg_ctrl_miso => open,
+ out_siso_arr => in_siso_arr,
+ out_sosi_arr => in_sosi_arr
+ );
in_siso_arr(0) <= c_dp_siso_rdy;
in_siso_arr(1) <= c_dp_siso_rdy;
-- device under test
u_dut : entity work.fft_r2_bf_par
- generic map (
- g_stage => g_stage,
- g_element => g_element
- )
- port map (
- clk => clk,
- rst => rst,
- x_in_re => in_sosi_arr(0).re(c_in_dat_w - 1 downto 0),
- x_in_im => in_sosi_arr(0).im(c_in_dat_w - 1 downto 0),
- y_in_re => in_sosi_arr(1).re(c_in_dat_w - 1 downto 0),
- y_in_im => in_sosi_arr(1).im(c_in_dat_w - 1 downto 0),
- in_val => in_sosi_arr(0).valid,
- x_out_re => x_out_re,
- x_out_im => x_out_im,
- y_out_re => y_out_re,
- y_out_im => y_out_im,
- out_val => out_val
- );
+ generic map (
+ g_stage => g_stage,
+ g_element => g_element
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ x_in_re => in_sosi_arr(0).re(c_in_dat_w - 1 downto 0),
+ x_in_im => in_sosi_arr(0).im(c_in_dat_w - 1 downto 0),
+ y_in_re => in_sosi_arr(1).re(c_in_dat_w - 1 downto 0),
+ y_in_im => in_sosi_arr(1).im(c_in_dat_w - 1 downto 0),
+ in_val => in_sosi_arr(0).valid,
+ x_out_re => x_out_re,
+ x_out_im => x_out_im,
+ y_out_re => y_out_re,
+ y_out_im => y_out_im,
+ out_val => out_val
+ );
-- verification
weight_re <= wRe(wMap(g_element, g_stage));
@@ -208,52 +208,52 @@ begin
end process;
u_verify_pipeline_x_re : entity common_lib.common_pipeline
- generic map (
- g_pipeline => (c_pipeline.bf_lat + c_pipeline.mul_lat),
- g_in_dat_w => ref_x_out_re'length,
- g_out_dat_w => ref_x_out_re'length
- )
- port map (
- clk => clk,
- in_dat => ref_x_out_re,
- out_dat => ref_x_out_re_dly
- );
+ generic map (
+ g_pipeline => (c_pipeline.bf_lat + c_pipeline.mul_lat),
+ g_in_dat_w => ref_x_out_re'length,
+ g_out_dat_w => ref_x_out_re'length
+ )
+ port map (
+ clk => clk,
+ in_dat => ref_x_out_re,
+ out_dat => ref_x_out_re_dly
+ );
u_verify_pipeline_x_im : entity common_lib.common_pipeline
- generic map (
- g_pipeline => (c_pipeline.bf_lat + c_pipeline.mul_lat),
- g_in_dat_w => ref_x_out_im'length,
- g_out_dat_w => ref_x_out_im'length
- )
- port map (
- clk => clk,
- in_dat => ref_x_out_im,
- out_dat => ref_x_out_im_dly
- );
+ generic map (
+ g_pipeline => (c_pipeline.bf_lat + c_pipeline.mul_lat),
+ g_in_dat_w => ref_x_out_im'length,
+ g_out_dat_w => ref_x_out_im'length
+ )
+ port map (
+ clk => clk,
+ in_dat => ref_x_out_im,
+ out_dat => ref_x_out_im_dly
+ );
u_verify_pipeline_y_re : entity common_lib.common_pipeline
- generic map (
- g_pipeline => (c_pipeline.bf_lat + c_pipeline.mul_lat),
- g_in_dat_w => ref_y_out_re'length,
- g_out_dat_w => ref_y_out_re'length
- )
- port map (
- clk => clk,
- in_dat => ref_y_out_re,
- out_dat => ref_y_out_re_dly
- );
+ generic map (
+ g_pipeline => (c_pipeline.bf_lat + c_pipeline.mul_lat),
+ g_in_dat_w => ref_y_out_re'length,
+ g_out_dat_w => ref_y_out_re'length
+ )
+ port map (
+ clk => clk,
+ in_dat => ref_y_out_re,
+ out_dat => ref_y_out_re_dly
+ );
u_verify_pipeline_y_im : entity common_lib.common_pipeline
- generic map (
- g_pipeline => (c_pipeline.bf_lat + c_pipeline.mul_lat),
- g_in_dat_w => ref_y_out_im'length,
- g_out_dat_w => ref_y_out_im'length
- )
- port map (
- clk => clk,
- in_dat => ref_y_out_im,
- out_dat => ref_y_out_im_dly
- );
+ generic map (
+ g_pipeline => (c_pipeline.bf_lat + c_pipeline.mul_lat),
+ g_in_dat_w => ref_y_out_im'length,
+ g_out_dat_w => ref_y_out_im'length
+ )
+ port map (
+ clk => clk,
+ in_dat => ref_y_out_im,
+ out_dat => ref_y_out_im_dly
+ );
------------------------------------------------------------------------
-- Simples process that does the final test.
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd
index b1a979ee6a..56d5bd7028 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd
@@ -56,18 +56,18 @@
-- able to disable the dut_clk during verification to significantly speed
-- up the simulation.
library ieee, common_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_textio.all;
-use std.textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.fft_pkg.all;
-use work.tb_fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.std_logic_textio.all;
+ use std.textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.fft_pkg.all;
+ use work.tb_fft_pkg.all;
entity tb_fft_r2_par is
generic(
@@ -130,7 +130,7 @@ architecture tb of tb_fft_r2_par is
constant c_rnd_factor : natural := sel_a_b(g_enable_in_val_gaps, 3, 1);
constant c_dut_block_latency : natural := 3;
constant c_dut_clk_latency : natural := g_fft.nof_points * c_dut_block_latency * c_rnd_factor; -- worst case
- -- need to account for g_fft.nof_points, because tb verifies on serialized output
+ -- need to account for g_fft.nof_points, because tb verifies on serialized output
-- input/output data width
constant c_in_dat_w : natural := g_fft.in_dat_w;
@@ -301,19 +301,19 @@ begin
-- DUT = Device Under Test
---------------------------------------------------------------
u_dut : entity work.fft_r2_par
- generic map(
- g_fft => g_fft
- )
- port map(
- clk => dut_clk,
- rst => rst,
- in_re_arr => in_re_arr,
- in_im_arr => in_im_arr,
- in_val => in_val,
- out_re_arr => out_re_arr,
- out_im_arr => out_im_arr,
- out_val => out_val
- );
+ generic map(
+ g_fft => g_fft
+ )
+ port map(
+ clk => dut_clk,
+ rst => rst,
+ in_re_arr => in_re_arr,
+ in_im_arr => in_im_arr,
+ in_val => in_val,
+ out_re_arr => out_re_arr,
+ out_im_arr => out_im_arr,
+ out_val => out_val
+ );
-- Block count
in_val_cnt <= in_val_cnt + 1 when rising_edge(dut_clk) and in_val = '1' else in_val_cnt;
@@ -407,7 +407,7 @@ begin
out_cnt <= out_cnt + 1 when rising_edge(tb_clk) and out_val_c = '1' else out_cnt;
proc_fft_out_control(1, g_fft.nof_points, c_nof_channels, g_fft.use_reorder, g_fft.use_fft_shift, g_fft.use_separate,
- out_cnt, out_val_c, out_val_a, out_val_b, out_channel, out_bin, out_bin_cnt);
+ out_cnt, out_val_c, out_val_a, out_val_b, out_channel, out_bin, out_bin_cnt);
---------------------------------------------------------------
-- VERIFY OUTPUT
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
index 93d3ba3dd3..faec75305b 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
@@ -83,18 +83,18 @@
-- signals in the Wave window
--
library ieee, common_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_textio.all;
-use std.textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.fft_pkg.all;
-use work.tb_fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.std_logic_textio.all;
+ use std.textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.fft_pkg.all;
+ use work.tb_fft_pkg.all;
entity tb_fft_r2_pipe is
generic(
@@ -324,26 +324,26 @@ begin
-- DUT = Device Under Test
---------------------------------------------------------------
u_dut : entity work.fft_r2_pipe
- generic map (
- g_fft => g_fft
- )
- port map (
- clk => clk,
- rst => rst,
- in_re => in_dat_a,
- in_im => in_dat_b,
- in_val => in_val,
- out_quant_re => out_re,
- out_quant_im => out_im,
- out_val => out_val
- );
+ generic map (
+ g_fft => g_fft
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_re => in_dat_a,
+ in_im => in_dat_b,
+ in_val => in_val,
+ out_quant_re => out_re,
+ out_quant_im => out_im,
+ out_val => out_val
+ );
-- Separate output
in_val_cnt <= in_val_cnt + 1 when rising_edge(clk) and in_val = '1' else in_val_cnt;
out_val_cnt <= out_val_cnt + 1 when rising_edge(clk) and out_val = '1' else out_val_cnt;
proc_fft_out_control(1, g_fft.nof_points, c_nof_channels, g_fft.use_reorder, g_fft.use_fft_shift, g_fft.use_separate,
- out_val_cnt, out_val, out_val_a, out_val_b, out_channel, out_bin, out_bin_cnt);
+ out_val_cnt, out_val, out_val_a, out_val_b, out_channel, out_bin, out_bin_cnt);
-- Block count t_blk for c_nof_channels>=1 channels per block
in_blk_val <= '1' when in_val = '1' and (in_val_cnt mod c_nof_channels) = 0 else '0';
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd
index 89835d3eeb..8c9aadce24 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd
@@ -43,18 +43,18 @@
-- signals in the Wave window
--
library ieee, common_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_textio.all;
-use std.textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.fft_pkg.all;
-use work.tb_fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.std_logic_textio.all;
+ use std.textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.fft_pkg.all;
+ use work.tb_fft_pkg.all;
entity tb_fft_r2_wide is
generic(
@@ -310,19 +310,19 @@ begin
-- DUT = Device Under Test
---------------------------------------------------------------
u_dut : entity work.fft_r2_wide
- generic map(
- g_fft => g_fft
- )
- port map(
- clk => clk,
- rst => rst,
- in_re_arr => in_re_arr,
- in_im_arr => in_im_arr,
- in_val => in_val,
- out_re_arr => out_re_arr,
- out_im_arr => out_im_arr,
- out_val => out_val
- );
+ generic map(
+ g_fft => g_fft
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+ in_re_arr => in_re_arr,
+ in_im_arr => in_im_arr,
+ in_val => in_val,
+ out_re_arr => out_re_arr,
+ out_im_arr => out_im_arr,
+ out_val => out_val
+ );
-- Data valid count
in_val_cnt <= in_val_cnt + 1 when rising_edge(clk) and in_val = '1' else in_val_cnt;
@@ -360,7 +360,7 @@ begin
out_cnt <= out_cnt + 1 when rising_edge(sclk) and out_val_c = '1' else out_cnt;
proc_fft_out_control(g_fft.wb_factor, g_fft.nof_points, c_nof_channels, g_fft.use_reorder, g_fft.use_fft_shift, g_fft.use_separate,
- out_cnt, out_val_c, out_val_a, out_val_b, out_channel, out_bin, out_bin_cnt);
+ out_cnt, out_val_c, out_val_a, out_val_b, out_channel, out_bin, out_bin_cnt);
-- clk diff to avoid combinatorial glitches when selecting the data with out_val_a,b,c
reg_out_val_a <= out_val_a when rising_edge(sclk);
@@ -449,86 +449,86 @@ begin
end process;
u_in_re_scope : entity common_lib.common_wideband_data_scope
- generic map (
- g_sim => true,
- g_wideband_factor => g_fft.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => false, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_in_dat_w -- Actual width of the data samples
- )
- port map (
- -- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
-
- -- Streaming input data
- in_data => in_re_data,
- in_val => in_val,
-
- -- Scope output samples
- out_dat => OPEN,
- out_int => in_re_scope,
- out_val => in_val_scope
- );
+ generic map (
+ g_sim => true,
+ g_wideband_factor => g_fft.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_big_endian => false, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_dat_w => c_in_dat_w -- Actual width of the data samples
+ )
+ port map (
+ -- Sample clock
+ SCLK => sclk, -- sample clk, use only for simulation purposes
+
+ -- Streaming input data
+ in_data => in_re_data,
+ in_val => in_val,
+
+ -- Scope output samples
+ out_dat => OPEN,
+ out_int => in_re_scope,
+ out_val => in_val_scope
+ );
u_in_im_scope : entity common_lib.common_wideband_data_scope
- generic map (
- g_sim => true,
- g_wideband_factor => g_fft.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => false, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_in_dat_w -- Actual width of the data samples
- )
- port map (
- -- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
-
- -- Streaming input data
- in_data => in_im_data,
- in_val => in_val,
-
- -- Scope output samples
- out_dat => OPEN,
- out_int => in_im_scope,
- out_val => open
- );
+ generic map (
+ g_sim => true,
+ g_wideband_factor => g_fft.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_big_endian => false, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_dat_w => c_in_dat_w -- Actual width of the data samples
+ )
+ port map (
+ -- Sample clock
+ SCLK => sclk, -- sample clk, use only for simulation purposes
+
+ -- Streaming input data
+ in_data => in_im_data,
+ in_val => in_val,
+
+ -- Scope output samples
+ out_dat => OPEN,
+ out_int => in_im_scope,
+ out_val => open
+ );
u_out_re_scope : entity common_lib.common_wideband_data_scope
- generic map (
- g_sim => true,
- g_wideband_factor => g_fft.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => false, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_out_dat_w -- Actual width of the data samples
- )
- port map (
- -- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
-
- -- Streaming input data
- in_data => out_re_data,
- in_val => out_val,
-
- -- Scope output samples
- out_dat => OPEN,
- out_int => out_re_scope,
- out_val => out_val_c
- );
+ generic map (
+ g_sim => true,
+ g_wideband_factor => g_fft.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_big_endian => false, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_dat_w => c_out_dat_w -- Actual width of the data samples
+ )
+ port map (
+ -- Sample clock
+ SCLK => sclk, -- sample clk, use only for simulation purposes
+
+ -- Streaming input data
+ in_data => out_re_data,
+ in_val => out_val,
+
+ -- Scope output samples
+ out_dat => OPEN,
+ out_int => out_re_scope,
+ out_val => out_val_c
+ );
u_out_im_scope : entity common_lib.common_wideband_data_scope
- generic map (
- g_sim => true,
- g_wideband_factor => g_fft.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => false, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_out_dat_w -- Actual width of the data samples
- )
- port map (
- -- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
-
- -- Streaming input data
- in_data => out_im_data,
- in_val => out_val,
-
- -- Scope output samples
- out_dat => OPEN,
- out_int => out_im_scope,
- out_val => open
- );
+ generic map (
+ g_sim => true,
+ g_wideband_factor => g_fft.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_big_endian => false, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_dat_w => c_out_dat_w -- Actual width of the data samples
+ )
+ port map (
+ -- Sample clock
+ SCLK => sclk, -- sample clk, use only for simulation purposes
+
+ -- Streaming input data
+ in_data => out_im_data,
+ in_val => out_val,
+
+ -- Scope output samples
+ out_dat => OPEN,
+ out_int => out_im_scope,
+ out_val => open
+ );
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
index 7720437603..4a2483d7e5 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
@@ -30,15 +30,15 @@
-- Run testbench for different values of c_seperate and c_reorder. (Recompile is required)
library IEEE, common_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
entity tb_fft_reorder_sepa_pipe is
end tb_fft_reorder_sepa_pipe;
@@ -121,44 +121,44 @@ begin
end process;
u_block_generator : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => 1,
- g_buf_dat_w => c_nof_complex * c_in_dat_w,
- g_buf_addr_w => c_bg_addr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
- g_file_name_prefix => c_bg_prefix
- )
- port map(
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
- en_sync => '1',
- ram_bg_data_mosi => ram_bg_data_mosi,
- ram_bg_data_miso => open,
- reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
- reg_bg_ctrl_miso => open,
- out_siso_arr => in_siso_arr,
- out_sosi_arr => in_sosi_arr
- );
+ generic map(
+ g_nof_streams => 1,
+ g_buf_dat_w => c_nof_complex * c_in_dat_w,
+ g_buf_addr_w => c_bg_addr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_file_name_prefix => c_bg_prefix
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+ en_sync => '1',
+ ram_bg_data_mosi => ram_bg_data_mosi,
+ ram_bg_data_miso => open,
+ reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
+ reg_bg_ctrl_miso => open,
+ out_siso_arr => in_siso_arr,
+ out_sosi_arr => in_sosi_arr
+ );
in_siso_arr(0) <= c_dp_siso_rdy;
-- device under test
u_dut : entity work.fft_reorder_sepa_pipe
- generic map (
- g_separate => c_separate,
- g_nof_points => c_nof_points,
- g_bit_flip => c_reorder,
- g_nof_chan => c_nof_chan
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => in_dat,
- in_val => in_sosi_arr(0).valid,
- out_dat => out_dat,
- out_val => out_val
- );
+ generic map (
+ g_separate => c_separate,
+ g_nof_points => c_nof_points,
+ g_bit_flip => c_reorder,
+ g_nof_chan => c_nof_chan
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => in_dat,
+ in_val => in_sosi_arr(0).valid,
+ out_dat => out_dat,
+ out_val => out_val
+ );
in_dat <= in_sosi_arr(0).im(c_in_dat_w - 1 downto 0) & in_sosi_arr(0).re(c_in_dat_w - 1 downto 0);
out_dat_re <= out_dat(c_in_dat_w - 1 downto 0);
@@ -185,48 +185,48 @@ begin
proc_common_wait_some_cycles(clk, 1);
-- Perform re-order function to the reference data if re-ordering is enabled
if(c_reorder = true) then
- for H in 0 to c_nof_channels - 1 loop
- for J in 0 to c_nof_points - 1 loop
- v_buf_input_re_temp(c_nof_channels * J + H) := buf_input_re(TO_UINT(TO_UVEC(H, c_nof_chan) & FLIP(TO_UVEC(J, ceil_log2(c_nof_points)))));
- v_buf_input_im_temp(c_nof_channels * J + H) := buf_input_im(TO_UINT(TO_UVEC(H, c_nof_chan) & FLIP(TO_UVEC(J, ceil_log2(c_nof_points)))));
- end loop;
+ for H in 0 to c_nof_channels - 1 loop
+ for J in 0 to c_nof_points - 1 loop
+ v_buf_input_re_temp(c_nof_channels * J + H) := buf_input_re(TO_UINT(TO_UVEC(H, c_nof_chan) & FLIP(TO_UVEC(J, ceil_log2(c_nof_points)))));
+ v_buf_input_im_temp(c_nof_channels * J + H) := buf_input_im(TO_UINT(TO_UVEC(H, c_nof_chan) & FLIP(TO_UVEC(J, ceil_log2(c_nof_points)))));
end loop;
+ end loop;
else
- for H in 0 to c_nof_channels - 1 loop
- for J in 0 to c_nof_points - 1 loop
- v_buf_input_re_temp(H * c_nof_points + J) := buf_input_re(c_nof_channels * J + H);
- v_buf_input_im_temp(H * c_nof_points + J) := buf_input_im(c_nof_channels * J + H);
- end loop;
+ for H in 0 to c_nof_channels - 1 loop
+ for J in 0 to c_nof_points - 1 loop
+ v_buf_input_re_temp(H * c_nof_points + J) := buf_input_re(c_nof_channels * J + H);
+ v_buf_input_im_temp(H * c_nof_points + J) := buf_input_im(c_nof_channels * J + H);
end loop;
+ end loop;
end if;
-- Do the separate function on the reference data if separata is enabled.
if(c_separate = true) then
- for H in 0 to c_nof_channels - 1 loop
- for J in 0 to c_nof_points / 2 - 1 loop
- if(J = 0) then
- v_buf_output_a_re(H * c_nof_points / 2 + J) := v_buf_input_re_temp(H * c_nof_points);
- v_buf_output_a_im(H * c_nof_points / 2 + J) := (others => '0');
- v_buf_output_b_re(H * c_nof_points / 2 + J) := v_buf_input_im_temp(H * c_nof_points);
- v_buf_output_b_im(H * c_nof_points / 2 + J) := (others => '0');
- buf_output_re(H * c_nof_points) <= v_buf_output_a_re(H * c_nof_points / 2 + J);
- buf_output_im(H * c_nof_points) <= v_buf_output_a_im(H * c_nof_points / 2 + J);
- buf_output_re(H * c_nof_points + 1) <= v_buf_output_b_re(H * c_nof_points / 2 + J);
- buf_output_im(H * c_nof_points + 1) <= v_buf_output_b_im(H * c_nof_points / 2 + J);
- else
- v_buf_output_a_re(H * c_nof_points / 2 + J) := ADD_SVEC(v_buf_input_re_temp(H * c_nof_points + c_nof_points - J), v_buf_input_re_temp(H * c_nof_points + J), c_in_dat_w + 1)(c_in_dat_w downto 1);
- v_buf_output_a_im(H * c_nof_points / 2 + J) := SUB_SVEC(v_buf_input_im_temp(H * c_nof_points + J), v_buf_input_im_temp(H * c_nof_points + c_nof_points - J), c_in_dat_w + 1)(c_in_dat_w downto 1);
- v_buf_output_b_re(H * c_nof_points / 2 + J) := ADD_SVEC(v_buf_input_im_temp(H * c_nof_points + c_nof_points - J), v_buf_input_im_temp(H * c_nof_points + J), c_in_dat_w + 1)(c_in_dat_w downto 1);
- v_buf_output_b_im(H * c_nof_points / 2 + J) := SUB_SVEC(v_buf_input_re_temp(H * c_nof_points + c_nof_points - J), v_buf_input_re_temp(H * c_nof_points + J), c_in_dat_w + 1)(c_in_dat_w downto 1);
- buf_output_re(H * c_nof_points + 2 * J) <= v_buf_output_a_re(H * c_nof_points / 2 + J);
- buf_output_im(H * c_nof_points + 2 * J) <= v_buf_output_a_im(H * c_nof_points / 2 + J);
- buf_output_re(H * c_nof_points + 2 * J + 1) <= v_buf_output_b_re(H * c_nof_points / 2 + J);
- buf_output_im(H * c_nof_points + 2 * J + 1) <= v_buf_output_b_im(H * c_nof_points / 2 + J);
- end if;
- end loop;
+ for H in 0 to c_nof_channels - 1 loop
+ for J in 0 to c_nof_points / 2 - 1 loop
+ if(J = 0) then
+ v_buf_output_a_re(H * c_nof_points / 2 + J) := v_buf_input_re_temp(H * c_nof_points);
+ v_buf_output_a_im(H * c_nof_points / 2 + J) := (others => '0');
+ v_buf_output_b_re(H * c_nof_points / 2 + J) := v_buf_input_im_temp(H * c_nof_points);
+ v_buf_output_b_im(H * c_nof_points / 2 + J) := (others => '0');
+ buf_output_re(H * c_nof_points) <= v_buf_output_a_re(H * c_nof_points / 2 + J);
+ buf_output_im(H * c_nof_points) <= v_buf_output_a_im(H * c_nof_points / 2 + J);
+ buf_output_re(H * c_nof_points + 1) <= v_buf_output_b_re(H * c_nof_points / 2 + J);
+ buf_output_im(H * c_nof_points + 1) <= v_buf_output_b_im(H * c_nof_points / 2 + J);
+ else
+ v_buf_output_a_re(H * c_nof_points / 2 + J) := ADD_SVEC(v_buf_input_re_temp(H * c_nof_points + c_nof_points - J), v_buf_input_re_temp(H * c_nof_points + J), c_in_dat_w + 1)(c_in_dat_w downto 1);
+ v_buf_output_a_im(H * c_nof_points / 2 + J) := SUB_SVEC(v_buf_input_im_temp(H * c_nof_points + J), v_buf_input_im_temp(H * c_nof_points + c_nof_points - J), c_in_dat_w + 1)(c_in_dat_w downto 1);
+ v_buf_output_b_re(H * c_nof_points / 2 + J) := ADD_SVEC(v_buf_input_im_temp(H * c_nof_points + c_nof_points - J), v_buf_input_im_temp(H * c_nof_points + J), c_in_dat_w + 1)(c_in_dat_w downto 1);
+ v_buf_output_b_im(H * c_nof_points / 2 + J) := SUB_SVEC(v_buf_input_re_temp(H * c_nof_points + c_nof_points - J), v_buf_input_re_temp(H * c_nof_points + J), c_in_dat_w + 1)(c_in_dat_w downto 1);
+ buf_output_re(H * c_nof_points + 2 * J) <= v_buf_output_a_re(H * c_nof_points / 2 + J);
+ buf_output_im(H * c_nof_points + 2 * J) <= v_buf_output_a_im(H * c_nof_points / 2 + J);
+ buf_output_re(H * c_nof_points + 2 * J + 1) <= v_buf_output_b_re(H * c_nof_points / 2 + J);
+ buf_output_im(H * c_nof_points + 2 * J + 1) <= v_buf_output_b_im(H * c_nof_points / 2 + J);
+ end if;
end loop;
+ end loop;
else
- buf_output_re <= v_buf_input_re_temp;
- buf_output_im <= v_buf_input_im_temp;
+ buf_output_re <= v_buf_input_re_temp;
+ buf_output_im <= v_buf_input_im_temp;
end if;
wait;
end process;
@@ -242,13 +242,13 @@ begin
assert buf_output_re(I) = out_dat_re report "Error: wrong RTL result in real path" severity error;
assert buf_output_im(I) = out_dat_im report "Error: wrong RTL result in imag path" severity error;
if(I = c_nof_channels * c_nof_points - 1 ) then
- I := 0;
- else
- I := I + 1;
- end if;
+ I := 0;
+ else
+ I := I + 1;
end if;
+ end if;
else
- I := 0;
+ I := 0;
end if;
end process p_tester;
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
index a38cdfba65..7113d7fc60 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
@@ -30,14 +30,14 @@
-- First frame contains always some errors.
library IEEE, common_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
entity tb_fft_sepa is
end tb_fft_sepa;
@@ -118,38 +118,38 @@ begin
end process;
u_block_generator : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => 1,
- g_buf_dat_w => c_nof_complex * c_in_dat_w,
- g_buf_addr_w => c_bg_addr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
- g_file_name_prefix => c_bg_prefix
- )
- port map(
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
- en_sync => '1',
- ram_bg_data_mosi => ram_bg_data_mosi,
- ram_bg_data_miso => open,
- reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
- reg_bg_ctrl_miso => open,
- out_siso_arr => in_siso_arr,
- out_sosi_arr => in_sosi_arr
- );
+ generic map(
+ g_nof_streams => 1,
+ g_buf_dat_w => c_nof_complex * c_in_dat_w,
+ g_buf_addr_w => c_bg_addr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_file_name_prefix => c_bg_prefix
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+ en_sync => '1',
+ ram_bg_data_mosi => ram_bg_data_mosi,
+ ram_bg_data_miso => open,
+ reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
+ reg_bg_ctrl_miso => open,
+ out_siso_arr => in_siso_arr,
+ out_sosi_arr => in_sosi_arr
+ );
in_siso_arr(0) <= c_dp_siso_rdy;
-- device under test
u_dut : entity work.fft_sepa
- port map (
- clk => clk,
- rst => rst,
- in_dat => in_dat,
- in_val => in_sosi_arr(0).valid,
- out_dat => out_dat,
- out_val => out_val
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => in_dat,
+ in_val => in_sosi_arr(0).valid,
+ out_dat => out_dat,
+ out_val => out_val
+ );
in_dat <= in_sosi_arr(0).im(c_in_dat_w - 1 downto 0) & in_sosi_arr(0).re(c_in_dat_w - 1 downto 0);
out_dat_re <= out_dat(c_in_dat_w - 1 downto 0);
@@ -198,13 +198,13 @@ begin
assert buf_output_re(I) = out_dat_re report "Error: wrong RTL result in real path" severity ERROR;
assert buf_output_im(I) = out_dat_im report "Error: wrong RTL result in imag path" severity ERROR;
if(I = c_nof_points - 1 ) then
- I := 0;
- else
- I := I + 1;
- end if;
+ I := 0;
+ else
+ I := I + 1;
end if;
+ end if;
else
- I := 0;
+ I := 0;
end if;
end process p_tester;
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
index 26a50b4369..f9ef6c2f40 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
@@ -49,10 +49,10 @@
-- # view a,b and re,im signals in radix decimal
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.fft_pkg.all;
entity tb_fft_switch is
generic (
@@ -158,20 +158,20 @@ begin
-- Create in strobes for debugging
u_in_strobes : entity common_lib.common_create_strobes_from_valid
- generic map (
- g_pipeline => false,
- g_nof_clk_per_sync => g_nof_clk_per_sync,
- g_nof_clk_per_block => c_nof_clk_per_block
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- out_val => OPEN, -- out_val = in_val, because g_pipeline = FALSE
- out_sop => in_sop,
- out_eop => in_eop,
- out_sync => in_sync
- );
+ generic map (
+ g_pipeline => false,
+ g_nof_clk_per_sync => g_nof_clk_per_sync,
+ g_nof_clk_per_block => c_nof_clk_per_block
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ out_val => OPEN, -- out_val = in_val, because g_pipeline = FALSE
+ out_sop => in_sop,
+ out_eop => in_eop,
+ out_sync => in_sync
+ );
gen_increment_at_val : if g_increment_at_val = true generate
in_a <= INCR_SVEC(in_a, 1) when rising_edge(clk) and in_val = '1';
@@ -184,23 +184,23 @@ begin
end generate;
u_fft_switch : entity work.fft_switch
- generic map (
- g_switch_en => g_switch_en,
- g_seed1 => c_switch_seed1,
- g_seed2 => c_switch_seed2,
- g_fft_sz_w => g_fft_size_w,
- g_dat_w => c_dat_w
- )
- port map (
- in_re => in_a,
- in_im => in_b,
- in_val => in_val,
- out_re => switch_a,
- out_im => switch_b,
- out_val => switch_val,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_switch_en => g_switch_en,
+ g_seed1 => c_switch_seed1,
+ g_seed2 => c_switch_seed2,
+ g_fft_sz_w => g_fft_size_w,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ in_re => in_a,
+ in_im => in_b,
+ in_val => in_val,
+ out_re => switch_a,
+ out_im => switch_b,
+ out_val => switch_val,
+ clk => clk,
+ rst => rst
+ );
-- Model A, B multiplexing part of FFT
-- 0 1 2 .. N-1
@@ -227,23 +227,23 @@ begin
mux_val <= switch_val when rising_edge(clk);
u_fft_unswitch : entity work.fft_unswitch
- generic map (
- g_switch_en => g_switch_en,
- g_seed1 => c_switch_seed1,
- g_seed2 => c_switch_seed2,
- g_fft_sz_w => g_fft_size_w,
- g_dat_w => c_dat_w
- )
- port map (
- in_re => mux_re,
- in_im => mux_im,
- in_val => mux_val,
- out_re => unswitch_re,
- out_im => unswitch_im,
- out_val => unswitch_val,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_switch_en => g_switch_en,
+ g_seed1 => c_switch_seed1,
+ g_seed2 => c_switch_seed2,
+ g_fft_sz_w => g_fft_size_w,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ in_re => mux_re,
+ in_im => mux_im,
+ in_val => mux_val,
+ out_re => unswitch_re,
+ out_im => unswitch_im,
+ out_val => unswitch_val,
+ clk => clk,
+ rst => rst
+ );
-- Demultiplex output to ease verification
-- 0 1 2 3 .. N-2 N-1
@@ -271,20 +271,20 @@ begin
-- Create out strobes for debugging
u_out_strobes : entity common_lib.common_create_strobes_from_valid
- generic map (
- g_pipeline => false,
- g_nof_clk_per_sync => g_nof_clk_per_sync,
- g_nof_clk_per_block => c_nof_clk_per_block
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => out_val,
- out_val => OPEN, -- out_val = in_val, because g_pipeline = FALSE
- out_sop => out_sop,
- out_eop => out_eop,
- out_sync => out_sync
- );
+ generic map (
+ g_pipeline => false,
+ g_nof_clk_per_sync => g_nof_clk_per_sync,
+ g_nof_clk_per_block => c_nof_clk_per_block
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => out_val,
+ out_val => OPEN, -- out_val = in_val, because g_pipeline = FALSE
+ out_sop => out_sop,
+ out_eop => out_eop,
+ out_sync => out_sync
+ );
-- Account for pipeling in fft_switch, mux, fft_unswitch and demux
dly_val(0) <= in_val;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
index c021f0cdfb..c24c90b35c 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
@@ -30,20 +30,20 @@
--
library ieee, common_lib, dp_lib, diag_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_textio.all;
-use STD.textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use rTwoSDF_lib.twiddlesPkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.tb_fft_pkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.std_logic_textio.all;
+ use STD.textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use rTwoSDF_lib.twiddlesPkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.tb_fft_pkg.all;
+ use work.fft_pkg.all;
entity tb_fft_wide_unit is
generic(
@@ -99,7 +99,7 @@ architecture tb of tb_fft_wide_unit is
constant c_normal : boolean := true;
- -- input from uniform noise file created automatically by MATLAB testFFT_input.m
+ -- input from uniform noise file created automatically by MATLAB testFFT_input.m
constant c_noiseInputFile : string := "data/test/in/uniNoise_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(c_twiddle_w) & "_in.txt";
constant c_noiseGoldenFile : string := "data/test/out/uniNoise_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(c_twiddle_w) & "_tb" & natural'image(wTyp'length) & "_out.txt";
constant c_noiseOutputFile : string := "data/test/out/uniNoise_out.txt";
@@ -136,17 +136,20 @@ architecture tb of tb_fft_wide_unit is
constant c_preSelSinusGoldenFile : string := sel_a_b(g_use_2xreal_inputs, c_2xrealSinusGoldenFile, c_sinusGoldenFile);
constant c_preSelSinNoiseGoldenFile : string := sel_a_b(g_use_2xreal_inputs, c_2xrealSinNoiseGoldenFile, c_sinNoiseGoldenFile);
- constant c_inputFile : string := sel_a_b(g_use_uniNoise_file, c_noiseInputFile,
- sel_a_b(g_use_sinus_file, c_sinusInputFile,
- sel_a_b(g_use_sinNoise_file, c_sinNoiseInputFile, c_preSelImpulseInputFile)));
+ constant c_inputFile : string := sel_a_b(
+ g_use_uniNoise_file, c_noiseInputFile,
+ sel_a_b(g_use_sinus_file, c_sinusInputFile,
+ sel_a_b(g_use_sinNoise_file, c_sinNoiseInputFile, c_preSelImpulseInputFile)));
- constant c_goldenFile : string := sel_a_b(g_use_uniNoise_file, c_preSelNoiseGoldenFile,
- sel_a_b(g_use_sinus_file, c_preSelSinusGoldenFile,
- sel_a_b(g_use_sinNoise_file, c_preSelSinNoiseGoldenFile, c_preSelImpulseGoldenFile)));
+ constant c_goldenFile : string := sel_a_b(
+ g_use_uniNoise_file, c_preSelNoiseGoldenFile,
+ sel_a_b(g_use_sinus_file, c_preSelSinusGoldenFile,
+ sel_a_b(g_use_sinNoise_file, c_preSelSinNoiseGoldenFile, c_preSelImpulseGoldenFile)));
- constant c_outputFile : string := sel_a_b(g_use_uniNoise_file, c_noiseOutputFile,
- sel_a_b(g_use_sinus_file, c_sinusOutputFile,
- sel_a_b(g_use_sinNoise_file, c_sinNoiseOutputFile, c_preSelImpulseOutputFile)));
+ constant c_outputFile : string := sel_a_b(
+ g_use_uniNoise_file, c_noiseOutputFile,
+ sel_a_b(g_use_sinus_file, c_sinusOutputFile,
+ sel_a_b(g_use_sinNoise_file, c_sinNoiseOutputFile, c_preSelImpulseOutputFile)));
-- signal definitions
signal tb_end : std_logic := '0';
@@ -271,26 +274,26 @@ begin
---------------------------------------------------------------
gen_block_gen : for I in 0 to g_fft.wb_factor - 1 generate
u_block_generator : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => 1,
- g_buf_dat_w => c_nof_complex * g_fft.in_dat_w,
- g_buf_addr_w => c_bg_addr_w,
- g_file_name_prefix => c_bg_prefix
- )
- port map(
- -- Clocks and Reset
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
- en_sync => '1',
- ram_bg_data_mosi => ram_bg_data_mosi_arr(I),
- ram_bg_data_miso => open,
- reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
- reg_bg_ctrl_miso => open,
- out_siso_arr => in_siso_matrix(I),
- out_sosi_arr => in_sosi_matrix(I)
- );
+ generic map(
+ g_nof_streams => 1,
+ g_buf_dat_w => c_nof_complex * g_fft.in_dat_w,
+ g_buf_addr_w => c_bg_addr_w,
+ g_file_name_prefix => c_bg_prefix
+ )
+ port map(
+ -- Clocks and Reset
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+ en_sync => '1',
+ ram_bg_data_mosi => ram_bg_data_mosi_arr(I),
+ ram_bg_data_miso => open,
+ reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
+ reg_bg_ctrl_miso => open,
+ out_siso_arr => in_siso_matrix(I),
+ out_sosi_arr => in_sosi_matrix(I)
+ );
in_sosi_arr(I) <= in_sosi_matrix(I)(0);
in_siso_matrix(I)(0) <= c_dp_siso_rdy;
end generate;
@@ -311,13 +314,13 @@ begin
end loop;
while(true) loop
- wait until result_sosi_arr(0).sync = '1';
- proc_common_wait_some_cycles(clk, c_nof_samples_in_packet + 10);
+ wait until result_sosi_arr(0).sync = '1';
+ proc_common_wait_some_cycles(clk, c_nof_samples_in_packet + 10);
- for I in 0 to g_fft.wb_factor - 1 loop
- proc_fft_read_subband_statistics_memory(I, g_fft, clk, ram_sst_mosi, ram_sst_miso, result_sst_arr_temp);
- result_sst_arr((I + 1) * c_nof_samples_in_packet - 1 downto I * c_nof_samples_in_packet) <= result_sst_arr_temp; -- can not use result_bst_arr2(I) directly as argument in proc_bf_read_beamlet_statistics_memory()
- end loop;
+ for I in 0 to g_fft.wb_factor - 1 loop
+ proc_fft_read_subband_statistics_memory(I, g_fft, clk, ram_sst_mosi, ram_sst_miso, result_sst_arr_temp);
+ result_sst_arr((I + 1) * c_nof_samples_in_packet - 1 downto I * c_nof_samples_in_packet) <= result_sst_arr_temp; -- can not use result_bst_arr2(I) directly as argument in proc_bf_read_beamlet_statistics_memory()
+ end loop;
end loop;
end process;
@@ -325,19 +328,19 @@ begin
-- DUT = Device Under Test
---------------------------------------------------------------
u_dut : entity work.fft_wide_unit
- generic map (
- g_fft => g_fft
- )
- port map (
- dp_rst => rst,
- dp_clk => clk,
- mm_rst => rst,
- mm_clk => clk,
- ram_st_sst_mosi => ram_sst_mosi,
- ram_st_sst_miso => ram_sst_miso,
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => result_sosi_arr
- );
+ generic map (
+ g_fft => g_fft
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => clk,
+ mm_rst => rst,
+ mm_clk => clk,
+ ram_st_sst_mosi => ram_sst_mosi,
+ ram_st_sst_miso => ram_sst_miso,
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => result_sosi_arr
+ );
---------------------------------------------------------------
-- REARRANGE THE OUTPUT-DATA FOR VERIFICATION
---------------------------------------------------------------
@@ -373,48 +376,48 @@ begin
begin
wait until rising_edge(clk);
if(out_val = '1') then
- if(v_spectrum_index = v_nof_outs - 1) then
- v_spectrum_index := 0;
- v_bin_index := v_bin_index + g_fft.nof_points - v_nof_outs;
- else
- v_spectrum_index := v_spectrum_index + 1;
- end if;
- v_bin_index := v_bin_index + 1;
+ if(v_spectrum_index = v_nof_outs - 1) then
+ v_spectrum_index := 0;
+ v_bin_index := v_bin_index + g_fft.nof_points - v_nof_outs;
+ else
+ v_spectrum_index := v_spectrum_index + 1;
+ end if;
+ v_bin_index := v_bin_index + 1;
- if(v_list_index = c_file_len / g_fft.wb_factor - 1) then
- v_bin_index := 0;
- v_list_index := 0;
- else
- v_list_index := v_list_index + 1;
- end if;
+ if(v_list_index = c_file_len / g_fft.wb_factor - 1) then
+ v_bin_index := 0;
+ v_list_index := 0;
+ else
+ v_list_index := v_list_index + 1;
+ end if;
- for I in 0 to g_fft.wb_factor - 1 loop
- -- Calculate the auto correlation power:
- v_sum_re := RESIZE_SVEC(TO_SVEC(gold_re_arr(I), c_word_w), v_sum_re'length);
- v_sum_im := RESIZE_SVEC(TO_SVEC(gold_im_arr(I), c_word_w), v_sum_im'length);
- v_sum_pwr(32 downto 0) := func_complex_multiply(v_sum_re, v_sum_im, v_sum_re, v_sum_im, c_normal, "RE", 33);
- v_acc_pwr_arr(I * v_nof_outs + v_subband_cnt) := ADD_UVEC(v_acc_pwr_arr(I * v_nof_outs + v_subband_cnt), v_sum_pwr);
- end loop;
+ for I in 0 to g_fft.wb_factor - 1 loop
+ -- Calculate the auto correlation power:
+ v_sum_re := RESIZE_SVEC(TO_SVEC(gold_re_arr(I), c_word_w), v_sum_re'length);
+ v_sum_im := RESIZE_SVEC(TO_SVEC(gold_im_arr(I), c_word_w), v_sum_im'length);
+ v_sum_pwr(32 downto 0) := func_complex_multiply(v_sum_re, v_sum_im, v_sum_re, v_sum_im, c_normal, "RE", 33);
+ v_acc_pwr_arr(I * v_nof_outs + v_subband_cnt) := ADD_UVEC(v_acc_pwr_arr(I * v_nof_outs + v_subband_cnt), v_sum_pwr);
+ end loop;
- if(v_subband_cnt = v_nof_outs - 1) then
- v_subband_cnt := 0;
- else
- v_subband_cnt := v_subband_cnt + 1;
- end if;
+ if(v_subband_cnt = v_nof_outs - 1) then
+ v_subband_cnt := 0;
+ else
+ v_subband_cnt := v_subband_cnt + 1;
+ end if;
- ------------------------------------------------------------------------
- -- Latch the expected accumulated statistics to the output at the sync
- ------------------------------------------------------------------------
- if(v_int_time = c_nof_accum_per_sync * v_nof_outs - 1) then
- v_int_time := 0;
- -- Output the expected BST array
- expected_sst_arr <= v_acc_pwr_arr;
- v_acc_pwr_arr := (others => (others => '0'));
- assert expected_sst_arr = result_sst_arr report "Output statistics error" severity error;
- assert expected_sst_arr /= result_sst_arr report "Output statistics OK!!!!" severity note;
- else
- v_int_time := v_int_time + 1;
- end if;
+ ------------------------------------------------------------------------
+ -- Latch the expected accumulated statistics to the output at the sync
+ ------------------------------------------------------------------------
+ if(v_int_time = c_nof_accum_per_sync * v_nof_outs - 1) then
+ v_int_time := 0;
+ -- Output the expected BST array
+ expected_sst_arr <= v_acc_pwr_arr;
+ v_acc_pwr_arr := (others => (others => '0'));
+ assert expected_sst_arr = result_sst_arr report "Output statistics error" severity error;
+ assert expected_sst_arr /= result_sst_arr report "Output statistics OK!!!!" severity note;
+ else
+ v_int_time := v_int_time + 1;
+ end if;
end if;
for I in 0 to g_fft.wb_factor - 1 loop
diff --git a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2.vhd b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2.vhd
index 3551d70065..6bee107f68 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2.vhd
@@ -44,19 +44,19 @@
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
library IEEE, common_lib, mm_lib, diag_lib, dp_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.fft_pkg.all;
entity tb_mmf_fft_r2 is
generic(
@@ -74,23 +74,23 @@ end tb_mmf_fft_r2;
architecture tb of tb_mmf_fft_r2 is
constant c_fft : t_fft := (true, false, g_use_separate, g_nof_chan, g_wb_factor, 0, g_nof_points, g_in_dat_w, g_out_dat_w, 0, c_dsp_mult_w, 2, true, 56, 2);
- -- type t_rtwo_fft is record
- -- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
- -- use_fft_shift : boolean; -- = false for [0, pos, neg] bin frequencies order, true for [neg, 0, pos] bin frequencies order in case of complex input
- -- use_separate : boolean; -- = false for complex input, true for two real inputs
- -- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
- -- wb_factor : natural; -- = default 1, wideband factor
- -- twiddle_offset : natural; -- = default 0, twiddle offset for PFT sections in a wideband FFT
- -- nof_points : natural; -- = 1024, N point FFT
- -- in_dat_w : natural; -- = 8, number of input bits
- -- out_dat_w : natural; -- = 13, number of output bits: in_dat_w + natural((ceil_log2(nof_points))/2 + 2)
- -- out_gain_w : natural; -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
- -- stage_dat_w : natural; -- = 18, data width used between the stages(= DSP multiplier-width)
- -- guard_w : natural; -- = 2, Guard used to avoid overflow in FFT stage.
- -- guard_enable : boolean; -- = true when input needs guarding, false when input requires no guarding but scaling must be skipped at the last stage(s) (used in wb fft)
- -- stat_data_w : positive; -- = 56
- -- stat_data_sz : positive; -- = 2
- -- end record;
+ -- type t_rtwo_fft is record
+ -- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
+ -- use_fft_shift : boolean; -- = false for [0, pos, neg] bin frequencies order, true for [neg, 0, pos] bin frequencies order in case of complex input
+ -- use_separate : boolean; -- = false for complex input, true for two real inputs
+ -- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
+ -- wb_factor : natural; -- = default 1, wideband factor
+ -- twiddle_offset : natural; -- = default 0, twiddle offset for PFT sections in a wideband FFT
+ -- nof_points : natural; -- = 1024, N point FFT
+ -- in_dat_w : natural; -- = 8, number of input bits
+ -- out_dat_w : natural; -- = 13, number of output bits: in_dat_w + natural((ceil_log2(nof_points))/2 + 2)
+ -- out_gain_w : natural; -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
+ -- stage_dat_w : natural; -- = 18, data width used between the stages(= DSP multiplier-width)
+ -- guard_w : natural; -- = 2, Guard used to avoid overflow in FFT stage.
+ -- guard_enable : boolean; -- = true when input needs guarding, false when input requires no guarding but scaling must be skipped at the last stage(s) (used in wb fft)
+ -- stat_data_w : positive; -- = 56
+ -- stat_data_sz : positive; -- = 2
+ -- end record;
constant c_sim : boolean := true;
@@ -172,7 +172,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -181,64 +181,70 @@ begin
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_ram_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+ u_mm_file_ram_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
- u_mm_file_reg_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+ u_mm_file_reg_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
- u_mm_file_ram_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+ u_mm_file_ram_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
- u_mm_file_reg_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+ u_mm_file_reg_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => c_nof_streams,
- g_buf_dat_w => c_nof_complex * c_fft.in_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_nof_streams,
+ g_buf_dat_w => c_nof_complex * c_fft.in_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
u_in_scope : entity dp_lib.dp_wideband_wb_arr_scope
- generic map (
- g_sim => true,
- g_wideband_factor => c_fft.wb_factor,
- g_wideband_big_endian => false,
- g_dat_w => c_fft.in_dat_w
- )
- port map (
- SCLK => SCLK,
- wb_sosi_arr => bg_sosi_arr,
- scope_sosi => scope_in_sosi
- );
+ generic map (
+ g_sim => true,
+ g_wideband_factor => c_fft.wb_factor,
+ g_wideband_big_endian => false,
+ g_dat_w => c_fft.in_dat_w
+ )
+ port map (
+ SCLK => SCLK,
+ wb_sosi_arr => bg_sosi_arr,
+ scope_sosi => scope_in_sosi
+ );
connect_input_data : for I in 0 to c_fft.wb_factor - 1 generate
in_re_arr(I) <= RESIZE_SVEC(bg_sosi_arr(I).re(c_fft.in_dat_w - 1 downto 0), in_re_arr(I)'length);
@@ -252,53 +258,53 @@ begin
-- DUT is instantiated.
gen_wideband_fft : if g_fft_type = "wide" generate
u_dut : entity work.fft_r2_wide
- generic map(
- g_fft => c_fft -- generics for the FFT
- )
- port map(
- clk => dp_clk,
- rst => dp_rst,
- in_re_arr => in_re_arr,
- in_im_arr => in_im_arr,
- in_val => in_val,
- out_re_arr => out_re_arr,
- out_im_arr => out_im_arr,
- out_val => out_val
- );
+ generic map(
+ g_fft => c_fft -- generics for the FFT
+ )
+ port map(
+ clk => dp_clk,
+ rst => dp_rst,
+ in_re_arr => in_re_arr,
+ in_im_arr => in_im_arr,
+ in_val => in_val,
+ out_re_arr => out_re_arr,
+ out_im_arr => out_im_arr,
+ out_val => out_val
+ );
end generate;
gen_pipelined_fft : if g_fft_type = "pipe" generate
u_dut : entity work.fft_r2_pipe
- generic map(
- g_fft => c_fft
- )
- port map(
- clk => dp_clk,
- rst => dp_rst,
- in_re => in_re_arr(0)(c_fft.in_dat_w - 1 downto 0),
- in_im => in_im_arr(0)(c_fft.in_dat_w - 1 downto 0),
- in_val => in_val,
- out_quant_re => out_re_arr(0)(c_fft.out_dat_w - 1 downto 0),
- out_quant_im => out_im_arr(0)(c_fft.out_dat_w - 1 downto 0),
- out_val => out_val
- );
+ generic map(
+ g_fft => c_fft
+ )
+ port map(
+ clk => dp_clk,
+ rst => dp_rst,
+ in_re => in_re_arr(0)(c_fft.in_dat_w - 1 downto 0),
+ in_im => in_im_arr(0)(c_fft.in_dat_w - 1 downto 0),
+ in_val => in_val,
+ out_quant_re => out_re_arr(0)(c_fft.out_dat_w - 1 downto 0),
+ out_quant_im => out_im_arr(0)(c_fft.out_dat_w - 1 downto 0),
+ out_val => out_val
+ );
end generate;
gen_parallel_fft : if g_fft_type = "par" generate
u_dut : entity work.fft_r2_par
- generic map(
- g_fft => c_fft
- )
- port map(
- clk => dp_clk,
- rst => dp_rst,
- in_re_arr => in_re_arr,
- in_im_arr => in_im_arr,
- in_val => in_val,
- out_re_arr => out_re_arr,
- out_im_arr => out_im_arr,
- out_val => out_val
- );
+ generic map(
+ g_fft => c_fft
+ )
+ port map(
+ clk => dp_clk,
+ rst => dp_rst,
+ in_re_arr => in_re_arr,
+ in_im_arr => in_im_arr,
+ in_val => in_val,
+ out_re_arr => out_re_arr,
+ out_im_arr => out_im_arr,
+ out_val => out_val
+ );
end generate;
connect_output_data : for I in 0 to c_fft.wb_factor - 1 generate
@@ -308,75 +314,75 @@ begin
end generate;
u_out_scope : entity dp_lib.dp_wideband_wb_arr_scope
- generic map (
- g_sim => true,
- g_wideband_factor => c_fft.wb_factor,
- g_wideband_big_endian => false,
- g_dat_w => c_fft.out_dat_w
- )
- port map (
- SCLK => SCLK,
- wb_sosi_arr => out_sosi_arr,
- scope_sosi => scope_out_sosi
- );
+ generic map (
+ g_sim => true,
+ g_wideband_factor => c_fft.wb_factor,
+ g_wideband_big_endian => false,
+ g_dat_w => c_fft.out_dat_w
+ )
+ port map (
+ SCLK => SCLK,
+ wb_sosi_arr => out_sosi_arr,
+ scope_sosi => scope_out_sosi
+ );
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_type => e_real,
- g_data_w => c_fft.out_dat_w,
- g_buf_nof_data => c_bg_block_len,
- g_buf_use_sync => false
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
- ram_data_buf_miso => ram_diag_data_buf_re_miso,
-
- reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
- reg_data_buf_miso => reg_diag_data_buf_re_miso,
-
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_type => e_real,
+ g_data_w => c_fft.out_dat_w,
+ g_buf_nof_data => c_bg_block_len,
+ g_buf_use_sync => false
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_type => e_imag,
- g_data_w => c_fft.out_dat_w,
- g_buf_nof_data => c_bg_block_len,
- g_buf_use_sync => false
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
- ram_data_buf_miso => ram_diag_data_buf_im_miso,
-
- reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
- reg_data_buf_miso => reg_diag_data_buf_im_miso,
-
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_type => e_imag,
+ g_data_w => c_fft.out_dat_w,
+ g_buf_nof_data => c_bg_block_len,
+ g_buf_use_sync => false
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_par.vhd
index 2a417eabe3..e2856e676c 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_par.vhd
@@ -35,18 +35,18 @@
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
library IEEE, common_lib, unb_common_lib, mm_lib, diag_lib, dp_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.fft_pkg.all;
entity tb_mmf_fft_r2_par is
generic(
@@ -148,7 +148,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -157,51 +157,57 @@ begin
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_ram_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+ u_mm_file_ram_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
- u_mm_file_reg_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+ u_mm_file_reg_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
- u_mm_file_ram_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+ u_mm_file_ram_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
- u_mm_file_reg_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+ u_mm_file_reg_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_output_streams => c_nof_streams,
- g_buf_dat_w => c_nof_complex * g_fft.in_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_output_streams => c_nof_streams,
+ g_buf_dat_w => c_nof_complex * g_fft.in_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
connect_input_data : for I in 0 to g_fft.nof_points - 1 generate
in_re_arr(I) <= RESIZE_SVEC(bg_sosi_arr(I).re(g_fft.in_dat_w - 1 downto 0), in_re_arr(I)'length);
@@ -212,19 +218,19 @@ begin
-- DUT = Device Under Test
u_dut : entity work.fft_r2_par
- generic map(
- g_fft => g_fft -- generics for the FFT
- )
- port map(
- clk => dp_clk,
- rst => dp_rst,
- in_re_arr => in_re_arr,
- in_im_arr => in_im_arr,
- in_val => in_val,
- out_re_arr => out_re_arr,
- out_im_arr => out_im_arr,
- out_val => out_val
- );
+ generic map(
+ g_fft => g_fft -- generics for the FFT
+ )
+ port map(
+ clk => dp_clk,
+ rst => dp_rst,
+ in_re_arr => in_re_arr,
+ in_im_arr => in_im_arr,
+ in_val => in_val,
+ out_re_arr => out_re_arr,
+ out_im_arr => out_im_arr,
+ out_val => out_val
+ );
connect_output_data : for I in 0 to g_fft.nof_points - 1 generate
ss_out_sosi_re_arr(I).data <= RESIZE_SVEC(out_re_arr(I), ss_out_sosi_re_arr(I).data'length);
@@ -240,57 +246,57 @@ begin
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => g_fft.out_dat_w,
- g_buf_nof_data => 1024,
- g_buf_use_sync => false
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
- ram_data_buf_miso => ram_diag_data_buf_re_miso,
-
- reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
- reg_data_buf_miso => reg_diag_data_buf_re_miso,
-
- -- ST interface
- in_sync => ss_out_sosi_re_arr(0).sync,
- in_sosi_arr => ss_out_sosi_re_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => g_fft.out_dat_w,
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+
+ -- ST interface
+ in_sync => ss_out_sosi_re_arr(0).sync,
+ in_sosi_arr => ss_out_sosi_re_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => g_fft.out_dat_w,
- g_buf_nof_data => 1024,
- g_buf_use_sync => false
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
- ram_data_buf_miso => ram_diag_data_buf_im_miso,
-
- reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
- reg_data_buf_miso => reg_diag_data_buf_im_miso,
-
- -- ST interface
- in_sync => ss_out_sosi_im_arr(0).sync,
- in_sosi_arr => ss_out_sosi_im_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => g_fft.out_dat_w,
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+
+ -- ST interface
+ in_sync => ss_out_sosi_im_arr(0).sync,
+ in_sosi_arr => ss_out_sosi_im_arr
+ );
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_pipe.vhd
index 39505893a1..641ad1869e 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_pipe.vhd
@@ -35,18 +35,18 @@
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
library IEEE, common_lib, unb_common_lib, mm_lib, diag_lib, dp_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.fft_pkg.all;
entity tb_mmf_fft_r2_pipe is
generic(
@@ -150,7 +150,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -159,51 +159,57 @@ begin
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_ram_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+ u_mm_file_ram_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
- u_mm_file_reg_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+ u_mm_file_reg_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
- u_mm_file_ram_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+ u_mm_file_ram_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
- u_mm_file_reg_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+ u_mm_file_reg_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_output_streams => c_nof_streams,
- g_buf_dat_w => c_nof_complex * g_fft.in_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_output_streams => c_nof_streams,
+ g_buf_dat_w => c_nof_complex * g_fft.in_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
in_re <= bg_sosi_arr(0).re(g_fft.in_dat_w - 1 downto 0);
in_im <= bg_sosi_arr(0).im(g_fft.in_dat_w - 1 downto 0);
@@ -211,19 +217,19 @@ begin
-- DUT = Device Under Test
u_dut : entity work.fft_r2_pipe
- generic map(
- g_fft => g_fft -- generics for the FFT
- )
- port map(
- clk => dp_clk,
- rst => dp_rst,
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- out_quant_re => out_re,
- out_quant_im => out_im,
- out_val => out_val
- );
+ generic map(
+ g_fft => g_fft -- generics for the FFT
+ )
+ port map(
+ clk => dp_clk,
+ rst => dp_rst,
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ out_quant_re => out_re,
+ out_quant_im => out_im,
+ out_val => out_val
+ );
ss_out_sosi_re_arr(0).data <= RESIZE_SVEC(out_re, ss_out_sosi_re_arr(0).data'length);
ss_out_sosi_re_arr(0).valid <= out_val;
@@ -237,57 +243,57 @@ begin
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => g_fft.out_dat_w,
- g_buf_nof_data => c_bg_block_len,
- g_buf_use_sync => false
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
- ram_data_buf_miso => ram_diag_data_buf_re_miso,
-
- reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
- reg_data_buf_miso => reg_diag_data_buf_re_miso,
-
- -- ST interface
- in_sync => ss_out_sosi_re_arr(0).sync,
- in_sosi_arr => ss_out_sosi_re_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => g_fft.out_dat_w,
+ g_buf_nof_data => c_bg_block_len,
+ g_buf_use_sync => false
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+
+ -- ST interface
+ in_sync => ss_out_sosi_re_arr(0).sync,
+ in_sosi_arr => ss_out_sosi_re_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => g_fft.out_dat_w,
- g_buf_nof_data => c_bg_block_len,
- g_buf_use_sync => false
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
- ram_data_buf_miso => ram_diag_data_buf_im_miso,
-
- reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
- reg_data_buf_miso => reg_diag_data_buf_im_miso,
-
- -- ST interface
- in_sync => ss_out_sosi_im_arr(0).sync,
- in_sosi_arr => ss_out_sosi_im_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => g_fft.out_dat_w,
+ g_buf_nof_data => c_bg_block_len,
+ g_buf_use_sync => false
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+
+ -- ST interface
+ in_sync => ss_out_sosi_im_arr(0).sync,
+ in_sosi_arr => ss_out_sosi_im_arr
+ );
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_wide_unit.vhd b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_wide_unit.vhd
index acc5adb123..dc066e472e 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_wide_unit.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_wide_unit.vhd
@@ -43,18 +43,18 @@
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
library IEEE, common_lib, mm_lib, diag_lib, dp_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.fft_pkg.all;
entity tb_mmf_fft_wide_unit is
generic(
@@ -72,23 +72,23 @@ end tb_mmf_fft_wide_unit;
architecture tb of tb_mmf_fft_wide_unit is
constant c_fft : t_fft := (true, false, g_use_separate, g_nof_chan, g_wb_factor, 0, g_nof_points, g_in_dat_w, g_out_dat_w, 0, c_dsp_mult_w, 2, true, 56, 2);
- -- type t_rtwo_fft is record
- -- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
- -- use_fft_shift : boolean; -- = false for [0, pos, neg] bin frequencies order, true for [neg, 0, pos] bin frequencies order in case of complex input
- -- use_separate : boolean; -- = false for complex input, true for two real inputs
- -- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
- -- wb_factor : natural; -- = default 1, wideband factor
- -- twiddle_offset : natural; -- = default 0, twiddle offset for PFT sections in a wideband FFT
- -- nof_points : natural; -- = 1024, N point FFT
- -- in_dat_w : natural; -- = 8, number of input bits
- -- out_dat_w : natural; -- = 13, number of output bits: in_dat_w + natural((ceil_log2(nof_points))/2 + 2)
- -- out_gain_w : natural; -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
- -- stage_dat_w : natural; -- = 18, data width used between the stages(= DSP multiplier-width)
- -- guard_w : natural; -- = 2, Guard used to avoid overflow in FFT stage.
- -- guard_enable : boolean; -- = true when input needs guarding, false when input requires no guarding but scaling must be skipped at the last stage(s) (used in wb fft)
- -- stat_data_w : positive; -- = 56
- -- stat_data_sz : positive; -- = 2
- -- end record;
+ -- type t_rtwo_fft is record
+ -- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
+ -- use_fft_shift : boolean; -- = false for [0, pos, neg] bin frequencies order, true for [neg, 0, pos] bin frequencies order in case of complex input
+ -- use_separate : boolean; -- = false for complex input, true for two real inputs
+ -- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
+ -- wb_factor : natural; -- = default 1, wideband factor
+ -- twiddle_offset : natural; -- = default 0, twiddle offset for PFT sections in a wideband FFT
+ -- nof_points : natural; -- = 1024, N point FFT
+ -- in_dat_w : natural; -- = 8, number of input bits
+ -- out_dat_w : natural; -- = 13, number of output bits: in_dat_w + natural((ceil_log2(nof_points))/2 + 2)
+ -- out_gain_w : natural; -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
+ -- stage_dat_w : natural; -- = 18, data width used between the stages(= DSP multiplier-width)
+ -- guard_w : natural; -- = 2, Guard used to avoid overflow in FFT stage.
+ -- guard_enable : boolean; -- = true when input needs guarding, false when input requires no guarding but scaling must be skipped at the last stage(s) (used in wb fft)
+ -- stat_data_w : positive; -- = 56
+ -- stat_data_sz : positive; -- = 2
+ -- end record;
constant c_sim : boolean := true;
@@ -165,7 +165,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -174,72 +174,79 @@ begin
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_ram_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+ u_mm_file_ram_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
- u_mm_file_reg_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
- port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+ u_mm_file_reg_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
- u_mm_file_ram_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+ u_mm_file_ram_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
- u_mm_file_reg_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
- port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+ u_mm_file_reg_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
- u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso);
+ u_mm_file_ram_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(0, 0, "BN") & "RAM_ST_SST")
+ port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => c_nof_streams,
- g_buf_dat_w => c_nof_complex * c_fft.in_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_nof_streams,
+ g_buf_dat_w => c_nof_complex * c_fft.in_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
---------------------------------------------------------------
-- DUT = Device Under Test
---------------------------------------------------------------
u_dut : entity work.fft_wide_unit
- generic map (
- g_fft => c_fft
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- in_sosi_arr => bg_sosi_arr,
- out_sosi_arr => result_sosi_arr
- );
+ generic map (
+ g_fft => c_fft
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ in_sosi_arr => bg_sosi_arr,
+ out_sosi_arr => result_sosi_arr
+ );
connect_output_data : for I in 0 to c_fft.wb_factor - 1 generate
ss_out_sosi_re_arr(I).data <= RESIZE_SVEC(result_sosi_arr(I).re, ss_out_sosi_re_arr(I).data'length);
@@ -255,57 +262,57 @@ begin
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => c_fft.out_dat_w,
- g_buf_nof_data => c_bg_block_len,
- g_buf_use_sync => true
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
- ram_data_buf_miso => ram_diag_data_buf_re_miso,
-
- reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
- reg_data_buf_miso => reg_diag_data_buf_re_miso,
-
- -- ST interface
- in_sync => ss_out_sosi_re_arr(0).sync,
- in_sosi_arr => ss_out_sosi_re_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_fft.out_dat_w,
+ g_buf_nof_data => c_bg_block_len,
+ g_buf_use_sync => true
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+
+ -- ST interface
+ in_sync => ss_out_sosi_re_arr(0).sync,
+ in_sosi_arr => ss_out_sosi_re_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => c_fft.out_dat_w,
- g_buf_nof_data => c_bg_block_len,
- g_buf_use_sync => true
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
- ram_data_buf_miso => ram_diag_data_buf_im_miso,
-
- reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
- reg_data_buf_miso => reg_diag_data_buf_im_miso,
-
- -- ST interface
- in_sync => ss_out_sosi_im_arr(0).sync,
- in_sosi_arr => ss_out_sosi_im_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_fft.out_dat_w,
+ g_buf_nof_data => c_bg_block_len,
+ g_buf_use_sync => true
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+
+ -- ST interface
+ in_sync => ss_out_sosi_im_arr(0).sync,
+ in_sosi_arr => ss_out_sosi_im_arr
+ );
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
index 090afe6549..16d052722d 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
@@ -29,10 +29,10 @@
-- > run -all
library IEEE, common_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.fft_pkg.all;
entity tb_tb_fft_r2_par is
end tb_tb_fft_r2_par;
@@ -60,38 +60,38 @@ architecture tb of tb_tb_fft_r2_par is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- -- DUT generics
--- g_fft : t_fft := (true, false, true, 0, 1, 0, 128, 9, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
--- -- type t_rtwo_fft is record
--- -- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
--- -- use_fft_shift : boolean; -- = false for [0, pos, neg] bin frequencies order, true for [neg, 0, pos] bin frequencies order in case of complex input
--- -- use_separate : boolean; -- = false for complex input, true for two real inputs
--- -- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
--- -- wb_factor : natural; -- = default 1, wideband factor
--- -- twiddle_offset : natural; -- = default 0, twiddle offset for PFT sections in a wideband FFT
--- -- nof_points : natural; -- = 1024, N point FFT
--- -- in_dat_w : natural; -- = 8, number of input bits
--- -- out_dat_w : natural; -- = 13, number of output bits, bit growth: in_dat_w + natural((ceil_log2(nof_points))/2 + 2)
--- -- out_gain_w : natural; -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
--- -- stage_dat_w : natural; -- = 18, data width used between the stages(= DSP multiplier-width)
--- -- guard_w : natural; -- = 2, Guard used to avoid overflow in FFT stage.
--- -- guard_enable : boolean; -- = true when input needs guarding, false when input requires no guarding but scaling must be skipped at the last stage(s) (used in wb fft)
--- -- stat_data_w : positive; -- = 56 (= 18b+18b)+log2(781250)
--- -- stat_data_sz : positive; -- = 2 (complex re and im)
--- -- end record;
--- --
--- -- TB generics
--- g_diff_margin : integer := 2; -- maximum difference between HDL output and expected output (> 0 to allow minor rounding differences)
--- -- Two real input data files A and B used when g_fft.use_separate = true
--- g_data_file_a : string := "data/run_pfft_m_impulse_chirp_8b_128points_16b.dat"; -- real input data and expected output data for 1 stream, or zeros when UNUSED
--- g_data_file_a_nof_lines : natural := 25600; -- number of lines with input data that is available in the g_data_file_a
--- g_data_file_b : string := "UNUSED";
--- g_data_file_b_nof_lines : natural := 25600; -- number of lines with input data that is available in the g_data_file_b
--- -- One complex input data file C used when g_fft.use_separate = false
--- g_data_file_c : string := "data/run_pfft_complex_m_phasor_8b_64points_16b.dat";
--- g_data_file_c_nof_lines : natural := 320;
--- g_data_file_nof_lines : natural := 320;
--- g_enable_in_val_gaps : boolean := FALSE -- when false then in_val flow control active continuously, else with random inactive gaps
+ -- -- DUT generics
+ -- g_fft : t_fft := (true, false, true, 0, 1, 0, 128, 9, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
+ -- -- type t_rtwo_fft is record
+ -- -- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
+ -- -- use_fft_shift : boolean; -- = false for [0, pos, neg] bin frequencies order, true for [neg, 0, pos] bin frequencies order in case of complex input
+ -- -- use_separate : boolean; -- = false for complex input, true for two real inputs
+ -- -- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
+ -- -- wb_factor : natural; -- = default 1, wideband factor
+ -- -- twiddle_offset : natural; -- = default 0, twiddle offset for PFT sections in a wideband FFT
+ -- -- nof_points : natural; -- = 1024, N point FFT
+ -- -- in_dat_w : natural; -- = 8, number of input bits
+ -- -- out_dat_w : natural; -- = 13, number of output bits, bit growth: in_dat_w + natural((ceil_log2(nof_points))/2 + 2)
+ -- -- out_gain_w : natural; -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
+ -- -- stage_dat_w : natural; -- = 18, data width used between the stages(= DSP multiplier-width)
+ -- -- guard_w : natural; -- = 2, Guard used to avoid overflow in FFT stage.
+ -- -- guard_enable : boolean; -- = true when input needs guarding, false when input requires no guarding but scaling must be skipped at the last stage(s) (used in wb fft)
+ -- -- stat_data_w : positive; -- = 56 (= 18b+18b)+log2(781250)
+ -- -- stat_data_sz : positive; -- = 2 (complex re and im)
+ -- -- end record;
+ -- --
+ -- -- TB generics
+ -- g_diff_margin : integer := 2; -- maximum difference between HDL output and expected output (> 0 to allow minor rounding differences)
+ -- -- Two real input data files A and B used when g_fft.use_separate = true
+ -- g_data_file_a : string := "data/run_pfft_m_impulse_chirp_8b_128points_16b.dat"; -- real input data and expected output data for 1 stream, or zeros when UNUSED
+ -- g_data_file_a_nof_lines : natural := 25600; -- number of lines with input data that is available in the g_data_file_a
+ -- g_data_file_b : string := "UNUSED";
+ -- g_data_file_b_nof_lines : natural := 25600; -- number of lines with input data that is available in the g_data_file_b
+ -- -- One complex input data file C used when g_fft.use_separate = false
+ -- g_data_file_c : string := "data/run_pfft_complex_m_phasor_8b_64points_16b.dat";
+ -- g_data_file_c_nof_lines : natural := 320;
+ -- g_data_file_nof_lines : natural := 320;
+ -- g_enable_in_val_gaps : boolean := FALSE -- when false then in_val flow control active continuously, else with random inactive gaps
-- Two real input data A and B
u_act_two_real_chirp : entity work.tb_fft_r2_par generic map (c_fft_two_real, c_diff_margin, c_sinusoid_chirp, 25600, c_impulse_chirp, 25600, c_unused, 0, 25600, false);
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
index 2a72e3c1de..82e19b8237 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
@@ -29,10 +29,10 @@
-- > run -all
library IEEE, common_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.fft_pkg.all;
entity tb_tb_fft_r2_pipe is
end tb_tb_fft_r2_pipe;
@@ -65,38 +65,38 @@ architecture tb of tb_tb_fft_r2_pipe is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- -- DUT generics
--- g_fft : t_fft := (true, false, true, 0, 1, 0, 128, 9, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
--- -- type t_rtwo_fft is record
--- -- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
--- -- use_fft_shift : boolean; -- = false for [0, pos, neg] bin frequencies order, true for [neg, 0, pos] bin frequencies order in case of complex input
--- -- use_separate : boolean; -- = false for complex input, true for two real inputs
--- -- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
--- -- wb_factor : natural; -- = default 1, wideband factor
--- -- twiddle_offset : natural; -- = default 0, twiddle offset for PFT sections in a wideband FFT
--- -- nof_points : natural; -- = 1024, N point FFT
--- -- in_dat_w : natural; -- = 8, number of input bits
--- -- out_dat_w : natural; -- = 13, number of output bits, bit growth: in_dat_w + natural((ceil_log2(nof_points))/2 + 2)
--- -- out_gain_w : natural; -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
--- -- stage_dat_w : natural; -- = 18, data width used between the stages(= DSP multiplier-width)
--- -- guard_w : natural; -- = 2, Guard used to avoid overflow in FFT stage.
--- -- guard_enable : boolean; -- = true when input needs guarding, false when input requires no guarding but scaling must be skipped at the last stage(s) (used in wb fft)
--- -- stat_data_w : positive; -- = 56 (= 18b+18b)+log2(781250)
--- -- stat_data_sz : positive; -- = 2 (complex re and im)
--- -- end record;
--- --
--- -- TB generics
--- g_diff_margin : integer := 2; -- maximum difference between HDL output and expected output (> 0 to allow minor rounding differences)
--- -- Two real input data files A and B used when g_fft.use_separate = true
--- g_data_file_a : string := "data/run_pfft_m_impulse_chirp_8b_128points_16b.dat"; -- real input data and expected output data for 1 stream, or zeros when UNUSED
--- g_data_file_a_nof_lines : natural := 25600; -- number of lines with input data that is available in the g_data_file_a
--- g_data_file_b : string := "UNUSED";
--- g_data_file_b_nof_lines : natural := 25600; -- number of lines with input data that is available in the g_data_file_b
--- -- One complex input data file C used when g_fft.use_separate = false
--- g_data_file_c : string := "data/run_pfft_complex_m_phasor_8b_64points_16b.dat";
--- g_data_file_c_nof_lines : natural := 320;
--- g_data_file_nof_lines : natural := 320;
--- g_enable_in_val_gaps : boolean := FALSE -- when false then in_val flow control active continuously, else with random inactive gaps
+ -- -- DUT generics
+ -- g_fft : t_fft := (true, false, true, 0, 1, 0, 128, 9, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
+ -- -- type t_rtwo_fft is record
+ -- -- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
+ -- -- use_fft_shift : boolean; -- = false for [0, pos, neg] bin frequencies order, true for [neg, 0, pos] bin frequencies order in case of complex input
+ -- -- use_separate : boolean; -- = false for complex input, true for two real inputs
+ -- -- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
+ -- -- wb_factor : natural; -- = default 1, wideband factor
+ -- -- twiddle_offset : natural; -- = default 0, twiddle offset for PFT sections in a wideband FFT
+ -- -- nof_points : natural; -- = 1024, N point FFT
+ -- -- in_dat_w : natural; -- = 8, number of input bits
+ -- -- out_dat_w : natural; -- = 13, number of output bits, bit growth: in_dat_w + natural((ceil_log2(nof_points))/2 + 2)
+ -- -- out_gain_w : natural; -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
+ -- -- stage_dat_w : natural; -- = 18, data width used between the stages(= DSP multiplier-width)
+ -- -- guard_w : natural; -- = 2, Guard used to avoid overflow in FFT stage.
+ -- -- guard_enable : boolean; -- = true when input needs guarding, false when input requires no guarding but scaling must be skipped at the last stage(s) (used in wb fft)
+ -- -- stat_data_w : positive; -- = 56 (= 18b+18b)+log2(781250)
+ -- -- stat_data_sz : positive; -- = 2 (complex re and im)
+ -- -- end record;
+ -- --
+ -- -- TB generics
+ -- g_diff_margin : integer := 2; -- maximum difference between HDL output and expected output (> 0 to allow minor rounding differences)
+ -- -- Two real input data files A and B used when g_fft.use_separate = true
+ -- g_data_file_a : string := "data/run_pfft_m_impulse_chirp_8b_128points_16b.dat"; -- real input data and expected output data for 1 stream, or zeros when UNUSED
+ -- g_data_file_a_nof_lines : natural := 25600; -- number of lines with input data that is available in the g_data_file_a
+ -- g_data_file_b : string := "UNUSED";
+ -- g_data_file_b_nof_lines : natural := 25600; -- number of lines with input data that is available in the g_data_file_b
+ -- -- One complex input data file C used when g_fft.use_separate = false
+ -- g_data_file_c : string := "data/run_pfft_complex_m_phasor_8b_64points_16b.dat";
+ -- g_data_file_c_nof_lines : natural := 320;
+ -- g_data_file_nof_lines : natural := 320;
+ -- g_enable_in_val_gaps : boolean := FALSE -- when false then in_val flow control active continuously, else with random inactive gaps
-- Two real input data A and B
u_act_two_real_chirp : entity work.tb_fft_r2_pipe generic map (c_fft_two_real, c_diff_margin, c_sinusoid_chirp, 25600, c_impulse_chirp, 25600, c_unused, 0, 25600, false);
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
index e48519e064..94ad63bee6 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
@@ -31,10 +31,10 @@
-- > run -all
library IEEE, common_lib, rTwoSDF_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use work.fft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use work.fft_pkg.all;
entity tb_tb_fft_r2_wide is
end tb_tb_fft_r2_wide;
@@ -65,69 +65,69 @@ architecture tb of tb_tb_fft_r2_wide is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- -- DUT generics
--- --g_fft : t_fft := ( true, false, true, 0, 4, 0, 128, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- two real inputs A and B
--- g_fft : t_fft := ( true, false, true, 0, 4, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- two real inputs A and B
--- --g_fft : t_fft := ( true, false, false, 0, 4, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- complex input reordered
--- --g_fft : t_fft := (false, false, false, 0, 4, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- complex input flipped
--- -- type t_rtwo_fft is record
--- -- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
--- -- use_fft_shift : boolean; -- = false for [0, pos, neg] bin frequencies order, true for [neg, 0, pos] bin frequencies order in case of complex input
--- -- use_separate : boolean; -- = false for complex input, true for two real inputs
--- -- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
--- -- wb_factor : natural; -- = default 1, wideband factor
--- -- twiddle_offset : natural; -- = default 0, twiddle offset for PFT sections in a wideband FFT
--- -- nof_points : natural; -- = 1024, N point FFT
--- -- in_dat_w : natural; -- = 8, number of input bits
--- -- out_dat_w : natural; -- = 13, number of output bits, bit growth: in_dat_w + natural((ceil_log2(nof_points))/2 + 2)
--- -- out_gain_w : natural; -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
--- -- stage_dat_w : natural; -- = 18, data width used between the stages(= DSP multiplier-width)
--- -- guard_w : natural; -- = 2, Guard used to avoid overflow in FFT stage.
--- -- guard_enable : boolean; -- = true when input needs guarding, false when input requires no guarding but scaling must be skipped at the last stage(s) (used in wb fft)
--- -- stat_data_w : positive; -- = 56 (= 18b+18b)+log2(781250)
--- -- stat_data_sz : positive; -- = 2 (complex re and im)
--- -- end record;
--- --
--- -- TB generics
--- g_diff_margin : integer := 2; -- maximum difference between HDL output and expected output (> 0 to allow minor rounding differences)
---
--- -- Two real input data files A and B used when g_fft.use_separate = true
--- -- * 128 points = 64 subbands
--- --g_data_file_a : string := "data/run_pfft_m_sinusoid_chirp_8b_128points_16b.dat";
--- --g_data_file_a_nof_lines : natural := 25600;
--- --g_data_file_b : string := "UNUSED";
--- --g_data_file_b_nof_lines : natural := 0;
---
--- -- * 32 points = 16 subbands
--- g_data_file_a : string := "data/run_pfft_m_sinusoid_chirp_8b_32points_16b.dat";
--- g_data_file_a_nof_lines : natural := 6400;
--- --g_data_file_a : string := "data/run_pfft_m_sinusoid_8b_32points_16b.dat";
--- --g_data_file_a_nof_lines : natural := 160;
---
--- --g_data_file_b : string := "data/run_pfft_m_impulse_chirp_8b_32points_16b.dat";
--- --g_data_file_b_nof_lines : natural := 6400;
--- g_data_file_b : string := "UNUSED";
--- g_data_file_b_nof_lines : natural := 0;
---
--- -- One complex input data file C used when g_fft.use_separate = false
--- -- * 64 points = 64 channels
--- --g_data_file_c : string := "data/run_pfft_complex_m_phasor_chirp_8b_64points_16b.dat";
--- --g_data_file_c_nof_lines : natural := 12800;
--- --g_data_file_c : string := "data/run_pfft_complex_m_phasor_8b_64points_16b.dat";
--- --g_data_file_c_nof_lines : natural := 320;
--- --g_data_file_c : string := "data/run_pfft_complex_m_noise_8b_64points_16b.dat";
--- --g_data_file_c_nof_lines : natural := 640;
---
--- -- * 32 points = 32 channels
--- g_data_file_c : string := "data/run_pfft_complex_m_phasor_chirp_8b_32points_16b.dat";
--- g_data_file_c_nof_lines : natural := 6400;
--- --g_data_file_c : string := "data/run_pfft_complex_m_phasor_8b_32points_16b.dat";
--- --g_data_file_c_nof_lines : natural := 160;
--- --g_data_file_c : string := "data/run_pfft_complex_m_noise_8b_32points_16b.dat";
--- --g_data_file_c_nof_lines : natural := 320;
---
--- g_data_file_nof_lines : natural := 6400; -- actual number of lines with input data to simulate from the data files, must be <= g_data_file_*_nof_lines
--- g_enable_in_val_gaps : boolean := TRUE -- when false then in_val flow control active continuously, else with random inactive gaps
+ -- -- DUT generics
+ -- --g_fft : t_fft := ( true, false, true, 0, 4, 0, 128, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- two real inputs A and B
+ -- g_fft : t_fft := ( true, false, true, 0, 4, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- two real inputs A and B
+ -- --g_fft : t_fft := ( true, false, false, 0, 4, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- complex input reordered
+ -- --g_fft : t_fft := (false, false, false, 0, 4, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- complex input flipped
+ -- -- type t_rtwo_fft is record
+ -- -- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
+ -- -- use_fft_shift : boolean; -- = false for [0, pos, neg] bin frequencies order, true for [neg, 0, pos] bin frequencies order in case of complex input
+ -- -- use_separate : boolean; -- = false for complex input, true for two real inputs
+ -- -- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
+ -- -- wb_factor : natural; -- = default 1, wideband factor
+ -- -- twiddle_offset : natural; -- = default 0, twiddle offset for PFT sections in a wideband FFT
+ -- -- nof_points : natural; -- = 1024, N point FFT
+ -- -- in_dat_w : natural; -- = 8, number of input bits
+ -- -- out_dat_w : natural; -- = 13, number of output bits, bit growth: in_dat_w + natural((ceil_log2(nof_points))/2 + 2)
+ -- -- out_gain_w : natural; -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
+ -- -- stage_dat_w : natural; -- = 18, data width used between the stages(= DSP multiplier-width)
+ -- -- guard_w : natural; -- = 2, Guard used to avoid overflow in FFT stage.
+ -- -- guard_enable : boolean; -- = true when input needs guarding, false when input requires no guarding but scaling must be skipped at the last stage(s) (used in wb fft)
+ -- -- stat_data_w : positive; -- = 56 (= 18b+18b)+log2(781250)
+ -- -- stat_data_sz : positive; -- = 2 (complex re and im)
+ -- -- end record;
+ -- --
+ -- -- TB generics
+ -- g_diff_margin : integer := 2; -- maximum difference between HDL output and expected output (> 0 to allow minor rounding differences)
+ --
+ -- -- Two real input data files A and B used when g_fft.use_separate = true
+ -- -- * 128 points = 64 subbands
+ -- --g_data_file_a : string := "data/run_pfft_m_sinusoid_chirp_8b_128points_16b.dat";
+ -- --g_data_file_a_nof_lines : natural := 25600;
+ -- --g_data_file_b : string := "UNUSED";
+ -- --g_data_file_b_nof_lines : natural := 0;
+ --
+ -- -- * 32 points = 16 subbands
+ -- g_data_file_a : string := "data/run_pfft_m_sinusoid_chirp_8b_32points_16b.dat";
+ -- g_data_file_a_nof_lines : natural := 6400;
+ -- --g_data_file_a : string := "data/run_pfft_m_sinusoid_8b_32points_16b.dat";
+ -- --g_data_file_a_nof_lines : natural := 160;
+ --
+ -- --g_data_file_b : string := "data/run_pfft_m_impulse_chirp_8b_32points_16b.dat";
+ -- --g_data_file_b_nof_lines : natural := 6400;
+ -- g_data_file_b : string := "UNUSED";
+ -- g_data_file_b_nof_lines : natural := 0;
+ --
+ -- -- One complex input data file C used when g_fft.use_separate = false
+ -- -- * 64 points = 64 channels
+ -- --g_data_file_c : string := "data/run_pfft_complex_m_phasor_chirp_8b_64points_16b.dat";
+ -- --g_data_file_c_nof_lines : natural := 12800;
+ -- --g_data_file_c : string := "data/run_pfft_complex_m_phasor_8b_64points_16b.dat";
+ -- --g_data_file_c_nof_lines : natural := 320;
+ -- --g_data_file_c : string := "data/run_pfft_complex_m_noise_8b_64points_16b.dat";
+ -- --g_data_file_c_nof_lines : natural := 640;
+ --
+ -- -- * 32 points = 32 channels
+ -- g_data_file_c : string := "data/run_pfft_complex_m_phasor_chirp_8b_32points_16b.dat";
+ -- g_data_file_c_nof_lines : natural := 6400;
+ -- --g_data_file_c : string := "data/run_pfft_complex_m_phasor_8b_32points_16b.dat";
+ -- --g_data_file_c_nof_lines : natural := 160;
+ -- --g_data_file_c : string := "data/run_pfft_complex_m_noise_8b_32points_16b.dat";
+ -- --g_data_file_c_nof_lines : natural := 320;
+ --
+ -- g_data_file_nof_lines : natural := 6400; -- actual number of lines with input data to simulate from the data files, must be <= g_data_file_*_nof_lines
+ -- g_enable_in_val_gaps : boolean := TRUE -- when false then in_val flow control active continuously, else with random inactive gaps
-- Two real input data A and B
u_act_two_real_chirp : entity work.tb_fft_r2_wide generic map (c_fft_wb4_two_real, c_diff_margin, c_sinusoid_chirp, 25600, c_impulse_chirp, 25600, c_unused, 0, 25600, false);
diff --git a/libraries/dsp/filter/src/vhdl/fil_pkg.vhd b/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
index 0526a3ce5e..9beb023bee 100644
--- a/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library ieee, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package fil_pkg is
-- Parameters for the (wideband) poly phase filter.
@@ -65,7 +65,7 @@ package fil_pkg is
-- . Not used in RTL, only used in test benches to verify expected subband levels
constant c_fil_lofar1_fir_filter_dc_gain : real := 0.994817;
-end package fil_pkg;
+ end package fil_pkg;
package body fil_pkg is
-end fil_pkg;
+ end fil_pkg;
diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd
index b77dcee842..616efdc65c 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd
@@ -31,10 +31,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.fil_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.fil_pkg.all;
entity fil_ppf_ctrl is
generic (
@@ -65,25 +65,25 @@ architecture rtl of fil_ppf_ctrl is
constant c_adder_latency : natural := ceil_log2(g_fil_ppf.nof_taps) * g_fil_ppf_pipeline.adder_stage;
constant c_filter_zdly : natural := g_fil_ppf.nof_bands * (2**g_fil_ppf.nof_chan);
- constant c_tot_latency : natural := g_fil_ppf_pipeline.mem_delay + c_ctrl_latency + c_mult_latency +
- c_adder_latency + g_fil_ppf_pipeline.requant_remove_lsb +
- g_fil_ppf_pipeline.requant_remove_msb;
+ constant c_tot_latency : natural := g_fil_ppf_pipeline.mem_delay + c_ctrl_latency + c_mult_latency +
+ c_adder_latency + g_fil_ppf_pipeline.requant_remove_lsb +
+ g_fil_ppf_pipeline.requant_remove_msb;
- constant c_single_taps_vec_w : natural := g_fil_ppf.in_dat_w * g_fil_ppf.nof_taps;
- constant c_taps_vec_w : natural := c_single_taps_vec_w * g_fil_ppf.nof_streams;
+ constant c_single_taps_vec_w : natural := g_fil_ppf.in_dat_w * g_fil_ppf.nof_taps;
+ constant c_taps_vec_w : natural := c_single_taps_vec_w * g_fil_ppf.nof_streams;
- type reg_type is record
- in_dat_arr : t_in_dat_delay; -- Input register for the data
- init_dly_cnt : integer range 0 to c_filter_zdly; -- Counter used to overcome the settling time of the filter.
- val_dly : std_logic_vector(c_tot_latency - 1 downto 0); -- Delay register for the valid signal
- rd_addr : std_logic_vector(c_addr_w - 1 downto 0); -- The read address
- wr_addr : std_logic_vector(c_addr_w - 1 downto 0); -- The write address
- wr_en : std_logic; -- Write enable signal for the taps memory
- taps_out_vec : std_logic_vector(c_taps_vec_w - 1 downto 0); -- Output register containing the next taps data
- out_val_ena : std_logic; -- Output enable
- end record;
+ type reg_type is record
+ in_dat_arr : t_in_dat_delay; -- Input register for the data
+ init_dly_cnt : integer range 0 to c_filter_zdly; -- Counter used to overcome the settling time of the filter.
+ val_dly : std_logic_vector(c_tot_latency - 1 downto 0); -- Delay register for the valid signal
+ rd_addr : std_logic_vector(c_addr_w - 1 downto 0); -- The read address
+ wr_addr : std_logic_vector(c_addr_w - 1 downto 0); -- The write address
+ wr_en : std_logic; -- Write enable signal for the taps memory
+ taps_out_vec : std_logic_vector(c_taps_vec_w - 1 downto 0); -- Output register containing the next taps data
+ out_val_ena : std_logic; -- Output enable
+ end record;
- signal r, rin : reg_type;
+ signal r, rin : reg_type;
begin
@@ -101,39 +101,39 @@ begin
v.in_dat_arr(g_fil_ppf_pipeline.mem_delay downto 1) := r.in_dat_arr(g_fil_ppf_pipeline.mem_delay - 1 downto 0);
if(r.val_dly(0) = '1') then -- Wait for incoming data
- v.rd_addr := INCR_UVEC(r.rd_addr, 1);
+ v.rd_addr := INCR_UVEC(r.rd_addr, 1);
end if;
if(r.val_dly(c_tot_latency - 2) = '1') then -- Wait for incoming data
- if(r.init_dly_cnt < c_filter_zdly) then
- v.init_dly_cnt := r.init_dly_cnt + 1;
- v.out_val_ena := '0';
- else
- v.out_val_ena := '1';
- end if;
+ if(r.init_dly_cnt < c_filter_zdly) then
+ v.init_dly_cnt := r.init_dly_cnt + 1;
+ v.out_val_ena := '0';
+ else
+ v.out_val_ena := '1';
+ end if;
end if;
if(r.val_dly(g_fil_ppf_pipeline.mem_delay + 1) = '1') then
- v.wr_addr := INCR_UVEC(r.wr_addr, 1);
+ v.wr_addr := INCR_UVEC(r.wr_addr, 1);
end if;
if(r.val_dly(g_fil_ppf_pipeline.mem_delay) = '1') then
- for I in 0 to g_fil_ppf.nof_streams - 1 loop
- v.taps_out_vec((I + 1) * c_single_taps_vec_w - 1 downto I * c_single_taps_vec_w) := taps_in_vec((I + 1) * c_single_taps_vec_w - g_fil_ppf.in_dat_w - 1 downto I * c_single_taps_vec_w) & r.in_dat_arr(g_fil_ppf_pipeline.mem_delay)((I + 1) * g_fil_ppf.in_dat_w - 1 downto I * g_fil_ppf.in_dat_w);
- end loop;
- --v.taps_out_vec := taps_in_vec(taps_in_vec'HIGH - g_fil_ppf.in_dat_w downto 0) & r.in_dat_arr(g_fil_ppf_pipeline.mem_delay);
- v.wr_en := '1';
+ for I in 0 to g_fil_ppf.nof_streams - 1 loop
+ v.taps_out_vec((I + 1) * c_single_taps_vec_w - 1 downto I * c_single_taps_vec_w) := taps_in_vec((I + 1) * c_single_taps_vec_w - g_fil_ppf.in_dat_w - 1 downto I * c_single_taps_vec_w) & r.in_dat_arr(g_fil_ppf_pipeline.mem_delay)((I + 1) * g_fil_ppf.in_dat_w - 1 downto I * g_fil_ppf.in_dat_w);
+ end loop;
+ --v.taps_out_vec := taps_in_vec(taps_in_vec'HIGH - g_fil_ppf.in_dat_w downto 0) & r.in_dat_arr(g_fil_ppf_pipeline.mem_delay);
+ v.wr_en := '1';
end if;
if(rst = '1') then
- v.init_dly_cnt := 0;
- v.in_dat_arr := (others => (others => '0'));
- v.val_dly := (others => '0');
- v.rd_addr := (others => '0');
- v.wr_addr := (others => '0');
- v.wr_en := '0';
- v.taps_out_vec := (others => '0');
- v.out_val_ena := '0';
+ v.init_dly_cnt := 0;
+ v.in_dat_arr := (others => (others => '0'));
+ v.val_dly := (others => '0');
+ v.rd_addr := (others => '0');
+ v.wr_addr := (others => '0');
+ v.wr_en := '0';
+ v.taps_out_vec := (others => '0');
+ v.out_val_ena := '0';
end if;
rin <= v;
diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd
index d1e6c814ba..06c5614fd8 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd
@@ -28,11 +28,11 @@
--
library IEEE, common_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use work.fil_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use work.fil_pkg.all;
entity fil_ppf_filter is
generic (
@@ -54,7 +54,7 @@ architecture rtl of fil_ppf_filter is
constant c_in_dat_w : natural := g_fil_ppf.backoff_w + g_fil_ppf.in_dat_w; -- add optional input backoff to fit output overshoot
constant c_prod_w : natural := c_in_dat_w + g_fil_ppf.coef_dat_w - c_sign_w; -- skip double sign bit
constant c_gain_w : natural := 0; -- no need for adder bit growth so fixed 0, because filter coefficients should have DC gain <= 1.
- -- The adder tree bit growth depends on DC gain of FIR coefficients, not on ceil_log2(g_fil_ppf.nof_taps).
+ -- The adder tree bit growth depends on DC gain of FIR coefficients, not on ceil_log2(g_fil_ppf.nof_taps).
constant c_sum_w : natural := c_prod_w + c_gain_w;
constant c_ppf_lsb_w : natural := c_sum_w - g_fil_ppf.out_dat_w;
@@ -75,26 +75,26 @@ begin
in_taps_backoff((I + 1) * c_in_dat_w - 1 downto I * c_in_dat_w) <= resize_svec(in_taps((I + 1) * g_fil_ppf.in_dat_w - 1 downto I * g_fil_ppf.in_dat_w), c_in_dat_w);
u_multiplier : entity common_mult_lib.common_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => c_in_dat_w,
- g_in_b_w => g_fil_ppf.coef_dat_w,
- g_out_p_w => c_prod_w,
- g_nof_mult => 1,
- g_pipeline_input => g_fil_ppf_pipeline.mult_input,
- g_pipeline_product => g_fil_ppf_pipeline.mult_product,
- g_pipeline_output => g_fil_ppf_pipeline.mult_output,
- g_representation => "SIGNED"
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_a => in_taps_backoff((I + 1) * c_in_dat_w - 1 downto I * c_in_dat_w),
- in_b => coefs((I + 1) * g_fil_ppf.coef_dat_w - 1 downto I * g_fil_ppf.coef_dat_w),
- out_p => prod_vec((I + 1) * c_prod_w - 1 downto I * c_prod_w)
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => c_in_dat_w,
+ g_in_b_w => g_fil_ppf.coef_dat_w,
+ g_out_p_w => c_prod_w,
+ g_nof_mult => 1,
+ g_pipeline_input => g_fil_ppf_pipeline.mult_input,
+ g_pipeline_product => g_fil_ppf_pipeline.mult_product,
+ g_pipeline_output => g_fil_ppf_pipeline.mult_output,
+ g_representation => "SIGNED"
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_a => in_taps_backoff((I + 1) * c_in_dat_w - 1 downto I * c_in_dat_w),
+ in_b => coefs((I + 1) * g_fil_ppf.coef_dat_w - 1 downto I * g_fil_ppf.coef_dat_w),
+ out_p => prod_vec((I + 1) * c_prod_w - 1 downto I * c_prod_w)
+ );
end generate;
---------------------------------------------------------------
@@ -102,40 +102,40 @@ begin
---------------------------------------------------------------
-- The adder tree summarizes the outputs of all multipliers.
u_adder_tree : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "SIGNED",
- g_pipeline => g_fil_ppf_pipeline.adder_stage,
- g_nof_inputs => g_fil_ppf.nof_taps,
- g_dat_w => c_prod_w,
- g_sum_w => c_sum_w
- )
- port map (
- clk => clk,
- in_dat => prod_vec,
- sum => adder_out
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => g_fil_ppf_pipeline.adder_stage,
+ g_nof_inputs => g_fil_ppf.nof_taps,
+ g_dat_w => c_prod_w,
+ g_sum_w => c_sum_w
+ )
+ port map (
+ clk => clk,
+ in_dat => prod_vec,
+ sum => adder_out
+ );
u_requantize_adder_output : entity common_lib.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_ppf_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_lsb_round_even => g_round_even,
- g_msb_clip => false,
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => g_fil_ppf_pipeline.requant_remove_lsb,
- g_pipeline_remove_msb => g_fil_ppf_pipeline.requant_remove_msb,
- g_in_dat_w => c_sum_w,
- g_out_dat_w => g_fil_ppf.out_dat_w
- )
- port map (
- clk => clk,
- clken => '1',
- in_dat => adder_out,
- out_dat => requant_out,
- out_ovr => open
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_ppf_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_lsb_round_even => g_round_even,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => g_fil_ppf_pipeline.requant_remove_lsb,
+ g_pipeline_remove_msb => g_fil_ppf_pipeline.requant_remove_msb,
+ g_in_dat_w => c_sum_w,
+ g_out_dat_w => g_fil_ppf.out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ in_dat => adder_out,
+ out_dat => requant_out,
+ out_ovr => open
+ );
result <= RESIZE_SVEC(requant_out, result'length);
end rtl;
diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_single.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_single.vhd
index 57baa9b3d8..ce1a959968 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_single.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_single.vhd
@@ -64,11 +64,11 @@
-- . See also description tb_fil_ppf_single.vhd for more info.
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.fil_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.fil_pkg.all;
entity fil_ppf_single is
generic (
@@ -101,17 +101,19 @@ architecture rtl of fil_ppf_single is
constant c_taps_mem_data_w : natural := g_fil_ppf.in_dat_w * g_fil_ppf.nof_taps;
constant c_coef_mem_data_w : natural := g_fil_ppf.coef_dat_w;
- constant c_taps_mem : t_c_mem := (latency => c_taps_mem_delay,
- adr_w => c_taps_mem_addr_w,
- dat_w => c_taps_mem_data_w,
- nof_dat => g_fil_ppf.nof_bands * (2**g_fil_ppf.nof_chan),
- init_sl => '0'); -- use '0' instead of 'X' to avoid RTL RAM simulation warnings due to read before write
+ constant c_taps_mem : t_c_mem := (
+ latency => c_taps_mem_delay,
+ adr_w => c_taps_mem_addr_w,
+ dat_w => c_taps_mem_data_w,
+ nof_dat => g_fil_ppf.nof_bands * (2**g_fil_ppf.nof_chan),
+ init_sl => '0'); -- use '0' instead of 'X' to avoid RTL RAM simulation warnings due to read before write
- constant c_coef_mem : t_c_mem := (latency => c_coef_mem_delay,
- adr_w => c_coef_mem_addr_w,
- dat_w => c_coef_mem_data_w,
- nof_dat => g_fil_ppf.nof_bands,
- init_sl => '0'); -- use '0' instead of 'X' to avoid RTL RAM simulation warnings due to read before write
+ constant c_coef_mem : t_c_mem := (
+ latency => c_coef_mem_delay,
+ adr_w => c_coef_mem_addr_w,
+ dat_w => c_coef_mem_data_w,
+ nof_dat => g_fil_ppf.nof_bands,
+ init_sl => '0'); -- use '0' instead of 'X' to avoid RTL RAM simulation warnings due to read before write
signal ram_coefs_mosi_arr : t_mem_mosi_arr(g_fil_ppf.nof_taps - 1 downto 0);
signal ram_coefs_miso_arr : t_mem_miso_arr(g_fil_ppf.nof_taps - 1 downto 0) := (others => c_mem_miso_rst);
@@ -128,21 +130,21 @@ begin
---------------------------------------------------------------
gen_taps_mems : for I in 0 to g_fil_ppf.nof_streams - 1 generate
u_taps_mem : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_taps_mem,
- g_init_file => "UNUSED" -- assume block RAM gets initialized to '0' by default in simulation
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- wr_en => taps_wren,
- wr_adr => taps_wraddr,
- wr_dat => taps_mem_in_vec((I + 1) * c_taps_mem_data_w - 1 downto I * c_taps_mem_data_w),
- rd_en => '1',
- rd_adr => taps_rdaddr,
- rd_dat => taps_mem_out_vec((I + 1) * c_taps_mem_data_w - 1 downto I * c_taps_mem_data_w),
- rd_val => open
- );
+ generic map (
+ g_ram => c_taps_mem,
+ g_init_file => "UNUSED" -- assume block RAM gets initialized to '0' by default in simulation
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ wr_en => taps_wren,
+ wr_adr => taps_wraddr,
+ wr_dat => taps_mem_in_vec((I + 1) * c_taps_mem_data_w - 1 downto I * c_taps_mem_data_w),
+ rd_en => '1',
+ rd_adr => taps_rdaddr,
+ rd_dat => taps_mem_out_vec((I + 1) * c_taps_mem_data_w - 1 downto I * c_taps_mem_data_w),
+ rd_val => open
+ );
end generate;
---------------------------------------------------------------
@@ -151,16 +153,16 @@ begin
-- Combine the internal array of mm interfaces for the coefficents
-- memory to one array that is connected to the port of the fil_ppf
u_mem_mux_coef : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_fil_ppf.nof_taps,
- g_mult_addr_w => c_coef_mem_addr_w
- )
- port map (
- mosi => ram_coefs_mosi,
- miso => ram_coefs_miso,
- mosi_arr => ram_coefs_mosi_arr,
- miso_arr => ram_coefs_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_fil_ppf.nof_taps,
+ g_mult_addr_w => c_coef_mem_addr_w
+ )
+ port map (
+ mosi => ram_coefs_mosi,
+ miso => ram_coefs_miso,
+ mosi_arr => ram_coefs_mosi_arr,
+ miso_arr => ram_coefs_miso_arr
+ );
---------------------------------------------------------------
-- GENERATE THE COEFFICIENT MEMORIES
@@ -169,31 +171,31 @@ begin
-- the corresponding coefficients for all the bands.
gen_coef_mems : for I in 0 to g_fil_ppf.nof_taps - 1 generate
u_coef_mem : entity common_lib.common_ram_crw_crw
- generic map (
- g_ram => c_coef_mem,
- -- Sequence number and ".hex" extensie are added to the relative path in case a ram file is provided.
- g_init_file => sel_a_b(g_coefs_file_prefix = "UNUSED", g_coefs_file_prefix, g_coefs_file_prefix & "_" & natural'image(g_file_index_arr(I)) & c_coefs_postfix)
- )
- port map (
- -- MM side
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_coefs_mosi_arr(I).wr,
- wr_dat_a => ram_coefs_mosi_arr(I).wrdata(g_fil_ppf.coef_dat_w - 1 downto 0),
- adr_a => ram_coefs_mosi_arr(I).address(c_coef_mem.adr_w - 1 downto 0),
- rd_en_a => ram_coefs_mosi_arr(I).rd,
- rd_dat_a => ram_coefs_miso_arr(I).rddata(g_fil_ppf.coef_dat_w - 1 downto 0),
- rd_val_a => ram_coefs_miso_arr(I).rdval,
- -- Datapath side
- rst_b => dp_rst,
- clk_b => dp_clk,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- adr_b => coef_rdaddr,
- rd_en_b => '1',
- rd_dat_b => coef_vec((I + 1) * c_coef_mem_data_w - 1 downto I * c_coef_mem_data_w),
- rd_val_b => open
- );
+ generic map (
+ g_ram => c_coef_mem,
+ -- Sequence number and ".hex" extensie are added to the relative path in case a ram file is provided.
+ g_init_file => sel_a_b(g_coefs_file_prefix = "UNUSED", g_coefs_file_prefix, g_coefs_file_prefix & "_" & natural'image(g_file_index_arr(I)) & c_coefs_postfix)
+ )
+ port map (
+ -- MM side
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_coefs_mosi_arr(I).wr,
+ wr_dat_a => ram_coefs_mosi_arr(I).wrdata(g_fil_ppf.coef_dat_w - 1 downto 0),
+ adr_a => ram_coefs_mosi_arr(I).address(c_coef_mem.adr_w - 1 downto 0),
+ rd_en_a => ram_coefs_mosi_arr(I).rd,
+ rd_dat_a => ram_coefs_miso_arr(I).rddata(g_fil_ppf.coef_dat_w - 1 downto 0),
+ rd_val_a => ram_coefs_miso_arr(I).rdval,
+ -- Datapath side
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ adr_b => coef_rdaddr,
+ rd_en_b => '1',
+ rd_dat_b => coef_vec((I + 1) * c_coef_mem_data_w - 1 downto I * c_coef_mem_data_w),
+ rd_val_b => open
+ );
end generate;
-- Address the coefficients, taking into account the nof_chan. The coefficients will only be
@@ -207,22 +209,22 @@ begin
-- the tap memory, along with the historical tap data.
-- It also controls the reading of the coefficients memory.
u_fil_ctrl : entity work.fil_ppf_ctrl
- generic map (
- g_fil_ppf_pipeline => g_fil_ppf_pipeline,
- g_fil_ppf => g_fil_ppf
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
- in_dat => in_dat,
- in_val => in_val,
- taps_rdaddr => taps_rdaddr,
- taps_wraddr => taps_wraddr,
- taps_wren => taps_wren,
- taps_in_vec => taps_mem_out_vec,
- taps_out_vec => taps_mem_in_vec,
- out_val => out_val
- );
+ generic map (
+ g_fil_ppf_pipeline => g_fil_ppf_pipeline,
+ g_fil_ppf => g_fil_ppf
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+ in_dat => in_dat,
+ in_val => in_val,
+ taps_rdaddr => taps_rdaddr,
+ taps_wraddr => taps_wraddr,
+ taps_wren => taps_wren,
+ taps_in_vec => taps_mem_out_vec,
+ taps_out_vec => taps_mem_in_vec,
+ out_val => out_val
+ );
---------------------------------------------------------------
-- FILTER UNIT
@@ -231,18 +233,18 @@ begin
-- multiplications and additions.
gen_filter_units : for I in 0 to g_fil_ppf.nof_streams - 1 generate
u_filter : entity work.fil_ppf_filter
- generic map (
- g_fil_ppf_pipeline => g_fil_ppf_pipeline,
- g_fil_ppf => g_fil_ppf,
- g_round_even => g_round_even
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
- taps => taps_mem_out_vec((I + 1) * c_taps_mem_data_w - 1 downto I * c_taps_mem_data_w),
- coefs => coef_vec,
- result => out_dat((I + 1) * g_fil_ppf.out_dat_w - 1 downto I * g_fil_ppf.out_dat_w)
- );
+ generic map (
+ g_fil_ppf_pipeline => g_fil_ppf_pipeline,
+ g_fil_ppf => g_fil_ppf,
+ g_round_even => g_round_even
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+ taps => taps_mem_out_vec((I + 1) * c_taps_mem_data_w - 1 downto I * c_taps_mem_data_w),
+ coefs => coef_vec,
+ result => out_dat((I + 1) * g_fil_ppf.out_dat_w - 1 downto I * g_fil_ppf.out_dat_w)
+ );
end generate;
end rtl;
diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd
index fa57b10ec6..7506d986f5 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd
@@ -109,11 +109,11 @@
-- . See also description tb_fil_ppf_single.vhd for more info.
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.fil_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.fil_pkg.all;
entity fil_ppf_wide is
generic (
@@ -123,7 +123,7 @@ entity fil_ppf_wide is
g_fil_ppf_pipeline : t_fil_ppf_pipeline := c_fil_ppf_pipeline;
g_round_even : boolean := true;
g_coefs_file_prefix : string := "../../data/coef" -- Relative path to the mif files that contain the FIR the coefficients
- -- The sequence number and ".mif"-extension are added within the entity.
+ -- The sequence number and ".mif"-extension are added within the entity.
);
port (
dp_clk : in std_logic;
@@ -200,16 +200,16 @@ begin
-- Combine the internal array of mm interfaces for the coefficents
-- memory to one array that is connected to the port of the fil_ppf_w
u_mem_mux_coef : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_fil_ppf.wb_factor,
- g_mult_addr_w => c_mem_addr_w
- )
- port map (
- mosi => ram_coefs_mosi,
- miso => ram_coefs_miso,
- mosi_arr => ram_coefs_mosi_arr,
- miso_arr => ram_coefs_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_fil_ppf.wb_factor,
+ g_mult_addr_w => c_mem_addr_w
+ )
+ port map (
+ mosi => ram_coefs_mosi,
+ miso => ram_coefs_miso,
+ mosi_arr => ram_coefs_mosi_arr,
+ miso_arr => ram_coefs_miso_arr
+ );
p_wire_input : process(in_dat_arr)
variable vP : natural;
@@ -231,25 +231,25 @@ begin
---------------------------------------------------------------
gen_fil_ppf_singles : for P in 0 to g_fil_ppf.wb_factor - 1 generate
u_fil_ppf_single : entity work.fil_ppf_single
- generic map (
- g_fil_ppf => c_fil_ppf_arr(P),
- g_fil_ppf_pipeline => g_fil_ppf_pipeline,
- g_round_even => g_round_even,
- g_file_index_arr => c_file_index_arr2(P), -- use (g_fil_ppf.wb_factor-1 - P) to try impact of reversed WB FIR coefficients
- g_coefs_file_prefix => g_coefs_file_prefix
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- ram_coefs_mosi => ram_coefs_mosi_arr(P),
- ram_coefs_miso => ram_coefs_miso_arr(P),
- in_dat => streams_in_arr(P),
- in_val => in_val,
- out_dat => streams_out_arr(P),
- out_val => streams_out_val_arr(P)
- );
+ generic map (
+ g_fil_ppf => c_fil_ppf_arr(P),
+ g_fil_ppf_pipeline => g_fil_ppf_pipeline,
+ g_round_even => g_round_even,
+ g_file_index_arr => c_file_index_arr2(P), -- use (g_fil_ppf.wb_factor-1 - P) to try impact of reversed WB FIR coefficients
+ g_coefs_file_prefix => g_coefs_file_prefix
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ ram_coefs_mosi => ram_coefs_mosi_arr(P),
+ ram_coefs_miso => ram_coefs_miso_arr(P),
+ in_dat => streams_in_arr(P),
+ in_val => in_val,
+ out_dat => streams_out_arr(P),
+ out_val => streams_out_val_arr(P)
+ );
end generate;
p_wire_output : process(streams_out_arr)
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
index a46728b9cf..de0562955e 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
@@ -130,47 +130,47 @@
-- > testbench is selftesting.
--
library ieee, common_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_textio.all;
-use STD.textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.fil_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.std_logic_textio.all;
+ use STD.textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.fil_pkg.all;
entity tb_fil_ppf_single is
generic(
g_fil_ppf_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
- -- type t_fil_pipeline is record
- -- -- generic for the taps and coefficients memory
- -- mem_delay : natural; -- = 2
- -- -- generics for the multiplier in in the filter unit
- -- mult_input : natural; -- = 1
- -- mult_product : natural; -- = 1
- -- mult_output : natural; -- = 1
- -- -- generics for the adder tree in in the filter unit
- -- adder_stage : natural; -- = 1
- -- -- generics for the requantizer in the filter unit
- -- requant_remove_lsb : natural; -- = 1
- -- requant_remove_msb : natural; -- = 0
- -- end record;
+ -- type t_fil_pipeline is record
+ -- -- generic for the taps and coefficients memory
+ -- mem_delay : natural; -- = 2
+ -- -- generics for the multiplier in in the filter unit
+ -- mult_input : natural; -- = 1
+ -- mult_product : natural; -- = 1
+ -- mult_output : natural; -- = 1
+ -- -- generics for the adder tree in in the filter unit
+ -- adder_stage : natural; -- = 1
+ -- -- generics for the requantizer in the filter unit
+ -- requant_remove_lsb : natural; -- = 1
+ -- requant_remove_msb : natural; -- = 0
+ -- end record;
g_fil_ppf : t_fil_ppf := (1, 1, 64, 8, 1, 0, 8, 16, 16);
- -- type t_fil_ppf is record
- -- wb_factor : natural; -- = 1, the wideband factor
- -- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
- -- nof_bands : natural; -- = 128, the number of polyphase channels (= number of points of the FFT)
- -- nof_taps : natural; -- = 16, the number of FIR taps per subband
- -- nof_streams : natural; -- = 1, the number of streams that are served by the same coefficients.
- -- backoff_w : natural; -- = 0, number of bits for input backoff to avoid output overflow
- -- in_dat_w : natural; -- = 8, number of input bits per stream
- -- out_dat_w : natural; -- = 23, number of output bits (per stream). It is set to in_dat_w+coef_dat_w-1 = 23 to be sure the requantizer
- -- does not remove any of the data in order to be able to verify with the original coefficients values.
- -- coef_dat_w : natural; -- = 16, data width of the FIR coefficients
- -- end record;
+ -- type t_fil_ppf is record
+ -- wb_factor : natural; -- = 1, the wideband factor
+ -- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
+ -- nof_bands : natural; -- = 128, the number of polyphase channels (= number of points of the FFT)
+ -- nof_taps : natural; -- = 16, the number of FIR taps per subband
+ -- nof_streams : natural; -- = 1, the number of streams that are served by the same coefficients.
+ -- backoff_w : natural; -- = 0, number of bits for input backoff to avoid output overflow
+ -- in_dat_w : natural; -- = 8, number of input bits per stream
+ -- out_dat_w : natural; -- = 23, number of output bits (per stream). It is set to in_dat_w+coef_dat_w-1 = 23 to be sure the requantizer
+ -- does not remove any of the data in order to be able to verify with the original coefficients values.
+ -- coef_dat_w : natural; -- = 16, data width of the FIR coefficients
+ -- end record;
g_coefs_file_prefix : string := "hex/run_pfir_coeff_m_incrementing";
g_enable_in_val_gaps : boolean := false
);
@@ -187,51 +187,52 @@ architecture tb of tb_fil_ppf_single is
constant c_nof_mif_files : natural := g_fil_ppf.nof_taps;
constant c_mif_coef_mem_addr_w : natural := ceil_log2(g_fil_ppf.nof_bands);
constant c_mif_coef_mem_span : natural := 2**c_mif_coef_mem_addr_w; -- mif coef mem span for one tap
- constant c_coefs_file_prefix : string := g_coefs_file_prefix & "_" & integer'image(g_fil_ppf.nof_taps) & "taps" &
- "_" & integer'image(g_fil_ppf.nof_bands) & "points" &
- "_" & integer'image(g_fil_ppf.coef_dat_w) & "b";
- constant c_mif_file_prefix : string := c_coefs_file_prefix & "_" & "1wb";
- constant c_mif_file_index_arr : t_nat_natural_arr := array_init(0, c_nof_mif_files, 1);
+ constant c_coefs_file_prefix : string := g_coefs_file_prefix & "_" & integer'image(
+ g_fil_ppf.nof_taps) & "taps" &
+ "_" & integer'image(g_fil_ppf.nof_bands) & "points" &
+ "_" & integer'image(g_fil_ppf.coef_dat_w) & "b";
+ constant c_mif_file_prefix : string := c_coefs_file_prefix & "_" &