diff --git a/libraries/external/easics/hdllib.cfg b/libraries/external/easics/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..01eb4c9ed0a40e1b5311e3092f38bb789695f1ec
--- /dev/null
+++ b/libraries/external/easics/hdllib.cfg
@@ -0,0 +1,65 @@
+hdl_lib_name = easics
+hdl_library_clause_name = easics_lib
+hdl_lib_uses = 
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+    src/vhdl/PCK_CRC64_D8.vhd
+    src/vhdl/PCK_CRC64_D16.vhd
+    src/vhdl/PCK_CRC64_D32.vhd
+    src/vhdl/PCK_CRC64_D64.vhd
+    src/vhdl/PCK_CRC64_D72.vhd
+    src/vhdl/PCK_CRC64_D128.vhd
+    src/vhdl/PCK_CRC64_D256.vhd
+    src/vhdl/PCK_CRC64_D512.vhd
+    src/vhdl/PCK_CRC64_D1024.vhd
+    src/vhdl/PCK_CRC32_D4.vhd
+    src/vhdl/PCK_CRC32_D8.vhd
+    src/vhdl/PCK_CRC32_D9.vhd
+    src/vhdl/PCK_CRC32_D10.vhd
+    src/vhdl/PCK_CRC32_D16.vhd
+    src/vhdl/PCK_CRC32_D18.vhd
+    src/vhdl/PCK_CRC32_D20.vhd
+    src/vhdl/PCK_CRC32_D24.vhd
+    src/vhdl/PCK_CRC32_D32.vhd
+    src/vhdl/PCK_CRC32_D36.vhd
+    src/vhdl/PCK_CRC32_D40.vhd
+    src/vhdl/PCK_CRC32_D48.vhd
+    src/vhdl/PCK_CRC32_D64.vhd
+    src/vhdl/PCK_CRC32_D72.vhd
+    src/vhdl/PCK_CRC32_D128.vhd
+    src/vhdl/PCK_CRC32_D256.vhd
+    src/vhdl/PCK_CRC32_D512.vhd
+    src/vhdl/PCK_CRC32_D1024.vhd
+    src/vhdl/PCK_CRC16_D4.vhd
+    src/vhdl/PCK_CRC16_D8.vhd
+    src/vhdl/PCK_CRC16_D9.vhd
+    src/vhdl/PCK_CRC16_D10.vhd
+    src/vhdl/PCK_CRC16_D16.vhd
+    src/vhdl/PCK_CRC16_D18.vhd
+    src/vhdl/PCK_CRC16_D20.vhd
+    src/vhdl/PCK_CRC16_D24.vhd
+    src/vhdl/PCK_CRC16_D32.vhd
+    src/vhdl/PCK_CRC16_D36.vhd
+    src/vhdl/PCK_CRC16_D48.vhd
+    src/vhdl/PCK_CRC16_D64.vhd
+    src/vhdl/PCK_CRC16_D72.vhd
+    src/vhdl/PCK_CRC8_D4.vhd
+    src/vhdl/PCK_CRC8_D8.vhd
+    src/vhdl/PCK_CRC8_D9.vhd
+    src/vhdl/PCK_CRC8_D10.vhd
+    src/vhdl/PCK_CRC8_D16.vhd
+    src/vhdl/PCK_CRC8_D18.vhd
+    src/vhdl/PCK_CRC8_D20.vhd
+    src/vhdl/PCK_CRC8_D24.vhd
+    src/vhdl/PCK_CRC8_D32.vhd
+    src/vhdl/PCK_CRC8_D36.vhd
+    src/vhdl/PCK_CRC8_D48.vhd
+    src/vhdl/PCK_CRC8_D64.vhd
+    src/vhdl/PCK_CRC8_D72.vhd
+    src/vhdl/RAD_CRC20_D20.vhd
+    src/vhdl/RAD_CRC16_D16.vhd
+    src/vhdl/RAD_CRC18_D18.vhd
+test_bench_files =