diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
index c854fbb25961c387d6ba0ccfda5a233dab1bd38c..b45b48b74132a6b57e3dd8ea406b5e1f1c03d8be 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = lofar2_unb2b_adc
hdl_library_clause_name = lofar2_unb2b_adc_lib
-hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tr_10GbE diagnostics diag aduh tech_jesd204b
+hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tr_10GbE diagnostics diag aduh tech_jesd204b lofar2_sdp
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 8b1fd257b00d9900b3a2a5f9a52e7540b3d5497b..96e3c42900bd80357dc8c4f7ef22ca834fa67a6e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -26,7 +26,7 @@
-- Contains all the signal processing blocks to receive and time the ADC input data
-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -37,6 +37,7 @@ USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE work.lofar2_unb2b_adc_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
ENTITY node_adc_input_and_timing IS
GENERIC (
@@ -329,7 +330,7 @@ BEGIN
g_buf_addr_w => c_wg_buf_addr_w,
g_calc_support => TRUE,
g_calc_gain_w => 1,
- g_calc_dat_w => c_wg_buf_dat_w
+ g_calc_dat_w => c_sdp_W_adc
)
PORT MAP (
-- Memory-mapped clock domain
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl
index b9b185d65f45da9dd8b0cba70ebb5c255029ec7e..851a631d744084345d1228d08c4c7b09bce10c5c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl
@@ -72,40 +72,41 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[4]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST
-### QSFP_0_0
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[0]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0]
-
-### QSFP_0_RX
-set_location_assignment PIN_AN38 -to QSFP_0_RX[0]
-set_location_assignment PIN_AM40 -to QSFP_0_RX[1]
-set_location_assignment PIN_AK40 -to QSFP_0_RX[2]
-set_location_assignment PIN_AJ38 -to QSFP_0_RX[3]
-
-### QSFP_0_TX
-set_location_assignment PIN_AN42 -to QSFP_0_TX[0]
-set_location_assignment PIN_AM44 -to QSFP_0_TX[1]
-set_location_assignment PIN_AK44 -to QSFP_0_TX[2]
-set_location_assignment PIN_AJ42 -to QSFP_0_TX[3]
+### QSFP_1_0
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[0]
+
+### QSFP_1_RX
+set_location_assignment PIN_AC38 -to QSFP_1_RX[0]
+set_location_assignment PIN_AD40 -to QSFP_1_RX[1]
+set_location_assignment PIN_AF40 -to QSFP_1_RX[2]
+set_location_assignment PIN_AG38 -to QSFP_1_RX[3]
+
+### QSFP_1_TX
+set_location_assignment PIN_AC42 -to QSFP_1_TX[0]
+set_location_assignment PIN_AD44 -to QSFP_1_TX[1]
+set_location_assignment PIN_AF44 -to QSFP_1_TX[2]
+set_location_assignment PIN_AG42 -to QSFP_1_TX[3]
+
#=====================
# JESD pins
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
index d1e04a698ce4bcbee592cde4a04cfd68fe45efd4..f81831264c54622703af2c96fabe1c164ced74af 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
@@ -77,8 +77,8 @@ ENTITY lofar2_unb2b_beamformer_one_node IS
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
-- front transceivers
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
@@ -160,8 +160,8 @@ BEGIN
SA_CLK => SA_CLK,
-- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
-- LEDs
QSFP_LED => QSFP_LED,
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
index f71e3bc47ae99291e402634751d1410167a3e742..b543da94832479e51499a57d5fcbe6974a8c86dc 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
@@ -77,8 +77,8 @@ ENTITY lofar2_unb2b_beamformer_one_node_256MHz IS
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
-- front transceivers
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
@@ -160,8 +160,8 @@ BEGIN
SA_CLK => SA_CLK,
-- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
-- LEDs
QSFP_LED => QSFP_LED,
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
index 713a076bafdea9b2bc0346797ea45a4e1551446c..f894280241e8152fb4286f01898c31d001f18756 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
@@ -88,8 +88,8 @@ ENTITY lofar2_unb2b_beamformer IS
-- Transceiver clocks
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
-- front transceivers
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
@@ -652,7 +652,8 @@ BEGIN
dp_clk => dp_clk,
dp_rst => dp_rst,
- -- mm control buses
+ -- mm control buses
+ jesd_ctrl_mosi => c_mem_mosi_rst,
jesd204b_mosi => jesd204b_mosi,
jesd204b_miso => jesd204b_miso,
reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
@@ -720,7 +721,13 @@ BEGIN
ram_gains_mosi => ram_equalizer_gains_mosi,
ram_gains_miso => ram_equalizer_gains_miso,
reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso
+ reg_selector_miso => reg_dp_selector_miso,
+
+ sdp_info => sdp_info,
+ gn_id => ID(c_sdp_W_gn_id-1 DOWNTO 0),
+ eth_src_mac => eth_src_mac,
+ ip_src_addr => ip_src_addr,
+ udp_src_port => udp_src_port
);
@@ -913,8 +920,8 @@ BEGIN
-----------------------------------------------------------------------------
-- put the QSFP_TX/RX ports into arrays
- i_QSFP_RX(0) <= QSFP_0_RX;
- QSFP_0_TX <= i_QSFP_TX(0);
+ i_QSFP_RX(0) <= QSFP_1_RX;
+ QSFP_1_TX <= i_QSFP_TX(0);
------------
-- Front IO
------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
index 2835898c6e22aca78028e8df312539a1a65d3313..6b60e21f0ab95664410e5e844ebb2c187d442c36 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
@@ -93,9 +93,9 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_beamformer IS
CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
-- WG
- CONSTANT c_full_scale_ampl : REAL := REAL(2**(18-1)-1); -- = full scale of WG
+ CONSTANT c_full_scale_ampl : REAL := REAL(2**(14-1)-1); -- = full scale of WG
CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/2; -- in number of lsb
+ CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1) / 2; -- in number of lsb
CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
@@ -215,7 +215,7 @@ BEGIN
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
- proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
jesd204b_sysref <= pps;
ext_pps <= pps;
@@ -261,8 +261,8 @@ BEGIN
-- Transceiver clocks
SA_CLK => SA_CLK,
-- front transceivers
- QSFP_0_RX => si_lpbk_0,
- QSFP_0_TX => si_lpbk_0,
+ QSFP_1_RX => si_lpbk_0,
+ QSFP_1_TX => si_lpbk_0,
-- LEDs
QSFP_LED => open,
@@ -337,7 +337,7 @@ BEGIN
-- Enable UDP offload (dp_xonoff) of beamset 0
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff,0 , 1, tb_clk);
- --mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff,2 , 1, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff,2 , 1, tb_clk);
----------------------------------------------------------------------------
-- Enable BS
@@ -458,7 +458,7 @@ BEGIN
-- Read 10GbE Stream
---------------------------------------------------------------------------
proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.sop);
- FOR I IN 0 TO 9 LOOP -- Packet header
+ FOR I IN 0 TO 8 LOOP -- Packet header is 9.25 words wide, which can be discarded
proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
proc_common_wait_some_cycles(ext_clk, 1);
END LOOP;