From c17aaa0a2bb4c1c9d1d4345c19a49a6bbc77ed52 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Wed, 21 Mar 2018 15:55:06 +0000
Subject: [PATCH] added ip_arria10_e1sg_complex_mult component
---
.../technology/mult/tech_mult_component_pkg.vhd | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/libraries/technology/mult/tech_mult_component_pkg.vhd b/libraries/technology/mult/tech_mult_component_pkg.vhd
index 2aa97f8b26..e61c3307a1 100644
--- a/libraries/technology/mult/tech_mult_component_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_component_pkg.vhd
@@ -176,6 +176,7 @@ PACKAGE tech_mult_component_pkg IS
);
END COMPONENT;
+
COMPONENT ip_arria10_complex_mult_rtl IS
GENERIC (
g_in_a_w : POSITIVE := 18;
@@ -300,4 +301,17 @@ PACKAGE tech_mult_component_pkg IS
);
END COMPONENT;
+ COMPONENT ip_arria10_e1sg_complex_mult is
+ PORT (
+ dataa_real : in std_logic_vector(17 downto 0) := (others => '0'); -- complex_input.dataa_real
+ dataa_imag : in std_logic_vector(17 downto 0) := (others => '0'); -- .dataa_imag
+ datab_real : in std_logic_vector(17 downto 0) := (others => '0'); -- .datab_real
+ datab_imag : in std_logic_vector(17 downto 0) := (others => '0'); -- .datab_imag
+ clock : in std_logic := '0'; -- .clk
+ aclr : in std_logic := '0'; -- .aclr
+ ena : in std_logic := '0'; -- .ena
+ result_real : out std_logic_vector(35 downto 0); -- complex_output.result_real
+ result_imag : out std_logic_vector(35 downto 0) -- .result_imag
+ );
+ END COMPONENT;
END tech_mult_component_pkg;
--
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