diff --git a/libraries/technology/mult/tech_mult_component_pkg.vhd b/libraries/technology/mult/tech_mult_component_pkg.vhd
index 2aa97f8b26fa147695a67f88c86e9ec34f70562d..e61c3307a1df27d336acbfe6630c06615d3e6883 100644
--- a/libraries/technology/mult/tech_mult_component_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_component_pkg.vhd
@@ -176,6 +176,7 @@ PACKAGE tech_mult_component_pkg IS
   );
   END COMPONENT;
 
+
   COMPONENT ip_arria10_complex_mult_rtl IS
   GENERIC (
     g_in_a_w           : POSITIVE := 18;
@@ -300,4 +301,17 @@ PACKAGE tech_mult_component_pkg IS
   );
   END COMPONENT;
 
+  COMPONENT ip_arria10_e1sg_complex_mult is
+  PORT (
+    dataa_real  : in  std_logic_vector(17 downto 0) := (others => '0'); --  complex_input.dataa_real
+    dataa_imag  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .dataa_imag
+    datab_real  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .datab_real
+    datab_imag  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .datab_imag
+    clock       : in  std_logic                     := '0';             --               .clk
+    aclr        : in  std_logic                     := '0';             --               .aclr
+    ena         : in  std_logic                     := '0';             --               .ena
+    result_real : out std_logic_vector(35 downto 0);                    -- complex_output.result_real
+    result_imag : out std_logic_vector(35 downto 0)                     --               .result_imag
+  );
+  END COMPONENT;
 END tech_mult_component_pkg;