From c157ca314a4061e816b608d41b48e3ed334105d6 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Mon, 22 Dec 2014 15:31:28 +0000
Subject: [PATCH] Prepare for DDR mosi/miso ports by adding ports
ctlr_rddata,rdval and ctlr_address,wrdata.
---
libraries/io/ddr/src/vhdl/io_ddr_driver.vhd | 59 +++++++++++++--------
1 file changed, 38 insertions(+), 21 deletions(-)
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd b/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
index fdd662524d..02589d8c25 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
@@ -20,10 +20,11 @@
--
--------------------------------------------------------------------------------
-LIBRARY IEEE, tech_ddr_lib, common_lib;
+LIBRARY IEEE, tech_ddr_lib, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY io_ddr_driver IS
@@ -36,9 +37,15 @@ ENTITY io_ddr_driver IS
rst : IN STD_LOGIC;
ctlr_init_done : IN STD_LOGIC;
- ctlr_rdy : IN STD_LOGIC;
+
+ ctlr_rddata : IN STD_LOGIC_VECTOR(c_tech_ddr_ctlr_data_w-1 DOWNTO 0);
+ ctlr_rdval : IN STD_LOGIC;
+ ctlr_waitrequest_n : IN STD_LOGIC;
+
+ ctlr_address : OUT STD_LOGIC_VECTOR(c_tech_ddr_ctlr_address_w-1 DOWNTO 0);
+ ctlr_wrdata : OUT STD_LOGIC_VECTOR(c_tech_ddr_ctlr_data_w-1 DOWNTO 0);
ctlr_burst : OUT STD_LOGIC;
- ctlr_burst_size : OUT STD_LOGIC_VECTOR(g_tech_ddr.maxburstsize_w-1 DOWNTO 0);
+ ctlr_burst_size : OUT STD_LOGIC_VECTOR(c_tech_ddr_ctlr_burstsize_w-1 DOWNTO 0);
ctlr_wr_req : OUT STD_LOGIC;
ctlr_rd_req : OUT STD_LOGIC;
@@ -46,11 +53,14 @@ ENTITY io_ddr_driver IS
dvr_wr_not_rd : IN STD_LOGIC;
dvr_done : OUT STD_LOGIC; -- Requested wr or rd sequence is done.
+ wr_data : IN STD_LOGIC_VECTOR(c_dp_stream_data_w-1 DOWNTO 0);
wr_val : IN STD_LOGIC;
- wr_rdy : OUT STD_LOGIC;
- rd_rdy : IN STD_LOGIC;
+ wr_ready : OUT STD_LOGIC;
+
+ rd_data : OUT STD_LOGIC_VECTOR(c_dp_stream_data_w-1 DOWNTO 0);
+ rd_val : OUT STD_LOGIC;
+ rd_ready : IN STD_LOGIC;
- cur_addr : OUT t_tech_ddr_addr;
start_addr : IN t_tech_ddr_addr;
end_addr : IN t_tech_ddr_addr;
@@ -83,7 +93,7 @@ ARCHITECTURE str OF io_ddr_driver IS
SIGNAL nxt_wr_burst_size : NATURAL;
SIGNAL nxt_rd_burst_size : NATURAL;
- SIGNAL i_ctlr_burst_size : STD_LOGIC_VECTOR(g_tech_ddr.maxburstsize_w-1 DOWNTO 0);
+ SIGNAL i_ctlr_burst_size : STD_LOGIC_VECTOR(c_tech_ddr_ctlr_burstsize_w-1 DOWNTO 0);
SIGNAL i_dvr_done : STD_LOGIC;
SIGNAL nxt_dvr_done : STD_LOGIC;
@@ -91,6 +101,7 @@ ARCHITECTURE str OF io_ddr_driver IS
SIGNAL start_address : STD_LOGIC_VECTOR(c_address_w-1 DOWNTO 0);
SIGNAL end_address : STD_LOGIC_VECTOR(c_address_w-1 DOWNTO 0);
+ SIGNAL cur_addr : t_tech_ddr_addr;
SIGNAL cur_address : STD_LOGIC_VECTOR(c_address_w-1 DOWNTO 0);
SIGNAL nxt_cur_address : STD_LOGIC_VECTOR(c_address_w-1 DOWNTO 0);
SIGNAL diff_address : STD_LOGIC_VECTOR(c_address_w-1 DOWNTO 0);
@@ -160,7 +171,13 @@ BEGIN
nxt_rd_burst_size <= v_burst_size;
END PROCESS;
- p_state : PROCESS(prev_state, state, i_dvr_done, ctlr_rdy, req_burst_cycles, dvr_wr_not_rd, wr_val, wr_fifo_usedw, wr_burst_size, rd_burst_size, dvr_en, ctlr_init_done, reg_addresses_rem, rd_rdy, i_ctlr_burst_size, start_address, cur_address)
+ ctlr_address <= func_tech_ddr_ctlr_address(cur_addr, g_tech_ddr, c_tech_ddr_ctlr_address_w);
+ ctlr_wrdata <= RESIZE_DDR_CTLR_DATA(wr_data);
+
+ rd_val <= ctlr_rdval;
+ rd_data <= RESIZE_DP_DATA(ctlr_rddata);
+
+ p_state : PROCESS(prev_state, state, i_dvr_done, ctlr_waitrequest_n, req_burst_cycles, dvr_wr_not_rd, wr_val, wr_fifo_usedw, wr_burst_size, rd_burst_size, dvr_en, ctlr_init_done, reg_addresses_rem, rd_ready, i_ctlr_burst_size, start_address, cur_address)
BEGIN
nxt_state <= state;
ctlr_wr_req <= '0';
@@ -168,7 +185,7 @@ BEGIN
ctlr_burst <= '0';
i_ctlr_burst_size <= (OTHERS => '0');
nxt_req_burst_cycles <= req_burst_cycles;
- wr_rdy <= '0';
+ wr_ready <= '0';
nxt_dvr_done <= i_dvr_done;
nxt_cur_address <= cur_address;
@@ -176,9 +193,9 @@ BEGIN
WHEN s_wr_burst => -- Performs the burst portion (word 2+)
ctlr_wr_req <= '1';
- IF ctlr_rdy = '1' THEN -- when local_ready goes low, that cycle does not count as a burst cycle
+ IF ctlr_waitrequest_n = '1' THEN -- when local_ready goes low, that cycle does not count as a burst cycle
nxt_req_burst_cycles <= INCR_UVEC(req_burst_cycles, -1);
- wr_rdy <= '1'; -- wr side uses latency of 0, so wr_rdy<='1' acknowledges a successful write request.
+ wr_ready <= '1'; -- wr side uses latency of 0, so wr_ready<='1' acknowledges a successful write request.
IF UNSIGNED(req_burst_cycles) = 1 THEN -- Then we're in the last cycle of this burst sequence
nxt_state <= s_wr_request; -- We can only initiate a burst through the wr_request state
END IF;
@@ -189,18 +206,18 @@ BEGIN
IF UNSIGNED(reg_addresses_rem) = 0 THEN -- end address reached
nxt_dvr_done <= '1';
nxt_state <= s_idle;
- ELSIF ctlr_rdy = '1' THEN
+ ELSIF ctlr_waitrequest_n = '1' THEN
IF wr_val = '1' THEN
-- Always perform 1st write here
ctlr_burst <= '1'; -- assert burst begin: strictly this is a burst of 1.
ctlr_wr_req <= '1';
- wr_rdy <= '1';
- i_ctlr_burst_size <= TO_UVEC(1, g_tech_ddr.maxburstsize_w); -- Set ctlr_burst_size to 1 by default
+ wr_ready <= '1';
+ i_ctlr_burst_size <= TO_DDR_CTLR_BURSTSIZE(1); -- Set ctlr_burst_size to 1 by default
IF wr_burst_size > 1 THEN
-- Perform any remaining writes in a burst
nxt_state <= s_wr_burst;
- nxt_req_burst_cycles <= TO_UVEC(wr_burst_size-1, g_tech_ddr.maxburstsize_w); -- Forward the required nof burst cycles (-1 as we've done the 1st in this state already) to burst state
- i_ctlr_burst_size <= TO_UVEC(wr_burst_size , g_tech_ddr.maxburstsize_w);
+ nxt_req_burst_cycles <= TO_DDR_CTLR_BURSTSIZE(wr_burst_size-1); -- Forward the required nof burst cycles (-1 as we've done the 1st in this state already) to burst state
+ i_ctlr_burst_size <= TO_DDR_CTLR_BURSTSIZE(wr_burst_size );
END IF; -- ELSE: there is only 1 word, so no need for remaining burst
nxt_cur_address <= INCR_UVEC(cur_address, UNSIGNED(i_ctlr_burst_size)*g_tech_ddr.rsl);
-- IF UNSIGNED(i_ctlr_burst_size) = 1 THEN -- Prevents FSM from going into this state again too soon (reg_addresses_rem invalid)
@@ -215,12 +232,12 @@ BEGIN
nxt_dvr_done <= '1';
nxt_state <= s_idle;
ELSE
- IF rd_rdy = '1' THEN -- Fifo uses its internal almost_full signal to toggle its snk_out.rdy
- IF ctlr_rdy = '1' THEN
+ IF rd_ready = '1' THEN -- Fifo uses its internal almost_full signal to toggle its snk_out.rdy
+ IF ctlr_waitrequest_n = '1' THEN
ctlr_rd_req <= '1';
ctlr_burst <= '1'; -- assert burst begin: strictly this is a burst of 1.
- i_ctlr_burst_size <= TO_UVEC(rd_burst_size, g_tech_ddr.maxburstsize_w);
- IF rd_burst_size = 0 THEN i_ctlr_burst_size <= TO_UVEC(1, g_tech_ddr.maxburstsize_w); END IF;
+ i_ctlr_burst_size <= TO_DDR_CTLR_BURSTSIZE(rd_burst_size);
+ IF rd_burst_size = 0 THEN i_ctlr_burst_size <= TO_DDR_CTLR_BURSTSIZE(1); END IF;
nxt_cur_address <= INCR_UVEC(cur_address, UNSIGNED(i_ctlr_burst_size)*g_tech_ddr.rsl);
-- IF UNSIGNED(i_ctlr_burst_size) = 1 THEN -- Prevents FSM from going into this state again too soon (reg_addresses_rem invalid)
-- nxt_state <= s_wait3;
@@ -267,6 +284,6 @@ BEGIN
start_address <= func_tech_ddr_dq_address(start_addr, g_tech_ddr, c_address_w);
cur_addr <= func_tech_ddr_dq_address(cur_address, g_tech_ddr);
-
+
END str;
--
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